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Fix lots of occurrences of 'the the', 'the there', 'the these', 'the then', 'the they.

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This commit is contained in:
Gregory Nutt 2017-05-11 13:35:56 -06:00
parent ba12817f9c
commit 0de294a586
342 changed files with 438 additions and 438 deletions
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8
ChangeLog
View file

@ -10770,8 +10770,8 @@
serial device servers. From Anton D. Kachalov (2015-07-29).
* drivers/net/ and include/nuttx/net: Add support for a Faraday
* FTMAC100 Ethernet MAC Driver. From Anton D. Kachalov (2015-07-29).
* 16550 UART Driver: Add a configuration option to indicate the the
THR empty bit is inverted. This is the the case for the moxART SoC.
* 16550 UART Driver: Add a configuration option to indicate the
THR empty bit is inverted. This is the case for the moxART SoC.
Based comments from Anton D. Kachalov (2015-07-29).
* STM32 F4: Add DMA support to the ADC driver for STM32 F4. From
Max Kriegler (2015-07-30).
@ -13129,7 +13129,7 @@
protect code.
So this change adds locking (via enter_critical section) to wdog
expiration logic for the the case if the SMP configuration
expiration logic for the case if the SMP configuration
(2016-11-18).
* SAM3/4: Add delay between setting and clearing the endpoint RESET bit
in sam_ep_resume(). We need to add a delay between setting and
@ -13248,7 +13248,7 @@
select to log only notes from certain CPUs (2016-11-28).
* Misoc LM3: Add Misoc Ethernet driver. Integrate network support into
configs/misoc/hello. Remove configs/misoc/include/generated directory.
I suppose the the intent now is that this is a symbolic link? DANGER!
I suppose the intent now is that this is a symbolic link? DANGER!
This means that you cannot compile this code with first generating
these files a providing a symbolic link to this location! From Ramtin
Amin (2016-11-28).

2
Documentation/NfsHowto.html
View file

@ -287,7 +287,7 @@ This is a test
<p>
Setting up the server will be done in two steps:
First, setting up the configuration file for NFS, and then starting the NFS services.
But first, you need to install the nfs server on Ubuntu with the these two commands:
But first, you need to install the nfs server on Ubuntu with these two commands:
</p>
<ul><pre>
# sudo apt-get install nfs-common</FONT>

2
Documentation/NuttXBinfmt.html
View file

@ -381,7 +381,7 @@ EXEPATH_HANDLE exepath_init(void);
<ul>
On success, <code>exepath_init()</code> return a non-<code>NULL</code>, opaque handle that may subsequently be used in calls to <code>exepath_next()</code> and <code>exepath_release()</code>.
On error, a <code>NULL</code> handle value will be returned.
The most likely cause of an error would be that the there is no value associated with the <code>PATH</code> variable.
The most likely cause of an error would be that there is no value associated with the <code>PATH</code> variable.
</ul>
<h3>2.3.9 <a name="exepath_next"><code>exepath_next()</code></a></h3>

8
Documentation/NuttxPortingGuide.html
View file

@ -2291,7 +2291,7 @@ config ARCH_SIM
In the default configuration where system time is provided by a periodic timer interrupt, the default system timer is configure the timer for 100Hz or <code>CONFIG_USEC_PER_TICK=10000</code>. If <code>CONFIG_SCHED_TICKLESS</code> is selected, then there are no system timer interrupt. In this case, <code>CONFIG_USEC_PER_TICK</code> does not control any timer rates. Rather, it only determines the resolution of time reported by <code>clock_systimer()</code> and the resolution of times that can be set for certain delays including watchdog timers and delayed work.
</p>
<p>
In this case there is still a trade-off: It is better to have the <code>CONFIG_USEC_PER_TICK</code> as low as possible for higher timing resolution. However, the the time is currently held in <code>unsigned int</code>. On some systems, this may be 16-bits in width but on most contemporary systems it will be 32-bits. In either case, smaller values of <code>CONFIG_USEC_PER_TICK</code> will reduce the range of values that delays that can be represented. So the trade-off is between range and resolution (you could also modify the code to use a 64-bit value if you really want both).
In this case there is still a trade-off: It is better to have the <code>CONFIG_USEC_PER_TICK</code> as low as possible for higher timing resolution. However, the time is currently held in <code>unsigned int</code>. On some systems, this may be 16-bits in width but on most contemporary systems it will be 32-bits. In either case, smaller values of <code>CONFIG_USEC_PER_TICK</code> will reduce the range of values that delays that can be represented. So the trade-off is between range and resolution (you could also modify the code to use a 64-bit value if you really want both).
</p>
<p>
The default, 100 microseconds, will provide for a range of delays up to 120 hours.
@ -2408,7 +2408,7 @@ int up_timer_gettime(FAR struct timespec *ts);
</ul>
<p><b>Assumptions</b>:</p>
<ul>
Called from the the normal tasking context. The implementation must provide whatever mutual exclusion is necessary for correct operation. This can include disabling interrupts in order to assure atomic register operations.
Called from the normal tasking context. The implementation must provide whatever mutual exclusion is necessary for correct operation. This can include disabling interrupts in order to assure atomic register operations.
</ul>
<h5><a name="upalarmcancel">4.3.4.4.3 <code>up_alarm_cancel()</code></a></h5>
@ -2761,7 +2761,7 @@ typedef uint32_t wdparm_t;
<h3><a name="wqclasses">4.4.1 Classes of Work Queues</a></h3>
<p><b>Classes of Work Queues</b>.
There are three different classes of work queues, each with different properties and intended usage. These class of work queues along with the the common work queue interface are described in the following paragraphs.
There are three different classes of work queues, each with different properties and intended usage. These class of work queues along with the common work queue interface are described in the following paragraphs.
</p>
<h4><a name="hpwork">4.4.1.1 High Priority Kernel Work queue</a></h4>
@ -2786,7 +2786,7 @@ typedef uint32_t wdparm_t;
The execution priority of the high-priority worker thread. Default: 224
</li>
<li><code>CONFIG_SCHED_HPWORKPERIOD</code>.
How often the worker thread re-checks for work in units of microseconds. This work period is really only necessary if the the high priority thread is performing periodic garbage collection. The worker thread will be awakened immediately with it is queued work to be done. If the high priority worker thread is performing garbage collection, then the default is 50*1000 (50 MS). Otherwise, if the lower priority worker thread is performing garbage collection, the default is 100*1000.
How often the worker thread re-checks for work in units of microseconds. This work period is really only necessary if the high priority thread is performing periodic garbage collection. The worker thread will be awakened immediately with it is queued work to be done. If the high priority worker thread is performing garbage collection, then the default is 50*1000 (50 MS). Otherwise, if the lower priority worker thread is performing garbage collection, the default is 100*1000.
<li><code>CONFIG_SCHED_HPWORKSTACKSIZE</code>.
The stack size allocated for the worker thread in bytes. Default: 2048.
</li>

4
Documentation/NuttxUserGuide.html
View file

@ -6433,7 +6433,7 @@ The cancellation cleanup handler will be popped from the cancellation cleanup st
<b>Input Parameters:</b>
<p>
<ul>
<li><code>routine</code>. The cleanup routine to be pushed on the the cleanup stack.</li>
<li><code>routine</code>. The cleanup routine to be pushed on the cleanup stack.</li>
<li><code>arg</code>. An argument that will accompany the callback.</li>
</ul>
<p>
@ -10115,7 +10115,7 @@ int shmctl(int shmid, int cmd, FAR struct shmid_ds *buf);
<ul>
<li>
<code>IPC_SET</code>.
Does not set the the <code>shm_perm.uid</code> or <code>shm_perm.gid</code>members of the <code>shmid_ds</code> data structure associated with <code>shmid</code> because user and group IDs are not yet supported by NuttX
Does not set the <code>shm_perm.uid</code> or <code>shm_perm.gid</code>members of the <code>shmid_ds</code> data structure associated with <code>shmid</code> because user and group IDs are not yet supported by NuttX
</li>
<li>
<code>IPC_SET</code>.

4
ReleaseNotes
View file

@ -11146,7 +11146,7 @@ Additional new features and extended functionality:
- SYSLOG character device channel will now expand LF to CR-LF.
Controllable with a configuration option.
- Add a SYSLOG character device that can be used to re-direct output
to the SYSLOG channel (Not be be confused the the SYSLGO output to a
to the SYSLOG channel (Not be be confused the SYSLGO output to a
character device).
- Debug features are now enabled separately from debug output.
(1) CONFIG_DEBUG is gone. It is replaced with CONFIG_DEBUG_FEATURES.
@ -12417,7 +12417,7 @@ Additional new features and extended functionality:
- Misoc LM32 Qemu: Integrate network support into configs/misoc/hello.
From Ramtin Amin.
- Misoc LM32 Qemu: Remove configs/misoc/include/generated directory. I
suppose the the intent now is that this is a symbolic link? DANGER!
suppose the intent now is that this is a symbolic link? DANGER!
This means that you cannot compile this code with first generating
these files a providing a symbolic link to this location! There is a
sample directory containing generated sources. This is really only

2
TODO
View file

@ -2065,7 +2065,7 @@ o Pascal Add-On (pcode/)
Priority: Medium
Title: PDBG
Description: Move the the pascal p-code debugger into the NuttX apps/ tree
Description: Move the pascal p-code debugger into the NuttX apps/ tree
where it can be used from the NSH command line.
Status: Open
Priority: Low

2
arch/Kconfig
View file

@ -767,7 +767,7 @@ config ARCH_HIPRI_INTERRUPT
there will most likely be a system failure.
If the interrupt stack is selected, on the other hand, then the
interrupt handler will always set the the MSP to the interrupt
interrupt handler will always set the MSP to the interrupt
stack. So when the high priority interrupt occurs, it will either
use the MSP of the last privileged thread to run or, in the case of
the nested interrupt, the interrupt stack if no privileged task has

2
arch/arm/include/stm32/ltdc.h
View file

@ -410,7 +410,7 @@ struct ltdc_layer_s
* On error - -EINVAL
*
* Procedure Information:
* If the srcxpos and srcypos unequal the the xpos and ypos of the coord
* If the srcxpos and srcypos unequal the xpos and ypos of the coord
* structure this acts like moving the visible area to another position on
* the screen during the next update operation.
*

2
arch/arm/src/a1x/a1x_lowputc.c
View file

@ -228,7 +228,7 @@ void a1x_lowsetup(void)
#warning Missing logic
/* Configure UART pins for the selected CONSOLE. If there are multiple
* pin options for a given UART, the the applicable option must be
* pin options for a given UART, the applicable option must be
* disambiguated in the board.h header file.
*/

2
arch/arm/src/armv7-a/arm_addrenv.c
View file

@ -149,7 +149,7 @@
* Name: up_addrenv_initdata
*
* Description:
* Initialize the region of memory at the the beginning of the .bss/.data
* Initialize the region of memory at the beginning of the .bss/.data
* region that is shared between the user process and the kernel.
*
****************************************************************************/

2
arch/arm/src/armv7-a/arm_gicv2.c
View file

@ -298,7 +298,7 @@ void arm_gic_initialize(void)
#endif
#if !defined(CONFIG_ARCH_HAVE_TRUSTZONE)
/* Enable the distributor by setting the the Enable bit in the enable
/* Enable the distributor by setting the Enable bit in the enable
* register (no security extensions).
*/

2
arch/arm/src/armv7-a/pgalloc.h
View file

@ -102,7 +102,7 @@ static inline void arm_tmprestore(uint32_t l1save)
*
* Description:
* If the page memory pool is statically mapped, then we do not have to
* go through the the temporary mapping. We simply have to perform a
* go through the temporary mapping. We simply have to perform a
* physical to virtual memory address mapping.
*
****************************************************************************/

4
arch/arm/src/armv7-m/gnu/up_exception.S
View file

@ -60,7 +60,7 @@
* stale MSP, there will most likely be a system failure.
*
* If the interrupt stack is selected, on the other hand, then the interrupt
* handler will always set the the MSP to the interrupt stack. So when the high
* handler will always set the MSP to the interrupt stack. So when the high
* priority interrupt occurs, it will either use the MSP of the last privileged
* thread to run or, in the case of the nested interrupt, the interrupt stack if
* no privileged task has run.
@ -70,7 +70,7 @@
# error Interrupt stack must be used with high priority interrupts in kernel mode
# endif
/* Use the the BASEPRI to control interrupts is required if nested, high
/* Use the BASEPRI to control interrupts is required if nested, high
* priority interrupts are supported.
*/

4
arch/arm/src/armv7-m/gnu/up_lazyexception.S
View file

@ -58,7 +58,7 @@
* interrupt occurs and uses this stale MSP, there will most likely be a system failure.
*
* If the interrupt stack is selected, on the other hand, then the interrupt handler will
* always set the the MSP to the interrupt stack. So when the high priority interrupt occurs,
* always set the MSP to the interrupt stack. So when the high priority interrupt occurs,
* it will either use the MSP of the last privileged thread to run or, in the case of the
* nested interrupt, the interrupt stack if no privileged task has run.
*/
@ -67,7 +67,7 @@
# error Interrupt stack must be used with high priority interrupts in kernel mode
# endif
/* Use the the BASEPRI to control interrupts is required if nested, high
/* Use the BASEPRI to control interrupts is required if nested, high
* priority interrupts are supported.
*/

2
arch/arm/src/efm32/efm32_dma.h
View file

@ -96,7 +96,7 @@
typedef FAR void *DMA_HANDLE;
/* Description:
* This is the type of the callback that is used to inform the user of the the
* This is the type of the callback that is used to inform the user of the
* completion of the DMA.
*
* Input Parameters:

10
arch/arm/src/efm32/efm32_usbhost.c
View file

@ -1955,8 +1955,8 @@ static ssize_t efm32_in_transfer(FAR struct efm32_usbhost_s *priv, int chidx,
/* Check for a special case: If (1) the transfer was NAKed and (2)
* no Tx FIFO empty or Rx FIFO not-empty event occurred, then we
* should be able to just flush the Rx and Tx FIFOs and try again.
* We can detect this latter case because the then the transfer
* buffer pointer and buffer size will be unaltered.
* We can detect this latter case because then the transfer buffer
* pointer and buffer size will be unaltered.
*/
elapsed = clock_systimer() - start;
@ -2221,8 +2221,8 @@ static ssize_t efm32_out_transfer(FAR struct efm32_usbhost_s *priv, int chidx,
/* Check for a special case: If (1) the transfer was NAKed and (2)
* no Tx FIFO empty or Rx FIFO not-empty event occurred, then we
* should be able to just flush the Rx and Tx FIFOs and try again.
* We can detect this latter case because the then the transfer
* buffer pointer and buffer size will be unaltered.
* We can detect this latter case because then the transfer buffer
* pointer and buffer size will be unaltered.
*/
elapsed = clock_systimer() - start;
@ -4613,7 +4613,7 @@ static ssize_t efm32_transfer(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep
* Description:
* Process a request to handle a transfer descriptor. This method will
* enqueue the transfer request and return immediately. When the transfer
* completes, the the callback will be invoked with the provided transfer.
* completes, the callback will be invoked with the provided transfer.
* This method is useful for receiving interrupt transfers which may come
* infrequently.
*

4
arch/arm/src/efm32/efm32_vectors.S
View file

@ -59,7 +59,7 @@
* stale MSP, there will most likely be a system failure.
*
* If the interrupt stack is selected, on the other hand, then the interrupt
* handler will always set the the MSP to the interrupt stack. So when the high
* handler will always set the MSP to the interrupt stack. So when the high
* priority interrupt occurs, it will either use the MSP of the last privileged
* thread to run or, in the case of the nested interrupt, the interrupt stack if
* no privileged task has run.
@ -69,7 +69,7 @@
# error Interrupt stack must be used with high priority interrupts in kernel mode
# endif
/* Use the the BASEPRI to control interrupts is required if nested, high
/* Use the BASEPRI to control interrupts is required if nested, high
* priority interrupts are supported.
*/

2
arch/arm/src/imx6/imx_memorymap.h
View file

@ -50,7 +50,7 @@
************************************************************************************/
/* The vectors are, by default, positioned at the beginning of the text
* section. Under what conditions do we have to remap the these vectors?
* section. Under what conditions do we have to remap these vectors?
*
* 1) If we are using high vectors (CONFIG_ARCH_LOWVECTORS=n). In this case,
* the vectors will lie at virtual address 0xffff:000 and we will need

2
arch/arm/src/kinetis/kinetis_lpserial.c
View file

@ -457,7 +457,7 @@ static void kinetis_shutdown(struct uart_dev_s *dev)
* Description:
* Configure the LPUART to operation in interrupt driven mode. This
* method is called when the serial port is opened. Normally, this is
* just after the the setup() method is called, however, the serial
* just after the setup() method is called, however, the serial
* console may operate in a non-interrupt driven mode during the boot phase.
*
* RX and TX interrupts are not enabled when by the attach method (unless

2
arch/arm/src/kinetis/kinetis_sdhc.c
View file

@ -95,7 +95,7 @@
/* Enable pull-up resistors
*
* Kinetis does not have pullups on all their development boards
* So allow the the board config to enable them.
* So allow the board config to enable them.
*/
#if defined(BOARD_SDHC_ENABLE_PULLUPS)

4
arch/arm/src/kinetis/kinetis_vectors.S
View file

@ -60,7 +60,7 @@
* stale MSP, there will most likely be a system failure.
*
* If the interrupt stack is selected, on the other hand, then the interrupt
* handler will always set the the MSP to the interrupt stack. So when the high
* handler will always set the MSP to the interrupt stack. So when the high
* priority interrupt occurs, it will either use the MSP of the last privileged
* thread to run or, in the case of the nested interrupt, the interrupt stack if
* no privileged task has run.
@ -70,7 +70,7 @@
# error Interrupt stack must be used with high priority interrupts in kernel mode
# endif
/* Use the the BASEPRI to control interrupts is required if nested, high
/* Use the BASEPRI to control interrupts is required if nested, high
* priority interrupts are supported.
*/

2
arch/arm/src/lpc11xx/lpc11_serial.c
View file

@ -498,7 +498,7 @@ static void up_shutdown(struct uart_dev_s *dev)
* Description:
* Configure the UART to operation in interrupt driven mode. This method
* is called when the serial port is opened. Normally, this is just after
* the the setup() method is called, however, the serial console may
* the setup() method is called, however, the serial console may
* operate in a non-interrupt driven mode during the boot phase.
*
* RX and TX interrupts are not enabled when by the attach method (unless

2
arch/arm/src/lpc17xx/lpc17_usbhost.c
View file

@ -3164,7 +3164,7 @@ static void lpc17_asynch_completion(struct lpc17_usbhost_s *priv,
* Description:
* Process a request to handle a transfer descriptor. This method will
* enqueue the transfer request and return immediately. When the transfer
* completes, the the callback will be invoked with the provided transfer.
* completes, the callback will be invoked with the provided transfer.
* This method is useful for receiving interrupt transfers which may come
* infrequently.
*

4
arch/arm/src/lpc17xx/lpc17_vectors.S
View file

@ -58,7 +58,7 @@
* interrupt occurs and uses this stale MSP, there will most likely be a system failure.
*
* If the interrupt stack is selected, on the other hand, then the interrupt handler will
* always set the the MSP to the interrupt stack. So when the high priority interrupt occurs,
* always set the MSP to the interrupt stack. So when the high priority interrupt occurs,
* it will either use the MSP of the last privileged thread to run or, in the case of the
* nested interrupt, the interrupt stack if no privileged task has run.
*/
@ -67,7 +67,7 @@
# error Interrupt stack must be used with high priority interrupts in kernel mode
# endif
/* Use the the BASEPRI to control interrupts is required if nested, high
/* Use the BASEPRI to control interrupts is required if nested, high
* priority interrupts are supported.
*/

2
arch/arm/src/lpc31xx/Kconfig
View file

@ -263,7 +263,7 @@ config LPC31_EHCI_SDIS
Selecting this option ensures that overruns/underruns of the latency
FIFO are eliminated for low bandwidth systems where the RX and TX
buffers are sufficient to contain the entire packet. Enabling stream
disable also has the effect of ensuring the the TX latency is filled
disable also has the effect of ensuring the TX latency is filled
to capacity before the packet is launched onto the USB.
Note: Time duration to pre-fill the FIFO becomes significant when stream disable is active.

6
arch/arm/src/lpc31xx/lpc31_ehci.c
View file

@ -3008,7 +3008,7 @@ static inline void lpc31_ioc_bottomhalf(void)
qh = (struct lpc31_qh_s *)lpc31_virtramaddr(lpc31_swap32(*bp) & QH_HLP_MASK);
/* If the asynchronous queue is empty, then the forward point in the
* asynchronous queue head will point back to the the queue head.
* asynchronous queue head will point back to the queue head.
*/
if (qh && qh != &g_asynchead)
@ -4362,7 +4362,7 @@ errout_with_sem:
* Description:
* Process a request to handle a transfer descriptor. This method will
* enqueue the transfer request and return immediately. When the transfer
* completes, the the callback will be invoked with the provided transfer.
* completes, the callback will be invoked with the provided transfer.
* This method is useful for receiving interrupt transfers which may come
* infrequently.
*
@ -4560,7 +4560,7 @@ static int lpc31_cancel(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep)
qh = (struct lpc31_qh_s *)lpc31_virtramaddr(lpc31_swap32(*bp) & QH_HLP_MASK);
/* If the asynchronous queue is empty, then the forward point in
* the asynchronous queue head will point back to the the queue
* the asynchronous queue head will point back to the queue
* head.
*/

6
arch/arm/src/lpc43xx/lpc43_ehci.c
View file

@ -2849,7 +2849,7 @@ static inline void lpc43_ioc_bottomhalf(void)
qh = (struct lpc43_qh_s *)lpc43_virtramaddr(lpc43_swap32(*bp) & QH_HLP_MASK);
/* If the asynchronous queue is empty, then the forward point in the
* asynchronous queue head will point back to the the queue head.
* asynchronous queue head will point back to the queue head.
*/
if (qh && qh != &g_asynchead)
@ -4193,7 +4193,7 @@ errout_with_sem:
* Description:
* Process a request to handle a transfer descriptor. This method will
* enqueue the transfer request and return immediately. When the transfer
* completes, the the callback will be invoked with the provided transfer.
* completes, the callback will be invoked with the provided transfer.
* This method is useful for receiving interrupt transfers which may come
* infrequently.
*
@ -4391,7 +4391,7 @@ static int lpc43_cancel(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep)
qh = (struct lpc43_qh_s *)lpc43_virtramaddr(lpc43_swap32(*bp) & QH_HLP_MASK);
/* If the asynchronous queue is empty, then the forward point in
* the asynchronous queue head will point back to the the queue
* the asynchronous queue head will point back to the queue
* head.
*/

2
arch/arm/src/lpc43xx/lpc43_ethernet.c
View file

@ -1483,7 +1483,7 @@ static int lpc43_recvframe(FAR struct lpc43_ethmac_s *priv)
{
priv->segments++;
/* Check if the there is only one segment in the frame */
/* Check if there is only one segment in the frame */
if (priv->segments == 1)
{

2
arch/arm/src/sam34/sam4cm_oneshot.c
View file

@ -405,7 +405,7 @@ int sam_oneshot_cancel(struct sam_oneshot_s *oneshot,
* the counter expires while we are doing this, the counter clock will be
* stopped, but the clock will not be disabled.
*
* The expected behavior is that the the counter register will freezes at
* The expected behavior is that the counter register will freezes at
* a value equal to the RC register when the timer expires. The counter
* should have values between 0 and RC in all other cased.
*

2
arch/arm/src/sam34/sam4cm_tc.c
View file

@ -1166,7 +1166,7 @@ uint32_t sam_tc_divfreq(TC_HANDLE handle)
DEBUGASSERT(chan);
/* Get the the TC_CMR register contents for this channel and extract the
/* Get the TC_CMR register contents for this channel and extract the
* TCCLKS index.
*/

2
arch/arm/src/sam34/sam4cm_tickless.c
View file

@ -313,7 +313,7 @@ void arm_timer_initialize(void)
* any failure.
*
* Assumptions:
* Called from the the normal tasking context. The implementation must
* Called from the normal tasking context. The implementation must
* provide whatever mutual exclusion is necessary for correct operation.
* This can include disabling interrupts in order to assure atomic register
* operations.

6
arch/arm/src/sam34/sam_emac.c
View file

@ -893,7 +893,7 @@ static int sam_txpoll(struct net_driver_s *dev)
sam_transmit(priv);
/* Check if the there are any free TX descriptors. We cannot perform
/* Check if there are any free TX descriptors. We cannot perform
* the TX poll if we do not have buffering for another packet.
*/
@ -941,7 +941,7 @@ static void sam_dopoll(struct sam_emac_s *priv)
{
struct net_driver_s *dev = &priv->dev;
/* Check if the there are any free TX descriptors. We cannot perform the
/* Check if there are any free TX descriptors. We cannot perform the
* TX poll if we do not have buffering for another packet.
*/
@ -1747,7 +1747,7 @@ static void sam_poll_work(FAR void *arg)
FAR struct sam_emac_s *priv = (FAR struct sam_emac_s *)arg;
struct net_driver_s *dev = &priv->dev;
/* Check if the there are any free TX descriptors. We cannot perform the
/* Check if there are any free TX descriptors. We cannot perform the
* TX poll if we do not have buffering for another packet.
*/

4
arch/arm/src/sam34/sam_vectors.S
View file

@ -57,7 +57,7 @@
* interrupt occurs and uses this stale MSP, there will most likely be a system failure.
*
* If the interrupt stack is selected, on the other hand, then the interrupt handler will
* always set the the MSP to the interrupt stack. So when the high priority interrupt occurs,
* always set the MSP to the interrupt stack. So when the high priority interrupt occurs,
* it will either use the MSP of the last privileged thread to run or, in the case of the
* nested interrupt, the interrupt stack if no privileged task has run.
*/
@ -66,7 +66,7 @@
# error Interrupt stack must be used with high priority interrupts in kernel mode
# endif
/* Use the the BASEPRI to control interrupts is required if nested, high
/* Use the BASEPRI to control interrupts is required if nested, high
* priority interrupts are supported.
*/

8
arch/arm/src/sama5/Kconfig
View file

@ -953,7 +953,7 @@ config SAMA5_LCDC_BACKCOLOR
config SAMA5_LCDC_FB_VBASE
hex "Framebuffer memory start address (virtual)"
---help---
If you are using the the LCDC, then you must provide the virtual
If you are using the LCDC, then you must provide the virtual
address of the start of the framebuffer. This address must be
aligned to a 1MB bounder (i.e., the last five "digits" of the
hexadecimal address must be zero).
@ -961,7 +961,7 @@ config SAMA5_LCDC_FB_VBASE
config SAMA5_LCDC_FB_PBASE
hex "Framebuffer memory start address (virtual)"
---help---
If you are using the the LCDC, then you must provide the physical
If you are using the LCDC, then you must provide the physical
address of the start of the framebuffer. This address must be
aligned to a 1MB bounder (i.e., the last five "digits" of the
hexadecimal address must be zero).
@ -4953,7 +4953,7 @@ config SAMA5_DDRCS_PGHEAP_OFFSET
If you are executing from DRAM, then you must have already reserved
this region with SAMA5_DDRCS_RESERVE, setting SAMA5_DDRCS_HEAP_END
so that this page cache region defined by SAMA5_DDRCS_PGHEAP_OFFSET
and SAMA5_DDRCS_PGHEAP_SIZE does not overlap the the region of DRAM
and SAMA5_DDRCS_PGHEAP_SIZE does not overlap the region of DRAM
that is added to the heap. If you are not executing from DRAM, then
you must have excluding this page cache region from the heap ether
by (1) not selecting SAMA5_DDRCS_HEAP, or (2) selecting
@ -4971,7 +4971,7 @@ config SAMA5_DDRCS_PGHEAP_SIZE
If you are executing from DRAM, then you must have already reserved
this region with SAMA5_DDRCS_RESERVE, setting SAMA5_DDRCS_HEAP_END
so that this page cache region defined by SAMA5_DDRCS_PGHEAP_OFFSET
and SAMA5_DDRCS_PGHEAP_SIZE does not overlap the the region of DRAM
and SAMA5_DDRCS_PGHEAP_SIZE does not overlap the region of DRAM
that is added to the heap. If you are not executing from DRAM, then
you must have excluding this page cache region from the heap ether
by (1) not selecting SAMA5_DDRCS_HEAP, or (2) selecting

2
arch/arm/src/sama5/chip/sam_emaca.h
View file

@ -1,6 +1,6 @@
/************************************************************************************
* arch/arm/src/sama5/chip/sam_emaca.h
* This is the form of the EMAC interface used the the SAMA5D3
* This is the form of the EMAC interface used the SAMA5D3
*
* Copyright (C) 2013-2014 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>

2
arch/arm/src/sama5/chip/sam_emacb.h
View file

@ -1,6 +1,6 @@
/************************************************************************************
* arch/arm/src/sama5/chip/sam_emacb.h
* This is the form of the EMAC interface used the the SAMA5D4 (and also the SAM43).
* This is the form of the EMAC interface used the SAMA5D4 (and also the SAM43).
* This is referred as GMAC in the documentation even though it does not support
* Gibabit Ethernet.
*

6
arch/arm/src/sama5/sam_adc.c
View file

@ -736,7 +736,7 @@ static void sam_adc_dmacallback(DMA_HANDLE handle, void *arg, int result)
/* Check of the bottom half is keeping up with us.
*
* ready == false: Would mean that the worker thready has not ran since
* the the last DMA callback.
* the last DMA callback.
* enabled == false: Means that the upper half has asked us nicely to stop
* transferring DMA data.
*/
@ -1294,7 +1294,7 @@ static int sam_adc_settimer(struct sam_adc_s *priv, uint32_t frequency,
return ret;
}
/* Set the timer/counter waveform mode the the clock input slected by
/* Set the timer/counter waveform mode the clock input slected by
* sam_tc_divisor()
*/
@ -1448,7 +1448,7 @@ static int sam_adc_trigger(struct sam_adc_s *priv)
/* Configure to trigger using Timer/counter 0, channel 1, 2, or 3.
* NOTE: This trigger option depends on having properly configuer
* timer/counter 0 to provide this output. That is done independently
* the the timer/counter driver.
* the timer/counter driver.
*/
/* Set TIOAn trigger where n=0, 1, or 2 */

2
arch/arm/src/sama5/sam_allocateheap.c
View file

@ -147,7 +147,7 @@
# define SAMA5_PRIMARY_HEAP_END CONFIG_SAMA5_DDRCS_HEAP_END
#else
/* Otherwise, add the RAM all the way to the the end of the primary memory
/* Otherwise, add the RAM all the way to the end of the primary memory
* region to the heap.
*/

2
arch/arm/src/sama5/sam_dbgu.c
View file

@ -580,7 +580,7 @@ void sam_dbgu_devinitialize(void)
putreg32(DBGU_INT_ALLINTS, SAM_DBGU_IDR);
#ifdef CONFIG_SAMA5_DBGU_CONSOLE
/* Configuration the DBGU as the the console */
/* Configuration the DBGU as the console */
g_dbgu_port.isconsole = true;
dbgu_configure();

6
arch/arm/src/sama5/sam_ehci.c
View file

@ -2819,7 +2819,7 @@ static inline void sam_ioc_bottomhalf(void)
qh = (struct sam_qh_s *)sam_virtramaddr(sam_swap32(*bp) & QH_HLP_MASK);
/* If the asynchronous queue is empty, then the forward point in the
* asynchronous queue head will point back to the the queue head.
* asynchronous queue head will point back to the queue head.
*/
if (qh && qh != &g_asynchead)
@ -4183,7 +4183,7 @@ errout_with_sem:
* Description:
* Process a request to handle a transfer descriptor. This method will
* enqueue the transfer request and return immediately. When the transfer
* completes, the the callback will be invoked with the provided transfer.
* completes, the callback will be invoked with the provided transfer.
* This method is useful for receiving interrupt transfers which may come
* infrequently.
*
@ -4373,7 +4373,7 @@ static int sam_cancel(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep)
qh = (struct sam_qh_s *)sam_virtramaddr(sam_swap32(*bp) & QH_HLP_MASK);
/* If the asynchronous queue is empty, then the forward point in
* the asynchronous queue head will point back to the the queue
* the asynchronous queue head will point back to the queue
* head.
*/

6
arch/arm/src/sama5/sam_emaca.c
View file

@ -902,7 +902,7 @@ static int sam_txpoll(struct net_driver_s *dev)
sam_transmit(priv);
/* Check if the there are any free TX descriptors. We cannot perform
/* Check if there are any free TX descriptors. We cannot perform
* the TX poll if we do not have buffering for another packet.
*/
@ -949,7 +949,7 @@ static void sam_dopoll(struct sam_emac_s *priv)
{
struct net_driver_s *dev = &priv->dev;
/* Check if the there are any free TX descriptors. We cannot perform the
/* Check if there are any free TX descriptors. We cannot perform the
* TX poll if we do not have buffering for another packet.
*/
@ -1783,7 +1783,7 @@ static void sam_poll_work(FAR void *arg)
FAR struct sam_emac_s *priv = (FAR struct sam_emac_s *)arg;
struct net_driver_s *dev = &priv->dev;
/* Check if the there are any free TX descriptors. We cannot perform the
/* Check if there are any free TX descriptors. We cannot perform the
* TX poll if we do not have buffering for another packet.
*/

6
arch/arm/src/sama5/sam_emacb.c
View file

@ -1237,7 +1237,7 @@ static int sam_txpoll(struct net_driver_s *dev)
sam_transmit(priv);
/* Check if the there are any free TX descriptors. We cannot perform
/* Check if there are any free TX descriptors. We cannot perform
* the TX poll if we do not have buffering for another packet.
*/
@ -1285,7 +1285,7 @@ static void sam_dopoll(struct sam_emac_s *priv)
{
struct net_driver_s *dev = &priv->dev;
/* Check if the there are any free TX descriptors. We cannot perform the
/* Check if there are any free TX descriptors. We cannot perform the
* TX poll if we do not have buffering for another packet.
*/
@ -2144,7 +2144,7 @@ static void sam_poll_work(FAR void *arg)
FAR struct sam_emac_s *priv = (FAR struct sam_emac_s *)arg;
struct net_driver_s *dev = &priv->dev;
/* Check if the there are any free TX descriptors. We cannot perform the
/* Check if there are any free TX descriptors. We cannot perform the
* TX poll if we do not have buffering for another packet.
*/

6
arch/arm/src/sama5/sam_gmac.c
View file

@ -834,7 +834,7 @@ static int sam_txpoll(struct net_driver_s *dev)
sam_transmit(priv);
/* Check if the there are any free TX descriptors. We cannot perform
/* Check if there are any free TX descriptors. We cannot perform
* the TX poll if we do not have buffering for another packet.
*/
@ -881,7 +881,7 @@ static void sam_dopoll(struct sam_gmac_s *priv)
{
struct net_driver_s *dev = &priv->dev;
/* Check if the there are any free TX descriptors. We cannot perform the
/* Check if there are any free TX descriptors. We cannot perform the
* TX poll if we do not have buffering for another packet.
*/
@ -1735,7 +1735,7 @@ static void sam_poll_work(FAR void *arg)
FAR struct sam_gmac_s *priv = (FAR struct sam_gmac_s *)arg;
struct net_driver_s *dev = &priv->dev;
/* Check if the there are any free TX descriptors. We cannot perform the
/* Check if there are any free TX descriptors. We cannot perform the
* TX poll if we do not have buffering for another packet.
*/

2
arch/arm/src/sama5/sam_hsmci.c
View file

@ -3102,7 +3102,7 @@ static void sam_callback(void *arg)
priv->cbevents = 0;
/* This function is called either from (1) the context of the calling
* thread or from the the context of (2) card detection logic. The
* thread or from the context of (2) card detection logic. The
* caller may or may not have interrupts disabled (we have them
* disabled here!).
*

2
arch/arm/src/sama5/sam_memorymap.h
View file

@ -50,7 +50,7 @@
************************************************************************************/
/* The vectors are, by default, positioned at the beginning of the text
* section. Under what conditions do we have to remap the these vectors?
* section. Under what conditions do we have to remap these vectors?
*
* 1) If we are using high vectors (CONFIG_ARCH_LOWVECTORS=n). In this case,
* the vectors will lie at virtual address 0xffff:000 and we will need

2
arch/arm/src/sama5/sam_nand.c
View file

@ -1245,7 +1245,7 @@ static int nand_wait_dma(struct sam_nandcs_s *priv)
*
* Description:
* Called when one NAND DMA sequence completes. This function just wakes
* the the waiting NAND driver logic.
* the waiting NAND driver logic.
*
****************************************************************************/

2
arch/arm/src/sama5/sam_ohci.c
View file

@ -3531,7 +3531,7 @@ static void sam_asynch_completion(struct sam_eplist_s *eplist)
* Description:
* Process a request to handle a transfer descriptor. This method will
* enqueue the transfer request and return immediately. When the transfer
* completes, the the callback will be invoked with the provided transfer.
* completes, the callback will be invoked with the provided transfer.
* This method is useful for receiving interrupt transfers which may come
* infrequently.
*

2
arch/arm/src/sama5/sam_oneshot.c
View file

@ -417,7 +417,7 @@ int sam_oneshot_cancel(struct sam_oneshot_s *oneshot,
* the counter expires while we are doing this, the counter clock will be
* stopped, but the clock will not be disabled.
*
* The expected behavior is that the the counter register will freezes at
* The expected behavior is that the counter register will freezes at
* a value equal to the RC register when the timer expires. The counter
* should have values between 0 and RC in all other cased.
*

2
arch/arm/src/sama5/sam_tc.c
View file

@ -1427,7 +1427,7 @@ uint32_t sam_tc_divfreq(TC_HANDLE handle)
DEBUGASSERT(chan);
/* Get the the TC_CMR register contents for this channel and extract the
/* Get the TC_CMR register contents for this channel and extract the
* TCCLKS index.
*/

2
arch/arm/src/sama5/sam_tickless.c
View file

@ -325,7 +325,7 @@ void arm_timer_initialize(void)
* any failure.
*
* Assumptions:
* Called from the the normal tasking context. The implementation must
* Called from the normal tasking context. The implementation must
* provide whatever mutual exclusion is necessary for correct operation.
* This can include disabling interrupts in order to assure atomic register
* operations.

4
arch/arm/src/sama5/sam_udphs.c
View file

@ -1298,7 +1298,7 @@ static void sam_req_wrsetup(struct sam_usbdev_s *priv,
* When this function starts a transfer it will update the request
* 'inflight' field to indicate the size of the transfer.
*
* When the transfer completes, the the 'inflight' field must hold the
* When the transfer completes, the 'inflight' field must hold the
* number of bytes that have completed the transfer. This function will
* update 'xfrd' with the new size of the transfer.
*
@ -4554,7 +4554,7 @@ int usbdev_register(struct usbdevclass_driver_s *driver)
up_enable_irq(SAM_IRQ_UDPHS);
/* Enable pull-up to connect the device. The host should enumerate us
* some time after this. The next thing we expect the the ENDRESET
* some time after this. The next thing we expect the ENDRESET
* interrupt.
*/

6
arch/arm/src/sama5/sama5d2x_pio.c
View file

@ -571,13 +571,13 @@ bool sam_pioread(pio_pinset_t pinset)
pin = sam_piopin(pinset);
/* For output PIOs, the ODSR register provides the output value to
* drive the pin. The PDSR register, on the the other hand, provides
* drive the pin. The PDSR register, on the other hand, provides
* the current sensed value on a pin, whether the pin is configured
* as an input, an output or as a peripheral.
*
* There is small delay between the setting in ODSR and PDSR but
* otherwise the they should be the same unless something external
* is driving the pin.
* otherwise they should be the same unless something external is
* driving the pin.
*
* Let's assume that PDSR is what the caller wants.
*/

8
arch/arm/src/sama5/sama5d3x4x_pio.c
View file

@ -262,7 +262,7 @@ static void sam_pio_enableclk(pio_pinset_t cfgset)
* 1) No pins are configured as PIO inputs (peripheral inputs don't need
* clocking, and
* 2) Glitch and debounce filtering are not enabled. Currently, this can
* only happen if the the pin is a PIO input, but we may need to
* only happen if the pin is a PIO input, but we may need to
* implement glitch filtering on peripheral inputs as well in the
* future???
* 3) The port is not configured for PIO interrupts. At present, the logic
@ -816,13 +816,13 @@ bool sam_pioread(pio_pinset_t pinset)
pin = sam_piopin(pinset);
/* For output PIOs, the ODSR register provides the output value to
* drive the pin. The PDSR register, on the the other hand, provides
* drive the pin. The PDSR register, on the other hand, provides
* the current sensed value on a pin, whether the pin is configured
* as an input, an output or as a peripheral.
*
* There is small delay between the setting in ODSR and PDSR but
* otherwise the they should be the same unless something external
* is driving the pin.
* otherwise they should be the same unless something external is
* driving the pin.
*
* Let's assume that PDSR is what the caller wants.
*/

2
arch/arm/src/samdl/sam_timerisr.c
View file

@ -61,7 +61,7 @@
* system clock ticks per second. That value is a user configurable setting
* that defaults to 100 (100 ticks per second = 10 MS interval).
*
* Then, for example, if the CPU clock is the the SysTick and
* Then, for example, if the CPU clock is the SysTick and
* BOARD_CPU_FREQUENCY is 48MHz and CLK_TCK is 100, then the reload value
* would be:
*

2
arch/arm/src/samdl/saml_clockconfig.c
View file

@ -1131,7 +1131,7 @@ static inline void sam_fdpll96m_config(void)
static inline void sam_fdpll96m_refclk(void)
{
#ifdef BOARD_FDPLL96M_LOCKTIME_ENABLE
/* Enable the GCLK that is configured to the the FDPLL lock timer */
/* Enable the GCLK that is configured to the FDPLL lock timer */
sam_gclk_chan_enable(GCLK_CHAN_DPLL_32K, BOARD_FDPLL96M_LOCKTIME_CLKGEN);
#endif

2
arch/arm/src/samv7/chip/sam_emac.h
View file

@ -1,6 +1,6 @@
/************************************************************************************
* arch/arm/src/samv7/chip/sam_emac.h
* This is the form of the EMAC interface used the the SAMV7.
* This is the form of the EMAC interface used the SAMV7.
* This is referred as GMAC in the documentation even though it does not support
* Gibabit Ethernet.
*

2
arch/arm/src/samv7/sam_dac.c
View file

@ -381,7 +381,7 @@ static int dac_timer_init(struct sam_dac_s *priv, uint32_t freq_required,
DEBUGASSERT(priv && (freq_required > 0) && (channel >= 0 && channel <= 2));
/* Set the timer/counter waveform mode the the clock input. Use smallest
/* Set the timer/counter waveform mode the clock input. Use smallest
* MCK divisor of 8 to have highest clock resolution thus smallest frequency
* error. With 32 bit counter the lowest possible frequency of 1 Hz is easily
* supported.

6
arch/arm/src/samv7/sam_emac.c
View file

@ -1551,7 +1551,7 @@ static int sam_txpoll(struct net_driver_s *dev)
sam_transmit(priv, EMAC_QUEUE_0);
/* Check if the there are any free TX descriptors. We cannot perform
/* Check if there are any free TX descriptors. We cannot perform
* the TX poll if we do not have buffering for another packet.
*/
@ -1601,7 +1601,7 @@ static void sam_dopoll(struct sam_emac_s *priv, int qid)
{
struct net_driver_s *dev = &priv->dev;
/* Check if the there are any free TX descriptors. We cannot perform the
/* Check if there are any free TX descriptors. We cannot perform the
* TX poll if we do not have buffering for another packet.
*/
@ -2615,7 +2615,7 @@ static void sam_poll_work(FAR void *arg)
FAR struct sam_emac_s *priv = (FAR struct sam_emac_s *)arg;
struct net_driver_s *dev = &priv->dev;
/* Check if the there are any free TX descriptors. We cannot perform the
/* Check if there are any free TX descriptors. We cannot perform the
* TX poll if we do not have buffering for another packet.
*/

2
arch/arm/src/samv7/sam_hsmci.c
View file

@ -3176,7 +3176,7 @@ static void sam_callback(void *arg)
priv->cbevents = 0;
/* This function is called either from (1) the context of the calling
* thread or from the the context of (2) card detection logic. The
* thread or from the context of (2) card detection logic. The
* caller may or may not have interrupts disabled (we have them
* disabled here!).
*

2
arch/arm/src/samv7/sam_oneshot.c
View file

@ -419,7 +419,7 @@ int sam_oneshot_cancel(struct sam_oneshot_s *oneshot,
* the counter expires while we are doing this, the counter clock will be
* stopped, but the clock will not be disabled.
*
* The expected behavior is that the the counter register will freezes at
* The expected behavior is that the counter register will freezes at
* a value equal to the RC register when the timer expires. The counter
* should have values between 0 and RC in all other cased.
*

2
arch/arm/src/samv7/sam_tc.c
View file

@ -1615,7 +1615,7 @@ uint32_t sam_tc_divfreq(TC_HANDLE handle)
DEBUGASSERT(chan);
/* Get the the TC_CMR register contents for this channel and extract the
/* Get the TC_CMR register contents for this channel and extract the
* TCCLKS index.
*/

2
arch/arm/src/samv7/sam_tickless.c
View file

@ -311,7 +311,7 @@ void arm_timer_initialize(void)
* any failure.
*
* Assumptions:
* Called from the the normal tasking context. The implementation must
* Called from the normal tasking context. The implementation must
* provide whatever mutual exclusion is necessary for correct operation.
* This can include disabling interrupts in order to assure atomic register
* operations.

2
arch/arm/src/samv7/sam_usbdevhs.c
View file

@ -1359,7 +1359,7 @@ static void sam_req_wrsetup(struct sam_usbdev_s *priv,
* When this function starts a transfer it will update the request
* 'inflight' field to indicate the size of the transfer.
*
* When the transfer completes, the the 'inflight' field must hold the
* When the transfer completes, the 'inflight' field must hold the
* number of bytes that have completed the transfer. This function will
* update 'xfrd' with the new size of the transfer.
*

2
arch/arm/src/stm32/Kconfig
View file

@ -6855,7 +6855,7 @@ config STM32_LTDC_DITHER_BLUE
config STM32_LTDC_FB_BASE
hex "Framebuffer memory start address"
---help---
If you are using the the LTDC, then you must provide the address
If you are using the LTDC, then you must provide the address
of the start of the framebuffer. This address will typically
be in the SRAM or SDRAM memory region of the FSMC.

4
arch/arm/src/stm32/gnu/stm32_vectors.S
View file

@ -63,7 +63,7 @@
* stale MSP, there will most likely be a system failure.
*
* If the interrupt stack is selected, on the other hand, then the interrupt
* handler will always set the the MSP to the interrupt stack. So when the high
* handler will always set the MSP to the interrupt stack. So when the high
* priority interrupt occurs, it will either use the MSP of the last privileged
* thread to run or, in the case of the nested interrupt, the interrupt stack if
* no privileged task has run.
@ -73,7 +73,7 @@
# error Interrupt stack must be used with high priority interrupts in kernel mode
# endif
/* Use the the BASEPRI to control interrupts is required if nested, high
/* Use the BASEPRI to control interrupts is required if nested, high
* priority interrupts are supported.
*/

4
arch/arm/src/stm32/iar/stm32_vectors.S
View file

@ -63,7 +63,7 @@
* stale MSP, there will most likely be a system failure.
*
* If the interrupt stack is selected, on the other hand, then the interrupt
* handler will always set the the MSP to the interrupt stack. So when the high
* handler will always set the MSP to the interrupt stack. So when the high
* priority interrupt occurs, it will either use the MSP of the last privileged
* thread to run or, in the case of the nested interrupt, the interrupt stack if
* no privileged task has run.
@ -73,7 +73,7 @@
# error Interrupt stack must be used with high priority interrupts in kernel mode
# endif
/* Use the the BASEPRI to control interrupts is required if nested, high
/* Use the BASEPRI to control interrupts is required if nested, high
* priority interrupts are supported.
*/

2
arch/arm/src/stm32/stm32_bbsram.c
View file

@ -612,7 +612,7 @@ static int stm32_bbsram_ioctl(FAR struct file *filep, int cmd,
* This function will remove the remove the file from the file system
* it will zero the contents and time stamp. It will leave the fileno
* and pointer to the BBSRAM intact.
* It should be called called on the the file used for the crash dump
* It should be called called on the file used for the crash dump
* to remove it from visibility in the file system after it is created or
* read thus arming it.
*

2
arch/arm/src/stm32/stm32_dma.h
View file

@ -94,7 +94,7 @@
typedef FAR void *DMA_HANDLE;
/* Description:
* This is the type of the callback that is used to inform the user of the the
* This is the type of the callback that is used to inform the user of the
* completion of the DMA.
*
* Input Parameters:

2
arch/arm/src/stm32/stm32_eth.c
View file

@ -1551,7 +1551,7 @@ static int stm32_recvframe(FAR struct stm32_ethmac_s *priv)
{
priv->segments++;
/* Check if the there is only one segment in the frame */
/* Check if there is only one segment in the frame */
if (priv->segments == 1)
{

2
arch/arm/src/stm32/stm32_ltdc.c
View file

@ -3014,7 +3014,7 @@ static int stm32_getblendmode(FAR struct ltdc_layer_s *layer, uint32_t *mode)
* On error - -EINVAL
*
* Procedure Information:
* If the srcxpos and srcypos unequal the the xpos and ypos of the area
* If the srcxpos and srcypos unequal the xpos and ypos of the area
* structure this acts like moving the visible area to another position on
* the screen during the next update operation.
*

2
arch/arm/src/stm32/stm32_oneshot.c
View file

@ -393,7 +393,7 @@ int stm32_oneshot_cancel(struct stm32_oneshot_s *oneshot,
* If the counter expires while we are doing this, the counter clock will
* be stopped, but the clock will not be disabled.
*
* The expected behavior is that the the counter register will freezes at
* The expected behavior is that the counter register will freezes at
* a value equal to the RC register when the timer expires. The counter
* should have values between 0 and RC in all other cased.
*

2
arch/arm/src/stm32/stm32_otgfsdev.c
View file

@ -5238,7 +5238,7 @@ static void stm32_hwinitialize(FAR struct stm32_usbdev_s *priv)
# endif
#else
/* In the case of the the all others the meaning of the bit is No VBUS
/* In the case of the all others the meaning of the bit is No VBUS
* Sense when Set
*/

8
arch/arm/src/stm32/stm32_otgfshost.c
View file

@ -1978,7 +1978,7 @@ static ssize_t stm32_in_transfer(FAR struct stm32_usbhost_s *priv, int chidx,
{
/* Successfully received another chunk of data... add that to the
* runing total. Then continue reading until we read 'buflen'
* bytes of data or until the the devices NAKs (implying a short
* bytes of data or until the devices NAKs (implying a short
* packet).
*/
@ -2235,8 +2235,8 @@ static ssize_t stm32_out_transfer(FAR struct stm32_usbhost_s *priv, int chidx,
/* Check for a special case: If (1) the transfer was NAKed and (2)
* no Tx FIFO empty or Rx FIFO not-empty event occurred, then we
* should be able to just flush the Rx and Tx FIFOs and try again.
* We can detect this latter case because the then the transfer
* buffer pointer and buffer size will be unaltered.
* We can detect this latter case because then the transfer buffer
* pointer and buffer size will be unaltered.
*/
elapsed = clock_systimer() - start;
@ -4630,7 +4630,7 @@ static ssize_t stm32_transfer(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep
* Description:
* Process a request to handle a transfer descriptor. This method will
* enqueue the transfer request and return immediately. When the transfer
* completes, the the callback will be invoked with the provided transfer.
* completes, the callback will be invoked with the provided transfer.
* This method is useful for receiving interrupt transfers which may come
* infrequently.
*

8
arch/arm/src/stm32/stm32_otghshost.c
View file

@ -1983,7 +1983,7 @@ static ssize_t stm32_in_transfer(FAR struct stm32_usbhost_s *priv, int chidx,
{
/* Successfully received another chunk of data... add that to the
* runing total. Then continue reading until we read 'buflen'
* bytes of data or until the the devices NAKs (implying a short
* bytes of data or until the devices NAKs (implying a short
* packet).
*/
@ -2240,8 +2240,8 @@ static ssize_t stm32_out_transfer(FAR struct stm32_usbhost_s *priv, int chidx,
/* Check for a special case: If (1) the transfer was NAKed and (2)
* no Tx FIFO empty or Rx FIFO not-empty event occurred, then we
* should be able to just flush the Rx and Tx FIFOs and try again.
* We can detect this latter case because the then the transfer
* buffer pointer and buffer size will be unaltered.
* We can detect this latter case because then the transfer buffer
* pointer and buffer size will be unaltered.
*/
elapsed = clock_systimer() - start;
@ -4635,7 +4635,7 @@ static ssize_t stm32_transfer(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep
* Description:
* Process a request to handle a transfer descriptor. This method will
* enqueue the transfer request and return immediately. When the transfer
* completes, the the callback will be invoked with the provided transfer.
* completes, the callback will be invoked with the provided transfer.
* This method is useful for receiving interrupt transfers which may come
* infrequently.
*

2
arch/arm/src/stm32/stm32_tickless.c
View file

@ -590,7 +590,7 @@ void arm_timer_initialize(void)
* any failure.
*
* Assumptions:
* Called from the the normal tasking context. The implementation must
* Called from the normal tasking context. The implementation must
* provide whatever mutual exclusion is necessary for correct operation.
* This can include disabling interrupts in order to assure atomic register
* operations.

2
arch/arm/src/stm32/stm32f40xxx_rtcc.c
View file

@ -1354,7 +1354,7 @@ int stm32_rtc_setalarm(FAR struct alm_setalarm_s *alminfo)
ASSERT(alminfo != NULL);
DEBUGASSERT(RTC_ALARM_LAST > alminfo->as_id);
/* Make sure the the alarm interrupt is enabled at the NVIC */
/* Make sure the alarm interrupt is enabled at the NVIC */
rtc_enable_alarm();

2
arch/arm/src/stm32f0/stm32f0_hsi48.c
View file

@ -137,7 +137,7 @@ void stm32f0_enable_hsi48(enum syncsrc_e syncsrc)
putreg32(regval, STM32F0_CRS_CFGR);
/* Set the AUTOTRIMEN bit the the CRS_CR register to enables the automatic
/* Set the AUTOTRIMEN bit the CRS_CR register to enables the automatic
* hardware adjustment of TRIM bits according to the measured frequency
* error between the selected SYNC event.
*/

2
arch/arm/src/stm32f7/stm32_bbsram.c
View file

@ -613,7 +613,7 @@ static int stm32_bbsram_ioctl(FAR struct file *filep, int cmd,
* This function will remove the remove the file from the file system
* it will zero the contents and time stamp. It will leave the fileno
* and pointer to the BBSRAM intact.
* It should be called called on the the file used for the crash dump
* It should be called called on the file used for the crash dump
* to remove it from visibility in the file system after it is created or
* read thus arming it.
*

2
arch/arm/src/stm32f7/stm32_dma.h
View file

@ -69,7 +69,7 @@
typedef FAR void *DMA_HANDLE;
/* Description:
* This is the type of the callback that is used to inform the user of the the
* This is the type of the callback that is used to inform the user of the
* completion of the DMA. NOTE: The DMA module does *NOT* perform any cache
* operations. It is the responsibility of the DMA client to invalidate DMA
* buffers after completion of the DMA RX operations.

2
arch/arm/src/stm32f7/stm32_ethernet.c
View file

@ -1636,7 +1636,7 @@ static int stm32_recvframe(struct stm32_ethmac_s *priv)
{
priv->segments++;
/* Check if the there is only one segment in the frame */
/* Check if there is only one segment in the frame */
if (priv->segments == 1)
{

8
arch/arm/src/stm32f7/stm32_otghost.c
View file

@ -1977,7 +1977,7 @@ static ssize_t stm32_in_transfer(FAR struct stm32_usbhost_s *priv, int chidx,
{
/* Successfully received another chunk of data... add that to the
* runing total. Then continue reading until we read 'buflen'
* bytes of data or until the the devices NAKs (implying a short
* bytes of data or until the devices NAKs (implying a short
* packet).
*/
@ -2234,8 +2234,8 @@ static ssize_t stm32_out_transfer(FAR struct stm32_usbhost_s *priv, int chidx,
/* Check for a special case: If (1) the transfer was NAKed and (2)
* no Tx FIFO empty or Rx FIFO not-empty event occurred, then we
* should be able to just flush the Rx and Tx FIFOs and try again.
* We can detect this latter case because the then the transfer
* buffer pointer and buffer size will be unaltered.
* We can detect this latter case because then the transfer buffer
* pointer and buffer size will be unaltered.
*/
elapsed = clock_systimer() - start;
@ -4628,7 +4628,7 @@ static ssize_t stm32_transfer(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep
* Description:
* Process a request to handle a transfer descriptor. This method will
* enqueue the transfer request and return immediately. When the transfer
* completes, the the callback will be invoked with the provided transfer.
* completes, the callback will be invoked with the provided transfer.
* This method is useful for receiving interrupt transfers which may come
* infrequently.
*

2
arch/arm/src/stm32l4/stm32l4_dma.h
View file

@ -79,7 +79,7 @@
typedef FAR void *DMA_HANDLE;
/* Description:
* This is the type of the callback that is used to inform the user of the the
* This is the type of the callback that is used to inform the user of the
* completion of the DMA.
*
* Input Parameters:

2
arch/arm/src/stm32l4/stm32l4_oneshot.c
View file

@ -395,7 +395,7 @@ int stm32l4_oneshot_cancel(FAR struct stm32l4_oneshot_s *oneshot,
* If the counter expires while we are doing this, the counter clock will
* be stopped, but the clock will not be disabled.
*
* The expected behavior is that the the counter register will freezes at
* The expected behavior is that the counter register will freezes at
* a value equal to the RC register when the timer expires. The counter
* should have values between 0 and RC in all other cased.
*

8
arch/arm/src/stm32l4/stm32l4_otgfshost.c
View file

@ -1982,7 +1982,7 @@ static ssize_t stm32l4_in_transfer(FAR struct stm32l4_usbhost_s *priv,
{
/* Successfully received another chunk of data... add that to the
* runing total. Then continue reading until we read 'buflen'
* bytes of data or until the the devices NAKs (implying a short
* bytes of data or until the devices NAKs (implying a short
* packet).
*/
@ -2240,8 +2240,8 @@ static ssize_t stm32l4_out_transfer(FAR struct stm32l4_usbhost_s *priv,
/* Check for a special case: If (1) the transfer was NAKed and (2)
* no Tx FIFO empty or Rx FIFO not-empty event occurred, then we
* should be able to just flush the Rx and Tx FIFOs and try again.
* We can detect this latter case because the then the transfer
* buffer pointer and buffer size will be unaltered.
* We can detect this latter case because then the transfer buffer
* pointer and buffer size will be unaltered.
*/
elapsed = clock_systimer() - start;
@ -4635,7 +4635,7 @@ static ssize_t stm32l4_transfer(FAR struct usbhost_driver_s *drvr, usbhost_ep_t
* Description:
* Process a request to handle a transfer descriptor. This method will
* enqueue the transfer request and return immediately. When the transfer
* completes, the the callback will be invoked with the provided transfer.
* completes, the callback will be invoked with the provided transfer.
* This method is useful for receiving interrupt transfers which may come
* infrequently.
*

2
arch/arm/src/stm32l4/stm32l4_rtcc.c
View file

@ -1295,7 +1295,7 @@ int stm32l4_rtc_setalarm(FAR struct alm_setalarm_s *alminfo)
ASSERT(alminfo != NULL);
DEBUGASSERT(RTC_ALARM_LAST > alminfo->as_id);
/* Make sure the the alarm interrupt is enabled at the NVIC */
/* Make sure the alarm interrupt is enabled at the NVIC */
rtc_enable_alarm();

2
arch/arm/src/stm32l4/stm32l4_tickless.c
View file

@ -266,7 +266,7 @@ void arm_timer_initialize(void)
* any failure.
*
* Assumptions:
* Called from the the normal tasking context. The implementation must
* Called from the normal tasking context. The implementation must
* provide whatever mutual exclusion is necessary for correct operation.
* This can include disabling interrupts in order to assure atomic register
* operations.

4
arch/arm/src/tiva/tiva_i2c.c
View file

@ -1301,7 +1301,7 @@ static int tiva_i2c_process(struct tiva_i2c_priv_s *priv, uint32_t status)
{
/* Just continue transferring data. In this case,
* no STOP was sent at the end of the last message
* and the there is no new address.
* and there is no new address.
*
* REVISIT: In this case, the address or the
* direction of the transfer cannot be permitted to
@ -1485,7 +1485,7 @@ static int tiva_i2c_initialize(struct tiva_i2c_priv_s *priv, uint32_t frequency)
#endif
#endif
/* Configure the the initial I2C clock frequency. */
/* Configure the initial I2C clock frequency. */
tiva_i2c_setclock(priv, frequency);

4
arch/arm/src/tiva/tiva_timer.h
View file

@ -600,7 +600,7 @@ uint32_t tiva_timer32_remaining(TIMER_HANDLE handle);
* Description:
* This function may be called at any time to change the timer interval
* match value of a 32-bit timer. This function sets the match register
* the the absolute value specified.
* the absolute value specified.
*
* Input Parameters:
* handle - The handle value returned by tiva_gptm_configure()
@ -625,7 +625,7 @@ static inline void tiva_timer32_absmatch(TIMER_HANDLE handle,
* Description:
* This function may be called at any time to change the timer interval
* match value of a 16-bit timer. This function sets the match register
* the the absolute value specified.
* the absolute value specified.
*
* Input Parameters:
* handle - The handle value returned by tiva_gptm_configure()

2
arch/arm/src/tiva/tiva_timerlib.c
View file

@ -2634,7 +2634,7 @@ uint32_t tiva_timer32_remaining(TIMER_HANDLE handle)
* the timeout event (0x0), the timer reloads its start value
* from the GPTMTAILR register on the next cycle.
*
* The time remaining it then just the the value of the counter
* The time remaining it then just the value of the counter
* register.
*
* REVISIT: Or the counter value +1?

2
arch/arm/src/tiva/tiva_timerlow32.c
View file

@ -433,7 +433,7 @@ static int tiva_settimeout(struct timer_lowerhalf_s *lower, uint32_t timeout)
tmrinfo("Entry: timeout=%d\n", timeout);
/* Calculate the the new time settings */
/* Calculate the new time settings */
tiva_timeout(priv, timeout);

4
arch/arm/src/tiva/tiva_vectors.S
View file

@ -63,7 +63,7 @@
* stale MSP, there will most likely be a system failure.
*
* If the interrupt stack is selected, on the other hand, then the interrupt
* handler will always set the the MSP to the interrupt stack. So when the high
* handler will always set the MSP to the interrupt stack. So when the high
* priority interrupt occurs, it will either use the MSP of the last privileged
* thread to run or, in the case of the nested interrupt, the interrupt stack if
* no privileged task has run.
@ -73,7 +73,7 @@
# error Interrupt stack must be used with high priority interrupts in kernel mode
# endif
/* Use the the BASEPRI to control interrupts is required if nested, high
/* Use the BASEPRI to control interrupts is required if nested, high
* priority interrupts are supported.
*/

4
arch/arm/src/tiva/tm4c_ethernet.c
View file

@ -1591,7 +1591,7 @@ static int tiva_recvframe(FAR struct tiva_ethmac_s *priv)
{
priv->segments++;
/* Check if the there is only one segment in the frame */
/* Check if there is only one segment in the frame */
if (priv->segments == 1)
{
@ -4197,7 +4197,7 @@ void up_netinitialize(void)
* and SIOCSMIIREG ioctl calls** to communicate with the PHY,
* determine what network event took place (Link Up/Down?), and
* take the appropriate actions.
* d. It should then interact the the PHY to clear any pending
* d. It should then interact the PHY to clear any pending
* interrupts, then re-enable the PHY interrupt.
*
* * This is an OS internal interface and should not be used from

2
arch/misoc/src/common/misoc.h
View file

@ -118,7 +118,7 @@ void misoc_puts(const char *str);
* Name: misoc_lowputc
*
* Description:
* Low-level, blocking character output the the serial console.
* Low-level, blocking character output the serial console.
*
****************************************************************************/

2
arch/sim/src/up_simsmp.c
View file

@ -248,7 +248,7 @@ static void sim_handle_signal(int signo, siginfo_t *info, void *context)
*
* Description:
* Create the pthread-specific data key and set the indication of CPU0
* the the main thread.
* the main thread.
*
* Input Parameters:
* None

2
arch/sim/src/up_tickless.c
View file

@ -150,7 +150,7 @@ void sim_timer_initialize(void)
* any failure.
*
* Assumptions:
* Called from the the normal tasking context. The implementation must
* Called from the normal tasking context. The implementation must
* provide whatever mutual exclusion is necessary for correct operation.
* This can include disabling interrupts in order to assure atomic register
* operations.

2
arch/xtensa/src/common/xtensa_testset.c
View file

@ -133,7 +133,7 @@ spinlock_t up_testset(volatile FAR spinlock_t *lock)
* code."
*
* In any case, the return value of SP_UNLOCKED can be trusted and will
* always mean that the the spinlock was set.
* always mean that the spinlock was set.
*/
return (prev == SP_UNLOCKED) ? SP_UNLOCKED : SP_LOCKED;

2
arch/xtensa/src/esp32/chip/esp32_uart.h
View file

@ -1464,7 +1464,7 @@
/* UART_PRE_IDLE_NUM : R/W ;bitpos:[23:0] ;default: 24'h186a00 ; */
/* Description: This register is used to configure the idle duration time
* before the first at_cmd is received by receiver. when the the duration
* before the first at_cmd is received by receiver. when the duration
* is less than this register value it will not take the next data received
* as at_cmd char.
*/

2
arch/xtensa/src/esp32/esp32_gpio.h
View file

@ -100,7 +100,7 @@
#ifndef __ASSEMBLY__
/* Must be big enough to hold the the above encodings */
/* Must be big enough to hold the above encodings */
typedef uint16_t gpio_pinattr_t;
typedef uint8_t gpio_intrtype_t;

2
arch/xtensa/src/esp32/esp32_intercpu_interrupt.c
View file

@ -93,7 +93,7 @@ static int esp32_fromcpu_interrupt(int fromcpu)
DPORT_CPU_INTR_FROM_CPU_1_REG;
putreg32(0, regaddr);
/* Get the the inter-CPU interrupt code */
/* Get the inter-CPU interrupt code */
tocpu = up_cpu_index();
intcode = g_intcode[tocpu];

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