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Initial changes for BeagleBone Black board support (TI AM335x family based on Cortex-A8)

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Squashed commit of the following:

Author: Gregory Nutt <gnutt@nuttx.org>
    Many small changes related to coding style.

Author: Petro Karashchenko <petro.karashchenko@gmail.com>
    configs/beaglebone-black:  Adds initial support for the BeagleBone Black board.
    arch/arm/src/am335x:  Adds initial support for the TI AM355x family.
This commit is contained in:
Petro Karashchenko 2019-01-06 09:05:38 -06:00 committed by Gregory Nutt
parent 5e48ca91fc
commit 1727e47d2e
44 changed files with 9999 additions and 0 deletions
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1
arch/README.txt
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@ -157,6 +157,7 @@ arch/arm - ARM-based micro-controllers
MCU support
arch/arm/include/a1x and arch/arm/src/a1x
arch/arm/include/am335x and arch/arm/src/am335x
arch/arm/include/c5471 and arch/arm/src/c5471
arch/arm/include/dm320 and arch/arm/src/dm320
arch/arm/include/efm32 and arch/arm/src/efm32

18
arch/arm/Kconfig
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@ -24,6 +24,20 @@ config ARCH_CHIP_A1X
---help---
Allwinner A1X family: A10, A10S (A12), A13 (ARM Cortex-A8)
config ARCH_CHIP_AM335X
bool "TI AM335X"
select ARCH_CORTEXA8
select ARCH_HAVE_FPU
select ARCH_HAVE_IRQPRIO
select ARCH_HAVE_LOWVECTORS
select ARCH_HAVE_FETCHADD
select ARCH_HAVE_SDRAM
select BOOT_RUNFROMSDRAM
select ARCH_HAVE_ADDRENV
select ARCH_NEED_ADDRENV_MAPPING
---help---
TI AM335X family: AM3356, AM3357, AM3358, AM3359 (ARM Cortex-A8)
config ARCH_CHIP_C5471
bool "TMS320 C5471"
select ARCH_ARM7TDMI
@ -586,6 +600,7 @@ config ARCH_FAMILY
config ARCH_CHIP
string
default "a1x" if ARCH_CHIP_A1X
default "am335x" if ARCH_CHIP_AM335X
default "c5471" if ARCH_CHIP_C5471
default "dm320" if ARCH_CHIP_DM320
default "efm32" if ARCH_CHIP_EFM32
@ -783,6 +798,9 @@ endif
if ARCH_CHIP_A1X
source arch/arm/src/a1x/Kconfig
endif
if ARCH_CHIP_AM335X
source arch/arm/src/am335x/Kconfig
endif
if ARCH_CHIP_C5471
source arch/arm/src/c5471/Kconfig
endif

251
arch/arm/src/am335x/Kconfig Normal file
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@ -0,0 +1,251 @@
#
# For a description of the syntax of this configuration file,
# see the file kconfig-language.txt in the NuttX tools repository.
#
if ARCH_CHIP_AM335X
comment "AM335x Configuration Options"
choice
prompt "TI AM335X Chip Selection"
default ARCH_CHIP_AM3358
config ARCH_CHIP_AM3358
bool "AM3358"
endchoice
menu "TI AM335X Peripheral Support"
config AM335X_UART0
bool "UART 0"
default n
select UART0_SERIALDRIVER
select ARCH_HAVE_SERIAL_TERMIOS
config AM335X_UART1
bool "UART 1"
default n
select UART1_SERIALDRIVER
select ARCH_HAVE_SERIAL_TERMIOS
config AM335X_UART2
bool "UART 2"
default n
select UART2_SERIALDRIVER
select ARCH_HAVE_SERIAL_TERMIOS
config AM335X_UART3
bool "UART 3"
default n
select UART3_SERIALDRIVER
select ARCH_HAVE_SERIAL_TERMIOS
config AM335X_UART4
bool "UART 4"
default n
select UART4_SERIALDRIVER
select ARCH_HAVE_SERIAL_TERMIOS
config AM335X_UART5
bool "UART 5"
default n
select UART5_SERIALDRIVER
select ARCH_HAVE_SERIAL_TERMIOS
config AM335X_DMTIMER0
bool "Timer 0"
default n
config AM335X_DMTIMER2
bool "Timer 2"
default n
config AM335X_DMTIMER3
bool "Timer 3"
default n
config AM335X_DMTIMER4
bool "Timer 4"
default n
config AM335X_DMTIMER5
bool "Timer 5"
default n
config AM335X_DMTIMER6
bool "Timer 6"
default n
config AM335X_DMTIMER7
bool "Timer 7"
default n
config AM335X_IRQ_WD
bool "Watchdog"
default n
config AM335X_EDMA
bool "Enhanced Direct Memory Access"
default n
config AM335X_GPIO
bool "GPIO"
default n
config AM335X_TSC
bool "Touchscreen Controller"
default n
config AM335X_LCDC
bool "LCD Controller"
default n
config AM335X_CPSW
bool "Ethernet subsustem"
default n
config AM335X_PWMSS
bool "Pulse-Width Modulation Subsystem"
default n
config AM335X_USB0
bool "USB 0"
default n
config AM335X_USB1
bool "USB 1"
default n
config AM335X_MMCHS0
bool "MMC/SD/SDIO0 High Speed Host Controller 0"
default n
config AM335X_MMCHS1
bool "MMC/SD/SDIO0 High Speed Host Controller 1"
default n
config AM335X_MMCHS2
bool "MMC/SD/SDIO0 High Speed Host Controller 2"
default n
config AM335X_I2C0
bool "Multi-master I2C Controller 0"
default n
config AM335X_I2C0
bool "Multi-master I2C Controller 1"
default n
config AM335X_I2C0
bool "Multi-master I2C Controller 2"
default n
config AM335X_MCASP0
bool "Multichannel Audio Serial Port 0"
default n
config AM335X_MCASP1
bool "Multichannel Audio Serial Port 1"
default n
config AM335X_DCAN0
bool "DCAN Bus 0 Controller"
default n
config AM335X_DCAN1
bool "DCAN Bus 1 Controller"
default n
config AM335X_MCSPI0
bool "MCSPI 0"
default n
config AM335X_MCSPI1
bool "MCSPI 1"
default n
config AM335X_IRQ_PERFMU
bool "Performance monitor"
default n
config AM335X_SGX
bool "Graphics Accelerator"
default n
endmenu
config AM335X_GPIO_IRQ
bool "GPIO interrupts"
default n
---help---
Select to enable support for GPIO interrupts. These will
be handled through a second level of interrupt decoding and will
otherwise appear as any other interrupt.
choice
prompt "Boot device"
default AM335X_BOOT_SDCARD
config AM335X_BOOT_NAND
bool "NAND FLASH"
config AM335X_BOOT_SPINOR
bool "SPI NOR FLASH"
config AM335X_BOOT_SDCARD
bool "SD card"
config AM335X_BOOT_USB
bool "USB"
endchoice # Boot device
config AM335X_DDR_MAPOFFSET
int "Installed SDRAM offset"
default 0
---help---
The size of the installed SRAM memory is required in order to
properly configure memory mapping. The mapping will begin at the
start of SDRAM plus AM335X_DDR_MAPOFFSET and extend for DDR_MAPSIZE
bytes. NOTE typically AM335X_MAP_OFFSET is zero and AM335X_DDR_MAPSIZE is
the full, installed size of the DRAM. But these values can be
modified to set aside memory at the beginning or end of SRAM that is
unmapped (or mapped differently). NOTE also that this value relates
closely to other settings:
RAM_START and RAM_VSTART give this physical and virtual addresses
of the start of usable memory (begining with .text). NOTE that
this may not necessarily be the actual start of the mapped SDRAM
region. It will be larger if NuttX begins at an offset from
beginning of mapped SDRAM (which is the normal case).
RAM_SIZE gives the size of the .text, .data, and .bss sections
plus the size of the available heap. NOTE that RAM_SIZE may not
include all of SDRAM up to the end of mapped region.
config AM335X_DDR_MAPSIZE
int "Installed SDRAM size"
default 536870912
---help---
The size of the installed SRAM memory is required in order to
properly configure memory mapping. The mapping will begin at the
start of SDRAM plus AM335X_DDR_MAPOFFSET and extend for DDR_MAPSIZE
bytes. NOTE typically AM335X_MAP_OFFSET is zero and AM335X_DDR_MAPSIZE is
the full, installed size of the DRAM. But these values can be
modified to set aside memory at the beginning or end of SRAM that is
unmapped (or mapped differently). NOTE also that this value relates
closely to other settings:
RAM_START and RAM_VSTART give this physical and virtual addresses
of the start of usable memory (begining with .text). NOTE that
this may not necessarily be the actual start of the mapped SDRAM
region. It will be larger if NuttX begins at an offset from
beginning of mapped SDRAM (which is the normal case).
RAM_SIZE gives the size of the .text, .data, and .bss sections
plus the size of the available heap. NOTE that RAM_SIZE may not
include all of SDRAM up to the end of mapped region.
endif # ARCH_CHIP_AM335X

140
arch/arm/src/am335x/Make.defs Normal file
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@ -0,0 +1,140 @@
############################################################################
# arch/arm/am335x/Make.defs
#
# Copyright (C) 2019 Gregory Nutt. All rights reserved.
# Author: Gregory Nutt <gnutt@nuttx.org>
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions
# are met:
#
# 1. Redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer.
# 2. Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in
# the documentation and/or other materials provided with the
# distribution.
# 3. Neither the name NuttX nor the names of its contributors may be
# used to endorse or promote products derived from this software
# without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
# POSSIBILITY OF SUCH DAMAGE.
#
############################################################################
# The vector table is the "head" object, i.e., the one that must forced into
# the link in order to draw in all of the other components
HEAD_ASRC = arm_vectortab.S
ifeq ($(CONFIG_BUILD_KERNEL),y)
STARTUP_OBJS = crt0$(OBJEXT)
endif
# Force the start-up logic to be at the beginning of the .text to simplify
# debug.
ifeq ($(CONFIG_PAGING),y)
CMN_ASRCS = arm_pghead.S
else
CMN_ASRCS = arm_head.S
endif
# Common assembly language files
CMN_ASRCS += arm_vectors.S arm_fpuconfig.S arm_fullcontextrestore.S
CMN_ASRCS += arm_saveusercontext.S arm_vectoraddrexcptn.S arm_vfork.S
CMN_ASRCS += arm_testset.S
CMN_ASRCS += cp15_coherent_dcache.S cp15_invalidate_dcache.S
CMN_ASRCS += cp15_clean_dcache.S cp15_flush_dcache.S cp15_invalidate_dcache_all.S
# Common C source files
CMN_CSRCS = up_initialize.c up_idle.c up_interruptcontext.c up_exit.c
CMN_CSRCS += up_createstack.c up_releasestack.c up_usestack.c up_vfork.c
CMN_CSRCS += up_puts.c up_mdelay.c up_stackframe.c up_udelay.c
CMN_CSRCS += up_modifyreg8.c up_modifyreg16.c up_modifyreg32.c
CMN_CSRCS += arm_assert.c arm_blocktask.c arm_copyfullstate.c arm_dataabort.c
CMN_CSRCS += arm_doirq.c arm_initialstate.c arm_mmu.c arm_prefetchabort.c
CMN_CSRCS += arm_releasepending.c arm_reprioritizertr.c
CMN_CSRCS += arm_schedulesigaction.c arm_sigdeliver.c arm_syscall.c
CMN_CSRCS += arm_unblocktask.c arm_undefinedinsn.c
# Use common heap allocation for now (may need to be customized later)
CMN_CSRCS += up_allocateheap.c
# Configuration dependent C and assembly language files
ifeq ($(CONFIG_PAGING),y)
CMN_CSRCS += arm_allocpage.c arm_checkmapping.c arm_pginitialize.c
CMN_CSRCS += arm_va2pte.c
endif
ifeq ($(CONFIG_BUILD_KERNEL),y)
CMN_CSRCS += up_task_start.c up_pthread_start.c arm_signal_dispatch.c
endif
ifeq ($(CONFIG_ARCH_ADDRENV),y)
CMN_CSRCS += arm_addrenv.c arm_addrenv_utils.c arm_pgalloc.c
ifeq ($(CONFIG_ARCH_STACK_DYNAMIC),y)
CMN_CSRCS += arm_addrenv_ustack.c
endif
ifeq ($(CONFIG_ARCH_KERNEL_STACK),y)
CMN_CSRCS += arm_addrenv_kstack.c
endif
ifeq ($(CONFIG_MM_SHM),y)
CMN_CSRCS += arm_addrenv_shm.c
endif
endif
ifeq ($(CONFIG_MM_PGALLOC),y)
CMN_CSRCS += arm_physpgaddr.c
ifeq ($(CONFIG_ARCH_PGPOOL_MAPPING),y)
CMN_CSRCS += arm_virtpgaddr.c
endif
endif
ifeq ($(CONFIG_ELF),y)
CMN_CSRCS += arm_coherent_dcache.c
else ifeq ($(CONFIG_MODULE),y)
CMN_CSRCS += arm_coherent_dcache.c
endif
ifeq ($(CONFIG_ARCH_FPU),y)
CMN_ASRCS += arm_savefpu.S arm_restorefpu.S
CMN_CSRCS += arm_copyarmstate.c
endif
ifeq ($(CONFIG_STACK_COLORATION),y)
CMN_CSRCS += up_checkstack.c
endif
# AM335x-specific assembly language files
CHIP_ASRCS =
# AM335x-specific C source files
CHIP_CSRCS = am335x_boot.c am335x_clockconfig.c am335x_pinmux.c am335x_irq.c
CHIP_CSRCS += am335x_gpio.c am335x_lowputc.c am335x_serial.c
ifneq ($(CONFIG_SCHED_TICKLESS),y)
CHIP_CSRCS += am335x_timerisr.c
endif
ifeq ($(CONFIG_AM335X_GPIO_IRQ),y)
CHIP_CSRCS += am335x_gpioirq.c
endif

457
arch/arm/src/am335x/am335x_boot.c Normal file
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@ -0,0 +1,457 @@
/****************************************************************************
* arch/arm/src/am335x/am335x_boot.c
*
* Copyright (C) 2018 Petro Karashchenko. All rights reserved.
* Author: Petro Karashchenko <petro.karashchenko@gmail.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <assert.h>
#include <debug.h>
#ifdef CONFIG_PAGING
# include <nuttx/page.h>
#endif
#include <arch/board/board.h>
#include "chip.h"
#include "arm.h"
#include "mmu.h"
#include "cache.h"
#include "fpu.h"
#include "up_internal.h"
#include "up_arch.h"
#include "am335x_clockconfig.h"
#include "am335x_lowputc.h"
#include "am335x_boot.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Name: showprogress
*
* Description:
* Print a character on the UART to show boot status.
*
****************************************************************************/
#ifdef CONFIG_DEBUG_FEATURES
# define showprogress(c) up_lowputc(c)
#else
# define showprogress(c)
#endif
/* The vectors are, by default, positioned at the beginning of the text
* section. They will always have to be copied to the correct location.
*
* If we are using high vectors (CONFIG_ARCH_LOWVECTORS=n). In this case,
* the vectors will lie at virtual address 0xffff:0000 and we will need
* to a) copy the vectors to another location, and b) map the vectors
* to that address, and
*
* For the case of CONFIG_ARCH_LOWVECTORS=y, defined. Vectors will be
* copied to OCMC0 RAM at address 0x0000:0000
*/
#if !defined(CONFIG_ARCH_LOWVECTORS) && defined(CONFIG_ARCH_ROMPGTABLE)
# error High vector remap cannot be performed if we are using a ROM page table
#endif
/****************************************************************************
* Public Data
****************************************************************************/
/* Symbols defined via the linker script */
extern uint32_t _vector_start; /* Beginning of vector block */
extern uint32_t _vector_end; /* End+1 of vector block */
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Private Data
****************************************************************************/
/* This table describes how to map a set of 1Mb pages to space the physical
* address space of the A1X.
*/
#ifndef CONFIG_ARCH_ROMPGTABLE
static const struct section_mapping_s g_section_mapping[] =
{
{ AM335X_GPMC_PSECTION, AM335X_GPMC_VSECTION, /* Includes vectors and page table */
AM335X_GPMC_MMUFLAGS, AM335X_GPMC_NSECTIONS
},
{ AM335X_BROM_PSECTION, AM335X_BROM_VSECTION,
AM335X_BROM_MMUFLAGS, AM335X_BROM_NSECTIONS
},
{ AM335X_ISRAM_PSECTION, AM335X_ISRAM_VSECTION,
AM335X_ISRAM_MMUFLAGS, AM335X_ISRAM_NSECTIONS
},
{ AM335X_OCMC0_PSECTION, AM335X_OCMC0_VSECTION,
AM335X_OCMC0_MMUFLAGS, AM335X_OCMC0_NSECTIONS
},
{ AM335X_PERIPH_PSECTION, AM335X_PERIPH_VSECTION,
AM335X_PERIPH_MMUFLAGS, AM335X_PERIPH_NSECTIONS
},
{ AM335X_DDR_PSECTION, AM335X_DDR_VSECTION,
AM335X_DDR_MMUFLAGS, AM335X_DDR_NSECTIONS
}
};
#define NMAPPINGS \
(sizeof(g_section_mapping) / sizeof(struct section_mapping_s))
const size_t g_num_mappings = NMAPPINGS;
#endif
/****************************************************************************
* Name: am335x_setupmappings
*
* Description
* Map all of the initial memory regions defined in g_section_mapping[]
*
****************************************************************************/
#ifndef CONFIG_ARCH_ROMPGTABLE
static inline void am335x_setupmappings(void)
{
int i;
/* Set up each group of section mappings */
for (i = 0; i < g_num_mappings; i++)
{
mmu_l1_map_region(&g_section_mapping[i]);
}
}
#else
# define am335x_setupmappings()
#endif
/****************************************************************************
* Name: am335x_remap
*
* Description
* Map all of the final memory regions defined in g_operational_mapping[]
*
****************************************************************************/
#ifdef NEED_SDRAM_REMAPPING
static inline void am335x_remap(void)
{
int i;
/* Re-map each group of section */
for (i = 0; i < g_num_opmappings; i++)
{
mmu_l1_map_region(&g_operational_mapping[i]);
}
}
#endif
/****************************************************************************
* Name: am335x_vectorpermissions
*
* Description:
* Set permissions on the vector mapping.
*
****************************************************************************/
#if !defined(CONFIG_ARCH_ROMPGTABLE) && defined(CONFIG_ARCH_LOWVECTORS) && \
defined(CONFIG_PAGING)
static void am335x_vectorpermissions(uint32_t mmuflags)
{
/* The PTE for the beginning of OCMC0 RAM is at the base of the L2 page table */
uint32_t pte = mmu_l2_getentry(PG_L2_VECT_VADDR, 0);
/* Mask out the old MMU flags from the page table entry.
*
* The pte might be zero the first time this function is called.
*/
if (pte == 0)
{
pte = PG_VECT_PBASE;
}
else
{
pte &= PG_L1_PADDRMASK;
}
/* Update the page table entry with the MMU flags and save */
mmu_l2_setentry(PG_L2_VECT_VADDR, pte, 0, mmuflags);
}
#endif
/****************************************************************************
* Name: am335x_vectorsize
*
* Description:
* Return the size of the vector data
*
****************************************************************************/
static inline size_t am335x_vectorsize(void)
{
uintptr_t src;
uintptr_t end;
src = (uintptr_t)&_vector_start;
end = (uintptr_t)&_vector_end;
return (size_t)(end - src);
}
/****************************************************************************
* Name: am335x_vectormapping
*
* Description:
* Setup a special mapping for the interrupt vectors when (1) the
* interrupt vectors are not positioned in ROM, and when (2) the interrupt
* vectors are located at the high address, 0xffff0000. When the
* interrupt vectors are located in ROM, we just have to assume that they
* were set up correctly; When vectors are located in low memory,
* 0x00000000, the mapping for the ROM memory region will be suppressed.
*
****************************************************************************/
#if !defined(CONFIG_ARCH_ROMPGTABLE) && !defined(CONFIG_ARCH_LOWVECTORS)
static void am335x_vectormapping(void)
{
uint32_t vector_paddr = AM335X_VECTOR_PADDR & PTE_SMALL_PADDR_MASK;
uint32_t vector_vaddr = AM335X_VECTOR_VADDR & PTE_SMALL_PADDR_MASK;
uint32_t vector_size = (uint32_t)&_vector_end - (uint32_t)&_vector_start;
uint32_t end_paddr = AM335X_VECTOR_PADDR + vector_size;
/* REVISIT: Cannot really assert in this context */
DEBUGASSERT (vector_size <= VECTOR_TABLE_SIZE);
/* We want to keep our interrupt vectors and interrupt-related logic in
* on-chip RAM (OCMC0). The AM335X has 64Kb of OCMC0 RAM positioned at
* physical address 0x4030:0000; we need to map this to 0xffff:0000.
*/
while (vector_paddr < end_paddr)
{
mmu_l2_setentry(VECTOR_L2_VBASE, vector_paddr, vector_vaddr,
MMU_L2_VECTORFLAGS);
vector_paddr += 4096;
vector_vaddr += 4096;
}
/* Now set the level 1 descriptor to refer to the level 2 page table. */
mmu_l1_setentry(VECTOR_L2_PBASE & PMD_PTE_PADDR_MASK,
AM335X_VECTOR_VADDR & PMD_PTE_PADDR_MASK,
MMU_L1_VECTORFLAGS);
}
#else
/* No vector remap */
# define am335x_vectormapping()
#endif
/****************************************************************************
* Name: am335x_copyvectorblock
*
* Description:
* Copy the interrupt block to its final destination. Vectors are already
* positioned at the beginning of the text region and only need to be
* copied in the case where we are using high vectors or where the beginning
* of the text region cannot be remapped to address zero.
*
****************************************************************************/
static void am335x_copyvectorblock(void)
{
uint32_t *src;
uint32_t *end;
uint32_t *dest;
#ifdef CONFIG_PAGING
/* If we are using re-mapped vectors in an area that has been marked
* read only, then temporarily mark the mapping write-able (non-buffered).
*/
am335x_vectorpermissions(MMU_L2_VECTRWFLAGS);
#endif
/* Copy the vectors into OCMC0 RAM at the address that will be mapped to the vector
* address:
*
* AM335X_VECTOR_PADDR - Unmapped, physical address of vector table in OCMC0 RAM
* AM335X_VECTOR_VSRAM - Virtual address of vector table in OCMC0 RAM
* AM335X_VECTOR_VADDR - Virtual address of vector table (0x00000000 or
* 0xffff0000)
*/
src = (uint32_t *)&_vector_start;
end = (uint32_t *)&_vector_end;
dest = (uint32_t *)(AM335X_VECTOR_VSRAM);
while (src < end)
{
*dest++ = *src++;
}
#if !defined(CONFIG_ARCH_LOWVECTORS) && defined(CONFIG_PAGING)
/* Make the vectors read-only, cache-able again */
am335x_vectorpermissions(MMU_L2_VECTORFLAGS);
#else
/* Flush the DCache to assure that the vector data is in physical RAM */
arch_clean_dcache((uintptr_t)AM335X_VECTOR_VSRAM,
(uintptr_t)AM335X_VECTOR_VSRAM + am335x_vectorsize());
#endif
}
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: arm_boot
*
* Description:
* Complete boot operations started in arm_head.S
*
* This logic will be executing in SDRAM. This boot logic was started by
* the AM335x boot logic. At this point in time, clocking and SDRAM have
* already be initialized (they must be because we are executing out of
* SDRAM). So all that must be done here is to:
*
* 1) Refine the memory mapping,
* 2) Configure the serial console, and
* 3) Perform board-specific initializations.
*
****************************************************************************/
void arm_boot(void)
{
#ifndef CONFIG_ARCH_ROMPGTABLE
/* __start provided the basic MMU mappings for OCMC0 RAM. Now provide mappings
* for all IO regions (Including the vector region).
*/
am335x_setupmappings();
/* Provide a special mapping for the OCMC0 RAM interrupt vector positioned in
* high memory.
*/
am335x_vectormapping();
#endif /* CONFIG_ARCH_ROMPGTABLE */
/* Setup up vector block. _vector_start and _vector_end are exported from
* arm_vector.S
*/
am335x_copyvectorblock();
/* Initialize clocking to settings provided by board-specific logic */
am335x_clockconfig();
#ifdef CONFIG_ARCH_FPU
/* Initialize the FPU */
arm_fpuconfig();
#endif
/* Perform board-specific memory initialization, This must include
* initialization of board-specific memory resources (e.g., SDRAM)
*
* NOTE: We must use caution prior to this point to make sure that
* the logic does not access any global variables that might lie
* in SDRAM.
*/
am335x_memory_initialize();
#ifdef NEED_SDRAM_REMAPPING
/* SDRAM was configured in a temporary state to support low-level
* initialization. Now that the SDRAM has been fully initialized,
* we can reconfigure the SDRAM in its final, fully cache-able state.
*/
am335x_remap();
#endif
#ifdef CONFIG_BOOT_SDRAM_DATA
/* This setting is inappropriate for the AM335x because the code is *always*
* executing from SDRAM. If CONFIG_BOOT_SDRAM_DATA happens to be set,
* let's try to do the right thing and initialize the .data and .bss
* sections.
*/
arm_data_initialize();
#endif
/* Perform common, low-level chip initialization (might do nothing) */
am335x_lowsetup();
#ifdef USE_EARLYSERIALINIT
/* Perform early serial initialization if we are going to use the serial
* driver.
*/
up_earlyserialinit();
#endif
/* Perform board-specific initialization, This must include:
*
* - Initialization of board-specific memory resources (e.g., SDRAM)
* - Configuration of board specific resources (PIOs, LEDs, etc).
*/
am335x_board_initialize();
}

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/****************************************************************************
* arch/arm/src/am335x/am335x_boot.h
*
* Copyright (C) 2018 Petro Karashchenko. All rights reserved.
* Author: Petro Karashchenko <petro.karashchneko@gmail.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_AM335X_AM335X_BOOT_H
#define __ARCH_ARM_SRC_AM335X_AM335X_BOOT_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: am335x_memory_initialize
*
* Description:
* All AM335X architectures must provide the following entry point. This
* entry point is called early in the initialization before memory has
* been configured. This board-specific function is responsible for
* configuring any on-board memories.
*
* Logic in imx_memory_initialize must be careful to avoid using any
* global variables because those will be uninitialized at the time this
* function is called.
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
void am335x_memory_initialize(void);
/****************************************************************************
* Name: imx_board_initialize
*
* Description:
* All AM335X architectures must provide the following entry point. This
* entry point is called in the initialization phase -- after
* imx_memory_initialize and after all memory has been configured and
* mapped but before any devices have been initialized.
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
void am335x_board_initialize(void);
#endif /* __ARCH_ARM_SRC_AM335X_AM335X_BOOT_H */

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/****************************************************************************
* arch/arm/src/am335x/am335x_clockconfig.c
*
* Copyright (C) 2018 Petro Karashchenko. All rights reserved.
* Author: Petro Karashchenko <petro.karashchenko@gmail.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "up_arch.h"
#if 0
/* TODO: add clock register module */
#include "chip/am335x_ccm.h"
#endif
#include "am335x_config.h"
#include "am335x_clockconfig.h"
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: am335x_clockconfig
*
* Description:
* Called to initialize the AM335X. This does whatever setup is needed to
* put the SoC in a usable state. This includes the initialization of
* clocking using the settings in board.h.
*
****************************************************************************/
void am335x_clockconfig(void)
{
/* Don't change the current basic clock configuration if we are running
* from SDRAM. In this case, some bootloader logic has already configured
* clocking and SDRAM. We are pretty much committed to using things the
* way that the bootloader has left them.
*
* Clocking will be configured at 792 MHz initially when started via
* U-Boot. The Linux kernel will uses the CPU frequency scaling code
* which will switch the processor frequency between 400 MHz and 1GHz based
* on load and temperature. For now, NuttX simply leaves the clocking at
* 792MHz.
*/
#ifndef CONFIG_AM335X_BOOT_SDRAM
# warning Missing logic
#endif
}

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/****************************************************************************
* arch/arm/src/am335x/am335x_clockconfig.h
*
* Copyright (C) 2018 Petro Karashchenko. All rights reserved.
* Author: Petro Karashchenko <petro.karashchenko@gmail.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_AM335X_AM335X_CLOCKCONFIG_H
#define __ARCH_ARM_SRC_AM335X_AM335X_CLOCKCONFIG_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: am335x_clockconfig
*
* Description:
* Called to initialize the AM335X. This does whatever setup is needed to
* put the SoC in a usable state. This includes the initialization of
* clocking using the settings in board.h.
*
****************************************************************************/
void am335x_clockconfig(void);
#endif /* __ARCH_ARM_SRC_AM335X_AM335X_CLOCKCONFIG_H */

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/************************************************************************************
* arch/arm/src/am335x/am335x_config.h
*
* Copyright (C) 2018 Petro Karashchenko. All rights reserved.
* Author: Petro Karashchenko <petro.karashchenko@gmail.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_AM335X_AM335X_CONFIG_H
#define __ARCH_ARM_SRC_AM335X_AM335X_CONFIG_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
#include <arch/board/board.h>
#include "chip.h"
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* Configuration *********************************************************************/
/* Are any UARTs enabled? */
#undef HAVE_UART_DEVICE
#if defined(CONFIG_AM335X_UART0) || defined(CONFIG_AM335X_UART1) || \
defined(CONFIG_AM335X_UART2) || defined(CONFIG_AM335X_UART3) || \
defined(CONFIG_AM335X_UART4) || defined(CONFIG_AM335X_UART5)
# define HAVE_UART_DEVICE 1
#endif
/* Is there a serial console? There should be at most one defined. It could be on
* any UARTn, n=0,1,2,3,4,5
*/
#if defined(CONFIG_UART0_SERIAL_CONSOLE) && defined(CONFIG_AM335X_UART0)
# undef CONFIG_UART1_SERIAL_CONSOLE
# undef CONFIG_UART2_SERIAL_CONSOLE
# undef CONFIG_UART3_SERIAL_CONSOLE
# undef CONFIG_UART4_SERIAL_CONSOLE
# undef CONFIG_UART5_SERIAL_CONSOLE
# define HAVE_SERIAL_CONSOLE 1
#elif defined(CONFIG_UART1_SERIAL_CONSOLE) && defined(CONFIG_AM335X_UART1)
# undef CONFIG_UART0_SERIAL_CONSOLE
# undef CONFIG_UART2_SERIAL_CONSOLE
# undef CONFIG_UART3_SERIAL_CONSOLE
# undef CONFIG_UART4_SERIAL_CONSOLE
# undef CONFIG_UART5_SERIAL_CONSOLE
# define HAVE_SERIAL_CONSOLE 1
#elif defined(CONFIG_UART2_SERIAL_CONSOLE) && defined(CONFIG_AM335X_UART2)
# undef CONFIG_UART0_SERIAL_CONSOLE
# undef CONFIG_UART1_SERIAL_CONSOLE
# undef CONFIG_UART3_SERIAL_CONSOLE
# undef CONFIG_UART4_SERIAL_CONSOLE
# undef CONFIG_UART5_SERIAL_CONSOLE
# define HAVE_SERIAL_CONSOLE 1
#elif defined(CONFIG_UART3_SERIAL_CONSOLE) && defined(CONFIG_AM335X_UART3)
# undef CONFIG_UART0_SERIAL_CONSOLE
# undef CONFIG_UART1_SERIAL_CONSOLE
# undef CONFIG_UART2_SERIAL_CONSOLE
# undef CONFIG_UART4_SERIAL_CONSOLE
# undef CONFIG_UART5_SERIAL_CONSOLE
# define HAVE_SERIAL_CONSOLE 1
#elif defined(CONFIG_UART4_SERIAL_CONSOLE) && defined(CONFIG_AM335X_UART4)
# undef CONFIG_UART0_SERIAL_CONSOLE
# undef CONFIG_UART1_SERIAL_CONSOLE
# undef CONFIG_UART2_SERIAL_CONSOLE
# undef CONFIG_UART3_SERIAL_CONSOLE
# undef CONFIG_UART5_SERIAL_CONSOLE
# define HAVE_SERIAL_CONSOLE 1
#elif defined(CONFIG_UART5_SERIAL_CONSOLE) && defined(CONFIG_AM335X_UART5)
# undef CONFIG_UART0_SERIAL_CONSOLE
# undef CONFIG_UART1_SERIAL_CONSOLE
# undef CONFIG_UART2_SERIAL_CONSOLE
# undef CONFIG_UART3_SERIAL_CONSOLE
# undef CONFIG_UART4_SERIAL_CONSOLE
# define HAVE_SERIAL_CONSOLE 1
#else
# undef CONFIG_UART0_SERIAL_CONSOLE
# undef CONFIG_UART1_SERIAL_CONSOLE
# undef CONFIG_UART2_SERIAL_CONSOLE
# undef CONFIG_UART3_SERIAL_CONSOLE
# undef CONFIG_UART4_SERIAL_CONSOLE
# undef CONFIG_UART5_SERIAL_CONSOLE
# undef HAVE_SERIAL_CONSOLE
#endif
/* Check UART flow control (Not yet supported) */
# undef CONFIG_UART0_FLOWCONTROL
# undef CONFIG_UART1_FLOWCONTROL
# undef CONFIG_UART2_FLOWCONTROL
# undef CONFIG_UART3_FLOWCONTROL
# undef CONFIG_UART4_FLOWCONTROL
# undef CONFIG_UART5_FLOWCONTROL
/************************************************************************************
* Public Types
************************************************************************************/
/************************************************************************************
* Public Data
************************************************************************************/
/************************************************************************************
* Public Functions
************************************************************************************/
#endif /* __ARCH_ARM_SRC_AM335X_AM335X_CONFIG_H */

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/****************************************************************************
* arch/arm/src/am335x/am335x_gpio.c
*
* Copyright (C) 2018 Petro Karashchenko. All rights reserved.
* Author: Petro Karashchenko <petro.karashchneko@gmail.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <stdbool.h>
#include <errno.h>
#include <nuttx/irq.h>
#include "chip.h"
#include "up_arch.h"
#include "am335x_pinmux.h"
#include "am335x_gpio.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#define AM335X_PADCTL_INVALID 255
/****************************************************************************
* Private Data
****************************************************************************/
const uintptr_t g_gpiobase[AM335X_GPIO_NPORTS] =
{
AM335X_GPIO0_VADDR, /* GPIO0 */
AM335X_GPIO1_VADDR, /* GPIO1 */
AM335X_GPIO2_VADDR, /* GPIO2 */
AM335X_GPIO3_VADDR /* GPIO3 */
};
static const uint8_t g_gpio0_padctl[AM335X_GPIO_NPINS] =
{
AM335X_PADCTL_MDIO_INDEX, /* GPIO0 Pin 0 */
AM335X_PADCTL_MDC_INDEX, /* GPIO0 Pin 1 */
AM335X_PADCTL_SPI0_SCLK_INDEX, /* GPIO0 Pin 2 */
AM335X_PADCTL_SPI0_D0_INDEX, /* GPIO0 Pin 3 */
AM335X_PADCTL_SPI0_D1_INDEX, /* GPIO0 Pin 4 */
AM335X_PADCTL_SPI0_CS0_INDEX, /* GPIO0 Pin 5 */
AM335X_PADCTL_SPI0_CS1_INDEX, /* GPIO0 Pin 6 */
AM335X_PADCTL_ECAP0_IN_PWM0_OUT_INDEX, /* GPIO0 Pin 7 */
AM335X_PADCTL_LCD_DATA12_INDEX, /* GPIO0 Pin 8 */
AM335X_PADCTL_LCD_DATA13_INDEX, /* GPIO0 Pin 9 */
AM335X_PADCTL_LCD_DATA14_INDEX, /* GPIO0 Pin 10 */
AM335X_PADCTL_LCD_DATA15_INDEX, /* GPIO0 Pin 11 */
AM335X_PADCTL_UART1_CTSN_INDEX, /* GPIO0 Pin 12 */
AM335X_PADCTL_UART1_RTSN_INDEX, /* GPIO0 Pin 13 */
AM335X_PADCTL_UART1_RXD_INDEX, /* GPIO0 Pin 14 */
AM335X_PADCTL_UART1_TXD_INDEX, /* GPIO0 Pin 15 */
AM335X_PADCTL_MII1_TXD3_INDEX, /* GPIO0 Pin 16 */
AM335X_PADCTL_MII1_TXD2_INDEX, /* GPIO0 Pin 17 */
AM335X_PADCTL_USB0_DRVVBUS_INDEX, /* GPIO0 Pin 18 */
AM335X_PADCTL_XDMA_EVENT_INTR0_INDEX, /* GPIO0 Pin 19 */
AM335X_PADCTL_XDMA_EVENT_INTR1_INDEX, /* GPIO0 Pin 20 */
AM335X_PADCTL_MII1_TXD1_INDEX, /* GPIO0 Pin 21 */
AM335X_PADCTL_GPMC_AD8_INDEX, /* GPIO0 Pin 22 */
AM335X_PADCTL_GPMC_AD9_INDEX, /* GPIO0 Pin 23 */
AM335X_PADCTL_INVALID, /* GPIO0 Pin 24 */
AM335X_PADCTL_INVALID, /* GPIO0 Pin 25 */
AM335X_PADCTL_GPMC_AD10_INDEX, /* GPIO0 Pin 26 */
AM335X_PADCTL_GPMC_AD11_INDEX, /* GPIO0 Pin 27 */
AM335X_PADCTL_MII1_TXD0_INDEX, /* GPIO0 Pin 28 */
AM335X_PADCTL_RMII1_REF_CLK_INDEX, /* GPIO0 Pin 29 */
AM335X_PADCTL_GPMC_WAIT0_INDEX, /* GPIO0 Pin 30 */
AM335X_PADCTL_GPMC_WPN_INDEX /* GPIO0 Pin 31 */
};
static const uint8_t g_gpio1_padctl[AM335X_GPIO_NPINS] =
{
AM335X_PADCTL_GPMC_AD0_INDEX, /* GPIO1 Pin 0 */
AM335X_PADCTL_GPMC_AD1_INDEX, /* GPIO1 Pin 1 */
AM335X_PADCTL_GPMC_AD2_INDEX, /* GPIO1 Pin 2 */
AM335X_PADCTL_GPMC_AD3_INDEX, /* GPIO1 Pin 3 */
AM335X_PADCTL_GPMC_AD4_INDEX, /* GPIO1 Pin 4 */
AM335X_PADCTL_GPMC_AD5_INDEX, /* GPIO1 Pin 5 */
AM335X_PADCTL_GPMC_AD6_INDEX, /* GPIO1 Pin 6 */
AM335X_PADCTL_GPMC_AD7_INDEX, /* GPIO1 Pin 7 */
AM335X_PADCTL_UART0_CTSN_INDEX, /* GPIO1 Pin 8 */
AM335X_PADCTL_UART0_RTSN_INDEX, /* GPIO1 Pin 9 */
AM335X_PADCTL_UART0_RXD_INDEX, /* GPIO1 Pin 10 */
AM335X_PADCTL_UART0_TXD_INDEX, /* GPIO1 Pin 11 */
AM335X_PADCTL_GPMC_AD12_INDEX, /* GPIO1 Pin 12 */
AM335X_PADCTL_GPMC_AD13_INDEX, /* GPIO1 Pin 13 */
AM335X_PADCTL_GPMC_AD14_INDEX, /* GPIO1 Pin 14 */
AM335X_PADCTL_GPMC_AD15_INDEX, /* GPIO1 Pin 15 */
AM335X_PADCTL_GPMC_A0_INDEX, /* GPIO1 Pin 16 */
AM335X_PADCTL_GPMC_A1_INDEX, /* GPIO1 Pin 17 */
AM335X_PADCTL_GPMC_A2_INDEX, /* GPIO1 Pin 18 */
AM335X_PADCTL_GPMC_A3_INDEX, /* GPIO1 Pin 19 */
AM335X_PADCTL_GPMC_A4_INDEX, /* GPIO1 Pin 20 */
AM335X_PADCTL_GPMC_A5_INDEX, /* GPIO1 Pin 21 */
AM335X_PADCTL_GPMC_A6_INDEX, /* GPIO1 Pin 22 */
AM335X_PADCTL_GPMC_A7_INDEX, /* GPIO1 Pin 23 */
AM335X_PADCTL_GPMC_A8_INDEX, /* GPIO1 Pin 24 */
AM335X_PADCTL_GPMC_A9_INDEX, /* GPIO1 Pin 25 */
AM335X_PADCTL_GPMC_A10_INDEX, /* GPIO1 Pin 26 */
AM335X_PADCTL_GPMC_A11_INDEX, /* GPIO1 Pin 27 */
AM335X_PADCTL_GPMC_BEN1_INDEX, /* GPIO1 Pin 28 */
AM335X_PADCTL_GPMC_CSN0_INDEX, /* GPIO1 Pin 29 */
AM335X_PADCTL_GPMC_CSN1_INDEX, /* GPIO1 Pin 30 */
AM335X_PADCTL_GPMC_CSN2_INDEX, /* GPIO1 Pin 31 */
};
static const uint8_t g_gpio2_padctl[AM335X_GPIO_NPINS] =
{
AM335X_PADCTL_GPMC_CSN3_INDEX, /* GPIO2 Pin 0 */
AM335X_PADCTL_GPMC_CLK_INDEX, /* GPIO2 Pin 1 */
AM335X_PADCTL_GPMC_ADVN_ALE_INDEX, /* GPIO2 Pin 2 */
AM335X_PADCTL_GPMC_OEN_REN_INDEX, /* GPIO2 Pin 3 */
AM335X_PADCTL_GPMC_WEN_INDEX, /* GPIO2 Pin 4 */
AM335X_PADCTL_GPMC_BEN0_CLE_INDEX, /* GPIO2 Pin 5 */
AM335X_PADCTL_LCD_DATA0_INDEX, /* GPIO2 Pin 6 */
AM335X_PADCTL_LCD_DATA1_INDEX, /* GPIO2 Pin 7 */
AM335X_PADCTL_LCD_DATA2_INDEX, /* GPIO2 Pin 8 */
AM335X_PADCTL_LCD_DATA3_INDEX, /* GPIO2 Pin 9 */
AM335X_PADCTL_LCD_DATA4_INDEX, /* GPIO2 Pin 10 */
AM335X_PADCTL_LCD_DATA5_INDEX, /* GPIO2 Pin 11 */
AM335X_PADCTL_LCD_DATA6_INDEX, /* GPIO2 Pin 12 */
AM335X_PADCTL_LCD_DATA7_INDEX, /* GPIO2 Pin 13 */
AM335X_PADCTL_LCD_DATA8_INDEX, /* GPIO2 Pin 14 */
AM335X_PADCTL_LCD_DATA9_INDEX, /* GPIO2 Pin 15 */
AM335X_PADCTL_LCD_DATA10_INDEX, /* GPIO2 Pin 16 */
AM335X_PADCTL_LCD_DATA11_INDEX, /* GPIO2 Pin 17 */
AM335X_PADCTL_MII1_RXD3_INDEX, /* GPIO2 Pin 18 */
AM335X_PADCTL_MII1_RXD2_INDEX, /* GPIO2 Pin 19 */
AM335X_PADCTL_MII1_RXD1_INDEX, /* GPIO2 Pin 20 */
AM335X_PADCTL_MII1_RXD0_INDEX, /* GPIO2 Pin 21 */
AM335X_PADCTL_LCD_VSYNC_INDEX, /* GPIO2 Pin 22 */
AM335X_PADCTL_LCD_HSYNC_INDEX, /* GPIO2 Pin 23 */
AM335X_PADCTL_LCD_PCLK_INDEX, /* GPIO2 Pin 24 */
AM335X_PADCTL_LCD_AC_BIAS_EN_INDEX, /* GPIO2 Pin 25 */
AM335X_PADCTL_MMC0_DAT3_INDEX, /* GPIO2 Pin 26 */
AM335X_PADCTL_MMC0_DAT2_INDEX, /* GPIO2 Pin 27 */
AM335X_PADCTL_MMC0_DAT1_INDEX, /* GPIO2 Pin 28 */
AM335X_PADCTL_MMC0_DAT0_INDEX, /* GPIO2 Pin 29 */
AM335X_PADCTL_MMC0_CLK_INDEX, /* GPIO2 Pin 30 */
AM335X_PADCTL_MMC0_CMD_INDEX, /* GPIO2 Pin 31 */
};
static const uint8_t g_gpio3_padctl[AM335X_GPIO_NPINS] =
{
AM335X_PADCTL_MII1_COL_INDEX, /* GPIO3 Pin 0 */
AM335X_PADCTL_MII1_CRS_INDEX, /* GPIO3 Pin 1 */
AM335X_PADCTL_MII1_RX_ER_INDEX, /* GPIO3 Pin 2 */
AM335X_PADCTL_MII1_TX_EN_INDEX, /* GPIO3 Pin 3 */
AM335X_PADCTL_MII1_RX_DV_INDEX, /* GPIO3 Pin 4 */
AM335X_PADCTL_I2C0_SDA_INDEX, /* GPIO3 Pin 5 */
AM335X_PADCTL_I2C0_SCL_INDEX, /* GPIO3 Pin 6 */
AM335X_PADCTL_EMU0_INDEX, /* GPIO3 Pin 7 */
AM335X_PADCTL_EMU1_INDEX, /* GPIO3 Pin 8 */
AM335X_PADCTL_MII1_TX_CLK_INDEX, /* GPIO3 Pin 9 */
AM335X_PADCTL_MII1_RX_CLK_INDEX, /* GPIO3 Pin 10 */
AM335X_PADCTL_INVALID, /* GPIO3 Pin 11 */
AM335X_PADCTL_INVALID, /* GPIO3 Pin 12 */
AM335X_PADCTL_USB1_DRVVBUS_INDEX, /* GPIO3 Pin 13 */
AM335X_PADCTL_MCASP0_ACLKX_INDEX, /* GPIO3 Pin 14 */
AM335X_PADCTL_MCASP0_FSX_INDEX, /* GPIO3 Pin 15 */
AM335X_PADCTL_MCASP0_AXR0_INDEX, /* GPIO3 Pin 16 */
AM335X_PADCTL_MCASP0_AHCLKR_INDEX, /* GPIO3 Pin 17 */
AM335X_PADCTL_MCASP0_ACLKR_INDEX, /* GPIO3 Pin 18 */
AM335X_PADCTL_MCASP0_FSR_INDEX, /* GPIO3 Pin 19 */
AM335X_PADCTL_MCASP0_AXR1_INDEX, /* GPIO3 Pin 20 */
AM335X_PADCTL_MCASP0_AHCLKX_INDEX, /* GPIO3 Pin 21 */
AM335X_PADCTL_INVALID, /* GPIO3 Pin 22 */
AM335X_PADCTL_INVALID, /* GPIO3 Pin 23 */
AM335X_PADCTL_INVALID, /* GPIO3 Pin 24 */
AM335X_PADCTL_INVALID, /* GPIO3 Pin 25 */
AM335X_PADCTL_INVALID, /* GPIO3 Pin 26 */
AM335X_PADCTL_INVALID, /* GPIO3 Pin 27 */
AM335X_PADCTL_INVALID, /* GPIO3 Pin 28 */
AM335X_PADCTL_INVALID, /* GPIO3 Pin 29 */
AM335X_PADCTL_INVALID, /* GPIO3 Pin 30 */
AM335X_PADCTL_INVALID, /* GPIO3 Pin 31 */
};
static const uint8_t *g_gpio_padctl[AM335X_GPIO_NPORTS] =
{
g_gpio0_padctl, /* GPIO0 */
g_gpio1_padctl, /* GPIO1 */
g_gpio2_padctl, /* GPIO2 */
g_gpio3_padctl, /* GPIO3 */
};
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Name: am335x_gpio_dirout
****************************************************************************/
static inline void am335x_gpio_dirout(int port, int pin)
{
uint32_t regval = getreg32(AM335X_GPIO_OER(am335x_gpion_vbase(port)));
regval &= ~GPIO_PIN(pin);
putreg32(regval, AM335X_GPIO_OER(am335x_gpion_vbase(port)));
}
/****************************************************************************
* Name: am335x_gpio_dirin
****************************************************************************/
static inline void am335x_gpio_dirin(int port, int pin)
{
uint32_t regval = getreg32(AM335X_GPIO_OER(am335x_gpion_vbase(port)));
regval |= GPIO_PIN(pin);
putreg32(regval, AM335X_GPIO_OER(am335x_gpion_vbase(port)));
}
/****************************************************************************
* Name: am335x_gpio_setoutput
****************************************************************************/
static void am335x_gpio_setoutput(int port, int pin, bool value)
{
uint32_t regval = GPIO_PIN(pin);
putreg32(regval, value ? AM335X_GPIO_SDOR(am335x_gpion_vbase(port)) :
AM335X_GPIO_CDOR(am335x_gpion_vbase(port)));
}
/****************************************************************************
* Name: am335x_gpio_getinput
****************************************************************************/
static inline bool am335x_gpio_getinput(int port, int pin)
{
uint32_t regval = getreg32(AM335X_GPIO_DIR(am335x_gpion_vbase(port)));
return ((regval & GPIO_PIN(pin)) != 0);
}
/****************************************************************************
* Name: am335x_gpio_configinput
****************************************************************************/
static int am335x_gpio_configinput(gpio_pinset_t pinset)
{
int port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
int pin = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT;
pinmux_pinset_t muxset;
uintptr_t regaddr;
uint8_t index;
/* Configure pin as in input */
am335x_gpio_dirin(port, pin);
/* Configure pin interrupt levels */
am335x_gpioirq(pinset);
/* Configure pin as a GPIO */
index = g_gpio_padctl[port][pin];
if (index >= AM335X_PADCTL_NREGISTERS)
{
return -EINVAL;
}
/* Ensure that RX is enabled */
pinset |= PINMUX_MODE7 | PINMUX_RX_ENABLE;
/* Configure pin pad settings */
index = ((pinset & GPIO_PADCTL_MASK) >> GPIO_PADCTL_SHIFT);
regaddr = AM335X_PADCTL_ADDRESS(index);
muxset = (pinmux_pinset_t)((pinset & GPIO_PINMUX_MASK) >> GPIO_PINMUX_SHIFT);
return am335x_pinmux_configure(regaddr, muxset);
}
/****************************************************************************
* Name: am335x_gpio_configoutput
****************************************************************************/
static inline int am335x_gpio_configoutput(gpio_pinset_t pinset)
{
int port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
int pin = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT;
bool value = ((pinset & GPIO_OUTPUT_ONE) != 0);
/* Set the output value */
am335x_gpio_setoutput(port, pin, value);
/* Convert the configured input GPIO to an output */
am335x_gpio_dirout(port, pin);
return OK;
}
/****************************************************************************
* Name: am335x_gpio_configperiph
****************************************************************************/
static inline int am335x_gpio_configperiph(gpio_pinset_t pinset)
{
pinmux_pinset_t muxset;
uintptr_t regaddr;
unsigned int index;
/* Configure pin as a peripheral */
index = ((pinset & GPIO_PADCTL_MASK) >> GPIO_PADCTL_SHIFT);
regaddr = AM335X_PADCTL_ADDRESS(index);
muxset = (pinmux_pinset_t)((pinset & GPIO_PINMUX_MASK) >> GPIO_PINMUX_SHIFT);
return am335x_pinmux_configure(regaddr, muxset);
}
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: am335x_gpio_config
*
* Description:
* Configure a GPIO pin based on pin-encoded description of the pin.
*
****************************************************************************/
int am335x_gpio_config(gpio_pinset_t pinset)
{
irqstate_t flags;
int ret;
/* Configure the pin as an input initially to avoid any spurious outputs */
flags = enter_critical_section();
/* Configure based upon the pin mode */
switch (pinset & GPIO_MODE_MASK)
{
case GPIO_INPUT:
{
/* Configure the pin as a GPIO input */
ret = am335x_gpio_configinput(pinset);
}
break;
case GPIO_OUTPUT:
{
/* First configure the pin as a GPIO input to avoid output
* glitches.
*/
ret = am335x_gpio_configinput(pinset);
if (ret >= 0)
{
/* Convert the input to an output */
ret = am335x_gpio_configoutput(pinset);
}
}
break;
case GPIO_PERIPH:
{
/* Configure the pin as a peripheral */
ret = am335x_gpio_configperiph(pinset);
}
break;
default:
ret = -EINVAL;
break;
}
leave_critical_section(flags);
return ret;
}
/************************************************************************************
* Name: am335x_gpio_write
*
* Description:
* Write one or zero to the selected GPIO pin
*
************************************************************************************/
void am335x_gpio_write(gpio_pinset_t pinset, bool value)
{
irqstate_t flags;
int port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
int pin = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT;
flags = enter_critical_section();
am335x_gpio_setoutput(port, pin, value);
leave_critical_section(flags);
}
/************************************************************************************
* Name: am335x_gpio_read
*
* Description:
* Read one or zero from the selected GPIO pin
*
************************************************************************************/
bool am335x_gpio_read(gpio_pinset_t pinset)
{
irqstate_t flags;
int port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
int pin = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT;
bool value;
flags = enter_critical_section();
value = am335x_gpio_getinput(port, pin);
leave_critical_section(flags);
return value;
}

307
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/************************************************************************************
* arch/arm/src/am335x/am335x_gpio.h
*
* Copyright (C) 2018 Petro Karashchenko. All rights reserved.
* Author: Petro Karashchenko <petro.karashchneko@gmail.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_AM335X_AM335X_GPIO_H
#define __ARCH_ARM_SRC_AM335X_AM335X_GPIO_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <stdbool.h>
#include "chip/am335x_control.h"
#include "chip/am335x_gpio.h"
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* 32-bit Encoding:
*
* ENCODING IIXX XXXX XXXX XXXX XXXX XXXX MMMM MMMM
* GPIO INPUT 00.. RRRR .GGP PPPP .... .... MMMM MMMM
* GPIO OUTPUT 01V. .... .GGP PPPP .... .... MMMM MMMM
* PERIPHERAL 10.. .... CCCC CCCC .... .... MMMM MMMM
*/
/* Input/Output Selection:
*
* ENCODING II.. .... .... .... .... .... .... ....
*/
#define GPIO_MODE_SHIFT (30) /* Bits 30-31: Pin mode */
#define GPIO_MODE_MASK (3 << GPIO_MODE_SHIFT)
# define GPIO_INPUT (0 << GPIO_MODE_SHIFT) /* GPIO input */
# define GPIO_OUTPUT (1 << GPIO_MODE_SHIFT) /* GPIO output */
# define GPIO_PERIPH (2 << GPIO_MODE_SHIFT) /* Peripheral */
/* Interrupt Detection Modes:
*
* GPIO INPUT 00.. RRRR .GGP PPPP .... .... MMMM MMMM
*/
#define GPIO_INT_SHIFT (24) /* Bits 24-27: GPIO interrupt bits */
#define GPIO_INT_MASK (0xf << GPIO_INT_SHIFT)
# define GPIO_INT_NONE (0 << GPIO_INT_SHIFT)
# define GPIO_INT_RISING (1 << GPIO_INT_SHIFT)
# define GPIO_INT_FALLING (2 << GPIO_INT_SHIFT)
# define GPIO_INT_BOTHEDGES (GPIO_INT_RISING | GPIO_INT_FALLING)
# define GPIO_INT_HIGHLEVEL (4 << GPIO_INT_SHIFT)
# define GPIO_INT_LOWLEVEL (8 << GPIO_INT_SHIFT)
# define GPIO_INT_LEVELBOTH (GPIO_INT_HIGHLEVEL | GPIO_INT_LOWLEVEL)
/* Initial Output Value:
*
* GPIO OUTPUT 01V. .... .... .... .... .... .... ....
*/
#define GPIO_OUTPUT_ZERO (0) /* Bit 29: 0=Initial output is low */
#define GPIO_OUTPUT_ONE (1 << 29) /* Bit 29: 1=Initial output is high */
/* GPIO Port Number
*
* GPIO INPUT 00.. .... .GG. .... .... .... .... ....
* GPIO OUTPUT 01.. .... .GG. .... .... .... .... ....
*/
#define GPIO_PORT_SHIFT (21) /* Bits 21-22: GPIO port index */
#define GPIO_PORT_MASK (3 << GPIO_PORT_SHIFT)
# define GPIO_PORT0 (0 << GPIO_PORT_SHIFT) /* GPIO0 */
# define GPIO_PORT1 (1 << GPIO_PORT_SHIFT) /* GPIO1 */
# define GPIO_PORT2 (2 << GPIO_PORT_SHIFT) /* GPIO2 */
# define GPIO_PORT3 (3 << GPIO_PORT_SHIFT) /* GPIO3 */
/* GPIO Pin Number:
*
* GPIO INPUT 00.. .... ...P PPPP .... .... .... ....
* GPIO OUTPUT 01.. .... ...P PPPP .... .... .... ....
*/
#define GPIO_PIN_SHIFT (16) /* Bits 16-20: GPIO pin number */
#define GPIO_PIN_MASK (31 << GPIO_PIN_SHIFT)
# define GPIO_PIN0 (0 << GPIO_PIN_SHIFT) /* Pin 0 */
# define GPIO_PIN1 (1 << GPIO_PIN_SHIFT) /* Pin 1 */
# define GPIO_PIN2 (2 << GPIO_PIN_SHIFT) /* Pin 2 */
# define GPIO_PIN3 (3 << GPIO_PIN_SHIFT) /* Pin 3 */
# define GPIO_PIN4 (4 << GPIO_PIN_SHIFT) /* Pin 4 */
# define GPIO_PIN5 (5 << GPIO_PIN_SHIFT) /* Pin 5 */
# define GPIO_PIN6 (6 << GPIO_PIN_SHIFT) /* Pin 6 */
# define GPIO_PIN7 (7 << GPIO_PIN_SHIFT) /* Pin 7 */
# define GPIO_PIN8 (8 << GPIO_PIN_SHIFT) /* Pin 8 */
# define GPIO_PIN9 (9 << GPIO_PIN_SHIFT) /* Pin 9 */
# define GPIO_PIN10 (10 << GPIO_PIN_SHIFT) /* Pin 10 */
# define GPIO_PIN11 (11 << GPIO_PIN_SHIFT) /* Pin 11 */
# define GPIO_PIN12 (12 << GPIO_PIN_SHIFT) /* Pin 12 */
# define GPIO_PIN13 (13 << GPIO_PIN_SHIFT) /* Pin 13 */
# define GPIO_PIN14 (14 << GPIO_PIN_SHIFT) /* Pin 14 */
# define GPIO_PIN15 (15 << GPIO_PIN_SHIFT) /* Pin 15 */
# define GPIO_PIN16 (16 << GPIO_PIN_SHIFT) /* Pin 16 */
# define GPIO_PIN17 (17 << GPIO_PIN_SHIFT) /* Pin 17 */
# define GPIO_PIN18 (18 << GPIO_PIN_SHIFT) /* Pin 18 */
# define GPIO_PIN19 (19 << GPIO_PIN_SHIFT) /* Pin 19 */
# define GPIO_PIN20 (20 << GPIO_PIN_SHIFT) /* Pin 20 */
# define GPIO_PIN21 (21 << GPIO_PIN_SHIFT) /* Pin 21 */
# define GPIO_PIN22 (22 << GPIO_PIN_SHIFT) /* Pin 22 */
# define GPIO_PIN23 (23 << GPIO_PIN_SHIFT) /* Pin 23 */
# define GPIO_PIN24 (24 << GPIO_PIN_SHIFT) /* Pin 24 */
# define GPIO_PIN25 (25 << GPIO_PIN_SHIFT) /* Pin 25 */
# define GPIO_PIN26 (26 << GPIO_PIN_SHIFT) /* Pin 26 */
# define GPIO_PIN27 (27 << GPIO_PIN_SHIFT) /* Pin 27 */
# define GPIO_PIN28 (28 << GPIO_PIN_SHIFT) /* Pin 28 */
# define GPIO_PIN29 (29 << GPIO_PIN_SHIFT) /* Pin 29 */
# define GPIO_PIN30 (30 << GPIO_PIN_SHIFT) /* Pin 30 */
# define GPIO_PIN31 (31 << GPIO_PIN_SHIFT) /* Pin 31 */
/* Pad Control Register Index:
*
* PERIPHERAL 10.. .... CCCC CCCC .... .... MMMM MMMM
*/
#define GPIO_PADCTL_SHIFT (16) /* Bits 16-23: Peripheral control index */
#define GPIO_PADCTL_MASK (0xff << GPIO_PADCTL_SHIFT)
# define GPIO_PADCTL(n) ((uint32_t)(n) << GPIO_PADCTL_SHIFT)
/* Pin Mux Configuration:
*
* ENCODING .... .... .... .... .... .... MMMM MMMM
*
* See am335x_pinmux.h for detailed content.
*/
#define GPIO_PINMUX_SHIFT (0) /* Bits 0-8: PINMUX pin configuration */
#define GPIO_PINMUX_MASK (0xff << GPIO_PINMUX_SHIFT)
/************************************************************************************
* Public Types
************************************************************************************/
/* The smallest integer type that can hold the GPIO encoding */
typedef uint32_t gpio_pinset_t;
/************************************************************************************
* Public Data
************************************************************************************/
/************************************************************************************
* Inline Functions
************************************************************************************/
extern const uintptr_t g_gpiobase[AM335X_GPIO_NPORTS];
#define am335x_gpion_vbase(n) (g_gpiobase[(n)])
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/************************************************************************************
* Public Function Prototypes
************************************************************************************/
/************************************************************************************
* Name: am335x_gpioirq_initialize
*
* Description:
* Initialize logic to support a second level of interrupt decoding for GPIO pins.
*
************************************************************************************/
#ifdef CONFIG_AM335X_GPIO_IRQ
void am335x_gpioirq_initialize(void);
#else
# define am335x_gpio_irqinitialize()
#endif
/************************************************************************************
* Name: am335x_gpio_config
*
* Description:
* Configure a GPIO pin based on bit-encoded description of the pin.
*
************************************************************************************/
int am335x_gpio_config(gpio_pinset_t pinset);
/************************************************************************************
* Name: am335x_gpio_write
*
* Description:
* Write one or zero to the selected GPIO pin
*
************************************************************************************/
void am335x_gpio_write(gpio_pinset_t pinset, bool value);
/************************************************************************************
* Name: am335x_gpio_read
*
* Description:
* Read one or zero from the selected GPIO pin
*
************************************************************************************/
bool am335x_gpio_read(gpio_pinset_t pinset);
/************************************************************************************
* Name: am335x_gpioirq
*
* Description:
* Configure an interrupt for the specified GPIO pin.
*
************************************************************************************/
#ifdef CONFIG_AM335X_GPIO_IRQ
void am335x_gpioirq(gpio_pinset_t pinset);
#else
# define am335x_gpioirq(pinset)
#endif
/************************************************************************************
* Name: am335x_gpioirq_enable
*
* Description:
* Enable the interrupt for specified GPIO IRQ
*
************************************************************************************/
#ifdef CONFIG_AM335X_GPIO_IRQ
void am335x_gpioirq_enable(int irq);
#else
# define am335x_gpioirq_enable(irq)
#endif
/************************************************************************************
* Name: am335x_gpioirq_disable
*
* Description:
* Disable the interrupt for specified GPIO IRQ
*
************************************************************************************/
#ifdef CONFIG_AM335X_GPIO_IRQ
void am335x_gpioirq_disable(int irq);
#else
# define am335x_gpioirq_disable(irq)
#endif
/************************************************************************************
* Function: am335x_dump_gpio
*
* Description:
* Dump all GPIO registers associated with the base address of the provided pinset.
*
************************************************************************************/
#ifdef CONFIG_DEBUG_GPIO_INFO
int am335x_dump_gpio(uint32_t pinset, const char *msg);
#else
# define am335x_dump_gpio(p,m)
#endif
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ARCH_ARM_SRC_AM335X_AM335X_GPIO_H */

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/****************************************************************************
* arch/arm/src/am335x/am335x_gpioirq.c
*
* Copyright (C) 2018 Petro Karashchenko. All rights reserved.
* Author: Petro Karashchenko <petro.karashchenko@gmail.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <stdbool.h>
#include <errno.h>
#include <nuttx/irq.h>
#include "chip.h"
#include "up_arch.h"
#include "am335x_gpio.h"
#ifdef CONFIG_AM335X_GPIO_IRQ
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Name: am335x_gpio_risingedge
*
* Description:
* Set/clear rising edge detection.
*
****************************************************************************/
static void am335x_gpio_risingedge(gpio_pinset_t pinset)
{
int port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
int pin = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT;
uintptr_t regaddr = AM335X_GPIO_RDR(am335x_gpion_vbase(port));
uint32_t mask = GPIO_PIN(pin);
if ((pinset & GPIO_INT_MASK) == GPIO_INT_RISING)
{
modifyreg32(regaddr, 0, mask);
}
else
{
modifyreg32(regaddr, mask, 0);
}
}
/****************************************************************************
* Name: am335x_gpio_fallingedge
*
* Description:
* Set/clear falling edge detection.
*
****************************************************************************/
static void am335x_gpio_fallingedge(gpio_pinset_t pinset)
{
int port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
int pin = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT;
uintptr_t regaddr = AM335X_GPIO_FDR(am335x_gpion_vbase(port));
uint32_t mask = GPIO_PIN(pin);
if ((pinset & GPIO_INT_MASK) == GPIO_INT_FALLING)
{
modifyreg32(regaddr, 0, mask);
}
else
{
modifyreg32(regaddr, mask, 0);
}
}
/****************************************************************************
* Name: am335x_gpio_highlevel
*
* Description:
* Set/clear high level detection.
*
****************************************************************************/
static void am335x_gpio_highlevel(gpio_pinset_t pinset)
{
int port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
int pin = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT;
uintptr_t regaddr = AM335X_GPIO_LDR1(am335x_gpion_vbase(port));
uint32_t mask = PIO_PIN(pin);
if ((pinset & GPIO_INT_MASK) == GPIO_INT_HIGHLEVEL)
{
modifyreg32(regaddr, 0, mask);
}
else
{
modifyreg32(regaddr, mask, 0);
}
}
/****************************************************************************
* Name: am335x_gpio_lowlevel
*
* Description:
* Set/clear low level detection.
*
****************************************************************************/
static void am335x_gpio_lowlevel(gpio_pinset_t pinset)
{
int port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
int pin = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT;
uintptr_t regaddr = AM335X_GPIO_LDR0(am335x_gpion_vbase(port));
uint32_t mask = GPIO_PIN(pin);
if ((pinset & GPIO_INT_MASK) == GPIO_INT_LOWLEVEL
{
modifiyreg32(regaddr, 0, mask);
}
else
{
modifiyreg32(regaddr, mask, 0);
}
}
/****************************************************************************
* Name: am335x_gpio_interrupt
*
* Description:
* GPIO0/1/2/3 interrupt handler
*
****************************************************************************/
static int am335x_gpio_interrupt(uint32_t base, int irq0, void *context)
{
uint32_t isr;
uint32_t mask;
int pin;
/* Clear all pending interrupts */
isr = getreg32(AM335X_GPIO_ISR0(base));
putreg32(isr, AM335X_GPIO_ISR0(base));
/* Then process each pending GPIO interrupt */
for (pin = 0; (pin < AM335X_GPIO_NPINS) && (isr != 0); pin++)
{
mask = GPIO_PIN(pin);
if ((isr & mask) != 0)
{
/* Remove the pending interrupt bit from the mask */
isr &= ~mask;
/* Re-deliver the IRQ (recurses! We got here from irq_dispatch!) */
irq_dispatch(irq0 + pin, context);
}
}
return OK;
}
#ifdef CONFIG_AM335X_GPIO0_IRQ
static int am335x_gpio0_interrupt(int irq, FAR void *context, FAR void *arg)
{
return am335x_gpio_interrupt(AM335X_GPIO0_VADDR, AM335X_IRQ_GPIO0P0, context);
}
#endif
#ifdef CONFIG_AM335X_GPIO1_IRQ
static int am335x_gpio1_interrupt(int irq, FAR void *context, FAR void *arg)
{
return am335x_gpio_interrupt(AM335X_GPIO1_VADDR, AM335X_IRQ_GPIO1P0, context);
}
#endif
#ifdef CONFIG_AM335X_GPIO2_IRQ
static int am335x_gpio2_interrupt(int irq, FAR void *context, FAR void *arg)
{
return am335x_gpio_interrupt(AM335X_GPIO2_VADDR, AM335X_IRQ_GPIO2P0, context);
}
#endif
#ifdef CONFIG_AM335X_GPIO3_IRQ
static int am335x_gpio3_interrupt(int irq, FAR void *context, FAR void *arg)
{
return am335x_gpio_interrupt(AM335X_GPIO3_VADDR, AM335X_IRQ_GPIO3P0, context);
}
#endif
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: am335x_gpio_irqinitialize
*
* Description:
* Initialize logic to support a second level of interrupt decoding for
* GPIO pins.
*
****************************************************************************/
void am335x_gpio_irqinitialize(void)
{
/* Configure GPIO0 interrupts */
#ifdef CONFIG_AM335X_GPIO0_IRQ
/* Enable GPIO0 clocking */
//am335x_gpio0_enableclk();
/* Clear and disable all GPIO0 interrupts */
putreg32(0xffffffff, AM335X_GPIO_ISCR0(AM335X_GPIO0_VADDR));
putreg32(0xffffffff, AM335X_GPIO_ISR0(AM335X_GPIO0_VADDR));
/* Disable all event detections */
putreg32(0, AM335X_GPIO_LDR0(AM335X_GPIO0_VADDR));
putreg32(0, AM335X_GPIO_LDR1(AM335X_GPIO0_VADDR));
putreg32(0, AM335X_GPIO_RDR(AM335X_GPIO0_VADDR));
putreg32(0, AM335X_GPIO_FDR(AM335X_GPIO0_VADDR));
/* Attach and enable the GPIO0 IRQ */
(void)irq_attach(AM335X_IRQ_GPIO0A, am335x_gpio0_interrupt, NULL);
up_enable_irq(AM335X_IRQ_GPIO0A);
#endif
/* Configure GPIO1 interrupts */
#ifdef CONFIG_AM335X_GPIO1_IRQ
/* Enable GPIO1 clocking */
//am335x_gpio1_enableclk();
/* Clear and disable all GPIO1 interrupts */
putreg32(0xffffffff, AM335X_GPIO_ISCR0(AM335X_GPIO1_VADDR));
putreg32(0xffffffff, AM335X_GPIO_ISR0(AM335X_GPIO1_VADDR));
/* Disable all event detections */
putreg32(0, AM335X_GPIO_LDR0(AM335X_GPIO1_VADDR));
putreg32(0, AM335X_GPIO_LDR1(AM335X_GPIO1_VADDR));
putreg32(0, AM335X_GPIO_RDR(AM335X_GPIO1_VADDR));
putreg32(0, AM335X_GPIO_FDR(AM335X_GPIO1_VADDR));
/* Attach and enable the GPIO1 IRQ */
(void)irq_attach(AM335X_IRQ_GPIO1A, am335x_gpio1_interrupt, NULL);
up_enable_irq(AM335X_IRQ_GPIO1A);
#endif
/* Configure GPIO2 interrupts */
#ifdef CONFIG_AM335X_GPIO2_IRQ
/* Enable GPIO2 clocking */
//am335x_gpio2_enableclk();
/* Clear and disable all GPIO2 interrupts */
putreg32(0xffffffff, AM335X_GPIO_ISCR0(AM335X_GPIO2_VADDR));
putreg32(0xffffffff, AM335X_GPIO_ISR0(AM335X_GPIO2_VADDR));
/* Disable all event detections */
putreg32(0, AM335X_GPIO_LDR0(AM335X_GPIO2_VADDR));
putreg32(0, AM335X_GPIO_LDR1(AM335X_GPIO2_VADDR));
putreg32(0, AM335X_GPIO_RDR(AM335X_GPIO2_VADDR));
putreg32(0, AM335X_GPIO_FDR(AM335X_GPIO2_VADDR));
/* Attach and enable the GPIO2 IRQ */
(void)irq_attach(AM335X_IRQ_GPIO2A, am335x_gpio2_interrupt, NULL);
up_enable_irq(AM335X_IRQ_GPIO2A);
#endif
/* Configure GPIO3 interrupts */
#ifdef CONFIG_AM335X_GPIO3_IRQ
/* Enable GPIO3 clocking */
//am335x_gpio3_enableclk();
/* Clear and disable all GPIO3 interrupts */
putreg32(0xffffffff, AM335X_GPIO_ISCR0(AM335X_GPIO3_VADDR));
putreg32(0xffffffff, AM335X_GPIO_ISR0(AM335X_GPIO3_VADDR));
/* Disable all event detections */
putreg32(0, AM335X_GPIO_LDR0(AM335X_GPIO3_VADDR));
putreg32(0, AM335X_GPIO_LDR1(AM335X_GPIO3_VADDR));
putreg32(0, AM335X_GPIO_RDR(AM335X_GPIO3_VADDR));
putreg32(0, AM335X_GPIO_FDR(AM335X_GPIO3_VADDR));
/* Attach and enable the GPIO3 IRQ */
(void)irq_attach(AM335X_IRQ_GPIO3A, am335x_gpio3_interrupt, NULL);
up_enable_irq(AM335X_IRQ_GPIO3A);
#endif
}
/****************************************************************************
* Name: am335x_gpioirq
*
* Description:
* Configure interrupt event detection for the specified GPIO pin.
*
****************************************************************************/
void am335x_gpioirq(gpio_pinset_t pinset)
{
/* Configure pin detection settings */
am335x_gpio_risingedge(pinset);
am335x_gpio_fallingedge(pinset);
am335x_gpio_highlevel(pinset);
am335x_gpio_lowlevel(pinset);
}
/************************************************************************************
* Name: am335x_gpio_irqenable
*
* Description:
* Enable generation of interrupt from GPIO pin
*
************************************************************************************/
void am335x_gpio_irqenable(gpio_pinset_t pinset);
{
int port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
int pin = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT;
/* Clear and enable GPIO pin interrupt */
putreg32(GPIO_PIN(pin), AM335X_GPIO_ISR0(am335x_gpion_vbase(port)));
putreg32(GPIO_PIN(pin), AM335X_GPIO_ISSR0(am335x_gpion_vbase(port)));
}
/************************************************************************************
* Name: am335x_gpio_irqdisable
*
* Description:
* Disable generation of interrupt from GPIO pin
*
************************************************************************************/
void am335x_gpio_irqdisable(gpio_pinset_t pinset);
{
int port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
int pin = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT;
/* Disable GPIO pin interrupt */
putreg32(GPIO_PIN(pin), AM335X_GPIO_ISCR0(am335x_gpion_vbase(port)));
}
#endif /* CONFIG_AM335X_GPIO_IRQ */

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/****************************************************************************
* arch/arm/src/am335x/am335x_irq.c
*
* Copyright (C) 2018 Petro Karashchenko. All rights reserved.
* Author: Petro Karashchenko <petro.karashchenko@gmail.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <assert.h>
#include <nuttx/arch.h>
#include "up_arch.h"
#include "up_internal.h"
#include "sctlr.h"
#include "am335x_gpio.h"
#include "am335x_irq.h"
/****************************************************************************
* Public Data
****************************************************************************/
/* g_current_regs[] holds a references to the current interrupt level
* register storage structure. If is non-NULL only during interrupt
* processing. Access to g_current_regs[] must be through the macro
* CURRENT_REGS for portability.
*/
volatile uint32_t *g_current_regs[1];
/* Symbols defined via the linker script */
extern uint32_t _vector_start; /* Beginning of vector block */
extern uint32_t _vector_end; /* End+1 of vector block */
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: up_irqinitialize
*
* Description:
* This function is called by up_initialize() during the bring-up of the
* system. It is the responsibility of this function to but the interrupt
* subsystem into the working and ready state.
*
****************************************************************************/
void up_irqinitialize(void)
{
int i;
#ifdef CONFIG_ARCH_LOWVECTORS
/* If CONFIG_ARCH_LOWVECTORS is defined, then the vectors located at the
* beginning of the .text region must appear at address at the address
* specified in the VBAR. There are two ways to accomplish this:
*
* 1. By explicitly mapping the beginning of .text region with a page
* table entry so that the virtual address zero maps to the beginning
* of the .text region. VBAR == 0x0000:0000.
*
* 2. Set the Cortex-A8 VBAR register so that the vector table address
* is moved to a location other than 0x0000:0000.
*
* The second method is used by this logic.
*/
/* Set the VBAR register to the address of the vector table */
DEBUGASSERT((((uintptr_t)&_vector_start) & ~VBAR_MASK) == 0);
cp15_wrvbar((uint32_t)&_vector_start);
#endif /* CONFIG_ARCH_LOWVECTORS */
/* The following operations need to be atomic, but since this function is
* called early in the initialization sequence, we expect to have exclusive
* access to the INTC.
*/
/* Reset the ARM interrupt controller */
putreg32(INTC_SYSCONFIG_SOFTRESET, AM335X_INTC_SYSCONFIG);
/* Wait for the reset to complete */
while ((getreg32(AM335X_INTC_SYSSTATUS) & INTC_SYSSTATUS_RESETDONE) !=
INTC_SYSSTATUS_RESETDONE)
{
}
/* Enable any interrupt generation by setting priority threshold */
putreg32(INTC_THRESHOLD_DISABLE, AM335X_INTC_THRESHOLD);
/* Disable, mask, and clear all interrupts */
for (i = 0; i < AM335X_IRQ_NINT; i += 32)
{
putreg32(0xffffffff, AM335X_INTC_MIR_SET(i)); /* 1 masks corresponding interrupt */
(void)getreg32(AM335X_INTC_PEND_IRQ(i)); /* Reading status clears pending interrupts */
(void)getreg32(AM335X_INTC_PEND_FIQ(i)); /* Reading status clears pending interrupts */
}
/* currents_regs is non-NULL only while processing an interrupt */
CURRENT_REGS = NULL;
#ifndef CONFIG_SUPPRESS_INTERRUPTS
/* Initialize logic to support a second level of interrupt decoding for
* GPIO pins.
*/
#ifdef CONFIG_AM335X_GPIO_IRQ
am335x_gpio_irqinitialize();
#endif
/* And finally, enable interrupts */
(void)up_irq_enable();
#endif
}
/****************************************************************************
* Name: arm_decodeirq
*
* Description:
* This function is called from the IRQ vector handler in arm_vectors.S.
* At this point, the interrupt has been taken and the registers have
* been saved on the stack. This function simply needs to determine the
* the irq number of the interrupt and then to call arm_doirq to dispatch
* the interrupt.
*
* Input parameters:
* regs - A pointer to the register save area on the stack.
*
****************************************************************************/
uint32_t *arm_decodeirq(uint32_t *regs)
{
#if 1 /* Use PEND registers instead */
uint32_t regval;
regval = getreg32(AM335X_INTC_SIR_IRQ) & INTC_SIR_IRQ_ACTIVE_MASK;
/* Dispatch the interrupt */
return arm_doirq((int)regval, regs);
#else
uintptr_t regaddr;
uint32_t pending;
int startirq;
int lastirq;
int irq;
#if 0
/* Check each PEND register for pending interrupts. Since the unused
* interrupts are disabled, we do not have to be concerned about which
* are MASKed.
*/
for (startirq = 0, regaddr = AM335X_INTC_IRQ_PEND0;
startirq < AM335X_IRQ_NINT;
startirq += 32, regaddr += 4)
{
/* Check this register for pending interrupts */
pending = getreg32(regaddr);
if (pending != 0)
{
/* The last interrupt in this register */
lastirq = startirq + 32;
if (lastirq > AM335X_IRQ_NINT)
{
lastirq = AM335X_IRQ_NINT;
}
for (irq = startirq; irq < lastirq && pending != 0; )
{
/* Check for pending interrupts in any of the lower 16-bits */
if ((pending & 0x0000ffff) == 0)
{
irq += 16;
pending >>= 16;
}
/* Check for pending interrupts in any of the lower 16-bits */
else if ((pending & 0x000000ff) == 0)
{
irq += 8;
pending >>= 8;
}
/* Check for pending interrupts in any of the lower 4-bits */
else if ((pending & 0x0000000f) == 0)
{
irq += 4;
pending >>= 4;
}
/* Check for pending interrupts in any of the lower 2-bits */
else if ((pending & 0x00000003) == 0)
{
irq += 2;
pending >>= 2;
}
/* Check for pending interrupts in any of the last bits */
else
{
if ((pending & 0x00000001) != 0)
{
/* Yes.. dispatch the interrupt */
regs = arm_doirq(irq, regs);
}
irq++;
pending >>= 1;
}
}
}
}
#endif
return regs;
#endif
}
/****************************************************************************
* Name: up_disable_irq
*
* Description:
* Disable the IRQ specified by 'irq'
*
****************************************************************************/
void up_disable_irq(int irq)
{
if (irq < AM335X_IRQ_NINT)
{
//__asm__ __volatile__ ("\tdsb");
/* Disable interrupt on INTC */
//putreg32(INTC_MIR_SET(irq), AM335X_INTC_MIR_SET(irq));
}
#ifdef CONFIG_AM335X_GPIO_IRQ
else
{
/* Maybe it is a (derived) GPIO IRQ */
am335x_gpioirq_disable(irq);
}
#endif
}
/****************************************************************************
* Name: up_enable_irq
*
* Description:
* Enable the IRQ specified by 'irq'
*
****************************************************************************/
void up_enable_irq(int irq)
{
if (irq < AM335X_IRQ_NINT)
{
//__asm__ __volatile__ ("\tdsb");
/* Enable interrupt on INTC */
//putreg32(INTC_MIR_CLEAR(irq), AM335X_INTC_MIR_CLEAR(irq));
}
#ifdef CONFIG_AM335X_GPIO_IRQ
else
{
/* Maybe it is a (derived) GPIO IRQ */
am335x_gpioirq_enable(irq);
}
#endif
}
/****************************************************************************
* Name: up_prioritize_irq
*
* Description:
* Set the priority of an IRQ.
*
* Since this API is not supported on all architectures, it should be
* avoided in common implementations where possible.
*
****************************************************************************/
#ifdef CONFIG_ARCH_IRQPRIO
int up_prioritize_irq(int irq, int priority)
{
irqstate_t flags;
uintptr_t regaddr;
uint32_t regval;
DEBUGASSERT(irq < AM335X_IRQ_NINT && (unsigned)priority <= INTC_PRIO_MAX);
if (irq < AM335X_IRQ_NINT)
{
/* These operations must be atomic */
flags = enter_critical_section();
#if 0 // TODO
/* Set the new priority */
regaddr = A1X_INTC_PRIO_OFFSET(irq);
regval = getreg32(regaddr);
regval &= ~INTC_PRIO_MASK(irq);
regval |= INTC_PRIO(irq, priority);
putreg32(regval, regaddr);
#endif
leave_critical_section(flags);
return OK;
}
return -EINVAL;
}
#endif

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/****************************************************************************
* arch/arm/src/am335x/am335x_irq.h
*
* Copyright (C) 2018 Petro Karashchenko. All rights reserved.
* Author: Petro Karashchenko <petro.karashchenko@gmail.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_AM335X_AM335X_IRQ_H
#define __ARCH_ARM_SRC_AM335X_AM335X_IRQ_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "chip/am335x_intc.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Public Types
****************************************************************************/
/****************************************************************************
* Inline Functions
****************************************************************************/
#ifndef __ASSEMBLY__
/****************************************************************************
* Public Data
****************************************************************************/
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_SRC_AM335X_AM335X_IRQ_H */

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/****************************************************************************
* arch/arm/src/am335x/am335x_lowputc.c
*
* Copyright (C) 2018 Petro Karashchenko. All rights reserved.
* Author: Petro Karashchenko <petro.karashchneko@gmail.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <arch/irq.h>
#include <arch/board/board.h>
#include "up_internal.h"
#include "up_arch.h"
#include "am335x_config.h"
#include "am335x_gpio.h"
#include "am335x_pinmux.h"
#include "chip/am335x_uart.h"
/**************************************************************************
* Pre-processor Definitions
**************************************************************************/
/* Select UART parameters for the selected console */
#if defined(CONFIG_UART0_SERIAL_CONSOLE)
# define CONSOLE_BASE AM335X_UART0_VADDR
# define CONSOLE_BAUD CONFIG_UART0_BAUD
# define CONSOLE_BITS CONFIG_UART0_BITS
# define CONSOLE_PARITY CONFIG_UART0_PARITY
# define CONSOLE_2STOP CONFIG_UART0_2STOP
#elif defined(CONFIG_UART1_SERIAL_CONSOLE)
# define CONSOLE_BASE AM335X_UART1_VADDR
# define CONSOLE_BAUD CONFIG_UART1_BAUD
# define CONSOLE_BITS CONFIG_UART1_BITS
# define CONSOLE_PARITY CONFIG_UART1_PARITY
# define CONSOLE_2STOP CONFIG_UART1_2STOP
#elif defined(CONFIG_UART2_SERIAL_CONSOLE)
# define CONSOLE_BASE AM335X_UART2_VADDR
# define CONSOLE_BAUD CONFIG_UART2_BAUD
# define CONSOLE_BITS CONFIG_UART2_BITS
# define CONSOLE_PARITY CONFIG_UART2_PARITY
# define CONSOLE_2STOP CONFIG_UART2_2STOP
#elif defined(CONFIG_UART3_SERIAL_CONSOLE)
# define CONSOLE_BASE AM335X_UART3_VADDR
# define CONSOLE_BAUD CONFIG_UART3_BAUD
# define CONSOLE_BITS CONFIG_UART3_BITS
# define CONSOLE_PARITY CONFIG_UART3_PARITY
# define CONSOLE_2STOP CONFIG_UART3_2STOP
#elif defined(CONFIG_UART4_SERIAL_CONSOLE)
# define CONSOLE_BASE AM335X_UART4_VADDR
# define CONSOLE_BAUD CONFIG_UART4_BAUD
# define CONSOLE_BITS CONFIG_UART4_BITS
# define CONSOLE_PARITY CONFIG_UART4_PARITY
# define CONSOLE_2STOP CONFIG_UART4_2STOP
#elif defined(CONFIG_UART5_SERIAL_CONSOLE)
# define CONSOLE_BASE AM335X_UART5_VADDR
# define CONSOLE_BAUD CONFIG_UART5_BAUD
# define CONSOLE_BITS CONFIG_UART5_BITS
# define CONSOLE_PARITY CONFIG_UART5_PARITY
# define CONSOLE_2STOP CONFIG_UART5_2STOP
#elif defined(HAVE_SERIAL_CONSOLE)
# error "No CONFIG_UARTn_SERIAL_CONSOLE Setting"
#endif
/* Get word length setting for the console */
#if CONSOLE_BITS == 5
# define CONSOLE_LCR_DLS UART_LCR_DLS_5BITS
#elif CONSOLE_BITS == 6
# define CONSOLE_LCR_DLS UART_LCR_DLS_6BITS
#elif CONSOLE_BITS == 7
# define CONSOLE_LCR_DLS UART_LCR_DLS_7BITS
#elif CONSOLE_BITS == 8
# define CONSOLE_LCR_DLS UART_LCR_DLS_8BITS
#elif defined(HAVE_SERIAL_CONSOLE)
# error "Invalid CONFIG_UARTn_BITS setting for console "
#endif
/* Get parity setting for the console */
#if CONSOLE_PARITY == 0
# define CONSOLE_LCR_PAR UART_LCR_PARITY_NONE
#elif CONSOLE_PARITY == 1
# define CONSOLE_LCR_PAR UART_LCR_PARITY_ODD
#elif CONSOLE_PARITY == 2
# define CONSOLE_LCR_PAR UART_LCR_PARITY_EVEN
#elif CONSOLE_PARITY == 3
#elif defined(HAVE_SERIAL_CONSOLE)
# error "Invalid CONFIG_UARTn_PARITY setting for CONSOLE"
#endif
/* Get stop-bit setting for the console and UART0-3 */
#if CONSOLE_2STOP != 0
# define CONSOLE_LCR_STOP UART_LCR_STOP_2BITS
#else
# define CONSOLE_LCR_STOP UART_LCR_STOP_1BITS
#endif
/* LCR and FCR values for the console */
#define CONSOLE_LCR_VALUE (CONSOLE_LCR_DLS | CONSOLE_LCR_PAR | \
CONSOLE_LCR_STOP)
#define CONSOLE_FCR_VALUE (UART_FCR_FIFO_EN | UART_FCR_RFT_60CHAR | \
UART_FCR_TFT_56CHAR)
/* SCLK is the UART input clock.
*
* Through experimentation, it has been found that the serial clock is
* OSC24M
*/
#define AM335X_SCLK 48000000
/* The output baud rate is equal to the serial clock (SCLK) frequency divided
* by sixteen times the value of the baud rate divisor, as follows:
*
* baud rate = Fsclk / (16 * divisor).
*/
#define CONSOLE_DL (AM335X_SCLK / (CONSOLE_BAUD << 4))
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: up_lowputc
*
* Description:
* Output one byte on the serial console
*
****************************************************************************/
void up_lowputc(char ch)
{
#if defined(HAVE_UART_DEVICE) && defined(HAVE_SERIAL_CONSOLE)
/* Wait for the transmitter to be available */
while ((getreg32(CONSOLE_BASE+AM335X_UART_LSR_OFFSET) & UART_LSR_THRE) == 0);
/* Send the character */
putreg32((uint32_t)ch, CONSOLE_BASE+AM335X_UART_THR_OFFSET);
while ((getreg32(CONSOLE_BASE+AM335X_UART_LSR_OFFSET) & UART_LSR_THRE) == 0);
#endif
}
/****************************************************************************
* Name: am335x_lowsetup
*
* Description:
* This performs basic initialization of the UART used for the serial
* console. Its purpose is to get the console output available as soon
* as possible.
*
****************************************************************************/
void am335x_lowsetup(void)
{
#ifdef HAVE_UART_DEVICE
/* Enable power and clocking to the UART peripheral */
#warning Missing logic
/* Configure UART pins for the selected CONSOLE. If there are multiple
* pin options for a given UART, the the applicable option must be
* disambiguated in the board.h header file.
*/
#if defined(CONFIG_UART0_SERIAL_CONSOLE)
am335x_gpio_config(GPIO_UART0_TXD);
am335x_gpio_config(GPIO_UART0_RXD);
#elif defined(CONFIG_UART1_SERIAL_CONSOLE)
am335x_gpio_config(GPIO_UART1_TXD);
am335x_gpio_config(GPIO_UART1_RXD);
#elif defined(CONFIG_UART2_SERIAL_CONSOLE)
am335x_gpio_config(GPIO_UART2_TXD);
am335x_gpio_config(GPIO_UART2_RXD);
#elif defined(CONFIG_UART3_SERIAL_CONSOLE)
am335x_gpio_config(GPIO_UART3_TXD);
am335x_gpio_config(GPIO_UART3_RXD);
#elif defined(CONFIG_UART4_SERIAL_CONSOLE)
am335x_gpio_config(GPIO_UART4_TXD);
am335x_gpio_config(GPIO_UART4_RXD);
#elif defined(CONFIG_UART5_SERIAL_CONSOLE)
am335x_gpio_config(GPIO_UART5_TXD);
am335x_gpio_config(GPIO_UART5_RXD);
#endif
/* Configure the console (only) */
#if defined(HAVE_SERIAL_CONSOLE) && !defined(CONFIG_SUPPRESS_UART_CONFIG)
#if 0
/* Performing Software Reset of the module. */
putreg32(UART_SYSC_SRESET | getreg32(CONSOLE_BASE + AM335X_UART_SYSC_OFFSET),
CONSOLE_BASE + AM335X_UART_SYSC_OFFSET);
#endif
/* Wait until the process of Module Reset is complete. */
//while(!(getreg32(CONSOLE_BASE + AM335X_UART_SYSS_OFFSET) & 1));
/* Put UART to disabled mode */
putreg32(UART_MDR1_MODE_DISABLE, CONSOLE_BASE + AM335X_UART_MDR1_OFFSET);
/* Enter configuration mode and enable access to Latch Divisor DLAB=1 */
putreg32(UART_LCR_CONFIG_MODE_B, CONSOLE_BASE + AM335X_UART_LCR_OFFSET);
/* Set Divisor values to zero to be able to write FCR correctly */
putreg32(0, CONSOLE_BASE + AM335X_UART_DLH_OFFSET);
putreg32(0, CONSOLE_BASE + AM335X_UART_DLL_OFFSET);
/* Enable writing FCR[5:4] */
putreg32(UART_EFR_ENHANCEDEN, CONSOLE_BASE + AM335X_UART_EFR_OFFSET);
/* Exit configuration mode and enable access to Latch Divisor DLAB=1 */
putreg32(UART_LCR_CONFIG_MODE_A, CONSOLE_BASE + AM335X_UART_LCR_OFFSET);
/* Clear FIFOs */
putreg32(UART_FCR_RFIFO_CLEAR | UART_FCR_TFIFO_CLEAR, CONSOLE_BASE + AM335X_UART_FCR_OFFSET);
/* Configure the FIFOs */
putreg32(CONSOLE_FCR_VALUE, CONSOLE_BASE + AM335X_UART_FCR_OFFSET);
/* Set the BAUD divisor */
putreg32((CONSOLE_DL >> 8) & UART_DLH_MASK, CONSOLE_BASE + AM335X_UART_DLH_OFFSET);
putreg32(CONSOLE_DL & UART_DLL_MASK, CONSOLE_BASE + AM335X_UART_DLL_OFFSET);
/* Clear DLAB */
putreg32(CONSOLE_LCR_VALUE, CONSOLE_BASE + AM335X_UART_LCR_OFFSET);
/* Enable Auto-Flow Control in the Modem Control Register */
#if defined(CONFIG_SERIAL_IFLOWCONTROL) || defined(CONFIG_SERIAL_OFLOWCONTROL)
# warning Missing logic
#endif
putreg32(UART_MDR1_MODE_16x, CONSOLE_BASE + AM335X_UART_MDR1_OFFSET);
#endif
#endif /* HAVE_UART_DEVICE */
}

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/****************************************************************************
* arch/arm/src/am335x/am335x_lowputc.h
*
* Copyright (C) 2018 Petro Karashchenko. All rights reserved.
* Author: Petro Karashchenko <petro.karashchneko@gmail.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_AM335X_AM335X_LOWPUTC_H
#define __ARCH_ARM_SRC_AM335X_AM335X_LOWPUTC_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Public Types
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
#ifndef __ASSEMBLY__
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: am335x_lowsetup
*
* Description:
* Called at the very beginning of _start. Performs low level
* initialization including setup of the console UART. This UART done
* early so that the serial console is available for debugging very early
* in the boot sequence.
*
****************************************************************************/
void am335x_lowsetup(void);
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_SRC_AM335X_AM335X_LOWPUTC_H */

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/****************************************************************************
* arch/arm/src/am335x/am335x_pinmux.c
*
* Copyright (C) 2018 Petro Karashchenko. All rights reserved.
* Author: Petro Karashchenko <petro.karashchneko@gmail.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <sys/types.h>
#include <stdint.h>
#include <assert.h>
#include <errno.h>
#include "up_arch.h"
#include "am335x_pinmux.h"
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: am335x_pinmux_configure
*
* Description:
* This function writes the encoded pad configuration to the Pad Control
* register.
*
****************************************************************************/
int am335x_pinmux_configure(uintptr_t padctl, pinmux_pinset_t muxset)
{
uint32_t regval = 0;
uint32_t value;
/* Select mux mode */
value = (muxset & PINMUX_MODE_MASK) >> PINMUX_MODE_SHIFT;
regval |= PADCTL_MUXMODE(value);
/* Select pull up/down type */
if ((muxset & PINMUX_PULL_TYPE_UP) != 0)
{
regval |= PADCTL_PULLUP_EN;
}
/* Select pull up/down enable */
if ((muxset & PINMUX_PULL_UP_DISABLE) != 0)
{
regval |= PADCTL_PULLUDDIS;
}
/* Select receive enable */
if ((muxset & PINMUX_RX_ENABLE) != 0)
{
regval |= PADCTL_RXACTIVE;
}
/* Select slow/fast slew rate */
if ((muxset & PINMUX_SLEW_SLOW) != 0)
{
regval |= PADCTL_SLEWCTRL;
}
/* Write the result to the specified Pad Control register */
putreg32(regval, padctl);
return OK;
}

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/****************************************************************************
* arch/arm/src/am335x/am335x_pinmux.h
*
* Copyright (C) 2018 Petro Karashchenko. All rights reserved.
* Author: Petro Karashchenko <petro.karashchenko@gmail.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_AM335X_AM335X_PINMUX_H
#define __ARCH_ARM_SRC_AM335X_AM335X_PINMUX_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "chip/am335x_control.h"
#include "chip/am335x_pinmux.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* 8-bit Encoding:
*
* .SRT PMMM
*/
/* Select Between Faster or Slower Slew Rate:
*
* .S.. ....
*/
#define PINMUX_SLEW_FAST (0) /* Bit 6: 0=Fast Slew Rate */
#define PINMUX_SLEW_SLOW (1 << 6) /* Bit 6: 1=Slow Slew Rate */
/* Input Enable Value for the Pad. Set to 1 for Input or Output:
*
* ..R. ....
*/
#define PINMUX_RX_DISABLE (0) /* Bit 5: 0=Receiver Disabled */
#define PINMUX_RX_ENABLE (1 << 5) /* Bit 5: 1=Receiver Enabled */
/* Pad Pull Up/Down Type Selection:
*
* ...T ....
*/
#define PINMUX_PULL_TYPE_DOWN (0) /* Bit 4: 0=Pull Down Selected */
#define PINMUX_PULL_TYPE_UP (1 << 4) /* Bit 4: 1=Pull Up Selected */
/* Pad Pull Up/Down Enable:
*
* .... P...
*/
#define PINMUX_PULL_UP_ENABLE (0) /* Bit 3: 0=Pull Up/Down Enabled */
#define PINMUX_PULL_UP_DISABLE (1 << 3) /* Bit 3: 1=Pull Up/Down Disabled */
/* Pin Multiplexing Mode:
*
* .... .MMM
*/
#define PINMUX_MODE_SHIFT (0) /* Bits 0-2: Pin Multiplexing Mode */
#define PINMUX_MODE_MASK (7 << PINMUX_MODE_SHIFT)
# define PINMUX_MODE0 (0 << PINMUX_MODE_SHIFT) /* Mode 0 = Primary Mode */
# define PINMUX_MODE1 (1 << PINMUX_MODE_SHIFT) /* Mode 1 */
# define PINMUX_MODE2 (2 << PINMUX_MODE_SHIFT) /* Mode 2 */
# define PINMUX_MODE3 (3 << PINMUX_MODE_SHIFT) /* Mode 3 */
# define PINMUX_MODE4 (4 << PINMUX_MODE_SHIFT) /* Mode 4 */
# define PINMUX_MODE5 (5 << PINMUX_MODE_SHIFT) /* Mode 5 */
# define PINMUX_MODE6 (6 << PINMUX_MODE_SHIFT) /* Mode 6 */
# define PINMUX_MODE7 (7 << PINMUX_MODE_SHIFT) /* Mode 7 */
/****************************************************************************
* Public Types
****************************************************************************/
#ifndef __ASSEMBLY__
#include <stdint.h>
/* The smallest integer type that can hold the PINMUX encoding */
typedef uint8_t pinmux_pinset_t;
/****************************************************************************
* Public Data
****************************************************************************/
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: am335x_pinmux_configure
*
* Description:
* This function writes the encoded pad configuration to the Pad Control
* register.
*
****************************************************************************/
int am335x_pinmux_configure(uintptr_t padctl, pinmux_pinset_t muxset);
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_SRC_AM335X_AM335X_PINMUX_H */

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/************************************************************************************
* arch/arm/src/am335x/am335x_serial.h
*
* Copyright (C) 2018 Petro Karashchenko. All rights reserved.
* Author: Petro Karashchenko <petro.karashchneko@gmail.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_AM335X_AM335X_SERIAL_H
#define __ARCH_ARM_SRC_AM335X_AM335X_SERIAL_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
#include <arch/board/board.h>
#include "chip/am335x_uart.h"
#include "am335x_config.h"
#include "chip/am335x_gpio.h"
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/************************************************************************************
* Public Types
************************************************************************************/
/************************************************************************************
* Public Data
************************************************************************************/
/************************************************************************************
* Inline Functions
************************************************************************************/
/************************************************************************************
* Public Functions
************************************************************************************/
#endif /* __ARCH_ARM_SRC_AM335X_AM335X_SERIAL_H */

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/****************************************************************************
* arch/arm/src/am335x/am335x_timerisr.c
*
* Copyright (C) 2018 Petro Karashchenko. All rights reserved.
* Author: Petro Karashchenko <petro.karashchenko@gmail.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <time.h>
#include <assert.h>
#include <nuttx/arch.h>
#include <arch/irq.h>
#include <arch/board/board.h>
#include "up_arch.h"
#include "chip/am335x_timer.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Timer 1 clock selects the external 32.768 KHz oscillator/clock */
#define TMR_CLOCK (32768)
/* The desired timer interrupt frequency is provided by the definition
* CLK_TCK (see include/time.h). CLK_TCK defines the desired number of
* system clock ticks per second. That value is a user configurable setting
* that defaults to 100 (100 ticks per second = 10 MS interval).
*
* Timer 1 counts down from the interval reload value to zero, generating
* an interrupt (and reload) when the counts decrements to zero.
*/
#define TMR_TLDR (0xffffffff - (TMR_CLOCK / CLK_TCK) + 1)
#define TMR_TCRR (0xffffffff - (TMR_CLOCK / CLK_TCK) + 1)
#define TMR_TPIR \
(((TMR_CLOCK / CLK_TCK + 1) * 1000000l) - (TMR_CLOCK * (1000000l / CLK_TCK)))
#define TMR_TNIR \
(((TMR_CLOCK / CLK_TCK) * 1000000l) - (TMR_CLOCK * (1000000l / CLK_TCK)))
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Function: am335x_timerisr
*
* Description:
* The timer ISR will perform a variety of services for various portions
* of the systems.
*
****************************************************************************/
static int am335x_timerisr(int irq, uint32_t *regs, void *arg)
{
/* Clear the pending interrupt by writing a '1' to the status register */
putreg32(getreg32(AM335X_TMR1MS_TISR), AM335X_TMR1MS_TISR);
/* Process timer interrupt */
sched_process_timer();
return OK;
}
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Function: arm_timer_initialize
*
* Description:
* This function is called during start-up to initialize
* the timer interrupt.
*
****************************************************************************/
void arm_timer_initialize(void)
{
uint32_t regval;
/* Stop timer */
putreg32(0, AM335X_TMR1MS_TCLR);
putreg32(TMR_TPIR, AM335X_TMR1MS_TPIR);
putreg32(TMR_TNIR, AM335X_TMR1MS_TNIR);
putreg32(TMR_TLDR, AM335X_TMR1MS_TLDR);
putreg32(TMR_TCRR, AM335X_TMR1MS_TCRR);
/* Setup auto-reload, trigger on overflow and start timer */
regval = TMR1MS_TCLR_TRG_OFLOW | TMR1MS_TCLR_AR |
TMR1MS_TCLR_ST;
putreg32(regval, AM335X_TMR1MS_TCLR);
/* Make sure that interrupts from the Timer 0 are disabled */
up_disable_irq(AM335X_IRQ_TIMER1_1MS);
/* Attach the timer interrupt vector */
(void)irq_attach(AM335X_IRQ_TIMER1_1MS, (xcpt_t)am335x_timerisr, NULL);
/* Clear interrupt status */
regval = TMR1MS_IRQ_FlAG_MAT | TMR1MS_IRQ_FLAG_OVF |
TMR1MS_IRQ_FLAG_TCAR;
putreg32(regval, AM335X_TMR1MS_TISR);
/* Enable overflow interrupt */
putreg32(TMR1MS_IRQ_FLAG_OVF, AM335X_TMR1MS_TIER);
/* And enable the timer interrupt */
up_enable_irq(AM335X_IRQ_TIMER1_1MS);
}

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/************************************************************************************
* arch/arm/src/am335x/chip.h
*
* Copyright (C) 2018 Petro Karashchenko. All rights reserved.
* Author: Petro Karashchenko <petro.karashchenko@gmail.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_AM335X_CHIP_H
#define __ARCH_ARM_SRC_AM335X_CHIP_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
#include "chip/am335x_memorymap.h"
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/************************************************************************************
* Public Types
************************************************************************************/
/************************************************************************************
* Public Data
************************************************************************************/
/************************************************************************************
* Public Functions
************************************************************************************/
#endif /* __ARCH_ARM_SRC_AM335X_CHIP_H */

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/************************************************************************************
* arch/arm/src/am335x/chip/am3358_memorymap.h
*
* Copyright (C) 2018 Petro Karashchenko. All rights reserved.
* Author: Petro Karashchenko <petro.karashchenko@gmail.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_AM335X_CHIP_AM3358_MEMORYMAP_H
#define __ARCH_ARM_SRC_AM335X_CHIP_AM3358_MEMORYMAP_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
#include <arch/am335x/chip.h>
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* Decimal configuration values may exceed 2Gb and, hence, overflow to negative
* values unless we force them to unsigned long:
*/
#define __CONCAT(a,b) a ## b
#define MKULONG(a) __CONCAT(a,ul)
/* AM335X physical section base addresses (aligned to 1MB boundaries) */
#define AM335X_GPMC_PSECTION 0x00000000 /* External Memory : 0x0000_0000-0x1FFF_FFFF : 512MB 8-/16-bit External Memory (Ex/R/W) */
#define AM335X_BROM_PSECTION 0x40000000 /* Boot ROM : 0x4000_0000-0x4002_BFFF : 128KB + 48KB 32-bit Ex/R – Public */
#define AM335X_ISRAM_PSECTION 0x40200000 /* SRAM internal : 0x4020_0000-0x402F_FFFF : 961KB Reserved + 63KB 32-bit Ex/R/W */
#define AM335X_OCMC0_PSECTION 0x40300000 /* L3 OCMC0 : 0x4030_0000-0x4030_FFFF : 64KB 32-bit Ex/R/W OCMC SRAM */
#define AM335X_PERIPH_PSECTION 0x44000000 /* Peripherals : 0x4400_0000-0x7FFF_FFFF : The region between OCMC and DDR */
#define AM335X_DDR_PSECTION 0x80000000 /* EMIF0 SDRAM : 0x8000_0000-0xBFFF_FFFF : 1GB 8-/16-bit External Memory (Ex/R/W) */
/* AM335X offsets from the BRROM section base address */
#define AM335X_BROM_OFFSET 0x00020000 /* 0x4002_0000-0x4002_BFFF 48KB ??? TODO: clear out is offset 0x20000 or 0 */
/* AM335X offsets from the internal memory section base address */
#define AM335X_ISRAM_OFFSET 0x000F0400 /* 0x402F_0400-0x402F_FFFF 63KB Internal SRAM 32-bit Ex/R/W */
/* AM335X offsets from the L3 OCMC0 memory section base address */
#define AM335X_OCMC0_OFFSET 0x00000000 /* 0x4030_0000-0x4030_FFFF 64KB 32-bit Ex/R/W OCMC SRAM */
/* AM335X offsets from the peripheral section base address */
#define AM335X_L3_FAST_CFG_OFFSET 0x00000000 /* 0x4400_0000-0x443F_FFFF 4MB L3Fast configuration registers */
#define AM335X_L3_SLOW_CFG_OFFSET 0x00800000 /* 0x4480_0000-0x44BF_FFFF 4MB L3Slow configuration registers */
#define AM335X_L4_WKUP_CFG_OFFSET 0x00C00000 /* 0x4400_0000-0x44C0_1FFF 8KB L4_WKUP configuration */
#define AM335X_CM_PER_OFFSET 0x00E00000 /* 0x44E0_0000-0x44E0_3FFF 1KB Clock Module Peripheral Registers */
#define AM335X_CM_WKUP_OFFSET 0x00E00400 /* 0x44E0_0400-0x44E0_04FF 256 Bytes Clock Module Wakeup Registers */
#define AM335X_CM_DPLL_OFFSET 0x00E00500 /* 0x44E0_0500-0x44E0_05FF 256 Bytes Clock Module PLL Registers */
#define AM335X_CM_MPU_OFFSET 0x00E00600 /* 0x44E0_0600-0x44E0_06FF 256 Bytes Clock Module MPU Registers */
#define AM335X_CM_DEVICE_OFFSET 0x00E00700 /* 0x44E0_0700-0x44E0_07FF 256 Bytes Clock Module Device Registers */
#define AM335X_CM_RTC_OFFSET 0x00E00800 /* 0x44E0_0800-0x44E0_08FF 256 Bytes Clock Module RTC Registers */
#define AM335X_CM_GFX_OFFSET 0x00E00900 /* 0x44E0_0900-0x44E0_09FF 256 Bytes Clock Module Graphics Controller Registers */
#define AM335X_CM_CEFUSE_OFFSET 0x00E00A00 /* 0x44E0_0A00-0x44E0_0AFF 256 Bytes Clock Module Efuse Registers */
#define AM335X_PRM_IRQ_OFFSET 0x00E00B00 /* 0x44E0_0B00-0x44E0_0BFF 256 Bytes Power Reset Module Interrupt Registers */
#define AM335X_PRM_PER_OFFSET 0x00E00C00 /* 0x44E0_0C00-0x44E0_0CFF 256 Bytes Power Reset Module Peripheral Registers */
#define AM335X_PRM_WKUP_OFFSET 0x00E00D00 /* 0x44E0_0D00-0x44E0_0DFF 256 Bytes Power Reset Module Wakeup Registers */
#define AM335X_PRM_MPU_OFFSET 0x00E00E00 /* 0x44E0_0E00-0x44E0_0EFF 256 Bytes Power Reset Module MPU Registers */
#define AM335X_PRM_DEV_OFFSET 0x00E00F00 /* 0x44E0_0F00-0x44E0_0FFF 256 Bytes Power Reset Module Device Registers */
#define AM335X_PRM_RTC_OFFSET 0x00E01000 /* 0x44E0_1000-0x44E0_10FF 256 Bytes Power Reset Module RTC Registers */
#define AM335X_PRM_GFX_OFFSET 0x00E01100 /* 0x44E0_1100-0x44E0_11FF 256 Bytes Power Reset Module Graphics Controller Registers */
#define AM335X_PRM_CEFUSE_OFFSET 0x00E01200 /* 0x44E0_1200-0x44E0_12FF 256 Bytes Power Reset Module Efuse Registers */
#define AM335X_DMTIMER0_OFFSET 0x00E05000 /* 0x44E0_5000-0x44E0_5FFF 4KB DMTimer0 Registers */
#define AM335X_GPIO0_OFFSET 0x00E07000 /* 0x44E0_7000-0x44E0_7FFF 4KB GPIO Registers */
#define AM335X_UART0_OFFSET 0x00E09000 /* 0x44E0_9000-0x44E0_9FFF 4KB UART Registers */
#define AM335X_I2C0_OFFSET 0x00E0B000 /* 0x44E0_B000-0x44E0_BFFF 4KB I2C Registers */
#define AM335X_ADC_TSC_OFFSET 0x00E0D000 /* 0x44E0_D000-0x44E0_EFFF 8KB ADC_TSC Registers */
#define AM335X_CONTROL_MODULE_OFFSET 0x00E10000 /* 0x44E1_0000-0x44E1_1FFF 8KB Control Module Registers */
#define AM335X_DDR_PHY_OFFSET 0x00E12000 /* 0x44E1_2000-0x44E1_23FF 1KB DDR2/3/mDDR PHY Registers */
#define AM335X_DMTIMER1_1MS_OFFSET 0x00E31000 /* 0x44E3_1000-0x44E3_1FFF 4KB DMTimer1 1ms Registers (Accurate 1ms timer) */
#define AM335X_WDT1_OFFSET 0x00E35000 /* 0x44E3_5000-0x44E3_5FFF 4KB Watchdog Timer Registers */
#define AM335X_SMART_REFLEX0_OFFSET 0x00E37000 /* 0x44E3_7000-0x44E3_7FFF 4KB L3 Registers */
#define AM335X_SMART_REFLEX1_OFFSET 0x00E39000 /* 0x44E3_9000-0x44E3_9FFF 4KB L3 Registers */
#define AM335X_RTCSS_OFFSET 0x00E3E000 /* 0x44E3_E000-0x44E3_EFFF 4KB RTC Registers */
#define AM335X_DEBUG_SS_OFFSET 0x00E40000 /* 0x44E4_0000-0x44E7_FFFF 256KB Debug Register */
#define AM335X_MCASP0_DATA_OFFSET 0x02000000 /* 0x4600_0000-0x463F_FFFF 4MB McASP0 Data Registers */
#define AM335X_MCASP1_DATA_OFFSET 0x02400000 /* 0x4640_0000-0x467F_FFFF 4MB McASP1 Data Registers */
#define AM335X_USBSS_OFFSET 0x03400000 /* 0x4740_0000-0x4740_0FFF USB Subsystem Registers */
#define AM335X_USB0_OFFSET 0x03401000 /* 0x4740_1000-0x4740_12FF USB0 Controller Registers */
#define AM335X_USB0_PHY_OFFSET 0x03401300 /* 0x4740_1300-0x4740_13FF USB0 PHY Registers */
#define AM335X_USB0_CORE_OFFSET 0x03401400 /* 0x4740_1400-0x4740_17FF USB0 Core Registers */
#define AM335X_USB1_OFFSET 0x03401800 /* 0x4740_1800-0x4740_1AFF USB1 Controller Registers */
#define AM335X_USB1_PHY_OFFSET 0x03401B00 /* 0x4740_1B00-0x4740_1BFF USB1 PHY Registers */
#define AM335X_USB1_CORE_OFFSET 0x03401C00 /* 0x4740_1C00-0x4740_1FFF USB1 Core Registers */
#define AM335X_USB_DMA_OFFSET 0x03402000 /* 0x4740_2000-0x4740_2FFF USB CPPI DMA Controller Registers */
#define AM335X_USB_DMA_SCHED_OFFSET 0x03403000 /* 0x4740_3000-0x4740_3FFF USB CPPI DMA Scheduler Registers */
#define AM335X_USB_QUEUE_MGR_OFFSET 0x03404000 /* 0x4740_4000-0x4740_7FFF USB Queue Manager Registers */
#define AM335X_MMCHS2_OFFSET 0x03810000 /* 0x4781_0000-0x4781_FFFF 64KB MMCHS2 */
#define AM335X_UART1_OFFSET 0x04022000 /* 0x4802_2000-0x4802_2FFF 4KB UART1 Registers */
#define AM335X_UART2_OFFSET 0x04024000 /* 0x4802_4000-0x4802_4FFF 4KB UART2 Registers */
#define AM335X_I2C1_OFFSET 0x0402A000 /* 0x4802_A000-0x4802_AFFF 4KB I2C1 Registers */
#define AM335X_MCSPI0_OFFSET 0x04030000 /* 0x4803_0000-0x4803_0FFF 4KB McSPI0 Registers */
#define AM335X_MCASP0_OFFSET 0x04038000 /* 0x4803_8000-0x4803_9FFF 8KB McASP0 CFG Registers */
#define AM335X_MCASP1_OFFSET 0x0403C000 /* 0x4803_C000-0x4803_DFFF 8KB McASP1 CFG Registers */
#define AM335X_DMTIMER2_OFFSET 0x04040000 /* 0x4804_0000-0x4804_0FFF 4KB DMTimer2 Registers */
#define AM335X_DMTIMER3_OFFSET 0x04042000 /* 0x4804_2000-0x4804_2FFF 4KB DMTimer3 Registers */
#define AM335X_DMTIMER4_OFFSET 0x04044000 /* 0x4804_4000-0x4804_4FFF 4KB DMTimer4 Registers */
#define AM335X_DMTIMER5_OFFSET 0x04046000 /* 0x4804_6000-0x4804_6FFF 4KB DMTimer5 Registers */
#define AM335X_DMTIMER6_OFFSET 0x04048000 /* 0x4804_8000-0x4804_8FFF 4KB DMTimer6 Registers */
#define AM335X_DMTIMER7_OFFSET 0x0404A000 /* 0x4804_A000-0x4804_AFFF 4KB DMTimer7 Registers */
#define AM335X_GPIO1_OFFSET 0x0404C000 /* 0x4804_C000-0x4804_CFFF 4KB GPIO1 Registers */
#define AM335X_MMCHS0_OFFSET 0x04060000 /* 0x4806_0000-0x4806_0FFF 4KB MMCHS0 Registers */
#define AM335X_ELM_OFFSET 0x04080000 /* 0x4808_0000-0x4808_FFFF 64KB ELM Registers */
#define AM335X_MAIBOX_OFFSET 0x040C8000 /* 0x480C_8000-0x480C_8FFF 4KB Mailbox Registers */
#define AM335X_SPINLOCK_OFFSET 0x040CA000 /* 0x480C_A000-0x480C_AFFF 4KB Spinlock Registers */
#define AM335X_OCP_WATCHPOINT_OFFSET 0x0418C000 /* 0x4818_C000-0x4818_CFFF 4KB OCP Watchpoint Registers */
#define AM335X_I2C2_OFFSET 0x0419C000 /* 0x4819_C000-0x4819_CFFF 4KB I2C2 Registers */
#define AM335X_MCSPI1_OFFSET 0x041A0000 /* 0x481A_0000-0x481A_0FFF 4KB McSPI1 Registers */
#define AM335X_UART3_OFFSET 0x041A6000 /* 0x481A_6000-0x481A_6FFF 4KB UART3 Registers */
#define AM335X_UART4_OFFSET 0x041A8000 /* 0x481A_8000-0x481A_8FFF 4KB UART4 Registers */
#define AM335X_UART5_OFFSET 0x041AA000 /* 0x481A_A000-0x481A_AFFF 4KB UART5 Registers */
#define AM335X_GPIO2_OFFSET 0x041AC000 /* 0x481A_C000-0x481A_CFFF 4KB GPIO2 Registers */
#define AM335X_GPIO3_OFFSET 0x041AE000 /* 0x481A_E000-0x481A_EFFF 4KB GPIO3 Registers */
#define AM335X_DCAN0_OFFSET 0x041CC000 /* 0x481C_C000-0x481C_DFFF 8KB DCAN0 Registers */
#define AM335X_DCAN1_OFFSET 0x041D0000 /* 0x481D_0000-0x481D_1FFF 8KB DCAN1 Registers */
#define AM335X_MMC1_OFFSET 0x041D8000 /* 0x481D_8000-0x481D_8FFF 4KB MMC1 Registers */
#define AM335X_INTC_OFFSET 0x04200000 /* 0x4820_0000-0x4820_0FFF 4KB Interrupt Controller Registers */
#define AM335X_MPUSS_OFFSET 0x04240000 /* 0x4824_0000-0x4824_0FFF 4KB Host ARM non-shared device mapping */
#define AM335X_PWMSS0_OFFSET 0x04300000 /* 0x4830_0000-0x4830_00FF XXKB PWM Subsystem 0 Configuration Registers */
#define AM335X_ECAP0_OFFSET 0x04300100 /* 0x4830_0100-0x4830_017F XXKB PWMSS eCAP0 Registers */
#define AM335X_EQEP0_OFFSET 0x04300180 /* 0x4830_0180-0x4830_01FF XXKB PWMSS eQEP0 Registers */
#define AM335X_EPWM0_OFFSET 0x04300200 /* 0x4830_0200-0x4830_025F XXKB PWMSS ePWM0 Registers */
#define AM335X_PWMSS1_OFFSET 0x04302000 /* 0x4830_2000-0x4830_20FF XXKB PWM Subsystem 1 Configuration Registers */
#define AM335X_ECAP1_OFFSET 0x04302100 /* 0x4830_2100-0x4830_217F XXKB PWMSS eCAP1 Registers */
#define AM335X_EQEP1_OFFSET 0x04302180 /* 0x4830_2180-0x4830_21FF XXKB PWMSS eQEP1 Registers */
#define AM335X_EPWM1_OFFSET 0x04302200 /* 0x4830_2200-0x4830_225F XXKB PWMSS ePWM1 Registers */
#define AM335X_PWMSS2_OFFSET 0x04304000 /* 0x4830_4000-0x4830_40FF XXKB PWM Subsystem 2 Configuration Registers */
#define AM335X_ECAP2_OFFSET 0x04304100 /* 0x4830_4100-0x4830_417F XXKB PWMSS eCAP2 Registers */
#define AM335X_EQEP2_OFFSET 0x04304180 /* 0x4830_4180-0x4830_41FF XXKB PWMSS eQEP2 Registers */
#define AM335X_EPWM2_OFFSET 0x04304200 /* 0x4830_4200-0x4830_425F XXKB PWMSS ePWM2 Registers */
#define AM335X_LCD_OFFSET 0x0430E000 /* 0x4830_E000-0x4830_EFFF 4KB LCD Registers */
#define AM335X_EDMA3CC_OFFSET 0x05000000 /* 0x4900_0000-0x490F_FFFF 1MB EDMA3 Channel Controller Registers */
#define AM335X_EDMA3TC0_OFFSET 0x05800000 /* 0x4980_0000-0x498F_FFFF 1MB EDMA3 Transfer Controller 0 Registers */
#define AM335X_EDMA3TC1_OFFSET 0x05900000 /* 0x4990_0000-0x499F_FFFF 1MB EDMA3 Transfer Controller 1 Registers */
#define AM335X_EDMA3TC2_OFFSET 0x05A00000 /* 0x49A0_0000-0x49AF_FFFF 1MB EDMA3 Transfer Controller 2 Registers */
#define AM335X_L4_FAST_CONFIG_OFFSET 0x06000000 /* 0x4A00_0000-0x4A00_1FFF 8KB L4_FAST configuration */
#define AM335X_CPSW_SS_OFFSET 0x06100000 /* 0x4A10_0000-0x4A10_7FFF 32KB Ethernet Switch Subsystem */
#define AM335X_CPSW_PORT_OFFSET 0x06100100 /* 0x4A10_0100-0x4A10_07FF Ethernet Switch Port Control */
#define AM335X_CPSW_CPDMA_OFFSET 0x06100800 /* 0x4A10_0800-0x4A10_08FF CPPI DMA Controller Module */
#define AM335X_CPSW_STATS_OFFSET 0x06100900 /* 0x4A10_0900-0x4A10_09FF Ethernet Statistics */
#define AM335X_CPSW_STATERAM_OFFSET 0x06100A00 /* 0x4A10_0A00-0x4A10_0BFF CPPI DMA State RAM */
#define AM335X_CPSW_CPTS_OFFSET 0x06100C00 /* 0x4A10_0C00-0x4A10_0CFF Ethernet Time Sync Module */
#define AM335X_CPSW_ALE_OFFSET 0x06100D00 /* 0x4A10_0D00-0x4A10_0D7F Ethernet Address Lookup Engine */
#define AM335X_CPSW_SL1_OFFSET 0x06100D80 /* 0x4A10_0D80-0x4A10_0DBF Ethernet Sliver for Port 1 */
#define AM335X_CPSW_SL2_OFFSET 0x06100DC0 /* 0x4A10_0DC0-0x4A10_0DFF Ethernet Sliver for Port 2 */
#define AM335X_MDIO_OFFSET 0x06101000 /* 0x4A10_1000-0x4A10_10FF Ethernet MDIO Controller */
#define AM335X_CPSW_WR_OFFSET 0x06101200 /* 0x4A10_1200-0x4A10_1FFF Ethernet Subsystem Wrapper for RMII/RGMII */
#define AM335X_CPPI_RAM_OFFSET 0x06102000 /* 0x4A10_2000-0x4A10_3FFF Communications Port Programming Interface RAM */
#define AM335X_PRU_ICSS_OFFSET 0x06300000 /* 0x4A30_0000-0x4A37_FFFF 512KB PRU-ICSS Instruction/Data/Control Space */
#define AM335X_DEBUG_SS_DRM_OFFSET 0x07160000 /* 0x4B16_0000-0x4B16_0FFF 4KB Debug Subsystem: Debug Resource Manager */
#define AM335X_DEBUG_SS_ETB_OFFSET 0x07162000 /* 0x4B16_2000-0x4B16_2FFF 4KB Debug Subsystem: Embedded Trace Buffer */
#define AM335X_EMIF0_OFFSET 0x08000000 /* 0x4C00_0000-0x4CFF_FFFF 16MB EMIF0 Configuration registers */
#define AM335X_GPMC_OFFSET 0x0C000000 /* 0x5000_0000-0x50FF_FFFF 16MB GPMC Configuration registers */
#define AM335X_ADC_TSC_DMA_OFFSET 0x10C00000 /* 0x54C0_0000-0x54FF_FFFF 4MB ADC_TSC DMA Port */
#define AM335X_SGX530_OFFSET 0x12000000 /* 0x5600_0000-0x56FF_FFFF 16MB SGX530 Slave Port */
/* AM335X internal memory physical base addresses */
#define AM335X_ISRAM_PADDR (AM335X_ISRAM_PSECTION+AM335X_ISRAM_OFFSET)
/* AM335X L3 OCMC0 memory physical base addresses */
#define AM335X_OCMC0_PADDR (AM335X_OCMC0_PSECTION+AM335X_OCMC0_OFFSET)
/* Sizes of memory regions in bytes.
*
* These sizes exclude the undefined addresses at the end of the memory
* region. The implemented sizes of the external memory regions are
* not known apriori and must be specified with configuration settings.
*/
#define AM335X_GPMC_SIZE 0x20000000 /* GPMC (External Memory) 0x0000_0000-0x1FFF_FFFF 512MB */
#define AM335X_BROM_SIZE 0x0002c000 /* BROM 0x4000_0000-0x4002_BFFF 176KB */
#define AM335X_ISRAM_SIZE 0x00100000 /* SRAM internal 0x4020_0000 0x402F_FFFF 1MB */
#define AM335X_OCMC0_SIZE 0x00010000 /* L3 OCMC0 0x4030_0000 0x4030_FFFF 64KB */
#define AM335X_PERIPH_SIZE 0x3c000000 /* Peripherals 0x4400_0000-0x7FFF_FFFF 960MB */
/* Force configured sizes that might exceed 1GB to be unsigned long */
#define AM335X_DDR_MAPOFFSET MKULONG(CONFIG_AM335X_DDR_MAPOFFSET)
#define AM335X_DDR_MAPSIZE MKULONG(CONFIG_AM335X_DDR_MAPSIZE)
#define AM335X_DDR_HEAP_OFFSET MKULONG(CONFIG_AM335X_DDR_HEAP_OFFSET)
#define AM335X_DDR_HEAP_SIZE MKULONG(CONFIG_AM335X_DDR_HEAP_SIZE)
/* Convert size in bytes to number of sections (in Mb). */
#define _NSECTIONS(b) (((b)+0x000fffff) >> 20)
/* Sizes of memory regions in sections.
*
* The boot logic in AM335X_boot.c, will select 1Mb level 1 MMU mappings to
* span the entire physical address space. The definitions below specify
* the number of 1Mb entries that are required to span a particular address
* region.
*
* NOTE: the size of the mapped SDRAM region depends on the configured size
* of DRAM, not on the size of the address space assigned to DRAM.
*/
#define AM335X_GPMC_NSECTIONS _NSECTIONS(AM335X_GPMC_SIZE)
#define AM335X_BROM_NSECTIONS _NSECTIONS(AM335X_BROM_SIZE)
#define AM335X_ISRAM_NSECTIONS _NSECTIONS(AM335X_ISRAM_SIZE)
#define AM335X_OCMC0_NSECTIONS _NSECTIONS(AM335X_OCMC0_SIZE)
#define AM335X_PERIPH_NSECTIONS _NSECTIONS(AM335X_PERIPH_SIZE)
#define AM335X_DDR_NSECTIONS _NSECTIONS(AM335X_DDR_MAPSIZE)
/* Section MMU Flags */
#define AM335X_GPMC_MMUFLAGS MMU_MEMFLAGS
#define AM335X_BROM_MMUFLAGS MMU_ROMFLAGS
#define AM335X_ISRAM_MMUFLAGS MMU_MEMFLAGS
#define AM335X_OCMC0_MMUFLAGS MMU_MEMFLAGS
#define AM335X_PERIPH_MMUFLAGS MMU_IOFLAGS
#define AM335X_DDR_MMUFLAGS MMU_MEMFLAGS
/* AM335X Virtual (mapped) Memory Map
*
* board_memorymap.h contains special mappings that are needed when a ROM
* memory map is used. It is included in this odd location because it depends
* on some the virtual address definitions provided above.
*/
#include <arch/board/board_memorymap.h>
/* AM335X Virtual (mapped) Memory Map. These are the mappings that will
* be created if the page table lies in RAM. If the platform has another,
* read-only, pre-initialized page table (perhaps in ROM), then the board.h
* file must provide these definitions.
*/
#ifndef CONFIG_ARCH_ROMPGTABLE
/* The default mappings are a simple 1-to-1 mapping */
#define AM335X_GPMC_VSECTION 0x00000000 /* External Memory : 0x0000_0000-0x1FFF_FFFF : 512MB 8-/16-bit External Memory (Ex/R/W) */
#define AM335X_BROM_VSECTION 0x40000000 /* Boot ROM : 0x4000_0000-0x4002_BFFF : 128KB + 48KB 32-bit Ex/R – Public */
#define AM335X_ISRAM_VSECTION 0x40200000 /* SRAM internal : 0x4020_0000-0x402F_FFFF : 961KB Reserved + 63KB 32-bit Ex/R/W */
#define AM335X_OCMC0_VSECTION 0x40300000 /* L3 OCMC0 : 0x4030_0000-0x4030_FFFF : 64KB 32-bit Ex/R/W OCMC SRAM */
#define AM335X_PERIPH_VSECTION 0x44000000 /* Peripherals : 0x4400_0000-0x7FFF_FFFF : The region between OCMC and DDR */
#define AM335X_DDR_VSECTION 0x80000000 /* EMIF0 SDRAM : 0x8000_0000-0xBFFF_FFFF : 1GB 8-/16-bit External Memory (Ex/R/W) */
#endif
/* AM335X internal memory virtual base addresses */
#define AM335X_ISRAM_VADDR (AM335X_ISRAM_VSECTION+AM335X_ISRAM_OFFSET)
/* AM335X L3 OCMC0 memory virtual base addresses */
#define AM335X_OCMC0_VADDR (AM335X_OCMC0_VSECTION+AM335X_OCMC0_OFFSET)
/* Peripheral virtual base addresses */
#define AM335X_L3_FAST_CFG_VADDR (AM335X_PERIPH_VSECTION+AM335X_L3_FAST_CFG_OFFSET)
#define AM335X_L3_SLOW_CFG_VADDR (AM335X_PERIPH_VSECTION+AM335X_L3_SLOW_CFG_OFFSET)
#define AM335X_L4_WKUP_CFG_VADDR (AM335X_PERIPH_VSECTION+AM335X_L4_WKUP_CFG_OFFSET)
#define AM335X_CM_PER_VADDR (AM335X_PERIPH_VSECTION+AM335X_CM_PER_OFFSET)
#define AM335X_CM_WKUP_VADDR (AM335X_PERIPH_VSECTION+AM335X_CM_WKUP_OFFSET)
#define AM335X_CM_DPLL_VADDR (AM335X_PERIPH_VSECTION+AM335X_CM_DPLL_OFFSET)
#define AM335X_CM_MPU_VADDR (AM335X_PERIPH_VSECTION+AM335X_CM_MPU_OFFSET)
#define AM335X_CM_DEVICE_VADDR (AM335X_PERIPH_VSECTION+AM335X_CM_DEVICE_OFFSET)
#define AM335X_CM_RTC_VADDR (AM335X_PERIPH_VSECTION+AM335X_CM_RTC_OFFSET)
#define AM335X_CM_GFX_VADDR (AM335X_PERIPH_VSECTION+AM335X_CM_GFX_OFFSET)
#define AM335X_CM_CEFUSE_VADDR (AM335X_PERIPH_VSECTION+AM335X_CM_CEFUSE_OFFSET)
#define AM335X_PRM_IRQ_VADDR (AM335X_PERIPH_VSECTION+AM335X_PRM_IRQ_OFFSET)
#define AM335X_PRM_PER_VADDR (AM335X_PERIPH_VSECTION+AM335X_PRM_PER_OFFSET)
#define AM335X_PRM_WKUP_VADDR (AM335X_PERIPH_VSECTION+AM335X_PRM_WKUP_OFFSET)
#define AM335X_PRM_MPU_VADDR (AM335X_PERIPH_VSECTION+AM335X_PRM_MPU_OFFSET)
#define AM335X_PRM_DEV_VADDR (AM335X_PERIPH_VSECTION+AM335X_PRM_DEV_OFFSET)
#define AM335X_PRM_RTC_VADDR (AM335X_PERIPH_VSECTION+AM335X_PRM_RTC_OFFSET)
#define AM335X_PRM_GFX_VADDR (AM335X_PERIPH_VSECTION+AM335X_PRM_GFX_OFFSET)
#define AM335X_PRM_CEFUSE_VADDR (AM335X_PERIPH_VSECTION+AM335X_PRM_CEFUSE_OFFSET)
#define AM335X_DMTIMER0_VADDR (AM335X_PERIPH_VSECTION+AM335X_DMTIMER0_OFFSET)
#define AM335X_GPIO0_VADDR (AM335X_PERIPH_VSECTION+AM335X_GPIO0_OFFSET)
#define AM335X_UART0_VADDR (AM335X_PERIPH_VSECTION+AM335X_UART0_OFFSET)
#define AM335X_I2C0_VADDR (AM335X_PERIPH_VSECTION+AM335X_I2C0_OFFSET)
#define AM335X_ADC_TSC_VADDR (AM335X_PERIPH_VSECTION+AM335X_ADC_TSC_OFFSET)
#define AM335X_CONTROL_MODULE_VADDR (AM335X_PERIPH_VSECTION+AM335X_CONTROL_MODULE_OFFSET)
#define AM335X_DDR_PHY_VADDR (AM335X_PERIPH_VSECTION+AM335X_DDR_PHY_OFFSET)
#define AM335X_DMTIMER1_1MS_VADDR (AM335X_PERIPH_VSECTION+AM335X_DMTIMER1_1MS_OFFSET)
#define AM335X_WDT1_VADDR (AM335X_PERIPH_VSECTION+AM335X_WDT1_OFFSET)
#define AM335X_SMART_REFLEX0_VADDR (AM335X_PERIPH_VSECTION+AM335X_SMART_REFLEX0_OFFSET)
#define AM335X_SMART_REFLEX1_VADDR (AM335X_PERIPH_VSECTION+AM335X_SMART_REFLEX1_OFFSET)
#define AM335X_RTCSS_VADDR (AM335X_PERIPH_VSECTION+AM335X_RTCSS_OFFSET)
#define AM335X_DEBUG_SS_VADDR (AM335X_PERIPH_VSECTION+AM335X_DEBUG_SS_OFFSET)
#define AM335X_MCASP0_DATA_VADDR (AM335X_PERIPH_VSECTION+AM335X_MCASP0_DATA_OFFSET)
#define AM335X_MCASP1_DATA_VADDR (AM335X_PERIPH_VSECTION+AM335X_MCASP1_DATA_OFFSET)
#define AM335X_USBSS_VADDR (AM335X_PERIPH_VSECTION+AM335X_USBSS_OFFSET)
#define AM335X_USB0_VADDR (AM335X_PERIPH_VSECTION+AM335X_USB0_OFFSET)
#define AM335X_USB0_PHY_VADDR (AM335X_PERIPH_VSECTION+AM335X_USB0_PHY_OFFSET)
#define AM335X_USB0_CORE_VADDR (AM335X_PERIPH_VSECTION+AM335X_USB0_CORE_OFFSET)
#define AM335X_USB1_VADDR (AM335X_PERIPH_VSECTION+AM335X_USB1_OFFSET)
#define AM335X_USB1_PHY_VADDR (AM335X_PERIPH_VSECTION+AM335X_USB1_PHY_OFFSET)
#define AM335X_USB1_CORE_VADDR (AM335X_PERIPH_VSECTION+AM335X_USB1_CORE_OFFSET)
#define AM335X_USB_DMA_VADDR (AM335X_PERIPH_VSECTION+AM335X_USB_DMA_OFFSET)
#define AM335X_USB_DMA_SCHED_VADDR (AM335X_PERIPH_VSECTION+AM335X_USB_DMA_SCHED_OFFSET)
#define AM335X_USB_QUEUE_MGR_VADDR (AM335X_PERIPH_VSECTION+AM335X_USB_QUEUE_MGR_OFFSET)
#define AM335X_MMCHS2_VADDR (AM335X_PERIPH_VSECTION+AM335X_MMCHS2_OFFSET)
#define AM335X_UART1_VADDR (AM335X_PERIPH_VSECTION+AM335X_UART1_OFFSET)
#define AM335X_UART2_VADDR (AM335X_PERIPH_VSECTION+AM335X_UART2_OFFSET)
#define AM335X_I2C1_VADDR (AM335X_PERIPH_VSECTION+AM335X_I2C1_OFFSET)
#define AM335X_MCSPI0_VADDR (AM335X_PERIPH_VSECTION+AM335X_MCSPI0_OFFSET)
#define AM335X_MCASP0_VADDR (AM335X_PERIPH_VSECTION+AM335X_MCASP0_OFFSET)
#define AM335X_MCASP1_VADDR (AM335X_PERIPH_VSECTION+AM335X_MCASP1_OFFSET)
#define AM335X_DMTIMER2_VADDR (AM335X_PERIPH_VSECTION+AM335X_DMTIMER2_OFFSET)
#define AM335X_DMTIMER3_VADDR (AM335X_PERIPH_VSECTION+AM335X_DMTIMER3_OFFSET)
#define AM335X_DMTIMER4_VADDR (AM335X_PERIPH_VSECTION+AM335X_DMTIMER4_OFFSET)
#define AM335X_DMTIMER5_VADDR (AM335X_PERIPH_VSECTION+AM335X_DMTIMER5_OFFSET)
#define AM335X_DMTIMER6_VADDR (AM335X_PERIPH_VSECTION+AM335X_DMTIMER6_OFFSET)
#define AM335X_DMTIMER7_VADDR (AM335X_PERIPH_VSECTION+AM335X_DMTIMER7_OFFSET)
#define AM335X_GPIO1_VADDR (AM335X_PERIPH_VSECTION+AM335X_GPIO1_OFFSET)
#define AM335X_MMCHS0_VADDR (AM335X_PERIPH_VSECTION+AM335X_MMCHS0_OFFSET)
#define AM335X_ELM_VADDR (AM335X_PERIPH_VSECTION+AM335X_ELM_OFFSET)
#define AM335X_MAIBOX_VADDR (AM335X_PERIPH_VSECTION+AM335X_MAIBOX_OFFSET)
#define AM335X_SPINLOCK_VADDR (AM335X_PERIPH_VSECTION+AM335X_SPINLOCK_OFFSET)
#define AM335X_OCP_WATCHPOINT_VADDR (AM335X_PERIPH_VSECTION+AM335X_OCP_WATCHPOINT_OFFSET)
#define AM335X_I2C2_VADDR (AM335X_PERIPH_VSECTION+AM335X_I2C2_OFFSET)
#define AM335X_MCSPI1_VADDR (AM335X_PERIPH_VSECTION+AM335X_MCSPI1_OFFSET)
#define AM335X_UART3_VADDR (AM335X_PERIPH_VSECTION+AM335X_UART3_OFFSET)
#define AM335X_UART4_VADDR (AM335X_PERIPH_VSECTION+AM335X_UART4_OFFSET)
#define AM335X_UART5_VADDR (AM335X_PERIPH_VSECTION+AM335X_UART5_OFFSET)
#define AM335X_GPIO2_VADDR (AM335X_PERIPH_VSECTION+AM335X_GPIO2_OFFSET)
#define AM335X_GPIO3_VADDR (AM335X_PERIPH_VSECTION+AM335X_GPIO3_OFFSET)
#define AM335X_DCAN0_VADDR (AM335X_PERIPH_VSECTION+AM335X_DCAN0_OFFSET)
#define AM335X_DCAN1_VADDR (AM335X_PERIPH_VSECTION+AM335X_DCAN1_OFFSET)
#define AM335X_MMC1_VADDR (AM335X_PERIPH_VSECTION+AM335X_MMC1_OFFSET)
#define AM335X_INTC_VADDR (AM335X_PERIPH_VSECTION+AM335X_INTC_OFFSET)
#define AM335X_MPUSS_VADDR (AM335X_PERIPH_VSECTION+AM335X_MPUSS_OFFSET)
#define AM335X_PWMSS0_VADDR (AM335X_PERIPH_VSECTION+AM335X_PWMSS0_OFFSET)
#define AM335X_ECAP0_VADDR (AM335X_PERIPH_VSECTION+AM335X_ECAP0_OFFSET)
#define AM335X_EQEP0_VADDR (AM335X_PERIPH_VSECTION+AM335X_EQEP0_OFFSET)
#define AM335X_EPWM0_VADDR (AM335X_PERIPH_VSECTION+AM335X_EPWM0_OFFSET)
#define AM335X_PWMSS1_VADDR (AM335X_PERIPH_VSECTION+AM335X_PWMSS1_OFFSET)
#define AM335X_ECAP1_VADDR (AM335X_PERIPH_VSECTION+AM335X_ECAP1_OFFSET)
#define AM335X_EQEP1_VADDR (AM335X_PERIPH_VSECTION+AM335X_EQEP1_OFFSET)
#define AM335X_EPWM1_VADDR (AM335X_PERIPH_VSECTION+AM335X_EPWM1_OFFSET)
#define AM335X_PWMSS2_VADDR (AM335X_PERIPH_VSECTION+AM335X_PWMSS2_OFFSET)
#define AM335X_ECAP2_VADDR (AM335X_PERIPH_VSECTION+AM335X_ECAP2_OFFSET)
#define AM335X_EQEP2_VADDR (AM335X_PERIPH_VSECTION+AM335X_EQEP2_OFFSET)
#define AM335X_EPWM2_VADDR (AM335X_PERIPH_VSECTION+AM335X_EPWM2_OFFSET)
#define AM335X_LCD_VADDR (AM335X_PERIPH_VSECTION+AM335X_LCD_OFFSET)
#define AM335X_EDMA3CC_VADDR (AM335X_PERIPH_VSECTION+AM335X_EDMA3CC_OFFSET)
#define AM335X_EDMA3TC0_VADDR (AM335X_PERIPH_VSECTION+AM335X_EDMA3TC0_OFFSET)
#define AM335X_EDMA3TC1_VADDR (AM335X_PERIPH_VSECTION+AM335X_EDMA3TC1_OFFSET)
#define AM335X_EDMA3TC2_VADDR (AM335X_PERIPH_VSECTION+AM335X_EDMA3TC2_OFFSET)
#define AM335X_L4_FAST_CONFIG_VADDR (AM335X_PERIPH_VSECTION+AM335X_L4_FAST_CONFIG_OFFSET)
#define AM335X_CPSW_SS_VADDR (AM335X_PERIPH_VSECTION+AM335X_CPSW_SS_OFFSET)
#define AM335X_CPSW_PORT_VADDR (AM335X_PERIPH_VSECTION+AM335X_CPSW_PORT_OFFSET)
#define AM335X_CPSW_CPDMA_VADDR (AM335X_PERIPH_VSECTION+AM335X_CPSW_CPDMA_OFFSET)
#define AM335X_CPSW_STATS_VADDR (AM335X_PERIPH_VSECTION+AM335X_CPSW_STATS_OFFSET)
#define AM335X_CPSW_STATERAM_VADDR (AM335X_PERIPH_VSECTION+AM335X_CPSW_STATERAM_OFFSET)
#define AM335X_CPSW_CPTS_VADDR (AM335X_PERIPH_VSECTION+AM335X_CPSW_CPTS_OFFSET)
#define AM335X_CPSW_ALE_VADDR (AM335X_PERIPH_VSECTION+AM335X_CPSW_ALE_OFFSET)
#define AM335X_CPSW_SL1_VADDR (AM335X_PERIPH_VSECTION+AM335X_CPSW_SL1_OFFSET)
#define AM335X_CPSW_SL2_VADDR (AM335X_PERIPH_VSECTION+AM335X_CPSW_SL2_OFFSET)
#define AM335X_MDIO_VADDR (AM335X_PERIPH_VSECTION+AM335X_MDIO_OFFSET)
#define AM335X_CPSW_WR_VADDR (AM335X_PERIPH_VSECTION+AM335X_CPSW_WR_OFFSET)
#define AM335X_CPPI_RAM_VADDR (AM335X_PERIPH_VSECTION+AM335X_CPPI_RAM_OFFSET)
#define AM335X_PRU_ICSS_VADDR (AM335X_PERIPH_VSECTION+AM335X_PRU_ICSS_OFFSET)
#define AM335X_DEBUG_SS_DRM_VADDR (AM335X_PERIPH_VSECTION+AM335X_DEBUG_SS_DRM_OFFSET)
#define AM335X_DEBUG_SS_ETB_VADDR (AM335X_PERIPH_VSECTION+AM335X_DEBUG_SS_ETB_OFFSET)
#define AM335X_EMIF0_VADDR (AM335X_PERIPH_VSECTION+AM335X_EMIF0_OFFSET)
#define AM335X_GPMC_VADDR (AM335X_PERIPH_VSECTION+AM335X_GPMC_OFFSET)
#define AM335X_ADC_TSC_DMA_VADDR (AM335X_PERIPH_VSECTION+AM335X_ADC_TSC_DMA_OFFSET)
#define AM335X_SGX530_VADDR (AM335X_PERIPH_VSECTION+AM335X_SGX530_OFFSET)
/* Offset DDR address */
#define AM335X_DDR_MAPPADDR (AM335X_DDR_PSECTION+AM335X_DDR_MAPOFFSET)
#define AM335X_DDR_MAPVADDR (AM335X_DDR_VSECTION+AM335X_DDR_MAPOFFSET)
/* NuttX virtual base address
*
* The boot logic will create a temporarily mapping based on where NuttX is
* executing in memory. In this case, NuttX will be running from either
* internal SRAM or external SDRAM.
*
* Setup the RAM region as the NUTTX .txt, .bss, and .data region.
*/
#define NUTTX_TEXT_VADDR (CONFIG_RAM_VSTART & 0xfff00000)
#define NUTTX_TEXT_PADDR (CONFIG_RAM_START & 0xfff00000)
#define NUTTX_TEXT_PEND ((CONFIG_RAM_END + 0x000fffff) & 0xfff00000)
#define NUTTX_TEXT_SIZE (NUTTX_TEXT_PEND - NUTTX_TEXT_PADDR)
/* MMU Page Table
*
* Determine the address of the MMU page table. Regardless of the memory
* configuration, we will keep the page table in the AM335X's internal SRAM.
*/
#if defined(PGTABLE_BASE_PADDR) || defined(PGTABLE_BASE_VADDR)
/* Sanity check.. if one is undefined, both should be undefined */
# if !defined(PGTABLE_BASE_PADDR) || !defined(PGTABLE_BASE_VADDR)
# error "Only one of PGTABLE_BASE_PADDR or PGTABLE_BASE_VADDR is defined"
# endif
/* A sanity check, if the configuration says that the page table is read-only
* and pre-initialized (maybe ROM), then it should have also defined both of
* the page table base addresses.
*/
# ifdef CONFIG_ARCH_ROMPGTABLE
# error "CONFIG_ARCH_ROMPGTABLE defined; PGTABLE_BASE_P/VADDR not defined"
# endif
#else /* PGTABLE_BASE_PADDR || PGTABLE_BASE_VADDR */
/* If CONFIG_PAGING is selected, then parts of the 1-to-1 virtual memory
* map probably do not apply because paging logic will probably partition
* the SRAM section differently. In particular, if the page table is located
* at the end of SRAM, then the virtual page table address defined below
* will probably be in error. In that case PGTABLE_BASE_VADDR is defined
* in the file mmu.h
*
* We must declare the page table at the bottom or at the top of internal
* SRAM. We pick the bottom of internal SRAM *unless* there are vectors
* in the way at that position.
*/
# if defined(CONFIG_ARCH_LOWVECTORS)
/* In this case, page table must lie at the top 16Kb of OCMC0 RAM. */
# define PGTABLE_BASE_PADDR (AM335X_OCMC0_PADDR + AM335X_OCMC0_SIZE - PGTABLE_SIZE)
# define PGTABLE_BASE_VADDR (AM335X_OCMC0_VADDR + AM335X_OCMC0_SIZE - PGTABLE_SIZE)
# define PGTABLE_IN_HIGHSRAM 1
/* We will force the IDLE stack to precede the page table */
# define IDLE_STACK_PBASE (PGTABLE_BASE_PADDR - CONFIG_IDLETHREAD_STACKSIZE)
# define IDLE_STACK_VBASE (PGTABLE_BASE_VADDR - CONFIG_IDLETHREAD_STACKSIZE)
//# define IDLE_STACK_PBASE 0x8d000000
//# define IDLE_STACK_VBASE 0x8d000000
# else /* CONFIG_ARCH_LOWVECTORS */
/* Otherwise, the vectors lie at another location (perhaps in NOR FLASH,
* perhaps elsewhere in OCMC0 RAM). The page table will then be positioned
* at the first 16Kb of OCMC0 RAM.
*/
# define PGTABLE_BASE_PADDR AM335X_OCMC0_PADDR
# define PGTABLE_BASE_VADDR AM335X_OCMC0_VADDR
# define PGTABLE_IN_LOWSRAM 1
/* We will force the IDLE stack to follow the page table */
# define IDLE_STACK_PBASE (PGTABLE_BASE_PADDR + PGTABLE_SIZE)
# define IDLE_STACK_VBASE (PGTABLE_BASE_VADDR + PGTABLE_SIZE)
# endif /* CONFIG_ARCH_LOWVECTORS */
/* Note that the page table does not lie in the same address space as does the
* mapped RAM in either case. So we will need to create a special mapping for
* the page table at boot time.
*/
# define ARMV7A_PGTABLE_MAPPING 1
#endif /* PGTABLE_BASE_PADDR || PGTABLE_BASE_VADDR */
/* Level 2 Page table start addresses.
*
* 16Kb of memory is reserved hold the page table for the virtual mappings. A
* portion of this table is not accessible in the virtual address space (for
* normal operation).
*/
#if !defined(CONFIG_ARCH_LOWVECTORS)
/* Vector L2 page table offset/size */
# define VECTOR_L2_OFFSET 0x000000400
# define VECTOR_L2_SIZE 0x000000bfc
/* Vector L2 page table base addresses */
# define VECTOR_L2_PBASE (PGTABLE_BASE_PADDR + VECTOR_L2_OFFSET)
# define VECTOR_L2_VBASE (PGTABLE_BASE_VADDR + VECTOR_L2_OFFSET)
/* Vector L2 page table end addresses */
# define VECTOR_L2_END_PADDR (VECTOR_L2_PBASE + VECTOR_L2_SIZE)
# define VECTOR_L2_END_VADDR (VECTOR_L2_VBASE + VECTOR_L2_SIZE)
#endif /* !CONFIG_ARCH_LOWVECTORS */
/* Paging L2 page table offset/size */
#define PGTABLE_L2_START_PADDR (AM335X_DDR_PSECTION + AM335X_DDR_MAPOFFSET + AM335X_DDR_MAPSIZE)
#define PGTABLE_BROM_OFFSET 0x3ffc
#define PGTABLE_L2_OFFSET ((PGTABLE_L2_START_PADDR >> 18) & ~3)
#define PGTABLE_L2_SIZE (PGTABLE_BROM_OFFSET - PGTABLE_L2_OFFSET)
/* Paging L2 page table base addresses
*
* NOTE: If CONFIG_PAGING is defined, mmu.h will re-assign the virtual
* address of the page table.
*/
#define PGTABLE_L2_PBASE (PGTABLE_BASE_PADDR + PGTABLE_L2_OFFSET)
#define PGTABLE_L2_VBASE (PGTABLE_BASE_VADDR + PGTABLE_L2_OFFSET)
/* Paging L2 page table end addresses */
#define PGTABLE_L2_END_PADDR (PGTABLE_L2_PBASE + PGTABLE_L2_SIZE)
#define PGTABLE_L2_END_VADDR (PGTABLE_L2_VBASE + PGTABLE_L2_SIZE)
/* Base address of the interrupt vector table.
*
* AM335X_VECTOR_PADDR - Unmapped, physical address of vector table in SRAM
* AM335X_VECTOR_VSRAM - Virtual address of vector table in SRAM
* AM335X_VECTOR_VADDR - Virtual address of vector table (0x00000000 or 0xffff0000)
*/
#define VECTOR_TABLE_SIZE 0x00010000
/* REVISIT: These definitions are not used: The vector table is at some
* arbitrary (but aligned) position in RAM or NOR FLASH and is positioned
* using the VBAR register. For AM335X at start of OCMC0 RAM by default.
*/
#ifdef CONFIG_ARCH_LOWVECTORS /* Vectors located at 0x0000:0000 */
# define AM335X_VECTOR_PADDR AM335X_OCMC0_PADDR
# define AM335X_VECTOR_VSRAM AM335X_OCMC0_VADDR
# define AM335X_VECTOR_VADDR 0x00000000
#else /* Vectors located at 0xffff:0000 -- this probably does not work */
# define AM335X_VECTOR_PADDR (AM335X_OCMC0_PADDR + AM335X_OCMC0_SIZE - VECTOR_TABLE_SIZE)
# define AM335X_VECTOR_VSRAM (AM335X_OCMC0_VADDR + AM335X_OCMC0_SIZE - VECTOR_TABLE_SIZE)
# define AM335X_VECTOR_VADDR 0xffff0000
#endif
/************************************************************************************
* Public Types
************************************************************************************/
/************************************************************************************
* Public Data
************************************************************************************/
/************************************************************************************
* Public Functions
************************************************************************************/
#endif /* __ARCH_ARM_SRC_AM335X_CHIP_AM3358_MEMORYMAP_H */

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/************************************************************************************
* arch/arm/src/am335x/chip/am3358_pinmux.h
*
* Copyright (C) 2018 Petro Karashchenko. All rights reserved.
* Author: Petro Karashchenko <petro.karashchneko@gmail.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_AM335X_CHIP_AM3358_PINMUX_H
#define __ARCH_ARM_SRC_AM335X_CHIP_AM3358_PINMUX_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
#include "chip/am335x_memorymap.h"
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* Alternate Pin Functions.
*
* Alternative pin selections are provided with a numeric suffix like _1, _2, etc.
* Drivers, however, will use the pin selection without the numeric suffix.
* Additional definitions are required in the board.h file. For example, if
* UART2 RXD connects via the MMC0_CLK pin, then the following definition should
* appear in the board.h header file for that board:
*
* #define GPIO_UART2_RXD GPIO_UART2_RXD_1
*
* The driver will then automatically configure to use the MMC0_CLK pin for UART2 RXD.*/
/* WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!!
* Additional effort is required to select specific GPIO options (such as pull-up or
* -down). Just the basics are defined for most pins in this file at the present
* time.
*/
/* Debug Subsystem */
#define GPIO_EMU0 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_EMU0_INDEX) | PINMUX_MODE0 | PINMUX_RX_ENABLE)
#define GPIO_EMU1 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_EMU1_INDEX) | PINMUX_MODE0 | PINMUX_RX_ENABLE)
#define GPIO_EMU2_1 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_SPI0_SCLK_INDEX) | PINMUX_MODE6 | PINMUX_RX_ENABLE)
#define GPIO_EMU2_2 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MCASP0_FSR_INDEX) | PINMUX_MODE4 | PINMUX_RX_ENABLE)
#define GPIO_EMU2_3 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_XDMA_EVENT_INTR0_INDEX) | PINMUX_MODE6 | PINMUX_RX_ENABLE)
#define GPIO_EMU3_1 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_SPI0_D0_INDEX) | PINMUX_MODE6 | PINMUX_RX_ENABLE)
#define GPIO_EMU3_2 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MCASP0_AXR1_INDEX) | PINMUX_MODE4 | PINMUX_RX_ENABLE)
#define GPIO_EMU3_3 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_XDMA_EVENT_INTR1_INDEX) | PINMUX_MODE6 | PINMUX_RX_ENABLE)
#define GPIO_EMU4_1 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_CSN3_INDEX) | PINMUX_MODE6 | PINMUX_RX_ENABLE)
#define GPIO_EMU4_2 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_SPI0_CS1_INDEX) | PINMUX_MODE6 | PINMUX_RX_ENABLE)
#define GPIO_EMU4_3 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MCASP0_AHCLKX_INDEX) | PINMUX_MODE4 | PINMUX_RX_ENABLE)
/* LCD Controller */
#define GPIO_LCD_PCLK (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_LCD_PCLK_INDEX) | PINMUX_MODE0)
#define GPIO_LCD_DATA0 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_LCD_DATA0_INDEX) | PINMUX_MODE0 | PINMUX_RX_ENABLE)
#define GPIO_LCD_DATA1 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_LCD_DATA1_INDEX) | PINMUX_MODE0 | PINMUX_RX_ENABLE)
#define GPIO_LCD_DATA2 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_LCD_DATA2_INDEX) | PINMUX_MODE0 | PINMUX_RX_ENABLE)
#define GPIO_LCD_DATA3 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_LCD_DATA3_INDEX) | PINMUX_MODE0 | PINMUX_RX_ENABLE)
#define GPIO_LCD_DATA4 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_LCD_DATA4_INDEX) | PINMUX_MODE0 | PINMUX_RX_ENABLE)
#define GPIO_LCD_DATA5 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_LCD_DATA5_INDEX) | PINMUX_MODE0 | PINMUX_RX_ENABLE)
#define GPIO_LCD_DATA6 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_LCD_DATA6_INDEX) | PINMUX_MODE0 | PINMUX_RX_ENABLE)
#define GPIO_LCD_DATA7 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_LCD_DATA7_INDEX) | PINMUX_MODE0 | PINMUX_RX_ENABLE)
#define GPIO_LCD_DATA8 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_LCD_DATA8_INDEX) | PINMUX_MODE0 | PINMUX_RX_ENABLE)
#define GPIO_LCD_DATA9 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_LCD_DATA9_INDEX) | PINMUX_MODE0 | PINMUX_RX_ENABLE)
#define GPIO_LCD_DATA10 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_LCD_DATA10_INDEX) | PINMUX_MODE0 | PINMUX_RX_ENABLE)
#define GPIO_LCD_DATA11 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_LCD_DATA11_INDEX) | PINMUX_MODE0 | PINMUX_RX_ENABLE)
#define GPIO_LCD_DATA12 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_LCD_DATA12_INDEX) | PINMUX_MODE0 | PINMUX_RX_ENABLE)
#define GPIO_LCD_DATA13 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_LCD_DATA13_INDEX) | PINMUX_MODE0 | PINMUX_RX_ENABLE)
#define GPIO_LCD_DATA14 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_LCD_DATA14_INDEX) | PINMUX_MODE0 | PINMUX_RX_ENABLE)
#define GPIO_LCD_DATA15 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_LCD_DATA15_INDEX) | PINMUX_MODE0 | PINMUX_RX_ENABLE)
#define GPIO_LCD_DATA16 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_AD15_INDEX) | PINMUX_MODE1)
#define GPIO_LCD_DATA17 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_AD14_INDEX) | PINMUX_MODE1)
#define GPIO_LCD_DATA18 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_AD13_INDEX) | PINMUX_MODE1)
#define GPIO_LCD_DATA19 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_AD12_INDEX) | PINMUX_MODE1)
#define GPIO_LCD_DATA20 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_AD11_INDEX) | PINMUX_MODE1)
#define GPIO_LCD_DATA21 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_AD10_INDEX) | PINMUX_MODE1)
#define GPIO_LCD_DATA22 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_AD9_INDEX) | PINMUX_MODE1)
#define GPIO_LCD_DATA23 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_AD8_INDEX) | PINMUX_MODE1)
#define GPIO_LCD_HSYNC (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_LCD_HSYNC_INDEX) | PINMUX_MODE0)
#define GPIO_LCD_VSYNC (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_LCD_VSYNC_INDEX) | PINMUX_MODE0)
#define GPIO_LCD_AC_BIAS_EN (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_LCD_AC_BIAS_EN_INDEX) | PINMUX_MODE0)
#define GPIO_LCD_MEMORY_CLK_1 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_CLK_INDEX) | PINMUX_MODE1)
#define GPIO_LCD_MEMORY_CLK_2 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MII1_RX_DV_INDEX) | PINMUX_MODE1)
/* General Purpose Memory Controller */
#define GPIO_GPMC_A0_1 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_A0_INDEX) | PINMUX_MODE0)
#define GPIO_GPMC_A0_2 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_LCD_DATA0_INDEX) | PINMUX_MODE1)
#define GPIO_GPMC_A1_1 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_A1_INDEX) | PINMUX_MODE0)
#define GPIO_GPMC_A1_2 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_LCD_DATA1_INDEX) | PINMUX_MODE1)
#define GPIO_GPMC_A1_3 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_LCD_VSYNC_INDEX) | PINMUX_MODE2)
#define GPIO_GPMC_A2_1 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_A2_INDEX) | PINMUX_MODE0)
#define GPIO_GPMC_A2_2 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_LCD_DATA2_INDEX) | PINMUX_MODE1)
#define GPIO_GPMC_A2_3 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_LCD_HSYNC_INDEX) | PINMUX_MODE2)
#define GPIO_GPMC_A3_1 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_A3_INDEX) | PINMUX_MODE0)
#define GPIO_GPMC_A3_2 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_CSN3_INDEX) | PINMUX_MODE1)
#define GPIO_GPMC_A3_3 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_LCD_DATA3_INDEX) | PINMUX_MODE1)
#define GPIO_GPMC_A4_1 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_A4_INDEX) | PINMUX_MODE0)
#define GPIO_GPMC_A4_2 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_LCD_DATA4_INDEX) | PINMUX_MODE1)
#define GPIO_GPMC_A5_1 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_A5_INDEX) | PINMUX_MODE0)
#define GPIO_GPMC_A5_2 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_LCD_DATA5_INDEX) | PINMUX_MODE1)
#define GPIO_GPMC_A6_1 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_A6_INDEX) | PINMUX_MODE0)
#define GPIO_GPMC_A6_2 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_LCD_DATA6_INDEX) | PINMUX_MODE1)
#define GPIO_GPMC_A7_1 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_A7_INDEX) | PINMUX_MODE0)
#define GPIO_GPMC_A7_2 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_LCD_DATA7_INDEX) | PINMUX_MODE1)
#define GPIO_GPMC_A8_1 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_A8_INDEX) | PINMUX_MODE0)
#define GPIO_GPMC_A8_2 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_LCD_VSYNC_INDEX) | PINMUX_MODE1)
#define GPIO_GPMC_A9_1 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_A9_INDEX) | PINMUX_MODE0)
#define GPIO_GPMC_A9_2 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_LCD_HSYNC_INDEX) | PINMUX_MODE1)
#define GPIO_GPMC_A10_1 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_A10_INDEX) | PINMUX_MODE0)
#define GPIO_GPMC_A10_2 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_LCD_PCLK_INDEX) | PINMUX_MODE1)
#define GPIO_GPMC_A11_1 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_A11_INDEX) | PINMUX_MODE0)
#define GPIO_GPMC_A11_2 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_LCD_AC_BIAS_EN_INDEX) | PINMUX_MODE1)
#define GPIO_GPMC_A12 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_LCD_DATA8_INDEX) | PINMUX_MODE1)
#define GPIO_GPMC_A13 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_LCD_DATA9_INDEX) | PINMUX_MODE1)
#define GPIO_GPMC_A14 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_LCD_DATA10_INDEX) | PINMUX_MODE1)
#define GPIO_GPMC_A15 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_LCD_DATA11_INDEX) | PINMUX_MODE1)
#define GPIO_GPMC_A16_1 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_LCD_DATA12_INDEX) | PINMUX_MODE1)
#define GPIO_GPMC_A16_2 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_A0_INDEX) | PINMUX_MODE4)
#define GPIO_GPMC_A17_1 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_LCD_DATA13_INDEX) | PINMUX_MODE1)
#define GPIO_GPMC_A17_2 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_A1_INDEX) | PINMUX_MODE4)
#define GPIO_GPMC_A18_1 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_LCD_DATA14_INDEX) | PINMUX_MODE1)
#define GPIO_GPMC_A18_2 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_A2_INDEX) | PINMUX_MODE4)
#define GPIO_GPMC_A19_1 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_LCD_DATA15_INDEX) | PINMUX_MODE1)
#define GPIO_GPMC_A19_2 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_A3_INDEX) | PINMUX_MODE4)
#define GPIO_GPMC_A20_1 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MMC0_DAT3_INDEX) | PINMUX_MODE1)
#define GPIO_GPMC_A20_2 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_A4_INDEX) | PINMUX_MODE4)
#define GPIO_GPMC_A21_1 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MMC0_DAT2_INDEX) | PINMUX_MODE1)
#define GPIO_GPMC_A21_2 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_A5_INDEX) | PINMUX_MODE4)
#define GPIO_GPMC_A22_1 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MMC0_DAT1_INDEX) | PINMUX_MODE1)
#define GPIO_GPMC_A22_2 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_A6_INDEX) | PINMUX_MODE4)
#define GPIO_GPMC_A23_1 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MMC0_DAT0_INDEX) | PINMUX_MODE1)
#define GPIO_GPMC_A23_2 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_A7_INDEX) | PINMUX_MODE4)
#define GPIO_GPMC_A24_1 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MMC0_CLK_INDEX) | PINMUX_MODE1)
#define GPIO_GPMC_A24_2 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_A8_INDEX) | PINMUX_MODE4)
#define GPIO_GPMC_A25_1 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MMC0_CMD_INDEX) | PINMUX_MODE1)
#define GPIO_GPMC_A25_2 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_A9_INDEX) | PINMUX_MODE4)
#define GPIO_GPMC_A26 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_A10_INDEX) | PINMUX_MODE4)
#define GPIO_GPMC_A27 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_A11_INDEX) | PINMUX_MODE4)
#define GPIO_GPMC_AD0 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_AD0_INDEX) | PINMUX_MODE0 | PINMUX_RX_ENABLE)
#define GPIO_GPMC_AD1 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_AD1_INDEX) | PINMUX_MODE0 | PINMUX_RX_ENABLE)
#define GPIO_GPMC_AD2 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_AD2_INDEX) | PINMUX_MODE0 | PINMUX_RX_ENABLE)
#define GPIO_GPMC_AD3 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_AD3_INDEX) | PINMUX_MODE0 | PINMUX_RX_ENABLE)
#define GPIO_GPMC_AD4 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_AD4_INDEX) | PINMUX_MODE0 | PINMUX_RX_ENABLE)
#define GPIO_GPMC_AD5 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_AD5_INDEX) | PINMUX_MODE0 | PINMUX_RX_ENABLE)
#define GPIO_GPMC_AD6 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_AD6_INDEX) | PINMUX_MODE0 | PINMUX_RX_ENABLE)
#define GPIO_GPMC_AD7 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_AD7_INDEX) | PINMUX_MODE0 | PINMUX_RX_ENABLE)
#define GPIO_GPMC_AD8 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_AD8_INDEX) | PINMUX_MODE0 | PINMUX_RX_ENABLE)
#define GPIO_GPMC_AD9 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_AD9_INDEX) | PINMUX_MODE0 | PINMUX_RX_ENABLE)
#define GPIO_GPMC_AD10 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_AD10_INDEX) | PINMUX_MODE0 | PINMUX_RX_ENABLE)
#define GPIO_GPMC_AD11 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_AD11_INDEX) | PINMUX_MODE0 | PINMUX_RX_ENABLE)
#define GPIO_GPMC_AD12 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_AD12_INDEX) | PINMUX_MODE0 | PINMUX_RX_ENABLE)
#define GPIO_GPMC_AD13 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_AD13_INDEX) | PINMUX_MODE0 | PINMUX_RX_ENABLE)
#define GPIO_GPMC_AD14 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_AD14_INDEX) | PINMUX_MODE0 | PINMUX_RX_ENABLE)
#define GPIO_GPMC_AD15 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_AD15_INDEX) | PINMUX_MODE0 | PINMUX_RX_ENABLE)
#define GPIO_GPMC_CSN0 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_CSN0_INDEX) | PINMUX_MODE0)
#define GPIO_GPMC_CSN1 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_CSN1_INDEX) | PINMUX_MODE0)
#define GPIO_GPMC_CSN2 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_CSN2_INDEX) | PINMUX_MODE0)
#define GPIO_GPMC_CSN3 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_CSN3_INDEX) | PINMUX_MODE0)
#define GPIO_GPMC_CSN4 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_WAIT0_INDEX) | PINMUX_MODE2)
#define GPIO_GPMC_CSN5 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_WPN_INDEX) | PINMUX_MODE2)
#define GPIO_GPMC_CSN6 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_BEN1_INDEX) | PINMUX_MODE2)
#define GPIO_GPMC_CLK_1 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_CSN1_INDEX) | PINMUX_MODE1 | PINMUX_RX_ENABLE)
#define GPIO_GPMC_CLK_2 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_CLK_INDEX) | PINMUX_MODE0 | PINMUX_RX_ENABLE)
#define GPIO_GPMC_ADVN_ALE (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_ADVN_ALE_INDEX) | PINMUX_MODE0)
#define GPIO_GPMC_OEN_REN (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_OEN_REN_INDEX) | PINMUX_MODE0)
#define GPIO_GPMC_WEN (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_WEN_INDEX) | PINMUX_MODE0)
#define GPIO_GPMC_BE0N_CLE (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_BEN0_CLE_INDEX) | PINMUX_MODE0)
#define GPIO_GPMC_BE1N_1 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_BEN1_INDEX) | PINMUX_MODE0)
#define GPIO_GPMC_BE1N_2 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_CSN2_INDEX) | PINMUX_MODE1)
#define GPIO_GPMC_WPN (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_WPN_INDEX) | PINMUX_MODE0)
#define GPIO_GPMC_WAIT0 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_WAIT0_INDEX) | PINMUX_MODE0 | PINMUX_RX_ENABLE)
#define GPIO_GPMC_WAIT1 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_CLK_INDEX) | PINMUX_MODE2 | PINMUX_RX_ENABLE)
#define GPIO_GPMC_DIR (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_BEN1_INDEX) | PINMUX_MODE4)
/* Miscellaneous */
#define GPIO_CLKOUT1 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_XDMA_EVENT_INTR0_INDEX) | PINMUX_MODE3)
#define GPIO_CLKOUT2 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_XDMA_EVENT_INTR1_INDEX) | PINMUX_MODE3)
#define GPIO_EXT_WAKEUP (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_EXT_WAKEUP_INDEX) | PINMUX_MODE0 | PINMUX_RX_ENABLE)
#define GPIO_EXTINTN (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_NNMI_INDEX) | PINMUX_MODE0 | PINMUX_RX_ENABLE)
#define GPIO_TCLKIN (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_XDMA_EVENT_INTR1_INDEX) | PINMUX_MODE2 | PINMUX_RX_ENABLE)
#define GPIO_XDMA_EVENT_INTR0 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_XDMA_EVENT_INTR0_INDEX) | PINMUX_MODE0 | PINMUX_RX_ENABLE)
#define GPIO_XDMA_EVENT_INTR1 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_XDMA_EVENT_INTR1_INDEX) | PINMUX_MODE0 | PINMUX_RX_ENABLE)
#define GPIO_XDMA_EVENT_INTR2_1 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_RMII1_REF_CLK_INDEX) | PINMUX_MODE1 | PINMUX_RX_ENABLE)
#define GPIO_XDMA_EVENT_INTR2_2 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_SPI0_CS1_INDEX) | PINMUX_MODE4 | PINMUX_RX_ENABLE)
#define GPIO_XDMA_EVENT_INTR2_3 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_ECAP0_IN_PWM0_OUT_INDEX) | PINMUX_MODE6 | PINMUX_RX_ENABLE)
/* eCAP */
#define GPIO_ECAP0_IN_PWM0_OUT (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_ECAP0_IN_PWM0_OUT_INDEX) | PINMUX_MODE0 | PINMUX_RX_ENABLE)
#define GPIO_ECAP1_IN_PWM1_OUT_1 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_SPI0_CS1_INDEX) | PINMUX_MODE2 | PINMUX_RX_ENABLE)
#define GPIO_ECAP1_IN_PWM1_OUT_2 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_UART0_TXD_INDEX) | PINMUX_MODE4 | PINMUX_RX_ENABLE)
#define GPIO_ECAP1_IN_PWM1_OUT_3 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_I2C0_SCL_INDEX) | PINMUX_MODE3 | PINMUX_RX_ENABLE)
#define GPIO_ECAP2_IN_PWM2_OUT_1 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_UART0_RXD_INDEX) | PINMUX_MODE4 | PINMUX_RX_ENABLE)
#define GPIO_ECAP2_IN_PWM2_OUT_2 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_I2C0_SDA_INDEX) | PINMUX_MODE3 | PINMUX_RX_ENABLE)
#define GPIO_ECAP2_IN_PWM2_OUT_3 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MCASP0_AHCLKR_INDEX) | PINMUX_MODE4 | PINMUX_RX_ENABLE)
/* eHRPWM */
#define GPIO_EHRPWM0A_1 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_SPI0_SCLK_INDEX) | PINMUX_MODE3)
#define GPIO_EHRPWM0A_2 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MCASP0_ACLKX_INDEX) | PINMUX_MODE1)
#define GPIO_EHRPWM0B_1 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_SPI0_D0_INDEX) | PINMUX_MODE3)
#define GPIO_EHRPWM0B_2 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MCASP0_FSX_INDEX) | PINMUX_MODE1)
#define GPIO_EHRPWM0_SYNCI_1 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_SPI0_CS0_INDEX) | PINMUX_MODE3 | PINMUX_RX_ENABLE)
#define GPIO_EHRPWM0_SYNCI_2 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MCASP0_AHCLKR_INDEX) | PINMUX_MODE1 | PINMUX_RX_ENABLE)
#define GPIO_EHRPWM0_SYNCO_1 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_AD11_INDEX) | PINMUX_MODE4)
#define GPIO_EHRPWM0_SYNCO_2 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_A1_INDEX) | PINMUX_MODE6)
#define GPIO_EHRPWM0_SYNCO_3 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_LCD_DATA3_INDEX) | PINMUX_MODE3)
#define GPIO_EHRPWM0_SYNCO_4 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_LCD_DATA9_INDEX) | PINMUX_MODE2)
#define GPIO_EHRPWM0_TRIPZONE_INPUT_1 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_SPI0_D1_INDEX) | PINMUX_MODE3 | PINMUX_RX_ENABLE)
#define GPIO_EHRPWM0_TRIPZONE_INPUT_2 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MCASP0_AXR0_INDEX) | PINMUX_MODE1 | PINMUX_RX_ENABLE)
#define GPIO_EHRPWM1A_1 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_A2_INDEX) | PINMUX_MODE6)
#define GPIO_EHRPWM1A_2 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_LCD_DATA10_INDEX) | PINMUX_MODE2)
#define GPIO_EHRPWM1B_1 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_A3_INDEX) | PINMUX_MODE6)
#define GPIO_EHRPWM1B_2 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_LCD_DATA11_INDEX) | PINMUX_MODE2)
#define GPIO_EHRPWM1_TRIPZONE_INPUT_1 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_A0_INDEX) | PINMUX_MODE6 | PINMUX_RX_ENABLE)
#define GPIO_EHRPWM1_TRIPZONE_INPUT_2 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_LCD_DATA8_INDEX) | PINMUX_MODE2 | PINMUX_RX_ENABLE)
#define GPIO_EHRPWM2A_1 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_AD8_INDEX) | PINMUX_MODE4)
#define GPIO_EHRPWM2A_2 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_LCD_DATA0_INDEX) | PINMUX_MODE3)
#define GPIO_EHRPWM2B_1 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_AD9_INDEX) | PINMUX_MODE4)
#define GPIO_EHRPWM2B_2 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_LCD_DATA1_INDEX) | PINMUX_MODE3)
#define GPIO_EHRPWM2_TRIPZONE_INPUT_1 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_AD10_INDEX) | PINMUX_MODE4 | PINMUX_RX_ENABLE)
#define GPIO_EHRPWM2_TRIPZONE_INPUT_2 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_LCD_DATA2_INDEX) | PINMUX_MODE3 | PINMUX_RX_ENABLE)
/* eQEP */
#define GPIO_EQEP0A_IN_1 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MCASP0_ACLKR_INDEX) | PINMUX_MODE1 | PINMUX_RX_ENABLE)
#define GPIO_EQEP0A_IN_2 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MII1_TXD1_INDEX) | PINMUX_MODE5 | PINMUX_RX_ENABLE)
#define GPIO_EQEP0B_IN_1 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MCASP0_FSR_INDEX) | PINMUX_MODE1 | PINMUX_RX_ENABLE)
#define GPIO_EQEP0B_IN_2 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MII1_TXD0_INDEX) | PINMUX_MODE5 | PINMUX_RX_ENABLE)
#define GPIO_EQEP0_INDEX_1 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MCASP0_AXR1_INDEX) | PINMUX_MODE1 | PINMUX_RX_ENABLE)
#define GPIO_EQEP0_INDEX_2 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MII1_TX_EN_INDEX) | PINMUX_MODE5 | PINMUX_RX_ENABLE)
#define GPIO_EQEP0_STROBE_1 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MCASP0_AHCLKX_INDEX) | PINMUX_MODE1 | PINMUX_RX_ENABLE)
#define GPIO_EQEP0_STROBE_2 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MII1_RXD1_INDEX) | PINMUX_MODE5 | PINMUX_RX_ENABLE)
#define GPIO_EQEP1A_IN_1 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_A4_INDEX) | PINMUX_MODE6 | PINMUX_RX_ENABLE)
#define GPIO_EQEP1A_IN_2 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_LCD_DATA12_INDEX) | PINMUX_MODE2 | PINMUX_RX_ENABLE)
#define GPIO_EQEP1B_IN_1 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_A5_INDEX) | PINMUX_MODE6 | PINMUX_RX_ENABLE)
#define GPIO_EQEP1B_IN_2 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_LCD_DATA13_INDEX) | PINMUX_MODE2 | PINMUX_RX_ENABLE)
#define GPIO_EQEP1_INDEX_1 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_A6_INDEX) | PINMUX_MODE6 | PINMUX_RX_ENABLE)
#define GPIO_EQEP1_INDEX_2 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_LCD_DATA14_INDEX) | PINMUX_MODE2 | PINMUX_RX_ENABLE)
#define GPIO_EQEP1_STROBE_1 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_A7_INDEX) | PINMUX_MODE6 | PINMUX_RX_ENABLE)
#define GPIO_EQEP1_STROBE_2 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_LCD_DATA15_INDEX) | PINMUX_MODE2 | PINMUX_RX_ENABLE)
#define GPIO_EQEP2A_IN_1 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_LCD_DATA4_INDEX) | PINMUX_MODE3 | PINMUX_RX_ENABLE)
#define GPIO_EQEP2A_IN_2 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_AD12_INDEX) | PINMUX_MODE4 | PINMUX_RX_ENABLE)
#define GPIO_EQEP2B_IN_1 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_LCD_DATA5_INDEX) | PINMUX_MODE3 | PINMUX_RX_ENABLE)
#define GPIO_EQEP2B_IN_2 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_AD13_INDEX) | PINMUX_MODE4 | PINMUX_RX_ENABLE)
#define GPIO_EQEP2_INDEX_1 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_LCD_DATA6_INDEX) | PINMUX_MODE3 | PINMUX_RX_ENABLE)
#define GPIO_EQEP2_INDEX_2 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_AD14_INDEX) | PINMUX_MODE4 | PINMUX_RX_ENABLE)
#define GPIO_EQEP2_STROBE_1 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_LCD_DATA7_INDEX) | PINMUX_MODE3 | PINMUX_RX_ENABLE)
#define GPIO_EQEP2_STROBE_2 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_AD15_INDEX) | PINMUX_MODE4 | PINMUX_RX_ENABLE)
/* Timer */
#define GPIO_TIMER4_1 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_XDMA_EVENT_INTR0_INDEX) | PINMUX_MODE2 | PINMUX_RX_ENABLE)
#define GPIO_TIMER4_2 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_I2C0_SDA_INDEX) | PINMUX_MODE1 | PINMUX_RX_ENABLE)
#define GPIO_TIMER4_3 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MII1_TX_EN_INDEX) | PINMUX_MODE3 | PINMUX_RX_ENABLE)
#define GPIO_TIMER4_4 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_ADVN_ALE_INDEX) | PINMUX_MODE2 | PINMUX_RX_ENABLE)
#define GPIO_TIMER5_1 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_UART1_RTSN_INDEX) | PINMUX_MODE1 | PINMUX_RX_ENABLE)
#define GPIO_TIMER5_2 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MMC0_DAT3_INDEX) | PINMUX_MODE3 | PINMUX_RX_ENABLE)
#define GPIO_TIMER5_3 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MDC_INDEX) | PINMUX_MODE1 | PINMUX_RX_ENABLE)
#define GPIO_TIMER5_4 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_BEN0_CLE_INDEX) | PINMUX_MODE2 | PINMUX_RX_ENABLE)
#define GPIO_TIMER6_1 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_WEN_INDEX) | PINMUX_MODE2 | PINMUX_RX_ENABLE)
#define GPIO_TIMER6_2 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MDIO_INDEX) | PINMUX_MODE1 | PINMUX_RX_ENABLE)
#define GPIO_TIMER6_3 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MMC0_DAT2_INDEX) | PINMUX_MODE3 | PINMUX_RX_ENABLE)
#define GPIO_TIMER6_4 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_UART1_CTSN_INDEX) | PINMUX_MODE1 | PINMUX_RX_ENABLE)
#define GPIO_TIMER7_1 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_OEN_REN_INDEX) | PINMUX_MODE2 | PINMUX_RX_ENABLE)
#define GPIO_TIMER7_2 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_I2C0_SCL_INDEX) | PINMUX_MODE1 | PINMUX_RX_ENABLE)
#define GPIO_TIMER7_3 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_UART0_CTSN_INDEX) | PINMUX_MODE5 | PINMUX_RX_ENABLE)
#define GPIO_TIMER7_4 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_XDMA_EVENT_INTR1_INDEX) | PINMUX_MODE4 | PINMUX_RX_ENABLE)
/* PRU-ICSS eCAP */
#define GPIO_PR1_ECAP0_CAPIN_APWM_1 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_ECAP0_IN_PWM0_OUT_INDEX) | PINMUX_MODE3 | PINMUX_RX_ENABLE)
#define GPIO_PR1_ECAP0_CAPIN_APWM_2 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_AD15_INDEX) | PINMUX_MODE5 | PINMUX_RX_ENABLE)
/* PRU-ICSS ECAT */
#define GPIO_PR1_EDC_LATCH0_IN_1 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_UART1_CTSN_INDEX) | PINMUX_MODE6 | PINMUX_RX_ENABLE)
#define GPIO_PR1_EDC_LATCH1_IN_2 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_UART1_RTSN_INDEX) | PINMUX_MODE6 | PINMUX_RX_ENABLE)
#define GPIO_PR1_EDC_SYNC0_OUT_1 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_UART0_CTSN_INDEX) | PINMUX_MODE6)
#define GPIO_PR1_EDC_SYNC1_OUT_2 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_UART0_RTSN_INDEX) | PINMUX_MODE6)
#define GPIO_PR1_EDIO_DATA_IN0 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_SPI0_D1_INDEX) | PINMUX_MODE5 | PINMUX_RX_ENABLE)
#define GPIO_PR1_EDIO_DATA_IN1 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_SPI0_CS0_INDEX) | PINMUX_MODE5 | PINMUX_RX_ENABLE)
#define GPIO_PR1_EDIO_DATA_IN2 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_LCD_VSYNC_INDEX) | PINMUX_MODE3 | PINMUX_RX_ENABLE)
#define GPIO_PR1_EDIO_DATA_IN3 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_LCD_HSYNC_INDEX) | PINMUX_MODE3 | PINMUX_RX_ENABLE)
#define GPIO_PR1_EDIO_DATA_IN4 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_LCD_PCLK_INDEX) | PINMUX_MODE3 | PINMUX_RX_ENABLE)
#define GPIO_PR1_EDIO_DATA_IN5 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_LCD_AC_BIAS_EN_INDEX) | PINMUX_MODE3 | PINMUX_RX_ENABLE)
#define GPIO_PR1_EDIO_DATA_IN6_1 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_CSN1_INDEX) | PINMUX_MODE3 | PINMUX_RX_ENABLE)
#define GPIO_PR1_EDIO_DATA_IN6_2 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_LCD_DATA6_INDEX) | PINMUX_MODE2 | PINMUX_RX_ENABLE)
#define GPIO_PR1_EDIO_DATA_IN7_1 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_CSN2_INDEX) | PINMUX_MODE3 | PINMUX_RX_ENABLE)
#define GPIO_PR1_EDIO_DATA_IN7_2 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_LCD_DATA7_INDEX) | PINMUX_MODE2 | PINMUX_RX_ENABLE)
#define GPIO_PR1_EDIO_DATA_OUT0 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_SPI0_D1_INDEX) | PINMUX_MODE6)
#define GPIO_PR1_EDIO_DATA_OUT1 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_SPI0_CS0_INDEX) | PINMUX_MODE6)
#define GPIO_PR1_EDIO_DATA_OUT2 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_LCD_VSYNC_INDEX) | PINMUX_MODE4)
#define GPIO_PR1_EDIO_DATA_OUT3 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_LCD_HSYNC_INDEX) | PINMUX_MODE4)
#define GPIO_PR1_EDIO_DATA_OUT4 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_LCD_PCLK_INDEX) | PINMUX_MODE4)
#define GPIO_PR1_EDIO_DATA_OUT5 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_LCD_AC_BIAS_EN_INDEX) | PINMUX_MODE4)
#define GPIO_PR1_EDIO_DATA_OUT6_1 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_CSN1_INDEX) | PINMUX_MODE4)
#define GPIO_PR1_EDIO_DATA_OUT6_2 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_LCD_DATA6_INDEX) | PINMUX_MODE4)
#define GPIO_PR1_EDIO_DATA_OUT7_1 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_CSN2_INDEX) | PINMUX_MODE4)
#define GPIO_PR1_EDIO_DATA_OUT7_2 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_LCD_DATA7_INDEX) | PINMUX_MODE4)
#define GPIO_PR1_EDIO_LATCH_IN (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_SPI0_D0_INDEX) | PINMUX_MODE5 | PINMUX_RX_ENABLE)
#define GPIO_PR1_EDIO_SOF (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_SPI0_SCLK_INDEX) | PINMUX_MODE5)
/* PRU-ICSS MDIO */
#define GPIO_PR1_MDIO_DATA (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_CSN3_INDEX) | PINMUX_MODE5 | PINMUX_RX_ENABLE)
#define GPIO_PR1_MDIO_MDCLK (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_CLK_INDEX) | PINMUX_MODE5)
/* PRU-ICSS MII */
#define GPIO_PR1_MII0_COL (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_AD9_INDEX) | PINMUX_MODE5 | PINMUX_RX_ENABLE)
#define GPIO_PR1_MII0_CRS_1 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_CSN3_INDEX) | PINMUX_MODE4 | PINMUX_RX_ENABLE)
#define GPIO_PR1_MII0_CRS_2 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_LCD_PCLK_INDEX) | PINMUX_MODE2 | PINMUX_RX_ENABLE)
#define GPIO_PR1_MII0_RXD0 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_LCD_DATA11_INDEX) | PINMUX_MODE5 | PINMUX_RX_ENABLE)
#define GPIO_PR1_MII0_RXD1 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_LCD_DATA10_INDEX) | PINMUX_MODE5 | PINMUX_RX_ENABLE)
#define GPIO_PR1_MII0_RXD2 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_LCD_DATA9_INDEX) | PINMUX_MODE5 | PINMUX_RX_ENABLE)
#define GPIO_PR1_MII0_RXD3 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_LCD_DATA8_INDEX) | PINMUX_MODE5 | PINMUX_RX_ENABLE)
#define GPIO_PR1_MII0_RXDV (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_LCD_DATA15_INDEX) | PINMUX_MODE5 | PINMUX_RX_ENABLE)
#define GPIO_PR1_MII0_RXER (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_LCD_DATA13_INDEX) | PINMUX_MODE5 | PINMUX_RX_ENABLE)
#define GPIO_PR1_MII0_RXLINK (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_LCD_DATA12_INDEX) | PINMUX_MODE5 | PINMUX_RX_ENABLE)
#define GPIO_PR1_MII0_TXD0_1 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_AD14_INDEX) | PINMUX_MODE5)
#define GPIO_PR1_MII0_TXD0_2 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_LCD_DATA5_INDEX) | PINMUX_MODE2)
#define GPIO_PR1_MII0_TXD1_1 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_AD13_INDEX) | PINMUX_MODE5)
#define GPIO_PR1_MII0_TXD1_2 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_LCD_DATA4_INDEX) | PINMUX_MODE2)
#define GPIO_PR1_MII0_TXD2_1 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_AD12_INDEX) | PINMUX_MODE5)
#define GPIO_PR1_MII0_TXD2_2 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_LCD_DATA3_INDEX) | PINMUX_MODE2)
#define GPIO_PR1_MII0_TXD3_1 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_AD11_INDEX) | PINMUX_MODE5)
#define GPIO_PR1_MII0_TXD3_2 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_LCD_DATA2_INDEX) | PINMUX_MODE2)
#define GPIO_PR1_MII0_TXEN_1 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_AD10_INDEX) | PINMUX_MODE5)
#define GPIO_PR1_MII0_TXEN_2 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_LCD_DATA1_INDEX) | PINMUX_MODE2)
#define GPIO_PR1_MII_MR0_CLK (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_LCD_DATA14_INDEX) | PINMUX_MODE5 | PINMUX_RX_ENABLE)
#define GPIO_PR1_MII_MT0_CLK_1 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_LCD_DATA0_INDEX) | PINMUX_MODE2 | PINMUX_RX_ENABLE)
#define GPIO_PR1_MII_MT0_CLK_2 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_AD8_INDEX) | PINMUX_MODE5 | PINMUX_RX_ENABLE)
#define GPIO_PR1_MII1_COL (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_WAIT0_INDEX) | PINMUX_MODE5 | PINMUX_RX_ENABLE)
#define GPIO_PR1_MII1_CRS_1 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_LCD_AC_BIAS_EN_INDEX) | PINMUX_MODE2 | PINMUX_RX_ENABLE)
#define GPIO_PR1_MII1_CRS_2 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_CLK_INDEX) | PINMUX_MODE4 | PINMUX_RX_ENABLE)
#define GPIO_PR1_MII1_RXD0 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_A8_INDEX) | PINMUX_MODE5 | PINMUX_RX_ENABLE)
#define GPIO_PR1_MII1_RXD1 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_A7_INDEX) | PINMUX_MODE5 | PINMUX_RX_ENABLE)
#define GPIO_PR1_MII1_RXD2 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_A6_INDEX) | PINMUX_MODE5 | PINMUX_RX_ENABLE)
#define GPIO_PR1_MII1_RXD3 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_A5_INDEX) | PINMUX_MODE5 | PINMUX_RX_ENABLE)
#define GPIO_PR1_MII1_RXDV (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_A10_INDEX) | PINMUX_MODE5 | PINMUX_RX_ENABLE)
#define GPIO_PR1_MII1_RXER (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_A11_INDEX) | PINMUX_MODE5 | PINMUX_RX_ENABLE)
#define GPIO_PR1_MII1_RXLINK (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_BEN1_INDEX) | PINMUX_MODE5 | PINMUX_RX_ENABLE)
#define GPIO_PR1_MII1_TXD0 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_A4_INDEX) | PINMUX_MODE5)
#define GPIO_PR1_MII1_TXD1 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_A3_INDEX) | PINMUX_MODE5)
#define GPIO_PR1_MII1_TXD2 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_A2_INDEX) | PINMUX_MODE5)
#define GPIO_PR1_MII1_TXD3 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_A1_INDEX) | PINMUX_MODE5)
#define GPIO_PR1_MII1_TXEN (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_WPN_INDEX) | PINMUX_MODE5)
#define GPIO_PR1_MII_MR1_CLK (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_A9_INDEX) | PINMUX_MODE5 | PINMUX_RX_ENABLE)
#define GPIO_PR1_MII_MT1_CLK (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_A0_INDEX) | PINMUX_MODE5 | PINMUX_RX_ENABLE)
/* PRU-ICSS UART0 */
#define GPIO_PR1_UART0_CTSN_1 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_SPI0_SCLK_INDEX) | PINMUX_MODE4 | PINMUX_RX_ENABLE)
#define GPIO_PR1_UART0_CTSN_2 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_UART1_CTSN_INDEX) | PINMUX_MODE5 | PINMUX_RX_ENABLE)
#define GPIO_PR1_UART0_RTSN_1 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_SPI0_D0_INDEX) | PINMUX_MODE4)
#define GPIO_PR1_UART0_RTSN_2 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_UART1_RTSN_INDEX) | PINMUX_MODE5)
#define GPIO_PR1_UART0_RXD_1 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_SPI0_D1_INDEX) | PINMUX_MODE4 | PINMUX_RX_ENABLE)
#define GPIO_PR1_UART0_RXD_2 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_UART1_RXD_INDEX) | PINMUX_MODE5 | PINMUX_RX_ENABLE)
#define GPIO_PR1_UART0_TXD_1 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_SPI0_CS0_INDEX) | PINMUX_MODE4)
#define GPIO_PR1_UART0_TXD_2 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_UART1_TXD_INDEX) | PINMUX_MODE5)
/* PRU-ICSS PRU0 General Purpose Inputs */
#define GPIO_PR1_PRU0_R31_0 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MCASP0_ACLKX_INDEX) | PINMUX_MODE6 | PINMUX_RX_ENABLE)
#define GPIO_PR1_PRU0_R31_1 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MCASP0_FSX_INDEX) | PINMUX_MODE6 | PINMUX_RX_ENABLE)
#define GPIO_PR1_PRU0_R31_2 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MCASP0_AXR0_INDEX) | PINMUX_MODE6 | PINMUX_RX_ENABLE)
#define GPIO_PR1_PRU0_R31_3 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MCASP0_AHCLKR_INDEX) | PINMUX_MODE6 | PINMUX_RX_ENABLE)
#define GPIO_PR1_PRU0_R31_4 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MCASP0_ACLKR_INDEX) | PINMUX_MODE6 | PINMUX_RX_ENABLE)
#define GPIO_PR1_PRU0_R31_5 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MCASP0_FSR_INDEX) | PINMUX_MODE6 | PINMUX_RX_ENABLE)
#define GPIO_PR1_PRU0_R31_6 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MCASP0_AXR1_INDEX) | PINMUX_MODE6 | PINMUX_RX_ENABLE)
#define GPIO_PR1_PRU0_R31_7 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MCASP0_AHCLKX_INDEX) | PINMUX_MODE6 | PINMUX_RX_ENABLE)
#define GPIO_PR1_PRU0_R31_8 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MMC0_DAT3_INDEX) | PINMUX_MODE6 | PINMUX_RX_ENABLE)
#define GPIO_PR1_PRU0_R31_9 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MMC0_DAT2_INDEX) | PINMUX_MODE6 | PINMUX_RX_ENABLE)
#define GPIO_PR1_PRU0_R31_10 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MMC0_DAT1_INDEX) | PINMUX_MODE6 | PINMUX_RX_ENABLE)
#define GPIO_PR1_PRU0_R31_11 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MMC0_DAT0_INDEX) | PINMUX_MODE6 | PINMUX_RX_ENABLE)
#define GPIO_PR1_PRU0_R31_12 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MMC0_CLK_INDEX) | PINMUX_MODE6 | PINMUX_RX_ENABLE)
#define GPIO_PR1_PRU0_R31_13 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MMC0_CMD_INDEX) | PINMUX_MODE6 | PINMUX_RX_ENABLE)
#define GPIO_PR1_PRU0_R31_14 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_AD14_INDEX) | PINMUX_MODE6 | PINMUX_RX_ENABLE)
#define GPIO_PR1_PRU0_R31_15 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_AD15_INDEX) | PINMUX_MODE6 | PINMUX_RX_ENABLE)
#define GPIO_PR1_PRU0_R31_16_1 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_UART1_TXD_INDEX) | PINMUX_MODE6 | PINMUX_RX_ENABLE)
#define GPIO_PR1_PRU0_R31_16_2 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_XDMA_EVENT_INTR1_INDEX) | PINMUX_MODE5 | PINMUX_RX_ENABLE)
/* PRU_ICSS PRU0 General Purpose Outputs */
#define GPIO_PR1_PRU0_R30_0 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MCASP0_ACLKX_INDEX) | PINMUX_MODE5)
#define GPIO_PR1_PRU0_R30_1 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MCASP0_FSX_INDEX) | PINMUX_MODE5)
#define GPIO_PR1_PRU0_R30_2 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MCASP0_AXR0_INDEX) | PINMUX_MODE5)
#define GPIO_PR1_PRU0_R30_3 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MCASP0_AHCLKR_INDEX) | PINMUX_MODE5)
#define GPIO_PR1_PRU0_R30_4 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MCASP0_ACLKR_INDEX) | PINMUX_MODE5)
#define GPIO_PR1_PRU0_R30_5 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MCASP0_FSR_INDEX) | PINMUX_MODE5)
#define GPIO_PR1_PRU0_R30_6 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MCASP0_AXR1_INDEX) | PINMUX_MODE5)
#define GPIO_PR1_PRU0_R30_7 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MCASP0_AHCLKX_INDEX) | PINMUX_MODE5)
#define GPIO_PR1_PRU0_R30_8 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MMC0_DAT3_INDEX) | PINMUX_MODE5)
#define GPIO_PR1_PRU0_R30_9 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MMC0_DAT2_INDEX) | PINMUX_MODE5)
#define GPIO_PR1_PRU0_R30_10 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MMC0_DAT1_INDEX) | PINMUX_MODE5)
#define GPIO_PR1_PRU0_R30_11 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MMC0_DAT0_INDEX) | PINMUX_MODE5)
#define GPIO_PR1_PRU0_R30_12 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MMC0_CLK_INDEX) | PINMUX_MODE5)
#define GPIO_PR1_PRU0_R30_13 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MMC0_CMD_INDEX) | PINMUX_MODE5)
#define GPIO_PR1_PRU0_R30_14 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_AD12_INDEX) | PINMUX_MODE6)
#define GPIO_PR1_PRU0_R30_15 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_AD13_INDEX) | PINMUX_MODE6)
/* PRU-ICSS PRU1 General Purpose Inputs */
#define GPIO_PR1_PRU1_R31_0 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_LCD_DATA0_INDEX) | PINMUX_MODE6 | PINMUX_RX_ENABLE)
#define GPIO_PR1_PRU1_R31_1 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_LCD_DATA1_INDEX) | PINMUX_MODE6 | PINMUX_RX_ENABLE)
#define GPIO_PR1_PRU1_R31_2 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_LCD_DATA2_INDEX) | PINMUX_MODE6 | PINMUX_RX_ENABLE)
#define GPIO_PR1_PRU1_R31_3 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_LCD_DATA3_INDEX) | PINMUX_MODE6 | PINMUX_RX_ENABLE)
#define GPIO_PR1_PRU1_R31_4 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_LCD_DATA4_INDEX) | PINMUX_MODE6 | PINMUX_RX_ENABLE)
#define GPIO_PR1_PRU1_R31_5 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_LCD_DATA5_INDEX) | PINMUX_MODE6 | PINMUX_RX_ENABLE)
#define GPIO_PR1_PRU1_R31_6 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_LCD_DATA6_INDEX) | PINMUX_MODE6 | PINMUX_RX_ENABLE)
#define GPIO_PR1_PRU1_R31_7 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_LCD_DATA7_INDEX) | PINMUX_MODE6 | PINMUX_RX_ENABLE)
#define GPIO_PR1_PRU1_R31_8 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_LCD_VSYNC_INDEX) | PINMUX_MODE6 | PINMUX_RX_ENABLE)
#define GPIO_PR1_PRU1_R31_9 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_LCD_HSYNC_INDEX) | PINMUX_MODE6 | PINMUX_RX_ENABLE)
#define GPIO_PR1_PRU1_R31_10 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_LCD_PCLK_INDEX) | PINMUX_MODE6 | PINMUX_RX_ENABLE)
#define GPIO_PR1_PRU1_R31_11 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_LCD_AC_BIAS_EN_INDEX) | PINMUX_MODE6 | PINMUX_RX_ENABLE)
#define GPIO_PR1_PRU1_R31_12 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_CSN1_INDEX) | PINMUX_MODE6 | PINMUX_RX_ENABLE)
#define GPIO_PR1_PRU1_R31_13 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_CSN2_INDEX) | PINMUX_MODE6 | PINMUX_RX_ENABLE)
#define GPIO_PR1_PRU1_R31_14 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_UART0_RXD_INDEX) | PINMUX_MODE6 | PINMUX_RX_ENABLE)
#define GPIO_PR1_PRU1_R31_15 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_UART0_TXD_INDEX) | PINMUX_MODE6 | PINMUX_RX_ENABLE)
#define GPIO_PR1_PRU1_R31_16_1 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_UART1_RXD_INDEX) | PINMUX_MODE6 | PINMUX_RX_ENABLE)
#define GPIO_PR1_PRU1_R31_16_2 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_XDMA_EVENT_INTR0_INDEX) | PINMUX_MODE5 | PINMUX_RX_ENABLE)
/* PRU_ICSS PRU1 General Purpose Outputs */
#define GPIO_PR1_PRU1_R30_0 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_LCD_DATA0_INDEX) | PINMUX_MODE5)
#define GPIO_PR1_PRU1_R30_1 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_LCD_DATA1_INDEX) | PINMUX_MODE5)
#define GPIO_PR1_PRU1_R30_2 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_LCD_DATA2_INDEX) | PINMUX_MODE5)
#define GPIO_PR1_PRU1_R30_3 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_LCD_DATA3_INDEX) | PINMUX_MODE5)
#define GPIO_PR1_PRU1_R30_4 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_LCD_DATA4_INDEX) | PINMUX_MODE5)
#define GPIO_PR1_PRU1_R30_5 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_LCD_DATA5_INDEX) | PINMUX_MODE5)
#define GPIO_PR1_PRU1_R30_6 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_LCD_DATA6_INDEX) | PINMUX_MODE5)
#define GPIO_PR1_PRU1_R30_7 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_LCD_DATA7_INDEX) | PINMUX_MODE5)
#define GPIO_PR1_PRU1_R30_8 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_LCD_VSYNC_INDEX) | PINMUX_MODE5)
#define GPIO_PR1_PRU1_R30_9 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_LCD_HSYNC_INDEX) | PINMUX_MODE5)
#define GPIO_PR1_PRU1_R30_10 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_LCD_PCLK_INDEX) | PINMUX_MODE5)
#define GPIO_PR1_PRU1_R30_11 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_LCD_AC_BIAS_EN_INDEX) | PINMUX_MODE5)
#define GPIO_PR1_PRU1_R30_12 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_CSN1_INDEX) | PINMUX_MODE5)
#define GPIO_PR1_PRU1_R30_13 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_CSN2_INDEX) | PINMUX_MODE5)
#define GPIO_PR1_PRU1_R30_14 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_UART0_RXD_INDEX) | PINMUX_MODE5)
#define GPIO_PR1_PRU1_R30_15 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_UART0_TXD_INDEX) | PINMUX_MODE5)
/* Removable Media SD/MMC Card Interfaces */
#define GPIO_MMC0_CLK (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MMC0_CLK_INDEX) | PINMUX_MODE0 | PINMUX_RX_ENABLE)
#define GPIO_MMC0_CMD (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MMC0_CMD_INDEX) | PINMUX_MODE0 | PINMUX_RX_ENABLE)
#define GPIO_MMC0_DAT0 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MMC0_DAT0_INDEX) | PINMUX_MODE0 | PINMUX_RX_ENABLE)
#define GPIO_MMC0_DAT1 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MMC0_DAT1_INDEX) | PINMUX_MODE0 | PINMUX_RX_ENABLE)
#define GPIO_MMC0_DAT2 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MMC0_DAT2_INDEX) | PINMUX_MODE0 | PINMUX_RX_ENABLE)
#define GPIO_MMC0_DAT3 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MMC0_DAT3_INDEX) | PINMUX_MODE0 | PINMUX_RX_ENABLE)
#define GPIO_MMC0_DAT4 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MII1_RXD2_INDEX) | PINMUX_MODE3 | PINMUX_RX_ENABLE)
#define GPIO_MMC0_DAT5 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MII1_RXD3_INDEX) | PINMUX_MODE3 | PINMUX_RX_ENABLE)
#define GPIO_MMC0_DAT6 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MII1_RX_CLK_INDEX) | PINMUX_MODE3 | PINMUX_RX_ENABLE)
#define GPIO_MMC0_DAT7 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MII1_TX_CLK_INDEX) | PINMUX_MODE3 | PINMUX_RX_ENABLE)
#define GPIO_MMC0_POW_1 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_RMII1_REF_CLK_INDEX) | PINMUX_MODE5)
#define GPIO_MMC0_POW_2 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_SPI0_CS1_INDEX) | PINMUX_MODE3)
#define GPIO_MMC0_SDCD_1 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MCASP0_ACLKX_INDEX) | PINMUX_MODE4 | PINMUX_RX_ENABLE)
#define GPIO_MMC0_SDCD_2 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MDIO_INDEX) | PINMUX_MODE4 | PINMUX_RX_ENABLE)
#define GPIO_MMC0_SDCD_3 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_SPI0_CS1_INDEX) | PINMUX_MODE5 | PINMUX_RX_ENABLE)
#define GPIO_MMC0_SDWP_1 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_ECAP0_IN_PWM0_OUT_INDEX) | PINMUX_MODE5 | PINMUX_RX_ENABLE)
#define GPIO_MMC0_SDWP_2 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MCASP0_ACLKR_INDEX) | PINMUX_MODE4 | PINMUX_RX_ENABLE)
#define GPIO_MMC0_SDWP_3 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MDC_INDEX) | PINMUX_MODE4 | PINMUX_RX_ENABLE)
#define GPIO_MMC1_CLK_1 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_CSN1_INDEX) | PINMUX_MODE2 | PINMUX_RX_ENABLE)
#define GPIO_MMC1_CLK_2 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MDC_INDEX) | PINMUX_MODE5 | PINMUX_RX_ENABLE)
#define GPIO_MMC1_CLK_3 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MII1_TXD0_INDEX) | PINMUX_MODE6 | PINMUX_RX_ENABLE)
#define GPIO_MMC1_CMD_1 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_CSN2_INDEX) | PINMUX_MODE2 | PINMUX_RX_ENABLE)
#define GPIO_MMC1_CMD_2 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MDIO_INDEX) | PINMUX_MODE5 | PINMUX_RX_ENABLE)
#define GPIO_MMC1_CMD_3 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MII1_TXD1_INDEX) | PINMUX_MODE6 | PINMUX_RX_ENABLE)
#define GPIO_MMC1_DAT0_1 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_AD0_INDEX) | PINMUX_MODE1 | PINMUX_RX_ENABLE)
#define GPIO_MMC1_DAT0_2 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_AD8_INDEX) | PINMUX_MODE2 | PINMUX_RX_ENABLE)
#define GPIO_MMC1_DAT0_3 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MII1_TX_CLK_INDEX) | PINMUX_MODE4 | PINMUX_RX_ENABLE)
#define GPIO_MMC1_DAT1_1 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_AD1_INDEX) | PINMUX_MODE1 | PINMUX_RX_ENABLE)
#define GPIO_MMC1_DAT1_2 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_AD9_INDEX) | PINMUX_MODE2 | PINMUX_RX_ENABLE)
#define GPIO_MMC1_DAT1_3 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MII1_RX_CLK_INDEX) | PINMUX_MODE4 | PINMUX_RX_ENABLE)
#define GPIO_MMC1_DAT2_1 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_AD2_INDEX) | PINMUX_MODE1 | PINMUX_RX_ENABLE)
#define GPIO_MMC1_DAT2_2 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_AD10_INDEX) | PINMUX_MODE2 | PINMUX_RX_ENABLE)
#define GPIO_MMC1_DAT2_3 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MII1_RXD3_INDEX) | PINMUX_MODE4 | PINMUX_RX_ENABLE)
#define GPIO_MMC1_DAT3_1 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_AD3_INDEX) | PINMUX_MODE1 | PINMUX_RX_ENABLE)
#define GPIO_MMC1_DAT3_2 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_AD11_INDEX) | PINMUX_MODE2 | PINMUX_RX_ENABLE)
#define GPIO_MMC1_DAT3_3 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MII1_RXD2_INDEX) | PINMUX_MODE4 | PINMUX_RX_ENABLE)
#define GPIO_MMC1_DAT4_1 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_AD4_INDEX) | PINMUX_MODE1 | PINMUX_RX_ENABLE)
#define GPIO_MMC1_DAT4_2 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_AD12_INDEX) | PINMUX_MODE2 | PINMUX_RX_ENABLE)
#define GPIO_MMC1_DAT5_1 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_AD5_INDEX) | PINMUX_MODE1 | PINMUX_RX_ENABLE)
#define GPIO_MMC1_DAT5_2 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_AD13_INDEX) | PINMUX_MODE2 | PINMUX_RX_ENABLE)
#define GPIO_MMC1_DAT6_1 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_AD6_INDEX) | PINMUX_MODE1 | PINMUX_RX_ENABLE)
#define GPIO_MMC1_DAT6_2 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_AD14_INDEX) | PINMUX_MODE2 | PINMUX_RX_ENABLE)
#define GPIO_MMC1_DAT7_1 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_AD7_INDEX) | PINMUX_MODE1 | PINMUX_RX_ENABLE)
#define GPIO_MMC1_DAT7_2 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_AD15_INDEX) | PINMUX_MODE2 | PINMUX_RX_ENABLE)
#define GPIO_MMC1_SDCD_1 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_WAIT0_INDEX) | PINMUX_MODE4 | PINMUX_RX_ENABLE)
#define GPIO_MMC1_SDCD_2 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MCASP0_FSX_INDEX) | PINMUX_MODE4 | PINMUX_RX_ENABLE)
#define GPIO_MMC1_SDWP_1 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_SPI0_D1_INDEX) | PINMUX_MODE1 | PINMUX_RX_ENABLE)
#define GPIO_MMC1_SDWP_2 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_UART1_RXD_INDEX) | PINMUX_MODE1 | PINMUX_RX_ENABLE)
#define GPIO_MMC2_CLK_1 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_CLK_INDEX) | PINMUX_MODE3 | PINMUX_RX_ENABLE)
#define GPIO_MMC2_CLK_2 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MDC_INDEX) | PINMUX_MODE6 | PINMUX_RX_ENABLE)
#define GPIO_MMC2_CLK_3 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MII1_RXD1_INDEX) | PINMUX_MODE6 | PINMUX_RX_ENABLE)
#define GPIO_MMC2_CMD_1 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_CSN3_INDEX) | PINMUX_MODE3 | PINMUX_RX_ENABLE)
#define GPIO_MMC2_CMD_2 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MDIO_INDEX) | PINMUX_MODE6 | PINMUX_RX_ENABLE)
#define GPIO_MMC2_CMD_3 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MII1_TX_EN_INDEX) | PINMUX_MODE6 | PINMUX_RX_ENABLE)
#define GPIO_MMC2_DAT0_1 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_A1_INDEX) | PINMUX_MODE3 | PINMUX_RX_ENABLE)
#define GPIO_MMC2_DAT0_2 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_AD12_INDEX) | PINMUX_MODE3 | PINMUX_RX_ENABLE)
#define GPIO_MMC2_DAT0_3 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MII1_RX_DV_INDEX) | PINMUX_MODE5 | PINMUX_RX_ENABLE)
#define GPIO_MMC2_DAT1_1 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_A2_INDEX) | PINMUX_MODE3 | PINMUX_RX_ENABLE)
#define GPIO_MMC2_DAT1_2 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_AD13_INDEX) | PINMUX_MODE3 | PINMUX_RX_ENABLE)
#define GPIO_MMC2_DAT1_3 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MII1_TXD3_INDEX) | PINMUX_MODE5 | PINMUX_RX_ENABLE)
#define GPIO_MMC2_DAT2_1 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_A3_INDEX) | PINMUX_MODE3 | PINMUX_RX_ENABLE)
#define GPIO_MMC2_DAT2_2 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_AD14_INDEX) | PINMUX_MODE3 | PINMUX_RX_ENABLE)
#define GPIO_MMC2_DAT2_3 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MII1_TXD2_INDEX) | PINMUX_MODE5 | PINMUX_RX_ENABLE)
#define GPIO_MMC2_DAT3_1 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_AD15_INDEX) | PINMUX_MODE3 | PINMUX_RX_ENABLE)
#define GPIO_MMC2_DAT3_2 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_BEN1_INDEX) | PINMUX_MODE3 | PINMUX_RX_ENABLE)
#define GPIO_MMC2_DAT3_3 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MII1_COL_INDEX) | PINMUX_MODE5 | PINMUX_RX_ENABLE)
#define GPIO_MMC2_DAT4_1 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_A6_INDEX) | PINMUX_MODE3 | PINMUX_RX_ENABLE)
#define GPIO_MMC2_DAT4_2 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_AD8_INDEX) | PINMUX_MODE3 | PINMUX_RX_ENABLE)
#define GPIO_MMC2_DAT5_1 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_A7_INDEX) | PINMUX_MODE3 | PINMUX_RX_ENABLE)
#define GPIO_MMC2_DAT5_2 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_AD9_INDEX) | PINMUX_MODE3 | PINMUX_RX_ENABLE)
#define GPIO_MMC2_DAT6_1 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_A8_INDEX) | PINMUX_MODE3 | PINMUX_RX_ENABLE)
#define GPIO_MMC2_DAT6_2 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_AD10_INDEX) | PINMUX_MODE3 | PINMUX_RX_ENABLE)
#define GPIO_MMC2_DAT7_1 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_A9_INDEX) | PINMUX_MODE3 | PINMUX_RX_ENABLE)
#define GPIO_MMC2_DAT7_2 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_AD11_INDEX) | PINMUX_MODE3 | PINMUX_RX_ENABLE)
#define GPIO_MMC2_SDCD_1 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_WPN_INDEX) | PINMUX_MODE4 | PINMUX_RX_ENABLE)
#define GPIO_MMC2_SDCD_2 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MCASP0_AXR0_INDEX) | PINMUX_MODE4 | PINMUX_RX_ENABLE)
#define GPIO_MMC2_SDWP_1 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_SPI0_CS0_INDEX) | PINMUX_MODE1 | PINMUX_RX_ENABLE)
#define GPIO_MMC2_SDWP_2 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_UART1_TXD_INDEX) | PINMUX_MODE1 | PINMUX_RX_ENABLE)
/* CAN */
#define GPIO_DCAN0_RX_1 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MII1_TXD2_INDEX) | PINMUX_MODE1 | PINMUX_RX_ENABLE)
#define GPIO_DCAN0_RX_2 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_UART0_TXD_INDEX) | PINMUX_MODE2 | PINMUX_RX_ENABLE)
#define GPIO_DCAN0_RX_3 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_UART1_RTSN_INDEX) | PINMUX_MODE2 | PINMUX_RX_ENABLE)
#define GPIO_DCAN0_TX_1 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MII1_TXD3_INDEX) | PINMUX_MODE1)
#define GPIO_DCAN0_TX_2 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_UART0_RXD_INDEX) | PINMUX_MODE2)
#define GPIO_DCAN0_TX_3 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_UART1_CTSN_INDEX) | PINMUX_MODE2)
#define GPIO_DCAN1_RX_1 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MMC0_CMD_INDEX) | PINMUX_MODE4 | PINMUX_RX_ENABLE)
#define GPIO_DCAN1_RX_2 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_UART0_RTSN_INDEX) | PINMUX_MODE2 | PINMUX_RX_ENABLE)
#define GPIO_DCAN1_RX_3 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_UART1_TXD_INDEX) | PINMUX_MODE2 | PINMUX_RX_ENABLE)
#define GPIO_DCAN1_TX_1 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MMC0_CLK_INDEX) | PINMUX_MODE4)
#define GPIO_DCAN1_TX_2 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_UART0_CTSN_INDEX) | PINMUX_MODE2)
#define GPIO_DCAN1_TX_3 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_UART1_RXD_INDEX) | PINMUX_MODE2)
/* GEMAC CPSW MDIO */
#define GPIO_MDIO_CLK (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MDC_INDEX) | PINMUX_MODE0)
#define GPIO_MDIO_DATA (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MDIO_INDEX) | PINMUX_MODE0 | PINMUX_RX_ENABLE)
/* GEMAC CPSW MII */
#define GPIO_GMII1_COL (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MII1_COL_INDEX) | PINMUX_MODE0 | PINMUX_RX_ENABLE)
#define GPIO_GMII1_CRS (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MII1_CRS_INDEX) | PINMUX_MODE0 | PINMUX_RX_ENABLE)
#define GPIO_GMII1_RXCLK (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MII1_RX_CLK_INDEX) | PINMUX_MODE0 | PINMUX_RX_ENABLE)
#define GPIO_GMII1_RXD0 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MII1_RXD0_INDEX) | PINMUX_MODE0 | PINMUX_RX_ENABLE)
#define GPIO_GMII1_RXD1 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MII1_RXD1_INDEX) | PINMUX_MODE0 | PINMUX_RX_ENABLE)
#define GPIO_GMII1_RXD2 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MII1_RXD2_INDEX) | PINMUX_MODE0 | PINMUX_RX_ENABLE)
#define GPIO_GMII1_RXD3 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MII1_RXD3_INDEX) | PINMUX_MODE0 | PINMUX_RX_ENABLE)
#define GPIO_GMII1_RXDV (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MII1_RX_DV_INDEX) | PINMUX_MODE0 | PINMUX_RX_ENABLE)
#define GPIO_GMII1_RXERR (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MII1_RX_ER_INDEX) | PINMUX_MODE0 | PINMUX_RX_ENABLE)
#define GPIO_GMII1_TXCLK (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MII1_TX_CLK_INDEX) | PINMUX_MODE0 | PINMUX_RX_ENABLE)
#define GPIO_GMII1_TXD0 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MII1_TXD0_INDEX) | PINMUX_MODE0)
#define GPIO_GMII1_TXD1 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MII1_TXD1_INDEX) | PINMUX_MODE0)
#define GPIO_GMII1_TXD2 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MII1_TXD2_INDEX) | PINMUX_MODE0)
#define GPIO_GMII1_TXD3 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MII1_TXD3_INDEX) | PINMUX_MODE0)
#define GPIO_GMII1_TXEN (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MII1_TX_EN_INDEX) | PINMUX_MODE0)
#define GPIO_GMII2_COL (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_BEN1_INDEX) | PINMUX_MODE1 | PINMUX_RX_ENABLE)
#define GPIO_GMII2_CRS (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_WAIT0_INDEX) | PINMUX_MODE1 | PINMUX_RX_ENABLE)
#define GPIO_GMII2_RXCLK (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_A7_INDEX) | PINMUX_MODE1 | PINMUX_RX_ENABLE)
#define GPIO_GMII2_RXD0 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_A11_INDEX) | PINMUX_MODE1 | PINMUX_RX_ENABLE)
#define GPIO_GMII2_RXD1 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_A10_INDEX) | PINMUX_MODE1 | PINMUX_RX_ENABLE)
#define GPIO_GMII2_RXD2 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_A9_INDEX) | PINMUX_MODE1 | PINMUX_RX_ENABLE)
#define GPIO_GMII2_RXD3 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_A8_INDEX) | PINMUX_MODE1 | PINMUX_RX_ENABLE)
#define GPIO_GMII2_RXDV (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_A1_INDEX) | PINMUX_MODE1 | PINMUX_RX_ENABLE)
#define GPIO_GMII2_RXERR (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_WPN_INDEX) | PINMUX_MODE1 | PINMUX_RX_ENABLE)
#define GPIO_GMII2_TXCLK (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_A6_INDEX) | PINMUX_MODE1 | PINMUX_RX_ENABLE)
#define GPIO_GMII2_TXD0 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_A5_INDEX) | PINMUX_MODE1)
#define GPIO_GMII2_TXD1 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_A4_INDEX) | PINMUX_MODE1)
#define GPIO_GMII2_TXD2 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_A3_INDEX) | PINMUX_MODE1)
#define GPIO_GMII2_TXD3 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_A2_INDEX) | PINMUX_MODE1)
#define GPIO_GMII2_TXEN (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_A0_INDEX) | PINMUX_MODE1)
/* GEMAC CPSW RGMII */
#define GPIO_RGMII1_RCLK (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MII1_RX_CLK_INDEX) | PINMUX_MODE2 | PINMUX_RX_ENABLE)
#define GPIO_RGMII1_RCTL (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MII1_RX_DV_INDEX) | PINMUX_MODE2 | PINMUX_RX_ENABLE)
#define GPIO_RGMII1_RD0 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MII1_RXD0_INDEX) | PINMUX_MODE2 | PINMUX_RX_ENABLE)
#define GPIO_RGMII1_RD1 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MII1_RXD1_INDEX) | PINMUX_MODE2 | PINMUX_RX_ENABLE)
#define GPIO_RGMII1_RD2 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MII1_RXD2_INDEX) | PINMUX_MODE2 | PINMUX_RX_ENABLE)
#define GPIO_RGMII1_RD3 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MII1_RXD3_INDEX) | PINMUX_MODE2 | PINMUX_RX_ENABLE)
#define GPIO_RGMII1_TCLK (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MII1_TX_CLK_INDEX) | PINMUX_MODE2)
#define GPIO_RGMII1_TCTL (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MII1_TX_EN_INDEX) | PINMUX_MODE2)
#define GPIO_RGMII1_TD0 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MII1_TXD0_INDEX) | PINMUX_MODE2)
#define GPIO_RGMII1_TD1 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MII1_TXD1_INDEX) | PINMUX_MODE2)
#define GPIO_RGMII1_TD2 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MII1_TXD2_INDEX) | PINMUX_MODE2)
#define GPIO_RGMII1_TD3 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MII1_TXD3_INDEX) | PINMUX_MODE2)
#define GPIO_RGMII2_RCLK (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_A7_INDEX) | PINMUX_MODE2 | PINMUX_RX_ENABLE)
#define GPIO_RGMII2_RCTL (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_A1_INDEX) | PINMUX_MODE2 | PINMUX_RX_ENABLE)
#define GPIO_RGMII2_RD0 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_A11_INDEX) | PINMUX_MODE2 | PINMUX_RX_ENABLE)
#define GPIO_RGMII2_RD1 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_A10_INDEX) | PINMUX_MODE2 | PINMUX_RX_ENABLE)
#define GPIO_RGMII2_RX2 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_A9_INDEX) | PINMUX_MODE2 | PINMUX_RX_ENABLE)
#define GPIO_RGMII2_RD3 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_A8_INDEX) | PINMUX_MODE2 | PINMUX_RX_ENABLE)
#define GPIO_RGMII2_TCLK (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_A6_INDEX) | PINMUX_MODE2)
#define GPIO_RGMII2_TCTL (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_A0_INDEX) | PINMUX_MODE2)
#define GPIO_RGMII2_TD0 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_A5_INDEX) | PINMUX_MODE2)
#define GPIO_RGMII2_TD1 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_A4_INDEX) | PINMUX_MODE2)
#define GPIO_RGMII2_TD2 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_A3_INDEX) | PINMUX_MODE2)
#define GPIO_RGMII2_TD3 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_A2_INDEX) | PINMUX_MODE2)
/* GEMAC CPSW RMII */
#define GPIO_RMII1_CRS_DV (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MII1_CRS_INDEX) | PINMUX_MODE1 | PINMUX_RX_ENABLE)
#define GPIO_RMII1_REFCLK (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_RMII1_REF_CLK_INDEX) | PINMUX_MODE0 | PINMUX_RX_ENABLE)
#define GPIO_RMII1_RXD0 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MII1_RXD0_INDEX) | PINMUX_MODE1 | PINMUX_RX_ENABLE)
#define GPIO_RMII1_RXD1 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MII1_RXD1_INDEX) | PINMUX_MODE1 | PINMUX_RX_ENABLE)
#define GPIO_RMII1_RXERR (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MII1_RX_ER_INDEX) | PINMUX_MODE1 | PINMUX_RX_ENABLE)
#define GPIO_RMII1_TXD0 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MII1_TXD0_INDEX) | PINMUX_MODE1)
#define GPIO_RMII1_TXD1 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MII1_TXD1_INDEX) | PINMUX_MODE1)
#define GPIO_RMII1_TXEN (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MII1_TX_EN_INDEX) | PINMUX_MODE1)
#define GPIO_RMII2_CRS_DV_1 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_CSN3_INDEX) | PINMUX_MODE2 | PINMUX_RX_ENABLE)
#define GPIO_RMII2_CRS_DV_2 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_WAIT0_INDEX) | PINMUX_MODE3 | PINMUX_RX_ENABLE)
#define GPIO_RMII2_REFCLK (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MII1_COL_INDEX) | PINMUX_MODE1 | PINMUX_RX_ENABLE)
#define GPIO_RMII2_RXD0 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_A11_INDEX) | PINMUX_MODE3 | PINMUX_RX_ENABLE)
#define GPIO_RMII2_RXD1 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_A10_INDEX) | PINMUX_MODE3 | PINMUX_RX_ENABLE)
#define GPIO_RMII2_RXERR (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_WPN_INDEX) | PINMUX_MODE3 | PINMUX_RX_ENABLE)
#define GPIO_RMII2_TXD0 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_A5_INDEX) | PINMUX_MODE3)
#define GPIO_RMII2_TXD1 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_A4_INDEX) | PINMUX_MODE3)
#define GPIO_RMII2_TXEN (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_A0_INDEX) | PINMUX_MODE3)
/* I2C */
#define GPIO_I2C0_SCL (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_I2C0_SCL_INDEX) | PINMUX_MODE0 | PINMUX_RX_ENABLE)
#define GPIO_I2C0_SDA (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_I2C0_SDA_INDEX) | PINMUX_MODE0 | PINMUX_RX_ENABLE)
#define GPIO_I2C1_SCL_1 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MII1_RX_ER_INDEX) | PINMUX_MODE3 | PINMUX_RX_ENABLE)
#define GPIO_I2C1_SCL_2 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_SPI0_CS0_INDEX) | PINMUX_MODE2 | PINMUX_RX_ENABLE)
#define GPIO_I2C1_SCL_3 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_UART0_RTSN_INDEX) | PINMUX_MODE3 | PINMUX_RX_ENABLE)
#define GPIO_I2C1_SCL_4 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_UART1_TXD_INDEX) | PINMUX_MODE3 | PINMUX_RX_ENABLE)
#define GPIO_I2C1_SDA_1 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MII1_CRS_INDEX) | PINMUX_MODE3 | PINMUX_RX_ENABLE)
#define GPIO_I2C1_SDA_2 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_SPI0_D1_INDEX) | PINMUX_MODE2 | PINMUX_RX_ENABLE)
#define GPIO_I2C1_SDA_3 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_UART0_CTSN_INDEX) | PINMUX_MODE3 | PINMUX_RX_ENABLE)
#define GPIO_I2C1_SDA_4 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_UART1_RXD_INDEX) | PINMUX_MODE3 | PINMUX_RX_ENABLE)
#define GPIO_I2C2_SCL_1 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_SPI0_D0_INDEX) | PINMUX_MODE2 | PINMUX_RX_ENABLE)
#define GPIO_I2C2_SCL_2 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_UART0_TXD_INDEX) | PINMUX_MODE3 | PINMUX_RX_ENABLE)
#define GPIO_I2C2_SCL_3 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_UART1_RTSN_INDEX) | PINMUX_MODE3 | PINMUX_RX_ENABLE)
#define GPIO_I2C2_SDA_1 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_SPI0_SCLK_INDEX) | PINMUX_MODE2 | PINMUX_RX_ENABLE)
#define GPIO_I2C2_SDA_2 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_UART0_RXD_INDEX) | PINMUX_MODE3 | PINMUX_RX_ENABLE)
#define GPIO_I2C2_SDA_3 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_UART1_CTSN_INDEX) | PINMUX_MODE3 | PINMUX_RX_ENABLE)
/* McASP */
#define GPIO_MCASP0_ACLKR_1 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_BEN1_INDEX) | PINMUX_MODE6 | PINMUX_RX_ENABLE)
#define GPIO_MCASP0_ACLKR_2 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_LCD_DATA12_INDEX) | PINMUX_MODE3 | PINMUX_RX_ENABLE)
#define GPIO_MCASP0_ACLKR_3 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MCASP0_ACLKR_INDEX) | PINMUX_MODE0 | PINMUX_RX_ENABLE)
#define GPIO_MCASP0_ACLKR_4 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MII1_RX_DV_INDEX) | PINMUX_MODE6 | PINMUX_RX_ENABLE)
#define GPIO_MCASP0_ACLKX_1 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_A8_INDEX) | PINMUX_MODE6 | PINMUX_RX_ENABLE)
#define GPIO_MCASP0_ACLKX_2 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_LCD_DATA8_INDEX) | PINMUX_MODE3 | PINMUX_RX_ENABLE)
#define GPIO_MCASP0_ACLKX_3 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MCASP0_ACLKX_INDEX) | PINMUX_MODE0 | PINMUX_RX_ENABLE)
#define GPIO_MCASP0_ACLKX_4 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MII1_TX_CLK_INDEX) | PINMUX_MODE6 | PINMUX_RX_ENABLE)
#define GPIO_MCASP0_AHCLKR_1 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_LCD_DATA11_INDEX) | PINMUX_MODE3 | PINMUX_RX_ENABLE)
#define GPIO_MCASP0_AHCLKR_2 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MCASP0_AHCLKR_INDEX) | PINMUX_MODE0 | PINMUX_RX_ENABLE)
#define GPIO_MCASP0_AHCLKX_1 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_LCD_DATA15_INDEX) | PINMUX_MODE3 | PINMUX_RX_ENABLE)
#define GPIO_MCASP0_AHCLKX_2 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MCASP0_AHCLKX_INDEX) | PINMUX_MODE0 | PINMUX_RX_ENABLE)
#define GPIO_MCASP0_AHCLKX_3 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MII1_TXD2_INDEX) | PINMUX_MODE6 | PINMUX_RX_ENABLE)
#define GPIO_MCASP0_AXR0_1 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_A10_INDEX) | PINMUX_MODE6 | PINMUX_RX_ENABLE)
#define GPIO_MCASP0_AXR0_2 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_LCD_DATA10_INDEX) | PINMUX_MODE3 | PINMUX_RX_ENABLE)
#define GPIO_MCASP0_AXR0_3 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MCASP0_AXR0_INDEX) | PINMUX_MODE0 | PINMUX_RX_ENABLE)
#define GPIO_MCASP0_AXR0_4 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MII1_RXD3_INDEX) | PINMUX_MODE6 | PINMUX_RX_ENABLE)
#define GPIO_MCASP0_AXR1_1 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_A11_INDEX) | PINMUX_MODE6 | PINMUX_RX_ENABLE)
#define GPIO_MCASP0_AXR1_2 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_LCD_DATA14_INDEX) | PINMUX_MODE3 | PINMUX_RX_ENABLE)
#define GPIO_MCASP0_AXR1_3 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MCASP0_AXR1_INDEX) | PINMUX_MODE0 | PINMUX_RX_ENABLE)
#define GPIO_MCASP0_AXR1_4 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MII1_RXD2_INDEX) | PINMUX_MODE6 | PINMUX_RX_ENABLE)
#define GPIO_MCASP0_AXR2_1 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_LCD_DATA11_INDEX) | PINMUX_MODE4 | PINMUX_RX_ENABLE)
#define GPIO_MCASP0_AXR2_2 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_LCD_DATA12_INDEX) | PINMUX_MODE4 | PINMUX_RX_ENABLE)
#define GPIO_MCASP0_AXR2_3 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MCASP0_ACLKR_INDEX) | PINMUX_MODE2 | PINMUX_RX_ENABLE)
#define GPIO_MCASP0_AXR2_4 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MCASP0_AHCLKR_INDEX) | PINMUX_MODE2 | PINMUX_RX_ENABLE)
#define GPIO_MCASP0_AXR2_5 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MII1_COL_INDEX) | PINMUX_MODE6 | PINMUX_RX_ENABLE)
#define GPIO_MCASP0_AXR3_1 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_LCD_DATA13_INDEX) | PINMUX_MODE4 | PINMUX_RX_ENABLE)
#define GPIO_MCASP0_AXR3_2 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_LCD_DATA15_INDEX) | PINMUX_MODE4 | PINMUX_RX_ENABLE)
#define GPIO_MCASP0_AXR3_3 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MCASP0_AHCLKX_INDEX) | PINMUX_MODE2 | PINMUX_RX_ENABLE)
#define GPIO_MCASP0_AXR3_4 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MCASP0_FSR_INDEX) | PINMUX_MODE2 | PINMUX_RX_ENABLE)
#define GPIO_MCASP0_AXR3_5 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MII1_RXD0_INDEX) | PINMUX_MODE6 | PINMUX_RX_ENABLE)
#define GPIO_MCASP0_FSR_1 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_CLK_INDEX) | PINMUX_MODE6 | PINMUX_RX_ENABLE)
#define GPIO_MCASP0_FSR_2 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_LCD_DATA13_INDEX) | PINMUX_MODE3 | PINMUX_RX_ENABLE)
#define GPIO_MCASP0_FSR_3 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MCASP0_FSR_INDEX) | PINMUX_MODE0 | PINMUX_RX_ENABLE)
#define GPIO_MCASP0_FSR_4 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MII1_TXD3_INDEX) | PINMUX_MODE6 | PINMUX_RX_ENABLE)
#define GPIO_MCASP0_FSX_1 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_A9_INDEX) | PINMUX_MODE6 | PINMUX_RX_ENABLE)
#define GPIO_MCASP0_FSX_2 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_LCD_DATA9_INDEX) | PINMUX_MODE3 | PINMUX_RX_ENABLE)
#define GPIO_MCASP0_FSX_3 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MCASP0_FSX_INDEX) | PINMUX_MODE0 | PINMUX_RX_ENABLE)
#define GPIO_MCASP0_FSX_4 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MII1_RX_CLK_INDEX) | PINMUX_MODE6 | PINMUX_RX_ENABLE)
#define GPIO_MCASP1_ACLKR_1 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MII1_RXD0_INDEX) | PINMUX_MODE5 | PINMUX_RX_ENABLE)
#define GPIO_MCASP1_ACLKR_2 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MII1_TXD0_INDEX) | PINMUX_MODE4 | PINMUX_RX_ENABLE)
#define GPIO_MCASP1_ACLKX_1 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MCASP0_ACLKR_INDEX) | PINMUX_MODE3 | PINMUX_RX_ENABLE)
#define GPIO_MCASP1_ACLKX_2 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MII1_RX_DV_INDEX) | PINMUX_MODE4 | PINMUX_RX_ENABLE)
#define GPIO_MCASP1_ACLKX_3 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MII1_CRS_INDEX) | PINMUX_MODE4 | PINMUX_RX_ENABLE)
#define GPIO_MCASP1_AHCLKR_1 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MII1_RXD0_INDEX) | PINMUX_MODE4 | PINMUX_RX_ENABLE)
#define GPIO_MCASP1_AHCLKX_1 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MII1_RXD0_INDEX) | PINMUX_MODE3 | PINMUX_RX_ENABLE)
#define GPIO_MCASP1_AHCLKX_2 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_RMII1_REF_CLK_INDEX) | PINMUX_MODE6 | PINMUX_RX_ENABLE)
#define GPIO_MCASP1_AXR0_1 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MCASP0_AXR1_INDEX) | PINMUX_MODE3 | PINMUX_RX_ENABLE)
#define GPIO_MCASP1_AXR0_2 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MII1_TX_EN_INDEX) | PINMUX_MODE4 | PINMUX_RX_ENABLE)
#define GPIO_MCASP1_AXR0_3 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MII1_TXD2_INDEX) | PINMUX_MODE4 | PINMUX_RX_ENABLE)
#define GPIO_MCASP1_AXR1_1 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MCASP0_AHCLKX_INDEX) | PINMUX_MODE3 | PINMUX_RX_ENABLE)
#define GPIO_MCASP1_AXR1_2 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MII1_TXD1_INDEX) | PINMUX_MODE4 | PINMUX_RX_ENABLE)
#define GPIO_MCASP1_AXR2_1 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MII1_COL_INDEX) | PINMUX_MODE4 | PINMUX_RX_ENABLE)
#define GPIO_MCASP1_AXR2_2 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MII1_TXD0_INDEX) | PINMUX_MODE3 | PINMUX_RX_ENABLE)
#define GPIO_MCASP1_AXR3_1 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MII1_RXD1_INDEX) | PINMUX_MODE3 | PINMUX_RX_ENABLE)
#define GPIO_MCASP1_AXR3_2 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_RMII1_REF_CLK_INDEX) | PINMUX_MODE4 | PINMUX_RX_ENABLE)
#define GPIO_MCASP1_FSR_1 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MII1_RXD1_INDEX) | PINMUX_MODE4 | PINMUX_RX_ENABLE)
#define GPIO_MCASP1_FSR_2 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MII1_TXD1_INDEX) | PINMUX_MODE3 | PINMUX_RX_ENABLE)
#define GPIO_MCASP1_FSX_1 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MCASP0_FSR_INDEX) | PINMUX_MODE3 | PINMUX_RX_ENABLE)
#define GPIO_MCASP1_FSX_2 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MII1_RX_ER_INDEX) | PINMUX_MODE4 | PINMUX_RX_ENABLE)
#define GPIO_MCASP1_FSX_3 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MII1_TXD3_INDEX) | PINMUX_MODE4 | PINMUX_RX_ENABLE)
/* SPI */
#define GPIO_SPI0_CS0 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_SPI0_CS0_INDEX) | PINMUX_MODE0 | PINMUX_RX_ENABLE)
#define GPIO_SPI0_CS1 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_SPI0_CS1_INDEX) | PINMUX_MODE0 | PINMUX_RX_ENABLE)
#define GPIO_SPI0_D0 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_SPI0_D0_INDEX) | PINMUX_MODE0 | PINMUX_RX_ENABLE)
#define GPIO_SPI0_D1 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_SPI0_D1_INDEX) | PINMUX_MODE0 | PINMUX_RX_ENABLE)
#define GPIO_SPI0_SCLK (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_SPI0_SCLK_INDEX) | PINMUX_MODE0 | PINMUX_RX_ENABLE)
#define GPIO_SPI1_CS0_1 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MCASP0_AHCLKR_INDEX) | PINMUX_MODE3 | PINMUX_RX_ENABLE)
#define GPIO_SPI1_CS0_2 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_RMII1_REF_CLK_INDEX) | PINMUX_MODE2 | PINMUX_RX_ENABLE)
#define GPIO_SPI1_CS0_3 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_UART0_RXD_INDEX) | PINMUX_MODE1 | PINMUX_RX_ENABLE)
#define GPIO_SPI1_CS0_4 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_UART0_RTSN_INDEX) | PINMUX_MODE5 | PINMUX_RX_ENABLE)
#define GPIO_SPI1_CS0_5 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_UART1_CTSN_INDEX) | PINMUX_MODE4 | PINMUX_RX_ENABLE)
#define GPIO_SPI1_CS1_1 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_ECAP0_IN_PWM0_OUT_INDEX) | PINMUX_MODE2 | PINMUX_RX_ENABLE)
#define GPIO_SPI1_CS1_2 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_UART0_TXD_INDEX) | PINMUX_MODE1 | PINMUX_RX_ENABLE)
#define GPIO_SPI1_CS1_3 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_UART1_RTSN_INDEX) | PINMUX_MODE4 | PINMUX_RX_ENABLE)
#define GPIO_SPI1_CS1_4 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_XDMA_EVENT_INTR0_INDEX) | PINMUX_MODE4 | PINMUX_RX_ENABLE)
#define GPIO_SPI1_D0_1 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MCASP0_FSX_INDEX) | PINMUX_MODE3 | PINMUX_RX_ENABLE)
#define GPIO_SPI1_D0_2 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MII1_CRS_INDEX) | PINMUX_MODE2 | PINMUX_RX_ENABLE)
#define GPIO_SPI1_D0_3 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_UART0_CTSN_INDEX) | PINMUX_MODE4 | PINMUX_RX_ENABLE)
#define GPIO_SPI1_D1_1 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MCASP0_AXR0_INDEX) | PINMUX_MODE3 | PINMUX_RX_ENABLE)
#define GPIO_SPI1_D1_2 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MII1_RX_ER_INDEX) | PINMUX_MODE2 | PINMUX_RX_ENABLE)
#define GPIO_SPI1_D1_3 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_UART0_RTSN_INDEX) | PINMUX_MODE4 | PINMUX_RX_ENABLE)
#define GPIO_SPI1_SCLK_1 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_ECAP0_IN_PWM0_OUT_INDEX) | PINMUX_MODE4 | PINMUX_RX_ENABLE)
#define GPIO_SPI1_SCLK_2 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MCASP0_ACLKX_INDEX) | PINMUX_MODE3 | PINMUX_RX_ENABLE)
#define GPIO_SPI1_SCLK_3 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MII1_COL_INDEX) | PINMUX_MODE2 | PINMUX_RX_ENABLE)
/* UART */
#define GPIO_UART0_CTSN (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_UART0_CTSN_INDEX) | PINMUX_MODE0 | PINMUX_RX_ENABLE)
#define GPIO_UART0_RTSN (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_UART0_RTSN_INDEX) | PINMUX_MODE0)
#define GPIO_UART0_RXD (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_UART0_RXD_INDEX) | PINMUX_MODE0 | PINMUX_RX_ENABLE)
#define GPIO_UART0_TXD (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_UART0_TXD_INDEX) | PINMUX_MODE0)
#define GPIO_UART1_CTSN (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_UART1_CTSN_INDEX) | PINMUX_MODE0 | PINMUX_RX_ENABLE)
#define GPIO_UART1_DCDN_1 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MII1_TX_CLK_INDEX) | PINMUX_MODE5 | PINMUX_RX_ENABLE)
#define GPIO_UART1_DCDN_2 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MMC0_DAT3_INDEX) | PINMUX_MODE4 | PINMUX_RX_ENABLE)
#define GPIO_UART1_DSRN_1 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MII1_RX_CLK_INDEX) | PINMUX_MODE5 | PINMUX_RX_ENABLE)
#define GPIO_UART1_DSRN_2 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MMC0_DAT2_INDEX) | PINMUX_MODE4 | PINMUX_RX_ENABLE)
#define GPIO_UART1_DTRN_1 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MII1_RXD3_INDEX) | PINMUX_MODE5)
#define GPIO_UART1_DTRN_2 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MMC0_DAT1_INDEX) | PINMUX_MODE4)
#define GPIO_UART1_RIN_1 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MII1_RXD2_INDEX) | PINMUX_MODE5 | PINMUX_RX_ENABLE)
#define GPIO_UART1_RIN_2 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MMC0_DAT0_INDEX) | PINMUX_MODE4 | PINMUX_RX_ENABLE)
#define GPIO_UART1_RTSN (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_UART1_RTSN_INDEX) | PINMUX_MODE0)
#define GPIO_UART1_RXD (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_UART1_RXD_INDEX) | PINMUX_MODE0 | PINMUX_RX_ENABLE)
#define GPIO_UART1_TXD (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_UART1_TXD_INDEX) | PINMUX_MODE0)
#define GPIO_UART2_CTSN_1 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_I2C0_SDA_INDEX) | PINMUX_MODE2 | PINMUX_RX_ENABLE)
#define GPIO_UART2_CTSN_2 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_LCD_DATA8_INDEX) | PINMUX_MODE6 | PINMUX_RX_ENABLE)
#define GPIO_UART2_RTSN_1 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_I2C0_SCL_INDEX) | PINMUX_MODE2)
#define GPIO_UART2_RTSN_2 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_LCD_DATA9_INDEX) | PINMUX_MODE6)
#define GPIO_UART2_RXD_1 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MII1_TX_CLK_INDEX) | PINMUX_MODE1 | PINMUX_RX_ENABLE
#define GPIO_UART2_RXD_2 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MII1_CRS_INDEX) | PINMUX_MODE6 | PINMUX_RX_ENABLE)
#define GPIO_UART2_RXD_3 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MMC0_CLK_INDEX) | PINMUX_MODE3 | PINMUX_RX_ENABLE)
#define GPIO_UART2_RXD_4 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_SPI0_SCLK_INDEX) | PINMUX_MODE1 | PINMUX_RX_ENABLE)
#define GPIO_UART2_TXD_1 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MII1_RX_ER_INDEX) | PINMUX_MODE6)
#define GPIO_UART2_TXD_2 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MII1_RX_CLK_INDEX) | PINMUX_MODE1)
#define GPIO_UART2_TXD_3 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MMC0_CMD_INDEX) | PINMUX_MODE3)
#define GPIO_UART2_TXD_4 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_SPI0_D0_INDEX) | PINMUX_MODE1)
#define GPIO_UART3_CTSN_1 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_LCD_DATA10_INDEX) | PINMUX_MODE6 | PINMUX_RX_ENABLE)
#define GPIO_UART3_CTSN_2 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MDIO_INDEX) | PINMUX_MODE3 | PINMUX_RX_ENABLE)
#define GPIO_UART3_CTSN_3 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MMC0_CLK_INDEX) | PINMUX_MODE2 | PINMUX_RX_ENABLE)
#define GPIO_UART3_RTSN_1 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_LCD_DATA11_INDEX) | PINMUX_MODE6)
#define GPIO_UART3_RTSN_2 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MDC_INDEX) | PINMUX_MODE3)
#define GPIO_UART3_RTSN_3 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MMC0_CMD_INDEX) | PINMUX_MODE2)
#define GPIO_UART3_RXD_1 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MII1_RXD3_INDEX) | PINMUX_MODE1 | PINMUX_RX_ENABLE)
#define GPIO_UART3_RXD_2 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MMC0_DAT1_INDEX) | PINMUX_MODE3 | PINMUX_RX_ENABLE)
#define GPIO_UART3_RXD_3 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_SPI0_CS1_INDEX) | PINMUX_MODE1 | PINMUX_RX_ENABLE)
#define GPIO_UART3_TXD_1 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_ECAP0_IN_PWM0_OUT_INDEX) | PINMUX_MODE1)
#define GPIO_UART3_TXD_2 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MII1_RXD2_INDEX) | PINMUX_MODE1)
#define GPIO_UART3_TXD_3 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MMC0_DAT0_INDEX) | PINMUX_MODE3)
#define GPIO_UART4_CTSN_1 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_LCD_DATA12_INDEX) | PINMUX_MODE6 | PINMUX_RX_ENABLE)
#define GPIO_UART4_CTSN_2 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MMC0_DAT3_INDEX) | PINMUX_MODE2 | PINMUX_RX_ENABLE)
#define GPIO_UART4_RTSN_1 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_LCD_DATA13_INDEX) | PINMUX_MODE6)
#define GPIO_UART4_RTSN_2 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MMC0_DAT2_INDEX) | PINMUX_MODE2)
#define GPIO_UART4_RXD_1 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_WAIT0_INDEX) | PINMUX_MODE6 | PINMUX_RX_ENABLE)
#define GPIO_UART4_RXD_2 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MII1_TXD3_INDEX) | PINMUX_MODE3 | PINMUX_RX_ENABLE)
#define GPIO_UART4_RXD_3 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_UART0_CTSN_INDEX) | PINMUX_MODE1 | PINMUX_RX_ENABLE)
#define GPIO_UART4_TXD_1 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_GPMC_WPN_INDEX) | PINMUX_MODE6)
#define GPIO_UART4_TXD_2 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MII1_TXD2_INDEX) | PINMUX_MODE3)
#define GPIO_UART4_TXD_3 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_UART0_RTSN_INDEX) | PINMUX_MODE1)
#define GPIO_UART5_CTSN_1 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_LCD_DATA14_INDEX) | PINMUX_MODE6 | PINMUX_RX_ENABLE)
#define GPIO_UART5_CTSN_2 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MII1_CRS_INDEX) | PINMUX_MODE5 | PINMUX_RX_ENABLE)
#define GPIO_UART5_CTSN_3 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MMC0_DAT1_INDEX) | PINMUX_MODE2 | PINMUX_RX_ENABLE)
#define GPIO_UART5_RTSN_1 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_LCD_DATA15_INDEX) | PINMUX_MODE6)
#define GPIO_UART5_RTSN_2 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MII1_RX_ER_INDEX) | PINMUX_MODE5)
#define GPIO_UART5_RTSN_3 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MMC0_DAT0_INDEX) | PINMUX_MODE2)
#define GPIO_UART5_RXD_1 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_LCD_DATA9_INDEX) | PINMUX_MODE4 | PINMUX_RX_ENABLE)
#define GPIO_UART5_RXD_2 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_LCD_DATA14_INDEX) | PINMUX_MODE4 | PINMUX_RX_ENABLE)
#define GPIO_UART5_RXD_3 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MDIO_INDEX) | PINMUX_MODE2 | PINMUX_RX_ENABLE)
#define GPIO_UART5_RXD_4 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MII1_COL_INDEX) | PINMUX_MODE3 | PINMUX_RX_ENABLE)
#define GPIO_UART5_TXD_1 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_LCD_DATA8_INDEX) | PINMUX_MODE4)
#define GPIO_UART5_TXD_2 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MDC_INDEX) | PINMUX_MODE2)
#define GPIO_UART5_TXD_3 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_MII1_RX_DV_INDEX) | PINMUX_MODE3)
#define GPIO_UART5_TXD_4 (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_RMII1_REF_CLK_INDEX) | PINMUX_MODE3)
/* USB */
#define GPIO_USB0_DRVVBUS (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_USB0_DRVVBUS_INDEX) | PINMUX_MODE0)
#define GPIO_USB1_DRVVBUS (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_USB1_DRVVBUS_INDEX) | PINMUX_MODE0)
#endif /* __ARCH_ARM_SRC_AM335X_CHIP_AM3358_PINMUX_H */

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/********************************************************************************************
* arch/arm/src/am335x/chip/am335x_control.h
*
* Copyright (C) 2018 Petro Karashchenko. All rights reserved.
* Author: Petro Karashchenko <petro.karashchenko@gmail.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
********************************************************************************************/
#ifndef __ARCH_ARM_SRC_AM335X_CHIP_AM335X_CONTROL_H
#define __ARCH_ARM_SRC_AM335X_CHIP_AM335X_CONTROL_H
/********************************************************************************************
* Included Files
********************************************************************************************/
#include <nuttx/config.h>
#include <chip/am335x_memorymap.h>
/********************************************************************************************
* Pre-processor Definitions
********************************************************************************************/
/* Control Module Register Offsets **********************************************************/
#define AM335X_CONTROL_SYS_CONF_OFFSET 0x0010
#define AM335X_CONTROL_STATUS_OFFSET 0x0040
#define AM335X_CONTROL_EMIF_SDRAM_CONF_OFFSET 0x0110
#define AM335X_CORE_SLDO_CTRL_OFFSET 0x0428
#define AM335X_MPU_SLDO_CTRL_OFFSET 0x042C
#define AM335X_CLK32KDIVRATIO_CTRL_OFFSET 0x0444
#define AM335X_BANDGAP_CTRL_OFFSET 0x0448
#define AM335X_BANDGAP_TRIM_OFFSET 0x044C
#define AM335X_PLL_CLKINPULOW_CTRL_OFFSET 0x0458
#define AM335X_MOSC_CTRL_OFFSET 0x0468
#define AM335X_DEEPSLEEP_CTRL_OFFSET 0x0470
#define AM335X_DPLL_PWR_SW_STATUS_OFFSET 0x050C
#define AM335X_DEVICE_ID_OFFSET 0x0600
#define AM335X_DEV_FEATURE_OFFSET 0x0604
#define AM335X_INIT_PRIORITY_0_OFFSET 0x0608
#define AM335X_INIT_PRIORITY_1_OFFSET 0x060C
#define AM335X_TPTC_CFG_OFFSET 0x0614
#define AM335X_USB_CTRL0_OFFSET 0x0620
#define AM335X_USB_STS0_OFFSET 0x0624
#define AM335X_USB_CTRL1_OFFSET 0x0628
#define AM335X_USB_STS1_OFFSET 0x062C
#define AM335X_MAC_ID0_LO_OFFSET 0x0630
#define AM335X_MAC_ID0_HI_OFFSET 0x0634
#define AM335X_MAC_ID1_LO_OFFSET 0x0638
#define AM335X_MAC_ID1_HI_OFFSET 0x063C
#define AM335X_DCAN_RAMINIT_OFFSET 0x0644
#define AM335X_USB_WKUP_CTRL_OFFSET 0x0648
#define AM335X_GMII_SEL_OFFSET 0x0650
#define AM335X_PWMSS_CTRL_OFFSET 0x0664
#define AM335X_MREGPRIO_0_OFFSET 0x0670
#define AM335X_MREGPRIO_1_OFFSET 0x0674
#define AM335X_HW_EVENT_SEL_GRP1_OFFSET 0x0690
#define AM335X_HW_EVENT_SEL_GRP2_OFFSET 0x0694
#define AM335X_HW_EVENT_SEL_GRP3_OFFSET 0x0698
#define AM335X_HW_EVENT_SEL_GRP4_OFFSET 0x069C
#define AM335X_SMRT_CTRL_OFFSET 0x06A0
#define AM335X_MPUSS_HW_DEBUG_SEL_OFFSET 0x06A4
#define AM335X_MPUSS_HW_DBG_INFO_OFFSET 0x06A8
#define AM335X_VDD_MPU_OPP_050_OFFSET 0x0770
#define AM335X_VDD_MPU_OPP_100_OFFSET 0x0774
#define AM335X_VDD_MPU_OPP_120_OFFSET 0x0778
#define AM335X_VDD_MPU_OPP_TURBO_OFFSET 0x077C
#define AM335X_VDD_CORE_OPP_050_OFFSET 0x07B8
#define AM335X_VDD_CORE_OPP_100_OFFSET 0x07BC
#define AM335X_BB_SCALE_OFFSET 0x07D0
#define AM335X_USB_VID_PID_OFFSET 0x07F4
#define AM335X_EFUSE_SMA_OFFSET 0x07FC
#define AM335X_CQDETECT_STATUS_OFFSET 0x0E00
#define AM335X_DDR_IO_CTRL_OFFSET 0x0E04
#define AM335X_VTP_CTRL_OFFSET 0x0E0C
#define AM335X_VREF_CTRL_OFFSET 0x0E14
#define AM335X_TPCC_EVT_MUX_0_3_OFFSET 0x0F90
#define AM335X_TPCC_EVT_MUX_4_7_OFFSET 0x0F94
#define AM335X_TPCC_EVT_MUX_8_11_OFFSET 0x0F98
#define AM335X_TPCC_EVT_MUX_12_15_OFFSET 0x0F9C
#define AM335X_TPCC_EVT_MUX_16_19_OFFSET 0x0FA0
#define AM335X_TPCC_EVT_MUX_20_23_OFFSET 0x0FA4
#define AM335X_TPCC_EVT_MUX_24_27_OFFSET 0x0FA8
#define AM335X_TPCC_EVT_MUX_28_31_OFFSET 0x0FAC
#define AM335X_TPCC_EVT_MUX_32_35_OFFSET 0x0FB0
#define AM335X_TPCC_EVT_MUX_36_39_OFFSET 0x0FB4
#define AM335X_TPCC_EVT_MUX_40_43_OFFSET 0x0FB8
#define AM335X_TPCC_EVT_MUX_44_47_OFFSET 0x0FBC
#define AM335X_TPCC_EVT_MUX_48_51_OFFSET 0x0FC0
#define AM335X_TPCC_EVT_MUX_52_55_OFFSET 0x0FC4
#define AM335X_TPCC_EVT_MUX_56_59_OFFSET 0x0FC8
#define AM335X_TPCC_EVT_MUX_60_63_OFFSET 0x0FCC
#define AM335X_TIMER_EVT_CAPT_OFFSET 0x0FD0
#define AM335X_ECAP_EVT_CAPT_OFFSET 0x0FD4
#define AM335X_ADC_EVT_CAPT_OFFSET 0x0FD8
#define AM335X_RESET_ISO_OFFSET 0x1000
#define AM335X_DPLL_PWR_SW_CTRL_OFFSET 0x1318
#define AM335X_DDR_CKE_CTRL_OFFSET 0x131C
#define AM335X_SMA2_OFFSET 0x1320
#define AM335X_M3_TXEV_EOI_OFFSET 0x1324
#define AM335X_IPC_MSG_REG0_OFFSET 0x1328
#define AM335X_IPC_MSG_REG1_OFFSET 0x132C
#define AM335X_IPC_MSG_REG2_OFFSET 0x1330
#define AM335X_IPC_MSG_REG3_OFFSET 0x1334
#define AM335X_IPC_MSG_REG4_OFFSET 0x1338
#define AM335X_IPC_MSG_REG5_OFFSET 0x133C
#define AM335X_IPC_MSG_REG6_OFFSET 0x1340
#define AM335X_IPC_MSG_REG7_OFFSET 0x1344
#define AM335X_DDR_CMD0_IOCTRL_OFFSET 0x1404
#define AM335X_DDR_CMD1_IOCTRL_OFFSET 0x1408
#define AM335X_DDR_CMD2_IOCTRL_OFFSET 0x140C
#define AM335X_DDR_DATA0_IOCTRL_OFFSET 0x1440
#define AM335X_DDR_DATA1_IOCTRL_OFFSET 0x1444
/* Pad Control Registers */
/* Pad Control Register Indices (used by software for table lookups) */
#define AM335X_PADCTL_GPMC_AD0_INDEX 0
#define AM335X_PADCTL_GPMC_AD1_INDEX 1
#define AM335X_PADCTL_GPMC_AD2_INDEX 2
#define AM335X_PADCTL_GPMC_AD3_INDEX 3
#define AM335X_PADCTL_GPMC_AD4_INDEX 4
#define AM335X_PADCTL_GPMC_AD5_INDEX 5
#define AM335X_PADCTL_GPMC_AD6_INDEX 6
#define AM335X_PADCTL_GPMC_AD7_INDEX 7
#define AM335X_PADCTL_GPMC_AD8_INDEX 8
#define AM335X_PADCTL_GPMC_AD9_INDEX 9
#define AM335X_PADCTL_GPMC_AD10_INDEX 10
#define AM335X_PADCTL_GPMC_AD11_INDEX 11
#define AM335X_PADCTL_GPMC_AD12_INDEX 12
#define AM335X_PADCTL_GPMC_AD13_INDEX 13
#define AM335X_PADCTL_GPMC_AD14_INDEX 14
#define AM335X_PADCTL_GPMC_AD15_INDEX 15
#define AM335X_PADCTL_GPMC_A0_INDEX 16
#define AM335X_PADCTL_GPMC_A1_INDEX 17
#define AM335X_PADCTL_GPMC_A2_INDEX 18
#define AM335X_PADCTL_GPMC_A3_INDEX 19
#define AM335X_PADCTL_GPMC_A4_INDEX 20
#define AM335X_PADCTL_GPMC_A5_INDEX 21
#define AM335X_PADCTL_GPMC_A6_INDEX 22
#define AM335X_PADCTL_GPMC_A7_INDEX 23
#define AM335X_PADCTL_GPMC_A8_INDEX 24
#define AM335X_PADCTL_GPMC_A9_INDEX 25
#define AM335X_PADCTL_GPMC_A10_INDEX 26
#define AM335X_PADCTL_GPMC_A11_INDEX 27
#define AM335X_PADCTL_GPMC_WAIT0_INDEX 28
#define AM335X_PADCTL_GPMC_WPN_INDEX 29
#define AM335X_PADCTL_GPMC_BEN1_INDEX 30
#define AM335X_PADCTL_GPMC_CSN0_INDEX 31
#define AM335X_PADCTL_GPMC_CSN1_INDEX 32
#define AM335X_PADCTL_GPMC_CSN2_INDEX 33
#define AM335X_PADCTL_GPMC_CSN3_INDEX 34
#define AM335X_PADCTL_GPMC_CLK_INDEX 35
#define AM335X_PADCTL_GPMC_ADVN_ALE_INDEX 36
#define AM335X_PADCTL_GPMC_OEN_REN_INDEX 37
#define AM335X_PADCTL_GPMC_WEN_INDEX 38
#define AM335X_PADCTL_GPMC_BEN0_CLE_INDEX 39
#define AM335X_PADCTL_LCD_DATA0_INDEX 40
#define AM335X_PADCTL_LCD_DATA1_INDEX 41
#define AM335X_PADCTL_LCD_DATA2_INDEX 42
#define AM335X_PADCTL_LCD_DATA3_INDEX 43
#define AM335X_PADCTL_LCD_DATA4_INDEX 44
#define AM335X_PADCTL_LCD_DATA5_INDEX 45
#define AM335X_PADCTL_LCD_DATA6_INDEX 46
#define AM335X_PADCTL_LCD_DATA7_INDEX 47
#define AM335X_PADCTL_LCD_DATA8_INDEX 48
#define AM335X_PADCTL_LCD_DATA9_INDEX 49
#define AM335X_PADCTL_LCD_DATA10_INDEX 50
#define AM335X_PADCTL_LCD_DATA11_INDEX 51
#define AM335X_PADCTL_LCD_DATA12_INDEX 52
#define AM335X_PADCTL_LCD_DATA13_INDEX 53
#define AM335X_PADCTL_LCD_DATA14_INDEX 54
#define AM335X_PADCTL_LCD_DATA15_INDEX 55
#define AM335X_PADCTL_LCD_VSYNC_INDEX 56
#define AM335X_PADCTL_LCD_HSYNC_INDEX 57
#define AM335X_PADCTL_LCD_PCLK_INDEX 58
#define AM335X_PADCTL_LCD_AC_BIAS_EN_INDEX 59
#define AM335X_PADCTL_MMC0_DAT3_INDEX 60
#define AM335X_PADCTL_MMC0_DAT2_INDEX 61
#define AM335X_PADCTL_MMC0_DAT1_INDEX 62
#define AM335X_PADCTL_MMC0_DAT0_INDEX 63
#define AM335X_PADCTL_MMC0_CLK_INDEX 64
#define AM335X_PADCTL_MMC0_CMD_INDEX 65
#define AM335X_PADCTL_MII1_COL_INDEX 66
#define AM335X_PADCTL_MII1_CRS_INDEX 67
#define AM335X_PADCTL_MII1_RX_ER_INDEX 68
#define AM335X_PADCTL_MII1_TX_EN_INDEX 69
#define AM335X_PADCTL_MII1_RX_DV_INDEX 70
#define AM335X_PADCTL_MII1_TXD3_INDEX 71
#define AM335X_PADCTL_MII1_TXD2_INDEX 72
#define AM335X_PADCTL_MII1_TXD1_INDEX 73
#define AM335X_PADCTL_MII1_TXD0_INDEX 74
#define AM335X_PADCTL_MII1_TX_CLK_INDEX 75
#define AM335X_PADCTL_MII1_RX_CLK_INDEX 76
#define AM335X_PADCTL_MII1_RXD3_INDEX 77
#define AM335X_PADCTL_MII1_RXD2_INDEX 78
#define AM335X_PADCTL_MII1_RXD1_INDEX 79
#define AM335X_PADCTL_MII1_RXD0_INDEX 80
#define AM335X_PADCTL_RMII1_REF_CLK_INDEX 81
#define AM335X_PADCTL_MDIO_INDEX 82
#define AM335X_PADCTL_MDC_INDEX 83
#define AM335X_PADCTL_SPI0_SCLK_INDEX 84
#define AM335X_PADCTL_SPI0_D0_INDEX 85
#define AM335X_PADCTL_SPI0_D1_INDEX 86
#define AM335X_PADCTL_SPI0_CS0_INDEX 87
#define AM335X_PADCTL_SPI0_CS1_INDEX 88
#define AM335X_PADCTL_ECAP0_IN_PWM0_OUT_INDEX 89
#define AM335X_PADCTL_UART0_CTSN_INDEX 90
#define AM335X_PADCTL_UART0_RTSN_INDEX 91
#define AM335X_PADCTL_UART0_RXD_INDEX 92
#define AM335X_PADCTL_UART0_TXD_INDEX 93
#define AM335X_PADCTL_UART1_CTSN_INDEX 94
#define AM335X_PADCTL_UART1_RTSN_INDEX 95
#define AM335X_PADCTL_UART1_RXD_INDEX 96
#define AM335X_PADCTL_UART1_TXD_INDEX 97
#define AM335X_PADCTL_I2C0_SDA_INDEX 98
#define AM335X_PADCTL_I2C0_SCL_INDEX 99
#define AM335X_PADCTL_MCASP0_ACLKX_INDEX 100
#define AM335X_PADCTL_MCASP0_FSX_INDEX 101
#define AM335X_PADCTL_MCASP0_AXR0_INDEX 102
#define AM335X_PADCTL_MCASP0_AHCLKR_INDEX 103
#define AM335X_PADCTL_MCASP0_ACLKR_INDEX 104
#define AM335X_PADCTL_MCASP0_FSR_INDEX 105
#define AM335X_PADCTL_MCASP0_AXR1_INDEX 106
#define AM335X_PADCTL_MCASP0_AHCLKX_INDEX 107
#define AM335X_PADCTL_XDMA_EVENT_INTR0_INDEX 108
#define AM335X_PADCTL_XDMA_EVENT_INTR1_INDEX 109
#define AM335X_PADCTL_WARMRSTN_INDEX 110
#define AM335X_PADCTL_NNMI_INDEX 112
#define AM335X_PADCTL_TMS_INDEX 116
#define AM335X_PADCTL_TDI_INDEX 117
#define AM335X_PADCTL_TDO_INDEX 118
#define AM335X_PADCTL_TCK_INDEX 119
#define AM335X_PADCTL_TRSTN_INDEX 120
#define AM335X_PADCTL_EMU0_INDEX 121
#define AM335X_PADCTL_EMU1_INDEX 122
#define AM335X_PADCTL_RTC_PWRONRSTN_INDEX 126
#define AM335X_PADCTL_PMIC_POWER_EN_INDEX 127
#define AM335X_PADCTL_EXT_WAKEUP_INDEX 128
#define AM335X_PADCTL_RTC_KALDO_ENN_INDEX 129
#define AM335X_PADCTL_USB0_DRVVBUS_INDEX 135
#define AM335X_PADCTL_USB1_DRVVBUS_INDEX 141
#define AM335X_PADCTL_NREGISTERS 142
/* Pad Control Register Offsets */
#define AM335X_PADCTL_OFFSET(n) (0x0800 + ((unsigned int)(n) << 2))
#define AM335X_PADCTL_GPMC_AD0_OFFSET 0x0800
#define AM335X_PADCTL_GPMC_AD1_OFFSET 0x0804
#define AM335X_PADCTL_GPMC_AD2_OFFSET 0x0808
#define AM335X_PADCTL_GPMC_AD3_OFFSET 0x080C
#define AM335X_PADCTL_GPMC_AD4_OFFSET 0x0810
#define AM335X_PADCTL_GPMC_AD5_OFFSET 0x0814
#define AM335X_PADCTL_GPMC_AD6_OFFSET 0x0818
#define AM335X_PADCTL_GPMC_AD7_OFFSET 0x081C
#define AM335X_PADCTL_GPMC_AD8_OFFSET 0x0820
#define AM335X_PADCTL_GPMC_AD9_OFFSET 0x0824
#define AM335X_PADCTL_GPMC_AD10_OFFSET 0x0828
#define AM335X_PADCTL_GPMC_AD11_OFFSET 0x082C
#define AM335X_PADCTL_GPMC_AD12_OFFSET 0x0830
#define AM335X_PADCTL_GPMC_AD13_OFFSET 0x0834
#define AM335X_PADCTL_GPMC_AD14_OFFSET 0x0838
#define AM335X_PADCTL_GPMC_AD15_OFFSET 0x083C
#define AM335X_PADCTL_GPMC_A0_OFFSET 0x0840
#define AM335X_PADCTL_GPMC_A1_OFFSET 0x0844
#define AM335X_PADCTL_GPMC_A2_OFFSET 0x0848
#define AM335X_PADCTL_GPMC_A3_OFFSET 0x084C
#define AM335X_PADCTL_GPMC_A4_OFFSET 0x0850
#define AM335X_PADCTL_GPMC_A5_OFFSET 0x0854
#define AM335X_PADCTL_GPMC_A6_OFFSET 0x0858
#define AM335X_PADCTL_GPMC_A7_OFFSET 0x085C
#define AM335X_PADCTL_GPMC_A8_OFFSET 0x0860
#define AM335X_PADCTL_GPMC_A9_OFFSET 0x0864
#define AM335X_PADCTL_GPMC_A10_OFFSET 0x0868
#define AM335X_PADCTL_GPMC_A11_OFFSET 0x086C
#define AM335X_PADCTL_GPMC_WAIT0_OFFSET 0x0870
#define AM335X_PADCTL_GPMC_WPN_OFFSET 0x0874
#define AM335X_PADCTL_GPMC_BEN1_OFFSET 0x0878
#define AM335X_PADCTL_GPMC_CSN0_OFFSET 0x087C
#define AM335X_PADCTL_GPMC_CSN1_OFFSET 0x0880
#define AM335X_PADCTL_GPMC_CSN2_OFFSET 0x0884
#define AM335X_PADCTL_GPMC_CSN3_OFFSET 0x0888
#define AM335X_PADCTL_GPMC_CLK_OFFSET 0x088C
#define AM335X_PADCTL_GPMC_ADVN_ALE_OFFSET 0x0890
#define AM335X_PADCTL_GPMC_OEN_REN_OFFSET 0x0894
#define AM335X_PADCTL_GPMC_WEN_OFFSET 0x0898
#define AM335X_PADCTL_GPMC_BEN0_CLE_OFFSET 0x089C
#define AM335X_PADCTL_LCD_DATA0_OFFSET 0x08A0
#define AM335X_PADCTL_LCD_DATA1_OFFSET 0x08A4
#define AM335X_PADCTL_LCD_DATA2_OFFSET 0x08A8
#define AM335X_PADCTL_LCD_DATA3_OFFSET 0x08AC
#define AM335X_PADCTL_LCD_DATA4_OFFSET 0x08B0
#define AM335X_PADCTL_LCD_DATA5_OFFSET 0x08B4
#define AM335X_PADCTL_LCD_DATA6_OFFSET 0x08B8
#define AM335X_PADCTL_LCD_DATA7_OFFSET 0x08BC
#define AM335X_PADCTL_LCD_DATA8_OFFSET 0x08C0
#define AM335X_PADCTL_LCD_DATA9_OFFSET 0x08C4
#define AM335X_PADCTL_LCD_DATA10_OFFSET 0x08C8
#define AM335X_PADCTL_LCD_DATA11_OFFSET 0x08CC
#define AM335X_PADCTL_LCD_DATA12_OFFSET 0x08D0
#define AM335X_PADCTL_LCD_DATA13_OFFSET 0x08D4
#define AM335X_PADCTL_LCD_DATA14_OFFSET 0x08D8
#define AM335X_PADCTL_LCD_DATA15_OFFSET 0x08DC
#define AM335X_PADCTL_LCD_VSYNC_OFFSET 0x08E0
#define AM335X_PADCTL_LCD_HSYNC_OFFSET 0x08E4
#define AM335X_PADCTL_LCD_PCLK_OFFSET 0x08E8
#define AM335X_PADCTL_LCD_AC_BIAS_EN_OFFSET 0x08EC
#define AM335X_PADCTL_MMC0_DAT3_OFFSET 0x08F0
#define AM335X_PADCTL_MMC0_DAT2_OFFSET 0x08F4
#define AM335X_PADCTL_MMC0_DAT1_OFFSET 0x08F8
#define AM335X_PADCTL_MMC0_DAT0_OFFSET 0x08FC
#define AM335X_PADCTL_MMC0_CLK_OFFSET 0x0900
#define AM335X_PADCTL_MMC0_CMD_OFFSET 0x0904
#define AM335X_PADCTL_MII1_COL_OFFSET 0x0908
#define AM335X_PADCTL_MII1_CRS_OFFSET 0x090C
#define AM335X_PADCTL_MII1_RX_ER_OFFSET 0x0910
#define AM335X_PADCTL_MII1_TX_EN_OFFSET 0x0914
#define AM335X_PADCTL_MII1_RX_DV_OFFSET 0x0918
#define AM335X_PADCTL_MII1_TXD3_OFFSET 0x091C
#define AM335X_PADCTL_MII1_TXD2_OFFSET 0x0920
#define AM335X_PADCTL_MII1_TXD1_OFFSET 0x0924
#define AM335X_PADCTL_MII1_TXD0_OFFSET 0x0928
#define AM335X_PADCTL_MII1_TX_CLK_OFFSET 0x092C
#define AM335X_PADCTL_MII1_RX_CLK_OFFSET 0x0930
#define AM335X_PADCTL_MII1_RXD3_OFFSET 0x0934
#define AM335X_PADCTL_MII1_RXD2_OFFSET 0x0938
#define AM335X_PADCTL_MII1_RXD1_OFFSET 0x093C
#define AM335X_PADCTL_MII1_RXD0_OFFSET 0x0940
#define AM335X_PADCTL_RMII1_REF_CLK_OFFSET 0x0944
#define AM335X_PADCTL_MDIO_OFFSET 0x0948
#define AM335X_PADCTL_MDC_OFFSET 0x094C
#define AM335X_PADCTL_SPI0_SCLK_OFFSET 0x0950
#define AM335X_PADCTL_SPI0_D0_OFFSET 0x0954
#define AM335X_PADCTL_SPI0_D1_OFFSET 0x0958
#define AM335X_PADCTL_SPI0_CS0_OFFSET 0x095C
#define AM335X_PADCTL_SPI0_CS1_OFFSET 0x0960
#define AM335X_PADCTL_ECAP0_IN_PWM0_OUT_OFFSET 0x0964
#define AM335X_PADCTL_UART0_CTSN_OFFSET 0x0968
#define AM335X_PADCTL_UART0_RTSN_OFFSET 0x096C
#define AM335X_PADCTL_UART0_RXD_OFFSET 0x0970
#define AM335X_PADCTL_UART0_TXD_OFFSET 0x0974
#define AM335X_PADCTL_UART1_CTSN_OFFSET 0x0978
#define AM335X_PADCTL_UART1_RTSN_OFFSET 0x097C
#define AM335X_PADCTL_UART1_RXD_OFFSET 0x0980
#define AM335X_PADCTL_UART1_TXD_OFFSET 0x0984
#define AM335X_PADCTL_I2C0_SDA_OFFSET 0x0988
#define AM335X_PADCTL_I2C0_SCL_OFFSET 0x098C
#define AM335X_PADCTL_MCASP0_ACLKX_OFFSET 0x0990
#define AM335X_PADCTL_MCASP0_FSX_OFFSET 0x0994
#define AM335X_PADCTL_MCASP0_AXR0_OFFSET 0x0998
#define AM335X_PADCTL_MCASP0_AHCLKR_OFFSET 0x099C
#define AM335X_PADCTL_MCASP0_ACLKR_OFFSET 0x09A0
#define AM335X_PADCTL_MCASP0_FSR_OFFSET 0x09A4
#define AM335X_PADCTL_MCASP0_AXR1_OFFSET 0x09A8
#define AM335X_PADCTL_MCASP0_AhCLKX_OFFSET 0x09AC
#define AM335X_PADCTL_XDMA_EVENT_INTR0_OFFSET 0x09B0
#define AM335X_PADCTL_XDMA_EVENT_INTR1_OFFSET 0x09B4
#define AM335X_PADCTL_WARMRSTN_OFFSET 0x09B8
#define AM335X_PADCTL_NNMI_OFFSET 0x09C0
#define AM335X_PADCTL_TMS_OFFSET 0x09D0
#define AM335X_PADCTL_TDI_OFFSET 0x09D4
#define AM335X_PADCTL_TDO_OFFSET 0x09D8
#define AM335X_PADCTL_TCK_OFFSET 0x09DC
#define AM335X_PADCTL_TRSTN_OFFSET 0x09E0
#define AM335X_PADCTL_EMU0_OFFSET 0x09E4
#define AM335X_PADCTL_EMU1_OFFSET 0x09E8
#define AM335X_PADCTL_RTC_PWRONRSTN_OFFSET 0x09F8
#define AM335X_PADCTL_PMIC_POWER_EN_OFFSET 0x09FC
#define AM335X_PADCTL_EXT_WAKEUP_OFFSET 0x0A00
#define AM335X_PADCTL_RTC_KALDO_ENN_OFFSET 0x0A04
#define AM335X_PADCTL_USB0_DRVVBUS_OFFSET 0x0A1C
#define AM335X_PADCTL_USB1_DRVVBUS_OFFSET 0x0A34
/* Control Module Register Addresses ********************************************************/
#define AM335X_CONTROL_SYS_CONF (AM335X_CONTROL_MODULE_VADDR + AM335X_CONTROL_SYS_CONF_OFFSET)
#define AM335X_CONTROL_STATUS (AM335X_CONTROL_MODULE_VADDR + AM335X_CONTROL_STATUS_OFFSET)
#define AM335X_CONTROL_EMIF_SDRAM_CONF (AM335X_CONTROL_MODULE_VADDR + AM335X_CONTROL_EMIF_SDRAM_CONF_OFFSET)
#define AM335X_CORE_SLDO_CTRL (AM335X_CONTROL_MODULE_VADDR + AM335X_CORE_SLDO_CTRL_OFFSET)
#define AM335X_MPU_SLDO_CTRL (AM335X_CONTROL_MODULE_VADDR + AM335X_MPU_SLDO_CTRL_OFFSET)
#define AM335X_CLK32KDIVRATIO_CTRL (AM335X_CONTROL_MODULE_VADDR + AM335X_CLK32KDIVRATIO_CTRL_OFFSET)
#define AM335X_BANDGAP_CTRL (AM335X_CONTROL_MODULE_VADDR + AM335X_BANDGAP_CTRL_OFFSET)
#define AM335X_BANDGAP_TRIM (AM335X_CONTROL_MODULE_VADDR + AM335X_BANDGAP_TRIM_OFFSET)
#define AM335X_PLL_CLKINPULOW_CTRL (AM335X_CONTROL_MODULE_VADDR + AM335X_PLL_CLKINPULOW_CTRL_OFFSET)
#define AM335X_MOSC_CTRL (AM335X_CONTROL_MODULE_VADDR + AM335X_MOSC_CTRL_OFFSET)
#define AM335X_DEEPSLEEP_CTRL (AM335X_CONTROL_MODULE_VADDR + AM335X_DEEPSLEEP_CTRL_OFFSET)
#define AM335X_DPLL_PWR_SW_STATUS (AM335X_CONTROL_MODULE_VADDR + AM335X_DPLL_PWR_SW_STATUS_OFFSET)
#define AM335X_DEVICE_ID (AM335X_CONTROL_MODULE_VADDR + AM335X_DEVICE_ID_OFFSET)
#define AM335X_DEV_FEATURE (AM335X_CONTROL_MODULE_VADDR + AM335X_DEV_FEATURE_OFFSET)
#define AM335X_INIT_PRIORITY_0 (AM335X_CONTROL_MODULE_VADDR + AM335X_INIT_PRIORITY_0_OFFSET)
#define AM335X_INIT_PRIORITY_1 (AM335X_CONTROL_MODULE_VADDR + AM335X_INIT_PRIORITY_1_OFFSET)
#define AM335X_TPTC_CFG (AM335X_CONTROL_MODULE_VADDR + AM335X_TPTC_CFG_OFFSET)
#define AM335X_USB_CTRL0 (AM335X_CONTROL_MODULE_VADDR + AM335X_USB_CTRL0_OFFSET)
#define AM335X_USB_STS0 (AM335X_CONTROL_MODULE_VADDR + AM335X_USB_STS0_OFFSET)
#define AM335X_USB_CTRL1 (AM335X_CONTROL_MODULE_VADDR + AM335X_USB_CTRL1_OFFSET)
#define AM335X_USB_STS1 (AM335X_CONTROL_MODULE_VADDR + AM335X_USB_STS1_OFFSET)
#define AM335X_MAC_ID0_LO (AM335X_CONTROL_MODULE_VADDR + AM335X_MAC_ID0_LO_OFFSET)
#define AM335X_MAC_ID0_HI (AM335X_CONTROL_MODULE_VADDR + AM335X_MAC_ID0_HI_OFFSET)
#define AM335X_MAC_ID1_LO (AM335X_CONTROL_MODULE_VADDR + AM335X_MAC_ID1_LO_OFFSET)
#define AM335X_MAC_ID1_HI (AM335X_CONTROL_MODULE_VADDR + AM335X_MAC_ID1_HI_OFFSET)
#define AM335X_DCAN_RAMINIT (AM335X_CONTROL_MODULE_VADDR + AM335X_DCAN_RAMINIT_OFFSET)
#define AM335X_USB_WKUP_CTRL (AM335X_CONTROL_MODULE_VADDR + AM335X_USB_WKUP_CTRL_OFFSET)
#define AM335X_GMII_SEL (AM335X_CONTROL_MODULE_VADDR + AM335X_GMII_SEL_OFFSET)
#define AM335X_PWMSS_CTRL (AM335X_CONTROL_MODULE_VADDR + AM335X_PWMSS_CTRL_OFFSET)
#define AM335X_MREGPRIO_0 (AM335X_CONTROL_MODULE_VADDR + AM335X_MREGPRIO_0_OFFSET)
#define AM335X_MREGPRIO_1 (AM335X_CONTROL_MODULE_VADDR + AM335X_MREGPRIO_1_OFFSET)
#define AM335X_HW_EVENT_SEL_GRP1 (AM335X_CONTROL_MODULE_VADDR + AM335X_HW_EVENT_SEL_GRP1_OFFSET)
#define AM335X_HW_EVENT_SEL_GRP2 (AM335X_CONTROL_MODULE_VADDR + AM335X_HW_EVENT_SEL_GRP2_OFFSET)
#define AM335X_HW_EVENT_SEL_GRP3 (AM335X_CONTROL_MODULE_VADDR + AM335X_HW_EVENT_SEL_GRP3_OFFSET)
#define AM335X_HW_EVENT_SEL_GRP4 (AM335X_CONTROL_MODULE_VADDR + AM335X_HW_EVENT_SEL_GRP4_OFFSET)
#define AM335X_SMRT_CTRL (AM335X_CONTROL_MODULE_VADDR + AM335X_SMRT_CTRL_OFFSET)
#define AM335X_MPUSS_HW_DEBUG_SEL (AM335X_CONTROL_MODULE_VADDR + AM335X_MPUSS_HW_DEBUG_SEL_OFFSET)
#define AM335X_MPUSS_HW_DBG_INFO (AM335X_CONTROL_MODULE_VADDR + AM335X_MPUSS_HW_DBG_INFO_OFFSET)
#define AM335X_VDD_MPU_OPP_050 (AM335X_CONTROL_MODULE_VADDR + AM335X_VDD_MPU_OPP_050_OFFSET)
#define AM335X_VDD_MPU_OPP_100 (AM335X_CONTROL_MODULE_VADDR + AM335X_VDD_MPU_OPP_100_OFFSET)
#define AM335X_VDD_MPU_OPP_120 (AM335X_CONTROL_MODULE_VADDR + AM335X_VDD_MPU_OPP_120_OFFSET)
#define AM335X_VDD_MPU_OPP_TURBO (AM335X_CONTROL_MODULE_VADDR + AM335X_VDD_MPU_OPP_TURBO_OFFSET)
#define AM335X_VDD_CORE_OPP_050 (AM335X_CONTROL_MODULE_VADDR + AM335X_VDD_CORE_OPP_050_OFFSET)
#define AM335X_VDD_CORE_OPP_100 (AM335X_CONTROL_MODULE_VADDR + AM335X_VDD_CORE_OPP_100_OFFSET)
#define AM335X_BB_SCALE (AM335X_CONTROL_MODULE_VADDR + AM335X_BB_SCALE_OFFSET)
#define AM335X_USB_VID_PID (AM335X_CONTROL_MODULE_VADDR + AM335X_USB_VID_PID_OFFSET)
#define AM335X_EFUSE_SMA (AM335X_CONTROL_MODULE_VADDR + AM335X_EFUSE_SMA_OFFSET)
#define AM335X_CQDETECT_STATUS (AM335X_CONTROL_MODULE_VADDR + AM335X_CQDETECT_STATUS_OFFSET)
#define AM335X_DDR_IO_CTRL (AM335X_CONTROL_MODULE_VADDR + AM335X_DDR_IO_CTRL_OFFSET)
#define AM335X_VTP_CTRL (AM335X_CONTROL_MODULE_VADDR + AM335X_VTP_CTRL_OFFSET)
#define AM335X_VREF_CTRL (AM335X_CONTROL_MODULE_VADDR + AM335X_VREF_CTRL_OFFSET)
#define AM335X_TPCC_EVT_MUX_0_3 (AM335X_CONTROL_MODULE_VADDR + AM335X_TPCC_EVT_MUX_0_3_OFFSET)
#define AM335X_TPCC_EVT_MUX_4_7 (AM335X_CONTROL_MODULE_VADDR + AM335X_TPCC_EVT_MUX_4_7_OFFSET)
#define AM335X_TPCC_EVT_MUX_8_11 (AM335X_CONTROL_MODULE_VADDR + AM335X_TPCC_EVT_MUX_8_11_OFFSET)
#define AM335X_TPCC_EVT_MUX_12_15 (AM335X_CONTROL_MODULE_VADDR + AM335X_TPCC_EVT_MUX_12_15_OFFSET)
#define AM335X_TPCC_EVT_MUX_16_19 (AM335X_CONTROL_MODULE_VADDR + AM335X_TPCC_EVT_MUX_16_19_OFFSET)
#define AM335X_TPCC_EVT_MUX_20_23 (AM335X_CONTROL_MODULE_VADDR + AM335X_TPCC_EVT_MUX_20_23_OFFSET)
#define AM335X_TPCC_EVT_MUX_24_27 (AM335X_CONTROL_MODULE_VADDR + AM335X_TPCC_EVT_MUX_24_27_OFFSET)
#define AM335X_TPCC_EVT_MUX_28_31 (AM335X_CONTROL_MODULE_VADDR + AM335X_TPCC_EVT_MUX_28_31_OFFSET)
#define AM335X_TPCC_EVT_MUX_32_35 (AM335X_CONTROL_MODULE_VADDR + AM335X_TPCC_EVT_MUX_32_35_OFFSET)
#define AM335X_TPCC_EVT_MUX_36_39 (AM335X_CONTROL_MODULE_VADDR + AM335X_TPCC_EVT_MUX_36_39_OFFSET)
#define AM335X_TPCC_EVT_MUX_40_43 (AM335X_CONTROL_MODULE_VADDR + AM335X_TPCC_EVT_MUX_40_43_OFFSET)
#define AM335X_TPCC_EVT_MUX_44_47 (AM335X_CONTROL_MODULE_VADDR + AM335X_TPCC_EVT_MUX_44_47_OFFSET)
#define AM335X_TPCC_EVT_MUX_48_51 (AM335X_CONTROL_MODULE_VADDR + AM335X_TPCC_EVT_MUX_48_51_OFFSET)
#define AM335X_TPCC_EVT_MUX_52_55 (AM335X_CONTROL_MODULE_VADDR + AM335X_TPCC_EVT_MUX_52_55_OFFSET)
#define AM335X_TPCC_EVT_MUX_56_59 (AM335X_CONTROL_MODULE_VADDR + AM335X_TPCC_EVT_MUX_56_59_OFFSET)
#define AM335X_TPCC_EVT_MUX_60_63 (AM335X_CONTROL_MODULE_VADDR + AM335X_TPCC_EVT_MUX_60_63_OFFSET)
#define AM335X_TIMER_EVT_CAPT (AM335X_CONTROL_MODULE_VADDR + AM335X_TIMER_EVT_CAPT_OFFSET)
#define AM335X_ECAP_EVT_CAPT (AM335X_CONTROL_MODULE_VADDR + AM335X_ECAP_EVT_CAPT_OFFSET)
#define AM335X_ADC_EVT_CAPT (AM335X_CONTROL_MODULE_VADDR + AM335X_ADC_EVT_CAPT_OFFSET)
#define AM335X_RESET_ISO (AM335X_CONTROL_MODULE_VADDR + AM335X_RESET_ISO_OFFSET)
#define AM335X_DPLL_PWR_SW_CTRL (AM335X_CONTROL_MODULE_VADDR + AM335X_DPLL_PWR_SW_CTRL_OFFSET)
#define AM335X_DDR_CKE_CTRL (AM335X_CONTROL_MODULE_VADDR + AM335X_DDR_CKE_CTRL_OFFSET)
#define AM335X_SMA2 (AM335X_CONTROL_MODULE_VADDR + AM335X_SMA2_OFFSET)
#define AM335X_M3_TXEV_EOI (AM335X_CONTROL_MODULE_VADDR + AM335X_M3_TXEV_EOI_OFFSET)
#define AM335X_IPC_MSG_REG0 (AM335X_CONTROL_MODULE_VADDR + AM335X_IPC_MSG_REG0_OFFSET)
#define AM335X_IPC_MSG_REG1 (AM335X_CONTROL_MODULE_VADDR + AM335X_IPC_MSG_REG1_OFFSET)
#define AM335X_IPC_MSG_REG2 (AM335X_CONTROL_MODULE_VADDR + AM335X_IPC_MSG_REG2_OFFSET)
#define AM335X_IPC_MSG_REG3 (AM335X_CONTROL_MODULE_VADDR + AM335X_IPC_MSG_REG3_OFFSET)
#define AM335X_IPC_MSG_REG4 (AM335X_CONTROL_MODULE_VADDR + AM335X_IPC_MSG_REG4_OFFSET)
#define AM335X_IPC_MSG_REG5 (AM335X_CONTROL_MODULE_VADDR + AM335X_IPC_MSG_REG5_OFFSET)
#define AM335X_IPC_MSG_REG6 (AM335X_CONTROL_MODULE_VADDR + AM335X_IPC_MSG_REG6_OFFSET)
#define AM335X_IPC_MSG_REG7 (AM335X_CONTROL_MODULE_VADDR + AM335X_IPC_MSG_REG7_OFFSET)
#define AM335X_DDR_CMD0_IOCTRL (AM335X_CONTROL_MODULE_VADDR + AM335X_DDR_CMD0_IOCTRL_OFFSET)
#define AM335X_DDR_CMD1_IOCTRL (AM335X_CONTROL_MODULE_VADDR + AM335X_DDR_CMD1_IOCTRL_OFFSET)
#define AM335X_DDR_CMD2_IOCTRL (AM335X_CONTROL_MODULE_VADDR + AM335X_DDR_CMD2_IOCTRL_OFFSET)
#define AM335X_DDR_DATA0_IOCTRL (AM335X_CONTROL_MODULE_VADDR + AM335X_DDR_DATA0_IOCTRL_OFFSET)
#define AM335X_DDR_DATA1_IOCTRL (AM335X_CONTROL_MODULE_VADDR + AM335X_DDR_DATA1_IOCTRL_OFFSET)
/* Pad Control Registers */
#define AM335X_PADCTL_ADDRESS(n) (AM335X_CONTROL_MODULE_VADDR + AM335X_PADCTL_OFFSET(n))
#define AM335X_PADCTL_GPMC_AD0 (AM335X_CONTROL_MODULE_VADDR + AM335X_PADCTL_GPMC_AD0_OFFSET)
#define AM335X_PADCTL_GPMC_AD1 (AM335X_CONTROL_MODULE_VADDR + AM335X_PADCTL_GPMC_AD1_OFFSET)
#define AM335X_PADCTL_GPMC_AD2 (AM335X_CONTROL_MODULE_VADDR + AM335X_PADCTL_GPMC_AD2_OFFSET)
#define AM335X_PADCTL_GPMC_AD3 (AM335X_CONTROL_MODULE_VADDR + AM335X_PADCTL_GPMC_AD3_OFFSET)
#define AM335X_PADCTL_GPMC_AD4 (AM335X_CONTROL_MODULE_VADDR + AM335X_PADCTL_GPMC_AD4_OFFSET)
#define AM335X_PADCTL_GPMC_AD5 (AM335X_CONTROL_MODULE_VADDR + AM335X_PADCTL_GPMC_AD5_OFFSET)
#define AM335X_PADCTL_GPMC_AD6 (AM335X_CONTROL_MODULE_VADDR + AM335X_PADCTL_GPMC_AD6_OFFSET)
#define AM335X_PADCTL_GPMC_AD7 (AM335X_CONTROL_MODULE_VADDR + AM335X_PADCTL_GPMC_AD7_OFFSET)
#define AM335X_PADCTL_GPMC_AD8 (AM335X_CONTROL_MODULE_VADDR + AM335X_PADCTL_GPMC_AD8_OFFSET)
#define AM335X_PADCTL_GPMC_AD9 (AM335X_CONTROL_MODULE_VADDR + AM335X_PADCTL_GPMC_AD9_OFFSET)
#define AM335X_PADCTL_GPMC_AD10 (AM335X_CONTROL_MODULE_VADDR + AM335X_PADCTL_GPMC_AD10_OFFSET)
#define AM335X_PADCTL_GPMC_AD11 (AM335X_CONTROL_MODULE_VADDR + AM335X_PADCTL_GPMC_AD11_OFFSET)
#define AM335X_PADCTL_GPMC_AD12 (AM335X_CONTROL_MODULE_VADDR + AM335X_PADCTL_GPMC_AD12_OFFSET)
#define AM335X_PADCTL_GPMC_AD13 (AM335X_CONTROL_MODULE_VADDR + AM335X_PADCTL_GPMC_AD13_OFFSET)
#define AM335X_PADCTL_GPMC_AD14 (AM335X_CONTROL_MODULE_VADDR + AM335X_PADCTL_GPMC_AD14_OFFSET)
#define AM335X_PADCTL_GPMC_AD15 (AM335X_CONTROL_MODULE_VADDR + AM335X_PADCTL_GPMC_AD15_OFFSET)
#define AM335X_PADCTL_GPMC_A0 (AM335X_CONTROL_MODULE_VADDR + AM335X_PADCTL_GPMC_A0_OFFSET)
#define AM335X_PADCTL_GPMC_A1 (AM335X_CONTROL_MODULE_VADDR + AM335X_PADCTL_GPMC_A1_OFFSET)
#define AM335X_PADCTL_GPMC_A2 (AM335X_CONTROL_MODULE_VADDR + AM335X_PADCTL_GPMC_A2_OFFSET)
#define AM335X_PADCTL_GPMC_A3 (AM335X_CONTROL_MODULE_VADDR + AM335X_PADCTL_GPMC_A3_OFFSET)
#define AM335X_PADCTL_GPMC_A4 (AM335X_CONTROL_MODULE_VADDR + AM335X_PADCTL_GPMC_A4_OFFSET)
#define AM335X_PADCTL_GPMC_A5 (AM335X_CONTROL_MODULE_VADDR + AM335X_PADCTL_GPMC_A5_OFFSET)
#define AM335X_PADCTL_GPMC_A6 (AM335X_CONTROL_MODULE_VADDR + AM335X_PADCTL_GPMC_A6_OFFSET)
#define AM335X_PADCTL_GPMC_A7 (AM335X_CONTROL_MODULE_VADDR + AM335X_PADCTL_GPMC_A7_OFFSET)
#define AM335X_PADCTL_GPMC_A8 (AM335X_CONTROL_MODULE_VADDR + AM335X_PADCTL_GPMC_A8_OFFSET)
#define AM335X_PADCTL_GPMC_A9 (AM335X_CONTROL_MODULE_VADDR + AM335X_PADCTL_GPMC_A9_OFFSET)
#define AM335X_PADCTL_GPMC_A10 (AM335X_CONTROL_MODULE_VADDR + AM335X_PADCTL_GPMC_A10_OFFSET)
#define AM335X_PADCTL_GPMC_A11 (AM335X_CONTROL_MODULE_VADDR + AM335X_PADCTL_GPMC_A11_OFFSET)
#define AM335X_PADCTL_GPMC_WAIT0 (AM335X_CONTROL_MODULE_VADDR + AM335X_PADCTL_GPMC_WAIT0_OFFSET)
#define AM335X_PADCTL_GPMC_WPN (AM335X_CONTROL_MODULE_VADDR + AM335X_PADCTL_GPMC_WPN_OFFSET)
#define AM335X_PADCTL_GPMC_BEN1 (AM335X_CONTROL_MODULE_VADDR + AM335X_PADCTL_GPMC_BEN1_OFFSET)
#define AM335X_PADCTL_GPMC_CSN0 (AM335X_CONTROL_MODULE_VADDR + AM335X_PADCTL_GPMC_CSN0_OFFSET)
#define AM335X_PADCTL_GPMC_CSN1 (AM335X_CONTROL_MODULE_VADDR + AM335X_PADCTL_GPMC_CSN1_OFFSET)
#define AM335X_PADCTL_GPMC_CSN2 (AM335X_CONTROL_MODULE_VADDR + AM335X_PADCTL_GPMC_CSN2_OFFSET)
#define AM335X_PADCTL_GPMC_CSN3 (AM335X_CONTROL_MODULE_VADDR + AM335X_PADCTL_GPMC_CSN3_OFFSET)
#define AM335X_PADCTL_GPMC_CLK (AM335X_CONTROL_MODULE_VADDR + AM335X_PADCTL_GPMC_CLK_OFFSET)
#define AM335X_PADCTL_GPMC_ADVN_ALE (AM335X_CONTROL_MODULE_VADDR + AM335X_PADCTL_GPMC_ADVN_ALE_OFFSET)
#define AM335X_PADCTL_GPMC_OEN_REN (AM335X_CONTROL_MODULE_VADDR + AM335X_PADCTL_GPMC_OEN_REN_OFFSET)
#define AM335X_PADCTL_GPMC_WEN (AM335X_CONTROL_MODULE_VADDR + AM335X_PADCTL_GPMC_WEN_OFFSET)
#define AM335X_PADCTL_GPMC_BEN0_CLE (AM335X_CONTROL_MODULE_VADDR + AM335X_PADCTL_GPMC_BEN0_CLE_OFFSET)
#define AM335X_PADCTL_LCD_DATA0 (AM335X_CONTROL_MODULE_VADDR + AM335X_PADCTL_LCD_DATA0_OFFSET)
#define AM335X_PADCTL_LCD_DATA1 (AM335X_CONTROL_MODULE_VADDR + AM335X_PADCTL_LCD_DATA1_OFFSET)
#define AM335X_PADCTL_LCD_DATA2 (AM335X_CONTROL_MODULE_VADDR + AM335X_PADCTL_LCD_DATA2_OFFSET)
#define AM335X_PADCTL_LCD_DATA3 (AM335X_CONTROL_MODULE_VADDR + AM335X_PADCTL_LCD_DATA3_OFFSET)
#define AM335X_PADCTL_LCD_DATA4 (AM335X_CONTROL_MODULE_VADDR + AM335X_PADCTL_LCD_DATA4_OFFSET)
#define AM335X_PADCTL_LCD_DATA5 (AM335X_CONTROL_MODULE_VADDR + AM335X_PADCTL_LCD_DATA5_OFFSET)
#define AM335X_PADCTL_LCD_DATA6 (AM335X_CONTROL_MODULE_VADDR + AM335X_PADCTL_LCD_DATA6_OFFSET)
#define AM335X_PADCTL_LCD_DATA7 (AM335X_CONTROL_MODULE_VADDR + AM335X_PADCTL_LCD_DATA7_OFFSET)
#define AM335X_PADCTL_LCD_DATA8 (AM335X_CONTROL_MODULE_VADDR + AM335X_PADCTL_LCD_DATA8_OFFSET)
#define AM335X_PADCTL_LCD_DATA9 (AM335X_CONTROL_MODULE_VADDR + AM335X_PADCTL_LCD_DATA9_OFFSET)
#define AM335X_PADCTL_LCD_DATA10 (AM335X_CONTROL_MODULE_VADDR + AM335X_PADCTL_LCD_DATA10_OFFSET)
#define AM335X_PADCTL_LCD_DATA11 (AM335X_CONTROL_MODULE_VADDR + AM335X_PADCTL_LCD_DATA11_OFFSET)
#define AM335X_PADCTL_LCD_DATA12 (AM335X_CONTROL_MODULE_VADDR + AM335X_PADCTL_LCD_DATA12_OFFSET)
#define AM335X_PADCTL_LCD_DATA13 (AM335X_CONTROL_MODULE_VADDR + AM335X_PADCTL_LCD_DATA13_OFFSET)
#define AM335X_PADCTL_LCD_DATA14 (AM335X_CONTROL_MODULE_VADDR + AM335X_PADCTL_LCD_DATA14_OFFSET)
#define AM335X_PADCTL_LCD_DATA15 (AM335X_CONTROL_MODULE_VADDR + AM335X_PADCTL_LCD_DATA15_OFFSET)
#define AM335X_PADCTL_LCD_VSYNC (AM335X_CONTROL_MODULE_VADDR + AM335X_PADCTL_LCD_VSYNC_OFFSET)
#define AM335X_PADCTL_LCD_HSYNC (AM335X_CONTROL_MODULE_VADDR + AM335X_PADCTL_LCD_HSYNC_OFFSET)
#define AM335X_PADCTL_LCD_PCLK (AM335X_CONTROL_MODULE_VADDR + AM335X_PADCTL_LCD_PCLK_OFFSET)
#define AM335X_PADCTL_LCD_AC_BIAS_EN (AM335X_CONTROL_MODULE_VADDR + AM335X_PADCTL_LCD_AC_BIAS_EN_OFFSET)
#define AM335X_PADCTL_MMC0_DAT3 (AM335X_CONTROL_MODULE_VADDR + AM335X_PADCTL_MMC0_DAT3_OFFSET)
#define AM335X_PADCTL_MMC0_DAT2 (AM335X_CONTROL_MODULE_VADDR + AM335X_PADCTL_MMC0_DAT2_OFFSET)
#define AM335X_PADCTL_MMC0_DAT1 (AM335X_CONTROL_MODULE_VADDR + AM335X_PADCTL_MMC0_DAT1_OFFSET)
#define AM335X_PADCTL_MMC0_DAT0 (AM335X_CONTROL_MODULE_VADDR + AM335X_PADCTL_MMC0_DAT0_OFFSET)
#define AM335X_PADCTL_MMC0_CLK (AM335X_CONTROL_MODULE_VADDR + AM335X_PADCTL_MMC0_CLK_OFFSET)
#define AM335X_PADCTL_MMC0_CMD (AM335X_CONTROL_MODULE_VADDR + AM335X_PADCTL_MMC0_CMD_OFFSET)
#define AM335X_PADCTL_MII1_COL (AM335X_CONTROL_MODULE_VADDR + AM335X_PADCTL_MII1_COL_OFFSET)
#define AM335X_PADCTL_MII1_CRS (AM335X_CONTROL_MODULE_VADDR + AM335X_PADCTL_MII1_CRS_OFFSET)
#define AM335X_PADCTL_MII1_RX_ER (AM335X_CONTROL_MODULE_VADDR + AM335X_PADCTL_MII1_RX_ER_OFFSET)
#define AM335X_PADCTL_MII1_TX_EN (AM335X_CONTROL_MODULE_VADDR + AM335X_PADCTL_MII1_TX_EN_OFFSET)
#define AM335X_PADCTL_MII1_RX_DV (AM335X_CONTROL_MODULE_VADDR + AM335X_PADCTL_MII1_RX_DV_OFFSET)
#define AM335X_PADCTL_MII1_TXD3 (AM335X_CONTROL_MODULE_VADDR + AM335X_PADCTL_MII1_TXD3_OFFSET)
#define AM335X_PADCTL_MII1_TXD2 (AM335X_CONTROL_MODULE_VADDR + AM335X_PADCTL_MII1_TXD2_OFFSET)
#define AM335X_PADCTL_MII1_TXD1 (AM335X_CONTROL_MODULE_VADDR + AM335X_PADCTL_MII1_TXD1_OFFSET)
#define AM335X_PADCTL_MII1_TXD0 (AM335X_CONTROL_MODULE_VADDR + AM335X_PADCTL_MII1_TXD0_OFFSET)
#define AM335X_PADCTL_MII1_TX_CLK (AM335X_CONTROL_MODULE_VADDR + AM335X_PADCTL_MII1_TX_CLK_OFFSET)
#define AM335X_PADCTL_MII1_RX_CLK (AM335X_CONTROL_MODULE_VADDR + AM335X_PADCTL_MII1_RX_CLK_OFFSET)
#define AM335X_PADCTL_MII1_RXD3 (AM335X_CONTROL_MODULE_VADDR + AM335X_PADCTL_MII1_RXD3_OFFSET)
#define AM335X_PADCTL_MII1_RXD2 (AM335X_CONTROL_MODULE_VADDR + AM335X_PADCTL_MII1_RXD2_OFFSET)
#define AM335X_PADCTL_MII1_RXD1 (AM335X_CONTROL_MODULE_VADDR + AM335X_PADCTL_MII1_RXD1_OFFSET)
#define AM335X_PADCTL_MII1_RXD0 (AM335X_CONTROL_MODULE_VADDR + AM335X_PADCTL_MII1_RXD0_OFFSET)
#define AM335X_PADCTL_RMII1_REF_CLK (AM335X_CONTROL_MODULE_VADDR + AM335X_PADCTL_RMII1_REF_CLK_OFFSET)
#define AM335X_PADCTL_MDIO (AM335X_CONTROL_MODULE_VADDR + AM335X_PADCTL_MDIO_OFFSET)
#define AM335X_PADCTL_MDC (AM335X_CONTROL_MODULE_VADDR + AM335X_PADCTL_MDC_OFFSET)
#define AM335X_PADCTL_SPI0_SCLK (AM335X_CONTROL_MODULE_VADDR + AM335X_PADCTL_SPI0_SCLK_OFFSET)
#define AM335X_PADCTL_SPI0_D0 (AM335X_CONTROL_MODULE_VADDR + AM335X_PADCTL_SPI0_D0_OFFSET)
#define AM335X_PADCTL_SPI0_D1 (AM335X_CONTROL_MODULE_VADDR + AM335X_PADCTL_SPI0_D1_OFFSET)
#define AM335X_PADCTL_SPI0_CS0 (AM335X_CONTROL_MODULE_VADDR + AM335X_PADCTL_SPI0_CS0_OFFSET)
#define AM335X_PADCTL_SPI0_CS1 (AM335X_CONTROL_MODULE_VADDR + AM335X_PADCTL_SPI0_CS1_OFFSET)
#define AM335X_PADCTL_ECAP0_IN_PWM0_OUT (AM335X_CONTROL_MODULE_VADDR + AM335X_PADCTL_ECAP0_IN_PWM0_OUT_OFFSET)
#define AM335X_PADCTL_UART0_CTSN (AM335X_CONTROL_MODULE_VADDR + AM335X_PADCTL_UART0_CTSN_OFFSET)
#define AM335X_PADCTL_UART0_RTSN (AM335X_CONTROL_MODULE_VADDR + AM335X_PADCTL_UART0_RTSN_OFFSET)
#define AM335X_PADCTL_UART0_RXD (AM335X_CONTROL_MODULE_VADDR + AM335X_PADCTL_UART0_RXD_OFFSET)
#define AM335X_PADCTL_UART0_TXD (AM335X_CONTROL_MODULE_VADDR + AM335X_PADCTL_UART0_TXD_OFFSET)
#define AM335X_PADCTL_UART1_CTSN (AM335X_CONTROL_MODULE_VADDR + AM335X_PADCTL_UART1_CTSN_OFFSET)
#define AM335X_PADCTL_UART1_RTSN (AM335X_CONTROL_MODULE_VADDR + AM335X_PADCTL_UART1_RTSN_OFFSET)
#define AM335X_PADCTL_UART1_RXD (AM335X_CONTROL_MODULE_VADDR + AM335X_PADCTL_UART1_RXD_OFFSET)
#define AM335X_PADCTL_UART1_TXD (AM335X_CONTROL_MODULE_VADDR + AM335X_PADCTL_UART1_TXD_OFFSET)
#define AM335X_PADCTL_I2C0_SDA (AM335X_CONTROL_MODULE_VADDR + AM335X_PADCTL_I2C0_SDA_OFFSET)
#define AM335X_PADCTL_I2C0_SCL (AM335X_CONTROL_MODULE_VADDR + AM335X_PADCTL_I2C0_SCL_OFFSET)
#define AM335X_PADCTL_MCASP0_ACLKX (AM335X_CONTROL_MODULE_VADDR + AM335X_PADCTL_MCASP0_ACLKX_OFFSET)
#define AM335X_PADCTL_MCASP0_FSX (AM335X_CONTROL_MODULE_VADDR + AM335X_PADCTL_MCASP0_FSX_OFFSET)
#define AM335X_PADCTL_MCASP0_AXR0 (AM335X_CONTROL_MODULE_VADDR + AM335X_PADCTL_MCASP0_AXR0_OFFSET)
#define AM335X_PADCTL_MCASP0_AHCLKR (AM335X_CONTROL_MODULE_VADDR + AM335X_PADCTL_MCASP0_AHCLKR_OFFSET)
#define AM335X_PADCTL_MCASP0_ACLKR (AM335X_CONTROL_MODULE_VADDR + AM335X_PADCTL_MCASP0_ACLKR_OFFSET)
#define AM335X_PADCTL_MCASP0_FSR (AM335X_CONTROL_MODULE_VADDR + AM335X_PADCTL_MCASP0_FSR_OFFSET)
#define AM335X_PADCTL_MCASP0_AXR1 (AM335X_CONTROL_MODULE_VADDR + AM335X_PADCTL_MCASP0_AXR1_OFFSET)
#define AM335X_PADCTL_MCASP0_AhCLKX (AM335X_CONTROL_MODULE_VADDR + AM335X_PADCTL_MCASP0_AhCLKX_OFFSET)
#define AM335X_PADCTL_XDMA_EVENT_INTR0 (AM335X_CONTROL_MODULE_VADDR + AM335X_PADCTL_XDMA_EVENT_INTR0_OFFSET)
#define AM335X_PADCTL_XDMA_EVENT_INTR1 (AM335X_CONTROL_MODULE_VADDR + AM335X_PADCTL_XDMA_EVENT_INTR1_OFFSET)
#define AM335X_PADCTL_WARMRSTN (AM335X_CONTROL_MODULE_VADDR + AM335X_PADCTL_WARMRSTN_OFFSET)
#define AM335X_PADCTL_NNMI (AM335X_CONTROL_MODULE_VADDR + AM335X_PADCTL_NNMI_OFFSET)
#define AM335X_PADCTL_TMS (AM335X_CONTROL_MODULE_VADDR + AM335X_PADCTL_TMS_OFFSET)
#define AM335X_PADCTL_TDI (AM335X_CONTROL_MODULE_VADDR + AM335X_PADCTL_TDI_OFFSET)
#define AM335X_PADCTL_TDO (AM335X_CONTROL_MODULE_VADDR + AM335X_PADCTL_TDO_OFFSET)
#define AM335X_PADCTL_TCK (AM335X_CONTROL_MODULE_VADDR + AM335X_PADCTL_TCK_OFFSET)
#define AM335X_PADCTL_TRSTN (AM335X_CONTROL_MODULE_VADDR + AM335X_PADCTL_TRSTN_OFFSET)
#define AM335X_PADCTL_EMU0 (AM335X_CONTROL_MODULE_VADDR + AM335X_PADCTL_EMU0_OFFSET)
#define AM335X_PADCTL_EMU1 (AM335X_CONTROL_MODULE_VADDR + AM335X_PADCTL_EMU1_OFFSET)
#define AM335X_PADCTL_RTC_PWRONRSTN (AM335X_CONTROL_MODULE_VADDR + AM335X_PADCTL_RTC_PWRONRSTN_OFFSET)
#define AM335X_PADCTL_PMIC_POWER_EN (AM335X_CONTROL_MODULE_VADDR + AM335X_PADCTL_PMIC_POWER_EN_OFFSET)
#define AM335X_PADCTL_EXT_WAKEUP (AM335X_CONTROL_MODULE_VADDR + AM335X_PADCTL_EXT_WAKEUP_OFFSET)
#define AM335X_PADCTL_RTC_KALDO_ENN (AM335X_CONTROL_MODULE_VADDR + AM335X_PADCTL_RTC_KALDO_ENN_OFFSET)
#define AM335X_PADCTL_USB0_DRVVBUS (AM335X_CONTROL_MODULE_VADDR + AM335X_PADCTL_USB0_DRVVBUS_OFFSET)
#define AM335X_PADCTL_USB1_DRVVBUS (AM335X_CONTROL_MODULE_VADDR + AM335X_PADCTL_USB1_DRVVBUS_OFFSET)
/* Control Module Register Bit Definitions **************************************************/
/* PAD Control Fields */
#define PADCTL_MUXMODE_SHIFT (0) /* Bits 0-2: Functional signal mux select */
#define PADCTL_MUXMODE_MASK (7 << PADCTL_MUXMODE_SHIFT)
# define PADCTL_MUXMODE_0 (0 << PADCTL_MUXMODE_SHIFT)
# define PADCTL_MUXMODE_1 (1 << PADCTL_MUXMODE_SHIFT)
# define PADCTL_MUXMODE_2 (2 << PADCTL_MUXMODE_SHIFT)
# define PADCTL_MUXMODE_3 (3 << PADCTL_MUXMODE_SHIFT)
# define PADCTL_MUXMODE_4 (4 << PADCTL_MUXMODE_SHIFT)
# define PADCTL_MUXMODE_5 (5 << PADCTL_MUXMODE_SHIFT)
# define PADCTL_MUXMODE_6 (6 << PADCTL_MUXMODE_SHIFT)
# define PADCTL_MUXMODE_7 (7 << PADCTL_MUXMODE_SHIFT)
# define PADCTL_MUXMODE(n) (((n) << PADCTL_MUXMODE_SHIFT) & PADCTL_MUXMODE_MASK)
#define PADCTL_PULLUDEN (0 << 3) /* Bit 3: Pull up enabled */
#define PADCTL_PULLUDDIS (1 << 3) /* Bit 3: Pull up disabled */
#define PADCTL_PULLDOWN_EN (0 << 4) /* Bit 4: Pull Down Selection */
#define PADCTL_PULLUP_EN (1 << 4) /* Bit 4: Pull Up Selection */
#define PADCTL_RXACTIVE (1 << 5) /* Bit 5: Receiver enabled */
#define PADCTL_SLEWCTRL (1 << 6) /* Bit 6: Select between faster or slower slew rate */
#endif /* __ARCH_ARM_SRC_AM335X_CHIP_AM335X_CONTROL_H */

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arch/arm/src/am335x/chip/am335x_gpio.h Normal file
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/************************************************************************************
* arch/arm/src/am335x/am335x_gpio.h
*
* Copyright (C) 2018 Petro Karashchenko. All rights reserved.
* Author: Petro Karashchenko <petro.karashchenko@gmail.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_AM335X_CHIP_AM335X_GPIO_H
#define __ARCH_ARM_SRC_AM335X_CHIP_AM335X_GPIO_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
#include <chip/am335x_memorymap.h>
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
#define GPIO0 0 /* Port 0 index */
#define GPIO1 1 /* Port 1 index */
#define GPIO2 2 /* Port 2 index */
#define GPIO3 3 /* Port 3 index */
#define AM335X_GPIO_NPORTS 4 /* Seven total ports */
#define AM335X_GPIO_NPINS 32 /* Up to 32 pins per port */
/* GPIO Register Offsets ************************************************************/
#define AM335X_GPIO_REV_OFFSET 0x0000 /* Module Revision Register */
#define AM335X_GPIO_SCR_OFFSET 0x0010 /* System Configuration Register */
#define AM335X_GPIO_EOIR_OFFSET 0x0020 /* End of Event Register */
#define AM335X_GPIO_ISRR0_OFFSET 0x0024 /* Interrupt Status Raw 0 Register */
#define AM335X_GPIO_ISRR1_OFFSET 0x0028 /* Interrupt Status Raw 0 Register */
#define AM335X_GPIO_ISR0_OFFSET 0x002C /* Interrupt Status 0 Register */
#define AM335X_GPIO_ISR1_OFFSET 0x0030 /* Interrupt Status 1 Register */
#define AM335X_GPIO_ISSR0_OFFSET 0x0034 /* Interrupt Status Set 0 Register */
#define AM335X_GPIO_ISSR1_OFFSET 0x0038 /* Interrupt Status Set 1 Register */
#define AM335X_GPIO_ISCR0_OFFSET 0x003C /* Interrupt Status Clear 0 Register */
#define AM335X_GPIO_ISCR1_OFFSET 0x0040 /* Interrupt Status Clear 1 Register */
#define AM335X_GPIO_IWER0_OFFSET 0x0044 /* Interrupt Wake-up Enable 0 Register */
#define AM335X_GPIO_IWER1_OFFSET 0x0048 /* Interrupt Wake-up Enable 1 Register */
#define AM335X_GPIO_SSR_OFFSET 0x0114 /* System Status Register */
#define AM335X_GPIO_CTRL_OFFSET 0x0130 /* Control Register */
#define AM335X_GPIO_OER_OFFSET 0x0134 /* Output Enable Register */
#define AM335X_GPIO_DIR_OFFSET 0x0138 /* Data Input Register */
#define AM335X_GPIO_DOR_OFFSET 0x013C /* Data Output Register */
#define AM335X_GPIO_LDR0_OFFSET 0x0140 /* Level Detect 0 Register */
#define AM335X_GPIO_LDR1_OFFSET 0x0144 /* Level Detect 1 Register */
#define AM335X_GPIO_RDR_OFFSET 0x0148 /* Rising-edge Detection Register */
#define AM335X_GPIO_FDR_OFFSET 0x014C /* Falling-edge Detection Register */
#define AM335X_GPIO_DER_OFFSET 0x0150 /* Debouncing Enable Register */
#define AM335X_GPIO_DTR_OFFSET 0x0154 /* Debouncing Time Register */
#define AM335X_GPIO_CDOR_OFFSET 0x0190 /* Clear Data Output Register */
#define AM335X_GPIO_SDOR_OFFSET 0x0194 /* Set Data Output Register */
/* GPIO Register Addresses **********************************************************/
#define AM335X_GPIO_SCR(v) ((v) + AM335X_GPIO_SCR_OFFSET)
#define AM335X_GPIO_EOIR(v) ((v) + AM335X_GPIO_EOIR_OFFSET)
#define AM335X_GPIO_ISRR0(v) ((v) + AM335X_GPIO_ISRR0_OFFSET)
#define AM335X_GPIO_ISRR1(v) ((v) + AM335X_GPIO_ISRR1_OFFSET)
#define AM335X_GPIO_ISR0(v) ((v) + AM335X_GPIO_ISR0_OFFSET)
#define AM335X_GPIO_ISR1(v) ((v) + AM335X_GPIO_ISR1_OFFSET)
#define AM335X_GPIO_ISSR0(v) ((v) + AM335X_GPIO_ISSR0_OFFSET)
#define AM335X_GPIO_ISSR1(v) ((v) + AM335X_GPIO_ISSR1_OFFSET)
#define AM335X_GPIO_ISCR0(v) ((v) + AM335X_GPIO_ISCR0_OFFSET)
#define AM335X_GPIO_ISCR1(v) ((v) + AM335X_GPIO_ISCR1_OFFSET)
#define AM335X_GPIO_IWER0(v) ((v) + AM335X_GPIO_IWER0_OFFSET)
#define AM335X_GPIO_IWER1(v) ((v) + AM335X_GPIO_IWER1_OFFSET)
#define AM335X_GPIO_SSR(v) ((v) + AM335X_GPIO_SSR_OFFSET)
#define AM335X_GPIO_CTRL(v) ((v) + AM335X_GPIO_CTRL_OFFSET)
#define AM335X_GPIO_OER(v) ((v) + AM335X_GPIO_OER_OFFSET)
#define AM335X_GPIO_DIR(v) ((v) + AM335X_GPIO_DIR_OFFSET)
#define AM335X_GPIO_DOR(v) ((v) + AM335X_GPIO_DOR_OFFSET)
#define AM335X_GPIO_LDR0(v) ((v) + AM335X_GPIO_LDR0_OFFSET)
#define AM335X_GPIO_LDR1(v) ((v) + AM335X_GPIO_LDR1_OFFSET)
#define AM335X_GPIO_RDR(v) ((v) + AM335X_GPIO_RDR_OFFSET)
#define AM335X_GPIO_FDR(v) ((v) + AM335X_GPIO_FDR_OFFSET)
#define AM335X_GPIO_DER(v) ((v) + AM335X_GPIO_DER_OFFSET)
#define AM335X_GPIO_DTR(v) ((v) + AM335X_GPIO_DTR_OFFSET)
#define AM335X_GPIO_CDOR(v) ((v) + AM335X_GPIO_CDOR_OFFSET)
#define AM335X_GPIO_SDOR(v) ((v) + AM335X_GPIO_SDOR_OFFSET)
#define AM335X_GPIO0_SCR (AM335X_GPIO0_VADDR + AM335X_GPIO_SCR_OFFSET)
#define AM335X_GPIO0_EOIR (AM335X_GPIO0_VADDR + AM335X_GPIO_EOIR_OFFSET)
#define AM335X_GPIO0_ISRR0 (AM335X_GPIO0_VADDR + AM335X_GPIO_ISRR0_OFFSET)
#define AM335X_GPIO0_ISRR1 (AM335X_GPIO0_VADDR + AM335X_GPIO_ISRR1_OFFSET)
#define AM335X_GPIO0_ISR0 (AM335X_GPIO0_VADDR + AM335X_GPIO_ISR0_OFFSET)
#define AM335X_GPIO0_ISR1 (AM335X_GPIO0_VADDR + AM335X_GPIO_ISR1_OFFSET)
#define AM335X_GPIO0_ISSR0 (AM335X_GPIO0_VADDR + AM335X_GPIO_ISSR0_OFFSET)
#define AM335X_GPIO0_ISSR1 (AM335X_GPIO0_VADDR + AM335X_GPIO_ISSR1_OFFSET)
#define AM335X_GPIO0_ISCR0 (AM335X_GPIO0_VADDR + AM335X_GPIO_ISCR0_OFFSET)
#define AM335X_GPIO0_ISCR1 (AM335X_GPIO0_VADDR + AM335X_GPIO_ISCR1_OFFSET)
#define AM335X_GPIO0_IWER0 (AM335X_GPIO0_VADDR + AM335X_GPIO_IWER0_OFFSET)
#define AM335X_GPIO0_IWER1 (AM335X_GPIO0_VADDR + AM335X_GPIO_IWER1_OFFSET)
#define AM335X_GPIO0_SSR (AM335X_GPIO0_VADDR + AM335X_GPIO_SSR_OFFSET)
#define AM335X_GPIO0_CTRL (AM335X_GPIO0_VADDR + AM335X_GPIO_CTRL_OFFSET)
#define AM335X_GPIO0_OER (AM335X_GPIO0_VADDR + AM335X_GPIO_OER_OFFSET)
#define AM335X_GPIO0_DIR (AM335X_GPIO0_VADDR + AM335X_GPIO_DIR_OFFSET)
#define AM335X_GPIO0_DOR (AM335X_GPIO0_VADDR + AM335X_GPIO_DOR_OFFSET)
#define AM335X_GPIO0_LDR0 (AM335X_GPIO0_VADDR + AM335X_GPIO_LDR0_OFFSET)
#define AM335X_GPIO0_LDR1 (AM335X_GPIO0_VADDR + AM335X_GPIO_LDR1_OFFSET)
#define AM335X_GPIO0_RDR (AM335X_GPIO0_VADDR + AM335X_GPIO_RDR_OFFSET)
#define AM335X_GPIO0_FDR (AM335X_GPIO0_VADDR + AM335X_GPIO_FDR_OFFSET)
#define AM335X_GPIO0_DER (AM335X_GPIO0_VADDR + AM335X_GPIO_DER_OFFSET)
#define AM335X_GPIO0_DTR (AM335X_GPIO0_VADDR + AM335X_GPIO_DTR_OFFSET)
#define AM335X_GPIO0_CDOR (AM335X_GPIO0_VADDR + AM335X_GPIO_CDOR_OFFSET)
#define AM335X_GPIO0_SDOR (AM335X_GPIO0_VADDR + AM335X_GPIO_SDOR_OFFSET)
#define AM335X_GPIO1_SCR (AM335X_GPIO1_VADDR + AM335X_GPIO_SCR_OFFSET)
#define AM335X_GPIO1_EOIR (AM335X_GPIO1_VADDR + AM335X_GPIO_EOIR_OFFSET)
#define AM335X_GPIO1_ISRR0 (AM335X_GPIO1_VADDR + AM335X_GPIO_ISRR0_OFFSET)
#define AM335X_GPIO1_ISRR1 (AM335X_GPIO1_VADDR + AM335X_GPIO_ISRR1_OFFSET)
#define AM335X_GPIO1_ISR0 (AM335X_GPIO1_VADDR + AM335X_GPIO_ISR0_OFFSET)
#define AM335X_GPIO1_ISR1 (AM335X_GPIO1_VADDR + AM335X_GPIO_ISR1_OFFSET)
#define AM335X_GPIO1_ISSR0 (AM335X_GPIO1_VADDR + AM335X_GPIO_ISSR0_OFFSET)
#define AM335X_GPIO1_ISSR1 (AM335X_GPIO1_VADDR + AM335X_GPIO_ISSR1_OFFSET)
#define AM335X_GPIO1_ISCR0 (AM335X_GPIO1_VADDR + AM335X_GPIO_ISCR0_OFFSET)
#define AM335X_GPIO1_ISCR1 (AM335X_GPIO1_VADDR + AM335X_GPIO_ISCR1_OFFSET)
#define AM335X_GPIO1_IWER0 (AM335X_GPIO1_VADDR + AM335X_GPIO_IWER0_OFFSET)
#define AM335X_GPIO1_IWER1 (AM335X_GPIO1_VADDR + AM335X_GPIO_IWER1_OFFSET)
#define AM335X_GPIO1_SSR (AM335X_GPIO1_VADDR + AM335X_GPIO_SSR_OFFSET)
#define AM335X_GPIO1_CTRL (AM335X_GPIO1_VADDR + AM335X_GPIO_CTRL_OFFSET)
#define AM335X_GPIO1_OER (AM335X_GPIO1_VADDR + AM335X_GPIO_OER_OFFSET)
#define AM335X_GPIO1_DIR (AM335X_GPIO1_VADDR + AM335X_GPIO_DIR_OFFSET)
#define AM335X_GPIO1_DOR (AM335X_GPIO1_VADDR + AM335X_GPIO_DOR_OFFSET)
#define AM335X_GPIO1_LDR0 (AM335X_GPIO1_VADDR + AM335X_GPIO_LDR0_OFFSET)
#define AM335X_GPIO1_LDR1 (AM335X_GPIO1_VADDR + AM335X_GPIO_LDR1_OFFSET)
#define AM335X_GPIO1_RDR (AM335X_GPIO1_VADDR + AM335X_GPIO_RDR_OFFSET)
#define AM335X_GPIO1_FDR (AM335X_GPIO1_VADDR + AM335X_GPIO_FDR_OFFSET)
#define AM335X_GPIO1_DER (AM335X_GPIO1_VADDR + AM335X_GPIO_DER_OFFSET)
#define AM335X_GPIO1_DTR (AM335X_GPIO1_VADDR + AM335X_GPIO_DTR_OFFSET)
#define AM335X_GPIO1_CDOR (AM335X_GPIO1_VADDR + AM335X_GPIO_CDOR_OFFSET)
#define AM335X_GPIO1_SDOR (AM335X_GPIO1_VADDR + AM335X_GPIO_SDOR_OFFSET)
#define AM335X_GPIO2_SCR (AM335X_GPIO2_VADDR + AM335X_GPIO_SCR_OFFSET)
#define AM335X_GPIO2_EOIR (AM335X_GPIO2_VADDR + AM335X_GPIO_EOIR_OFFSET)
#define AM335X_GPIO2_ISRR0 (AM335X_GPIO2_VADDR + AM335X_GPIO_ISRR0_OFFSET)
#define AM335X_GPIO2_ISRR1 (AM335X_GPIO2_VADDR + AM335X_GPIO_ISRR1_OFFSET)
#define AM335X_GPIO2_ISR0 (AM335X_GPIO2_VADDR + AM335X_GPIO_ISR0_OFFSET)
#define AM335X_GPIO2_ISR1 (AM335X_GPIO2_VADDR + AM335X_GPIO_ISR1_OFFSET)
#define AM335X_GPIO2_ISSR0 (AM335X_GPIO2_VADDR + AM335X_GPIO_ISSR0_OFFSET)
#define AM335X_GPIO2_ISSR1 (AM335X_GPIO2_VADDR + AM335X_GPIO_ISSR1_OFFSET)
#define AM335X_GPIO2_ISCR0 (AM335X_GPIO2_VADDR + AM335X_GPIO_ISCR0_OFFSET)
#define AM335X_GPIO2_ISCR1 (AM335X_GPIO2_VADDR + AM335X_GPIO_ISCR1_OFFSET)
#define AM335X_GPIO2_IWER0 (AM335X_GPIO2_VADDR + AM335X_GPIO_IWER0_OFFSET)
#define AM335X_GPIO2_IWER1 (AM335X_GPIO2_VADDR + AM335X_GPIO_IWER1_OFFSET)
#define AM335X_GPIO2_SSR (AM335X_GPIO2_VADDR + AM335X_GPIO_SSR_OFFSET)
#define AM335X_GPIO2_CTRL (AM335X_GPIO2_VADDR + AM335X_GPIO_CTRL_OFFSET)
#define AM335X_GPIO2_OER (AM335X_GPIO2_VADDR + AM335X_GPIO_OER_OFFSET)
#define AM335X_GPIO2_DIR (AM335X_GPIO2_VADDR + AM335X_GPIO_DIR_OFFSET)
#define AM335X_GPIO2_DOR (AM335X_GPIO2_VADDR + AM335X_GPIO_DOR_OFFSET)
#define AM335X_GPIO2_LDR0 (AM335X_GPIO2_VADDR + AM335X_GPIO_LDR0_OFFSET)
#define AM335X_GPIO2_LDR1 (AM335X_GPIO2_VADDR + AM335X_GPIO_LDR1_OFFSET)
#define AM335X_GPIO2_RDR (AM335X_GPIO2_VADDR + AM335X_GPIO_RDR_OFFSET)
#define AM335X_GPIO2_FDR (AM335X_GPIO2_VADDR + AM335X_GPIO_FDR_OFFSET)
#define AM335X_GPIO2_DER (AM335X_GPIO2_VADDR + AM335X_GPIO_DER_OFFSET)
#define AM335X_GPIO2_DTR (AM335X_GPIO2_VADDR + AM335X_GPIO_DTR_OFFSET)
#define AM335X_GPIO2_CDOR (AM335X_GPIO2_VADDR + AM335X_GPIO_CDOR_OFFSET)
#define AM335X_GPIO2_SDOR (AM335X_GPIO2_VADDR + AM335X_GPIO_SDOR_OFFSET)
#define AM335X_GPIO3_SCR (AM335X_GPIO3_VADDR + AM335X_GPIO_SCR_OFFSET)
#define AM335X_GPIO3_EOIR (AM335X_GPIO3_VADDR + AM335X_GPIO_EOIR_OFFSET)
#define AM335X_GPIO3_ISRR0 (AM335X_GPIO3_VADDR + AM335X_GPIO_ISRR0_OFFSET)
#define AM335X_GPIO3_ISRR1 (AM335X_GPIO3_VADDR + AM335X_GPIO_ISRR1_OFFSET)
#define AM335X_GPIO3_ISR0 (AM335X_GPIO3_VADDR + AM335X_GPIO_ISR0_OFFSET)
#define AM335X_GPIO3_ISR1 (AM335X_GPIO3_VADDR + AM335X_GPIO_ISR1_OFFSET)
#define AM335X_GPIO3_ISSR0 (AM335X_GPIO3_VADDR + AM335X_GPIO_ISSR0_OFFSET)
#define AM335X_GPIO3_ISSR1 (AM335X_GPIO3_VADDR + AM335X_GPIO_ISSR1_OFFSET)
#define AM335X_GPIO3_ISCR0 (AM335X_GPIO3_VADDR + AM335X_GPIO_ISCR0_OFFSET)
#define AM335X_GPIO3_ISCR1 (AM335X_GPIO3_VADDR + AM335X_GPIO_ISCR1_OFFSET)
#define AM335X_GPIO3_IWER0 (AM335X_GPIO3_VADDR + AM335X_GPIO_IWER0_OFFSET)
#define AM335X_GPIO3_IWER1 (AM335X_GPIO3_VADDR + AM335X_GPIO_IWER1_OFFSET)
#define AM335X_GPIO3_SSR (AM335X_GPIO3_VADDR + AM335X_GPIO_SSR_OFFSET)
#define AM335X_GPIO3_CTRL (AM335X_GPIO3_VADDR + AM335X_GPIO_CTRL_OFFSET)
#define AM335X_GPIO3_OER (AM335X_GPIO3_VADDR + AM335X_GPIO_OER_OFFSET)
#define AM335X_GPIO3_DIR (AM335X_GPIO3_VADDR + AM335X_GPIO_DIR_OFFSET)
#define AM335X_GPIO3_DOR (AM335X_GPIO3_VADDR + AM335X_GPIO_DOR_OFFSET)
#define AM335X_GPIO3_LDR0 (AM335X_GPIO3_VADDR + AM335X_GPIO_LDR0_OFFSET)
#define AM335X_GPIO3_LDR1 (AM335X_GPIO3_VADDR + AM335X_GPIO_LDR1_OFFSET)
#define AM335X_GPIO3_RDR (AM335X_GPIO3_VADDR + AM335X_GPIO_RDR_OFFSET)
#define AM335X_GPIO3_FDR (AM335X_GPIO3_VADDR + AM335X_GPIO_FDR_OFFSET)
#define AM335X_GPIO3_DER (AM335X_GPIO3_VADDR + AM335X_GPIO_DER_OFFSET)
#define AM335X_GPIO3_DTR (AM335X_GPIO3_VADDR + AM335X_GPIO_DTR_OFFSET)
#define AM335X_GPIO3_CDOR (AM335X_GPIO3_VADDR + AM335X_GPIO_CDOR_OFFSET)
#define AM335X_GPIO3_SDOR (AM335X_GPIO3_VADDR + AM335X_GPIO_SDOR_OFFSET)
/* GPIO Register Bit Definitions ****************************************************/
/* Most registers are laid out simply with one bit per pin */
#define GPIO_PIN(n) (1 << ((n) & 0x1f)) /* Bit n: Pin n, n=0-31 */
/* GPIO interrupt configuration register 1/2 */
#define GPIO_RDR_REN(n) (1 << ((n) & 0x1f)) /* Interrupt is rising-edge sensitive */
#define GPIO_FDR_FEN(n) (1 << ((n) & 0x1f))
#define GPIO_LDR0_HEN(n) (1 << ((n) & 0x1f))
#define GPIO_LDR1_LEN(n) (1 << ((n) & 0x1f))
#define GPIO_ICR_INDEX(n) (((n) >> 4) & 1)
#define GPIO_ICR_OFFSET(n) (GPIO_ICR1_OFFSET + (GPIO_ICR_INDEX(n) << 2))
#define GPIO_ICR_LOWLEVEL 0 /* Interrupt is low-level sensitive */
#define GPIO_ICR_HIGHLEVEL 1 /* Interrupt is high-level sensitive */
#define GPIO_ICR_RISINGEDGE 2 /* Interrupt is rising-edge sensitive */
#define GPIO_ICR_FALLINGEDGE 3 /* Interrupt is falling-edge sensitive */
#define GPIO_ICR_SHIFT(n) (((n) & 15) << 1)
#define GPIO_ICR_MASK(n) (3 << GPIO_ICR_SHIFT(n))
#define GPIO_ICR(i,n) ((uint32_t)(n) << GPIO_ICR_SHIFT(n))
#endif /* __ARCH_ARM_SRC_AM335X_CHIP_AM335X_GPIO_H */

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/************************************************************************************
* arch/arm/src/am335x/chip/am335x_intc.h
*
* Copyright (C) 2018 Petro Karashchenko. All rights reserved.
* Author: Petro Karashchenko <petro.karashchenko@gmail.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_AM335X_CHIP_AM335X_INTC_H
#define __ARCH_ARM_SRC_AM335X_CHIP_AM335X_INTC_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
#include "chip/am335x_memorymap.h"
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* Register offsets *****************************************************************/
#define AM335X_INTC_REVISION_OFFSET 0x0000 /* IP revision code */
#define AM335X_INTC_SYSCONFIG_OFFSET 0x0010 /* Various parameters of the OCP interface */
#define AM335X_INTC_SYSSTATUS_OFFSET 0x0014 /* Status information about the module */
#define AM335X_INTC_SIR_IRQ_OFFSET 0x0040 /* Currently active IRQ interrupt number */
#define AM335X_INTC_SIR_FIQ_OFFSET 0x0044 /* Currently active FIQ interrupt number */
#define AM335X_INTC_CONTROL_OFFSET 0x0048 /* New interrupt agreement bits */
#define AM335X_INTC_PROTECTION_OFFSET 0x004C /* Controls protection of the other registers */
#define AM335X_INTC_IDLE_OFFSET 0x0050 /* Controls the clock auto-idle for the functional clock and the input synchronizers */
#define AM335X_INTC_IRQ_PRIO_OFFSET 0x0060 /* Currently active IRQ priority level */
#define AM335X_INTC_FIQ_PRIO_OFFSET 0x0064 /* Currently active FIQ priority level */
#define AM335X_INTC_THRESHOLD_OFFSET 0x0068 /* Sets the priority threshold */
#define AM335X_INTC_ITR_OFFSET(n) (0x0080 + (((n) >> 5) * 0x20))
#define AM335X_INTC_ITR0_OFFSET 0x0080 /* Raw interrupt input status 0 before masking */
#define AM335X_INTC_ITR1_OFFSET 0x00A0 /* Raw interrupt input status 1 before masking */
#define AM335X_INTC_ITR2_OFFSET 0x00C0 /* Raw interrupt input status 2 before masking */
#define AM335X_INTC_ITR3_OFFSET 0x00E0 /* Raw interrupt input status 3 before masking */
#define AM335X_INTC_MIR_OFFSET(n) (0x0084 + (((n) >> 5) * 0x20))
#define AM335X_INTC_MIR0_OFFSET 0x0084 /* Interrupt mask 0 */
#define AM335X_INTC_MIR1_OFFSET 0x00A4 /* Interrupt mask 1 */
#define AM335X_INTC_MIR2_OFFSET 0x00C4 /* Interrupt mask 2 */
#define AM335X_INTC_MIR3_OFFSET 0x00E4 /* Interrupt mask 3 */
#define AM335X_INTC_MIR_CLEAR_OFFSET(n) (0x0088 + (((n) >> 5) * 0x20))
#define AM335X_INTC_MIR_CLEAR0_OFFSET 0x0088 /* Clear the interrupt mask 0 bits */
#define AM335X_INTC_MIR_CLEAR1_OFFSET 0x00A8 /* Clear the interrupt mask 1 bits */
#define AM335X_INTC_MIR_CLEAR2_OFFSET 0x00C8 /* Clear the interrupt mask 2 bits */
#define AM335X_INTC_MIR_CLEAR3_OFFSET 0x00E8 /* Clear the interrupt mask 3 bits */
#define AM335X_INTC_MIR_SET_OFFSET(n) (0x008C + (((n) >> 5) * 0x20))
#define AM335X_INTC_MIR_SET0_OFFSET 0x008C /* Set the interrupt mask 0 bits */
#define AM335X_INTC_MIR_SET1_OFFSET 0x00AC /* Set the interrupt mask 1 bits */
#define AM335X_INTC_MIR_SET2_OFFSET 0x00CC /* Set the interrupt mask 2 bits */
#define AM335X_INTC_MIR_SET3_OFFSET 0x00EC /* Set the interrupt mask 3 bits */
#define AM335X_INTC_ISR_SET_OFFSET(n) (0x0090 + (((n) >> 5) * 0x20))
#define AM335X_INTC_ISR_SET0_OFFSET 0x0090 /* Set/read the software interrupt 0 bits */
#define AM335X_INTC_ISR_SET1_OFFSET 0x00B0 /* Set/read the software interrupt 1 bits */
#define AM335X_INTC_ISR_SET2_OFFSET 0x00D0 /* Set/read the software interrupt 2 bits */
#define AM335X_INTC_ISR_SET3_OFFSET 0x00F0 /* Set/read the software interrupt 3 bits */
#define AM335X_INTC_ISR_CLEAR_OFFSET(n) (0x0094 + (((n) >> 5) * 0x20))
#define AM335X_INTC_ISR_CLEAR0_OFFSET 0x0094 /* Clear the software interrupt 0 bits */
#define AM335X_INTC_ISR_CLEAR1_OFFSET 0x00B4 /* Clear the software interrupt 1 bits */
#define AM335X_INTC_ISR_CLEAR2_OFFSET 0x00D4 /* Clear the software interrupt 2 bits */
#define AM335X_INTC_ISR_CLEAR3_OFFSET 0x00F4 /* Clear the software interrupt 3 bits */
#define AM335X_INTC_PEND_IRQ_OFFSET(n) (0x0098 + (((n) >> 5) * 0x20))
#define AM335X_INTC_PEND_IRQ0_OFFSET 0x0098 /* IRQ status 0 after masking */
#define AM335X_INTC_PEND_IRQ1_OFFSET 0x00B8 /* IRQ status 1 after masking */
#define AM335X_INTC_PEND_IRQ2_OFFSET 0x00D8 /* IRQ status 2 after masking */
#define AM335X_INTC_PEND_IRQ3_OFFSET 0x00F8 /* IRQ status 3 after masking */
#define AM335X_INTC_PEND_FIQ_OFFSET(n) (0x009C + (((n) >> 5) * 0x20))
#define AM335X_INTC_PEND_FIQ0_OFFSET 0x009C /* FIQ status 0 after masking */
#define AM335X_INTC_PEND_FIQ1_OFFSET 0x00BC /* FIQ status 1 after masking */
#define AM335X_INTC_PEND_FIQ2_OFFSET 0x00DC /* FIQ status 2 after masking */
#define AM335X_INTC_PEND_FIQ3_OFFSET 0x00FC /* FIQ status 3 after masking */
#define AM335X_INTC_ILR_OFFSET(n) (0x0100 + ((n) * 0x04)) /* Priority for the interrupts and the FIQ/IRQ steering */
/* Register virtual addresses *******************************************************/
#define AM335X_INTC_REVISION (AM335X_INTC_VADDR + AM335X_INTC_REVISION_OFFSET)
#define AM335X_INTC_SYSCONFIG (AM335X_INTC_VADDR + AM335X_INTC_SYSCONFIG_OFFSET)
#define AM335X_INTC_SYSSTATUS (AM335X_INTC_VADDR + AM335X_INTC_SYSSTATUS_OFFSET)
#define AM335X_INTC_SIR_IRQ (AM335X_INTC_VADDR + AM335X_INTC_SIR_IRQ_OFFSET)
#define AM335X_INTC_SIR_FIQ (AM335X_INTC_VADDR + AM335X_INTC_SIR_FIQ_OFFSET)
#define AM335X_INTC_CONTROL (AM335X_INTC_VADDR + AM335X_INTC_CONTROL_OFFSET)
#define AM335X_INTC_PROTECTION (AM335X_INTC_VADDR + AM335X_INTC_PROTECTION_OFFSET)
#define AM335X_INTC_IDLE (AM335X_INTC_VADDR + AM335X_INTC_IDLE_OFFSET)
#define AM335X_INTC_IRQ_PRIO (AM335X_INTC_VADDR + AM335X_INTC_IRQ_PRIO_OFFSET)
#define AM335X_INTC_FIQ_PRIO (AM335X_INTC_VADDR + AM335X_INTC_FIQ_PRIO_OFFSET)
#define AM335X_INTC_THRESHOLD (AM335X_INTC_VADDR + AM335X_INTC_THRESHOLD_OFFSET)
#define AM335X_INTC_ITR(n) (AM335X_INTC_VADDR + AM335X_INTC_ITR_OFFSET(n))
#define AM335X_INTC_ITR0 (AM335X_INTC_VADDR + AM335X_INTC_ITR0_OFFSET)
#define AM335X_INTC_ITR1 (AM335X_INTC_VADDR + AM335X_INTC_ITR1_OFFSET)
#define AM335X_INTC_ITR2 (AM335X_INTC_VADDR + AM335X_INTC_ITR2_OFFSET)
#define AM335X_INTC_ITR3 (AM335X_INTC_VADDR + AM335X_INTC_ITR3_OFFSET)
#define AM335X_INTC_MIR(n) (AM335X_INTC_VADDR + AM335X_INTC_MIR_OFFSET(n))
#define AM335X_INTC_MIR0 (AM335X_INTC_VADDR + AM335X_INTC_MIR0_OFFSET)
#define AM335X_INTC_MIR1 (AM335X_INTC_VADDR + AM335X_INTC_MIR1_OFFSET)
#define AM335X_INTC_MIR2 (AM335X_INTC_VADDR + AM335X_INTC_MIR2_OFFSET)
#define AM335X_INTC_MIR3 (AM335X_INTC_VADDR + AM335X_INTC_MIR3_OFFSET)
#define AM335X_INTC_MIR_CLEAR(n) (AM335X_INTC_VADDR + AM335X_INTC_MIR_CLEAR_OFFSET(n))
#define AM335X_INTC_MIR_CLEAR0 (AM335X_INTC_VADDR + AM335X_INTC_MIR_CLEAR0_OFFSET)
#define AM335X_INTC_MIR_CLEAR1 (AM335X_INTC_VADDR + AM335X_INTC_MIR_CLEAR1_OFFSET)
#define AM335X_INTC_MIR_CLEAR2 (AM335X_INTC_VADDR + AM335X_INTC_MIR_CLEAR2_OFFSET)
#define AM335X_INTC_MIR_CLEAR3 (AM335X_INTC_VADDR + AM335X_INTC_MIR_CLEAR3_OFFSET)
#define AM335X_INTC_MIR_SET(n) (AM335X_INTC_VADDR + AM335X_INTC_MIR_SET_OFFSET(n))
#define AM335X_INTC_MIR_SET0 (AM335X_INTC_VADDR + AM335X_INTC_MIR_SET0_OFFSET)
#define AM335X_INTC_MIR_SET1 (AM335X_INTC_VADDR + AM335X_INTC_MIR_SET1_OFFSET)
#define AM335X_INTC_MIR_SET2 (AM335X_INTC_VADDR + AM335X_INTC_MIR_SET2_OFFSET)
#define AM335X_INTC_MIR_SET3 (AM335X_INTC_VADDR + AM335X_INTC_MIR_SET3_OFFSET)
#define AM335X_INTC_ISR_SET(n) (AM335X_INTC_VADDR + AM335X_INTC_ISR_SET_OFFSET(n))
#define AM335X_INTC_ISR_SET0 (AM335X_INTC_VADDR + AM335X_INTC_ISR_SET0_OFFSET)
#define AM335X_INTC_ISR_SET1 (AM335X_INTC_VADDR + AM335X_INTC_ISR_SET1_OFFSET)
#define AM335X_INTC_ISR_SET2 (AM335X_INTC_VADDR + AM335X_INTC_ISR_SET2_OFFSET)
#define AM335X_INTC_ISR_SET3 (AM335X_INTC_VADDR + AM335X_INTC_ISR_SET3_OFFSET)
#define AM335X_INTC_ISR_CLEAR(n) (AM335X_INTC_VADDR + AM335X_INTC_ISR_CLEAR_OFFSET(n))
#define AM335X_INTC_ISR_CLEAR0 (AM335X_INTC_VADDR + AM335X_INTC_ISR_CLEAR0_OFFSET)
#define AM335X_INTC_ISR_CLEAR1 (AM335X_INTC_VADDR + AM335X_INTC_ISR_CLEAR1_OFFSET)
#define AM335X_INTC_ISR_CLEAR2 (AM335X_INTC_VADDR + AM335X_INTC_ISR_CLEAR2_OFFSET)
#define AM335X_INTC_ISR_CLEAR3 (AM335X_INTC_VADDR + AM335X_INTC_ISR_CLEAR3_OFFSET)
#define AM335X_INTC_PEND_IRQ(n) (AM335X_INTC_VADDR + AM335X_INTC_PEND_IRQ_OFFSET(n))
#define AM335X_INTC_PEND_IRQ0 (AM335X_INTC_VADDR + AM335X_INTC_PEND_IRQ0_OFFSET)
#define AM335X_INTC_PEND_IRQ1 (AM335X_INTC_VADDR + AM335X_INTC_PEND_IRQ1_OFFSET)
#define AM335X_INTC_PEND_IRQ2 (AM335X_INTC_VADDR + AM335X_INTC_PEND_IRQ2_OFFSET)
#define AM335X_INTC_PEND_IRQ3 (AM335X_INTC_VADDR + AM335X_INTC_PEND_IRQ3_OFFSET)
#define AM335X_INTC_PEND_FIQ(n) (AM335X_INTC_VADDR + AM335X_INTC_PEND_FIQ_OFFSET(n))
#define AM335X_INTC_PEND_FIQ0 (AM335X_INTC_VADDR + AM335X_INTC_PEND_FIQ0_OFFSET)
#define AM335X_INTC_PEND_FIQ1 (AM335X_INTC_VADDR + AM335X_INTC_PEND_FIQ1_OFFSET)
#define AM335X_INTC_PEND_FIQ2 (AM335X_INTC_VADDR + AM335X_INTC_PEND_FIQ2_OFFSET)
#define AM335X_INTC_PEND_FIQ3 (AM335X_INTC_VADDR + AM335X_INTC_PEND_FIQ3_OFFSET)
#define AM335X_INTC_ILR(n) (AM335X_INTC_VADDR + AM335X_INTC_ILR_OFFSET(n))
/* Register bit field definitions ***************************************************/
/* System Configuration */
#define INTC_SYSCONFIG_AUTOIDLE (1 << 0) /* Bit 0: Internal OCP clock gating strategy */
#define INTC_SYSCONFIG_SOFTRESET (1 << 1) /* Bit 1: Software reset */
/* System Status */
#define INTC_SYSSTATUS_RESETDONE (1 << 0) /* Bit 0: Internal reset monitoring */
/* System Interrupt IRQ */
#define INTC_SIR_IRQ_ACTIVE_MASK (0x0000007f) /* Bits 0..6: Active IRQ number */
#define INTC_SIR_IRQ_SPURIOUS_MASK (0xffffff80) /* Bits 7..31: Spurious IRQ flag */
/* System Interrupt FIQ */
#define INTC_SIR_FIQ_ACTIVE_MASK (0x0000007f) /* Bits 0..6: Active FIQ number */
#define INTC_SIR_FIQ_SPURIOUS_MASK (0xffffff80) /* Bits 7..31: Spurious FIQ flag */
/* Interrupt Control */
#define INTC_CONTROL_NEWIRQAGR (1 << 0) /* Bit 0: New IRQ generation */
#define INTC_CONTROL_NEWFIQAGR (1 << 1) /* Bit 1: Reset FIQ output and enable new FIQ generation */
/* Interrupt Protection */
#define INTC_PROTECTION_ENABLE (1 << 0) /* Bit 0: Enabled protected register access */
/* Interrupt Idle */
#define INTC_IDLE_FUNCIDLE (1 << 0) /* Bit 0: Functional clock auto-idle mode */
#define INTC_IDLE_TURBO (1 << 1) /* Bit 1: Input synchronizer clock auto-gating */
/* Interrupt IRQ Priority */
#define INTC_IRQ_PRIO_IRQ (0x0000003f) /* Bits 0..6: Current IRQ priority */
#define INTC_IRQ_PRIO_SPURIOUS_FLAG (0xffffffc0) /* Bits 7..31: Spurious IRQ flag */
/* Interrupt FIQ Priority */
#define INTC_FIQ_PRIORITY_FIQ (0x0000003f) /* Bits 0..6: Current FIQ priority */
#define INTC_FIQ_PRIO_SPURIOUS_FLAG (0xffffffc0) /* Bits 7..31: Spurious FIQ flag */
/* Interrupt Priority Threshold */
#define INTC_THRESHOLD_MASK (0x0000003f) /* Bits 0..6: Priority threshold */
#define INTC_THRESHOLD_DISABLE (0x000000ff) /* Value FFh disables the threshold */
/* Interrupt Input 0-3 Status Before Masking */
#define INTC_ITR(n) (1 << ((n) & 0x1f)) /* n=0-127: Interrupt status */
/* Interrupt Mask 0-3 */
#define INTC_MIR(n) (1 << ((n) & 0x1f)) /* n=0-127: Interrupt mask */
/* Clear Interrupt Mask 0-3 */
#define INTC_MIR_CLEAR(n) (1 << ((n) & 0x1f)) /* n=0-127: Interrupt clear mask */
/* Set Interrupt Mask 0-3 */
#define INTC_MIR_SET(n) (1 << ((n) & 0x1f)) /* n=0-127: Interrupt set mask */
/* Set Software Interrupt 0-3 / Currently Active Software Interrupts */
#define INTC_ISR_SET(n) (1 << ((n) & 0x1f)) /* n=0-127: Set software interrupt */
/* Clear Software Interrupt 0-3 */
#define INTC_ISR_CLEAR(n) (1 << ((n) & 0x1f)) /* n=0-127: Clear software Interrupt */
/* IRQ Status After Masking 0-3 */
#define INTC_PEND_IRQ(n) (1 << ((n) & 0x1f)) /* n=0-127: Interrupt pending */
/* FIQ Status After Masking 0-3 */
#define INTC_PEND_FIQ(n) (1 << ((n) & 0x1f)) /* n=0-127: Interrupt pending */
/* Priority for the Interrupt 0-127 and the FIQ/IRQ Steering */
#define INTC_PRIO_MIN 0
#define INTC_PRIO_MAX 127
#define INTC_ILR_MAP_IRQ (0 << 0) /* Bit 0: Interrupt is routed to IRQ */
#define INTC_ILR_MAP_FIQ (1 << 0) /* Bit 0: Interrupt is routed to FIQ */
#define INTC_ILR_PRIO_SHIFT (2)
#define INTC_ILR_PRIO_MASK (127) /* Bits 2..7: Interrupt Priority */
# define INTC_ILR_PRIO(p) (((p) & INTC_ILR_PRIO_MASK) << INTC_ILR_PRIO_SHIFT)
#endif /* __ARCH_ARM_SRC_AM335X_CHIP_AM335X_INTC_H */

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/************************************************************************************
* arch/arm/src/am335x/chip/am335x_memorymap.h
*
* Copyright (C) 2018 Petro Karashchenko. All rights reserved.
* Author: Petro Karashchenko <petro.karashchenko@gmail.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_AM335X_CHIP_AM335X_MEMORYMAP_H
#define __ARCH_ARM_SRC_AM335X_CHIP_AM335X_MEMORYMAP_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
#include <arch/am335x/chip.h>
#if defined(CONFIG_ARCH_CHIP_AM3358)
# include "chip/am3358_memorymap.h"
#else
# error Unrecognized AM335X architecture
#endif
#endif /* __ARCH_ARM_SRC_AM335X_CHIP_AM335X_MEMORYMAP_H */

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/************************************************************************************
* arch/arm/src/am335x/chip/am335x_pinmux.h
*
* Copyright (C) 2018 Petro Karashchenko. All rights reserved.
* Author: Petro Karashchenko <petro.karashchenko@gmail.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_AM335X_CHIP_AM335X_PINMUX_H
#define __ARCH_ARM_SRC_AM335X_CHIP_AM335X_PINMUX_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
#include <arch/am335x/chip.h>
#if defined(CONFIG_ARCH_CHIP_AM3358)
# include "chip/am3358_pinmux.h"
#else
# error Unrecognized AM335X architecture
#endif
#endif /* __ARCH_ARM_SRC_AM335X_CHIP_AM335X_PINMUX_H */

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/************************************************************************************
* arch/arm/src/am335x/chip/am335x_timer.h
*
* Copyright (C) 2018 Petro Karashchenko. All rights reserved.
* Author: Petro Karashchenko <petro.karashchenko@gmail.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_AM335X_CHIP_AM335X_TIMER_H
#define __ARCH_ARM_SRC_AM335X_CHIP_AM335X_TIMER_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
#include "chip/am335x_memorymap.h"
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* Register offsets *****************************************************************/
#define AM335X_TMR_TIDR_OFFSET 0x0000 /* Identification Register */
#define AM335X_TMR_TIOCP_CFG_OFFSET 0x0010 /* Timer OCP Configuration Register */
#define AM335X_TMR_IRQ_EOI_OFFSET 0x0020 /* Timer IRQ End-of-Interrupt Register */
#define AM335X_TMR_IRQ_STAT_RAW_OFFSET 0x0024 /* Timer IRQ Status Raw Register */
#define AM335X_TMR_IRQ_STAT_OFFSET 0x0028 /* Timer IRQ Status Register */
#define AM335X_TMR_IRQ_EN_SET_OFFSET 0x002C /* Timer IRQ Enable Set Register */
#define AM335X_TMR_IRQ_EN_CLR_OFFSET 0x0030 /* Timer IRQ Enable Clear Register */
#define AM335X_TMR_IRQ_WAKE_EN_OFFSET 0x0034 /* Timer IRQ Wakeup Enable Register */
#define AM335X_TMR_TCLR_OFFSET 0x0038 /* Timer Control Register */
#define AM335X_TMR_TCRR_OFFSET 0x003C /* Timer Counter Register */
#define AM335X_TMR_TLDR_OFFSET 0x0040 /* Timer Load Register */
#define AM335X_TMR_TTGR_OFFSET 0x0044 /* Timer Trigger Register */
#define AM335X_TMR_TWPS_OFFSET 0x0048 /* Timer Write Posting Bits Register */
#define AM335X_TMR_TMAR_OFFSET 0x004C /* Timer Match Register */
#define AM335X_TMR_TCAR1_OFFSET 0x0050 /* Timer Capture Register */
#define AM335X_TMR_TSICR_OFFSET 0x0054 /* Timer Synchronous Interface Control Register */
#define AM335X_TMR_TCAR2_OFFSET 0x0058 /* Timer Capture Register */
#define AM335X_TMR1MS_TIDR_OFFSET 0x0000 /* Identification Register Section */
#define AM335X_TMR1MS_TIOCP_CFG_OFFSET 0x0010 /* 1ms Timer OCP Configuration Register Section */
#define AM335X_TMR1MS_TISTAT_OFFSET 0x0014 /* 1ms Timer Status Information Register */
#define AM335X_TMR1MS_TISR_OFFSET 0x0018 /* 1ms Timer IRQ Status Register */
#define AM335X_TMR1MS_TIER_OFFSET 0x001C /* 1ms Timer IRQ Enable Register */
#define AM335X_TMR1MS_TWER_OFFSET 0x0020 /* 1ms Timer IRQ Wakeup Enable Register */
#define AM335X_TMR1MS_TCLR_OFFSET 0x0024 /* 1ms Timer Control Register */
#define AM335X_TMR1MS_TCRR_OFFSET 0x0028 /* 1ms Timer Counter Register */
#define AM335X_TMR1MS_TLDR_OFFSET 0x002C /* 1ms Timer Load Register */
#define AM335X_TMR1MS_TTGR_OFFSET 0x0030 /* 1ms Timer Trigger Register */
#define AM335X_TMR1MS_TWPS_OFFSET 0x0034 /* 1ms Timer Write Posting Bits Register */
#define AM335X_TMR1MS_TMAR_OFFSET 0x0038 /* 1ms Timer Match Register */
#define AM335X_TMR1MS_TCAR1_OFFSET 0x003C /* 1ms Timer Capture Register */
#define AM335X_TMR1MS_TSICR_OFFSET 0x0040 /* 1ms Timer Synchronous Interface Control Register */
#define AM335X_TMR1MS_TCAR2_OFFSET 0x0044 /* 1ms Timer Capture Register */
#define AM335X_TMR1MS_TPIR_OFFSET 0x0048 /* 1ms Timer Positive Increment Register */
#define AM335X_TMR1MS_TNIR_OFFSET 0x004C /* 1ms Timer Negative Increment Register */
#define AM335X_TMR1MS_TCVR_OFFSET 0x0050 /* 1ms Timer Counter Value Register */
#define AM335X_TMR1MS_TOCR_OFFSET 0x0054 /* 1ms Timer Overflow Counter Register */
#define AM335X_TMR1MS_TOWR_OFFSET 0x0058 /* 1ms Timer Overflow Interrupts Register */
/* Register virtual addresses *******************************************************/
#define AM335X_TMR1MS_TISR (AM335X_DMTIMER1_1MS_VADDR + AM335X_TMR1MS_TISR_OFFSET)
#define AM335X_TMR1MS_TIER (AM335X_DMTIMER1_1MS_VADDR + AM335X_TMR1MS_TIER_OFFSET)
#define AM335X_TMR1MS_TCLR (AM335X_DMTIMER1_1MS_VADDR + AM335X_TMR1MS_TCLR_OFFSET)
#define AM335X_TMR1MS_TCRR (AM335X_DMTIMER1_1MS_VADDR + AM335X_TMR1MS_TCRR_OFFSET)
#define AM335X_TMR1MS_TLDR (AM335X_DMTIMER1_1MS_VADDR + AM335X_TMR1MS_TLDR_OFFSET)
#define AM335X_TMR1MS_TPIR (AM335X_DMTIMER1_1MS_VADDR + AM335X_TMR1MS_TPIR_OFFSET)
#define AM335X_TMR1MS_TNIR (AM335X_DMTIMER1_1MS_VADDR + AM335X_TMR1MS_TNIR_OFFSET)
/* Register bit field definitions ***************************************************/
#define TMR_TIOCP_SOFT_RESET (1 << 0) /* Bit 0: Software reset */
#define TMR_TIOCP_EMU_FREE (1 << 1) /* Bit 1: Sensitivity to emulation (debug) suspend event from Debug Subsystem. */
#define TMR_TIOCP_IDLE_MODE_SHIFT (2) /* Bits 2-3: Power management, req/ack control */
#define TMR_TIOCP_IDLE_MODE_MASK (3 << TMR_TIOCP_IDLE_MODE_SHIFT)
# define TMR_TIOCP_IDLE_MODE_FORCE (0 << TMR_TIOCP_IDLE_MODE_SHIFT) /* Force-idle mode */
# define TMR_TIOCP_IDLE_MODE_NOIDLE (1 << TMR_TIOCP_IDLE_MODE_SHIFT) /* No-idle mode */
# define TMR_TIOCP_IDLE_MODE_SMART (2 << TMR_TIOCP_IDLE_MODE_SHIFT) /* Smart-idle mode */
# define TMR_TIOCP_IDLE_MODE_WAKEUP (3 << TMR_TIOCP_IDLE_MODE_SHIFT) /* Smart-idle wakeup-capable mode */
#define TMR_IRQ_EOI_DMA_ACK (1 << 0) /* Bit 0: DMA event acknowledge bit */
#define TMR_IRQ_FlAG_MAT (1 << 0) /* Bit 0: IRQ flag for Match */
#define TMR_IRQ_FLAG_OVF (1 << 1) /* Bit 1: IRQ flag for Overflow */
#define TMR_IRQ_FLAG_TCAR (1 << 2) /* Bit 2: IRQ flag for Capture */
#define TMR_TCLR_ST (1 << 0) /* Bit 0: Start/stop timer */
#define TMR_TCLR_AR (1 << 1) /* Bit 1: Auto-reload */
#define TMR_TCLR_PTV_SHIFT (2) /* Bits 2-4: Pre-scale clock Timer value */
#define TMR_TCLR_PTV_MASK (7 << TMR_TCLR_PTV_SHIFT)
#define TMR_TCLR_PRE (1 << 5) /* Bit 5: Prescaler enable */
#define TMR_TCLR_CE (1 << 6) /* Bit 6: Compare mode */
#define TMR_TCLR_SCPWM (1 << 7) /* Bit 7: Set/clear PORTIMERPWM output pin */
#define TMR_TCLR_TCM_SHIFT (8) /* Bits 8-9: Transition Capture Mode */
#define TMR_TCLR_TCM_MASK (3 << TMR_TCLR_TCM_SHIFT)
# define TMR_TCLR_TCM_NONE (0 << TMR_TCLR_TCM_SHIFT) /* No capture */
# define TMR_TCLR_TCM_RISING (1 << TMR_TCLR_TCM_SHIFT) /* Capture on rising edges */
# define TMR_TCLR_TCM_FALLING (2 << TMR_TCLR_TCM_SHIFT) /* Capture on falling edges */
# define TMR_TCLR_TCM_BOTH (3 << TMR_TCLR_TCM_SHIFT) /* Capture on both edges */
#define TMR_TCLR_TRG_SHIFT (10) /* Bits 10-11: Trigger Output Mode */
#define TMR_TCLR_TRG_MASK (3 << TMR_TCLR_TRG_SHIFT)
# define TMR_TCLR_TRG_NONE (0 << TMR_TCLR_TRG_SHIFT) /* No trigger */
# define TMR_TCLR_TRG_OFLOW (1 << TMR_TCLR_TRG_SHIFT) /* Trigger on overflow */
# define TMR_TCLR_TRG_OFLOWMATCH (2 << TMR_TCLR_TRG_SHIFT) /* Trigger on overflow and match */
#define TMR_TCLR_PT (1 << 12) /* Bit 12: Pulse or toggle mode */
#define TMR_TCLR_CAPT (1 << 13) /* Bit 13: Capture mode. */
#define TMR_TCLR_GPO_CFG (1 << 14) /* Bit 14: General purpose output configuration */
#define TMR_TWPS_W_PEND_TCLR (1 << 0) /* Bit 0: Write pending for TCLR register */
#define TMR_TWPS_W_PEND_TCRR (1 << 1) /* Bit 1: Write pending for TCRR register */
#define TMR_TWPS_W_PEND_TLDR (1 << 2) /* Bit 2: Write pending for TLDR register */
#define TMR_TWPS_W_PEND_TTGR (1 << 3) /* Bit 3: Write pending for TTGR register */
#define TMR_TWPS_W_PEND_TMAR (1 << 4) /* Bit 4: Write pending for TMAR register */
#define TMR_TSICR_SFT (1 << 1) /* Bit 1: Software reset */
#define TMR_TSICR_POSTED (1 << 2) /* Bit 2: Posted mode */
#define TMR1MS_TIOCP_AUTO_IDLE (1 << 0) /* Bit 0: Internal OCP clock gating strategy */
#define TMR1MS_TIOCP_SOFT_RESET (1 << 1) /* Bit 1: Software reset */
#define TMR1MS_TIOCP_ENA_WAKEUP (1 << 2) /* Bit 2: Wake-up feature global control */
#define TMR1MS_TIOCP_IDLE_MODE_SHIFT (3) /* Bits 3-4: Power management, req/ack control */
#define TMR1MS_TIOCP_IDLE_MODE_MASK (3 << TMR1MS_TIOCP_IDLE_MODE_SHIFT)
# define TMR1MS_TIOCP_IDLE_MODE_FORCE (0 << TMR1MS_TIOCP_IDLE_MODE_SHIFT) /* Force-idle mode */
# define TMR1MS_TIOCP_IDLE_MODE_NOIDLE (1 << TMR1MS_TIOCP_IDLE_MODE_SHIFT) /* No-idle mode */
# define TMR1MS_TIOCP_IDLE_MODE_SMART (2 << TMR1MS_TIOCP_IDLE_MODE_SHIFT) /* Smart-idle mode */
# define TMR1MS_TIOCP_IDLE_MODE_WAKEUP (3 << TMR1MS_TIOCP_IDLE_MODE_SHIFT) /* Smart-idle wakeup-capable mode */
#define TMR1MS_TIOCP_EMU_FREE (1 << 5) /* Bit 5: Sensitivity to emulation (debug) suspend event from Debug Subsystem. */
#define TMR1MS_TISTAT (1 << 0) /* Bit 0: Internal reset monitoring */
#define TMR1MS_IRQ_FlAG_MAT (1 << 0) /* Bit 0: IRQ flag for Match */
#define TMR1MS_IRQ_FLAG_OVF (1 << 1) /* Bit 1: IRQ flag for Overflow */
#define TMR1MS_IRQ_FLAG_TCAR (1 << 2) /* Bit 2: IRQ flag for Capture */
#define TMR1MS_TCLR_ST (1 << 0) /* Bit 0: Start/stop timer */
#define TMR1MS_TCLR_AR (1 << 1) /* Bit 1: Auto-reload */
#define TMR1MS_TCLR_PTV_SHIFT (2) /* Bits 2-4: Pre-scale clock Timer value */
#define TMR1MS_TCLR_PTV_MASK (7 << TMR1MS_TCLR_PTV_SHIFT)
#define TMR1MS_TCLR_PRE (1 << 5) /* Bit 5: Prescaler enable */
#define TMR1MS_TCLR_CE (1 << 6) /* Bit 6: Compare mode */
#define TMR1MS_TCLR_SCPWM (1 << 7) /* Bit 7: Pulse Width Modulation output pin default value */
#define TMR1MS_TCLR_TCM_SHIFT (8) /* Bits 8-9: Transition Capture Mode */
#define TMR1MS_TCLR_TCM_MASK (3 << TMR1MS_TCLR_TCM_SHIFT)
# define TMR1MS_TCLR_TCM_NONE (0 << TMR1MS_TCLR_TCM_SHIFT) /* No capture */
# define TMR1MS_TCLR_TCM_RISING (1 << TMR1MS_TCLR_TCM_SHIFT) /* Capture on rising edges */
# define TMR1MS_TCLR_TCM_FALLING (2 << TMR1MS_TCLR_TCM_SHIFT) /* Capture on falling edges */
# define TMR1MS_TCLR_TCM_BOTH (3 << TMR1MS_TCLR_TCM_SHIFT) /* Capture on both edges */
#define TMR1MS_TCLR_TRG_SHIFT (10) /* Bits 10-11: Trigger Output Mode */
#define TMR1MS_TCLR_TRG_MASK (3 << TMR1MS_TCLR_TRG_SHIFT)
# define TMR1MS_TCLR_TRG_NONE (0 << TMR1MS_TCLR_TRG_SHIFT) /* No trigger */
# define TMR1MS_TCLR_TRG_OFLOW (1 << TMR1MS_TCLR_TRG_SHIFT) /* Trigger on overflow */
# define TMR1MS_TCLR_TRG_OFLOWMATCH (2 << TMR1MS_TCLR_TRG_SHIFT) /* Trigger on overflow and match */
#define TMR1MS_TCLR_PT (1 << 12) /* Bit 12: Pulse or toggle mode */
#define TMR1MS_TCLR_CAPT (1 << 13) /* Bit 13: Capture mode. */
#define TMR1MS_TCLR_GPO_CFG (1 << 14) /* Bit 14: General purpose output configuration */
#define TMR1MS_TWPS_W_PEND_TCLR (1 << 0) /* Bit 0: Write pending for TCLR register */
#define TMR1MS_TWPS_W_PEND_TCRR (1 << 1) /* Bit 1: Write pending for TCRR register */
#define TMR1MS_TWPS_W_PEND_TLDR (1 << 2) /* Bit 2: Write pending for TLDR register */
#define TMR1MS_TWPS_W_PEND_TTGR (1 << 3) /* Bit 3: Write pending for TTGR register */
#define TMR1MS_TWPS_W_PEND_TMAR (1 << 4) /* Bit 4: Write pending for TMAR register */
#define TMR1MS_TWPS_W_PEND_TPIR (1 << 5) /* Bit 5: Write pending for TPIR register */
#define TMR1MS_TWPS_W_PEND_TNIR (1 << 6) /* Bit 6: Write pending for TNIR register */
#define TMR1MS_TWPS_W_PEND_TCVR (1 << 7) /* Bit 7: Write pending for TCVR register */
#define TMR1MS_TWPS_W_PEND_TOCR (1 << 8) /* Bit 8: Write pending for TOCR register */
#define TMR1MS_TWPS_W_PEND_TOWR (1 << 9) /* Bit 9: Write pending for TOWR register */
#define TMR1MS_TSICR_SFT (1 << 1) /* Bit 1: Software reset */
#define TMR1MS_TSICR_POSTED (1 << 2) /* Bit 2: Posted mode */
#define TMR1MS_TOCR_MASK (0xffffff)
#define TMR1MS_TOWR_MASK (0xffffff)
#endif /* __ARCH_ARM_SRC_AM335X_CHIP_AM335X_TIMER_H */

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/************************************************************************************
* arch/arm/src/am335x/chip/am335x_uart.h
*
* Copyright (C) 2018 Petro Karashchenko. All rights reserved.
* Author: Petro Karashchenko <petro.karashchenko@gmail.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_AM335X_CHIP_AM335X_UART_H
#define __ARCH_ARM_SRC_AM335X_CHIP_AM335X_UART_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
#include "chip/am335x_memorymap.h"
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* Register offsets *****************************************************************/
#define AM335X_UART_RBR_OFFSET 0x0000 /* UART Receive Buffer Register */
#define AM335X_UART_THR_OFFSET 0x0000 /* UART Transmit Holding Register */
#define AM335X_UART_DLL_OFFSET 0x0000 /* UART Divisor Latch Low Register */
#define AM335X_UART_DLH_OFFSET 0x0004 /* UART Divisor Latch High Register */
#define AM335X_UART_IER_OFFSET 0x0004 /* UART Interrupt Enable Register */
#define AM335X_UART_IIR_OFFSET 0x0008 /* UART Interrupt Identity Register */
#define AM335X_UART_FCR_OFFSET 0x0008 /* UART FIFO Control Register */
#define AM335X_UART_EFR_OFFSET 0x0008 /* UART Extended Feature Register */
#define AM335X_UART_LCR_OFFSET 0x000c /* UART Line Control Register */
#define AM335X_UART_MCR_OFFSET 0x0010 /* UART Modem Control Register */
#define AM335X_UART_LSR_OFFSET 0x0014 /* UART Line Status Register */
#define AM335X_UART_MSR_OFFSET 0x0018 /* UART Modem Status Register */
#define AM335X_UART_TCR_OFFSET 0x0018 /* UART Transmission Control Register */
#define AM335X_UART_SPR_OFFSET 0x001c /* UART Scratch Register */
#define AM335X_UART_TLR_OFFSET 0x001c /* UART Trigger Level Register */
#define AM335X_UART_MDR1_OFFSET 0x0020 /* UART Mode Definition Register 1 */
#define AM335X_UART_MDR2_OFFSET 0x0024 /* UART Mode Definition Register 2 */
#define AM335X_UART_SCR_OFFSET 0x0040 /* UART Supplementary Control Register */
#define AM335X_UART_SSR_OFFSET 0x0044 /* UART Supplementary Status Register */
#define AM335X_UART_SYSC_OFFSET 0x0054 /* UART System Configuration Register */
#define AM335X_UART_SYSS_OFFSET 0x0058 /* UART System Status Register */
#define AM335X_UART_RFL_OFFSET 0x0064 /* UART Received FIFO Level Register */
#define AM335X_UART_TFL_OFFSET 0x0068 /* UART Transmit FIFO Level Register */
/* Register virtual addresses *******************************************************/
#define AM335X_UART_RBR(n) (AM335X_UART_VADDR(n) + AM335X_UART_RBR_OFFSET)
#define AM335X_UART_THR(n) (AM335X_UART_VADDR(n) + AM335X_UART_THR_OFFSET)
#define AM335X_UART_DLL(n) (AM335X_UART_VADDR(n) + AM335X_UART_DLL_OFFSET)
#define AM335X_UART_DLH(n) (AM335X_UART_VADDR(n) + AM335X_UART_DLH_OFFSET)
#define AM335X_UART_IER(n) (AM335X_UART_VADDR(n) + AM335X_UART_IER_OFFSET)
#define AM335X_UART_IIR(n) (AM335X_UART_VADDR(n) + AM335X_UART_IIR_OFFSET)
#define AM335X_UART_FCR(n) (AM335X_UART_VADDR(n) + AM335X_UART_FCR_OFFSET)
#define AM335X_UART_EFR(n) (AM335X_UART_VADDR(n) + AM335X_UART_EFR_OFFSET)
#define AM335X_UART_LCR(n) (AM335X_UART_VADDR(n) + AM335X_UART_LCR_OFFSET)
#define AM335X_UART_MCR(n) (AM335X_UART_VADDR(n) + AM335X_UART_MCR_OFFSET)
#define AM335X_UART_LSR(n) (AM335X_UART_VADDR(n) + AM335X_UART_LSR_OFFSET)
#define AM335X_UART_MSR(n) (AM335X_UART_VADDR(n) + AM335X_UART_MSR_OFFSET)
#define AM335X_UART_TCR(n) (AM335X_UART_VADDR(n) + AM335X_UART_TCR_OFFSET)
#define AM335X_UART_SPR(n) (AM335X_UART_VADDR(n) + AM335X_UART_SPR_OFFSET)
#define AM335X_UART_TLR(n) (AM335X_UART_VADDR(n) + AM335X_UART_TLR_OFFSET)
#define AM335X_UART_MDR1(n) (AM335X_UART_VADDR(n) + AM335X_UART_MDR1_OFFSET)
#define AM335X_UART_MDR2(n) (AM335X_UART_VADDR(n) + AM335X_UART_MDR2_OFFSET)
#define AM335X_UART_SCR(n) (AM335X_UART_VADDR(n) + AM335X_UART_SCR_OFFSET)
#define AM335X_UART_SSR(n) (AM335X_UART_VADDR(n) + AM335X_UART_SSR_OFFSET)
#define AM335X_UART_SYSC(n) (AM335X_UART_VADDR(n) + AM335X_UART_SYSC_OFFSET)
#define AM335X_UART_SYSS(n) (AM335X_UART_VADDR(n) + AM335X_UART_SYSS_OFFSET)
#define AM335X_UART_RFL(n) (AM335X_UART_VADDR(n) + AM335X_UART_RFL_OFFSET)
#define AM335X_UART_TFL(n) (AM335X_UART_VADDR(n) + AM335X_UART_TFL_OFFSET)
#define AM335X_UART0_RBR (AM335X_UART0_VADDR + AM335X_UART_RBR_OFFSET)
#define AM335X_UART0_THR (AM335X_UART0_VADDR + AM335X_UART_THR_OFFSET)
#define AM335X_UART0_DLL (AM335X_UART0_VADDR + AM335X_UART_DLL_OFFSET)
#define AM335X_UART0_DLH (AM335X_UART0_VADDR + AM335X_UART_DLH_OFFSET)
#define AM335X_UART0_IER (AM335X_UART0_VADDR + AM335X_UART_IER_OFFSET)
#define AM335X_UART0_IIR (AM335X_UART0_VADDR + AM335X_UART_IIR_OFFSET)
#define AM335X_UART0_FCR (AM335X_UART0_VADDR + AM335X_UART_FCR_OFFSET)
#define AM335X_UART0_EFR (AM335X_UART0_VADDR + AM335X_UART_EFR_OFFSET)
#define AM335X_UART0_LCR (AM335X_UART0_VADDR + AM335X_UART_LCR_OFFSET)
#define AM335X_UART0_MCR (AM335X_UART0_VADDR + AM335X_UART_MCR_OFFSET)
#define AM335X_UART0_LSR (AM335X_UART0_VADDR + AM335X_UART_LSR_OFFSET)
#define AM335X_UART0_MSR (AM335X_UART0_VADDR + AM335X_UART_MSR_OFFSET)
#define AM335X_UART0_TCR (AM335X_UART0_VADDR + AM335X_UART_TCR_OFFSET)
#define AM335X_UART0_SPR (AM335X_UART0_VADDR + AM335X_UART_SPR_OFFSET)
#define AM335X_UART0_TLR (AM335X_UART0_VADDR + AM335X_UART_TLR_OFFSET)
#define AM335X_UART0_MDR1 (AM335X_UART0_VADDR + AM335X_UART_MDR1_OFFSET)
#define AM335X_UART0_MDR2 (AM335X_UART0_VADDR + AM335X_UART_MDR2_OFFSET)
#define AM335X_UART0_SCR (AM335X_UART0_VADDR + AM335X_UART_SCR_OFFSET)
#define AM335X_UART0_SSR (AM335X_UART0_VADDR + AM335X_UART_SSR_OFFSET)
#define AM335X_UART0_SYSC (AM335X_UART0_VADDR + AM335X_UART_SYSC_OFFSET)
#define AM335X_UART0_SYSS (AM335X_UART0_VADDR + AM335X_UART_SYSS_OFFSET)
#define AM335X_UART0_RFL (AM335X_UART0_VADDR + AM335X_UART_RFL_OFFSET)
#define AM335X_UART0_TFL (AM335X_UART0_VADDR + AM335X_UART_TFL_OFFSET)
#define AM335X_UART1_RBR (AM335X_UART1_VADDR + AM335X_UART_RBR_OFFSET)
#define AM335X_UART1_THR (AM335X_UART1_VADDR + AM335X_UART_THR_OFFSET)
#define AM335X_UART1_DLL (AM335X_UART1_VADDR + AM335X_UART_DLL_OFFSET)
#define AM335X_UART1_DLH (AM335X_UART1_VADDR + AM335X_UART_DLH_OFFSET)
#define AM335X_UART1_IER (AM335X_UART1_VADDR + AM335X_UART_IER_OFFSET)
#define AM335X_UART1_IIR (AM335X_UART1_VADDR + AM335X_UART_IIR_OFFSET)
#define AM335X_UART1_FCR (AM335X_UART1_VADDR + AM335X_UART_FCR_OFFSET)
#define AM335X_UART1_EFR (AM335X_UART1_VADDR + AM335X_UART_EFR_OFFSET)
#define AM335X_UART1_LCR (AM335X_UART1_VADDR + AM335X_UART_LCR_OFFSET)
#define AM335X_UART1_MCR (AM335X_UART1_VADDR + AM335X_UART_MCR_OFFSET)
#define AM335X_UART1_LSR (AM335X_UART1_VADDR + AM335X_UART_LSR_OFFSET)
#define AM335X_UART1_MSR (AM335X_UART1_VADDR + AM335X_UART_MSR_OFFSET)
#define AM335X_UART1_TCR (AM335X_UART1_VADDR + AM335X_UART_TCR_OFFSET)
#define AM335X_UART1_SPR (AM335X_UART1_VADDR + AM335X_UART_SPR_OFFSET)
#define AM335X_UART1_TLR (AM335X_UART1_VADDR + AM335X_UART_TLR_OFFSET)
#define AM335X_UART1_MDR1 (AM335X_UART1_VADDR + AM335X_UART_MDR1_OFFSET)
#define AM335X_UART1_MDR2 (AM335X_UART1_VADDR + AM335X_UART_MDR2_OFFSET)
#define AM335X_UART1_SCR (AM335X_UART1_VADDR + AM335X_UART_SCR_OFFSET)
#define AM335X_UART1_SSR (AM335X_UART1_VADDR + AM335X_UART_SSR_OFFSET)
#define AM335X_UART1_SYSC (AM335X_UART1_VADDR + AM335X_UART_SYSC_OFFSET)
#define AM335X_UART1_SYSS (AM335X_UART1_VADDR + AM335X_UART_SYSS_OFFSET)
#define AM335X_UART1_RFL (AM335X_UART1_VADDR + AM335X_UART_RFL_OFFSET)
#define AM335X_UART1_TFL (AM335X_UART1_VADDR + AM335X_UART_TFL_OFFSET)
#define AM335X_UART2_RBR (AM335X_UART2_VADDR + AM335X_UART_RBR_OFFSET)
#define AM335X_UART2_THR (AM335X_UART2_VADDR + AM335X_UART_THR_OFFSET)
#define AM335X_UART2_DLL (AM335X_UART2_VADDR + AM335X_UART_DLL_OFFSET)
#define AM335X_UART2_DLH (AM335X_UART2_VADDR + AM335X_UART_DLH_OFFSET)
#define AM335X_UART2_IER (AM335X_UART2_VADDR + AM335X_UART_IER_OFFSET)
#define AM335X_UART2_IIR (AM335X_UART2_VADDR + AM335X_UART_IIR_OFFSET)
#define AM335X_UART2_FCR (AM335X_UART2_VADDR + AM335X_UART_FCR_OFFSET)
#define AM335X_UART2_EFR (AM335X_UART2_VADDR + AM335X_UART_EFR_OFFSET)
#define AM335X_UART2_LCR (AM335X_UART2_VADDR + AM335X_UART_LCR_OFFSET)
#define AM335X_UART2_MCR (AM335X_UART2_VADDR + AM335X_UART_MCR_OFFSET)
#define AM335X_UART2_LSR (AM335X_UART2_VADDR + AM335X_UART_LSR_OFFSET)
#define AM335X_UART2_MSR (AM335X_UART2_VADDR + AM335X_UART_MSR_OFFSET)
#define AM335X_UART2_TCR (AM335X_UART2_VADDR + AM335X_UART_TCR_OFFSET)
#define AM335X_UART2_SPR (AM335X_UART2_VADDR + AM335X_UART_SPR_OFFSET)
#define AM335X_UART2_TLR (AM335X_UART2_VADDR + AM335X_UART_TLR_OFFSET)
#define AM335X_UART2_MDR1 (AM335X_UART2_VADDR + AM335X_UART_MDR1_OFFSET)
#define AM335X_UART2_MDR2 (AM335X_UART2_VADDR + AM335X_UART_MDR2_OFFSET)
#define AM335X_UART2_SCR (AM335X_UART2_VADDR + AM335X_UART_SCR_OFFSET)
#define AM335X_UART2_SSR (AM335X_UART2_VADDR + AM335X_UART_SSR_OFFSET)
#define AM335X_UART2_SYSC (AM335X_UART2_VADDR + AM335X_UART_SYSC_OFFSET)
#define AM335X_UART2_SYSS (AM335X_UART2_VADDR + AM335X_UART_SYSS_OFFSET)
#define AM335X_UART2_RFL (AM335X_UART2_VADDR + AM335X_UART_RFL_OFFSET)
#define AM335X_UART2_TFL (AM335X_UART2_VADDR + AM335X_UART_TFL_OFFSET)
#define AM335X_UART3_RBR (AM335X_UART3_VADDR + AM335X_UART_RBR_OFFSET)
#define AM335X_UART3_THR (AM335X_UART3_VADDR + AM335X_UART_THR_OFFSET)
#define AM335X_UART3_DLL (AM335X_UART3_VADDR + AM335X_UART_DLL_OFFSET)
#define AM335X_UART3_DLH (AM335X_UART3_VADDR + AM335X_UART_DLH_OFFSET)
#define AM335X_UART3_IER (AM335X_UART3_VADDR + AM335X_UART_IER_OFFSET)
#define AM335X_UART3_IIR (AM335X_UART3_VADDR + AM335X_UART_IIR_OFFSET)
#define AM335X_UART3_FCR (AM335X_UART3_VADDR + AM335X_UART_FCR_OFFSET)
#define AM335X_UART3_EFR (AM335X_UART3_VADDR + AM335X_UART_EFR_OFFSET)
#define AM335X_UART3_LCR (AM335X_UART3_VADDR + AM335X_UART_LCR_OFFSET)
#define AM335X_UART3_MCR (AM335X_UART3_VADDR + AM335X_UART_MCR_OFFSET)
#define AM335X_UART3_LSR (AM335X_UART3_VADDR + AM335X_UART_LSR_OFFSET)
#define AM335X_UART3_MSR (AM335X_UART3_VADDR + AM335X_UART_MSR_OFFSET)
#define AM335X_UART3_TCR (AM335X_UART3_VADDR + AM335X_UART_TCR_OFFSET)
#define AM335X_UART3_SPR (AM335X_UART3_VADDR + AM335X_UART_SPR_OFFSET)
#define AM335X_UART3_TLR (AM335X_UART3_VADDR + AM335X_UART_TLR_OFFSET)
#define AM335X_UART3_MDR1 (AM335X_UART3_VADDR + AM335X_UART_MDR1_OFFSET)
#define AM335X_UART3_MDR2 (AM335X_UART3_VADDR + AM335X_UART_MDR2_OFFSET)
#define AM335X_UART3_SCR (AM335X_UART3_VADDR + AM335X_UART_SCR_OFFSET)
#define AM335X_UART3_SSR (AM335X_UART3_VADDR + AM335X_UART_SSR_OFFSET)
#define AM335X_UART3_SYSC (AM335X_UART3_VADDR + AM335X_UART_SYSC_OFFSET)
#define AM335X_UART3_SYSS (AM335X_UART3_VADDR + AM335X_UART_SYSS_OFFSET)
#define AM335X_UART3_RFL (AM335X_UART3_VADDR + AM335X_UART_RFL_OFFSET)
#define AM335X_UART3_TFL (AM335X_UART3_VADDR + AM335X_UART_TFL_OFFSET)
#define AM335X_UART4_RBR (AM335X_UART4_VADDR + AM335X_UART_RBR_OFFSET)
#define AM335X_UART4_THR (AM335X_UART4_VADDR + AM335X_UART_THR_OFFSET)
#define AM335X_UART4_DLL (AM335X_UART4_VADDR + AM335X_UART_DLL_OFFSET)
#define AM335X_UART4_DLH (AM335X_UART4_VADDR + AM335X_UART_DLH_OFFSET)
#define AM335X_UART4_IER (AM335X_UART4_VADDR + AM335X_UART_IER_OFFSET)
#define AM335X_UART4_IIR (AM335X_UART4_VADDR + AM335X_UART_IIR_OFFSET)
#define AM335X_UART4_FCR (AM335X_UART4_VADDR + AM335X_UART_FCR_OFFSET)
#define AM335X_UART4_EFR (AM335X_UART4_VADDR + AM335X_UART_EFR_OFFSET)
#define AM335X_UART4_LCR (AM335X_UART4_VADDR + AM335X_UART_LCR_OFFSET)
#define AM335X_UART4_MCR (AM335X_UART4_VADDR + AM335X_UART_MCR_OFFSET)
#define AM335X_UART4_LSR (AM335X_UART4_VADDR + AM335X_UART_LSR_OFFSET)
#define AM335X_UART4_MSR (AM335X_UART4_VADDR + AM335X_UART_MSR_OFFSET)
#define AM335X_UART4_TCR (AM335X_UART4_VADDR + AM335X_UART_TCR_OFFSET)
#define AM335X_UART4_SPR (AM335X_UART4_VADDR + AM335X_UART_SPR_OFFSET)
#define AM335X_UART4_TLR (AM335X_UART4_VADDR + AM335X_UART_TLR_OFFSET)
#define AM335X_UART4_MDR1 (AM335X_UART4_VADDR + AM335X_UART_MDR1_OFFSET)
#define AM335X_UART4_MDR2 (AM335X_UART4_VADDR + AM335X_UART_MDR2_OFFSET)
#define AM335X_UART4_SCR (AM335X_UART4_VADDR + AM335X_UART_SCR_OFFSET)
#define AM335X_UART4_SSR (AM335X_UART4_VADDR + AM335X_UART_SSR_OFFSET)
#define AM335X_UART4_SYSC (AM335X_UART4_VADDR + AM335X_UART_SYSC_OFFSET)
#define AM335X_UART4_SYSS (AM335X_UART4_VADDR + AM335X_UART_SYSS_OFFSET)
#define AM335X_UART4_RFL (AM335X_UART4_VADDR + AM335X_UART_RFL_OFFSET)
#define AM335X_UART4_TFL (AM335X_UART4_VADDR + AM335X_UART_TFL_OFFSET)
#define AM335X_UART5_RBR (AM335X_UART5_VADDR + AM335X_UART_RBR_OFFSET)
#define AM335X_UART5_THR (AM335X_UART5_VADDR + AM335X_UART_THR_OFFSET)
#define AM335X_UART5_DLL (AM335X_UART5_VADDR + AM335X_UART_DLL_OFFSET)
#define AM335X_UART5_DLH (AM335X_UART5_VADDR + AM335X_UART_DLH_OFFSET)
#define AM335X_UART5_IER (AM335X_UART5_VADDR + AM335X_UART_IER_OFFSET)
#define AM335X_UART5_IIR (AM335X_UART5_VADDR + AM335X_UART_IIR_OFFSET)
#define AM335X_UART5_FCR (AM335X_UART5_VADDR + AM335X_UART_FCR_OFFSET)
#define AM335X_UART5_EFR (AM335X_UART5_VADDR + AM335X_UART_EFR_OFFSET)
#define AM335X_UART5_LCR (AM335X_UART5_VADDR + AM335X_UART_LCR_OFFSET)
#define AM335X_UART5_MCR (AM335X_UART5_VADDR + AM335X_UART_MCR_OFFSET)
#define AM335X_UART5_LSR (AM335X_UART5_VADDR + AM335X_UART_LSR_OFFSET)
#define AM335X_UART5_MSR (AM335X_UART5_VADDR + AM335X_UART_MSR_OFFSET)
#define AM335X_UART5_TCR (AM335X_UART5_VADDR + AM335X_UART_TCR_OFFSET)
#define AM335X_UART5_SPR (AM335X_UART5_VADDR + AM335X_UART_SPR_OFFSET)
#define AM335X_UART5_TLR (AM335X_UART5_VADDR + AM335X_UART_TLR_OFFSET)
#define AM335X_UART5_MDR1 (AM335X_UART5_VADDR + AM335X_UART_MDR1_OFFSET)
#define AM335X_UART5_MDR2 (AM335X_UART5_VADDR + AM335X_UART_MDR2_OFFSET)
#define AM335X_UART5_SCR (AM335X_UART5_VADDR + AM335X_UART_SCR_OFFSET)
#define AM335X_UART5_SSR (AM335X_UART5_VADDR + AM335X_UART_SSR_OFFSET)
#define AM335X_UART5_SYSC (AM335X_UART5_VADDR + AM335X_UART_SYSC_OFFSET)
#define AM335X_UART5_SYSS (AM335X_UART5_VADDR + AM335X_UART_SYSS_OFFSET)
#define AM335X_UART5_RFL (AM335X_UART5_VADDR + AM335X_UART_RFL_OFFSET)
#define AM335X_UART5_TFL (AM335X_UART5_VADDR + AM335X_UART_TFL_OFFSET)
/* Register bit field definitions ***************************************************/
/* UART Receive Buffer Register */
#define UART_RBR_MASK 0x000000ff
/* UART Transmit Holding Register */
#define UART_THR_MASK 0x000000ff
/* UART Divisor Latch Low Register */
#define UART_DLL_MASK 0x000000ff
/* UART Divisor Latch High Register */
#define UART_DLH_MASK 0x0000003f
/* UART Interrupt Enable Register */
#define UART_IER_RHR_CTI (1 << 0) /* Bit 0: Enable Received Data Available Interrupt */
#define UART_IER_THR (1 << 1) /* Bit 1: Enable Transmit Holding Register Empty Interrupt */
#define UART_IER_LINE_STS (1 << 2) /* Bit 2: Enable Receiver Line Status Interrupt */
#define UART_IER_MODEM_STS (1 << 3) /* Bit 3: Enable Modem Status Interrupt */
#define UART_IER_RTS (1 << 6) /* Bit 6: Enable RTS (active-low) interrupt */
#define UART_IER_CTS (1 << 7) /* Bit 7: Enable CTS (active-low) interrupt */
#define UART_IER_ALLIE 0x000000cf
/* UART Interrupt Identification Register */
#define UART_IIR_IID_SHIFT (0)
#define UART_IIR_IID_MASK (63 << UART_IIR_IID_SHIFT)
# define UART_IIR_IID_MODEM (0 << UART_IIR_IID_SHIFT)
# define UART_IIR_IID_NONE (1 << UART_IIR_IID_SHIFT) /* No interrupt pending */
# define UART_IIR_IID_THR (2 << UART_IIR_IID_SHIFT)
# define UART_IIR_IID_RHR (4 << UART_IIR_IID_SHIFT)
# define UART_IIR_IID_RXSTATUS (6 << UART_IIR_IID_SHIFT)
# define UART_IIR_IID_RXTIMEOUT (12 << UART_IIR_IID_SHIFT)
# define UART_IIR_IID_XOFF (16 << UART_IIR_IID_SHIFT)
# define UART_IIR_IID_STATECHANGE (32 << UART_IIR_IID_SHIFT)
#define UART_IIR_FEFLAG_SHIFT (6) /* Bits 6-7: FIFOs Enable Flag */
#define UART_IIR_FEFLAG_MASK (3 << UART_IIR_FEFLAG_SHIFT)
# define UART_IIR_FEFLAG_DISABLE (0 << UART_IIR_FEFLAG_SHIFT)
# define UART_IIR_FEFLAG_ENABLE (3 << UART_IIR_FEFLAG_SHIFT)
/* UART FIFO Control Register */
#define UART_FCR_FIFO_EN (1 << 0) /* Bit 0: Enable TX and RX FIFOs */
#define UART_FCR_RFIFO_CLEAR (1 << 1) /* Bit 1: Clear RX FIFO */
#define UART_FCR_TFIFO_CLEAR (1 << 2) /* Bit 2: Clear TX FIFO */
#define UART_FCR_DMA_MODE (1 << 3) /* Bit 3: DMA Mode */
#define UART_FCR_TFT_SHIFT (4) /* Bits 4-5: TX FIFO Trigger Level */
#define UART_FCR_TFT_MASK (3 << UART_FCR_TFT_SHIFT)
# define UART_FCR_TFT_8CHAR (0 << UART_FCR_TFT_SHIFT) /* 8 Chars in FIFO */
# define UART_FCR_TFT_16CHAR (1 << UART_FCR_TFT_SHIFT) /* 16 Chars in FIFO */
# define UART_FCR_TFT_32CHAR (2 << UART_FCR_TFT_SHIFT) /* 32 Chars in FIFO */
# define UART_FCR_TFT_56CHAR (3 << UART_FCR_TFT_SHIFT) /* 56 Chars in FIFO */
#define UART_FCR_RFT_SHIFT (6) /* Bits 6-7: RX FIFO Trigger Level */
#define UART_FCR_RFT_MASK (3 << UART_FCR_RFT_SHIFT)
# define UART_FCR_RFT_8CHAR (0 << UART_FCR_RFT_SHIFT) /* 8 Chars in FIFO */
# define UART_FCR_RFT_16CHAR (1 << UART_FCR_RFT_SHIFT) /* 16 Chars in FIFO */
# define UART_FCR_RFT_56CHAR (2 << UART_FCR_RFT_SHIFT) /* 56 Chars in FIFO */
# define UART_FCR_RFT_60CHAR (3 << UART_FCR_RFT_SHIFT) /* 60 Chars in FIFO */
/* UART Line Control Register */
#define UART_LCR_DLS_SHIFT (0) /* Bits 0-1: Data Length Select */
#define UART_LCR_DLS_MASK (3 << UART_LCR_DLS_SHIFT)
# define UART_LCR_DLS_5BITS (0 << UART_LCR_DLS_SHIFT) /* 5 Bits */
# define UART_LCR_DLS_6BITS (1 << UART_LCR_DLS_SHIFT) /* 6 Bits */
# define UART_LCR_DLS_7BITS (2 << UART_LCR_DLS_SHIFT) /* 7 Bits */
# define UART_LCR_DLS_8BITS (3 << UART_LCR_DLS_SHIFT) /* 8 Bits */
#define UART_LCR_STOP_SHIFT (2) /* Bit 2: Number of Stop Bits */
# define UART_LCR_STOP_1BITS (0 << UART_LCR_STOP_SHIFT) /* 1 Stop Bit */
# define UART_LCR_STOP_2BITS (1 << UART_LCR_STOP_SHIFT) /* 2 Stop Bits */
#define UART_LCR_PEN (1 << 3) /* Bit 3: Parity Enable */
#define UART_LCR_PARITY_SHIFT (3) /* Bit 3-4: Parity Enable and Parity Select */
# define UART_LCR_PARITY_NONE (0 << UART_LCR_PARITY_SHIFT) /* No Parity */
# define UART_LCR_PARITY_ODD (1 << UART_LCR_PARITY_SHIFT) /* Odd Parity Bit */
# define UART_LCR_PARITY_EVEN (3 << UART_LCR_PARITY_SHIFT) /* Even Parity Bit */
#define UART_LCR_BC (1 << 6) /* Bit 6: Break Control Bit */
#define UART_LCR_DLAB (1 << 7) /* Bit 7: Divisor Latch Access Enable Bit */
#define UART_LCR_CONFIG_MODE_A 0x00000080
#define UART_LCR_CONFIG_MODE_B 0x000000bf
#define UART_LCR_OPER_MODE 0x0000007f
/* UART Modem Control Register */
#define UART_MCR_DTR (1 << 0) /* Bit 0: Data Terminal Ready */
#define UART_MCR_RTS (1 << 1) /* Bit 1: Request to Send */
#define UART_MCR_LOOP (1 << 4) /* Bit 4: Enable Loop Back Mode */
/* UART Line Status Register */
#define UART_LSR_DR (1 << 0) /* Bit 0: Data Ready */
#define UART_LSR_OE (1 << 1) /* Bit 1: Overrun Error */
#define UART_LSR_PE (1 << 2) /* Bit 2: Parity Error */
#define UART_LSR_FE (1 << 3) /* Bit 3: Framing Error */
#define UART_LSR_BI (1 << 4) /* Bit 4: Break Interrupt */
#define UART_LSR_THRE (1 << 5) /* Bit 5: TX Holding Register Empty */
#define UART_LSR_TEMT (1 << 6) /* Bit 6: Transmitter Empty */
#define UART_LSR_FIFOERR (1 << 7) /* Bit 7: RX Data Error in FIFO */
/* UART Modem Status Register */
#define UART_MSR_CTS (1 << 0) /* Bit 0: Line State of Clear to Send */
#define UART_MSR_DSR (1 << 1) /* Bit 1: Line State of Data Set Ready */
#define UART_MSR_RI (1 << 2) /* Bit 2: Line State of Ring Indicator */
#define UART_MSR_DCD (1 << 3) /* Bit 3: Line State of Data Carrier Detect */
#define UART_MSR_NCTS (1 << 4) /* Bit 4: Complement of Clear To Send */
#define UART_MSR_NDSR (1 << 5) /* Bit 5: Complement of Data Set Ready */
#define UART_MSR_NRI (1 << 6) /* Bit 6: Complement of Ring Indicator */
#define UART_MSR_NDCD (1 << 7) /* Bit 7: Complement of Data Carrier Detect */
/* UART Scratchpad Register */
#define UART_SPR_MASK 0x000000ff
/* UART Transmit FIFO Level */
#define UART_TFL_SHIFT (0) /* Bits 0-7: Transmit FIFO Level */
#define UART_TFL_MASK (0xff << UART_TFL_SHIFT)
# define UART_TFL(n) ((uint32_t)(n) << UART_TFL_SHIFT)
/* UART Receive FIFO Level */
#define UART_RFL_SHIFT (0) /* Bits 0-7: Receive FIFO Level */
#define UART_RFL_MASK (0xff << UART_RFL_SHIFT)
# define UART_RFL(n) ((uint32_t)(n) << UART_RFL_SHIFT)
/* UART Mode Definition 1 Register */
#define UART_MDR1_MODE_SHIFT (0) /* Bits 0-2: Operation Mode Selection */
# define UART_MDR1_MODE_16x (0 << UART_MDR1_MODE_SHIFT) /* UART 16x Mode. */
# define UART_MDR1_MODE_SIR (1 << UART_MDR1_MODE_SHIFT) /* SIR mode */
# define UART_MDR1_MODE_16xAUTO (2 << UART_MDR1_MODE_SHIFT) /* UART 16x Auto-Baud */
# define UART_MDR1_MODE_13x (3 << UART_MDR1_MODE_SHIFT) /* UART 13x mode */
# define UART_MDR1_MODE_MIR (4 << UART_MDR1_MODE_SHIFT) /* MIR Mode */
# define UART_MDR1_MODE_FIR (5 << UART_MDR1_MODE_SHIFT) /* FIR Mode */
# define UART_MDR1_MODE_CIR (6 << UART_MDR1_MODE_SHIFT) /* CIR Mode */
# define UART_MDR1_MODE_DISABLE (7 << UART_MDR1_MODE_SHIFT) /* Disabled Mode */
/* UART System Configuration Register */
#define UART_SYSC_SRESET (1 << 1) /* Bit 1: Software Reset */
#define UART_SYSC_WAKEUP (1 << 2) /* Bit 2: Wake-up Control */
/* UART Enhanced Feature Register */
#define UART_EFR_ENHANCEDEN (1 << 4) /* Bit 4: Enable Enhanced Functions Write */
#define UART_EFR_AUTORTSEN (1 << 6) /* Bit 6: Enable Auto-RTS */
#define UART_EFR_AUTOCTSEN (1 << 7) /* Bit 7: Enable Auto-CTS */
#endif /* __ARCH_ARM_SRC_AM335X_CHIP_AM335X_UART_H */

13
configs/Kconfig
View file

@ -787,6 +787,15 @@ config ARCH_BOARD_PCDUINO_A10
the differences are cosmetic. This port was developed on the v1 board,
but the others may be compatible.
config ARCH_BOARD_BEAGLEBONE_BLACK
bool "beaglebone black"
depends on ARCH_CHIP_AM335X
select ARCH_HAVE_LEDS
select ARCH_HAVE_BUTTONS
select ARCH_HAVE_IRQBUTTONS
---help---
This is the port of NuttX to the TI Beaglebone Black board.
config ARCH_BOARD_PIC32MX_STARTERKIT
bool "Microchip PIC32MX Ethernet Starter Kit (DM320004)"
depends on ARCH_CHIP_PIC32MX795F512L
@ -1843,6 +1852,7 @@ config ARCH_BOARD
default "or1k" if ARCH_BOARD_OR1K
default "p112" if ARCH_BOARD_P112
default "pcduino-a10" if ARCH_BOARD_PCDUINO_A10
default "beaglebone-black" if ARCH_BOARD_BEAGLEBONE_BLACK
default "pic32mx-starterkit" if ARCH_BOARD_PIC32MX_STARTERKIT
default "pic32mx7mmb" if ARCH_BOARD_PIC32MX7MMB
default "pic32mz-starterkit" if ARCH_BOARD_PIC32MZ_STARTERKIT
@ -2233,6 +2243,9 @@ endif
if ARCH_BOARD_PCDUINO_A10
source "configs/pcduino-a10/Kconfig"
endif
if ARCH_BOARD_BEAGLEBONE_BLACK
source "configs/beaglebone-black/Kconfig"
endif
if ARCH_BOARD_PIC32MX_STARTERKIT
source "configs/pic32mx-starterkit/Kconfig"
endif

7
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@ -0,0 +1,7 @@
#
# For a description of the syntax of this configuration file,
# see the file kconfig-language.txt in the NuttX tools repository.
#
if ARCH_BOARD_BEAGLEBONE_BLACK
endif # ARCH_BOARD_BEAGLEBONE_BLACK

191
configs/beaglebone-black/README.txt Normal file
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@ -0,0 +1,191 @@
README
======
This directory contains the port of NuttX to the Beaglebone Black board
See http://beagleboard.org for information about Beaglebone Black. This
board is based around the TI AM335x Sitara Cortex-A8 CPU.
This port was developed on the rev. C of the board:
Beaglebone Black (See http://beagleboard.org/black)
ITEMS DETAILS
-------------------- ---------------------------------------------------
CPU 1GHz ARM Cortex-A8
GPU SG530 3D, 20M Polygons/S
DRAM 512MB DDR3 800MHz
Onboard Storage 4GB, 8bit Embedded MMC, microSD card (TF) slot for up to 32GB
Video Output HDMI
Extension Interface 2.54mm Headers, 92 pins
Network interface 10/100Mbps RJ45
Power 5V, 1000mA
Overall Size 3.4" X 2.15"
Main features of the TI AM335x Sitara
(See http://www.ti.com/product/am3358):
CPU
- ARM Cortex-A8
- 32KB I-Cache
- 32KB D-Cache
- 256KB L2 Cache with ECC
FPU
- NEON SIMD Coprocessor
Memory
- 176KB of On-Chip Boot ROM
- 64KB of Dedicated RAM
- 64KB of General-Purpose On-Chip Memory Controller (OCMC) RAM
- 16-bit DDR2/DDR3
- Memory capacity up to 8G bits
- 8-Bit and 16-Bit Asynchronous Memory Interface with up to Seven Chip Selects (NAND, NOR, Muxed-NOR, SRAM)
Boot Devices
- NAND Flash
- SPI NOR Flash
- SD Card
- UART
TODO:
Contents
========
- Beaglebone black Rev.C Connectors
- Serial Console
- LEDs
- Buttons
- JTAG
- Booting NuttX from an SD card
- Configurations
Beaglebone black Rev.C Connectors
=====================
Serial Console
==============
By default, the serial console will be provided on UART0 in all of these
configurations.
LEDs
====
The Beaglebone black Rev. C has four blue LEDs; three can be controlled from software.
Two are tied to ground and, hence, illuminated by driving the output pins to a high
value:
1. LED0 GPMC_A5 GPMC_A5/GMII2_TXD0/RGMII2_TD0/RMII2_TXD0/GPMC_A21/PR1_MII1_RXD3/eQEP1B_IN/GPIO1_21
2. LED1 GPMC_A6 GPMC_A6/GMII2_TXCLK/RGMII2_TCLK/MMC2_DAT4/GPMC_A22/PR1_MII1_RXD2/eQEP1_INDEX/GPIO1_22
3. LED2 GPMC_A7 GPMC_A7/GMII2_RXCLK/RGMII2_RCLK/MMC2_DAT5/GPMC_A23/PR1_MII1_RXD1/eQEP1_STROBE/GPIO1_23
4. LED3 GPMC_A8 GPMC_A8/GMII2_RXD3/RGMII2_RD3/MMC2_DAT6/GPMC_A24/PR1_MII1_RXD0/MCASP0_ACLKX/GPIO1_24
These LEDs are not used by the board port unless CONFIG_ARCH_LEDS is
defined. In that case, the usage by the board port is defined in
include/board.h and src/am335x_leds.c. The LEDs are used to encode OS-related
events as follows:
SYMBOL Meaning LED state
LED1 LED3 LED4
----------------- ----------------------- ---- ---- ------------
LED_STARTED NuttX has been started ON OFF OFF
LED_HEAPALLOCATE Heap has been allocated OFF ON OFF
LED_IRQSENABLED Interrupts enabled ON ON OFF
LED_STACKCREATED Idle stack created ON ON OFF
LED_INIRQ In an interrupt N/C N/C Soft glow
LED_SIGNAL In a signal handler N/C N/C Soft glow
LED_ASSERTION An assertion failed N/C N/C Soft glow
LED_PANIC The system has crashed N/C N/C 2Hz Flashing
LED_IDLE MCU is is sleep mode Not used
After booting, LED1 and 3 are not longer used by the system and can be used for
other purposes by the application (Of course, all LEDs are available to the
application if CONFIG_ARCH_LEDS is not defined.
Buttons
=======
JTAG
====
Booting NuttX from an SD card
=============================
These are the steps to get U-Boot booting from SD Card:
1. Stop Beaglebone Black boot process in U-Boot.
2. Insert a FLASH stick into host pc and format FAT32 FS.
3. Copy nuttx.bin into FLASH stick root.
4. Remove the FLASH stick from the host pc. Insert into the Beaglecone Black
microSD slot. Load Nuttx into memory and run
U-Boot# load mmc 0 0x8a000000 nuttx.bin
U-Boot# go 0x8a000000
Configurations
==============
Information Common to All Configurations
----------------------------------------
Each Beaglebone Black configuration is maintained in a sub-directory and
can be selected as follow:
tools/configure.sh [OPTIONS] beaglebone-black/<subdir>
Where [OPTIONS] include -l to configure for a Linux host platform and
-c means to configure for a Windows Cygwin host platform. -h will give
you the list of all options.
Before building, make sure the PATH environment variable includes the
correct path to the directory than holds your toolchain binaries.
And then build NuttX by simply typing the following. At the conclusion of
the make, the nuttx binary will reside in an ELF file called, simply, nuttx.
make
The <subdir> that is provided above as an argument to the tools/configure.sh
must be is one of the following.
NOTES:
1. These configurations use the mconf-based configuration tool. To
change any of these configurations using that tool, you should:
a. Build and install the kconfig-mconf tool. See nuttx/README.txt
see additional README.txt files in the NuttX tools repository.
b. Execute 'make menuconfig' in nuttx/ in order to start the
reconfiguration process.
2. Unless stated otherwise, all configurations generate console
output on UART0.
3. All of these configurations use the Code Sourcery for Windows toolchain
(unless stated otherwise in the description of the configuration). That
toolchain selection can easily be reconfigured using 'make menuconfig'.
Here are the relevant current settings:
Build Setup:
CONFIG_HOST_WINDOWS=y : Microsoft Windows
CONFIG_WINDOWS_CYGWIN=y : Using Cygwin or other POSIX environment
System Type -> Toolchain:
CONFIG_ARMV7A_TOOLCHAIN_CODESOURCERYW=y : CodeSourcery for Windows
Configuration Sub-directories
-----------------------------
nsh:
This configuration directory provide the NuttShell (NSH). There are
STATUS:
Work in progress. Till now it is possible to pass arm_boot(), but Prefetch abort
is met when devnull_register() call is done. Have no idea why. I was able to trace
down to _inode_search() call. If I put any debug statement like "up_lowputc('0');"
right after "desc->node = node;" statement at line 425 the code does not crash.

136
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@ -0,0 +1,136 @@
/************************************************************************************
* configs/beaglebone-black/include/board.h
*
* Copyright (C) 2018 Petro Karashchenko. All rights reserved.
* Author: Petro Karashchenko <petro.karashchenko@gmail.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __CONFIGS_BEAGLEBONE_BLACK_INCLUDE_BOARD_H
#define __CONFIGS_BEAGLEBONE_BLACK_INCLUDE_BOARD_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
#include "chip/am335x_pinmux.h"
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* Clocking *************************************************************************/
/* Since NuttX is booted from a loader on the AM335X, clocking should already be setup
* when NuttX starts.
*/
/* LED definitions ******************************************************************/
/* The beaglebone black has four user LEDs; all four can be controlled from software.
* All are tied to ground and, hence, illuminated by driving the output pins to a high
* value:
*
* 1. LED0 GPMC_A5 GPMC_A5/GMII2_TXD0/RGMII2_TD0/RMII2_TXD0/GPMC_A21/PR1_MII1_RXD3/
* eQEP1B_IN/GPIO1_21
* 2. LED1 GPMC_A6 GPMC_A6/GMII2_TXCLK/RGMII2_TCLK/MMC2_DAT4/GPMC_A22/PR1_MII1_RXD2/
* eQEP1_INDEX/GPIO1_22
* 3. LED2 GPMC_A7 GPMC_A7/GMII2_RXCLK/RGMII2_RCLK/MMC2_DAT5/GPMC_A23/PR1_MII1_RXD1/
* eQEP1_STROBE/GPIO1_23
* 4. LED3 GPMC_A8 GPMC_A8/GMII2_RXD3/RGMII2_RD3/MMC2_DAT6/GPMC_A24/PR1_MII1_RXD0/
* MCASP0_ACLKX/GPIO1_24
*/
/* LED index values for use with board_userled() */
#define USER_LED0 0
#define USER_LED1 1
#define USER_LED2 2
#define USER_LED3 3
#define BOARD_NLEDS 4
/* LED bits for use with board_userled_all() */
#define BOARD_LED0_BIT (1 << USER_LED0)
#define BOARD_LED1_BIT (1 << USER_LED1)
#define BOARD_LED2_BIT (1 << USER_LED2)
#define BOARD_LED3_BIT (1 << USER_LED3)
/* These LEDs are not used by the board port unless CONFIG_ARCH_LEDS is
* defined. In that case, the usage by the board port is defined in
* include/board.h and src/am335x_leds.c. The LEDs are used to encode OS-related
* events as follows:
*
* SYMBOL Value Meaning LED state
* LED0 LED1 LED2
* ----------------- ----- ----------------------- ---- ---- ------------ */
#define LED_STARTED 0 /* NuttX has been started ON OFF OFF */
#define LED_HEAPALLOCATE 1 /* Heap has been allocated OFF ON OFF */
#define LED_IRQSENABLED 2 /* Interrupts enabled ON ON OFF */
#define LED_STACKCREATED 2 /* Idle stack created ON ON OFF */
#define LED_INIRQ 3 /* In an interrupt N/C N/C Soft glow */
#define LED_SIGNAL 3 /* In a signal handler N/C N/C Soft glow */
#define LED_ASSERTION 3 /* An assertion failed N/C N/C Soft glow */
#define LED_PANIC 3 /* The system has crashed N/C N/C 2Hz Flashing */
/* LED_IDLE --- /* MCU is is sleep mode Not used
*
* After booting, LED0 and 1 are not longer used by the system and can be used for
* other purposes by the application (Of course, all LEDs are available to the
* application if CONFIG_ARCH_LEDS is not defined.
*/
/* NAND *****************************************************************************/
/* GPIO pin disambiguation **********************************************************/
/* UARTs ****************************************************************************/
/* One UART connections is available:
*
* 1. UART0 is available on FT2232H USB to Serial Adapter.
*
* FT2232H BDBUS1 Pin UART0-RXD UART0_RXD/SPI1_CS0/DCAN0_TX/I2C2_SDA/
eCAP2_IN_PWM2_OUT/PR1_PRU1_PRU_R30_14/
* PR1_PRU1_PRU_R31_14/GPIO1_10
* FT2232H BDBUS0 Pin UART0-TXD UART0_TXD/SPI1_CS1/DCAN0_RX/I2C2_SCL/
* eCAP1_IN_PWM1_OUT/PR1_PRU1_PRU_R30_15/
* PR1_PRU1_PRU_R31_15/GPIO1_11
*/
/************************************************************************************
* Assembly Language Macros
************************************************************************************/
#ifdef __ASSEMBLY__
.macro config_sdram
.endm
#endif /* __ASSEMBLY__ */
#endif /* __CONFIGS_BEAGLEBONE_BLACK_INCLUDE_BOARD_H */

74
configs/beaglebone-black/include/board_memorymap.h Normal file
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@ -0,0 +1,74 @@
/************************************************************************************
* configs/beaglebone-black/include/board_memorymap.h
*
* Copyright (C) 2019 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __CONFIGS_BEAGLEBONE_BLACK_INCLUDE_BOARD_MEMORYMAP_H
#define __CONFIGS_BEAGLEBONE_BLACK_INCLUDE_BOARD_MEMORYMAP_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/************************************************************************************
* Public Data
************************************************************************************/
#ifndef __ASSEMBLY__
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/************************************************************************************
* Public Function Prototypes
************************************************************************************/
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __CONFIGS_BEAGLEBONE_BLACK_INCLUDE_BOARD_MEMORYMAP_H */

52
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@ -0,0 +1,52 @@
# CONFIG_NSH_CMDOPT_DF_H is not set
# CONFIG_NSH_CMDOPT_HEXDUMP is not set
# CONFIG_NSH_CMDPARMS is not set
# CONFIG_NSH_DISABLE_IFCONFIG is not set
# CONFIG_NSH_DISABLE_PS is not set
CONFIG_AM335X_UART0=y
CONFIG_ARCH_BOARD_BEAGLEBONE_BLACK=y
CONFIG_ARCH_BOARD="beaglebone-black"
CONFIG_ARCH_CHIP_AM3358=y
CONFIG_ARCH_CHIP_AM335X=y
CONFIG_ARCH_INTERRUPTSTACK=2048
CONFIG_ARCH_LOWVECTORS=y
CONFIG_ARCH_STACKDUMP=y
CONFIG_ARCH="arm"
CONFIG_BOARD_LOOPSPERMSEC=49341
CONFIG_BOOT_RUNFROMSDRAM=y
CONFIG_BUILTIN=y
CONFIG_DISABLE_ENVIRON=y
CONFIG_DISABLE_POLL=y
CONFIG_SYSTEM_NSH=y
CONFIG_SYSTEM_NSH_CXXINITIALIZE=y
CONFIG_FAT_LCNAMES=y
CONFIG_FAT_LFN=y
CONFIG_FS_FAT=y
CONFIG_HAVE_CXX=y
CONFIG_HAVE_CXXINITIALIZE=y
CONFIG_HOST_WINDOWS=y
CONFIG_INTELHEX_BINARY=y
CONFIG_MAX_TASKS=16
CONFIG_MAX_WDOGPARMS=2
CONFIG_NFILE_DESCRIPTORS=8
CONFIG_NFILE_STREAMS=8
CONFIG_NSH_BUILTIN_APPS=y
CONFIG_NSH_FILEIOSIZE=512
CONFIG_NSH_READLINE=y
CONFIG_PREALLOC_MQ_MSGS=4
CONFIG_PREALLOC_TIMERS=4
CONFIG_PREALLOC_WDOGS=16
CONFIG_RAM_SIZE=369098752
CONFIG_RAM_START=0x8a000000
CONFIG_RAM_VSTART=0x8a000000
CONFIG_RAW_BINARY=y
CONFIG_RR_INTERVAL=200
CONFIG_SCHED_WAITPID=y
CONFIG_SDCLONE_DISABLE=y
CONFIG_START_DAY=1
CONFIG_START_MONTH=4
CONFIG_START_YEAR=2015
CONFIG_SYMTAB_ORDEREDBYNAME=y
CONFIG_UART0_SERIAL_CONSOLE=y
CONFIG_USER_ENTRYPOINT="nsh_main"
CONFIG_WDOG_INTRESERVE=2

131
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@ -0,0 +1,131 @@
############################################################################
# configs/beaglebone-black/scripts/Make.defs
#
# Copyright (C) 2018 Petro Karashchenko. All rights reserved.
# Author: Petro Karashchenko <petro.karashchenko@gmail.com>
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions
# are met:
#
# 1. Redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer.
# 2. Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in
# the documentation and/or other materials provided with the
# distribution.
# 3. Neither the name NuttX nor the names of its contributors may be
# used to endorse or promote products derived from this software
# without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
# POSSIBILITY OF SUCH DAMAGE.
#
############################################################################
include ${TOPDIR}/.config
include ${TOPDIR}/tools/Config.mk
include ${TOPDIR}/arch/arm/src/armv7-a/Toolchain.defs
# Setup for the kind of memory that we are executing from
LDSCRIPT = sdram.ld
# Setup for Windows vs Linux/Cygwin/OSX environments
ifeq ($(WINTOOL),y)
# Windows-native toolchains
DIRLINK = $(TOPDIR)/tools/copydir.sh
DIRUNLINK = $(TOPDIR)/tools/unlink.sh
MKDEP = $(TOPDIR)/tools/mkwindeps.sh
ARCHINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}"
ARCHXXINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" -isystem "${shell cygpath -w $(TOPDIR)/include/cxx}"
ARCHSCRIPT = -T "${shell cygpath -w $(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT)}"
else
# Linux/Cygwin-native toolchain
MKDEP = $(TOPDIR)/tools/mkdeps$(HOSTEXEEXT)
ARCHINCLUDES = -I. -isystem $(TOPDIR)/include
ARCHXXINCLUDES = -I. -isystem $(TOPDIR)/include -isystem $(TOPDIR)/include/cxx
ARCHSCRIPT = -T$(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT)
endif
CC = $(CROSSDEV)gcc
CXX = $(CROSSDEV)g++
CPP = $(CROSSDEV)gcc -E
LD = $(CROSSDEV)ld
AR = $(ARCROSSDEV)ar rcs
NM = $(ARCROSSDEV)nm
OBJCOPY = $(CROSSDEV)objcopy
OBJDUMP = $(CROSSDEV)objdump
ARCHCCVERSION = ${shell $(CC) -v 2>&1 | sed -n '/^gcc version/p' | sed -e 's/^gcc version \([0-9\.]\)/\1/g' -e 's/[-\ ].*//g' -e '1q'}
ARCHCCMAJOR = ${shell echo $(ARCHCCVERSION) | cut -d'.' -f1}
ifeq ($(ARCHCCMAJOR),2)
OLDGCC = y
else ifeq ($(ARCHCCMAJOR),3)
OLDGCC = y
else
OLDGCC = n
endif
ifeq ($(CONFIG_DEBUG_SYMBOLS),y)
ARCHOPTIMIZATION = -g
endif
ifneq ($(CONFIG_DEBUG_NOOPT),y)
ARCHOPTIMIZATION += $(MAXOPTIMIZATION) -fno-strict-aliasing -fno-strength-reduce -fomit-frame-pointer
endif
ifeq ($(OLDGCC),n)
ARCHCPUFLAGS = -mcpu=cortex-a8 -mfpu=neon -mfloat-abi=softfp -ftree-vectorize
else
ARCHCPUFLAGS = -mapcs-32 -march=arm7-a -msoft-float
endif
ARCHCFLAGS = -fno-builtin
ARCHCXXFLAGS = -fno-builtin -fno-exceptions -fcheck-new -fno-rtti
ARCHWARNINGS = -Wall -Wstrict-prototypes -Wshadow -Wundef
ARCHWARNINGSXX = -Wall -Wshadow -Wundef
ARCHDEFINES =
ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10
CFLAGS = $(ARCHCFLAGS) $(ARCHWARNINGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe
CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS)
CXXFLAGS = $(ARCHCXXFLAGS) $(ARCHWARNINGSXX) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe
CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS)
CPPFLAGS = $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES)
AFLAGS = $(CFLAGS) -D__ASSEMBLY__
NXFLATLDFLAGS1 = -r -d -warn-common
NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections
LDNXFLATFLAGS = -e main -s 2048
ASMEXT = .S
OBJEXT = .o
LIBEXT = .a
EXEEXT =
ifneq ($(CROSSDEV),arm-nuttx-elf-)
LDFLAGS += -nostartfiles -nodefaultlibs
endif
ifeq ($(CONFIG_DEBUG_SYMBOLS),y)
LDFLAGS += -g
endif
HOSTCC = gcc
HOSTINCLUDES = -I.
HOSTCFLAGS = -Wall -Wstrict-prototypes -Wshadow -Wundef -g -pipe
HOSTLDFLAGS =

138
configs/beaglebone-black/scripts/sdram.ld Normal file
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/****************************************************************************
* configs/beaglebone-black/scripts/sdram.ld
*
* Copyright (C) 2018 Petro Karashchenko. All rights reserved.
* Author: Petro Karashchenko <petro.karashchenko@gmail.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/* The Beaglebone Black and 512MB of SDRAM beginning at virtual address
* 0x8000:0000. Execution begins at address 0x8a00000, leaving 352MB for NuttX.
*
* Vectors in low memory are assumed and 16KB of OCMC0 is reserved at the
* high end of OCMC0 for the page table.
*/
MEMORY
{
isram (W!RX) : ORIGIN = 0x402F0400, LENGTH = 63K
ocmc0 (W!RX) : ORIGIN = 0x40300000, LENGTH = 64K -16K
ddr (W!RX) : ORIGIN = 0x8a000000, LENGTH = 512M - 160M
}
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
OUTPUT_ARCH(arm)
ENTRY(entry)
ENTRY(_stext)
SECTIONS
{
.text :
{
_stext = ABSOLUTE(.);
*(.vectors)
*(.text .text.*)
*(.fixup)
*(.gnu.warning)
*(.rodata .rodata.*)
*(.gnu.linkonce.t.*)
*(.glue_7)
*(.glue_7t)
*(.got)
*(.gcc_except_table)
*(.gnu.linkonce.r.*)
*(.ARM.extab*)
*(.gnu.linkonce.armextab.*)
_etext = ABSOLUTE(.);
} > ddr
.init_section :
{
_sinit = ABSOLUTE(.);
*(.init_array .init_array.*)
_einit = ABSOLUTE(.);
} > ddr
.ARM.extab :
{
*(.ARM.extab*)
} > ddr
/* .ARM.exidx is sorted, so has to go in its own output section. */
PROVIDE_HIDDEN (__exidx_start = .);
.ARM.exidx :
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} > ddr
PROVIDE_HIDDEN (__exidx_end = .);
.data :
{
_sdata = ABSOLUTE(.);
*(.data .data.*)
*(.gnu.linkonce.d.*)
CONSTRUCTORS
_edata = ABSOLUTE(.);
} > ddr
.bss :
{
_sbss = ABSOLUTE(.);
*(.bss .bss.*)
*(.gnu.linkonce.b.*)
*(COMMON)
_ebss = ABSOLUTE(.);
} > ddr
/* Uninitialized data */
.noinit :
{
_snoinit = ABSOLUTE(.);
*(.noinit*)
_enoinit = ABSOLUTE(.);
} > ddr
/* Stabs debugging sections. */
.stab 0 : { *(.stab) }
.stabstr 0 : { *(.stabstr) }
.stab.excl 0 : { *(.stab.excl) }
.stab.exclstr 0 : { *(.stab.exclstr) }
.stab.index 0 : { *(.stab.index) }
.stab.indexstr 0 : { *(.stab.indexstr) }
.comment 0 : { *(.comment) }
.debug_abbrev 0 : { *(.debug_abbrev) }
.debug_info 0 : { *(.debug_info) }
.debug_line 0 : { *(.debug_line) }
.debug_pubnames 0 : { *(.debug_pubnames) }
.debug_aranges 0 : { *(.debug_aranges) }
}

53
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############################################################################
# configs/beaglebone-black/src/Makefile
#
# Copyright (C) 2018 Petro Karashchenko. All rights reserved.
# Author: Gregory Nutt <petro.karashchenko@gmail.com>
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions
# are met:
#
# 1. Redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer.
# 2. Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in
# the documentation and/or other materials provided with the
# distribution.
# 3. Neither the name NuttX nor the names of its contributors may be
# used to endorse or promote products derived from this software
# without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
# POSSIBILITY OF SUCH DAMAGE.
#
############################################################################
-include $(TOPDIR)/Make.defs
ASRCS =
CSRCS = am335x_boot.c am335x_leds.c
ifeq ($(CONFIG_LIB_BOARDCTL),y)
CSRCS += am355x_appinit.c
endif
ifeq ($(CONFIG_CAN),y)
CSRCS += am335x_can.c
endif
ifeq ($(CONFIG_ARCH_BUTTONS),y)
CSRCS += am335x_buttons.c
endif
include $(TOPDIR)/configs/Board.mk

128
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/************************************************************************************
* configs/beaglebone-black/src/am335x_boot.c
*
* Copyright (C) 2018 Petro Karashchenko. All rights reserved.
* Author: Petro Karashchenko <petro.karashchenko@gmail.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
#include <debug.h>
#include <nuttx/board.h>
#include "beaglebone-black.h"
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/************************************************************************************
* Private Functions
************************************************************************************/
/************************************************************************************
* Public Functions
************************************************************************************/
/****************************************************************************
* Name: am335x_memory_initialize
*
* Description:
* All AM335X architectures must provide the following entry point. This
* entry point is called early in the initialization before memory has
* been configured. This board-specific function is responsible for
* configuring any on-board memories.
*
* Logic in am335x_memory_initialize must be careful to avoid using any
* global variables because those will be uninitialized at the time this
* function is called.
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
void am335x_memory_initialize(void)
{
/* SDRAM was initialized by a bootloader in the supported configurations. */
}
/************************************************************************************
* Name: am335x_board_initialize
*
* Description:
* All AM335x architectures must provide the following entry point. This entry
* point is called early in the initialization -- after all memory has been
* configured and mapped but before any devices have been initialized.
*
************************************************************************************/
void am335x_board_initialize(void)
{
/* Configure on-board LEDs. */
am335x_led_initialize();
}
/****************************************************************************
* Name: board_initialize
*
* Description:
* If CONFIG_BOARD_INITIALIZE is selected, then an additional
* initialization call will be performed in the boot-up sequence to a
* function called board_initialize(). board_initialize() will be
* called immediately after up_initialize() is called and just before the
* initial application is started. This additional initialization phase
* may be used, for example, to initialize board-specific device drivers.
*
****************************************************************************/
#ifdef CONFIG_BOARD_INITIALIZE
void board_initialize(void)
{
#if defined(CONFIG_NSH_LIBRARY) && !defined(CONFIG_LIB_BOARDCTL)
/* Perform NSH initialization here instead of from the NSH. This
* alternative NSH initialization is necessary when NSH is ran in user-space
* but the initialization function must run in kernel space.
*/
(void)board_app_initialize(0);
#endif
}
#endif /* CONFIG_BOARD_INITIALIZE */

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/****************************************************************************
* configs/beaglebone-black/src/am335x_buttons.c
*
* Copyright (C) 2018 Petro Karashchenko. All rights reserved.
* Author: Petro Karashchenko <petro.karashchenko@gmail.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <errno.h>
#include <nuttx/arch.h>
#include <nuttx/board.h>
#include <nuttx/irq.h>
#include <nuttx/irq.h>
#include <arch/board/board.h>
#include "beaglebone-black.h"
#ifdef CONFIG_ARCH_BUTTONS
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: board_button_initialize
*
* Description:
* board_button_initialize() must be called to initialize button resources.
* After that, board_buttons() may be called to collect the current state
* of all buttons or board_button_irq() may be called to register button
* interrupt handlers.
*
****************************************************************************/
void board_button_initialize(void)
{
# warning Missing logic
}
/****************************************************************************
* Name: board_buttons
*
* Description:
* After board_button_initialize() has been called, board_buttons() may be
* called to collect the state of all buttons. board_buttons() returns an
* 32-bit bit set with each bit associated with a button. See the BUTTON*
* definitions above for the meaning of each bit in the returned value.
*
****************************************************************************/
uint32_t board_buttons(void)
{
# warning Missing logic
}
/****************************************************************************
* Name: board_button_irq
*
* Description:
* This function may be called to register an interrupt handler that will
* be called when a button is depressed or released. The ID value is one
* of the BUTTON* definitions provided above. The previous interrupt
* handler address isreturned (so that it may restored, if so desired).
*
* Configuration Notes:
* Configuration CONFIG_ARCH_IRQBUTTONS must be selected to enable the
* overall GPIO IRQ feature.
*
****************************************************************************/
#ifdef CONFIG_ARCH_IRQBUTTONS
int board_button_irq(int id, xcpt_t irqhandler, FAR void *arg)
{
int ret = -EINVAL;
if (id < BOARD_NBUTTONS)
{
irqstate_t flags;
/* Disable interrupts until we are done. This guarantees that the
* following operations are atomic.
*/
flags = enter_critical_section();
/* Configure the interrupt */
am335x_gpioirq(xxx);
(void)irq_attach(xxx, irqhandler, arg);
am335x_gpioirq_enable(xxx);
leave_critical_section(flags);
ret = OK;
}
return ret;
}
#endif
#endif /* CONFIG_ARCH_BUTTONS */

253
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/****************************************************************************
* configs/beaglebone-black/src/am335x_leds.c
*
* Copyright (C) 2018 Petro Karashchenko. All rights reserved.
* Author: Petro Karashchenko <petro.karashchenko@gmail.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <stdbool.h>
#include <debug.h>
#include <nuttx/board.h>
#include <arch/board/board.h>
#include "chip.h"
#include "up_arch.h"
#include "up_internal.h"
#include "beaglebone-black.h"
/* The beaglebone black has four user LEDs; all four can be controlled from
* software. All are tied to ground and, hence, illuminated by driving the
* output pins to a high value:
*
* 1. LED0 GPMC_A5 GPMC_A5/GMII2_TXD0/RGMII2_TD0/RMII2_TXD0/GPMC_A21/
* PR1_MII1_RXD3/eQEP1B_IN/GPIO1_21
* 2. LED1 GPMC_A6 GPMC_A6/GMII2_TXCLK/RGMII2_TCLK/MMC2_DAT4/GPMC_A22/
* PR1_MII1_RXD2/eQEP1_INDEX/GPIO1_22
* 3. LED2 GPMC_A7 GPMC_A7/GMII2_RXCLK/RGMII2_RCLK/MMC2_DAT5/GPMC_A23/
* PR1_MII1_RXD1/eQEP1_STROBE/GPIO1_23
* 4. LED3 GPMC_A8 GPMC_A8/GMII2_RXD3/RGMII2_RD3/MMC2_DAT6/GPMC_A24/
* PR1_MII1_RXD0/MCASP0_ACLKX/GPIO1_24
* These LEDs are not used by the board port unless CONFIG_ARCH_LEDS is
* defined. In that case, the usage by the board port is defined in
* include/board.h and src/am335x_leds.c. The LEDs are used to encode OS-
* related events as follows:
*
* SYMBOL Meaning LED state
* LED1 LED3 LED4
* ----------------- ----------------------- ---- ---- ---- ------------
* LED_STARTED NuttX has been started ON OFF OFF
* LED_HEAPALLOCATE Heap has been allocated OFF ON OFF
* LED_IRQSENABLED Interrupts enabled ON ON OFF
* LED_STACKCREATED Idle stack created ON ON OFF
* LED_INIRQ In an interrupt N/C N/C Soft glow
* LED_SIGNAL In a signal handler N/C N/C Soft glow
* LED_ASSERTION An assertion failed N/C N/C Soft glow
* LED_PANIC The system has crashed N/C N/C 2Hz Flashing
* LED_IDLE MCU is is sleep mode Not used
*
* After booting, LED0 and 1 are not longer used by the system and can be
* used for other purposes by the application (Of course, all LEDs are
* available to the application if CONFIG_ARCH_LEDS is not defined.
*/
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: am335x_led_initialize
*
* Description:
* Configure LEDs. LEDs are left in the OFF state.
*
****************************************************************************/
void am335x_led_initialize(void)
{
am335x_gpio_config(GPIO_LED0);
am335x_gpio_config(GPIO_LED1);
am335x_gpio_config(GPIO_LED2);
am335x_gpio_config(GPIO_LED3);
}
/****************************************************************************
* Name: board_autoled_on
*
* Description:
* Select the "logical" ON state:
*
* SYMBOL Value Meaning LED state
* LED1 LED3 LED4
* ----------------- ----- ----------------------- ---- ---- ------------
* LED_STARTED 0 NuttX has been started ON OFF OFF
* LED_HEAPALLOCATE 1 Heap has been allocated OFF ON OFF
* LED_IRQSENABLED 2 Interrupts enabled ON ON OFF
* LED_STACKCREATED 2 Idle stack created ON ON OFF
* LED_INIRQ 3 In an interrupt N/C N/C Soft glow
* LED_SIGNAL 3 In a signal handler N/C N/C Soft glow
* LED_ASSERTION 3 An assertion failed N/C N/C Soft glow
* LED_PANIC 3 The system has crashed N/C N/C 2Hz Flashing
* LED_IDLE --- MCU is is sleep mode Not used
*
* LED1 is illuminated by driving the output pins to a high value
* LED3 and LED 4 are illuminated by taking the output to ground.
*
****************************************************************************/
#ifdef CONFIG_ARCH_LEDS
void board_autoled_on(int led)
{
switch (led)
{
case 0:
am335x_gpio_write(GPIO_LED0, true);
am335x_gpio_write(GPIO_LED1, true);
am335x_gpio_write(GPIO_LED3, true);
break;
case 1:
am335x_gpio_write(GPIO_LED0, false);
am335x_gpio_write(GPIO_LED1, false);
am335x_gpio_write(GPIO_LED3, true);
break;
case 2:
am335x_gpio_write(GPIO_LED0, false);
am335x_gpio_write(GPIO_LED1, true);
am335x_gpio_write(GPIO_LED3, true);
break;
case 3:
am335x_gpio_write(GPIO_LED3, false);
break;
}
}
#endif
/****************************************************************************
* Name: board_autoled_off
*
* Description:
* Select the "logical" OFF state:
*
* SYMBOL Value Meaning LED state
* LED1 LED3 LED4
* ----------------- ----- ----------------------- ---- ---- ------------
* LED_STARTED 0 NuttX has been started ON OFF OFF
* LED_HEAPALLOCATE 1 Heap has been allocated OFF ON OFF
* LED_IRQSENABLED 2 Interrupts enabled ON ON OFF
* LED_STACKCREATED 2 Idle stack created ON ON OFF
* LED_INIRQ 3 In an interrupt N/C N/C Soft glow
* LED_SIGNAL 3 In a signal handler N/C N/C Soft glow
* LED_ASSERTION 3 An assertion failed N/C N/C Soft glow
* LED_PANIC 3 The system has crashed N/C N/C 2Hz Flashing
* LED_IDLE --- MCU is is sleep mode Not used
*
* LED1 is illuminated by driving the output pins to a high value
* LED3 and LED 4 are illuminated by taking the output to ground.
*
****************************************************************************/
#ifdef CONFIG_ARCH_LEDS
void board_autoled_off(int led)
{
switch (led)
{
case 0:
case 1:
case 2:
break;
case 3:
am335x_gpio_write(GPIO_LED3, true);
break;
}
}
#endif
/************************************************************************************
* Name: board_userled_initialize, board_userled, and board_userled_all
*
* Description:
* These interfaces allow user control of the board LEDs.
*
* If CONFIG_ARCH_LEDS is defined, then NuttX will control both on-board LEDs up
* until the completion of boot. The it will continue to control LED1; LED0 is
* available for application use.
*
* If CONFIG_ARCH_LEDS is not defined, then both LEDs are available for application
* use.
*
************************************************************************************/
void board_userled_initialize(void)
{
/* Initialization already performed in am335x_led_initialize */
}
void board_userled(int led, bool ledon)
{
switch (led)
{
case USER_LED0:
am335x_gpio_write(GPIO_LED0, ledon);
break;
case USER_LED1:
am335x_gpio_write(GPIO_LED1, ledon);
break;
#ifndef CONFIG_ARCH_LEDS
case USER_LED3:
am335x_gpio_write(GPIO_LED3, ledon);
break;
#endif
}
}
void board_userled_all(uint8_t ledset)
{
board_userled(USER_LED0, (ledset & USER_LED0) != 0);
board_userled(USER_LED1, (ledset & USER_LED1) != 0);
#ifndef CONFIG_ARCH_LEDS
board_userled(USER_LED3, (ledset & USER_LED3) != 0);
#endif
}

131
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/************************************************************************************
* configs/beaglebone-black/src/beaglebone-black.h
*
* Copyright (C) 2018 Petro Karashchenko. All rights reserved.
* Author: Petro Karashchenko <petro.karashchenko@gmail.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __CONFIGS_BEAGLEBONE_BLACK_SRC_BEAGLEBONE_BLACK_H
#define __CONFIGS_BEAGLEBONE_BLACK_SRC_BEAGLEBONE_BLACK_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
#include <nuttx/compiler.h>
#include <stdint.h>
#include <arch/irq.h>
#include <nuttx/irq.h>
#include "am335x_gpio.h"
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* Configuration ********************************************************************/
/* LEDs *****************************************************************************/
/* The beaglebone black has four user LEDs; all four can be controlled from software.
* All are tied to ground and, hence, illuminated by driving the output pins to a
* high value:
*
* 1. LED0 GPMC_A5 GPMC_A5/GMII2_TXD0/RGMII2_TD0/RMII2_TXD0/GPMC_A21/PR1_MII1_RXD3/
* eQEP1B_IN/GPIO1_21
* 2. LED1 GPMC_A6 GPMC_A6/GMII2_TXCLK/RGMII2_TCLK/MMC2_DAT4/GPMC_A22/PR1_MII1_RXD2/
* eQEP1_INDEX/GPIO1_22
* 3. LED2 GPMC_A7 GPMC_A7/GMII2_RXCLK/RGMII2_RCLK/MMC2_DAT5/GPMC_A23/PR1_MII1_RXD1/
* eQEP1_STROBE/GPIO1_23
* 4. LED3 GPMC_A8 GPMC_A8/GMII2_RXD3/RGMII2_RD3/MMC2_DAT6/GPMC_A24/PR1_MII1_RXD0/
* MCASP0_ACLKX/GPIO1_24
*/
#define GPIO_LED0 (GPIO_OUTPUT | GPIO_OUTPUT_ZERO | GPIO_PORT1 | GPIO_PIN21 | \
GPIO_PADCTL(AM335X_PADCTL_GPMC_A5_INDEX))
#define GPIO_LED1 (GPIO_OUTPUT | GPIO_OUTPUT_ZERO | GPIO_PORT1 | GPIO_PIN22 | \
GPIO_PADCTL(AM335X_PADCTL_GPMC_A6_INDEX))
#define GPIO_LED2 (GPIO_OUTPUT | GPIO_OUTPUT_ZERO | GPIO_PORT1 | GPIO_PIN23 | \
GPIO_PADCTL(AM335X_PADCTL_GPMC_A7_INDEX))
#define GPIO_LED3 (GPIO_OUTPUT | GPIO_OUTPUT_ZERO | GPIO_PORT1 | GPIO_PIN24 | \
GPIO_PADCTL(AM335X_PADCTL_GPMC_A8_INDEX))
/* These LEDs are not used by the board port unless CONFIG_ARCH_LEDS is
* defined. In that case, the usage by the board port is defined in
* include/board.h and src/am335x_leds.c. The LEDs are used to encode OS-related
* events as follows:
*
* SYMBOL Meaning LED state
* LED1 LED3 LED4
* ----------------- ----------------------- ---- ---- ---- ------------
* LED_STARTED NuttX has been started ON OFF OFF
* LED_HEAPALLOCATE Heap has been allocated OFF ON OFF
* LED_IRQSENABLED Interrupts enabled ON ON OFF
* LED_STACKCREATED Idle stack created ON ON OFF
* LED_INIRQ In an interrupt N/C N/C Soft glow
* LED_SIGNAL In a signal handler N/C N/C Soft glow
* LED_ASSERTION An assertion failed N/C N/C Soft glow
* LED_PANIC The system has crashed N/C N/C 2Hz Flashing
* LED_IDLE MCU is is sleep mode Not used
*
* After booting, LED1 and 3 are not longer used by the system and can be used for
* other purposes by the application (Of course, all LEDs are available to the
* application if CONFIG_ARCH_LEDS is not defined.
*/
/************************************************************************************
* Public Types
************************************************************************************/
/************************************************************************************
* Public data
************************************************************************************/
#ifndef __ASSEMBLY__
/************************************************************************************
* Public Functions
************************************************************************************/
/****************************************************************************
* Name: am355x_led_initialize
*
* Description:
* Configure LEDs. LEDs are left in the OFF state.
*
****************************************************************************/
void am335x_led_initialize(void);
#endif /* __ASSEMBLY__ */
#endif /* __CONFIGS_BEAGLEBONE_BLACK_SRC_BEAGLEBONE_BLACK_H */