forked from nuttx/nuttx-update
Support RP2040 Clock Outputs
This commit is contained in:
Adam Comley
Xiang Xiao
parent
3594e3e541
commit
399cd88e7f
5 changed files with 350 additions and 4 deletions
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@ -23,6 +23,7 @@ USB
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PIO RP2040 Programmable I/O
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IRQs
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DMA
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Clock Output
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ws2812 Smart pixels (e.g. Neopixel)
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Flash ROM Boot
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SRAM Boot If Pico SDK is available a nuttx.uf2 file will be created
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@ -663,6 +663,218 @@ endif # ADC
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endif # RP2040_ADC
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#####################################################################
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# CLK_GPOUT Configuration
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#####################################################################
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menuconfig RP2040_CLK_GPOUT_ENABLE
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bool "Enable Clock Outputs"
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default n
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if RP2040_CLK_GPOUT_ENABLE
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config RP2040_CLK_GPOUT0
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bool "CLK_GPOUT0 Clock Output (pin 21)"
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default n
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---help---
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Enable CLK_GPOUT0
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if RP2040_CLK_GPOUT0
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choice
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prompt "Source Clock"
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config RP2040_CLK_GPOUT0_SRC_REF
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bool "REF (6 - 12 MHz)"
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---help---
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Reference clock that is always running unless in DORMANT mode. Runs from
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Ring Oscillator (ROSC) at power-up but can be switched to Crystal
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Oscillator (XOSC) for more accuracy.
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config RP2040_CLK_GPOUT0_SRC_SYS
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bool "SYS (125 MHz)"
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---help---
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System clock that is always running unless in DORMANT mode. Runs from
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clk_ref at power-up but is typically switched to a PLL.
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config RP2040_CLK_GPOUT0_SRC_USB
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bool "USB (48 MHz)"
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---help---
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USB reference clock. Must be 48MHz.
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config RP2040_CLK_GPOUT0_SRC_ADC
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bool "ADC (48 MHz)"
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---help---
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ADC reference clock. Must be 48MHz.
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config RP2040_CLK_GPOUT0_SRC_RTC
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bool "RTC (46875 Hz)"
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---help---
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RTC reference clock. The RTC divides this clock to generate a 1 second reference.
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endchoice
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config RP2040_CLK_GPOUT0_DIVINT
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int "Divisor (Integer)"
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default 1
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config RP2040_CLK_GPOUT0_DIVFRAC
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int "Divisor (Fractional)"
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default 0
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endif # RP2040_CLK_GPOUT0
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config RP2040_CLK_GPOUT1
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bool "CLK_GPOUT1 Clock Output (pin 23)"
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default n
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---help---
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Enable CLK_GPOUT1
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if RP2040_CLK_GPOUT1
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choice
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prompt "Source Clock"
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config RP2040_CLK_GPOUT1_SRC_REF
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bool "REF (6 - 12 MHz)"
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---help---
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Reference clock that is always running unless in DORMANT mode. Runs from
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Ring Oscillator (ROSC) at power-up but can be switched to Crystal
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Oscillator (XOSC) for more accuracy.
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config RP2040_CLK_GPOUT1_SRC_SYS
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bool "SYS (125 MHz)"
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---help---
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System clock that is always running unless in DORMANT mode. Runs from
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clk_ref at power-up but is typically switched to a PLL.
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config RP2040_CLK_GPOUT1_SRC_USB
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bool "USB (48 MHz)"
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---help---
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USB reference clock. Must be 48MHz.
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config RP2040_CLK_GPOUT1_SRC_ADC
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bool "ADC (48 MHz)"
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---help---
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ADC reference clock. Must be 48MHz.
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config RP2040_CLK_GPOUT1_SRC_RTC
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bool "RTC (46875 Hz)"
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---help---
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RTC reference clock. The RTC divides this clock to generate a 1 second reference.
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endchoice
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config RP2040_CLK_GPOUT1_DIVINT
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int "Divisor (Integer)"
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default 1
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config RP2040_CLK_GPOUT1_DIVFRAC
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int "Divisor (Fractional)"
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default 0
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endif # RP2040_CLK_GPOUT1
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config RP2040_CLK_GPOUT2
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bool "CLK_GPOUT2 Clock Output (pin 24)"
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default n
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---help---
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Enable CLK_GPOUT2
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if RP2040_CLK_GPOUT2
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choice
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prompt "Source Clock"
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config RP2040_CLK_GPOUT2_SRC_REF
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bool "REF (6 - 12 MHz)"
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---help---
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Reference clock that is always running unless in DORMANT mode. Runs from
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Ring Oscillator (ROSC) at power-up but can be switched to Crystal
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Oscillator (XOSC) for more accuracy.
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config RP2040_CLK_GPOUT2_SRC_SYS
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bool "SYS (125 MHz)"
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---help---
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System clock that is always running unless in DORMANT mode. Runs from
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clk_ref at power-up but is typically switched to a PLL.
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config RP2040_CLK_GPOUT2_SRC_USB
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bool "USB (48 MHz)"
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---help---
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USB reference clock. Must be 48MHz.
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config RP2040_CLK_GPOUT2_SRC_ADC
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bool "ADC (48 MHz)"
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---help---
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ADC reference clock. Must be 48MHz.
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config RP2040_CLK_GPOUT2_SRC_RTC
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bool "RTC (46875 Hz)"
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---help---
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RTC reference clock. The RTC divides this clock to generate a 1 second reference.
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endchoice
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config RP2040_CLK_GPOUT2_DIVINT
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int "Divisor (Integer)"
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default 1
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config RP2040_CLK_GPOUT2_DIVFRAC
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int "Divisor (Fractional)"
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default 0
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endif # RP2040_CLK_GPOUT2
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config RP2040_CLK_GPOUT3
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bool "CLK_GPOUT3 Clock Output (pin 25)"
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default n
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---help---
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Enable CLK_GPOUT3
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if RP2040_CLK_GPOUT3
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choice
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prompt "Source Clock"
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config RP2040_CLK_GPOUT3_SRC_REF
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bool "REF (6 - 12 MHz)"
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---help---
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Reference clock that is always running unless in DORMANT mode. Runs from
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Ring Oscillator (ROSC) at power-up but can be switched to Crystal
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Oscillator (XOSC) for more accuracy.
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config RP2040_CLK_GPOUT3_SRC_SYS
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bool "SYS (125 MHz)"
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---help---
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System clock that is always running unless in DORMANT mode. Runs from
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clk_ref at power-up but is typically switched to a PLL.
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config RP2040_CLK_GPOUT3_SRC_USB
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bool "USB (48 MHz)"
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---help---
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USB reference clock. Must be 48MHz.
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config RP2040_CLK_GPOUT3_SRC_ADC
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bool "ADC (48 MHz)"
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---help---
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ADC reference clock. Must be 48MHz.
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config RP2040_CLK_GPOUT3_SRC_RTC
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bool "RTC (46875 Hz)"
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---help---
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RTC reference clock. The RTC divides this clock to generate a 1 second reference.
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endchoice
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config RP2040_CLK_GPOUT3_DIVINT
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int "Divisor (Integer)"
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default 1
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config RP2040_CLK_GPOUT3_DIVFRAC
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int "Divisor (Fractional)"
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default 0
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endif # RP2040_CLK_GPOUT3
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endif # RP2040_CLK_GPOUT_ENABLE
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#####################################################################
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# WS2812 Configuration
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#####################################################################
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@ -81,6 +81,30 @@ static inline bool has_glitchless_mux(int clk_index)
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clk_index == RP2040_CLOCKS_NDX_REF;
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}
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#if defined(CONFIG_RP2040_CLK_GPOUT_ENABLE)
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static bool rp2040_clock_configure_gpout(int clk_index,
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uint32_t src,
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uint32_t div_int,
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uint32_t div_frac)
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{
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if (clk_index > RP2040_CLOCKS_NDX_GPOUT3 ||
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clk_index < RP2040_CLOCKS_NDX_GPOUT0 ||
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(src >> RP2040_CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_SHIFT) > 0xa)
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{
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return false;
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}
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putreg32((div_int << RP2040_CLOCKS_CLK_GPOUT0_DIV_INT_SHIFT) |
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(div_frac & RP2040_CLOCKS_CLK_GPOUT0_DIV_FRAC_MASK),
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(RP2040_CLOCKS_CLK_NDX_DIV(clk_index)));
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putreg32((src << RP2040_CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_SHIFT) |
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RP2040_CLOCKS_CLK_GPOUT0_CTRL_ENABLE,
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(RP2040_CLOCKS_CLK_NDX_CTRL(clk_index)));
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return true;
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}
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#endif
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bool rp2040_clock_configure(int clk_index,
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uint32_t src, uint32_t auxsrc,
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uint32_t src_freq, uint32_t freq)
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@ -274,6 +298,91 @@ void clocks_init(void)
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RP2040_CLOCKS_CLK_PERI_CTRL_AUXSRC_CLK_SYS,
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BOARD_SYS_FREQ,
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BOARD_PERI_FREQ);
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#if defined(CONFIG_RP2040_CLK_GPOUT_ENABLE)
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uint32_t src;
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#if defined(CONFIG_RP2040_CLK_GPOUT0)
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#if defined(CONFIG_RP2040_CLK_GPOUT0_SRC_REF)
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src = RP2040_CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_CLK_REF;
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#elif defined(CONFIG_RP2040_CLK_GPOUT0_SRC_SYS)
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src = RP2040_CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_CLK_SYS;
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#elif defined(CONFIG_RP2040_CLK_GPOUT0_SRC_USB)
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src = RP2040_CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_CLK_USB;
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#elif defined(CONFIG_RP2040_CLK_GPOUT0_SRC_ADC)
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src = RP2040_CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_CLK_ADC;
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#elif defined(CONFIG_RP2040_CLK_GPOUT0_SRC_RTC)
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src = RP2040_CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_CLK_RTC;
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#else
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src = 0;
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#endif
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rp2040_clock_configure_gpout(RP2040_CLOCKS_NDX_GPOUT0,
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src,
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CONFIG_RP2040_CLK_GPOUT0_DIVINT,
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CONFIG_RP2040_CLK_GPOUT0_DIVFRAC);
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#endif
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#if defined(CONFIG_RP2040_CLK_GPOUT1)
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#if defined(CONFIG_RP2040_CLK_GPOUT1_SRC_REF)
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src = RP2040_CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_CLK_REF;
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#elif defined(CONFIG_RP2040_CLK_GPOUT1_SRC_SYS)
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src = RP2040_CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_CLK_SYS;
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#elif defined(CONFIG_RP2040_CLK_GPOUT1_SRC_USB)
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src = RP2040_CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_CLK_USB;
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#elif defined(CONFIG_RP2040_CLK_GPOUT1_SRC_ADC)
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src = RP2040_CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_CLK_ADC;
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#elif defined(CONFIG_RP2040_CLK_GPOUT1_SRC_RTC)
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src = RP2040_CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_CLK_RTC;
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#else
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src = 0;
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#endif
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rp2040_clock_configure_gpout(RP2040_CLOCKS_NDX_GPOUT1,
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src,
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CONFIG_RP2040_CLK_GPOUT1_DIVINT,
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CONFIG_RP2040_CLK_GPOUT1_DIVFRAC);
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#endif
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#if defined(CONFIG_RP2040_CLK_GPOUT2)
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#if defined(CONFIG_RP2040_CLK_GPOUT2_SRC_REF)
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src = RP2040_CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_CLK_REF;
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#elif defined(CONFIG_RP2040_CLK_GPOUT2_SRC_SYS)
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src = RP2040_CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_CLK_SYS;
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#elif defined(CONFIG_RP2040_CLK_GPOUT2_SRC_USB)
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src = RP2040_CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_CLK_USB;
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#elif defined(CONFIG_RP2040_CLK_GPOUT2_SRC_ADC)
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src = RP2040_CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_CLK_ADC;
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#elif defined(CONFIG_RP2040_CLK_GPOUT2_SRC_RTC)
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src = RP2040_CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_CLK_RTC;
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#else
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src = 0;
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#endif
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rp2040_clock_configure_gpout(RP2040_CLOCKS_NDX_GPOUT2,
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src,
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CONFIG_RP2040_CLK_GPOUT2_DIVINT,
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CONFIG_RP2040_CLK_GPOUT2_DIVFRAC);
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#endif
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#if defined(CONFIG_RP2040_CLK_GPOUT3)
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#if defined(CONFIG_RP2040_CLK_GPOUT3_SRC_REF)
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src = RP2040_CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_CLK_REF;
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#elif defined(CONFIG_RP2040_CLK_GPOUT3_SRC_SYS)
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src = RP2040_CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_CLK_SYS;
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#elif defined(CONFIG_RP2040_CLK_GPOUT3_SRC_USB)
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src = RP2040_CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_CLK_USB;
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#elif defined(CONFIG_RP2040_CLK_GPOUT3_SRC_ADC)
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src = RP2040_CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_CLK_ADC;
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#elif defined(CONFIG_RP2040_CLK_GPOUT3_SRC_RTC)
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src = RP2040_CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_CLK_RTC;
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#else
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src = 0;
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#endif
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rp2040_clock_configure_gpout(RP2040_CLOCKS_NDX_GPOUT3,
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src,
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CONFIG_RP2040_CLK_GPOUT3_DIVINT,
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CONFIG_RP2040_CLK_GPOUT3_DIVFRAC);
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#endif
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#endif
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}
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/****************************************************************************
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@ -55,12 +55,19 @@
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#define RP2040_GPIO_FUNC_USB RP2040_IO_BANK0_GPIO_CTRL_FUNCSEL_USB
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#define RP2040_GPIO_FUNC_NULL RP2040_IO_BANK0_GPIO_CTRL_FUNCSEL_NULL
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/* GPIO function pins *******************************************************/
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#define RP2040_GPIO_PIN_CLK_GPOUT0 (21)
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#define RP2040_GPIO_PIN_CLK_GPOUT1 (23)
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#define RP2040_GPIO_PIN_CLK_GPOUT2 (24)
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#define RP2040_GPIO_PIN_CLK_GPOUT3 (25)
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/* GPIO interrupt modes *****************************************************/
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#define RP2040_GPIO_INTR_LEVEL_LOW 0
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#define RP2040_GPIO_INTR_LEVEL_HIGH 1
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#define RP2040_GPIO_INTR_EDGE_LOW 2
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#define RP2040_GPIO_INTR_EDGE_HIGH 3
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#define RP2040_GPIO_INTR_LEVEL_LOW 0
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#define RP2040_GPIO_INTR_LEVEL_HIGH 1
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#define RP2040_GPIO_INTR_EDGE_LOW 2
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#define RP2040_GPIO_INTR_EDGE_HIGH 3
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/****************************************************************************
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* Public Types
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@ -94,6 +94,23 @@ void rp2040_common_earlyinitialize(void)
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RP2040_GPIO_FUNC_UART); /* RTS */
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#endif
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#endif
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#if defined(CONFIG_RP2040_CLK_GPOUT0)
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rp2040_gpio_set_function(RP2040_GPIO_PIN_CLK_GPOUT0,
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RP2040_GPIO_FUNC_CLOCKS);
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#endif
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#if defined(CONFIG_RP2040_CLK_GPOUT1)
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rp2040_gpio_set_function(RP2040_GPIO_PIN_CLK_GPOUT1,
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RP2040_GPIO_FUNC_CLOCKS);
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#endif
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#if defined(CONFIG_RP2040_CLK_GPOUT2)
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rp2040_gpio_set_function(RP2040_GPIO_PIN_CLK_GPOUT2,
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RP2040_GPIO_FUNC_CLOCKS);
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#endif
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#if defined(CONFIG_RP2040_CLK_GPOUT3)
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rp2040_gpio_set_function(RP2040_GPIO_PIN_CLK_GPOUT3,
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RP2040_GPIO_FUNC_CLOCKS);
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#endif
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}
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/****************************************************************************
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