lupyuen/local-nuttx-update
1
0
Fork 0
forked from nuttx/nuttx-update
Code Pull requests Activity

drivers/coresight:Add caps member to coresight_desc_s for etr

Browse source 
Add caps member to coresight_desc_s for etr and fix etr compilation error

Signed-off-by: chenzhijia <chenzhijia@xiaomi.com>
This commit is contained in:
chenzhijia 2024-07-11 11:33:11 +08:00 committed by Xiang Xiao
parent 49ad5e05d5
commit 48a5419005
5 changed files with 31 additions and 25 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

1
drivers/coresight/coresight_tmc_core.c
View file

@ -143,6 +143,7 @@ tmc_register(FAR const struct coresight_desc_s *desc)
}
tmc_init_arch_data(tmcdev, desc);
tmcdev->caps = desc->caps;
switch (tmcdev->config_type)
{

23
drivers/coresight/coresight_tmc_core.h
View file

@ -120,29 +120,6 @@
#define TMC_DEVID_AXIAW_SHIFT 17
#define TMC_DEVID_AXIAW_MASK 0x7f
/* TMC ETR Capability bit definitions. These need to be set by software. */
#define TMC_ETR_SG (0x1U << 0)
/* ETR has separate read/write cache encodings. */
#define TMC_ETR_AXI_ARCACHE (0x1U << 1)
/* TMC_ETR_SAVE_RESTORE - Values of RRP/RWP/STS.Full are
* retained when TMC leaves Disabled state, allowing us to continue
* the tracing from a point where we stopped. This also implies that
* the RRP/RWP/STS.Full should always be programmed to the correct
* value. Unfortunately this is not advertised by the hardware,
* so we have to rely on PID of the IP to detect the functionality.
*/
#define TMC_ETR_SAVE_RESTORE (0x1U << 2)
/* Coresight SoC-600 TMC-ETR unadvertised capabilities */
#define TMC_600_ETR_CAPS \
(TMC_ETR_SAVE_RESTORE | TMC_ETR_AXI_ARCACHE)
#define TMC_MAX_NAME_LEN 32
/****************************************************************************

4
drivers/coresight/coresight_tmc_etr.c
View file

@ -125,11 +125,11 @@ static int tmc_etr_hw_enable(FAR struct coresight_tmc_dev_s *tmcdev)
if (tmcdev->caps & TMC_ETR_SAVE_RESTORE)
{
coresight_put32((uint32_t)tmcdev->buf, tmcdev->csdev.addr + TMC_RRP);
coresight_put32((uintptr_t)tmcdev->buf, tmcdev->csdev.addr + TMC_RRP);
coresight_put32(((uint64_t)(uintptr_t)tmcdev->buf >> 32),
tmcdev->csdev.addr + TMC_RRPHI);
coresight_put32((uint32_t)tmcdev->buf, tmcdev->csdev.addr + TMC_RWP);
coresight_put32((uintptr_t)tmcdev->buf, tmcdev->csdev.addr + TMC_RWP);
coresight_put32(((uint64_t)(uintptr_t)tmcdev->buf >> 32),
tmcdev->csdev.addr + TMC_RWPHI);

1
include/nuttx/coresight/coresight.h
View file

@ -151,6 +151,7 @@ struct coresight_desc_s
uint32_t buffer_size;
uint32_t burst_size;
uint32_t caps;
/* Description of outports of current device. */

27
include/nuttx/coresight/coresight_tmc.h
View file

@ -30,6 +30,33 @@
#include <nuttx/mutex.h>
#include <nuttx/coresight/coresight.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* TMC ETR Capability bit definitions. These need to be set by software. */
#define TMC_ETR_SG (0x1U << 0)
/* ETR has separate read/write cache encodings. */
#define TMC_ETR_AXI_ARCACHE (0x1U << 1)
/* TMC_ETR_SAVE_RESTORE - Values of RRP/RWP/STS.Full are
* retained when TMC leaves Disabled state, allowing us to continue
* the tracing from a point where we stopped. This also implies that
* the RRP/RWP/STS.Full should always be programmed to the correct
* value. Unfortunately this is not advertised by the hardware,
* so we have to rely on PID of the IP to detect the functionality.
*/
#define TMC_ETR_SAVE_RESTORE (0x1U << 2)
/* Coresight SoC-600 TMC-ETR unadvertised capabilities */
#define TMC_600_ETR_CAPS \
(TMC_ETR_SAVE_RESTORE | TMC_ETR_AXI_ARCACHE)
/****************************************************************************
* Public Types
****************************************************************************/