lupyuen/local-nuttx-update
1
0
Fork 0
forked from nuttx/nuttx-update
Code Pull requests Activity

refine driver

Browse source 
Signed-off-by: Peter Bee <pbjd97@gmail.com>
This commit is contained in:
Peter Bee 2024-10-21 19:52:32 +08:00 committed by Alan C. Assis
parent dac3f315a1
commit 48ded21e30
262 changed files with 32424 additions and 140253 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

114
arch/arm/include/rp23xx/i2c_slave.h Normal file
View file

@ -0,0 +1,114 @@
/****************************************************************************
* arch/arm/include/rp23xx/i2c_slave.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_INCLUDE_RP23XX_I2C_SLAVE_H
#define __ARCH_ARM_INCLUDE_RP23XX_I2C_SLAVE_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <nuttx/i2c/i2c_slave.h>
#ifndef __ASSEMBLY__
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/* There is no driver for I2C slave operations. To create an I2C slave,
* include this file (as: <arch/chip/i2c_slave.h>) and use either
* rp23xx_i2c0_slave_initialize or rp23xx_i2c1_slave_initialize to
* initialize the I2C for slave operations.
*/
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: rp23xx_i2c0_slave_initialize
*
* Description:
* Initialize I2C controller zero for slave operation, and return a pointer
* to the instance of struct i2c_slave_s. This function should only be
* called once of a give controller.
*
* Note: the same port cannot be initalized as both master and slave.
*
* Input Parameters:
* rx_buffer - Buffer for data transmitted to us by an I2C master.
* rx_buffer_len - Length of rx_buffer.
* callback - Callback function called when messages are received.
*
* Returned Value:
* Valid I2C device structure reference on success; a NULL on failure
*
****************************************************************************/
#ifdef CONFIG_RP23XX_I2C0_SLAVE
struct i2c_slave_s *rp23xx_i2c0_slave_initialize
(uint8_t *rx_buffer,
size_t rx_buffer_len,
i2c_slave_callback_t *callback);
#endif
/****************************************************************************
* Name: rp23xx_i2c1_slave_initialize
*
* Description:
* Initialize I2C controller zero for slave operation, and return a pointer
* to the instance of struct i2c_slave_s. This function should only be
* called once of a give controller.
*
* Note: the same port cannot be initalized as both master and slave.
*
* Input Parameters:
* rx_buffer - Buffer for data transmitted to us by an I2C master.
* rx_buffer_len - Length of rx_buffer.
* callback - Callback function called when messages are received.
*
* Returned Value:
* Valid I2C device structure reference on success; a NULL on failure
*
****************************************************************************/
#ifdef CONFIG_RP23XX_I2C1_SLAVE
struct i2c_slave_s *rp23xx_i2c1_slave_initialize
(uint8_t *rx_buffer,
size_t rx_buffer_len,
i2c_slave_callback_t *callback);
#endif
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_INCLUDE_RP23XX_I2C_SLAVE_H */

95
arch/arm/include/rp23xx/watchdog.h Normal file
View file

@ -0,0 +1,95 @@
/****************************************************************************
* arch/arm/include/rp23xx/watchdog.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_INCLUDE_RP23XX_WATCHDOG_H
#define __ARCH_ARM_INCLUDE_RP23XX_WATCHDOG_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <nuttx/timers/watchdog.h>
#ifndef __ASSEMBLY__
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
#ifdef CONFIG_WATCHDOG
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* IOCTL Commands ***********************************************************/
/* The watchdog driver uses a standard character driver framework. However,
* since the watchdog driver is a device control interface and not a data
* transfer interface, the majority of the functionality is implemented in
* driver ioctl calls.
*
* See nuttx/timers/watchdog.h for the IOCTLs handled by the upper half.
*
* These are detected and handled by the "lower half" watchdog timer driver.
*
* WDIOC_SET_SCRATCHn - save a 32-bit "arg" value in a scratch register
* that will be preserved over soft resets. A hard
* reset sets all scratch values to zero.
*
* WDIOC_GET_SCRATCHn - fetch a 32-bit value from a scratch register
* into a uint32_t pointed to by "arg".
*/
#define WDIOC_SET_SCRATCH0 _WDIOC(0x180)
#define WDIOC_SET_SCRATCH1 _WDIOC(0x181)
#define WDIOC_SET_SCRATCH2 _WDIOC(0x182)
#define WDIOC_SET_SCRATCH3 _WDIOC(0x183)
#define WDIOC_SET_SCRATCH4 _WDIOC(0x184)
#define WDIOC_SET_SCRATCH5 _WDIOC(0x185)
#define WDIOC_SET_SCRATCH6 _WDIOC(0x186)
#define WDIOC_SET_SCRATCH7 _WDIOC(0x187)
#define WDIOC_SET_SCRATCH(n) _WDIOC(0x180 + (n))
#define WDIOC_GET_SCRATCH0 _WDIOC(0x1f0)
#define WDIOC_GET_SCRATCH1 _WDIOC(0x1f1)
#define WDIOC_GET_SCRATCH2 _WDIOC(0x1f2)
#define WDIOC_GET_SCRATCH3 _WDIOC(0x1f3)
#define WDIOC_GET_SCRATCH4 _WDIOC(0x1f4)
#define WDIOC_GET_SCRATCH5 _WDIOC(0x1f5)
#define WDIOC_GET_SCRATCH6 _WDIOC(0x1f6)
#define WDIOC_GET_SCRATCH7 _WDIOC(0x1f7)
#define WDIOC_GET_SCRATCH(n) _WDIOC(0x1f0 + (n))
#endif /* CONFIG_WATCHDOG */
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_INCLUDE_RP23XX_WATCHDOG_H */

3
arch/arm/include/spinlock.h
View file

@ -117,7 +117,8 @@ typedef uint8_t spinlock_t;
#if defined(CONFIG_ARCH_HAVE_TESTSET) \
&& !defined(CONFIG_ARCH_CHIP_LC823450) \
&& !defined(CONFIG_ARCH_CHIP_CXD56XX) \
&& !defined(CONFIG_ARCH_CHIP_RP2040)
&& !defined(CONFIG_ARCH_CHIP_RP2040) \
&& !defined(CONFIG_ARCH_CHIP_RP23XX)
static inline_function spinlock_t up_testset(volatile spinlock_t *lock)
{
spinlock_t ret = SP_UNLOCKED;

2
arch/arm/src/rp2040/Kconfig
View file

@ -578,7 +578,7 @@ config RP2040_I2S_PIO_SM
endif # RP2040_I2S
#####################################################################
# I2S Configuration
# SPISD Configuration
#####################################################################
config RP2040_SPISD

2
arch/arm/src/rp2040/hardware/rp2040_dma.h
View file

@ -85,7 +85,7 @@
#define RP2040_DMA_CHAN_ABORT_OFFSET 0x000444 /* Abort an in-progress transfer sequence on one or more channels */
#define RP2040_DMA_N_CHANNELS_OFFSET 0x000448 /* The number of channels this DMA instance is equipped with. This DMA supports up to 16 hardware channels, but can be configured with as few as one, to minimise silicon area. */
#define RP2040_DMA_DBG_CTDREQ_OFFSET(n) (0x000800 + (n) * 0x0040)
#define RP2040_DMA_DBG_TCR_OFFSET (0x000804 + (n) * 0x0040)
#define RP2040_DMA_DBG_TCR_OFFSET(n) (0x000804 + (n) * 0x0040)
/* Register definitions *****************************************************/

8
arch/arm/src/rp2040/hardware/rp2040_pio.h
View file

@ -108,15 +108,7 @@
#define RP2040_PIO_FDEBUG(n) (RP2040_PIO_BASE(n) + RP2040_PIO_FDEBUG_OFFSET)
#define RP2040_PIO_FLEVEL(n) (RP2040_PIO_BASE(n) + RP2040_PIO_FLEVEL_OFFSET)
#define RP2040_PIO_TXF(n, m) (RP2040_PIO_BASE(n) + RP2040_PIO_TXF_OFFSET(m))
#define RP2040_PIO_TXF0(n) (RP2040_PIO_BASE(n) + RP2040_PIO_TXF0_OFFSET)
#define RP2040_PIO_TXF1(n) (RP2040_PIO_BASE(n) + RP2040_PIO_TXF1_OFFSET)
#define RP2040_PIO_TXF2(n) (RP2040_PIO_BASE(n) + RP2040_PIO_TXF2_OFFSET)
#define RP2040_PIO_TXF3(n) (RP2040_PIO_BASE(n) + RP2040_PIO_TXF3_OFFSET)
#define RP2040_PIO_RXF(n, m) (RP2040_PIO_BASE(n) + RP2040_PIO_RXF_OFFSET(m))
#define RP2040_PIO_RXF0(n) (RP2040_PIO_BASE(n) + RP2040_PIO_RXF0_OFFSET)
#define RP2040_PIO_RXF1(n) (RP2040_PIO_BASE(n) + RP2040_PIO_RXF1_OFFSET)
#define RP2040_PIO_RXF2(n) (RP2040_PIO_BASE(n) + RP2040_PIO_RXF2_OFFSET)
#define RP2040_PIO_RXF3(n) (RP2040_PIO_BASE(n) + RP2040_PIO_RXF3_OFFSET)
#define RP2040_PIO_IRQ(n) (RP2040_PIO_BASE(n) + RP2040_PIO_IRQ_OFFSET)
#define RP2040_PIO_IRQ_FORCE(n) (RP2040_PIO_BASE(n) + RP2040_PIO_IRQ_FORCE_OFFSET)
#define RP2040_PIO_INPUT_SYNC_BYPASS(n) (RP2040_PIO_BASE(n) + RP2040_PIO_INPUT_SYNC_BYPASS_OFFSET)

2
arch/arm/src/rp2040/hardware/rp2040_pwm.h
View file

@ -77,7 +77,7 @@
/* Register bit definitions *************************************************/
#define RP2040_PWM_CSR_PH_ADV (1 << 7) /* advance phase of counter by one */
#define RP2040_PWM_CSR_PH_RET (1 << 5) /* retard phase of counter by one */
#define RP2040_PWM_CSR_PH_RET (1 << 6) /* retard phase of counter by one */
#define RP2040_PWM_CSR_DIVMODE_SHIFT (4) /* divisor mode */
#define RP2040_PWM_CSR_DIVMODE_MASK (0x03 << RP2040_PWM_CSR_DIVMODE_SHIFT)
#define RP2040_PWM_CSR_B_INV (1 << 3) /* invert output B */

1
arch/arm/src/rp2040/hardware/rp2040_resets.h
View file

@ -62,6 +62,7 @@
/* Register bit definitions *************************************************/
#define RP2040_RESETS_RESET_MASK (0x1ffffff)
#define RP2040_RESETS_RESET_USBCTRL (1 << 24)
#define RP2040_RESETS_RESET_UART1 (1 << 23)
#define RP2040_RESETS_RESET_UART0 (1 << 22)

2
arch/arm/src/rp2040/rp2040_adc.c
View file

@ -584,7 +584,7 @@ static int my_ioctl(struct adc_dev_s *dev,
* Initialize and register the ADC driver.
*
* Input Parameters:
* path - Path to the ws2812 device (e.g. "/dev/adc0")
* path - Path to the adc device (e.g. "/dev/adc0")
* read_adc0 - This device reads ADC0
* read_adc1 - This device reads ADC1
* read_adc2 - This device reads ADC3

2
arch/arm/src/rp2040/rp2040_adc.h
View file

@ -72,7 +72,7 @@ extern "C"
* Initialize and register the ADC driver.
*
* Input Parameters:
* path - Path to the ws2812 device (e.g. "/dev/adc0")
* path - Path to the adc device (e.g. "/dev/adc0")
* read_adc0 - This device reads ADC0
* read_adc1 - This device reads ADC1
* read_adc2 - This device reads ADC3

42
arch/arm/src/rp2040/rp2040_clock.c
View file

@ -63,8 +63,6 @@
* Pre-processor Definitions
****************************************************************************/
#define RESETS_RESET_BITS 0x01ffffff
/****************************************************************************
* Private Data
****************************************************************************/
@ -412,33 +410,33 @@ void rp2040_clockconfig(void)
* this boot
*/
setbits_reg32(RESETS_RESET_BITS & ~(RP2040_RESETS_RESET_IO_QSPI |
RP2040_RESETS_RESET_PADS_QSPI |
RP2040_RESETS_RESET_PLL_USB |
RP2040_RESETS_RESET_PLL_SYS),
setbits_reg32(RP2040_RESETS_RESET_MASK & ~(RP2040_RESETS_RESET_IO_QSPI |
RP2040_RESETS_RESET_PADS_QSPI |
RP2040_RESETS_RESET_PLL_USB |
RP2040_RESETS_RESET_PLL_SYS),
RP2040_RESETS_RESET);
/* Remove reset from peripherals which are clocked only by clk_sys and
* clk_ref. Other peripherals stay in reset until we've configured clocks.
*/
clrbits_reg32(RESETS_RESET_BITS & ~(RP2040_RESETS_RESET_ADC |
RP2040_RESETS_RESET_RTC |
RP2040_RESETS_RESET_SPI0 |
RP2040_RESETS_RESET_SPI1 |
RP2040_RESETS_RESET_UART0 |
RP2040_RESETS_RESET_UART1 |
RP2040_RESETS_RESET_USBCTRL),
clrbits_reg32(RP2040_RESETS_RESET_MASK & ~(RP2040_RESETS_RESET_ADC |
RP2040_RESETS_RESET_RTC |
RP2040_RESETS_RESET_SPI0 |
RP2040_RESETS_RESET_SPI1 |
RP2040_RESETS_RESET_UART0 |
RP2040_RESETS_RESET_UART1 |
RP2040_RESETS_RESET_USBCTRL),
RP2040_RESETS_RESET);
while (~getreg32(RP2040_RESETS_RESET_DONE) &
(RESETS_RESET_BITS & ~(RP2040_RESETS_RESET_ADC |
RP2040_RESETS_RESET_RTC |
RP2040_RESETS_RESET_SPI0 |
RP2040_RESETS_RESET_SPI1 |
RP2040_RESETS_RESET_UART0 |
RP2040_RESETS_RESET_UART1 |
RP2040_RESETS_RESET_USBCTRL)))
(RP2040_RESETS_RESET_MASK & ~(RP2040_RESETS_RESET_ADC |
RP2040_RESETS_RESET_RTC |
RP2040_RESETS_RESET_SPI0 |
RP2040_RESETS_RESET_SPI1 |
RP2040_RESETS_RESET_UART0 |
RP2040_RESETS_RESET_UART1 |
RP2040_RESETS_RESET_USBCTRL)))
;
/* After calling preinit we have enough runtime to do the exciting maths
@ -449,7 +447,7 @@ void rp2040_clockconfig(void)
/* Peripheral clocks should now all be running */
clrbits_reg32(RESETS_RESET_BITS, RP2040_RESETS_RESET);
while (~getreg32(RP2040_RESETS_RESET_DONE) & RESETS_RESET_BITS)
clrbits_reg32(RP2040_RESETS_RESET_MASK, RP2040_RESETS_RESET);
while (~getreg32(RP2040_RESETS_RESET_DONE) & RP2040_RESETS_RESET_MASK)
;
}

275
arch/arm/src/rp23xx/Kconfig
View file

@ -5,55 +5,10 @@
comment "RP23XX Configuration Options"
#####################################################################
# PSRAM Configuration
#####################################################################
config RP23XX_PSRAM
bool "External PSRAM support"
config RP23XX_RP2350B
bool "Use RP2350B variant (QFN-80)"
default n
if RP23XX_PSRAM
choice
prompt "PSRAM heap mode"
default RP23XX_PSRAM_HEAP_USER
config RP23XX_PSRAM_HEAP_SINGLE
bool "Use PSRAM and SRAM as a single main heap"
depends on MM_REGIONS > 1 && !MM_KERNEL_HEAP
---help---
The external PSRAM and the internal SRAM will be used for
a single main heap. This configuration is good for maximum
usage of the memory without partitioning, however as there
is no control whether the memory is allocated in the SRAM
or the PSRAM, some regions will behave much slower than
others and the user must be careful in managing those
buffers for real world applications.
This option requires MM_REGIONS to be set >= 2, so the
PSRAM is added to the main heap as a new region.
config RP23XX_PSRAM_HEAP_USER
bool "Use PSRAM as user heap, SRAM as kernel heap"
depends on MM_KERNEL_HEAP
---help---
The external PSRAM is allocated to the default heap, while
the internal SRAM will be used for the kernel heap. This
configuration is useful because it allows drivers to
use the SRAM and behave much faster than if they used
memory on the PSRAM. While user applications can take
the bull benefit of the larger slower heap on the PSRAM.
config RP23XX_PSRAM_HEAP_SEPARATE
bool "Use PSRAM as a separate heap"
select ARCH_HAVE_EXTRA_HEAPS
---help---
The internal SRAM is used as the main heap for kernel and
applications. The external PSRAM is configured as a
separate user heap.
endchoice
endif
config RP23XX_DMAC
bool "DMAC support"
default y
@ -433,8 +388,6 @@ config RP23XX_PWM3
if RP23XX_PWM3
config RP23XX_PWM3A_GPIO
config RP23XX_PWM3A_INVERT
bool "PWM3 channel 1 invert"
default n
@ -568,8 +521,6 @@ config RP23XX_PWM7A_INVERT
if RP23XX_PWM_MULTICHAN && RP23XX_PWM_NCHANNELS > 1
config RP23XX_PWM7B_GPIO
config RP23XX_PWM7B_INVERT
bool "PWM7 channel 2 invert"
default n
@ -585,6 +536,130 @@ config RP23XX_PWM7_PHASE_CORRECT
endif # RP23XX_PWM7
config RP23XX_PWM8
bool "PWM7"
---help---
See the Board Selection menu to configure the pins used by I2C0.
if RP23XX_PWM8
config RP23XX_PWM8A_INVERT
bool "PWM7 channel 1 invert"
default n
---help---
If invert is enabled, the PWM on the A pin will idle high
with the pulse going low.
if RP23XX_PWM_MULTICHAN && RP23XX_PWM_NCHANNELS > 1
config RP23XX_PWM8B_INVERT
bool "PWM7 channel 2 invert"
default n
---help---
If invert is enabled, the PWM on the B pin will idle high
with the pulse going low.
endif # RP23XX_PWM_MULTICHAN && RP23XX_PWM_NCHANNELS > 1
config RP23XX_PWM8_PHASE_CORRECT
bool "PWM7 phase correct"
default n
endif # RP23XX_PWM8
config RP23XX_PWM9
bool "PWM7"
---help---
See the Board Selection menu to configure the pins used by I2C0.
if RP23XX_PWM9
config RP23XX_PWM9A_INVERT
bool "PWM7 channel 1 invert"
default n
---help---
If invert is enabled, the PWM on the A pin will idle high
with the pulse going low.
if RP23XX_PWM_MULTICHAN && RP23XX_PWM_NCHANNELS > 1
config RP23XX_PWM9B_INVERT
bool "PWM7 channel 2 invert"
default n
---help---
If invert is enabled, the PWM on the B pin will idle high
with the pulse going low.
endif # RP23XX_PWM_MULTICHAN && RP23XX_PWM_NCHANNELS > 1
config RP23XX_PWM9_PHASE_CORRECT
bool "PWM7 phase correct"
default n
endif # RP23XX_PWM9
config RP23XX_PWM10
bool "PWM7"
---help---
See the Board Selection menu to configure the pins used by I2C0.
if RP23XX_PWM10
config RP23XX_PWM10A_INVERT
bool "PWM7 channel 1 invert"
default n
---help---
If invert is enabled, the PWM on the A pin will idle high
with the pulse going low.
if RP23XX_PWM_MULTICHAN && RP23XX_PWM_NCHANNELS > 1
config RP23XX_PWM10B_INVERT
bool "PWM7 channel 2 invert"
default n
---help---
If invert is enabled, the PWM on the B pin will idle high
with the pulse going low.
endif # RP23XX_PWM_MULTICHAN && RP23XX_PWM_NCHANNELS > 1
config RP23XX_PWM10_PHASE_CORRECT
bool "PWM7 phase correct"
default n
endif # RP23XX_PWM10
config RP23XX_PWM11
bool "PWM7"
---help---
See the Board Selection menu to configure the pins used by I2C0.
if RP23XX_PWM11
config RP23XX_PWM11A_INVERT
bool "PWM7 channel 1 invert"
default n
---help---
If invert is enabled, the PWM on the A pin will idle high
with the pulse going low.
if RP23XX_PWM_MULTICHAN && RP23XX_PWM_NCHANNELS > 1
config RP23XX_PWM11B_INVERT
bool "PWM7 channel 2 invert"
default n
---help---
If invert is enabled, the PWM on the B pin will idle high
with the pulse going low.
endif # RP23XX_PWM_MULTICHAN && RP23XX_PWM_NCHANNELS > 1
config RP23XX_PWM11_PHASE_CORRECT
bool "PWM7 phase correct"
default n
endif # RP23XX_PWM11
endif # RP23XX_PWM
#####################################################################
@ -626,6 +701,32 @@ config RP23XX_I2S_PIO_SM
endif # RP23XX_I2S
#####################################################################
# SPISD Configuration
#####################################################################
config RP23XX_SPISD
bool "SPI SD Card"
default n
select MMCSD_SPI
if RP23XX_SPISD
config RP23XX_SPISD_SLOT_NO
int "SPI SD Card Slot Number"
default 0
---help---
Select spi sd card slot number.
config RP23XX_SPISD_SPI_CH
int "SPI channel number"
default 0
range 0 1
---help---
Select spi channel number to use spi sd card.
endif # SPISD Configuration
#####################################################################
# ADC Configuration
#####################################################################
@ -674,6 +775,30 @@ config RP23XX_ADC_CHANNEL3
---help---
If y, then ADC3 will be read.
config RP23XX_ADC_CHANNEL4
bool "Read ADC channel 4"
default n
---help---
If y, then ADC4 will be read.
config RP23XX_ADC_CHANNEL5
bool "Read ADC channel 5"
default n
---help---
If y, then ADC5 will be read.
config RP23XX_ADC_CHANNEL6
bool "Read ADC channel 6"
default n
---help---
If y, then ADC6 will be read.
config RP23XX_ADC_CHANNEL7
bool "Read ADC channel 7"
default n
---help---
If y, then ADC7 will be read.
config RP23XX_ADC_TEMPERATURE
bool "Read ADC chip temperature channel"
default n
@ -714,7 +839,7 @@ config RP23XX_CLK_GPOUT0_SRC_REF
Oscillator (XOSC) for more accuracy.
config RP23XX_CLK_GPOUT0_SRC_SYS
bool "SYS (125 MHz)"
bool "SYS (150 MHz)"
---help---
System clock that is always running unless in DORMANT mode. Runs from
clk_ref at power-up but is typically switched to a PLL.
@ -729,10 +854,15 @@ config RP23XX_CLK_GPOUT0_SRC_ADC
---help---
ADC reference clock. Must be 48MHz.
config RP23XX_CLK_GPOUT0_SRC_RTC
bool "RTC (46875 Hz)"
config RP23XX_CLK_GPOUT0_SRC_PERI
bool "PERI (150 MHz)"
---help---
RTC reference clock. The RTC divides this clock to generate a 1 second reference.
Peripheral reference clock. Defaults to system clock (150MHz).
config RP23XX_CLK_GPOUT0_SRC_HSTX
bool "HSTX (150 MHz)"
---help---
HSTX reference clock. Defaults to system clock (150MHz).
endchoice # Source Clock
@ -765,7 +895,7 @@ config RP23XX_CLK_GPOUT1_SRC_REF
Oscillator (XOSC) for more accuracy.
config RP23XX_CLK_GPOUT1_SRC_SYS
bool "SYS (125 MHz)"
bool "SYS (150 MHz)"
---help---
System clock that is always running unless in DORMANT mode. Runs from
clk_ref at power-up but is typically switched to a PLL.
@ -780,10 +910,15 @@ config RP23XX_CLK_GPOUT1_SRC_ADC
---help---
ADC reference clock. Must be 48MHz.
config RP23XX_CLK_GPOUT1_SRC_RTC
bool "RTC (46875 Hz)"
config RP23XX_CLK_GPOUT1_SRC_PERI
bool "PERI (150 MHz)"
---help---
RTC reference clock. The RTC divides this clock to generate a 1 second reference.
Peripheral reference clock. Defaults to system clock (150MHz).
config RP23XX_CLK_GPOUT1_SRC_HSTX
bool "HSTX (150 MHz)"
---help---
HSTX reference clock. Defaults to system clock (150MHz).
endchoice # Source Clock
@ -831,10 +966,15 @@ config RP23XX_CLK_GPOUT2_SRC_ADC
---help---
ADC reference clock. Must be 48MHz.
config RP23XX_CLK_GPOUT2_SRC_RTC
bool "RTC (46875 Hz)"
config RP23XX_CLK_GPOUT2_SRC_PERI
bool "PERI (150 MHz)"
---help---
RTC reference clock. The RTC divides this clock to generate a 1 second reference.
Peripheral reference clock. Defaults to system clock (150MHz).
config RP23XX_CLK_GPOUT2_SRC_HSTX
bool "HSTX (150 MHz)"
---help---
HSTX reference clock. Defaults to system clock (150MHz).
endchoice # Source Clock
@ -882,10 +1022,15 @@ config RP23XX_CLK_GPOUT3_SRC_ADC
---help---
ADC reference clock. Must be 48MHz.
config RP23XX_CLK_GPOUT3_SRC_RTC
bool "RTC (46875 Hz)"
config RP23XX_CLK_GPOUT3_SRC_PERI
bool "PERI (150 MHz)"
---help---
RTC reference clock. The RTC divides this clock to generate a 1 second reference.
Peripheral reference clock. Defaults to system clock (150MHz).
config RP23XX_CLK_GPOUT3_SRC_HSTX
bool "HSTX (150 MHz)"
---help---
HSTX reference clock. Defaults to system clock (150MHz).
endchoice # Source Clock

73
arch/arm/src/rp23xx/Make.defs
View file

@ -22,68 +22,61 @@ include armv8-m/Make.defs
CFLAGS += -Wno-array-bounds
CFLAGS += -DPICO_RP2040=0\
-DPICO_RP2350=1\
-DLIB_PICO_BINARY_INFO=0\
-DPICO_SECURE=1\
-D__ARM_ARCH_6M__=0
#CHIP_CSRCS += rp23xx_idle.c
CHIP_CSRCS += rp23xx_idle.c
CHIP_CSRCS += rp23xx_irq.c
CHIP_CSRCS += rp23xx_uart.c
CHIP_CSRCS += rp23xx_serial.c
CHIP_CSRCS += rp23xx_start.c
CHIP_CSRCS += rp23xx_timerisr.c
CHIP_CSRCS += rp23xx_gpio.c
#CHIP_CSRCS += rp23xx_pio.c
CHIP_CSRCS += rp23xx_pio.c
CHIP_CSRCS += rp23xx_clock.c
CHIP_CSRCS += rp23xx_xosc.c
CHIP_CSRCS += rp23xx_pll.c
ifeq ($(CONFIG_RP23XX_PSRAM),y)
CHIP_CSRCS += rp23xx_psram.c
CHIP_CSRCS += rp23xx_heaps.c
endif
ifeq ($(CONFIG_SMP),y)
CHIP_CSRCS += rp23xx_cpuindex.c
CHIP_CSRCS += rp23xx_cpustart.c
CHIP_CSRCS += rp23xx_cpupause.c
CHIP_CSRCS += rp23xx_cpuidlestack.c
#CHIP_CSRCS += rp23xx_testset.c
#CMN_ASRCS := $(filter-out arm_testset.S,$(CMN_ASRCS))
CHIP_CSRCS += rp23xx_testset.c
CMN_ASRCS := $(filter-out arm_testset.S,$(CMN_ASRCS))
endif
#ifeq ($(CONFIG_RP23XX_DMAC),y)
#CHIP_CSRCS += rp23xx_dmac.c
#endif
#
#ifeq ($(CONFIG_RP23XX_SPI),y)
#CHIP_CSRCS += rp23xx_spi.c
#endif
#
#ifeq ($(CONFIG_RP23XX_PWM),y)
#CHIP_CSRCS += rp23xx_pwm.c
#endif
#
#ifeq ($(CONFIG_RP23XX_I2C),y)
#CHIP_CSRCS += rp23xx_i2c.c
#endif
#
#ifeq ($(CONFIG_RP23XX_I2C_SLAVE),y)
#CHIP_CSRCS += rp23xx_i2c_slave.c
#endif
#
#ifeq ($(CONFIG_RP23XX_I2S),y)
#CHIP_CSRCS += rp23xx_i2s.c
#CHIP_CSRCS += rp23xx_i2s_pio.c
#endif
ifeq ($(CONFIG_RP23XX_DMAC),y)
CHIP_CSRCS += rp23xx_dmac.c
endif
ifeq ($(CONFIG_RP23XX_SPI),y)
CHIP_CSRCS += rp23xx_spi.c
endif
ifeq ($(CONFIG_RP23XX_PWM),y)
CHIP_CSRCS += rp23xx_pwm.c
endif
ifeq ($(CONFIG_RP23XX_I2C),y)
CHIP_CSRCS += rp23xx_i2c.c
endif
ifeq ($(CONFIG_RP23XX_I2C_SLAVE),y)
CHIP_CSRCS += rp23xx_i2c_slave.c
endif
ifeq ($(CONFIG_RP23XX_I2S),y)
CHIP_CSRCS += rp23xx_i2s.c
CHIP_CSRCS += rp23xx_i2s_pio.c
endif
ifeq ($(CONFIG_USBDEV),y)
CHIP_CSRCS += rp23xx_usbdev.c
endif
ifeq ($(CONFIG_RP23XX_ADC),y)
ifeq ($(CONFIG_WS2812),y)
CHIP_CSRCS += rp23xx_ws2812.c
endif
ifeq ($(CONFIG_ADC),y)
CHIP_CSRCS += rp23xx_adc.c
endif

309
arch/arm/src/rp23xx/hardware/adc.h
View file

@ -1,309 +0,0 @@
/*
* Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _HARDWARE_ADC_H
#define _HARDWARE_ADC_H
#include "pico.h"
#include "hardware/structs/adc.h"
#include "hardware/gpio.h"
/** \file hardware/adc.h
* \defgroup hardware_adc hardware_adc
*
* \brief Analog to Digital Converter (ADC) API
*
* RP-series microcontrollers have
* an internal analogue-digital converter (ADC) with the following features:
* - SAR ADC
* - 500 kS/s (Using an independent 48MHz clock)
* - 12 bit (RP2040 8.7 ENOB, RP2350 9.2 ENOB)
* \if rp2040_specific
* - RP2040 5 input mux:
* - 4 inputs that are available on package pins shared with GPIO[29:26]
* - 1 input is dedicated to the internal temperature sensor
* - 4 element receive sample FIFO
* \endif
*
* \if rp2350_specific
* - RP2350 5 or 9 input mux:
* - 4 inputs available on QFN-60 package pins shared with GPIO[29:26]
* - 8 inputs available on QFN-80 package pins shared with GPIO[47:40]
* - 8 element receive sample FIFO
* \endif
* - One input dedicated to the internal temperature sensor (see Section 12.4.6)
* - Interrupt generation
* - DMA interface
*
* Although there is only one ADC you can specify the input to it using the adc_select_input() function.
* In round robin mode (adc_set_round_robin()), the ADC will use that input and move to the next one after a read.
*
* RP2040, RP2350 QFN-60: User ADC inputs are on 0-3 (GPIO 26-29), the temperature sensor is on input 4.
* RP2350 QFN-80 : User ADC inputs are on 0-7 (GPIO 40-47), the temperature sensor is on input 8.
*
* Temperature sensor values can be approximated in centigrade as:
*
* T = 27 - (ADC_Voltage - 0.706)/0.001721
*
* \subsection adc_example Example
* \addtogroup hardware_adc
*
* \include hello_adc.c
*/
// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_HARDWARE_ADC, Enable/disable assertions in the hardware_adc module, type=bool, default=0, group=hardware_adc
#ifndef PARAM_ASSERTIONS_ENABLED_HARDWARE_ADC
#ifdef PARAM_ASSERTIONS_ENABLED_ADC // backwards compatibility with SDK < 2.0.0
#define PARAM_ASSERTIONS_ENABLED_HARDWARE_ADC PARAM_ASSERTIONS_ENABLED_ADC
#else
#define PARAM_ASSERTIONS_ENABLED_HARDWARE_ADC 0
#endif
#endif
/**
* The ADC channel number of the on-board temperature sensor
*/
#ifndef ADC_TEMPERATURE_CHANNEL_NUM
#define ADC_TEMPERATURE_CHANNEL_NUM (NUM_ADC_CHANNELS - 1)
#endif
#ifdef __cplusplus
extern "C" {
#endif
/*! \brief Initialise the ADC HW
* \ingroup hardware_adc
*
*/
void adc_init(void);
/*! \brief Initialise the gpio for use as an ADC pin
* \ingroup hardware_adc
*
* Prepare a GPIO for use with ADC by disabling all digital functions.
*
* \param gpio The GPIO number to use. Allowable GPIO numbers are 26 to 29 inclusive on RP2040 or RP2350A, 40-48 inclusive on RP2350B
*/
static inline void adc_gpio_init(uint gpio) {
invalid_params_if(HARDWARE_ADC, gpio < ADC_BASE_PIN || gpio >= ADC_BASE_PIN + NUM_ADC_CHANNELS - 1);
// Select NULL function to make output driver hi-Z
gpio_set_function(gpio, GPIO_FUNC_NULL);
// Also disable digital pulls and digital receiver
gpio_disable_pulls(gpio);
gpio_set_input_enabled(gpio, false);
}
/*! \brief ADC input select
* \ingroup hardware_adc
*
* Select an ADC input
* \if rp2040_specific
* On RP02040 0...3 are GPIOs 26...29 respectively. Input 4 is the onboard temperature sensor.
* \endif
* \if rp2350_specific
* On RP2350A 0...3 are GPIOs 26...29 respectively. Input 4 is the onboard temperature sensor.
* On RP2350B 0...7 are GPIOs 40...47 respectively. Input 8 is the onboard temperature sensor.
* \endif
*
* \param input Input to select.
*/
static inline void adc_select_input(uint input) {
valid_params_if(HARDWARE_ADC, input < NUM_ADC_CHANNELS);
hw_write_masked(&adc_hw->cs, input << ADC_CS_AINSEL_LSB, ADC_CS_AINSEL_BITS);
}
/*! \brief Get the currently selected ADC input channel
* \ingroup hardware_adc
*
* \return The currently selected input channel.
*
* \if rp2040_specific
* On RP02040 0...3 are GPIOs 26...29 respectively. Input 4 is the onboard temperature sensor.
* \endif
*
* \if rp2350_specific
* On RP2350A 0...3 are GPIOs 26...29 respectively. Input 4 is the onboard temperature sensor.
* On RP2350B 0...7 are GPIOs 40...47 respectively. Input 8 is the onboard temperature sensor.
* \endif
*/
static inline uint adc_get_selected_input(void) {
return (adc_hw->cs & ADC_CS_AINSEL_BITS) >> ADC_CS_AINSEL_LSB;
}
/*! \brief Round Robin sampling selector
* \ingroup hardware_adc
*
* This function sets which inputs are to be run through in round robin mode.
* RP2040, RP2350 QFN-60: Value between 0 and 0x1f (bit 0 to bit 4 for GPIO 26 to 29 and temperature sensor input respectively)
* RP2350 QFN-80: Value between 0 and 0xff (bit 0 to bit 7 for GPIO 40 to 47 and temperature sensor input respectively)
*
* \param input_mask A bit pattern indicating which of the 5/8 inputs are to be sampled. Write a value of 0 to disable round robin sampling.
*/
static inline void adc_set_round_robin(uint input_mask) {
valid_params_if(HARDWARE_ADC, input_mask < (1 << NUM_ADC_CHANNELS));
hw_write_masked(&adc_hw->cs, input_mask << ADC_CS_RROBIN_LSB, ADC_CS_RROBIN_BITS);
}
/*! \brief Enable the onboard temperature sensor
* \ingroup hardware_adc
*
* \param enable Set true to power on the onboard temperature sensor, false to power off.
*
*/
static inline void adc_set_temp_sensor_enabled(bool enable) {
if (enable)
hw_set_bits(&adc_hw->cs, ADC_CS_TS_EN_BITS);
else
hw_clear_bits(&adc_hw->cs, ADC_CS_TS_EN_BITS);
}
/*! \brief Perform a single conversion
* \ingroup hardware_adc
*
* Performs an ADC conversion, waits for the result, and then returns it.
*
* \return Result of the conversion.
*/
static inline uint16_t adc_read(void) {
hw_set_bits(&adc_hw->cs, ADC_CS_START_ONCE_BITS);
while (!(adc_hw->cs & ADC_CS_READY_BITS))
tight_loop_contents();
return (uint16_t) adc_hw->result;
}
/*! \brief Enable or disable free-running sampling mode
* \ingroup hardware_adc
*
* \param run false to disable, true to enable free running conversion mode.
*/
static inline void adc_run(bool run) {
if (run)
hw_set_bits(&adc_hw->cs, ADC_CS_START_MANY_BITS);
else
hw_clear_bits(&adc_hw->cs, ADC_CS_START_MANY_BITS);
}
/*! \brief Set the ADC Clock divisor
* \ingroup hardware_adc
*
* Period of samples will be (1 + div) cycles on average. Note it takes 96 cycles to perform a conversion,
* so any period less than that will be clamped to 96.
*
* \param clkdiv If non-zero, conversion will be started at intervals rather than back to back.
*/
static inline void adc_set_clkdiv(float clkdiv) {
invalid_params_if(HARDWARE_ADC, clkdiv >= 1 << (ADC_DIV_INT_MSB - ADC_DIV_INT_LSB + 1));
adc_hw->div = (uint32_t)(clkdiv * (float) (1 << ADC_DIV_INT_LSB));
}
/*! \brief Setup the ADC FIFO
* \ingroup hardware_adc
*
* \if rp2040_specific
* On RP2040 the FIFO is 4 samples long.
* \endif
*
* \if rp2350_specific
* On RP2350 the FIFO is 8 samples long.
* \endif
*
* If a conversion is completed and the FIFO is full, the result is dropped.
*
* \param en Enables write each conversion result to the FIFO
* \param dreq_en Enable DMA requests when FIFO contains data
* \param dreq_thresh Threshold for DMA requests/FIFO IRQ if enabled.
* \param err_in_fifo If enabled, bit 15 of the FIFO contains error flag for each sample
* \param byte_shift Shift FIFO contents to be one byte in size (for byte DMA) - enables DMA to byte buffers.
*/
static inline void adc_fifo_setup(bool en, bool dreq_en, uint16_t dreq_thresh, bool err_in_fifo, bool byte_shift) {
hw_write_masked(&adc_hw->fcs,
(bool_to_bit(en) << ADC_FCS_EN_LSB) |
(bool_to_bit(dreq_en) << ADC_FCS_DREQ_EN_LSB) |
(((uint)dreq_thresh) << ADC_FCS_THRESH_LSB) |
(bool_to_bit(err_in_fifo) << ADC_FCS_ERR_LSB) |
(bool_to_bit(byte_shift) << ADC_FCS_SHIFT_LSB),
ADC_FCS_EN_BITS |
ADC_FCS_DREQ_EN_BITS |
ADC_FCS_THRESH_BITS |
ADC_FCS_ERR_BITS |
ADC_FCS_SHIFT_BITS
);
}
/*! \brief Check FIFO empty state
* \ingroup hardware_adc
*
* \return Returns true if the FIFO is empty
*/
static inline bool adc_fifo_is_empty(void) {
return adc_hw->fcs & ADC_FCS_EMPTY_BITS;
}
/*! \brief Get number of entries in the ADC FIFO
* \ingroup hardware_adc
*
* \if rp2040_specific
* On RP2040 the FIFO is 4 samples long.
* \endif
* \if rp2350_specific
* On RP2350 the FIFO is 8 samples long.
* \endif
*
* This function will return how many samples are currently present.
*/
static inline uint8_t adc_fifo_get_level(void) {
return (adc_hw->fcs & ADC_FCS_LEVEL_BITS) >> ADC_FCS_LEVEL_LSB;
}
/*! \brief Get ADC result from FIFO
* \ingroup hardware_adc
*
* Pops the latest result from the ADC FIFO.
*/
static inline uint16_t adc_fifo_get(void) {
return (uint16_t)adc_hw->fifo;
}
/*! \brief Wait for the ADC FIFO to have data.
* \ingroup hardware_adc
*
* Blocks until data is present in the FIFO
*/
static inline uint16_t adc_fifo_get_blocking(void) {
while (adc_fifo_is_empty())
tight_loop_contents();
return (uint16_t)adc_hw->fifo;
}
/*! \brief Drain the ADC FIFO
* \ingroup hardware_adc
*
* Will wait for any conversion to complete then drain the FIFO, discarding any results.
*/
static inline void adc_fifo_drain(void) {
// Potentially there is still a conversion in progress -- wait for this to complete before draining
while (!(adc_hw->cs & ADC_CS_READY_BITS))
tight_loop_contents();
while (!adc_fifo_is_empty())
(void) adc_fifo_get();
}
/*! \brief Enable/Disable ADC interrupts.
* \ingroup hardware_adc
*
* \param enabled Set to true to enable the ADC interrupts, false to disable
*/
static inline void adc_irq_set_enabled(bool enabled) {
adc_hw->inte = !!enabled;
}
#ifdef __cplusplus
}
#endif
#endif

184
arch/arm/src/rp23xx/hardware/address_mapped.h
View file

@ -1,184 +0,0 @@
/*
* Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _HARDWARE_ADDRESS_MAPPED_H
#define _HARDWARE_ADDRESS_MAPPED_H
#include "pico.h"
#include "hardware/regs/addressmap.h"
/** \file address_mapped.h
* \defgroup hardware_base hardware_base
*
* \brief Low-level types and (atomic) accessors for memory-mapped hardware registers
*
* `hardware_base` defines the low level types and access functions for memory mapped hardware registers. It is included
* by default by all other hardware libraries.
*
* The following register access typedefs codify the access type (read/write) and the bus size (8/16/32) of the hardware register.
* The register type names are formed by concatenating one from each of the 3 parts A, B, C
* A | B | C | Meaning
* ------|---|---|--------
* io_ | | | A Memory mapped IO register
* &nbsp;|ro_| | read-only access
* &nbsp;|rw_| | read-write access
* &nbsp;|wo_| | write-only access (can't actually be enforced via C API)
* &nbsp;| | 8| 8-bit wide access
* &nbsp;| | 16| 16-bit wide access
* &nbsp;| | 32| 32-bit wide access
*
* When dealing with these types, you will always use a pointer, i.e. `io_rw_32 *some_reg` is a pointer to a read/write
* 32 bit register that you can write with `*some_reg = value`, or read with `value = *some_reg`.
*
* RP-series hardware is also aliased to provide atomic setting, clear or flipping of a subset of the bits within
* a hardware register so that concurrent access by two cores is always consistent with one atomic operation
* being performed first, followed by the second.
*
* See hw_set_bits(), hw_clear_bits() and hw_xor_bits() provide for atomic access via a pointer to a 32 bit register
*
* Additionally given a pointer to a structure representing a piece of hardware (e.g. `dma_hw_t *dma_hw` for the DMA controller), you can
* get an alias to the entire structure such that writing any member (register) within the structure is equivalent
* to an atomic operation via hw_set_alias(), hw_clear_alias() or hw_xor_alias()...
*
* For example `hw_set_alias(dma_hw)->inte1 = 0x80;` will set bit 7 of the INTE1 register of the DMA controller,
* leaving the other bits unchanged.
*/
#ifdef __cplusplus
extern "C" {
#endif
#define check_hw_layout(type, member, offset) static_assert(offsetof(type, member) == (offset), "hw offset mismatch")
#define check_hw_size(type, size) static_assert(sizeof(type) == (size), "hw size mismatch")
// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_ADDRESS_ALIAS, Enable/disable assertions in memory address aliasing macros, type=bool, default=0, group=hardware_base
#ifndef PARAM_ASSERTIONS_ENABLED_ADDRESS_ALIAS
#define PARAM_ASSERTIONS_ENABLED_ADDRESS_ALIAS 0
#endif
typedef volatile uint64_t io_rw_64;
typedef const volatile uint64_t io_ro_64;
typedef volatile uint64_t io_wo_64;
typedef volatile uint32_t io_rw_32;
typedef const volatile uint32_t io_ro_32;
typedef volatile uint32_t io_wo_32;
typedef volatile uint16_t io_rw_16;
typedef const volatile uint16_t io_ro_16;
typedef volatile uint16_t io_wo_16;
typedef volatile uint8_t io_rw_8;
typedef const volatile uint8_t io_ro_8;
typedef volatile uint8_t io_wo_8;
typedef volatile uint8_t *const ioptr;
typedef ioptr const const_ioptr;
// A non-functional (empty) helper macro to help IDEs follow links from the autogenerated
// hardware struct headers in hardware/structs/xxx.h to the raw register definitions
// in hardware/regs/xxx.h. A preprocessor define such as TIMER_TIMEHW_OFFSET (a timer register offset)
// is not generally clickable (in an IDE) if placed in a C comment, so _REG_(TIMER_TIMEHW_OFFSET) is
// included outside of a comment instead
#define _REG_(x)
// Helper method used by hw_alias macros to optionally check input validity
#define hw_alias_check_addr(addr) ((uintptr_t)(addr))
// can't use the following impl as it breaks existing static declarations using hw_alias, so would be a backwards incompatibility
//static __force_inline uint32_t hw_alias_check_addr(volatile void *addr) {
// uint32_t rc = (uintptr_t)addr;
// invalid_params_if(ADDRESS_ALIAS, rc < 0x40000000); // catch likely non HW pointer types
// return rc;
//}
#if PICO_RP2040
// Helper method used by xip_alias macros to optionally check input validity
__force_inline static uint32_t xip_alias_check_addr(const void *addr) {
uint32_t rc = (uintptr_t)addr;
valid_params_if(ADDRESS_ALIAS, rc >= XIP_MAIN_BASE && rc < XIP_NOALLOC_BASE);
return rc;
}
#else
//static __force_inline uint32_t xip_alias_check_addr(const void *addr) {
// uint32_t rc = (uintptr_t)addr;
// valid_params_if(ADDRESS_ALIAS, rc >= XIP_BASE && rc < XIP_END);
// return rc;
//}
#endif
// Untyped conversion alias pointer generation macros
#define hw_set_alias_untyped(addr) ((void *)(REG_ALIAS_SET_BITS + hw_alias_check_addr(addr)))
#define hw_clear_alias_untyped(addr) ((void *)(REG_ALIAS_CLR_BITS + hw_alias_check_addr(addr)))
#define hw_xor_alias_untyped(addr) ((void *)(REG_ALIAS_XOR_BITS + hw_alias_check_addr(addr)))
#if PICO_RP2040
#define xip_noalloc_alias_untyped(addr) ((void *)(XIP_NOALLOC_BASE | xip_alias_check_addr(addr)))
#define xip_nocache_alias_untyped(addr) ((void *)(XIP_NOCACHE_BASE | xip_alias_check_addr(addr)))
#define xip_nocache_noalloc_alias_untyped(addr) ((void *)(XIP_NOCACHE_NOALLOC_BASE | xip_alias_check_addr(addr)))
#endif
// Typed conversion alias pointer generation macros
#define hw_set_alias(p) ((typeof(p))hw_set_alias_untyped(p))
#define hw_clear_alias(p) ((typeof(p))hw_clear_alias_untyped(p))
#define hw_xor_alias(p) ((typeof(p))hw_xor_alias_untyped(p))
#define xip_noalloc_alias(p) ((typeof(p))xip_noalloc_alias_untyped(p))
#define xip_nocache_alias(p) ((typeof(p))xip_nocache_alias_untyped(p))
#define xip_nocache_noalloc_alias(p) ((typeof(p))xip_nocache_noalloc_alias_untyped(p))
/*! \brief Atomically set the specified bits to 1 in a HW register
* \ingroup hardware_base
*
* \param addr Address of writable register
* \param mask Bit-mask specifying bits to set
*/
__force_inline static void hw_set_bits(io_rw_32 *addr, uint32_t mask) {
*(io_rw_32 *) hw_set_alias_untyped((volatile void *) addr) = mask;
}
/*! \brief Atomically clear the specified bits to 0 in a HW register
* \ingroup hardware_base
*
* \param addr Address of writable register
* \param mask Bit-mask specifying bits to clear
*/
__force_inline static void hw_clear_bits(io_rw_32 *addr, uint32_t mask) {
*(io_rw_32 *) hw_clear_alias_untyped((volatile void *) addr) = mask;
}
/*! \brief Atomically flip the specified bits in a HW register
* \ingroup hardware_base
*
* \param addr Address of writable register
* \param mask Bit-mask specifying bits to invert
*/
__force_inline static void hw_xor_bits(io_rw_32 *addr, uint32_t mask) {
*(io_rw_32 *) hw_xor_alias_untyped((volatile void *) addr) = mask;
}
/*! \brief Set new values for a sub-set of the bits in a HW register
* \ingroup hardware_base
*
* Sets destination bits to values specified in \p values, if and only if corresponding bit in \p write_mask is set
*
* Note: this method allows safe concurrent modification of *different* bits of
* a register, but multiple concurrent access to the same bits is still unsafe.
*
* \param addr Address of writable register
* \param values Bits values
* \param write_mask Mask of bits to change
*/
__force_inline static void hw_write_masked(io_rw_32 *addr, uint32_t values, uint32_t write_mask) {
hw_xor_bits(addr, (*addr ^ values) & write_mask);
}
#if !PICO_RP2040
// include this here to avoid the check in every other hardware/structs header that needs it
#include "hardware/structs/accessctrl.h"
#endif
#ifdef __cplusplus
}
#endif
#endif

144
arch/arm/src/rp23xx/hardware/boot_lock.h
View file

@ -1,144 +0,0 @@
/*
* Copyright (c) 2024 Raspberry Pi (Trading) Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _HARDWARE_BOOT_LOCK_H
#define _HARDWARE_BOOT_LOCK_H
#include "pico.h"
// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_HARDWARE_BOOT_LOCK, Enable/disable assertions in the hardware_boot_lock module, type=bool, default=0, group=hardware_boot_lock
#ifndef PARAM_ASSERTIONS_ENABLED_HARDWARE_BOOT_LOCK
#define PARAM_ASSERTIONS_ENABLED_HARDWARE_BOOT_LOCK 0
#endif
#if NUM_BOOT_LOCKS > 0
#include "hardware/sync.h"
#include "hardware/structs/bootram.h"
/** \brief A boot lock identifier
* \ingroup hardware_sync
*/
typedef volatile uint32_t boot_lock_t;
/*! \brief Get HW Bootlock instance from number
* \ingroup hardware_sync
*
* \param lock_num Bootlock ID
* \return The bootlock instance
*/
__force_inline static boot_lock_t *boot_lock_instance(uint lock_num) {
invalid_params_if(HARDWARE_BOOT_LOCK, lock_num >= NUM_BOOT_LOCKS);
return (boot_lock_t *) (BOOTRAM_BASE + BOOTRAM_BOOTLOCK0_OFFSET + lock_num * 4);
}
/*! \brief Get HW Bootlock number from instance
* \ingroup hardware_sync
*
* \param lock The Bootlock instance
* \return The Bootlock ID
*/
__force_inline static uint boot_lock_get_num(boot_lock_t *lock) {
invalid_params_if(HARDWARE_BOOT_LOCK, (uint) lock < BOOTRAM_BASE + BOOTRAM_BOOTLOCK0_OFFSET ||
(uint) lock >= NUM_BOOT_LOCKS * sizeof(boot_lock_t) + BOOTRAM_BASE + BOOTRAM_BOOTLOCK0_OFFSET ||
((uint) lock - BOOTRAM_BASE + BOOTRAM_BOOTLOCK0_OFFSET) % sizeof(boot_lock_t) != 0);
return (uint) (lock - (boot_lock_t *) (BOOTRAM_BASE + BOOTRAM_BOOTLOCK0_OFFSET));
}
/*! \brief Acquire a boot lock without disabling interrupts (hence unsafe)
* \ingroup hardware_sync
*
* \param lock Bootlock instance
*/
__force_inline static void boot_lock_unsafe_blocking(boot_lock_t *lock) {
// Note we don't do a wfe or anything, because by convention these boot_locks are VERY SHORT LIVED and NEVER BLOCK and run
// with INTERRUPTS disabled (to ensure that)... therefore nothing on our core could be blocking us, so we just need to wait on another core
// anyway which should be finished soon
while (__builtin_expect(!*lock, 0)) { // read from bootlock register (tries to acquire the lock)
tight_loop_contents();
}
__mem_fence_acquire();
}
/*! \brief try to acquire a boot lock without disabling interrupts (hence unsafe)
* \ingroup hardware_sync
*
* \param lock Bootlock instance
*/
__force_inline static bool boot_try_lock_unsafe(boot_lock_t *lock) {
if (*lock) {
__mem_fence_acquire();
return true;
}
return false;
}
/*! \brief Release a boot lock without re-enabling interrupts
* \ingroup hardware_sync
*
* \param lock Bootlock instance
*/
__force_inline static void boot_unlock_unsafe(boot_lock_t *lock) {
__mem_fence_release();
*lock = 0; // write to bootlock register (release lock)
}
/*! \brief Acquire a boot lock safely
* \ingroup hardware_sync
*
* This function will disable interrupts prior to acquiring the bootlock
*
* \param lock Bootlock instance
* \return interrupt status to be used when unlocking, to restore to original state
*/
__force_inline static uint32_t boot_lock_blocking(boot_lock_t *lock) {
uint32_t save = save_and_disable_interrupts();
boot_lock_unsafe_blocking(lock);
return save;
}
/*! \brief Check to see if a bootlock is currently acquired elsewhere.
* \ingroup hardware_sync
*
* \param lock Bootlock instance
*/
inline static bool is_boot_locked(boot_lock_t *lock) {
check_hw_size(boot_lock_t, 4);
uint lock_num = boot_lock_get_num(lock);
return 0 != (*(io_ro_32 *) (BOOTRAM_BASE + BOOTRAM_BOOTLOCK_STAT_OFFSET) & (1u << lock_num));
}
/*! \brief Release a boot lock safely
* \ingroup hardware_sync
*
* This function will re-enable interrupts according to the parameters.
*
* \param lock Bootlock instance
* \param saved_irq Return value from the \ref boot_lock_blocking() function.
*
* \sa boot_lock_blocking()
*/
__force_inline static void boot_unlock(boot_lock_t *lock, uint32_t saved_irq) {
boot_unlock_unsafe(lock);
restore_interrupts_from_disabled(saved_irq);
}
/*! \brief Initialise a boot lock
* \ingroup hardware_sync
*
* The boot lock is initially unlocked
*
* \param lock_num The boot lock number
* \return The boot lock instance
*/
boot_lock_t *boot_lock_init(uint lock_num);
/*! \brief Release all boot locks
* \ingroup hardware_sync
*/
void boot_locks_reset(void);
#endif
#endif

473
arch/arm/src/rp23xx/hardware/clocks.h
View file

@ -1,473 +0,0 @@
/*
* Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _HARDWARE_CLOCKS_H
#define _HARDWARE_CLOCKS_H
#include "pico.h"
#include "hardware/structs/clocks.h"
#ifdef __cplusplus
extern "C" {
#endif
/** \file hardware/clocks.h
* \defgroup hardware_clocks hardware_clocks
*
* \brief Clock Management API
*
* This API provides a high level interface to the clock functions.
*
* The clocks block provides independent clocks to on-chip and external components. It takes inputs from a variety of clock
* sources allowing the user to trade off performance against cost, board area and power consumption. From these sources
* it uses multiple clock generators to provide the required clocks. This architecture allows the user flexibility to start and
* stop clocks independently and to vary some clock frequencies whilst maintaining others at their optimum frequencies
*
* Please refer to the appropriate datasheet for more details on the RP-series clocks.
*
* The clock source depends on which clock you are attempting to configure. The first table below shows main clock sources. If
* you are not setting the Reference clock or the System clock, or you are specifying that one of those two will be using an auxiliary
* clock source, then you will need to use one of the entries from the subsequent tables.
*
* * \if rp2040_specific
* On RP2040 the clock sources are:
*
* **Main Clock Sources**
*
* Source | Reference Clock | System Clock
* -------|-----------------|---------
* ROSC | CLOCKS_CLK_REF_CTRL_SRC_VALUE_ROSC_CLKSRC_PH | |
* Auxiliary | CLOCKS_CLK_REF_CTRL_SRC_VALUE_CLKSRC_CLK_REF_AUX | CLOCKS_CLK_SYS_CTRL_SRC_VALUE_CLKSRC_CLK_SYS_AUX
* XOSC | CLOCKS_CLK_REF_CTRL_SRC_VALUE_XOSC_CLKSRC | |
* Reference | | CLOCKS_CLK_SYS_CTRL_SRC_VALUE_CLK_REF
*
* **Auxiliary Clock Sources**
*
* The auxiliary clock sources available for use in the configure function depend on which clock is being configured. The following table
* describes the available values that can be used. Note that for clk_gpout[x], x can be 0-3.
*
*
* Aux Source | clk_gpout[x] | clk_ref | clk_sys
* -----------|------------|---------|--------
* System PLL | CLOCKS_CLK_GPOUTx_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS | | CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS
* GPIO in 0 | CLOCKS_CLK_GPOUTx_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 | CLOCKS_CLK_REF_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 | CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0
* GPIO in 1 | CLOCKS_CLK_GPOUTx_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 | CLOCKS_CLK_REF_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 | CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1
* USB PLL | CLOCKS_CLK_GPOUTx_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB | CLOCKS_CLK_REF_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB| CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB
* ROSC | CLOCKS_CLK_GPOUTx_CTRL_AUXSRC_VALUE_ROSC_CLKSRC | | CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_ROSC_CLKSRC
* XOSC | CLOCKS_CLK_GPOUTx_CTRL_AUXSRC_VALUE_XOSC_CLKSRC | | CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_XOSC_CLKSRC
* System clock | CLOCKS_CLK_GPOUTx_CTRL_AUXSRC_VALUE_CLK_SYS | | |
* USB Clock | CLOCKS_CLK_GPOUTx_CTRL_AUXSRC_VALUE_CLK_USB | | |
* ADC clock | CLOCKS_CLK_GPOUTx_CTRL_AUXSRC_VALUE_CLK_ADC | | |
* RTC Clock | CLOCKS_CLK_GPOUTx_CTRL_AUXSRC_VALUE_CLK_RTC | | |
* Ref clock | CLOCKS_CLK_GPOUTx_CTRL_AUXSRC_VALUE_CLK_REF | | |
*
* Aux Source | clk_peri | clk_usb | clk_adc
* -----------|-----------|---------|--------
* System PLL | CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS | CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS | CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS
* GPIO in 0 | CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 | CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 | CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0
* GPIO in 1 | CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 | CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 | CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1
* USB PLL | CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB | CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB | CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB
* ROSC | CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_ROSC_CLKSRC_PH | CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_ROSC_CLKSRC_PH | CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_ROSC_CLKSRC_PH
* XOSC | CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_XOSC_CLKSRC | CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_XOSC_CLKSRC | CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_XOSC_CLKSRC
* System clock | CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_CLK_SYS | | |
*
* Aux Source | clk_rtc
* -----------|----------
* System PLL | CLOCKS_CLK_RTC_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS
* GPIO in 0 | CLOCKS_CLK_RTC_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0
* GPIO in 1 | CLOCKS_CLK_RTC_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1
* USB PLL | CLOCKS_CLK_RTC_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB
* ROSC | CLOCKS_CLK_RTC_CTRL_AUXSRC_VALUE_ROSC_CLKSRC_PH
* XOSC | CLOCKS_CLK_RTC_CTRL_AUXSRC_VALUE_XOSC_CLKSRC
* \endif
*
* \if rp2350_specific
* On RP2350 the clock sources are:
* * **Main Clock Sources**
*
* Source | Reference Clock | System Clock
* -------|-----------------|---------
* ROSC | CLOCKS_CLK_REF_CTRL_SRC_VALUE_ROSC_CLKSRC_PH | |
* Auxiliary | CLOCKS_CLK_REF_CTRL_SRC_VALUE_CLKSRC_CLK_REF_AUX | CLOCKS_CLK_SYS_CTRL_SRC_VALUE_CLKSRC_CLK_SYS_AUX
* XOSC | CLOCKS_CLK_REF_CTRL_SRC_VALUE_XOSC_CLKSRC | |
* LPOSC | CLOCKS_CLK_REF_CTRL_SRC_VALUE_LPOSC_CLKSRC | |
* Reference | | CLOCKS_CLK_SYS_CTRL_SRC_VALUE_CLK_REF
*
* **Auxiliary Clock Sources**
*
* The auxiliary clock sources available for use in the configure function depend on which clock is being configured. The following table
* describes the available values that can be used. Note that for clk_gpout[x], x can be 0-3.
*
*
* Aux Source | clk_gpout[x] | clk_ref | clk_sys
* -----------|------------|---------|--------
* System PLL | CLOCKS_CLK_GPOUTx_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS | | CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS
* GPIO in 0 | CLOCKS_CLK_GPOUTx_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 | CLOCKS_CLK_REF_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 | CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0
* GPIO in 1 | CLOCKS_CLK_GPOUTx_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 | CLOCKS_CLK_REF_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 | CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1
* USB PLL | CLOCKS_CLK_GPOUTx_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB | CLOCKS_CLK_REF_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB| CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB
* ROSC | CLOCKS_CLK_GPOUTx_CTRL_AUXSRC_VALUE_ROSC_CLKSRC | | CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_ROSC_CLKSRC
* XOSC | CLOCKS_CLK_GPOUTx_CTRL_AUXSRC_VALUE_XOSC_CLKSRC | | CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_XOSC_CLKSRC
* LPOSC | CLOCKS_CLK_GPOUTx_CTRL_AUXSRC_VALUE_LPOSC_CLKSRC | CLOCKS_CLK_REF_CTRL_AUXSRC_VALUE_LPOSC_CLKSRC | |
* System clock | CLOCKS_CLK_GPOUTx_CTRL_AUXSRC_VALUE_CLK_SYS | | |
* USB Clock | CLOCKS_CLK_GPOUTx_CTRL_AUXSRC_VALUE_CLK_USB | | |
* ADC clock | CLOCKS_CLK_GPOUTx_CTRL_AUXSRC_VALUE_CLK_ADC | | |
* REF clock | CLOCKS_CLK_GPOUTx_CTRL_AUXSRC_VALUE_CLK_REF | | |
* PERI clock | CLOCKS_CLK_GPOUTx_CTRL_AUXSRC_VALUE_CLK_PERI | | |
* HSTX clock | CLOCKS_CLK_GPOUTx_CTRL_AUXSRC_VALUE_CLK_PERI | | |
*
* Aux Source | clk_peri | clk_hstx | clk_usb | clk_adc
* -----------|-----------|----------|---------|--------
* System PLL | CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS | CLOCKS_CLK_HSTX_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS | CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS | CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS
* GPIO in 0 | CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 | | CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 | CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0
* GPIO in 1 | CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 | | CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 | CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1
* USB PLL | CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB | CLOCKS_CLK_HSTX_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB | CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB | CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB
* ROSC | CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_ROSC_CLKSRC_PH | | CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_ROSC_CLKSRC_PH | CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_ROSC_CLKSRC_PH
* XOSC | CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_XOSC_CLKSRC | | CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_XOSC_CLKSRC | CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_XOSC_CLKSRC
* System clock | CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_CLK_SYS | CLOCKS_CLK_HSTX_CTRL_AUXSRC_VALUE_CLK_SYS | | |
* \endif
*
* \section clock_example Example
* \addtogroup hardware_clocks
* \include hello_48MHz.c
*/
#define KHZ 1000
#define MHZ 1000000
// \tag::pll_settings[]
// There are two PLLs in RP-series microcontrollers:
// 1. The 'SYS PLL' generates the system clock, the frequency is defined by `SYS_CLK_KHZ`.
// 2. The 'USB PLL' generates the USB clock, the frequency is defined by `USB_CLK_KHZ`.
//
// The two PLLs use the crystal oscillator output directly as their reference frequency input; the PLLs reference
// frequency cannot be reduced by the dividers present in the clocks block. The crystal frequency is defined by `XOSC_HZ` (or
// `XOSC_KHZ` or `XOSC_MHZ`).
//
// The system's default definitions are correct for the above frequencies with a 12MHz
// crystal frequency. If different frequencies are required, these must be defined in
// the board configuration file together with the revised PLL settings
// Use `vcocalc.py` to check and calculate new PLL settings if you change any of these frequencies.
//
// Default PLL configuration RP2040:
// REF FBDIV VCO POSTDIV
// PLL SYS: 12 / 1 = 12MHz * 125 = 1500MHz / 6 / 2 = 125MHz
// PLL USB: 12 / 1 = 12MHz * 100 = 1200MHz / 5 / 5 = 48MHz
//
// Default PLL configuration RP2350:
// REF FBDIV VCO POSTDIV
// PLL SYS: 12 / 1 = 12MHz * 125 = 1500MHz / 5 / 2 = 150MHz
// PLL USB: 12 / 1 = 12MHz * 100 = 1200MHz / 5 / 5 = 48MHz
// \end::pll_settings[]
#ifndef PLL_COMMON_REFDIV
// backwards compatibility, but now deprecated
#define PLL_COMMON_REFDIV 1
#endif
// PICO_CONFIG: PLL_SYS_REFDIV, PLL reference divider setting for PLL_SYS, type=int, default=1, advanced=true, group=hardware_clocks
#ifndef PLL_SYS_REFDIV
// backwards compatibility with deprecated PLL_COMMON_REFDIV
#ifdef PLL_COMMON_REFDIV
#define PLL_SYS_REFDIV PLL_COMMON_REFDIV
#else
#define PLL_SYS_REFDIV 1
#endif
#endif
#ifndef PLL_SYS_VCO_FREQ_HZ
// For backwards compatibility define PLL_SYS_VCO_FREQ_HZ if PLL_SYS_VCO_FREQ_KHZ is defined
#ifdef PLL_SYS_VCO_FREQ_KHZ
#define PLL_SYS_VCO_FREQ_HZ (PLL_SYS_VCO_FREQ_KHZ * KHZ)
#endif
#endif
#if (SYS_CLK_HZ == 125 * MHZ || SYS_CLK_HZ == 150 * MHZ) && (XOSC_HZ == 12 * MHZ) && (PLL_SYS_REFDIV == 1)
// PLL settings for standard 125/150 MHz system clock.
// PICO_CONFIG: PLL_SYS_VCO_FREQ_HZ, System clock PLL frequency, type=int, default=(1500 * MHZ), advanced=true, group=hardware_clocks
#ifndef PLL_SYS_VCO_FREQ_HZ
#define PLL_SYS_VCO_FREQ_HZ (1500 * MHZ)
#endif
// PICO_CONFIG: PLL_SYS_POSTDIV1, System clock PLL post divider 1 setting, type=int, default=6 on RP2040 5 or on RP2350, advanced=true, group=hardware_clocks
#ifndef PLL_SYS_POSTDIV1
#if SYS_CLK_HZ == 125 * MHZ
#define PLL_SYS_POSTDIV1 6
#else
#define PLL_SYS_POSTDIV1 5
#endif
#endif
// PICO_CONFIG: PLL_SYS_POSTDIV2, System clock PLL post divider 2 setting, type=int, default=2, advanced=true, group=hardware_clocks
#ifndef PLL_SYS_POSTDIV2
#define PLL_SYS_POSTDIV2 2
#endif
#endif // SYS_CLK_KHZ == 125000 && XOSC_KHZ == 12000 && PLL_COMMON_REFDIV == 1
#if !defined(PLL_SYS_VCO_FREQ_HZ) || !defined(PLL_SYS_POSTDIV1) || !defined(PLL_SYS_POSTDIV2)
#error PLL_SYS_VCO_FREQ_HZ, PLL_SYS_POSTDIV1 and PLL_SYS_POSTDIV2 must all be specified when using custom clock setup
#endif
// PICO_CONFIG: PLL_USB_REFDIV, PLL reference divider setting for PLL_USB, type=int, default=1, advanced=true, group=hardware_clocks
#ifndef PLL_USB_REFDIV
// backwards compatibility with deprecated PLL_COMMON_REFDIV
#ifdef PLL_COMMON_REFDIV
#define PLL_USB_REFDIV PLL_COMMON_REFDIV
#else
#define PLL_USB_REFDIV 1
#endif
#endif
#ifndef PLL_USB_VCO_FREQ_HZ
// For backwards compatibility define PLL_USB_VCO_FREQ_HZ if PLL_USB_VCO_FREQ_KHZ is defined
#ifdef PLL_USB_VCO_FREQ_KHZ
#define PLL_USB_VCO_FREQ_HZ (PLL_USB_VCO_FREQ_KHZ * KHZ)
#endif
#endif
#if (USB_CLK_HZ == 48 * MHZ) && (XOSC_HZ == 12 * MHZ) && (PLL_USB_REFDIV == 1)
// PLL settings for a USB clock of 48MHz.
// PICO_CONFIG: PLL_USB_VCO_FREQ_HZ, USB clock PLL frequency, type=int, default=(1200 * MHZ), advanced=true, group=hardware_clocks
#ifndef PLL_USB_VCO_FREQ_HZ
#define PLL_USB_VCO_FREQ_HZ (1200 * MHZ)
#endif
// PICO_CONFIG: PLL_USB_POSTDIV1, USB clock PLL post divider 1 setting, type=int, default=5, advanced=true, group=hardware_clocks
#ifndef PLL_USB_POSTDIV1
#define PLL_USB_POSTDIV1 5
#endif
// PICO_CONFIG: PLL_USB_POSTDIV2, USB clock PLL post divider 2 setting, type=int, default=5, advanced=true, group=hardware_clocks
#ifndef PLL_USB_POSTDIV2
#define PLL_USB_POSTDIV2 5
#endif
#endif // USB_CLK_HZ == 48000000 && XOSC_HZ == 12000000 && PLL_COMMON_REFDIV == 1
#if !defined(PLL_USB_VCO_FREQ_HZ) || !defined(PLL_USB_POSTDIV1) || !defined(PLL_USB_POSTDIV2)
#error PLL_USB_VCO_FREQ_HZ, PLL_USB_POSTDIV1 and PLL_USB_POSTDIV2 must all be specified when using custom clock setup.
#endif
// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_HARDWARE_CLOCKS, Enable/disable assertions in the hardware_clocks module, type=bool, default=0, group=hardware_clocks
#ifndef PARAM_ASSERTIONS_ENABLED_HARDWARE_CLOCKS
#ifdef PARAM_ASSERTIONS_ENABLED_CLOCKS // backwards compatibility with SDK < 2.0.0
#define PARAM_ASSERTIONS_ENABLED_HARDWARE_CLOCKS PARAM_ASSERTIONS_ENABLED_CLOCKS
#else
#define PARAM_ASSERTIONS_ENABLED_HARDWARE_CLOCKS 0
#endif
#endif
typedef clock_num_t clock_handle_t;
/*! \brief Configure the specified clock
* \ingroup hardware_clocks
*
* See the tables in the description for details on the possible values for clock sources.
*
* \param clock The clock to configure
* \param src The main clock source, can be 0.
* \param auxsrc The auxiliary clock source, which depends on which clock is being set. Can be 0
* \param src_freq Frequency of the input clock source
* \param freq Requested frequency
*/
bool clock_configure(clock_handle_t clock, uint32_t src, uint32_t auxsrc, uint32_t src_freq, uint32_t freq);
/*! \brief Configure the specified clock to use the undividded input source
* \ingroup hardware_clocks
*
* See the tables in the description for details on the possible values for clock sources.
*
* \param clock The clock to configure
* \param src The main clock source, can be 0.
* \param auxsrc The auxiliary clock source, which depends on which clock is being set. Can be 0
* \param src_freq Frequency of the input clock source
*/
void clock_configure_undivided(clock_handle_t clock, uint32_t src, uint32_t auxsrc, uint32_t src_freq);
/*! \brief Configure the specified clock to use the undividded input source
* \ingroup hardware_clocks
*
* See the tables in the description for details on the possible values for clock sources.
*
* \param clock The clock to configure
* \param src The main clock source, can be 0.
* \param auxsrc The auxiliary clock source, which depends on which clock is being set. Can be 0
* \param src_freq Frequency of the input clock source
* \param int_divider an integer divider
*/
void clock_configure_int_divider(clock_handle_t clock, uint32_t src, uint32_t auxsrc, uint32_t src_freq, uint32_t int_divider);
/*! \brief Stop the specified clock
* \ingroup hardware_clocks
*
* \param clock The clock to stop
*/
void clock_stop(clock_handle_t clock);
/*! \brief Get the current frequency of the specified clock
* \ingroup hardware_clocks
*
* \param clock Clock
* \return Clock frequency in Hz
*/
uint32_t clock_get_hz(clock_handle_t clock);
/*! \brief Measure a clocks frequency using the Frequency counter.
* \ingroup hardware_clocks
*
* Uses the inbuilt frequency counter to measure the specified clocks frequency.
* Currently, this function is accurate to +-1KHz. See the datasheet for more details.
*/
uint32_t frequency_count_khz(uint src);
/*! \brief Set the "current frequency" of the clock as reported by clock_get_hz without actually changing the clock
* \ingroup hardware_clocks
*
* \see clock_get_hz()
*/
void clock_set_reported_hz(clock_handle_t clock, uint hz);
/// \tag::frequency_count_mhz[]
static inline float frequency_count_mhz(uint src) {
return ((float) (frequency_count_khz(src))) / KHZ;
}
/// \end::frequency_count_mhz[]
/*! \brief Resus callback function type.
* \ingroup hardware_clocks
*
* User provided callback for a resus event (when clk_sys is stopped by the programmer and is restarted for them).
*/
typedef void (*resus_callback_t)(void);
/*! \brief Enable the resus function. Restarts clk_sys if it is accidentally stopped.
* \ingroup hardware_clocks
*
* The resuscitate function will restart the system clock if it falls below a certain speed (or stops). This
* could happen if the clock source the system clock is running from stops. For example if a PLL is stopped.
*
* \param resus_callback a function pointer provided by the user to call if a resus event happens.
*/
void clocks_enable_resus(resus_callback_t resus_callback);
/*! \brief Output an optionally divided clock to the specified gpio pin.
* \ingroup hardware_clocks
*
* \param gpio The GPIO pin to output the clock to. Valid GPIOs are: 21, 23, 24, 25. These GPIOs are connected to the GPOUT0-3 clock generators.
* \param src The source clock. See the register field CLOCKS_CLK_GPOUT0_CTRL_AUXSRC for a full list. The list is the same for each GPOUT clock generator.
* \param div_int The integer part of the value to divide the source clock by. This is useful to not overwhelm the GPIO pin with a fast clock. this is in range of 1..2^24-1.
* \param div_frac The fractional part of the value to divide the source clock by. This is in range of 0..255 (/256).
*/
void clock_gpio_init_int_frac(uint gpio, uint src, uint32_t div_int, uint8_t div_frac);
/*! \brief Output an optionally divided clock to the specified gpio pin.
* \ingroup hardware_clocks
*
* \param gpio The GPIO pin to output the clock to. Valid GPIOs are: 21, 23, 24, 25. These GPIOs are connected to the GPOUT0-3 clock generators.
* \param src The source clock. See the register field CLOCKS_CLK_GPOUT0_CTRL_AUXSRC for a full list. The list is the same for each GPOUT clock generator.
* \param div The float amount to divide the source clock by. This is useful to not overwhelm the GPIO pin with a fast clock.
*/
static inline void clock_gpio_init(uint gpio, uint src, float div)
{
uint div_int = (uint)div;
uint8_t frac = (uint8_t)((div - (float)div_int) * (1u << CLOCKS_CLK_GPOUT0_DIV_INT_LSB));
clock_gpio_init_int_frac(gpio, src, div_int, frac);
}
/*! \brief Configure a clock to come from a gpio input
* \ingroup hardware_clocks
*
* \param clock The clock to configure
* \param gpio The GPIO pin to run the clock from. Valid GPIOs are: 20 and 22.
* \param src_freq Frequency of the input clock source
* \param freq Requested frequency
*/
bool clock_configure_gpin(clock_handle_t clock, uint gpio, uint32_t src_freq, uint32_t freq);
/*! \brief Initialise the system clock to 48MHz
* \ingroup pico_stdlib
*
* Set the system clock to 48MHz, and set the peripheral clock to match.
*/
void set_sys_clock_48mhz(void);
/*! \brief Initialise the system clock
* \ingroup pico_stdlib
*
* \param vco_freq The voltage controller oscillator frequency to be used by the SYS PLL
* \param post_div1 The first post divider for the SYS PLL
* \param post_div2 The second post divider for the SYS PLL.
*
* See the PLL documentation in the datasheet for details of driving the PLLs.
*/
void set_sys_clock_pll(uint32_t vco_freq, uint post_div1, uint post_div2);
/*! \brief Check if a given system clock frequency is valid/attainable
* \ingroup pico_stdlib
*
* \param freq_hz Requested frequency
* \param vco_freq_out On success, the voltage controlled oscillator frequency to be used by the SYS PLL
* \param post_div1_out On success, The first post divider for the SYS PLL
* \param post_div2_out On success, The second post divider for the SYS PLL.
* @return true if the frequency is possible and the output parameters have been written.
*/
bool check_sys_clock_hz(uint32_t freq_hz, uint *vco_freq_out, uint *post_div1_out, uint *post_div2_out);
/*! \brief Check if a given system clock frequency is valid/attainable
* \ingroup pico_stdlib
*
* \param freq_khz Requested frequency
* \param vco_freq_out On success, the voltage controlled oscillator frequency to be used by the SYS PLL
* \param post_div1_out On success, The first post divider for the SYS PLL
* \param post_div2_out On success, The second post divider for the SYS PLL.
* @return true if the frequency is possible and the output parameters have been written.
*/
bool check_sys_clock_khz(uint32_t freq_khz, uint *vco_freq_out, uint *post_div1_out, uint *post_div2_out);
/*! \brief Attempt to set a system clock frequency in hz
* \ingroup pico_stdlib
*
* Note that not all clock frequencies are possible; it is preferred that you
* use src/rp2_common/hardware_clocks/scripts/vcocalc.py to calculate the parameters
* for use with set_sys_clock_pll
*
* \param freq_hz Requested frequency
* \param required if true then this function will assert if the frequency is not attainable.
* \return true if the clock was configured
*/
static inline bool set_sys_clock_hz(uint32_t freq_hz, bool required) {
uint vco, postdiv1, postdiv2;
if (check_sys_clock_hz(freq_hz, &vco, &postdiv1, &postdiv2)) {
set_sys_clock_pll(vco, postdiv1, postdiv2);
return true;
} else if (required) {
panic("System clock of %u Hz cannot be exactly achieved", freq_hz);
}
return false;
}
/*! \brief Attempt to set a system clock frequency in khz
* \ingroup pico_stdlib
*
* Note that not all clock frequencies are possible; it is preferred that you
* use src/rp2_common/hardware_clocks/scripts/vcocalc.py to calculate the parameters
* for use with set_sys_clock_pll
*
* \param freq_khz Requested frequency
* \param required if true then this function will assert if the frequency is not attainable.
* \return true if the clock was configured
*/
static inline bool set_sys_clock_khz(uint32_t freq_khz, bool required) {
uint vco, postdiv1, postdiv2;
if (check_sys_clock_khz(freq_khz, &vco, &postdiv1, &postdiv2)) {
set_sys_clock_pll(vco, postdiv1, postdiv2);
return true;
} else if (required) {
panic("System clock of %u kHz cannot be exactly achieved", freq_khz);
}
return false;
}
#ifdef __cplusplus
}
#endif
#endif

420
arch/arm/src/rp23xx/hardware/dcp_canned.inc.S
View file

@ -1,420 +0,0 @@
/*
* Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
// Canned instruction sequences for use with the DCP
.macro dcp_fadd_m rz,rx,ry
WXYU \rx,\ry
ADD0
ADD1
NRDF
RDFA \rz
.endm
.macro dcp_fsub_m rz,rx,ry
WXYU \rx,\ry
ADD0
SUB1
NRDF
RDFS \rz
.endm
.macro dcp_fmul_m rz,rx,ry,ra,rb
WXYU \rx,\ry
RXYH \ra,\rb
umull \ra,\rb,\ra,\rb
WXFM \ra,\rb
NRDF
RDFM \rz
.endm
.macro dcp_fxprod_m rzl,rzh,rx,ry,ra,rb
WXYU \rx,\ry
RXYH \ra,\rb
umull \ra,\rb,\ra,\rb
WXMO \ra,\rb
NRDD
RDDM \rzl,\rzh
.endm
.macro dcp_fdiv_fast_m rz,rx,ry,ra,rb,rc
WXYU \rx,\ry
RYMR \ra,\rb
umull \rb,\rc,\ra,\rb
mvn \rc,\rc,lsl #2
smmlar \ra,\rc,\ra,\ra
smmulr \rc,\rc,\rc
smmlar \ra,\rc,\ra,\ra
RXYH \rb,\rc
umull \ra,\rb,\ra,\rb
WXFD \rb,\rb
NRDF
RDFD \rz
.endm
.macro dcp_fdiv_m rz,rx,ry,ra,rb,rc,rd
WXYU \rx,\ry
RYMR \ra,\rb
umull \rb,\rc,\ra,\rb
mvn \rc,\rc,lsl #2
smmlar \ra,\rc,\ra,\ra
smmulr \rc,\rc,\rc
smmlar \ra,\rc,\ra,\ra
RXYH \rb,\rc
umull \rd,\ra,\ra,\rb
orr \ra,\ra,\ra,lsr #24
bic \ra,\ra,\ra,lsr #25
bic \ra,\ra,#15
mov \rc,\rc,lsr #7
mul \rd,\ra,\rc
rsb \rd,\rd,\rb,lsl #22
sub \ra,\ra,\rd,lsr #31
WXFD \ra,\ra
NRDF
RDFD \rz
.endm
.macro dcp_fsqrt_fast_m rz,rx,ra,rb,rc,rd
WXYU \rx,\rx
SQR0
RXMQ \rc,\rd
umull \ra,\rb,\rc,\rc
umull \ra,\rb,\rb,\rd
mov \rb,\rb,lsl #3
sub \rb,\rb,#2147483648
smmlsr \rc,\rc,\rb,\rc
umull \ra,\rb,\rc,\rc
umull \ra,\rb,\rb,\rd
movs \ra,\ra,lsr #28
adc \rb,\ra,\rb,lsl #4
smmulr \ra,\rb,\rc
sub \rc,\rc,\ra,asr #1
umull \ra,\rb,\rc,\rd
WXFQ \ra,\rb
NRDF
RDFQ \rz
.endm
.macro dcp_fsqrt_m rz,rx,ra,rb,rc,rd
WXYU \rx,\rx
SQR0
RXMQ \rc,\rd
umull \ra,\rb,\rc,\rc
umull \ra,\rb,\rb,\rd
mov \rb,\rb,lsl #3
sub \rb,\rb,#2147483648
smmlsr \rc,\rc,\rb,\rc
umull \ra,\rb,\rc,\rc
umull \ra,\rb,\rb,\rd
movs \ra,\ra,lsr #28
adc \rb,\ra,\rb,lsl #4
smmulr \ra,\rb,\rc
sub \rc,\rc,\ra,asr #1
umull \ra,\rb,\rc,\rd
orr \rb,\rb,#63
mov \ra,\rb,lsr #5
mul \ra,\ra,\ra
rsb \ra,\ra,\rd,lsl #18
bic \rb,\rb,\ra,lsr #26
WXFQ \ra,\rb
NRDF
RDFQ \rz
.endm
.macro dcp_fclassify_m rz,rx
WXYU \rx,\rx
RXVD \rz
.endm
.macro dcp_fcmp_m rz,rx,ry
WXYU \rx,\ry
ADD0
RCMP \rz
.endm
.macro dcp_dadd_m rzl,rzh,rxl,rxh,ryl,ryh
WXUP \rxl,\rxh
WYUP \ryl,\ryh
ADD0
ADD1
NRDD
RDDA \rzl,\rzh
.endm
.macro dcp_dsub_m rzl,rzh,rxl,rxh,ryl,ryh
WXUP \rxl,\rxh
WYUP \ryl,\ryh
ADD0
SUB1
NRDD
RDDS \rzl,\rzh
.endm
.macro dcp_dmul_m rzl,rzh,rxl,rxh,ryl,ryh,ra,rb,rc,rd,re,rf,rg
WXUP \rxl,\rxh
WYUP \ryl,\ryh
RXMS \ra,\rb,0
RYMS \rc,\rd,0
umull \re,\rf,\ra,\rc
movs \rg,#0
umlal \rf,\rg,\ra,\rd
umlal \rf,\rg,\rb,\rc
WXMS \re,\rf
movs \re,#0
umlal \rg,\re,\rb,\rd
WXMO \rg,\re
NRDD
RDDM \rzl,\rzh
.endm
.macro dcp_ddiv_fast_m rzl,rzh,rxl,rxh,ryl,ryh,ra,rb,rc,rd,re
WXUP \rxl,\rxh
WYUP \ryl,\ryh
RYMR \ra,\rb
umull \rb,\rc,\ra,\rb
mvn \rc,\rc,lsl #2
smmlar \ra,\rc,\ra,\ra
smmulr \rc,\rc,\rc
smmlar \ra,\rc,\ra,\ra
sub \re,\ra,\ra,lsr #31
RXMS \rc,\rd,0
smmulr \rb,\re,\rd
RYMS \rc,\rd,1
umull \rc,\ra,\rb,\rc
mla \ra,\rb,\rd,\ra
RXMS \rc,\rd,4
sub \ra,\rc,\ra
smmulr \rc,\ra,\re
mov \rd,\rb,lsr #4
adds \ra,\rc,\rb,lsl #28
adc \rb,\rd,\rc,asr #31
WXDD \ra,\rb
NRDD
RDDD \rzl,\rzh
.endm
.macro dcp_ddiv_m rzl,rzh,rxl,rxh,ryl,ryh,ra,rb,rc,rd,re
WXUP \rxl,\rxh
WYUP \ryl,\ryh
RYMR \ra,\rb
umull \rb,\rc,\ra,\rb
mvn \rc,\rc,lsl #2
smmlar \ra,\rc,\ra,\ra
smmulr \rc,\rc,\rc
smmlar \ra,\rc,\ra,\ra
sub \re,\ra,\ra,lsr #31
RXMS \rc,\rd,0
smmulr \rb,\re,\rd
RYMS \rc,\rd,1
umull \rc,\ra,\rb,\rc
mla \ra,\rb,\rd,\ra
RXMS \rc,\rd,4
sub \ra,\rc,\ra
smmulr \rc,\ra,\re
mov \rd,\rb,lsr #4
adds \ra,\rc,\rb,lsl #28
adc \rb,\rd,\rc,asr #31
orr \ra,\ra,\rb,lsr #21
bic \ra,\ra,\rb,lsr #22
bic \ra,\ra,#7
RYMS \rc,\rd,7
umull \rd,\re,\ra,\rc
RYMS \rc,\rd,7
mla \re,\ra,\rd,\re
mla \re,\rb,\rc,\re
RXMS \rc,\rd,0
sub \re,\re,\rc,lsl #18
orr \ra,\ra,\re,lsr #29
sub \ra,\ra,#1
WXDD \ra,\rb
NRDD
RDDD \rzl,\rzh
.endm
.macro dcp_dsqrt_fast_m rzl,rzh,rxl,rxh,ra,rb,rc,rd,re
WXUP \rxl,\rxh
SQR0
RXMQ \rc,\rd
umull \ra,\rb,\rc,\rc
umull \ra,\rb,\rb,\rd
mov \rb,\rb,lsl #3
sub \rb,\rb,#2147483648
smmlsr \rc,\rc,\rb,\rc
umull \ra,\rb,\rc,\rc
umull \ra,\rb,\rb,\rd
movs \ra,\ra,lsr #28
adc \rb,\ra,\rb,lsl #4
smmulr \ra,\rb,\rc
sub \rc,\rc,\ra,asr #1
umull \ra,\rb,\rc,\rd
mov \rb,\rb,lsr #1
umull \rd,\ra,\rb,\rb
RXMS \ra,\re,6
sub \ra,\ra,\rd
smmulr \ra,\ra,\rc
add \rb,\rb,\ra,asr #28
mov \ra,\ra,lsl #4
WXDQ \ra,\rb
NRDD
RDDQ \rzl,\rzh
.endm
.macro dcp_dsqrt_m rzl,rzh,rxl,rxh,ra,rb,rc,rd,re
WXUP \rxl,\rxh
SQR0
RXMQ \rc,\rd
umull \ra,\rb,\rc,\rc
umull \ra,\rb,\rb,\rd
mov \rb,\rb,lsl #3
sub \rb,\rb,#2147483648
smmlsr \rc,\rc,\rb,\rc
umull \ra,\rb,\rc,\rc
umull \ra,\rb,\rb,\rd
movs \ra,\ra,lsr #28
adc \rb,\ra,\rb,lsl #4
smmulr \ra,\rb,\rc
sub \rc,\rc,\ra,asr #1
umull \ra,\rb,\rc,\rd
mov \rb,\rb,lsr #1
umull \rd,\ra,\rb,\rb
RXMS \ra,\re,6
sub \rd,\ra,\rd
smmulr \rd,\rd,\rc
add \rb,\rb,\rd,asr #28
mov \rd,\rd,lsl #4
bic \rd,\rd,#255
orr \rd,\rd,#128
umull \re,\rc,\rd,\rd
mul \re,\rb,\rb
umlal \rc,\re,\rb,\rd
umlal \rc,\re,\rb,\rd
sub \re,\re,\ra
orr \rd,\rd,\re,lsr #24
sub \rd,\rd,#11
WXDQ \rd,\rb
NRDD
RDDQ \rzl,\rzh
.endm
.macro dcp_dclassify_m rz,rxl,rxh
WXUP \rxl,\rxh
RXVD \rz
.endm
.macro dcp_dcmp_m rz,rxl,rxh,ryl,ryh
WXUP \rxl,\rxh
WYUP \ryl,\ryh
ADD0
RCMP \rz
.endm
.macro dcp_float2double_m rzl,rzh,rx
WXYU \rx,\rx
NRDD
RDDG \rzl,\rzh
.endm
.macro dcp_double2float_m rz,rxl,rxh
WXUP \rxl,\rxh
NRDF
RDFG \rz
.endm
.macro dcp_int2double_m rzl,rzh,rx
WXIC \rx,\rx
ADD0
SUB1
NRDD
RDDS \rzl,\rzh
.endm
.macro dcp_uint2double_m rzl,rzh,rx
WXUC \rx,\rx
ADD0
SUB1
NRDD
RDDS \rzl,\rzh
.endm
.macro dcp_int2float_m rz,rx
WXIC \rx,\rx
ADD0
SUB1
NRDF
RDFS \rz
.endm
.macro dcp_uint2float_m rz,rx
WXUC \rx,\rx
ADD0
SUB1
NRDF
RDFS \rz
.endm
.macro dcp_double2int_m rz,rxl,rxh
WXDC \rxl,\rxh
ADD0
ADD1
NTDC
RDIC \rz
.endm
.macro dcp_double2uint_m rz,rxl,rxh
WXDC \rxl,\rxh
ADD0
ADD1
NTDC
RDUC \rz
.endm
.macro dcp_float2int_m rz,rx
WXFC \rx,\rx
ADD0
ADD1
NTDC
RDIC \rz
.endm
.macro dcp_float2uint_m rz,rx
WXFC \rx,\rx
ADD0
ADD1
NTDC
RDUC \rz
.endm
.macro dcp_double2int_r_m rz,rxl,rxh
WXDC \rxl,\rxh
ADD0
ADD1
NRDC
RDIC \rz
.endm
.macro dcp_double2uint_r_m rz,rxl,rxh
WXDC \rxl,\rxh
ADD0
ADD1
NRDC
RDUC \rz
.endm
.macro dcp_float2int_r_m rz,rx
WXFC \rx,\rx
ADD0
ADD1
NRDC
RDIC \rz
.endm
.macro dcp_float2uint_r_m rz,rx
WXFC \rx,\rx
ADD0
ADD1
NRDC
RDUC \rz
.endm

232
arch/arm/src/rp23xx/hardware/dcp_instr.inc.S
View file

@ -1,232 +0,0 @@
/*
* Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
.macro INIT
cdp p4,#0,c0,c0,c0,#0
.endm
.macro ADD0
cdp p4,#0,c0,c0,c1,#0
.endm
.macro ADD1
cdp p4,#1,c0,c0,c1,#0
.endm
.macro SUB1
cdp p4,#1,c0,c0,c1,#1
.endm
.macro SQR0
cdp p4,#2,c0,c0,c1,#0
.endm
.macro NORM
cdp p4,#8,c0,c0,c2,#0
.endm
.macro NRDF
cdp p4,#8,c0,c0,c2,#1
.endm
.macro NRDD
cdp p4,#8,c0,c0,c0,#1
.endm
.macro NTDC
cdp p4,#8,c0,c0,c0,#2
.endm
.macro NRDC
cdp p4,#8,c0,c0,c0,#3
.endm
.macro WXMD rl,rh
mcrr p4,#0,\rl,\rh,c0
.endm
.macro WYMD rl,rh
mcrr p4,#0,\rl,\rh,c1
.endm
.macro WEFD rl,rh
mcrr p4,#0,\rl,\rh,c2
.endm
.macro WXUP rl,rh
mcrr p4,#1,\rl,\rh,c0
.endm
.macro WYUP rl,rh
mcrr p4,#1,\rl,\rh,c1
.endm
.macro WXYU rl,rh
mcrr p4,#1,\rl,\rh,c2
.endm
.macro WXMS rl,rh
mcrr p4,#2,\rl,\rh,c0
.endm
.macro WXMO rl,rh
mcrr p4,#3,\rl,\rh,c0
.endm
.macro WXDD rl,rh
mcrr p4,#4,\rl,\rh,c0
.endm
.macro WXDQ rl,rh
mcrr p4,#5,\rl,\rh,c0
.endm
.macro WXUC rl,rh
mcrr p4,#6,\rl,\rh,c0
.endm
.macro WXIC rl,rh
mcrr p4,#7,\rl,\rh,c0
.endm
.macro WXDC rl,rh
mcrr p4,#8,\rl,\rh,c0
.endm
.macro WXFC rl,rh
mcrr p4,#9,\rl,\rh,c2
.endm
.macro WXFM rl,rh
mcrr p4,#10,\rl,\rh,c0
.endm
.macro WXFD rl,rh
mcrr p4,#11,\rl,\rh,c0
.endm
.macro WXFQ rl,rh
mcrr p4,#12,\rl,\rh,c0
.endm
.macro RXVD rt
mrc p4,#0,\rt,c0,c0,#0
.endm
.macro RCMP rt
mrc p4,#0,\rt,c0,c0,#1
.endm
.macro RDFA rt
mrc p4,#0,\rt,c0,c2,#0
.endm
.macro RDFS rt
mrc p4,#0,\rt,c0,c2,#1
.endm
.macro RDFM rt
mrc p4,#0,\rt,c0,c2,#2
.endm
.macro RDFD rt
mrc p4,#0,\rt,c0,c2,#3
.endm
.macro RDFQ rt
mrc p4,#0,\rt,c0,c2,#4
.endm
.macro RDFG rt
mrc p4,#0,\rt,c0,c2,#5
.endm
.macro RDIC rt
mrc p4,#0,\rt,c0,c3,#0
.endm
.macro RDUC rt
mrc p4,#0,\rt,c0,c3,#1
.endm
.macro RXMD rl,rh
mrrc p4,#0,\rl,\rh,c8
.endm
.macro RYMD rl,rh
mrrc p4,#0,\rl,\rh,c9
.endm
.macro REFD rl,rh
mrrc p4,#0,\rl,\rh,c10
.endm
.macro RXMS rl,rh,s
mrrc p4,#\s,\rl,\rh,c4
.endm
.macro RYMS rl,rh,s
mrrc p4,#\s,\rl,\rh,c5
.endm
.macro RXYH rl,rh
mrrc p4,#1,\rl,\rh,c1
.endm
.macro RYMR rl,rh
mrrc p4,#2,\rl,\rh,c1
.endm
.macro RXMQ rl,rh
mrrc p4,#4,\rl,\rh,c1
.endm
.macro RDDA rl,rh
mrrc p4,#1,\rl,\rh,c0
.endm
.macro RDDS rl,rh
mrrc p4,#3,\rl,\rh,c0
.endm
.macro RDDM rl,rh
mrrc p4,#5,\rl,\rh,c0
.endm
.macro RDDD rl,rh
mrrc p4,#7,\rl,\rh,c0
.endm
.macro RDDQ rl,rh
mrrc p4,#9,\rl,\rh,c0
.endm
.macro RDDG rl,rh
mrrc p4,#11,\rl,\rh,c0
.endm
.macro PXVD rt
mrc2 p4,#0,\rt,c0,c0,#0
.endm
.macro PCMP rt
mrc2 p4,#0,\rt,c0,c0,#1
.endm
.macro PDFA rt
mrc2 p4,#0,\rt,c0,c2,#0
.endm
.macro PDFS rt
mrc2 p4,#0,\rt,c0,c2,#1
.endm
.macro PDFM rt
mrc2 p4,#0,\rt,c0,c2,#2
.endm
.macro PDFD rt
mrc2 p4,#0,\rt,c0,c2,#3
.endm
.macro PDFQ rt
mrc2 p4,#0,\rt,c0,c2,#4
.endm
.macro PDFG rt
mrc2 p4,#0,\rt,c0,c2,#5
.endm
.macro PDIC rt
mrc2 p4,#0,\rt,c0,c3,#0
.endm
.macro PDUC rt
mrc2 p4,#0,\rt,c0,c3,#1
.endm
.macro PXMD rl,rh
mrrc2 p4,#0,\rl,\rh,c8
.endm
.macro PYMD rl,rh
mrrc2 p4,#0,\rl,\rh,c9
.endm
.macro PEFD rl,rh
mrrc2 p4,#0,\rl,\rh,c10
.endm
.macro PXMS rl,rh,s
mrrc2 p4,#\s,\rl,\rh,c4
.endm
.macro PYMS rl,rh,s
mrrc2 p4,#\s,\rl,\rh,c5
.endm
.macro PXYH rl,rh
mrrc2 p4,#1,\rl,\rh,c1
.endm
.macro PYMR rl,rh
mrrc2 p4,#2,\rl,\rh,c1
.endm
.macro PXMQ rl,rh
mrrc2 p4,#4,\rl,\rh,c1
.endm
.macro PDDA rl,rh
mrrc2 p4,#1,\rl,\rh,c0
.endm
.macro PDDS rl,rh
mrrc2 p4,#3,\rl,\rh,c0
.endm
.macro PDDM rl,rh
mrrc2 p4,#5,\rl,\rh,c0
.endm
.macro PDDD rl,rh
mrrc2 p4,#7,\rl,\rh,c0
.endm
.macro PDDQ rl,rh
mrrc2 p4,#9,\rl,\rh,c0
.endm
.macro PDDG rl,rh
mrrc2 p4,#11,\rl,\rh,c0
.endm

515
arch/arm/src/rp23xx/hardware/divider.h
View file

@ -1,515 +0,0 @@
/*
* Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _HARDWARE_DIVIDER_H
#define _HARDWARE_DIVIDER_H
#include "pico.h"
/** \file hardware/divider.h
* \defgroup hardware_divider hardware_divider
*
* \brief RP2040 Low Low-level hardware-divider API. Non-RP2040 platforms provide software versions of all the functions
*
* The SIO contains an 8-cycle signed/unsigned divide/modulo circuit, per core. Calculation is started by writing a dividend
* and divisor to the two argument registers, DIVIDEND and DIVISOR. The divider calculates the quotient / and remainder % of
* this division over the next 8 cycles, and on the 9th cycle the results can be read from the two result registers
* DIV_QUOTIENT and DIV_REMAINDER. A 'ready' bit in register DIV_CSR can be polled to wait for the calculation to
* complete, or software can insert a fixed 8-cycle delay
*
* This header provides low level macros and inline functions for accessing the hardware dividers directly,
* and perhaps most usefully performing asynchronous divides. These functions however do not follow the regular
* SDK conventions for saving/restoring the divider state, so are not generally safe to call from interrupt handlers
*
* The pico_divider library provides a more user friendly set of APIs over the divider (and support for
* 64 bit divides), and of course by default regular C language integer divisions are redirected through that library, meaning
* you can just use C level `/` and `%` operators and gain the benefits of the fast hardware divider.
*
* \if rp2350_specific
* On RP2350 there is no hardware divider, and the functions are implemented in software
* \endif
*
* @see pico_divider
*
* \subsection divider_example Example
* \addtogroup hardware_divider
* \include hello_divider.c
*/
#if HAS_SIO_DIVIDER
#include "hardware/structs/sio.h"
#else
#define PICO_EMULATE_DIVIDER 1
#endif
#ifdef __cplusplus
extern "C" {
#endif
typedef uint64_t divmod_result_t;
#if PICO_EMULATE_DIVIDER
extern divmod_result_t hw_divider_results[NUM_CORES];
static inline int __sign_of(int32_t v) {
return v > 0 ? 1 : (v < 0 ? -1 : 0);
}
#endif
/*! \brief Do a signed HW divide and wait for result
* \ingroup hardware_divider
*
* Divide \p a by \p b, wait for calculation to complete, return result as a pair of 32-bit quotient/remainder values.
*
* \param a The dividend
* \param b The divisor
* \return Results of divide as a pair of 32-bit quotient/remainder values.
*/
#if !PICO_EMULATE_DIVIDER
divmod_result_t hw_divider_divmod_s32(int32_t a, int32_t b);
#else
static inline divmod_result_t hw_divider_divmod_s32(int32_t a, int32_t b) {
if (!b) return (((uint64_t)a)<<32u) | (uint32_t)(-__sign_of(a));
return (((uint64_t)(a%b))<<32u) | (uint32_t)(a/b);
}
#endif
/*! \brief Do an unsigned HW divide and wait for result
* \ingroup hardware_divider
*
* Divide \p a by \p b, wait for calculation to complete, return result as a pair of 32-bit quotient/remainder values.
*
* \param a The dividend
* \param b The divisor
* \return Results of divide as a pair of 32-bit quotient/remainder values.
*/
#if !PICO_EMULATE_DIVIDER
divmod_result_t hw_divider_divmod_u32(uint32_t a, uint32_t b);
#else
static inline divmod_result_t hw_divider_divmod_u32(uint32_t a, uint32_t b) {
if (!b) return (((uint64_t)a)<<32u) | (uint32_t)(-1); // todo check this
return (((uint64_t)(a%b))<<32u) | (a/b);
}
#endif
/*! \brief Start a signed asynchronous divide
* \ingroup hardware_divider
*
* Start a divide of the specified signed parameters. You should wait for 8 cycles (__div_pause()) or wait for the ready bit to be set
* (hw_divider_wait_ready()) prior to reading the results.
*
* \param a The dividend
* \param b The divisor
*/
static inline void hw_divider_divmod_s32_start(int32_t a, int32_t b) {
#if !PICO_EMULATE_DIVIDER
check_hw_layout( sio_hw_t, div_sdividend, SIO_DIV_SDIVIDEND_OFFSET);
sio_hw->div_sdividend = (uint32_t)a;
sio_hw->div_sdivisor = (uint32_t)b;
#else
hw_divider_divmod_s32(a, b);
#endif
}
/*! \brief Start an unsigned asynchronous divide
* \ingroup hardware_divider
*
* Start a divide of the specified unsigned parameters. You should wait for 8 cycles (__div_pause()) or wait for the ready bit to be set
* (hw_divider_wait_ready()) prior to reading the results.
*
* \param a The dividend
* \param b The divisor
*/
static inline void hw_divider_divmod_u32_start(uint32_t a, uint32_t b) {
#if !PICO_EMULATE_DIVIDER
check_hw_layout(
sio_hw_t, div_udividend, SIO_DIV_UDIVIDEND_OFFSET);
sio_hw->div_udividend = a;
sio_hw->div_udivisor = b;
#else
hw_divider_divmod_u32(a, b);
#endif
}
/*! \brief Wait for a divide to complete
* \ingroup hardware_divider
*
* Wait for a divide to complete
*/
static inline void hw_divider_wait_ready(void) {
#if !PICO_EMULATE_DIVIDER
// this is #1 in lsr below
static_assert(SIO_DIV_CSR_READY_BITS == 1, "");
// we use one less register and instruction than gcc which uses a TST instruction
uint32_t tmp; // allow compiler to pick scratch register
pico_default_asm_volatile (
"hw_divider_result_loop_%=:"
"ldr %0, [%1, %2]\n\t"
"lsrs %0, %0, #1\n\t"
"bcc hw_divider_result_loop_%=\n\t"
: "=&l" (tmp)
: "l" (sio_hw), "I" (SIO_DIV_CSR_OFFSET)
: "cc"
);
#endif
}
/*! \brief Return result of HW divide, nowait
* \ingroup hardware_divider
*
* \note This is UNSAFE in that the calculation may not have been completed.
*
* \return Current result. Most significant 32 bits are the remainder, lower 32 bits are the quotient.
*/
static inline divmod_result_t hw_divider_result_nowait(void) {
#if !PICO_EMULATE_DIVIDER
// as ugly as this looks it is actually quite efficient
divmod_result_t rc = ((divmod_result_t) sio_hw->div_remainder) << 32u;
rc |= sio_hw->div_quotient;
return rc;
#else
return hw_divider_results[get_core_num()];
#endif
}
/*! \brief Return result of last asynchronous HW divide
* \ingroup hardware_divider
*
* This function waits for the result to be ready by calling hw_divider_wait_ready().
*
* \return Current result. Most significant 32 bits are the remainder, lower 32 bits are the quotient.
*/
static inline divmod_result_t hw_divider_result_wait(void) {
hw_divider_wait_ready();
return hw_divider_result_nowait();
}
/*! \brief Efficient extraction of unsigned quotient from 32p32 fixed point
* \ingroup hardware_divider
*
* \param r A pair of 32-bit quotient/remainder values.
* \return Unsigned quotient
*/
inline static uint32_t to_quotient_u32(divmod_result_t r) {
return (uint32_t) r;
}
/*! \brief Efficient extraction of signed quotient from 32p32 fixed point
* \ingroup hardware_divider
*
* \param r A pair of 32-bit quotient/remainder values.
* \return Unsigned quotient
*/
inline static int32_t to_quotient_s32(divmod_result_t r) {
return (int32_t)(uint32_t)r;
}
/*! \brief Efficient extraction of unsigned remainder from 32p32 fixed point
* \ingroup hardware_divider
*
* \param r A pair of 32-bit quotient/remainder values.
* \return Unsigned remainder
*
* \note On Arm this is just a 32 bit register move or a nop
*/
inline static uint32_t to_remainder_u32(divmod_result_t r) {
return (uint32_t)(r >> 32u);
}
/*! \brief Efficient extraction of signed remainder from 32p32 fixed point
* \ingroup hardware_divider
*
* \param r A pair of 32-bit quotient/remainder values.
* \return Signed remainder
*
* \note On arm this is just a 32 bit register move or a nop
*/
inline static int32_t to_remainder_s32(divmod_result_t r) {
return (int32_t)(r >> 32u);
}
/*! \brief Return result of last asynchronous HW divide, unsigned quotient only
* \ingroup hardware_divider
*
* This function waits for the result to be ready by calling hw_divider_wait_ready().
*
* \return Current unsigned quotient result.
*/
static inline uint32_t hw_divider_u32_quotient_wait(void) {
#if !PICO_EMULATE_DIVIDER
hw_divider_wait_ready();
return sio_hw->div_quotient;
#else
return to_quotient_u32(hw_divider_result_wait());
#endif
}
/*! \brief Return result of last asynchronous HW divide, signed quotient only
* \ingroup hardware_divider
*
* This function waits for the result to be ready by calling hw_divider_wait_ready().
*
* \return Current signed quotient result.
*/
static inline int32_t hw_divider_s32_quotient_wait(void) {
#if !PICO_EMULATE_DIVIDER
hw_divider_wait_ready();
return (int32_t)sio_hw->div_quotient;
#else
return to_quotient_s32(hw_divider_result_wait());
#endif
}
/*! \brief Return result of last asynchronous HW divide, unsigned remainder only
* \ingroup hardware_divider
*
* This function waits for the result to be ready by calling hw_divider_wait_ready().
*
* \return Current unsigned remainder result.
*/
static inline uint32_t hw_divider_u32_remainder_wait(void) {
#if !PICO_EMULATE_DIVIDER
hw_divider_wait_ready();
uint32_t rc = sio_hw->div_remainder;
sio_hw->div_quotient; // must read quotient to cooperate with other SDK code
return rc;
#else
return to_remainder_u32(hw_divider_result_wait());
#endif
}
/*! \brief Return result of last asynchronous HW divide, signed remainder only
* \ingroup hardware_divider
*
* This function waits for the result to be ready by calling hw_divider_wait_ready().
*
* \return Current remainder results.
*/
static inline int32_t hw_divider_s32_remainder_wait(void) {
#if !PICO_EMULATE_DIVIDER
hw_divider_wait_ready();
int32_t rc = (int32_t)sio_hw->div_remainder;
sio_hw->div_quotient; // must read quotient to cooperate with other SDK code
return rc;
#else
return to_remainder_s32(hw_divider_result_wait());
#endif
}
/*! \brief Do an unsigned HW divide, wait for result, return quotient
* \ingroup hardware_divider
*
* Divide \p a by \p b, wait for calculation to complete, return quotient.
*
* \param a The dividend
* \param b The divisor
* \return Quotient results of the divide
*/
static inline uint32_t hw_divider_u32_quotient(uint32_t a, uint32_t b) {
#if !PICO_EMULATE_DIVIDER
return to_quotient_u32(hw_divider_divmod_u32(a, b));
#else
return b ? (a / b) : (uint32_t)(-1);
#endif
}
/*! \brief Do an unsigned HW divide, wait for result, return remainder
* \ingroup hardware_divider
*
* Divide \p a by \p b, wait for calculation to complete, return remainder.
*
* \param a The dividend
* \param b The divisor
* \return Remainder results of the divide
*/
static inline uint32_t hw_divider_u32_remainder(uint32_t a, uint32_t b) {
#if !PICO_EMULATE_DIVIDER
return to_remainder_u32(hw_divider_divmod_u32(a, b));
#else
return b ? (a % b) : a;
#endif
}
/*! \brief Do a signed HW divide, wait for result, return quotient
* \ingroup hardware_divider
*
* Divide \p a by \p b, wait for calculation to complete, return quotient.
*
* \param a The dividend
* \param b The divisor
* \return Quotient results of the divide
*/
static inline int32_t hw_divider_quotient_s32(int32_t a, int32_t b) {
#if !PICO_EMULATE_DIVIDER
return to_quotient_s32(hw_divider_divmod_s32(a, b));
#else
return b ? (a / b) : -1;
#endif
}
/*! \brief Do a signed HW divide, wait for result, return remainder
* \ingroup hardware_divider
*
* Divide \p a by \p b, wait for calculation to complete, return remainder.
*
* \param a The dividend
* \param b The divisor
* \return Remainder results of the divide
*/
static inline int32_t hw_divider_remainder_s32(int32_t a, int32_t b) {
#if !PICO_EMULATE_DIVIDER
return to_remainder_s32(hw_divider_divmod_s32(a, b));
#else
return b ? (a % b) : a;
#endif
}
/*! \brief Pause for exact amount of time needed for a asynchronous divide to complete
* \ingroup hardware_divider
*/
static inline void hw_divider_pause(void) {
#if !PICO_EMULATE_DIVIDER
pico_default_asm_volatile(
"b _1_%=\n"
"_1_%=:\n"
"b _2_%=\n"
"_2_%=:\n"
"b _3_%=\n"
"_3_%=:\n"
"b _4_%=\n"
"_4_%=:\n"
:::);
#endif
}
/*! \brief Do a hardware unsigned HW divide, wait for result, return quotient
* \ingroup hardware_divider
*
* Divide \p a by \p b, wait for calculation to complete, return quotient.
*
* \param a The dividend
* \param b The divisor
* \return Quotient result of the divide
*/
static inline uint32_t hw_divider_u32_quotient_inlined(uint32_t a, uint32_t b) {
#if !PICO_EMULATE_DIVIDER
hw_divider_divmod_u32_start(a, b);
hw_divider_pause();
return sio_hw->div_quotient;
#else
return hw_divider_u32_quotient(a,b);
#endif
}
/*! \brief Do a hardware unsigned HW divide, wait for result, return remainder
* \ingroup hardware_divider
*
* Divide \p a by \p b, wait for calculation to complete, return remainder.
*
* \param a The dividend
* \param b The divisor
* \return Remainder result of the divide
*/
static inline uint32_t hw_divider_u32_remainder_inlined(uint32_t a, uint32_t b) {
#if !PICO_EMULATE_DIVIDER
hw_divider_divmod_u32_start(a, b);
hw_divider_pause();
uint32_t rc = sio_hw->div_remainder;
sio_hw->div_quotient; // must read quotient to cooperate with other SDK code
return rc;
#else
return hw_divider_u32_remainder(a,b);
#endif
}
/*! \brief Do a hardware signed HW divide, wait for result, return quotient
* \ingroup hardware_divider
*
* Divide \p a by \p b, wait for calculation to complete, return quotient.
*
* \param a The dividend
* \param b The divisor
* \return Quotient result of the divide
*/
static inline int32_t hw_divider_s32_quotient_inlined(int32_t a, int32_t b) {
#if !PICO_EMULATE_DIVIDER
hw_divider_divmod_s32_start(a, b);
hw_divider_pause();
return (int32_t)sio_hw->div_quotient;
#else
return hw_divider_quotient_s32(a,b);
#endif
}
/*! \brief Do a hardware signed HW divide, wait for result, return remainder
* \ingroup hardware_divider
*
* Divide \p a by \p b, wait for calculation to complete, return remainder.
*
* \param a The dividend
* \param b The divisor
* \return Remainder result of the divide
*/
static inline int32_t hw_divider_s32_remainder_inlined(int32_t a, int32_t b) {
#if !PICO_EMULATE_DIVIDER
hw_divider_divmod_s32_start(a, b);
hw_divider_pause();
int32_t rc = (int32_t)sio_hw->div_remainder;
sio_hw->div_quotient; // must read quotient to cooperate with other SDK code
return rc;
#else
return hw_divider_remainder_s32(a,b);
#endif
}
#if !PICO_EMULATE_DIVIDER
typedef struct {
uint32_t values[4];
} hw_divider_state_t;
#else
typedef uint64_t hw_divider_state_t;
#endif
/*! \brief Save the calling cores hardware divider state
* \ingroup hardware_divider
*
* Copy the current core's hardware divider state into the provided structure. This method
* waits for the divider results to be stable, then copies them to memory.
* They can be restored via hw_divider_restore_state()
*
* \param dest the location to store the divider state
*/
#if !PICO_EMULATE_DIVIDER
void hw_divider_save_state(hw_divider_state_t *dest);
#else
static inline void hw_divider_save_state(hw_divider_state_t *dest) {
*dest = hw_divider_results[get_core_num()];
}
#endif
/*! \brief Load a saved hardware divider state into the current core's hardware divider
* \ingroup hardware_divider
*
* Copy the passed hardware divider state into the hardware divider.
*
* \param src the location to load the divider state from
*/
#if !PICO_EMULATE_DIVIDER
void hw_divider_restore_state(hw_divider_state_t *src);
#else
static inline void hw_divider_restore_state(hw_divider_state_t *src) {
hw_divider_results[get_core_num()] = *src;
}
#endif
#ifdef __cplusplus
}
#endif
#endif // _HARDWARE_DIVIDER_H

68
arch/arm/src/rp23xx/hardware/divider_helper.S
View file

@ -1,68 +0,0 @@
/*
* Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
// Note this file is always included by another, so does not do pico_default_asm_setup
#include "hardware/regs/addressmap.h"
#include "hardware/regs/sio.h"
#if SIO_DIV_CSR_READY_LSB == 0
.equ SIO_DIV_CSR_READY_SHIFT_FOR_CARRY, 1
#else
need to change SHIFT above
#endif
#if SIO_DIV_CSR_DIRTY_LSB == 1
.equ SIO_DIV_CSR_DIRTY_SHIFT_FOR_CARRY, 2
#else
need to change SHIFT above
#endif
// SIO_BASE ptr in r2; pushes r4-r7, lr to stack
.macro save_div_state_and_lr
// originally we did this, however a) it uses r3, and b) the push and dividend/divisor
// readout takes 8 cycles, c) any IRQ which uses the divider will necessarily put the
// data back, which will immediately make it ready
//
// // ldr r3, [r2, #SIO_DIV_CSR_OFFSET]
// // // wait for results as we can't save signed-ness of operation
// // 1:
// // lsrs r3, #SIO_DIV_CSR_READY_SHIFT_FOR_CARRY
// // bcc 1b
// 6 cycle push + 2 ldr ensures the 8 cycle delay before remainder and quotient are ready
push {r4, r5, r6, r7, lr}
// note we must read quotient last, and since it isn't the last reg, we'll not use ldmia!
ldr r4, [r2, #SIO_DIV_UDIVIDEND_OFFSET]
ldr r5, [r2, #SIO_DIV_UDIVISOR_OFFSET]
ldr r7, [r2, #SIO_DIV_REMAINDER_OFFSET]
ldr r6, [r2, #SIO_DIV_QUOTIENT_OFFSET]
.endm
// restores divider state from r4-r7, then pops them and pc
.macro restore_div_state_and_return
// writing sdividend (r4), sdivisor (r5), quotient (r6), remainder (r7) in that order
//
// it is worth considering what happens if we are interrupted
//
// after writing r4: we are DIRTY and !READY
// ... interruptor using div will complete based on incorrect inputs, but dividend at least will be
// saved/restored correctly and we'll restore the rest ourselves
// after writing r4, r5: we are DIRTY and !READY
// ... interruptor using div will complete based on possibly wrongly signed inputs, but dividend, divisor
// at least will be saved/restored correctly and and we'll restore the rest ourselves
// after writing r4, r5, r6: we are DIRTY and READY
// ... interruptor using div will dividend, divisor, quotient registers as is (what we just restored ourselves),
// and we'll restore the remainder after the fact
// note we are not use STM not because it can be restarted due to interrupt which is harmless, more because this is 1 cycle IO space
// and so 4 reads is cheaper (and we don't have to adjust r2)
// note also, that we must restore via UDIVI* rather than SDIVI* to prevent the quotient/remainder being negated on read based
// on the signs of the inputs
str r4, [r2, #SIO_DIV_UDIVIDEND_OFFSET]
str r5, [r2, #SIO_DIV_UDIVISOR_OFFSET]
str r7, [r2, #SIO_DIV_REMAINDER_OFFSET]
str r6, [r2, #SIO_DIV_QUOTIENT_OFFSET]
pop {r4, r5, r6, r7, pc}
.endm

948
arch/arm/src/rp23xx/hardware/dma.h
View file

@ -1,948 +0,0 @@
/*
* Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _HARDWARE_DMA_H
#define _HARDWARE_DMA_H
#include "pico.h"
#include "hardware/structs/dma.h"
#include "hardware/regs/dreq.h"
#include "pico/assert.h"
#include "hardware/regs/intctrl.h"
#ifdef __cplusplus
extern "C" {
#endif
/** \file hardware/dma.h
* \defgroup hardware_dma hardware_dma
*
* \brief DMA Controller API
*
* The RP-series microcontroller Direct Memory Access (DMA) master performs bulk data transfers on a processor’s
* behalf. This leaves processors free to attend to other tasks, or enter low-power sleep states. The
* data throughput of the DMA is also significantly higher than one of RP-series microcontroller’s processors.
*
* The DMA can perform one read access and one write access, up to 32 bits in size, every clock cycle.
* There are 12 independent channels, which each supervise a sequence of bus transfers, usually in
* one of the following scenarios:
*
* * Memory to peripheral
* * Peripheral to memory
* * Memory to memory
*/
// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_HARDWARE_DMA, Enable/disable hardware_dma assertions, type=bool, default=0, group=hardware_dma
#ifndef PARAM_ASSERTIONS_ENABLED_HARDWARE_DMA
#ifdef PARAM_ASSERTIONS_ENABLED_DMA // backwards compatibility with SDK < 2.0.0
#define PARAM_ASSERTIONS_ENABLED_HARDWARE_DMA PARAM_ASSERTIONS_ENABLED_DMA
#else
#define PARAM_ASSERTIONS_ENABLED_HARDWARE_DMA 0
#endif
#endif
/**
* \def DMA_IRQ_NUM(n)
* \ingroup hardware_dma
* \hideinitializer
* \brief Returns the \ref irq_num_t for the nth DMA interrupt
*
* Note this macro is intended to resolve at compile time, and does no parameter checking
*/
#ifndef DMA_IRQ_NUM
#define DMA_IRQ_NUM(irq_index) (DMA_IRQ_0 + (irq_index))
#endif
static inline void check_dma_channel_param(__unused uint channel) {
#if PARAM_ASSERTIONS_ENABLED(HARDWARE_DMA)
// this method is used a lot by inline functions so avoid code bloat by deferring to function
extern void check_dma_channel_param_impl(uint channel);
check_dma_channel_param_impl(channel);
#endif
}
static inline void check_dma_timer_param(__unused uint timer_num) {
valid_params_if(HARDWARE_DMA, timer_num < NUM_DMA_TIMERS);
}
inline static dma_channel_hw_t *dma_channel_hw_addr(uint channel) {
check_dma_channel_param(channel);
return &dma_hw->ch[channel];
}
/*! \brief Mark a dma channel as used
* \ingroup hardware_dma
*
* Method for cooperative claiming of hardware. Will cause a panic if the channel
* is already claimed. Use of this method by libraries detects accidental
* configurations that would fail in unpredictable ways.
*
* \param channel the dma channel
*/
void dma_channel_claim(uint channel);
/*! \brief Mark multiple dma channels as used
* \ingroup hardware_dma
*
* Method for cooperative claiming of hardware. Will cause a panic if any of the channels
* are already claimed. Use of this method by libraries detects accidental
* configurations that would fail in unpredictable ways.
*
* \param channel_mask Bitfield of all required channels to claim (bit 0 == channel 0, bit 1 == channel 1 etc)
*/
void dma_claim_mask(uint32_t channel_mask);
/*! \brief Mark a dma channel as no longer used
* \ingroup hardware_dma
*
* \param channel the dma channel to release
*/
void dma_channel_unclaim(uint channel);
/*! \brief Mark multiple dma channels as no longer used
* \ingroup hardware_dma
*
* \param channel_mask Bitfield of all channels to unclaim (bit 0 == channel 0, bit 1 == channel 1 etc)
*/
void dma_unclaim_mask(uint32_t channel_mask);
/*! \brief Claim a free dma channel
* \ingroup hardware_dma
*
* \param required if true the function will panic if none are available
* \return the dma channel number or -1 if required was false, and none were free
*/
int dma_claim_unused_channel(bool required);
/*! \brief Determine if a dma channel is claimed
* \ingroup hardware_dma
*
* \param channel the dma channel
* \return true if the channel is claimed, false otherwise
* \see dma_channel_claim
* \see dma_channel_claim_mask
*/
bool dma_channel_is_claimed(uint channel);
/** \brief DMA channel configuration
* \defgroup channel_config channel_config
* \ingroup hardware_dma
*
* A DMA channel needs to be configured, these functions provide handy helpers to set up configuration
* structures. See \ref dma_channel_config
*/
/*! \brief Enumeration of available DMA channel transfer sizes.
* \ingroup hardware_dma
*
* Names indicate the number of bits.
*/
enum dma_channel_transfer_size {
DMA_SIZE_8 = 0, ///< Byte transfer (8 bits)
DMA_SIZE_16 = 1, ///< Half word transfer (16 bits)
DMA_SIZE_32 = 2 ///< Word transfer (32 bits)
};
typedef struct {
uint32_t ctrl;
} dma_channel_config;
/*! \brief Set DMA channel read increment in a channel configuration object
* \ingroup channel_config
*
* \param c Pointer to channel configuration object
* \param incr True to enable read address increments, if false, each read will be from the same address
* Usually disabled for peripheral to memory transfers
*/
static inline void channel_config_set_read_increment(dma_channel_config *c, bool incr) {
c->ctrl = incr ? (c->ctrl | DMA_CH0_CTRL_TRIG_INCR_READ_BITS) : (c->ctrl & ~DMA_CH0_CTRL_TRIG_INCR_READ_BITS);
}
/*! \brief Set DMA channel write increment in a channel configuration object
* \ingroup channel_config
*
* \param c Pointer to channel configuration object
* \param incr True to enable write address increments, if false, each write will be to the same address
* Usually disabled for memory to peripheral transfers
*/
static inline void channel_config_set_write_increment(dma_channel_config *c, bool incr) {
c->ctrl = incr ? (c->ctrl | DMA_CH0_CTRL_TRIG_INCR_WRITE_BITS) : (c->ctrl & ~DMA_CH0_CTRL_TRIG_INCR_WRITE_BITS);
}
/*! \brief Select a transfer request signal in a channel configuration object
* \ingroup channel_config
*
* The channel uses the transfer request signal to pace its data transfer rate.
* Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).
* 0x0 to 0x3a -> select DREQ n as TREQ
* 0x3b -> Select Timer 0 as TREQ
* 0x3c -> Select Timer 1 as TREQ
* 0x3d -> Select Timer 2 as TREQ (Optional)
* 0x3e -> Select Timer 3 as TREQ (Optional)
* 0x3f -> Permanent request, for unpaced transfers.
*
* \param c Pointer to channel configuration data
* \param dreq Source (see description)
*/
static inline void channel_config_set_dreq(dma_channel_config *c, uint dreq) {
assert(dreq <= DREQ_FORCE);
c->ctrl = (c->ctrl & ~DMA_CH0_CTRL_TRIG_TREQ_SEL_BITS) | (dreq << DMA_CH0_CTRL_TRIG_TREQ_SEL_LSB);
}
/*! \brief Set DMA channel chain_to channel in a channel configuration object
* \ingroup channel_config
*
* When this channel completes, it will trigger the channel indicated by chain_to. Disable by
* setting chain_to to itself (the same channel)
*
* \param c Pointer to channel configuration object
* \param chain_to Channel to trigger when this channel completes.
*/
static inline void channel_config_set_chain_to(dma_channel_config *c, uint chain_to) {
assert(chain_to <= NUM_DMA_CHANNELS);
c->ctrl = (c->ctrl & ~DMA_CH0_CTRL_TRIG_CHAIN_TO_BITS) | (chain_to << DMA_CH0_CTRL_TRIG_CHAIN_TO_LSB);
}
/*! \brief Set the size of each DMA bus transfer in a channel configuration object
* \ingroup channel_config
*
* Set the size of each bus transfer (byte/halfword/word). The read and write addresses
* advance by the specific amount (1/2/4 bytes) with each transfer.
*
* \param c Pointer to channel configuration object
* \param size See enum for possible values.
*/
static inline void channel_config_set_transfer_data_size(dma_channel_config *c, enum dma_channel_transfer_size size) {
assert(size == DMA_SIZE_8 || size == DMA_SIZE_16 || size == DMA_SIZE_32);
c->ctrl = (c->ctrl & ~DMA_CH0_CTRL_TRIG_DATA_SIZE_BITS) | (((uint)size) << DMA_CH0_CTRL_TRIG_DATA_SIZE_LSB);
}
/*! \brief Set address wrapping parameters in a channel configuration object
* \ingroup channel_config
*
* Size of address wrap region. If 0, don’t wrap. For values n > 0, only the lower n bits of the address
* will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned
* ring buffers.
* Ring sizes between 2 and 32768 bytes are possible (size_bits from 1 - 15)
*
* 0x0 -> No wrapping.
*
* \param c Pointer to channel configuration object
* \param write True to apply to write addresses, false to apply to read addresses
* \param size_bits 0 to disable wrapping. Otherwise the size in bits of the changing part of the address.
* Effectively wraps the address on a (1 << size_bits) byte boundary.
*/
static inline void channel_config_set_ring(dma_channel_config *c, bool write, uint size_bits) {
assert(size_bits < 32);
c->ctrl = (c->ctrl & ~(DMA_CH0_CTRL_TRIG_RING_SIZE_BITS | DMA_CH0_CTRL_TRIG_RING_SEL_BITS)) |
(size_bits << DMA_CH0_CTRL_TRIG_RING_SIZE_LSB) |
(write ? DMA_CH0_CTRL_TRIG_RING_SEL_BITS : 0);
}
/*! \brief Set DMA byte swapping config in a channel configuration object
* \ingroup channel_config
*
* No effect for byte data, for halfword data, the two bytes of each halfword are
* swapped. For word data, the four bytes of each word are swapped to reverse their order.
*
* \param c Pointer to channel configuration object
* \param bswap True to enable byte swapping
*/
static inline void channel_config_set_bswap(dma_channel_config *c, bool bswap) {
c->ctrl = bswap ? (c->ctrl | DMA_CH0_CTRL_TRIG_BSWAP_BITS) : (c->ctrl & ~DMA_CH0_CTRL_TRIG_BSWAP_BITS);
}
/*! \brief Set IRQ quiet mode in a channel configuration object
* \ingroup channel_config
*
* In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead,
* an IRQ is raised when NULL is written to a trigger register, indicating the end of a control
* block chain.
*
* \param c Pointer to channel configuration object
* \param irq_quiet True to enable quiet mode, false to disable.
*/
static inline void channel_config_set_irq_quiet(dma_channel_config *c, bool irq_quiet) {
c->ctrl = irq_quiet ? (c->ctrl | DMA_CH0_CTRL_TRIG_IRQ_QUIET_BITS) : (c->ctrl & ~DMA_CH0_CTRL_TRIG_IRQ_QUIET_BITS);
}
/*!
* \brief Set the channel priority in a channel configuration object
* \ingroup channel_config
*
* When true, gives a channel preferential treatment in issue scheduling: in each scheduling round,
* all high priority channels are considered first, and then only a single low
* priority channel, before returning to the high priority channels.
*
* This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed.
* If the DMA is not saturated then a low priority channel will see no loss of throughput.
*
* \param c Pointer to channel configuration object
* \param high_priority True to enable high priority
*/
static inline void channel_config_set_high_priority(dma_channel_config *c, bool high_priority) {
c->ctrl = high_priority ? (c->ctrl | DMA_CH0_CTRL_TRIG_HIGH_PRIORITY_BITS) : (c->ctrl & ~DMA_CH0_CTRL_TRIG_HIGH_PRIORITY_BITS);
}
/*!
* \brief Enable/Disable the DMA channel in a channel configuration object
* \ingroup channel_config
*
* When false, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will
* remain high if already high)
*
* \param c Pointer to channel configuration object
* \param enable True to enable the DMA channel. When enabled, the channel will respond to triggering events, and start transferring data.
*
*/
static inline void channel_config_set_enable(dma_channel_config *c, bool enable) {
c->ctrl = enable ? (c->ctrl | DMA_CH0_CTRL_TRIG_EN_BITS) : (c->ctrl & ~DMA_CH0_CTRL_TRIG_EN_BITS);
}
/*! \brief Enable access to channel by sniff hardware in a channel configuration object
* \ingroup channel_config
*
* Sniff HW must be enabled and have this channel selected.
*
* \param c Pointer to channel configuration object
* \param sniff_enable True to enable the Sniff HW access to this DMA channel.
*/
static inline void channel_config_set_sniff_enable(dma_channel_config *c, bool sniff_enable) {
c->ctrl = sniff_enable ? (c->ctrl | DMA_CH0_CTRL_TRIG_SNIFF_EN_BITS) : (c->ctrl &
~DMA_CH0_CTRL_TRIG_SNIFF_EN_BITS);
}
/*! \brief Get the default channel configuration for a given channel
* \ingroup channel_config
*
* Setting | Default
* --------|--------
* Read Increment | true
* Write Increment | false
* DReq | DREQ_FORCE
* Chain to | self
* Data size | DMA_SIZE_32
* Ring | write=false, size=0 (i.e. off)
* Byte Swap | false
* Quiet IRQs | false
* High Priority | false
* Channel Enable | true
* Sniff Enable | false
*
* \param channel DMA channel
* \return the default configuration which can then be modified.
*/
static inline dma_channel_config dma_channel_get_default_config(uint channel) {
dma_channel_config c = {0};
channel_config_set_read_increment(&c, true);
channel_config_set_write_increment(&c, false);
channel_config_set_dreq(&c, DREQ_FORCE);
channel_config_set_chain_to(&c, channel);
channel_config_set_transfer_data_size(&c, DMA_SIZE_32);
channel_config_set_ring(&c, false, 0);
channel_config_set_bswap(&c, false);
channel_config_set_irq_quiet(&c, false);
channel_config_set_enable(&c, true);
channel_config_set_sniff_enable(&c, false);
channel_config_set_high_priority( &c, false);
return c;
}
/*! \brief Get the current configuration for the specified channel.
* \ingroup channel_config
*
* \param channel DMA channel
* \return The current configuration as read from the HW register (not cached)
*/
static inline dma_channel_config dma_get_channel_config(uint channel) {
dma_channel_config c;
c.ctrl = dma_channel_hw_addr(channel)->ctrl_trig;
return c;
}
/*! \brief Get the raw configuration register from a channel configuration
* \ingroup channel_config
*
* \param config Pointer to a config structure.
* \return Register content
*/
static inline uint32_t channel_config_get_ctrl_value(const dma_channel_config *config) {
return config->ctrl;
}
/*! \brief Set a channel configuration
* \ingroup hardware_dma
*
* \param channel DMA channel
* \param config Pointer to a config structure with required configuration
* \param trigger True to trigger the transfer immediately
*/
static inline void dma_channel_set_config(uint channel, const dma_channel_config *config, bool trigger) {
// Don't use CTRL_TRIG since we don't want to start a transfer
if (!trigger) {
dma_channel_hw_addr(channel)->al1_ctrl = channel_config_get_ctrl_value(config);
} else {
dma_channel_hw_addr(channel)->ctrl_trig = channel_config_get_ctrl_value(config);
}
}
/*! \brief Set the DMA initial read address.
* \ingroup hardware_dma
*
* \param channel DMA channel
* \param read_addr Initial read address of transfer.
* \param trigger True to start the transfer immediately
*/
static inline void dma_channel_set_read_addr(uint channel, const volatile void *read_addr, bool trigger) {
if (!trigger) {
dma_channel_hw_addr(channel)->read_addr = (uintptr_t) read_addr;
} else {
dma_channel_hw_addr(channel)->al3_read_addr_trig = (uintptr_t) read_addr;
}
}
/*! \brief Set the DMA initial write address
* \ingroup hardware_dma
*
* \param channel DMA channel
* \param write_addr Initial write address of transfer.
* \param trigger True to start the transfer immediately
*/
static inline void dma_channel_set_write_addr(uint channel, volatile void *write_addr, bool trigger) {
if (!trigger) {
dma_channel_hw_addr(channel)->write_addr = (uintptr_t) write_addr;
} else {
dma_channel_hw_addr(channel)->al2_write_addr_trig = (uintptr_t) write_addr;
}
}
/*! \brief Set the number of bus transfers the channel will do
* \ingroup hardware_dma
*
* \param channel DMA channel
* \param trans_count The number of transfers (not NOT bytes, see channel_config_set_transfer_data_size)
* \param trigger True to start the transfer immediately
*/
static inline void dma_channel_set_trans_count(uint channel, uint32_t trans_count, bool trigger) {
if (!trigger) {
dma_channel_hw_addr(channel)->transfer_count = trans_count;
} else {
dma_channel_hw_addr(channel)->al1_transfer_count_trig = trans_count;
}
}
/*! \brief Configure all DMA parameters and optionally start transfer
* \ingroup hardware_dma
*
* \param channel DMA channel
* \param config Pointer to DMA config structure
* \param write_addr Initial write address
* \param read_addr Initial read address
* \param transfer_count Number of transfers to perform
* \param trigger True to start the transfer immediately
*/
static inline void dma_channel_configure(uint channel, const dma_channel_config *config, volatile void *write_addr,
const volatile void *read_addr,
uint transfer_count, bool trigger) {
dma_channel_set_read_addr(channel, read_addr, false);
dma_channel_set_write_addr(channel, write_addr, false);
dma_channel_set_trans_count(channel, transfer_count, false);
dma_channel_set_config(channel, config, trigger);
}
/*! \brief Start a DMA transfer from a buffer immediately
* \ingroup hardware_dma
*
* \param channel DMA channel
* \param read_addr Sets the initial read address
* \param transfer_count Number of transfers to make. Not bytes, but the number of transfers of channel_config_set_transfer_data_size() to be sent.
*/
inline static void __attribute__((always_inline)) dma_channel_transfer_from_buffer_now(uint channel,
const volatile void *read_addr,
uint32_t transfer_count) {
// check_dma_channel_param(channel);
dma_channel_hw_t *hw = dma_channel_hw_addr(channel);
hw->read_addr = (uintptr_t) read_addr;
hw->al1_transfer_count_trig = transfer_count;
}
/*! \brief Start a DMA transfer to a buffer immediately
* \ingroup hardware_dma
*
* \param channel DMA channel
* \param write_addr Sets the initial write address
* \param transfer_count Number of transfers to make. Not bytes, but the number of transfers of channel_config_set_transfer_data_size() to be sent.
*/
inline static void dma_channel_transfer_to_buffer_now(uint channel, volatile void *write_addr, uint32_t transfer_count) {
dma_channel_hw_t *hw = dma_channel_hw_addr(channel);
hw->write_addr = (uintptr_t) write_addr;
hw->al1_transfer_count_trig = transfer_count;
}
/*! \brief Start one or more channels simultaneously
* \ingroup hardware_dma
*
* \param chan_mask Bitmask of all the channels requiring starting. Channel 0 = bit 0, channel 1 = bit 1 etc.
*/
static inline void dma_start_channel_mask(uint32_t chan_mask) {
valid_params_if(HARDWARE_DMA, chan_mask && chan_mask < (1u << NUM_DMA_CHANNELS));
dma_hw->multi_channel_trigger = chan_mask;
}
/*! \brief Start a single DMA channel
* \ingroup hardware_dma
*
* \param channel DMA channel
*/
static inline void dma_channel_start(uint channel) {
dma_start_channel_mask(1u << channel);
}
/*! \brief Stop a DMA transfer
* \ingroup hardware_dma
*
* Function will only return once the DMA has stopped.
*
* \if rp2040_specific
* RP2040 only: Note that due to errata RP2040-E13, aborting a channel which has transfers
* in-flight (i.e. an individual read has taken place but the corresponding write has not), the ABORT
* status bit will clear prematurely, and subsequently the in-flight
* transfers will trigger a completion interrupt once they complete.
*\endif
*
* The effect of this is that you \em may see a spurious completion interrupt
* on the channel as a result of calling this method.
*
* The calling code should be sure to ignore a completion IRQ as a result of this method. This may
* not require any additional work, as aborting a channel which may be about to complete, when you have a completion
* IRQ handler registered, is inherently race-prone, and so code is likely needed to disambiguate the two occurrences.
*
* If that is not the case, but you do have a channel completion IRQ handler registered, you can simply
* disable/re-enable the IRQ around the call to this method as shown by this code fragment (using DMA IRQ0).
*
* \code
* // disable the channel on IRQ0
* dma_channel_set_irq0_enabled(channel, false);
* // abort the channel
* dma_channel_abort(channel);
* // clear the spurious IRQ (if there was one)
* dma_channel_acknowledge_irq0(channel);
* // re-enable the channel on IRQ0
* dma_channel_set_irq0_enabled(channel, true);
*\endcode
*
* \if rp2350_specific
* RP2350 only: Due to errata RP12350-E5 (see the RP2350 datasheet for further detail), it is necessary to clear the enable bit of
* the aborted channel and any chained channels prior to the abort to prevent re-triggering.
* \endif
*
* \param channel DMA channel
*/
static inline void dma_channel_abort(uint channel) {
check_dma_channel_param(channel);
dma_hw->abort = 1u << channel;
// Bit will go 0 once channel has reached safe state
// (i.e. any in-flight transfers have retired)
while (dma_hw->ch[channel].ctrl_trig & DMA_CH0_CTRL_TRIG_BUSY_BITS) tight_loop_contents();
}
/*! \brief Enable single DMA channel's interrupt via DMA_IRQ_0
* \ingroup hardware_dma
*
* \param channel DMA channel
* \param enabled true to enable interrupt 0 on specified channel, false to disable.
*/
static inline void dma_channel_set_irq0_enabled(uint channel, bool enabled) {
check_dma_channel_param(channel);
check_hw_layout(dma_hw_t, inte0, DMA_INTE0_OFFSET);
if (enabled)
hw_set_bits(&dma_hw->inte0, 1u << channel);
else
hw_clear_bits(&dma_hw->inte0, 1u << channel);
}
/*! \brief Enable multiple DMA channels' interrupts via DMA_IRQ_0
* \ingroup hardware_dma
*
* \param channel_mask Bitmask of all the channels to enable/disable. Channel 0 = bit 0, channel 1 = bit 1 etc.
* \param enabled true to enable all the interrupts specified in the mask, false to disable all the interrupts specified in the mask.
*/
static inline void dma_set_irq0_channel_mask_enabled(uint32_t channel_mask, bool enabled) {
if (enabled) {
hw_set_bits(&dma_hw->inte0, channel_mask);
} else {
hw_clear_bits(&dma_hw->inte0, channel_mask);
}
}
/*! \brief Enable single DMA channel's interrupt via DMA_IRQ_1
* \ingroup hardware_dma
*
* \param channel DMA channel
* \param enabled true to enable interrupt 1 on specified channel, false to disable.
*/
static inline void dma_channel_set_irq1_enabled(uint channel, bool enabled) {
check_dma_channel_param(channel);
check_hw_layout(dma_hw_t, inte1, DMA_INTE1_OFFSET);
if (enabled)
hw_set_bits(&dma_hw->inte1, 1u << channel);
else
hw_clear_bits(&dma_hw->inte1, 1u << channel);
}
/*! \brief Enable multiple DMA channels' interrupts via DMA_IRQ_1
* \ingroup hardware_dma
*
* \param channel_mask Bitmask of all the channels to enable/disable. Channel 0 = bit 0, channel 1 = bit 1 etc.
* \param enabled true to enable all the interrupts specified in the mask, false to disable all the interrupts specified in the mask.
*/
static inline void dma_set_irq1_channel_mask_enabled(uint32_t channel_mask, bool enabled) {
if (enabled) {
hw_set_bits(&dma_hw->inte1, channel_mask);
} else {
hw_clear_bits(&dma_hw->inte1, channel_mask);
}
}
/*! \brief Enable single DMA channel interrupt on either DMA_IRQ_0 or DMA_IRQ_1
* \ingroup hardware_dma
*
* \param irq_index the IRQ index; either 0 or 1 for DMA_IRQ_0 or DMA_IRQ_1
* \param channel DMA channel
* \param enabled true to enable interrupt via irq_index for specified channel, false to disable.
*/
static inline void dma_irqn_set_channel_enabled(uint irq_index, uint channel, bool enabled) {
invalid_params_if(HARDWARE_DMA, irq_index >= NUM_DMA_IRQS);
if (enabled)
hw_set_bits(&dma_hw->irq_ctrl[irq_index].inte, 1u << channel);
else
hw_clear_bits(&dma_hw->irq_ctrl[irq_index].inte, 1u << channel);
}
/*! \brief Enable multiple DMA channels' interrupt via either DMA_IRQ_0 or DMA_IRQ_1
* \ingroup hardware_dma
*
* \param irq_index the IRQ index; either 0 or 1 for DMA_IRQ_0 or DMA_IRQ_1
* \param channel_mask Bitmask of all the channels to enable/disable. Channel 0 = bit 0, channel 1 = bit 1 etc.
* \param enabled true to enable all the interrupts specified in the mask, false to disable all the interrupts specified in the mask.
*/
static inline void dma_irqn_set_channel_mask_enabled(uint irq_index, uint32_t channel_mask, bool enabled) {
invalid_params_if(HARDWARE_DMA, irq_index >= NUM_DMA_IRQS);
if (enabled) {
hw_set_bits(&dma_hw->irq_ctrl[irq_index].inte, channel_mask);
} else {
hw_clear_bits(&dma_hw->irq_ctrl[irq_index].inte, channel_mask);
}
}
/*! \brief Determine if a particular channel is a cause of DMA_IRQ_0
* \ingroup hardware_dma
*
* \param channel DMA channel
* \return true if the channel is a cause of DMA_IRQ_0, false otherwise
*/
static inline bool dma_channel_get_irq0_status(uint channel) {
check_dma_channel_param(channel);
return dma_hw->ints0 & (1u << channel);
}
/*! \brief Determine if a particular channel is a cause of DMA_IRQ_1
* \ingroup hardware_dma
*
* \param channel DMA channel
* \return true if the channel is a cause of DMA_IRQ_1, false otherwise
*/
static inline bool dma_channel_get_irq1_status(uint channel) {
check_dma_channel_param(channel);
return dma_hw->ints1 & (1u << channel);
}
/*! \brief Determine if a particular channel is a cause of DMA_IRQ_N
* \ingroup hardware_dma
*
* \param irq_index the IRQ index; either 0 or 1 for DMA_IRQ_0 or DMA_IRQ_1
* \param channel DMA channel
* \return true if the channel is a cause of the DMA_IRQ_N, false otherwise
*/
static inline bool dma_irqn_get_channel_status(uint irq_index, uint channel) {
invalid_params_if(HARDWARE_DMA, irq_index >= NUM_DMA_IRQS);
check_dma_channel_param(channel);
return dma_hw->irq_ctrl[irq_index].ints & (1u << channel);
}
/*! \brief Acknowledge a channel IRQ, resetting it as the cause of DMA_IRQ_0
* \ingroup hardware_dma
*
* \param channel DMA channel
*/
static inline void dma_channel_acknowledge_irq0(uint channel) {
check_dma_channel_param(channel);
dma_hw->ints0 = 1u << channel;
}
/*! \brief Acknowledge a channel IRQ, resetting it as the cause of DMA_IRQ_1
* \ingroup hardware_dma
*
* \param channel DMA channel
*/
static inline void dma_channel_acknowledge_irq1(uint channel) {
check_dma_channel_param(channel);
dma_hw->ints1 = 1u << channel;
}
/*! \brief Acknowledge a channel IRQ, resetting it as the cause of DMA_IRQ_N
* \ingroup hardware_dma
*
* \param irq_index the IRQ index; either 0 or 1 for DMA_IRQ_0 or DMA_IRQ_1
* \param channel DMA channel
*/
static inline void dma_irqn_acknowledge_channel(uint irq_index, uint channel) {
invalid_params_if(HARDWARE_DMA, irq_index >= NUM_DMA_IRQS);
check_dma_channel_param(channel);
dma_hw->irq_ctrl[irq_index].ints = 1u << channel;
}
/*! \brief Check if DMA channel is busy
* \ingroup hardware_dma
*
* \param channel DMA channel
* \return true if the channel is currently busy
*/
inline static bool dma_channel_is_busy(uint channel) {
check_dma_channel_param(channel);
return dma_hw->ch[channel].al1_ctrl & DMA_CH0_CTRL_TRIG_BUSY_BITS;
}
/*! \brief Wait for a DMA channel transfer to complete
* \ingroup hardware_dma
*
* \param channel DMA channel
*/
inline static void dma_channel_wait_for_finish_blocking(uint channel) {
while (dma_channel_is_busy(channel)) tight_loop_contents();
// stop the compiler hoisting a non-volatile buffer access above the DMA completion.
__compiler_memory_barrier();
}
/*! \brief Enable the DMA sniffing targeting the specified channel
* \ingroup hardware_dma
*
* The mode can be one of the following:
*
* Mode | Function
* -----|---------
* 0x0 | Calculate a CRC-32 (IEEE802.3 polynomial)
* 0x1 | Calculate a CRC-32 (IEEE802.3 polynomial) with bit reversed data
* 0x2 | Calculate a CRC-16-CCITT
* 0x3 | Calculate a CRC-16-CCITT with bit reversed data
* 0xe | XOR reduction over all data. == 1 if the total 1 population count is odd.
* 0xf | Calculate a simple 32-bit checksum (addition with a 32 bit accumulator)
*
* \param channel DMA channel
* \param mode See description
* \param force_channel_enable Set true to also turn on sniffing in the channel configuration (this
* is usually what you want, but sometimes you might have a chain DMA with only certain segments
* of the chain sniffed, in which case you might pass false).
*/
inline static void dma_sniffer_enable(uint channel, uint mode, bool force_channel_enable) {
check_dma_channel_param(channel);
check_hw_layout(dma_hw_t, sniff_ctrl, DMA_SNIFF_CTRL_OFFSET);
if (force_channel_enable) {
hw_set_bits(&dma_hw->ch[channel].al1_ctrl, DMA_CH0_CTRL_TRIG_SNIFF_EN_BITS);
}
hw_write_masked(&dma_hw->sniff_ctrl,
(((channel << DMA_SNIFF_CTRL_DMACH_LSB) & DMA_SNIFF_CTRL_DMACH_BITS) |
((mode << DMA_SNIFF_CTRL_CALC_LSB) & DMA_SNIFF_CTRL_CALC_BITS) |
DMA_SNIFF_CTRL_EN_BITS),
(DMA_SNIFF_CTRL_DMACH_BITS |
DMA_SNIFF_CTRL_CALC_BITS |
DMA_SNIFF_CTRL_EN_BITS));
}
/*! \brief Enable the Sniffer byte swap function
* \ingroup hardware_dma
*
* Locally perform a byte reverse on the sniffed data, before feeding into checksum.
*
* Note that the sniff hardware is downstream of the DMA channel byteswap performed in the
* read master: if channel_config_set_bswap() and dma_sniffer_set_byte_swap_enabled() are both enabled,
* their effects cancel from the sniffer’s point of view.
*
* \param swap Set true to enable byte swapping
*/
inline static void dma_sniffer_set_byte_swap_enabled(bool swap) {
if (swap)
hw_set_bits(&dma_hw->sniff_ctrl, DMA_SNIFF_CTRL_BSWAP_BITS);
else
hw_clear_bits(&dma_hw->sniff_ctrl, DMA_SNIFF_CTRL_BSWAP_BITS);
}
/*! \brief Enable the Sniffer output invert function
* \ingroup hardware_dma
*
* If enabled, the sniff data result appears bit-inverted when read.
* This does not affect the way the checksum is calculated.
*
* \param invert Set true to enable output bit inversion
*/
inline static void dma_sniffer_set_output_invert_enabled(bool invert) {
if (invert)
hw_set_bits(&dma_hw->sniff_ctrl, DMA_SNIFF_CTRL_OUT_INV_BITS);
else
hw_clear_bits(&dma_hw->sniff_ctrl, DMA_SNIFF_CTRL_OUT_INV_BITS);
}
/*! \brief Enable the Sniffer output bit reversal function
* \ingroup hardware_dma
*
* If enabled, the sniff data result appears bit-reversed when read.
* This does not affect the way the checksum is calculated.
*
* \param reverse Set true to enable output bit reversal
*/
inline static void dma_sniffer_set_output_reverse_enabled(bool reverse) {
if (reverse)
hw_set_bits(&dma_hw->sniff_ctrl, DMA_SNIFF_CTRL_OUT_REV_BITS);
else
hw_clear_bits(&dma_hw->sniff_ctrl, DMA_SNIFF_CTRL_OUT_REV_BITS);
}
/*! \brief Disable the DMA sniffer
* \ingroup hardware_dma
*
*/
inline static void dma_sniffer_disable(void) {
dma_hw->sniff_ctrl = 0;
}
/*! \brief Set the sniffer's data accumulator with initial value
* \ingroup hardware_dma
*
* Generally, CRC algorithms are used with the data accumulator initially
* seeded with 0xFFFF or 0xFFFFFFFF (for crc16 and crc32 algorithms)
*
* \param seed_value value to set data accumulator
*/
inline static void dma_sniffer_set_data_accumulator(uint32_t seed_value) {
dma_hw->sniff_data = seed_value;
}
/*! \brief Get the sniffer's data accumulator value
* \ingroup hardware_dma
*
* Read value calculated by the hardware from sniffing the DMA stream
*/
inline static uint32_t dma_sniffer_get_data_accumulator(void) {
return dma_hw->sniff_data;
}
/*! \brief Mark a dma timer as used
* \ingroup hardware_dma
*
* Method for cooperative claiming of hardware. Will cause a panic if the timer
* is already claimed. Use of this method by libraries detects accidental
* configurations that would fail in unpredictable ways.
*
* \param timer the dma timer
*/
void dma_timer_claim(uint timer);
/*! \brief Mark a dma timer as no longer used
* \ingroup hardware_dma
*
* Method for cooperative claiming of hardware.
*
* \param timer the dma timer to release
*/
void dma_timer_unclaim(uint timer);
/*! \brief Claim a free dma timer
* \ingroup hardware_dma
*
* \param required if true the function will panic if none are available
* \return the dma timer number or -1 if required was false, and none were free
*/
int dma_claim_unused_timer(bool required);
/*! \brief Determine if a dma timer is claimed
* \ingroup hardware_dma
*
* \param timer the dma timer
* \return true if the timer is claimed, false otherwise
* \see dma_timer_claim
*/
bool dma_timer_is_claimed(uint timer);
/*! \brief Set the multiplier for the given DMA timer
* \ingroup hardware_dma
*
* The timer will run at the system_clock_freq * numerator / denominator, so this is the speed
* that data elements will be transferred at via a DMA channel using this timer as a DREQ. The
* multiplier must be less than or equal to one.
*
* \param timer the dma timer
* \param numerator the fraction's numerator
* \param denominator the fraction's denominator
*/
static inline void dma_timer_set_fraction(uint timer, uint16_t numerator, uint16_t denominator) {
check_dma_timer_param(timer);
invalid_params_if(HARDWARE_DMA, numerator > denominator);
dma_hw->timer[timer] = (((uint32_t)numerator) << DMA_TIMER0_X_LSB) | (((uint32_t)denominator) << DMA_TIMER0_Y_LSB);
}
/*! \brief Return the DREQ number for a given DMA timer
* \ingroup hardware_dma
*
* \param timer_num DMA timer number 0-3
*/
static inline uint dma_get_timer_dreq(uint timer_num) {
static_assert(DREQ_DMA_TIMER1 == DREQ_DMA_TIMER0 + 1, "");
static_assert(DREQ_DMA_TIMER2 == DREQ_DMA_TIMER0 + 2, "");
static_assert(DREQ_DMA_TIMER3 == DREQ_DMA_TIMER0 + 3, "");
check_dma_timer_param(timer_num);
return DREQ_DMA_TIMER0 + timer_num;
}
/*! \brief Return DMA_IRQ_<irqn>
* \ingroup hardware_dma
*
* \param irq_index 0 the DMA irq index
* \return The \ref irq_num_to use for DMA
*/
static inline int dma_get_irq_num(uint irq_index) {
valid_params_if(HARDWARE_DMA, irq_index < NUM_DMA_IRQS);
return DMA_IRQ_NUM(irq_index);
}
/*! \brief Performs DMA channel cleanup after use
* \ingroup hardware_dma
*
* This can be used to cleanup dma channels when they're no longer needed, such that they are in a clean state for reuse.
* IRQ's for the channel are disabled, any in flight-transfer is aborted and any outstanding interrupts are cleared.
* The channel is then clear to be reused for other purposes.
*
* \code
* if (dma_channel >= 0) {
* dma_channel_cleanup(dma_channel);
* dma_channel_unclaim(dma_channel);
* dma_channel = -1;
* }
* \endcode
*
* \param channel DMA channel
*/
void dma_channel_cleanup(uint channel);
#ifndef NDEBUG
void print_dma_ctrl(dma_channel_hw_t *channel);
#endif
#ifdef __cplusplus
}
#endif
#endif

194
arch/arm/src/rp23xx/hardware/exception.h
View file

@ -1,194 +0,0 @@
/*
* Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _HARDWARE_EXCEPTION_H
#define _HARDWARE_EXCEPTION_H
#include "pico.h"
#include "hardware/address_mapped.h"
/** \file exception.h
* \defgroup hardware_exception hardware_exception
*
* \brief Methods for setting processor exception handlers
*
* Exceptions are identified by a \ref exception_number which is a number from -15 to -1; these are the numbers relative to
* the index of the first IRQ vector in the vector table. (i.e. vector table index is exception_num plus 16)
*
* There is one set of exception handlers per core, so the exception handlers for each core as set by these methods are independent.
*
* \note That all exception APIs affect the executing core only (i.e. the core calling the function).
*/
// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_HARDWARE_EXCEPTION, Enable/disable assertions in the hardware_exception module, type=bool, default=0, group=hardware_exception
#ifndef PARAM_ASSERTIONS_ENABLED_HARDWARE_EXCEPTION
#ifdef PARAM_ASSERTIONS_ENABLED_EXCEPTION // backwards compatibility with SDK < 2.0.0
#define PARAM_ASSERTIONS_ENABLED_HARDWARE_EXCEPTION PARAM_ASSERTIONS_ENABLED_EXCEPTION
#else
#define PARAM_ASSERTIONS_ENABLED_HARDWARE_EXCEPTION 0
#endif
#endif
#ifdef __cplusplus
extern "C" {
#endif
/*! \brief Exception number definitions
*
* On Arm these are vector table indices:
*
* Name | Value | Exception
* ---------------------|-------|-----------------------
* NMI_EXCEPTION | 2 | Non Maskable Interrupt
* HARDFAULT_EXCEPTION | 3 | HardFault
* SVCALL_EXCEPTION | 11 | SV Call
* PENDSV_EXCEPTION | 14 | Pend SV
* SYSTICK_EXCEPTION | 15 | System Tick
*
* \if rp2350_specific
* On RISC-V these are exception cause numbers:
*
* Name | Value | Exception
* ------------------------|-------|-----------------------------
* INSTR_ALIGN_EXCEPTION | 0 | Instruction fetch misaligned
* INSTR_FAULT_EXCEPTION | 1 | Instruction fetch bus fault
* INSTR_ILLEGAL_EXCEPTION | 2 | Invalid or illegal instruction
* EBREAK_EXCEPTION | 3 | ebreak was not caught by an ex
* LOAD_ALIGN_EXCEPTION | 4 | Load address not naturally ali
* LOAD_FAULT_EXCEPTION | 5 | Load bus fault
* STORE_ALIGN_EXCEPTION | 6 | Store or AMO address not natur
* STORE_FAULT_EXCEPTION | 7 | Store or AMO bus fault
* ECALL_UMODE_EXCEPTION | 8 | ecall was executed in U-mode
* ECALL_SMODE_EXCEPTION | 9 | ecall was executed in S-mode
* ECALL_MMODE_EXCEPTION | 11 | ecall was executed in M-mode
* \endif
*
* \ingroup hardware_exception
*/
#ifdef __riscv
enum exception_number {
// Assigned to non-IRQ xcause values
MIN_EXCEPTION_NUM = 0,
INSTR_ALIGN_EXCEPTION = 0, ///< Instruction fetch misaligned (never fires if C/Zca is present)
INSTR_FAULT_EXCEPTION = 1, ///< Instruction fetch bus fault
INSTR_ILLEGAL_EXCEPTION = 2, ///< Invalid or illegal instruction
EBREAK_EXCEPTION = 3, ///< ebreak was not caught by an external debugger
LOAD_ALIGN_EXCEPTION = 4, ///< Load address not naturally aligned
LOAD_FAULT_EXCEPTION = 5, ///< Load bus fault
STORE_ALIGN_EXCEPTION = 6, ///< Store or AMO address not naturally aligned
STORE_FAULT_EXCEPTION = 7, ///< Store or AMO bus fault
ECALL_UMODE_EXCEPTION = 8, ///< ecall was executed in U-mode
ECALL_SMODE_EXCEPTION = 9, ///< ecall was executed in S-mode
ECALL_MMODE_EXCEPTION = 11, ///< ecall was executed in M-mode
MAX_EXCEPTION_NUM = 11
};
#else
enum exception_number {
// Assigned to VTOR indices
MIN_EXCEPTION_NUM = 2,
NMI_EXCEPTION = 2, ///< Non Maskable Interrupt
HARDFAULT_EXCEPTION = 3, ///< HardFault Interrupt
SVCALL_EXCEPTION = 11, ///< SV Call Interrupt
PENDSV_EXCEPTION = 14, ///< Pend SV Interrupt
SYSTICK_EXCEPTION = 15, ///< System Tick Interrupt
MAX_EXCEPTION_NUM = 15
};
#endif
#define PICO_LOWEST_EXCEPTION_PRIORITY 0xff
#define PICO_HIGHEST_EXCEPTION_PRIORITY 0x00
/*! \brief Exception handler function type
* \ingroup hardware_exception
*
* All exception handlers should be of this type, and follow normal ARM EABI register saving conventions
*/
typedef void (*exception_handler_t)(void);
/*! \brief Set the exception handler for an exception on the executing core.
* \ingroup hardware_exception
*
* This method will assert if an exception handler has been set for this exception number on this core via
* this method, without an intervening restore via exception_restore_handler.
*
* \note this method may not be used to override an exception handler that was specified at link time by
* providing a strong replacement for the weakly defined stub exception handlers. It will assert in this case too.
*
* \param num Exception number
* \param handler The handler to set
* \see exception_number
*/
exception_handler_t exception_set_exclusive_handler(enum exception_number num, exception_handler_t handler);
/*! \brief Restore the original exception handler for an exception on this core
* \ingroup hardware_exception
*
* This method may be used to restore the exception handler for an exception on this core to the state
* prior to the call to exception_set_exclusive_handler(), so that exception_set_exclusive_handler()
* may be called again in the future.
*
* \param num Exception number \ref exception_number
* \param original_handler The original handler returned from \ref exception_set_exclusive_handler
* \see exception_set_exclusive_handler()
*/
void exception_restore_handler(enum exception_number num, exception_handler_t original_handler);
/*! \brief Get the current exception handler for the specified exception from the currently installed vector table
* of the execution core
* \ingroup hardware_exception
*
* \param num Exception number
* \return the address stored in the VTABLE for the given exception number
*/
exception_handler_t exception_get_vtable_handler(enum exception_number num);
#ifndef __riscv
/*! \brief Set specified exception's priority
* \ingroup hardware_exception
*
* \param num Exception number \ref exception_number
* \param hardware_priority Priority to set.
*
* Numerically-lower values indicate a higher priority. Hardware priorities
* range from 0 (highest priority) to 255 (lowest priority).
*
* \if rp2040_specific
* Only the top 2 bits are significant on ARM Cortex-M0+ on RP2040.
* \endif
*
* \if rp2350_specific
* Only the top 4 bits are significant on ARM Cortex-M33 on RP2350, and exception priorities
* are not supported on RISC-V
* \endif
*/
bool exception_set_priority(uint num, uint8_t hardware_priority);
/*! \brief Get specified exception's priority
* \ingroup hardware_exception
*
* Numerically-lower values indicate a higher priority. Hardware priorities
* range from 0 (highest priority) to 255 (lowest priority).
*
* \if rp2040_specific
* Only the top 2 bits are significant on ARM Cortex-M0+ on RP2040.
* \endif
*
* \if rp2350_specific
* Only the top 4 bits are significant on ARM Cortex-M33 on RP2350, and exception priorities
* are not supported on RISC-V
* \endif
*
* \param num Exception number \ref exception_number
* \return the exception priority
*/
uint exception_get_priority(uint num);
#endif
#ifdef __cplusplus
}
#endif
#endif

126
arch/arm/src/rp23xx/hardware/flash.h
View file

@ -1,126 +0,0 @@
/*
* Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _HARDWARE_FLASH_H
#define _HARDWARE_FLASH_H
#include "pico.h"
/** \file flash.h
* \defgroup hardware_flash hardware_flash
*
* \brief Low level flash programming and erase API
*
* Note these functions are *unsafe* if you are using both cores, and the other
* is executing from flash concurrently with the operation. In this could be the
* case, you must perform your own synchronisation to make sure that no XIP
* accesses take place during flash programming. One option is to use the
* \ref multicore_lockout functions.
*
* Likewise they are *unsafe* if you have interrupt handlers or an interrupt
* vector table in flash, so you must disable interrupts before calling in
* this case.
*
* If PICO_NO_FLASH=1 is not defined (i.e. if the program is built to run from
* flash) then these functions will make a static copy of the second stage
* bootloader in SRAM, and use this to reenter execute-in-place mode after
* programming or erasing flash, so that they can safely be called from
* flash-resident code.
*
* \subsection flash_example Example
* \include flash_program.c
*/
// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_HARDWARE_FLASH, Enable/disable assertions in the hardware_flash module, type=bool, default=0, group=hardware_flash
#ifndef PARAM_ASSERTIONS_ENABLED_HARDWARE_FLASH
#ifdef PARAM_ASSERTIONS_ENABLED_FLASH // backwards compatibility with SDK < 2.0.0
#define PARAM_ASSERTIONS_ENABLED_HARDWARE_FLASH PARAM_ASSERTIONS_ENABLED_FLASH
#else
#define PARAM_ASSERTIONS_ENABLED_HARDWARE_FLASH 0
#endif
#endif
#define FLASH_PAGE_SIZE (1u << 8)
#define FLASH_SECTOR_SIZE (1u << 12)
#define FLASH_BLOCK_SIZE (1u << 16)
#define FLASH_UNIQUE_ID_SIZE_BYTES 8
// PICO_CONFIG: PICO_FLASH_SIZE_BYTES, size of primary flash in bytes, type=int, default=Usually provided via board header, group=hardware_flash
#ifdef __cplusplus
extern "C" {
#endif
/*! \brief Erase areas of flash
* \ingroup hardware_flash
*
* \param flash_offs Offset into flash, in bytes, to start the erase. Must be aligned to a 4096-byte flash sector.
* \param count Number of bytes to be erased. Must be a multiple of 4096 bytes (one sector).
*
* @note Erasing a flash sector sets all the bits in all the pages in that sector to one.
* You can then "program" flash pages in the sector to turn some of the bits to zero.
* Once a bit is set to zero it can only be changed back to one by erasing the whole sector again.
*/
void flash_range_erase(uint32_t flash_offs, size_t count);
/*! \brief Program flash
* \ingroup hardware_flash
*
* \param flash_offs Flash address of the first byte to be programmed. Must be aligned to a 256-byte flash page.
* \param data Pointer to the data to program into flash
* \param count Number of bytes to program. Must be a multiple of 256 bytes (one page).
*
* @note: Programming a flash page effectively changes some of the bits from one to zero.
* The only way to change a zero bit back to one is to "erase" the whole sector that the page resides in.
* So you may need to make sure you have called flash_range_erase before calling flash_range_program.
*/
void flash_range_program(uint32_t flash_offs, const uint8_t *data, size_t count);
/*! \brief Get flash unique 64 bit identifier
* \ingroup hardware_flash
*
* Use a standard 4Bh RUID instruction to retrieve the 64 bit unique
* identifier from a flash device attached to the QSPI interface. Since there
* is a 1:1 association between the MCU and this flash, this also serves as a
* unique identifier for the board.
*
* \param id_out Pointer to an 8-byte buffer to which the ID will be written
*/
void flash_get_unique_id(uint8_t *id_out);
/*! \brief Execute bidirectional flash command
* \ingroup hardware_flash
*
* Low-level function to execute a serial command on a flash device attached
* to the QSPI interface. Bytes are simultaneously transmitted and received
* from txbuf and to rxbuf. Therefore, both buffers must be the same length,
* count, which is the length of the overall transaction. This is useful for
* reading metadata from the flash chip, such as device ID or SFDP
* parameters.
*
* The XIP cache is flushed following each command, in case flash state
* has been modified. Like other hardware_flash functions, the flash is not
* accessible for execute-in-place transfers whilst the command is in
* progress, so entering a flash-resident interrupt handler or executing flash
* code on the second core concurrently will be fatal. To avoid these pitfalls
* it is recommended that this function only be used to extract flash metadata
* during startup, before the main application begins to run: see the
* implementation of pico_get_unique_id() for an example of this.
*
* \param txbuf Pointer to a byte buffer which will be transmitted to the flash
* \param rxbuf Pointer to a byte buffer where data received from the flash will be written. txbuf and rxbuf may be the same buffer.
* \param count Length in bytes of txbuf and of rxbuf
*/
void flash_do_cmd(const uint8_t *txbuf, uint8_t *rxbuf, size_t count);
void flash_flush_cache(void);
#ifdef __cplusplus
}
#endif
#endif

1435
arch/arm/src/rp23xx/hardware/gpio.h
View file

File diff suppressed because it is too large Load diff

465
arch/arm/src/rp23xx/hardware/gpio_coproc.h
View file

@ -1,465 +0,0 @@
/*
* Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _HARDWARE_GPIO_COPROC_H
#define _HARDWARE_GPIO_COPROC_H
#ifdef __riscv
#error "GPIO coprocessor port is not available on RISC-V"
#endif
#if PICO_RP2040
#error "GPIO coprocessor is not available on RP2040"
#endif
#if !HAS_GPIO_COPROCESSOR
#error "GPIO coprocessor is not available"
#endif
#include "pico.h"
// ----------------------------------------------------------------------------
// OUT mask write instructions
// Equivalent to sio_hw->gpio_out = x;
__force_inline static void gpioc_lo_out_put(uint32_t x) {
pico_default_asm_volatile ("mcr p0, #0, %0, c0, c0" : : "r" (x));
}
// Equivalent to sio_hw->gpio_togl = x;
__force_inline static void gpioc_lo_out_xor(uint32_t x) {
pico_default_asm_volatile ("mcr p0, #1, %0, c0, c0" : : "r" (x));
}
// Equivalent to sio_hw->gpio_set = x;
__force_inline static void gpioc_lo_out_set(uint32_t x) {
pico_default_asm_volatile ("mcr p0, #2, %0, c0, c0" : : "r" (x));
}
// Equivalent to sio_hw->gpio_clr = x;
__force_inline static void gpioc_lo_out_clr(uint32_t x) {
pico_default_asm_volatile ("mcr p0, #3, %0, c0, c0" : : "r" (x));
}
// Equivalent to sio_hw->gpio_hi_out = x;
__force_inline static void gpioc_hi_out_put(uint32_t x) {
pico_default_asm_volatile ("mcr p0, #0, %0, c0, c1" : : "r" (x));
}
// Equivalent to sio_hw->gpio_hi_togl = x;
__force_inline static void gpioc_hi_out_xor(uint32_t x) {
pico_default_asm_volatile ("mcr p0, #1, %0, c0, c1" : : "r" (x));
}
// Equivalent to sio_hw->gpio_hi_set = x;
__force_inline static void gpioc_hi_out_set(uint32_t x) {
pico_default_asm_volatile ("mcr p0, #2, %0, c0, c1" : : "r" (x));
}
// Equivalent to sio_hw->gpio_hi_clr = x;
__force_inline static void gpioc_hi_out_clr(uint32_t x) {
pico_default_asm_volatile ("mcr p0, #3, %0, c0, c1" : : "r" (x));
}
// Equivalent to these two operations performed on the same cycle:
// - sio_hw->gpio_out = x & 0xffffffff;
// - sio_hw->gpio_hi_out = x >> 32;
__force_inline static void gpioc_hilo_out_put(uint64_t x) {
pico_default_asm_volatile ("mcrr p0, #0, %0, %1, c0" : : "r" (x & 0xffffffffu), "r" (x >> 32));
}
// Equivalent to these two operations performed on the same cycle:
// - sio_hw->gpio_togl = x & 0xffffffff;
// - sio_hw->gpio_hi_togl = x >> 32;
__force_inline static void gpioc_hilo_out_xor(uint64_t x) {
pico_default_asm_volatile ("mcrr p0, #1, %0, %1, c0" : : "r" (x & 0xffffffffu), "r" (x >> 32));
}
// Equivalent to these two operations performed on the same cycle:
// - sio_hw->gpio_set = x & 0xffffffff;
// - sio_hw->gpio_hi_set = x >> 32;
__force_inline static void gpioc_hilo_out_set(uint64_t x) {
pico_default_asm_volatile ("mcrr p0, #2, %0, %1, c0" : : "r" (x & 0xffffffffu), "r" (x >> 32));
}
// Equivalent to these two operations performed on the same cycle:
// - sio_hw->gpio_clr = x & 0xffffffff;
// - sio_hw->gpio_hi_clr = x >> 32;
__force_inline static void gpioc_hilo_out_clr(uint64_t x) {
pico_default_asm_volatile ("mcrr p0, #3, %0, %1, c0" : : "r" (x & 0xffffffffu), "r" (x >> 32));
}
// ----------------------------------------------------------------------------
// OE mask write instructions
// Equivalent to sio_hw->gpio_oe = x;
__force_inline static void gpioc_lo_oe_put(uint32_t x) {
pico_default_asm_volatile ("mcr p0, #0, %0, c0, c4" : : "r" (x));
}
// Equivalent to sio_hw->gpio_oe_togl = x;
__force_inline static void gpioc_lo_oe_xor(uint32_t x) {
pico_default_asm_volatile ("mcr p0, #1, %0, c0, c4" : : "r" (x));
}
// Equivalent to sio_hw->gpio_oe_set = x;
__force_inline static void gpioc_lo_oe_set(uint32_t x) {
pico_default_asm_volatile ("mcr p0, #2, %0, c0, c4" : : "r" (x));
}
// Equivalent to sio_hw->gpio_oe_clr = x;
__force_inline static void gpioc_lo_oe_clr(uint32_t x) {
pico_default_asm_volatile ("mcr p0, #3, %0, c0, c4" : : "r" (x));
}
// Equivalent to sio_hw->gpio_hi_oe = x;
__force_inline static void gpioc_hi_oe_put(uint32_t x) {
pico_default_asm_volatile ("mcr p0, #0, %0, c0, c5" : : "r" (x));
}
// Equivalent to sio_hw->gpio_hi_oe_togl = x;
__force_inline static void gpioc_hi_oe_xor(uint32_t x) {
pico_default_asm_volatile ("mcr p0, #1, %0, c0, c5" : : "r" (x));
}
// Equivalent to sio_hw->gpio_hi_oe_set = x;
__force_inline static void gpioc_hi_oe_set(uint32_t x) {
pico_default_asm_volatile ("mcr p0, #2, %0, c0, c5" : : "r" (x));
}
// Equivalent to sio_hw->gpio_hi_oe_clr = x;
__force_inline static void gpioc_hi_oe_clr(uint32_t x) {
pico_default_asm_volatile ("mcr p0, #3, %0, c0, c5" : : "r" (x));
}
// Equivalent to these two operations performed on the same cycle:
// - sio_hw->gpio_oe = x & 0xffffffff;
// - sio_hw->gpio_hi_oe = x >> 32;
__force_inline static void gpioc_hilo_oe_put(uint64_t x) {
pico_default_asm_volatile ("mcrr p0, #0, %0, %1, c4" : : "r" (x & 0xffffffffu), "r" (x >> 32));
}
// Equivalent to these two operations performed on the same cycle:
// - sio_hw->gpio_oe_togl = x & 0xffffffff;
// - sio_hw->gpio_hi_oe_togl = x >> 32;
__force_inline static void gpioc_hilo_oe_xor(uint64_t x) {
pico_default_asm_volatile ("mcrr p0, #1, %0, %1, c4" : : "r" (x & 0xffffffffu), "r" (x >> 32));
}
// Equivalent to these two operations performed on the same cycle:
// - sio_hw->gpio_oe_set = x & 0xffffffff;
// - sio_hw->gpio_hi_oe_set = x >> 32;
__force_inline static void gpioc_hilo_oe_set(uint64_t x) {
pico_default_asm_volatile ("mcrr p0, #2, %0, %1, c4" : : "r" (x & 0xffffffffu), "r" (x >> 32));
}
// Equivalent to these two operations performed on the same cycle:
// - sio_hw->gpio_oe_clr = x & 0xffffffff;
// - sio_hw->gpio_hi_oe_clr = x >> 32;
__force_inline static void gpioc_hilo_oe_clr(uint64_t x) {
pico_default_asm_volatile ("mcrr p0, #3, %0, %1, c4" : : "r" (x & 0xffffffffu), "r" (x >> 32));
}
// ----------------------------------------------------------------------------
// Single-bit write instructions
// Write a 1-bit value to any output. Equivalent to:
//
// if (val)
// gpioc_hilo_out_set(1ull << pin);
// else
// gpioc_hilo_out_clr(1ull << pin);
__force_inline static void gpioc_bit_out_put(uint pin, bool val) {
pico_default_asm_volatile ("mcrr p0, #4, %0, %1, c0" : : "r" (pin), "r" (val));
}
// Unconditionally toggle any single output. Equivalent to:
//
// gpioc_hilo_out_xor(1ull << pin);
__force_inline static void gpioc_bit_out_xor(uint pin) {
pico_default_asm_volatile ("mcr p0, #5, %0, c0, c0" : : "r" (pin));
}
// Unconditionally set any single output. Equivalent to:
//
// gpioc_hilo_out_set(1ull << pin);
__force_inline static void gpioc_bit_out_set(uint pin) {
pico_default_asm_volatile ("mcr p0, #6, %0, c0, c0" : : "r" (pin));
}
// Unconditionally clear any single output. Equivalent to:
//
// gpioc_hilo_out_clr(1ull << pin);
__force_inline static void gpioc_bit_out_clr(uint pin) {
pico_default_asm_volatile ("mcr p0, #7, %0, c0, c0" : : "r" (pin));
}
// Conditionally toggle any single output. Equivalent to:
//
// gpioc_hilo_out_xor((uint64_t)val << pin);
__force_inline static void gpioc_bit_out_xor2(uint pin, bool val) {
pico_default_asm_volatile ("mcrr p0, #5, %0, %1, c0" : : "r" (pin), "r" (val));
}
// Conditionally set any single output. Equivalent to:
//
// gpioc_hilo_out_set((uint64_t)val << pin);
__force_inline static void gpioc_bit_out_set2(uint pin, bool val) {
pico_default_asm_volatile ("mcrr p0, #6, %0, %1, c0" : : "r" (pin), "r" (val));
}
// Conditionally clear any single output. Equivalent to:
//
// gpioc_hilo_out_clr((uint64_t)val << pin);
__force_inline static void gpioc_bit_out_clr2(uint pin, bool val) {
pico_default_asm_volatile ("mcrr p0, #7, %0, %1, c0" : : "r" (pin), "r" (val));
}
// Write a 1-bit value to any output enable. Equivalent to:
//
// if (val)
// gpioc_hilo_oe_set(1ull << pin);
// else
// gpioc_hilo_oe_clr(1ull << pin);
__force_inline static void gpioc_bit_oe_put(uint pin, bool val) {
pico_default_asm_volatile ("mcrr p0, #4, %0, %1, c4" : : "r" (pin), "r" (val));
}
// Unconditionally toggle any output enable. Equivalent to:
//
// gpioc_hilo_oe_xor(1ull << pin);
__force_inline static void gpioc_bit_oe_xor(uint pin) {
pico_default_asm_volatile ("mcr p0, #5, %0, c0, c4" : : "r" (pin));
}
// Unconditionally set any output enable (set to output). Equivalent to:
//
// gpioc_hilo_oe_set(1ull << pin);
__force_inline static void gpioc_bit_oe_set(uint pin) {
pico_default_asm_volatile ("mcr p0, #6, %0, c0, c4" : : "r" (pin));
}
// Unconditionally clear any output enable (set to input). Equivalent to:
//
// gpioc_hilo_oe_clr(1ull << pin);
__force_inline static void gpioc_bit_oe_clr(uint pin) {
pico_default_asm_volatile ("mcr p0, #7, %0, c0, c4" : : "r" (pin));
}
// Conditionally toggle any output enable. Equivalent to:
//
// gpioc_hilo_oe_xor((uint64_t)val << pin);
__force_inline static void gpioc_bit_oe_xor2(uint pin, bool val) {
pico_default_asm_volatile ("mcrr p0, #5, %0, %1, c4" : : "r" (pin), "r" (val));
}
// Conditionally set any output enable (set to output). Equivalent to:
//
// gpioc_hilo_oe_set((uint64_t)val << pin);
__force_inline static void gpioc_bit_oe_set2(uint pin, bool val) {
pico_default_asm_volatile ("mcrr p0, #6, %0, %1, c4" : : "r" (pin), "r" (val));
}
// Conditionally clear any output enable (set to input). Equivalent to:
//
// gpioc_hilo_oe_clr((uint64_t)val << pin);
__force_inline static void gpioc_bit_oe_clr2(uint pin, bool val) {
pico_default_asm_volatile ("mcrr p0, #7, %0, %1, c4" : : "r" (pin), "r" (val));
}
// ----------------------------------------------------------------------------
// Indexed mask write instructions -- write to a dynamically selected 32-bit
// GPIO register
// Write to a selected GPIO output register. Equivalent to:
//
// if (reg_index == 0) {
// gpioc_lo_out_put(val);
// } else if (reg_index == 1) {
// gpioc_hi_out_put(val);
// } else {
// // undefined
// }
__force_inline static void gpioc_index_out_put(uint reg_index, uint32_t val) {
pico_default_asm_volatile ("mcrr p0, #8, %1, %0, c0" : : "r" (reg_index), "r" (val));
}
// Toggle bits in a selected GPIO output register. Equivalent to:
//
// if (reg_index == 0) {
// gpioc_lo_out_xor(val);
// } else if (reg_index == 1) {
// gpioc_hi_out_xor(val);
// } else {
// // undefined
// }
__force_inline static void gpioc_index_out_xor(uint reg_index, uint32_t mask) {
pico_default_asm_volatile ("mcrr p0, #9, %1, %0, c0" : : "r" (reg_index), "r" (mask));
}
// Set bits in a selected GPIO output register. Equivalent to:
//
// if (reg_index == 0) {
// gpioc_lo_out_set(val);
// } else if (reg_index == 1) {
// gpioc_hi_out_set(val);
// } else {
// // undefined
// }
__force_inline static void gpioc_index_out_set(uint reg_index, uint32_t mask) {
pico_default_asm_volatile ("mcrr p0, #10, %1, %0, c0" : : "r" (reg_index), "r" (mask));
}
// Clear bits in a selected GPIO output register. Equivalent to:
//
// if (reg_index == 0) {
// gpioc_lo_out_clr(val);
// } else if (reg_index == 1) {
// gpioc_hi_out_clr(val);
// } else {
// // undefined
// }
__force_inline static void gpioc_index_out_clr(uint reg_index, uint32_t mask) {
pico_default_asm_volatile ("mcrr p0, #11, %1, %0, c0" : : "r" (reg_index), "r" (mask));
}
// Write to a selected GPIO output enable register. Equivalent to:
//
// if (reg_index == 0) {
// gpioc_lo_oe_put(val);
// } else if (reg_index == 1) {
// gpioc_hi_oe_put(val);
// } else {
// // undefined
// }
__force_inline static void gpioc_index_oe_put(uint reg_index, uint32_t val) {
pico_default_asm_volatile ("mcrr p0, #8, %1, %0, c4" : : "r" (reg_index), "r" (val));
}
// Toggle bits in a selected GPIO output enable register. Equivalent to:
//
// if (reg_index == 0) {
// gpioc_lo_oe_xor(val);
// } else if (reg_index == 1) {
// gpioc_hi_oe_xor(val);
// } else {
// // undefined
// }
__force_inline static void gpioc_index_oe_xor(uint reg_index, uint32_t mask) {
pico_default_asm_volatile ("mcrr p0, #9, %1, %0, c4" : : "r" (reg_index), "r" (mask));
}
// Set bits in a selected GPIO output enable register (set to output). Equivalent to:
//
// if (reg_index == 0) {
// gpioc_lo_oe_set(val);
// } else if (reg_index == 1) {
// gpioc_hi_oe_set(val);
// } else {
// // undefined
// }
__force_inline static void gpioc_index_oe_set(uint reg_index, uint32_t mask) {
pico_default_asm_volatile ("mcrr p0, #10, %1, %0, c4" : : "r" (reg_index), "r" (mask));
}
// Clear bits in a selected GPIO output enable register (set to input). Equivalent to:
//
// if (reg_index == 0) {
// gpioc_lo_oe_clr(val);
// } else if (reg_index == 1) {
// gpioc_hi_oe_clr(val);
// } else {
// // undefined
// }
__force_inline static void gpioc_index_oe_clr(uint reg_index, uint32_t mask) {
pico_default_asm_volatile ("mcrr p0, #11, %1, %0, c4" : : "r" (reg_index), "r" (mask));
}
// ----------------------------------------------------------------------------
// Read instructions
// Read back the lower 32-bit output register. Equivalent to:
//
// return sio_hw->gpio_out;
__force_inline static uint32_t gpioc_lo_out_get(void) {
uint32_t lo;
pico_default_asm_volatile ("mrc p0, #0, %0, c0, c0" : "=r" (lo));
return lo;
}
// Read back the upper 32-bit output register. Equivalent to:
//
// return sio_hw->gpio_hi_out;
__force_inline static uint32_t gpioc_hi_out_get(void) {
uint32_t hi;
pico_default_asm_volatile ("mrc p0, #0, %0, c0, c1" : "=r" (hi));
return hi;
}
// Read back two 32-bit output registers in a single operation. Equivalent to:
//
// return sio_hw->gpio_out | ((uint64_t)sio_hw->gpio_hi_out << 32);
__force_inline static uint64_t gpioc_hilo_out_get(void) {
uint32_t hi, lo;
pico_default_asm_volatile ("mrrc p0, #0, %0, %1, c0" : "=r" (lo), "=r" (hi));
return ((uint64_t)hi << 32) | lo;
}
// Read back the lower 32-bit output enable register. Equivalent to:
//
// return sio_hw->gpio_oe;
__force_inline static uint32_t gpioc_lo_oe_get(void) {
uint32_t lo;
pico_default_asm_volatile ("mrc p0, #0, %0, c0, c4" : "=r" (lo));
return lo;
}
// Read back the upper 32-bit output enable register. Equivalent to:
//
// return sio_hw->gpio_hi_oe;
__force_inline static uint32_t gpioc_hi_oe_get(void) {
uint32_t hi;
pico_default_asm_volatile ("mrc p0, #0, %0, c0, c5" : "=r" (hi));
return hi;
}
// Read back two 32-bit output enable registers in a single operation. Equivalent to:
//
// return sio_hw->gpio_oe | ((uint64_t)sio_hw->gpio_hi_oe << 32);
__force_inline static uint64_t gpioc_hilo_oe_get(void) {
uint32_t hi, lo;
pico_default_asm_volatile ("mrrc p0, #0, %0, %1, c4" : "=r" (lo), "=r" (hi));
return ((uint64_t)hi << 32) | lo;
}
// Sample the lower 32 GPIOs. Equivalent to:
//
// return sio_hw->gpio_in;
__force_inline static uint32_t gpioc_lo_in_get(void) {
uint32_t lo;
pico_default_asm_volatile ("mrc p0, #0, %0, c0, c8" : "=r" (lo));
return lo;
}
// Sample the upper 32 GPIOs. Equivalent to:
//
// return sio_hw->gpio_hi_in;
__force_inline static uint32_t gpioc_hi_in_get(void) {
uint32_t hi;
pico_default_asm_volatile ("mrc p0, #0, %0, c0, c9" : "=r" (hi));
return hi;
}
// Sample 64 GPIOs on the same cycle. Equivalent to:
//
// return sio_hw->gpio_in | ((uint64_t)sio_hw->gpio_hi_in << 32);
__force_inline static uint64_t gpioc_hilo_in_get(void) {
uint32_t hi, lo;
pico_default_asm_volatile ("mrrc p0, #0, %0, %1, c8" : "=r" (lo), "=r" (hi));
return ((uint64_t)hi << 32) | lo;
}
#endif

178
arch/arm/src/rp23xx/hardware/hazard3.h
View file

@ -1,178 +0,0 @@
/*
* Copyright (c) 2022 Raspberry Pi (Trading) Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _HARDWARE_HAZARD3_
#define _HARDWARE_HAZARD3_
#include "pico.h"
#include "hardware/riscv.h"
#include "hardware/regs/rvcsr.h"
/** \file hardware/hazard3.h
* \defgroup hardware_hazard3 hardware_hazard3
*
* \brief Accessors for Hazard3-specific RISC-V CSRs, and intrinsics for Hazard3 custom instructions
*
*/
// Feature detection macros for Hazard3 custom extensions
#if PICO_RP2350
#define __hazard3_extension_xh3power
#define __hazard3_extension_xh3bextm
#define __hazard3_extension_xh3irq
#define __hazard3_extension_xh3pmpm
#endif
#ifdef __ASSEMBLER__
// Assembly language instruction macros for Hazard3 custom instructions
// h3.bextm: Extract up to 8 consecutive bits from register rs1, with the
// first bit indexed by rs2, and bit count configured by an immediate value.
// R-format instruction. Pseudocode:
//
// rd = (rs1 >> rs2[4:0]) & ~(-1 << nbits)
.macro h3.bextm rd rs1 rs2 nbits
.if (\nbits < 1) || (\nbits > 8)
.err
.endif
#ifdef __hazard3_extension_xh3bextm
.insn r 0x0b, 0x4, (((\nbits - 1) & 0x7 ) << 1), \rd, \rs1, \rs2
#else
srl \rd, \rs1, \rs2
andi \rd, \rd, ((1 << \nbits) - 1)
#endif
.endm
// h3.bextmi: Extract up to 8 consecutive bits from register rs1, with the
// first bit index and the number of bits both configured by immediate
// values. I-format instruction. Pseudocode:
//
// rd = (rs1 >> shamt) & ~(-1 << nbits)
.macro h3.bextmi rd rs1 shamt nbits
.if (\nbits < 1) || (\nbits > 8)
.err
.endif
.if (\shamt < 0) || (\shamt > 31)
.err
.endif
#ifdef __hazard3_extension_xh3bextm
.insn i 0x0b, 0x4, \rd, \rs1, (\shamt & 0x1f) | (((\nbits - 1) & 0x7 ) << 6)
#else
srli \rd, \rs1, \shamt
andi \rd, \rd, ((1 << \nbits) - 1)
#endif
.endm
// h3.block: enter an idle state until another processor in the same
// multiprocessor complex executes an h3.unblock instruction, or the
// processor is interrupted. Fall through immediately if an h3.unblock has
// been received since the last execution of an h3.block on this processor.
// On RP2350, processors also have their own h3.unblock signals reflected
// back to them.
.macro h3.block
#ifdef __hazard3_extension_xh3power
slt x0, x0, x0
#else
nop
#endif
.endm
// h3.unblock: signal other processors in the same multiprocessor complex to
// exit the idle state entered by an h3.block instruction. On RP2350, this
// signal is also reflected back to the processor that executed the
// h3.unblock, which will cause that processor's next h3.block to fall
// through immediately.
.macro h3.unblock
#ifdef __hazard3_extension_xh3power
slt x0, x0, x1
#else
nop
#endif
.endm
#else // !__ASSEMBLER__
#ifdef __cplusplus
extern "C" {
#endif
#ifdef __hazard3_extension_xh3irq
#define hazard3_irqarray_read(csr, index) (riscv_read_set_csr(csr, (index)) >> 16)
#else
#define hazard3_irqarray_read(csr, index) static_assert(false, "Not supported: Xh3irq extension")
#endif
#ifdef __hazard3_extension_xh3irq
#define hazard3_irqarray_write(csr, index, data) (riscv_write_csr(csr, (index) | ((uint32_t)(data) << 16)))
#else
#define hazard3_irqarray_write(csr, index, data) static_assert(false, "Not supported: Xh3irq extension")
#endif
#ifdef __hazard3_extension_xh3irq
#define hazard3_irqarray_set(csr, index, data) (riscv_set_csr(csr, (index) | ((uint32_t)(data) << 16)))
#else
#define hazard3_irqarray_set(csr, index, data) static_assert(false, "Not supported: Xh3irq extension")
#endif
#ifdef __hazard3_extension_xh3irq
#define hazard3_irqarray_clear(csr, index, data) (riscv_clear_csr(csr, (index) | ((uint32_t)(data) << 16)))
#else
#define hazard3_irqarray_clear(csr, index, data) static_assert(false, "Not supported: Xh3irq extension")
#endif
// nbits must be a constant expression
#ifdef __hazard3_extension_xh3bextm
#define __hazard3_bextm(nbits, rs1, rs2) ({\
uint32_t __h3_bextm_rd; \
asm (".insn r 0x0b, 0, %3, %0, %1, %2"\
: "=r" (__h3_bextm_rd) \
: "r" (rs1), "r" (rs2), "i" ((((nbits) - 1) & 0x7) << 1)\
); \
__h3_bextm_rd; \
})
#else
#define __hazard3_bextm(nbits, rs1, rs2) (((rs1) >> ((rs2) & 0x1f)) & (0xffu >> (7 - (((nbits) - 1) & 0x7))))
#endif
// nbits and shamt must be constant expressions
#ifdef __hazard3_extension_xh3bextm
#define __hazard3_bextmi(nbits, rs1, shamt) ({\
uint32_t __h3_bextmi_rd; \
asm (".insn i 0x0b, 0x4, %0, %1, %2"\
: "=r" (__h3_bextmi_rd) \
: "r" (rs1), "i" ((((nbits) - 1) & 0x7) << 6 | ((shamt) & 0x1f)) \
); \
__h3_bextmi_rd; \
})
#else
#define __hazard3_bextm(nbits, rs1, rs2) (((rs1) >> ((shamt) & 0x1f)) & (0xffu >> (7 - (((nbits) - 1) & 0x7))))
#endif
#ifdef __hazard3_extension_xh3power
#define __hazard3_block() asm volatile ("slt x0, x0, x0" : : : "memory")
#else
#define __hazard3_block() do {} while (0)
#endif
#ifdef __hazard3_extension_xh3power
#define __hazard3_unblock() asm volatile ("slt x0, x0, x1" : : : "memory")
#else
#define __hazard3_unblock() do {} while (0)
#endif
#ifdef __cplusplus
}
#endif
#endif // !__ASSEMBLER__
#endif

437
arch/arm/src/rp23xx/hardware/i2c.h
View file

@ -1,437 +0,0 @@
/*
* Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _HARDWARE_I2C_H
#define _HARDWARE_I2C_H
#include "pico.h"
#include "pico/time.h"
#include "hardware/structs/i2c.h"
#include "hardware/regs/dreq.h"
// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_HARDWARE_I2C, Enable/disable assertions in the hardware_i2c module, type=bool, default=0, group=hardware_i2c
#ifndef PARAM_ASSERTIONS_ENABLED_HARDWARE_I2C
#ifdef PARAM_ASSERTIONS_ENABLED_I2C // backwards compatibility with SDK < 2.0.0
#define PARAM_ASSERTIONS_ENABLED_HARDWARE_I2C PARAM_ASSERTIONS_ENABLED_I2C
#else
#define PARAM_ASSERTIONS_ENABLED_HARDWARE_I2C 0
#endif
#endif
#ifdef __cplusplus
extern "C" {
#endif
/** \file hardware/i2c.h
* \defgroup hardware_i2c hardware_i2c
*
* \brief I2C Controller API
*
* The I2C bus is a two-wire serial interface, consisting of a serial data line SDA and a serial clock SCL. These wires carry
* information between the devices connected to the bus. Each device is recognized by a unique 7-bit address and can operate as
* either a “transmitter” or “receiver”, depending on the function of the device. Devices can also be considered as masters or
* slaves when performing data transfers. A master is a device that initiates a data transfer on the bus and generates the
* clock signals to permit that transfer. The first byte in the data transfer always contains the 7-bit address and
* a read/write bit in the LSB position. This API takes care of toggling the read/write bit. After this, any device addressed
* is considered a slave.
*
* This API allows the controller to be set up as a master or a slave using the \ref i2c_set_slave_mode function.
*
* The external pins of each controller are connected to GPIO pins as defined in the GPIO muxing table in the datasheet. The muxing options
* give some IO flexibility, but each controller external pin should be connected to only one GPIO.
*
* Note that the controller does NOT support High speed mode or Ultra-fast speed mode, the fastest operation being fast mode plus
* at up to 1000Kb/s.
*
* See the datasheet for more information on the I2C controller and its usage.
*
* \subsection i2c_example Example
* \addtogroup hardware_i2c
* \include bus_scan.c
*/
typedef struct i2c_inst i2c_inst_t;
// PICO_CONFIG: PICO_DEFAULT_I2C, Define the default I2C for a board, min=0, max=1, default=Usually provided via board header, group=hardware_i2c
// PICO_CONFIG: PICO_DEFAULT_I2C_SDA_PIN, Define the default I2C SDA pin, min=0, max=29, default=Usually provided via board header, group=hardware_i2c
// PICO_CONFIG: PICO_DEFAULT_I2C_SCL_PIN, Define the default I2C SCL pin, min=0, max=29, default=Usually provided via board header, group=hardware_i2c
/** The I2C identifiers for use in I2C functions.
*
* e.g. i2c_init(i2c0, 48000)
*
* \ingroup hardware_i2c
* @{
*/
extern i2c_inst_t i2c0_inst;
extern i2c_inst_t i2c1_inst;
#define i2c0 (&i2c0_inst) ///< Identifier for I2C HW Block 0
#define i2c1 (&i2c1_inst) ///< Identifier for I2C HW Block 1
#if !defined(PICO_DEFAULT_I2C_INSTANCE) && defined(PICO_DEFAULT_I2C)
#define PICO_DEFAULT_I2C_INSTANCE() (__CONCAT(i2c,PICO_DEFAULT_I2C))
#endif
/**
* \def PICO_DEFAULT_I2C
* \ingroup hardware_i2c
* \hideinitializer
* \brief The default I2C instance number
*/
/**
* \def PICO_DEFAULT_I2C_INSTANCE()
* \ingroup hardware_i2c
* \hideinitializer
* \brief Returns the default I2C instance based on the value of PICO_DEFAULT_I2C
*/
#ifdef PICO_DEFAULT_I2C_INSTANCE
#define i2c_default PICO_DEFAULT_I2C_INSTANCE()
#endif
/** @} */
// ----------------------------------------------------------------------------
// Setup
/*! \brief Initialise the I2C HW block
* \ingroup hardware_i2c
*
* Put the I2C hardware into a known state, and enable it. Must be called
* before other functions. By default, the I2C is configured to operate as a
* master.
*
* The I2C bus frequency is set as close as possible to requested, and
* the actual rate set is returned
*
* \param i2c Either \ref i2c0 or \ref i2c1
* \param baudrate Baudrate in Hz (e.g. 100kHz is 100000)
* \return Actual set baudrate
*/
uint i2c_init(i2c_inst_t *i2c, uint baudrate);
/*! \brief Disable the I2C HW block
* \ingroup hardware_i2c
*
* \param i2c Either \ref i2c0 or \ref i2c1
*
* Disable the I2C again if it is no longer used. Must be reinitialised before
* being used again.
*/
void i2c_deinit(i2c_inst_t *i2c);
/*! \brief Set I2C baudrate
* \ingroup hardware_i2c
*
* Set I2C bus frequency as close as possible to requested, and return actual
* rate set.
* Baudrate may not be as exactly requested due to clocking limitations.
*
* \param i2c Either \ref i2c0 or \ref i2c1
* \param baudrate Baudrate in Hz (e.g. 100kHz is 100000)
* \return Actual set baudrate
*/
uint i2c_set_baudrate(i2c_inst_t *i2c, uint baudrate);
/*! \brief Set I2C port to slave mode
* \ingroup hardware_i2c
*
* \param i2c Either \ref i2c0 or \ref i2c1
* \param slave true to use slave mode, false to use master mode
* \param addr If \p slave is true, set the slave address to this value
*/
void i2c_set_slave_mode(i2c_inst_t *i2c, bool slave, uint8_t addr);
// ----------------------------------------------------------------------------
// Generic input/output
struct i2c_inst {
i2c_hw_t *hw;
bool restart_on_next;
};
/**
* \def I2C_NUM(i2c)
* \ingroup hardware_i2c
* \hideinitializer
* \brief Returns the I2C number for a I2C instance
*
* Note this macro is intended to resolve at compile time, and does no parameter checking
*/
#ifndef I2C_NUM
static_assert(NUM_I2CS == 2, "");
#define I2C_NUM(i2c) ((i2c) == i2c1)
#endif
/**
* \def I2C_INSTANCE(i2c_num)
* \ingroup hardware_i2c
* \hideinitializer
* \brief Returns the I2C instance with the given I2C number
*
* Note this macro is intended to resolve at compile time, and does no parameter checking
*/
#ifndef I2C_INSTANCE
static_assert(NUM_I2CS == 2, "");
#define I2C_INSTANCE(num) ((num) ? i2c1 : i2c0)
#endif
/**
* \def I2C_DREQ_NUM(i2c, is_tx)
* \ingroup hardware_i2c
* \hideinitializer
* \brief Returns the \ref dreq_num_t used for pacing DMA transfers to or from this I2C instance.
* If is_tx is true, then it is for transfers to the I2C instance else for transfers from the I2C instance.
*
* Note this macro is intended to resolve at compile time, and does no parameter checking
*/
#ifndef I2C_DREQ_NUM
static_assert(DREQ_I2C0_RX == DREQ_I2C0_TX + 1, "");
static_assert(DREQ_I2C1_RX == DREQ_I2C1_TX + 1, "");
static_assert(DREQ_I2C1_TX == DREQ_I2C0_TX + 2, "");
#define I2C_DREQ_NUM(i2c,is_tx) (DREQ_I2C0_TX + I2C_NUM(i2c) * 2 + !(is_tx))
#endif
/*! \brief Convert I2C instance to hardware instance number
* \ingroup hardware_i2c
*
* \param i2c I2C instance
* \return Number of I2C, 0 or 1.
*/
static inline uint i2c_get_index(i2c_inst_t *i2c) {
invalid_params_if(HARDWARE_I2C, i2c != i2c0 && i2c != i2c1);
return I2C_NUM(i2c);
}
// backward compatibility
#define i2c_hw_index(i2c) i2c_get_index(i2c)
/*! \brief Return pointer to structure containing i2c hardware registers
* \ingroup hardware_i2c
*
* \param i2c I2C instance
* \return pointer to \ref i2c_hw_t
*/
static inline i2c_hw_t *i2c_get_hw(i2c_inst_t *i2c) {
i2c_hw_index(i2c); // check it is a hw i2c
return i2c->hw;
}
/*! \brief Convert I2C hardware instance number to I2C instance
* \ingroup hardware_i2c
*
* \param num Number of I2C, 0 or 1
* \return I2C hardware instance
*/
static inline i2c_inst_t *i2c_get_instance(uint num) {
invalid_params_if(HARDWARE_I2C, num >= NUM_I2CS);
return I2C_INSTANCE(num);
}
/*! \brief Attempt to write specified number of bytes to address, blocking until the specified absolute time is reached.
* \ingroup hardware_i2c
*
* \param i2c Either \ref i2c0 or \ref i2c1
* \param addr 7-bit address of device to write to
* \param src Pointer to data to send
* \param len Length of data in bytes to send
* \param nostop If true, master retains control of the bus at the end of the transfer (no Stop is issued),
* and the next transfer will begin with a Restart rather than a Start.
* \param until The absolute time that the block will wait until the entire transaction is complete. Note, an individual timeout of
* this value divided by the length of data is applied for each byte transfer, so if the first or subsequent
* bytes fails to transfer within that sub timeout, the function will return with an error.
*
* \return Number of bytes written, or PICO_ERROR_GENERIC if address not acknowledged, no device present, or PICO_ERROR_TIMEOUT if a timeout occurred.
*/
int i2c_write_blocking_until(i2c_inst_t *i2c, uint8_t addr, const uint8_t *src, size_t len, bool nostop, absolute_time_t until);
/*! \brief Attempt to read specified number of bytes from address, blocking until the specified absolute time is reached.
* \ingroup hardware_i2c
*
* \param i2c Either \ref i2c0 or \ref i2c1
* \param addr 7-bit address of device to read from
* \param dst Pointer to buffer to receive data
* \param len Length of data in bytes to receive
* \param nostop If true, master retains control of the bus at the end of the transfer (no Stop is issued),
* and the next transfer will begin with a Restart rather than a Start.
* \param until The absolute time that the block will wait until the entire transaction is complete.
* \return Number of bytes read, or PICO_ERROR_GENERIC if address not acknowledged, no device present, or PICO_ERROR_TIMEOUT if a timeout occurred.
*/
int i2c_read_blocking_until(i2c_inst_t *i2c, uint8_t addr, uint8_t *dst, size_t len, bool nostop, absolute_time_t until);
/*! \brief Attempt to write specified number of bytes to address, with timeout
* \ingroup hardware_i2c
*
* \param i2c Either \ref i2c0 or \ref i2c1
* \param addr 7-bit address of device to write to
* \param src Pointer to data to send
* \param len Length of data in bytes to send
* \param nostop If true, master retains control of the bus at the end of the transfer (no Stop is issued),
* and the next transfer will begin with a Restart rather than a Start.
* \param timeout_us The time that the function will wait for the entire transaction to complete. Note, an individual timeout of
* this value divided by the length of data is applied for each byte transfer, so if the first or subsequent
* bytes fails to transfer within that sub timeout, the function will return with an error.
*
* \return Number of bytes written, or PICO_ERROR_GENERIC if address not acknowledged, no device present, or PICO_ERROR_TIMEOUT if a timeout occurred.
*/
static inline int i2c_write_timeout_us(i2c_inst_t *i2c, uint8_t addr, const uint8_t *src, size_t len, bool nostop, uint timeout_us) {
absolute_time_t t = make_timeout_time_us(timeout_us);
return i2c_write_blocking_until(i2c, addr, src, len, nostop, t);
}
int i2c_write_timeout_per_char_us(i2c_inst_t *i2c, uint8_t addr, const uint8_t *src, size_t len, bool nostop, uint timeout_per_char_us);
/*! \brief Attempt to read specified number of bytes from address, with timeout
* \ingroup hardware_i2c
*
* \param i2c Either \ref i2c0 or \ref i2c1
* \param addr 7-bit address of device to read from
* \param dst Pointer to buffer to receive data
* \param len Length of data in bytes to receive
* \param nostop If true, master retains control of the bus at the end of the transfer (no Stop is issued),
* and the next transfer will begin with a Restart rather than a Start.
* \param timeout_us The time that the function will wait for the entire transaction to complete
* \return Number of bytes read, or PICO_ERROR_GENERIC if address not acknowledged, no device present, or PICO_ERROR_TIMEOUT if a timeout occurred.
*/
static inline int i2c_read_timeout_us(i2c_inst_t *i2c, uint8_t addr, uint8_t *dst, size_t len, bool nostop, uint timeout_us) {
absolute_time_t t = make_timeout_time_us(timeout_us);
return i2c_read_blocking_until(i2c, addr, dst, len, nostop, t);
}
int i2c_read_timeout_per_char_us(i2c_inst_t *i2c, uint8_t addr, uint8_t *dst, size_t len, bool nostop, uint timeout_per_char_us);
/*! \brief Attempt to write specified number of bytes to address, blocking
* \ingroup hardware_i2c
*
* \param i2c Either \ref i2c0 or \ref i2c1
* \param addr 7-bit address of device to write to
* \param src Pointer to data to send
* \param len Length of data in bytes to send
* \param nostop If true, master retains control of the bus at the end of the transfer (no Stop is issued),
* and the next transfer will begin with a Restart rather than a Start.
* \return Number of bytes written, or PICO_ERROR_GENERIC if address not acknowledged, no device present.
*/
int i2c_write_blocking(i2c_inst_t *i2c, uint8_t addr, const uint8_t *src, size_t len, bool nostop);
/*! \brief Attempt to read specified number of bytes from address, blocking
* \ingroup hardware_i2c
*
* \param i2c Either \ref i2c0 or \ref i2c1
* \param addr 7-bit address of device to read from
* \param dst Pointer to buffer to receive data
* \param len Length of data in bytes to receive
* \param nostop If true, master retains control of the bus at the end of the transfer (no Stop is issued),
* and the next transfer will begin with a Restart rather than a Start.
* \return Number of bytes read, or PICO_ERROR_GENERIC if address not acknowledged or no device present.
*/
int i2c_read_blocking(i2c_inst_t *i2c, uint8_t addr, uint8_t *dst, size_t len, bool nostop);
/*! \brief Determine non-blocking write space available
* \ingroup hardware_i2c
*
* \param i2c Either \ref i2c0 or \ref i2c1
* \return 0 if no space is available in the I2C to write more data. If return is nonzero, at
* least that many bytes can be written without blocking.
*/
static inline size_t i2c_get_write_available(i2c_inst_t *i2c) {
const size_t IC_TX_BUFFER_DEPTH = 16;
return IC_TX_BUFFER_DEPTH - i2c_get_hw(i2c)->txflr;
}
/*! \brief Determine number of bytes received
* \ingroup hardware_i2c
*
* \param i2c Either \ref i2c0 or \ref i2c1
* \return 0 if no data available, if return is nonzero at
* least that many bytes can be read without blocking.
*/
static inline size_t i2c_get_read_available(i2c_inst_t *i2c) {
return i2c_get_hw(i2c)->rxflr;
}
/*! \brief Write direct to TX FIFO
* \ingroup hardware_i2c
*
* \param i2c Either \ref i2c0 or \ref i2c1
* \param src Data to send
* \param len Number of bytes to send
*
* Writes directly to the I2C TX FIFO which is mainly useful for
* slave-mode operation.
*/
static inline void i2c_write_raw_blocking(i2c_inst_t *i2c, const uint8_t *src, size_t len) {
for (size_t i = 0; i < len; ++i) {
// TODO NACK or STOP on end?
while (!i2c_get_write_available(i2c))
tight_loop_contents();
i2c_get_hw(i2c)->data_cmd = *src++;
}
}
/*! \brief Read direct from RX FIFO
* \ingroup hardware_i2c
*
* \param i2c Either \ref i2c0 or \ref i2c1
* \param dst Buffer to accept data
* \param len Number of bytes to read
*
* Reads directly from the I2C RX FIFO which is mainly useful for
* slave-mode operation.
*/
static inline void i2c_read_raw_blocking(i2c_inst_t *i2c, uint8_t *dst, size_t len) {
for (size_t i = 0; i < len; ++i) {
while (!i2c_get_read_available(i2c))
tight_loop_contents();
*dst++ = (uint8_t)i2c_get_hw(i2c)->data_cmd;
}
}
/**
* \brief Pop a byte from I2C Rx FIFO.
* \ingroup hardware_i2c
*
* This function is non-blocking and assumes the Rx FIFO isn't empty.
*
* \param i2c I2C instance.
* \return uint8_t Byte value.
*/
static inline uint8_t i2c_read_byte_raw(i2c_inst_t *i2c) {
i2c_hw_t *hw = i2c_get_hw(i2c);
assert(hw->status & I2C_IC_STATUS_RFNE_BITS); // Rx FIFO must not be empty
return (uint8_t)hw->data_cmd;
}
/**
* \brief Push a byte into I2C Tx FIFO.
* \ingroup hardware_i2c
*
* This function is non-blocking and assumes the Tx FIFO isn't full.
*
* \param i2c I2C instance.
* \param value Byte value.
*/
static inline void i2c_write_byte_raw(i2c_inst_t *i2c, uint8_t value) {
i2c_hw_t *hw = i2c_get_hw(i2c);
assert(hw->status & I2C_IC_STATUS_TFNF_BITS); // Tx FIFO must not be full
hw->data_cmd = value;
}
/*! \brief Return the DREQ to use for pacing transfers to/from a particular I2C instance
* \ingroup hardware_i2c
*
* \param i2c Either \ref i2c0 or \ref i2c1
* \param is_tx true for sending data to the I2C instance, false for receiving data from the I2C instance
*/
static inline uint i2c_get_dreq(i2c_inst_t *i2c, bool is_tx) {
return I2C_DREQ_NUM(i2c, is_tx);
}
#ifdef __cplusplus
}
#endif
#endif

462
arch/arm/src/rp23xx/hardware/interp.h
View file

@ -1,462 +0,0 @@
/*
* Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _HARDWARE_INTERP_H
#define _HARDWARE_INTERP_H
#include "pico.h"
#include "hardware/structs/interp.h"
#include "hardware/regs/sio.h"
// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_HARDWARE_INTERP, Enable/disable assertions in the hardware_interp module, type=bool, default=0, group=hardware_interp
#ifndef PARAM_ASSERTIONS_ENABLED_HARDWARE_INTERP
#ifdef PARAM_ASSERTIONS_ENABLED_INTERP // backwards compatibility with SDK < 2.0.0
#define PARAM_ASSERTIONS_ENABLED_HARDWARE_INTERP PARAM_ASSERTIONS_ENABLED_INTERP
#else
#define PARAM_ASSERTIONS_ENABLED_HARDWARE_INTERP 0
#endif
#endif
#ifdef __cplusplus
extern "C" {
#endif
/** \file hardware/interp.h
* \defgroup hardware_interp hardware_interp
*
* \brief Hardware Interpolator API
*
* Each core is equipped with two interpolators (INTERP0 and INTERP1) which can be used to accelerate
* tasks by combining certain pre-configured simple operations into a single processor cycle. Intended
* for cases where the pre-configured operation is repeated a large number of times, this results in
* code which uses both fewer CPU cycles and fewer CPU registers in the time critical sections of the
* code.
*
* The interpolators are used heavily to accelerate audio operations within the SDK, but their
* flexible configuration make it possible to optimise many other tasks such as quantization and
* dithering, table lookup address generation, affine texture mapping, decompression and linear feedback.
*
* Please refer to the appropriate RP-series microcontroller datasheet for more information on the HW
* interpolators and how they work.
*/
#define interp0 interp0_hw
#define interp1 interp1_hw
/** \brief Interpolator configuration
* \defgroup interp_config interp_config
* \ingroup hardware_interp
*
* Each interpolator needs to be configured, these functions provide handy helpers to set up configuration
* structures.
*
*/
typedef struct {
uint32_t ctrl;
} interp_config;
static inline uint interp_index(interp_hw_t *interp) {
valid_params_if(HARDWARE_INTERP, interp == interp0 || interp == interp1);
return interp == interp1 ? 1 : 0;
}
/*! \brief Claim the interpolator lane specified
* \ingroup hardware_interp
*
* Use this function to claim exclusive access to the specified interpolator lane.
*
* This function will panic if the lane is already claimed.
*
* \param interp Interpolator on which to claim a lane. interp0 or interp1
* \param lane The lane number, 0 or 1.
*/
void interp_claim_lane(interp_hw_t *interp, uint lane);
// The above really should be called this for consistency
#define interp_lane_claim interp_claim_lane
/*! \brief Claim the interpolator lanes specified in the mask
* \ingroup hardware_interp
*
* \param interp Interpolator on which to claim lanes. interp0 or interp1
* \param lane_mask Bit pattern of lanes to claim (only bits 0 and 1 are valid)
*/
void interp_claim_lane_mask(interp_hw_t *interp, uint lane_mask);
/*! \brief Release a previously claimed interpolator lane
* \ingroup hardware_interp
*
* \param interp Interpolator on which to release a lane. interp0 or interp1
* \param lane The lane number, 0 or 1
*/
void interp_unclaim_lane(interp_hw_t *interp, uint lane);
// The above really should be called this for consistency
#define interp_lane_unclaim interp_unclaim_lane
/*! \brief Determine if an interpolator lane is claimed
* \ingroup hardware_interp
*
* \param interp Interpolator whose lane to check
* \param lane The lane number, 0 or 1
* \return true if claimed, false otherwise
* \see interp_claim_lane
* \see interp_claim_lane_mask
*/
bool interp_lane_is_claimed(interp_hw_t *interp, uint lane);
/*! \brief Release previously claimed interpolator lanes \see interp_claim_lane_mask
* \ingroup hardware_interp
*
* \param interp Interpolator on which to release lanes. interp0 or interp1
* \param lane_mask Bit pattern of lanes to unclaim (only bits 0 and 1 are valid)
*/
void interp_unclaim_lane_mask(interp_hw_t *interp, uint lane_mask);
/*! \brief Set the interpolator shift value
* \ingroup interp_config
*
* Sets the number of bits the accumulator is shifted before masking, on each iteration.
*
* \param c Pointer to an interpolator config
* \param shift Number of bits
*/
static inline void interp_config_set_shift(interp_config *c, uint shift) {
valid_params_if(HARDWARE_INTERP, shift < 32);
c->ctrl = (c->ctrl & ~SIO_INTERP0_CTRL_LANE0_SHIFT_BITS) |
((shift << SIO_INTERP0_CTRL_LANE0_SHIFT_LSB) & SIO_INTERP0_CTRL_LANE0_SHIFT_BITS);
}
/*! \brief Set the interpolator mask range
* \ingroup interp_config
*
* Sets the range of bits (least to most) that are allowed to pass through the interpolator
*
* \param c Pointer to interpolation config
* \param mask_lsb The least significant bit allowed to pass
* \param mask_msb The most significant bit allowed to pass
*/
static inline void interp_config_set_mask(interp_config *c, uint mask_lsb, uint mask_msb) {
valid_params_if(HARDWARE_INTERP, mask_msb < 32);
valid_params_if(HARDWARE_INTERP, mask_lsb <= mask_msb);
c->ctrl = (c->ctrl & ~(SIO_INTERP0_CTRL_LANE0_MASK_LSB_BITS | SIO_INTERP0_CTRL_LANE0_MASK_MSB_BITS)) |
((mask_lsb << SIO_INTERP0_CTRL_LANE0_MASK_LSB_LSB) & SIO_INTERP0_CTRL_LANE0_MASK_LSB_BITS) |
((mask_msb << SIO_INTERP0_CTRL_LANE0_MASK_MSB_LSB) & SIO_INTERP0_CTRL_LANE0_MASK_MSB_BITS);
}
/*! \brief Enable cross input
* \ingroup interp_config
*
* Allows feeding of the accumulator content from the other lane back in to this lanes shift+mask hardware.
* This will take effect even if the interp_config_set_add_raw option is set as the cross input mux is before the
* shift+mask bypass
*
* \param c Pointer to interpolation config
* \param cross_input If true, enable the cross input.
*/
static inline void interp_config_set_cross_input(interp_config *c, bool cross_input) {
c->ctrl = (c->ctrl & ~SIO_INTERP0_CTRL_LANE0_CROSS_INPUT_BITS) |
(cross_input ? SIO_INTERP0_CTRL_LANE0_CROSS_INPUT_BITS : 0);
}
/*! \brief Enable cross results
* \ingroup interp_config
*
* Allows feeding of the other lane’s result into this lane’s accumulator on a POP operation.
*
* \param c Pointer to interpolation config
* \param cross_result If true, enables the cross result
*/
static inline void interp_config_set_cross_result(interp_config *c, bool cross_result) {
c->ctrl = (c->ctrl & ~SIO_INTERP0_CTRL_LANE0_CROSS_RESULT_BITS) |
(cross_result ? SIO_INTERP0_CTRL_LANE0_CROSS_RESULT_BITS : 0);
}
/*! \brief Set sign extension
* \ingroup interp_config
*
* Enables signed mode, where the shifted and masked accumulator value is sign-extended to 32 bits
* before adding to BASE1, and LANE1 PEEK/POP results appear extended to 32 bits when read by processor.
*
* \param c Pointer to interpolation config
* \param _signed If true, enables sign extension
*/
static inline void interp_config_set_signed(interp_config *c, bool _signed) {
c->ctrl = (c->ctrl & ~SIO_INTERP0_CTRL_LANE0_SIGNED_BITS) |
(_signed ? SIO_INTERP0_CTRL_LANE0_SIGNED_BITS : 0);
}
/*! \brief Set raw add option
* \ingroup interp_config
*
* When enabled, mask + shift is bypassed for LANE0 result. This does not affect the FULL result.
*
* \param c Pointer to interpolation config
* \param add_raw If true, enable raw add option.
*/
static inline void interp_config_set_add_raw(interp_config *c, bool add_raw) {
c->ctrl = (c->ctrl & ~SIO_INTERP0_CTRL_LANE0_ADD_RAW_BITS) |
(add_raw ? SIO_INTERP0_CTRL_LANE0_ADD_RAW_BITS : 0);
}
/*! \brief Set blend mode
* \ingroup interp_config
*
* If enabled, LANE1 result is a linear interpolation between BASE0 and BASE1, controlled
* by the 8 LSBs of lane 1 shift and mask value (a fractional number between 0 and 255/256ths)
*
* LANE0 result does not have BASE0 added (yields only the 8 LSBs of lane 1 shift+mask value)
*
* FULL result does not have lane 1 shift+mask value added (BASE2 + lane 0 shift+mask)
*
* LANE1 SIGNED flag controls whether the interpolation is signed or unsig
*
* \param c Pointer to interpolation config
* \param blend Set true to enable blend mode.
*/
static inline void interp_config_set_blend(interp_config *c, bool blend) {
c->ctrl = (c->ctrl & ~SIO_INTERP0_CTRL_LANE0_BLEND_BITS) |
(blend ? SIO_INTERP0_CTRL_LANE0_BLEND_BITS : 0);
}
/*! \brief Set interpolator clamp mode (Interpolator 1 only)
* \ingroup interp_config
*
* Only present on INTERP1 on each core. If CLAMP mode is enabled:
* - LANE0 result is a shifted and masked ACCUM0, clamped by a lower bound of BASE0 and an upper bound of BASE1.
* - Signedness of these comparisons is determined by LANE0_CTRL_SIGNED
*
* \param c Pointer to interpolation config
* \param clamp Set true to enable clamp mode
*/
static inline void interp_config_set_clamp(interp_config *c, bool clamp) {
c->ctrl = (c->ctrl & ~SIO_INTERP1_CTRL_LANE0_CLAMP_BITS) |
(clamp ? SIO_INTERP1_CTRL_LANE0_CLAMP_BITS : 0);
}
/*! \brief Set interpolator Force bits
* \ingroup interp_config
*
* ORed into bits 29:28 of the lane result presented to the processor on the bus.
*
* No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence
* of pointers into flash or SRAM
*
* \param c Pointer to interpolation config
* \param bits Sets the force bits to that specified. Range 0-3 (two bits)
*/
static inline void interp_config_set_force_bits(interp_config *c, uint bits) {
invalid_params_if(HARDWARE_INTERP, bits > 3);
// note cannot use hw_set_bits on SIO
c->ctrl = (c->ctrl & ~SIO_INTERP0_CTRL_LANE0_FORCE_MSB_BITS) |
(bits << SIO_INTERP0_CTRL_LANE0_FORCE_MSB_LSB);
}
/*! \brief Get a default configuration
* \ingroup interp_config
*
* \return A default interpolation configuration
*/
static inline interp_config interp_default_config(void) {
interp_config c = {0};
// Just pass through everything
interp_config_set_mask(&c, 0, 31);
return c;
}
/*! \brief Send configuration to a lane
* \ingroup interp_config
*
* If an invalid configuration is specified (ie a lane specific item is set on wrong lane),
* depending on setup this function can panic.
*
* \param interp Interpolator instance, interp0 or interp1.
* \param lane The lane to set
* \param config Pointer to interpolation config
*/
static inline void interp_set_config(interp_hw_t *interp, uint lane, interp_config *config) {
invalid_params_if(HARDWARE_INTERP, lane > 1);
invalid_params_if(HARDWARE_INTERP, config->ctrl & SIO_INTERP1_CTRL_LANE0_CLAMP_BITS &&
(!interp_index(interp) || lane)); // only interp1 lane 0 has clamp bit
invalid_params_if(HARDWARE_INTERP, config->ctrl & SIO_INTERP0_CTRL_LANE0_BLEND_BITS &&
(interp_index(interp) || lane)); // only interp0 lane 0 has blend bit
interp->ctrl[lane] = config->ctrl;
}
/*! \brief Directly set the force bits on a specified lane
* \ingroup hardware_interp
*
* These bits are ORed into bits 29:28 of the lane result presented to the processor on the bus.
* There is no effect on the internal 32-bit datapath.
*
* Useful for using a lane to generate sequence of pointers into flash or SRAM, saving a subsequent
* OR or add operation.
*
* \param interp Interpolator instance, interp0 or interp1.
* \param lane The lane to set
* \param bits The bits to set (bits 0 and 1, value range 0-3)
*/
static inline void interp_set_force_bits(interp_hw_t *interp, uint lane, uint bits) {
// note cannot use hw_set_bits on SIO
interp->ctrl[lane] = interp->ctrl[lane] | (bits << SIO_INTERP0_CTRL_LANE0_FORCE_MSB_LSB);
}
typedef struct {
uint32_t accum[2];
uint32_t base[3];
uint32_t ctrl[2];
} interp_hw_save_t;
/*! \brief Save the specified interpolator state
* \ingroup hardware_interp
*
* Can be used to save state if you need an interpolator for another purpose, state
* can then be recovered afterwards and continue from that point
*
* \param interp Interpolator instance, interp0 or interp1.
* \param saver Pointer to the save structure to fill in
*/
void interp_save(interp_hw_t *interp, interp_hw_save_t *saver);
/*! \brief Restore an interpolator state
* \ingroup hardware_interp
*
* \param interp Interpolator instance, interp0 or interp1.
* \param saver Pointer to save structure to reapply to the specified interpolator
*/
void interp_restore(interp_hw_t *interp, interp_hw_save_t *saver);
/*! \brief Sets the interpolator base register by lane
* \ingroup hardware_interp
*
* \param interp Interpolator instance, interp0 or interp1.
* \param lane The lane number, 0 or 1 or 2
* \param val The value to apply to the register
*/
static inline void interp_set_base(interp_hw_t *interp, uint lane, uint32_t val) {
interp->base[lane] = val;
}
/*! \brief Gets the content of interpolator base register by lane
* \ingroup hardware_interp
*
* \param interp Interpolator instance, interp0 or interp1.
* \param lane The lane number, 0 or 1 or 2
* \return The current content of the lane base register
*/
static inline uint32_t interp_get_base(interp_hw_t *interp, uint lane) {
return interp->base[lane];
}
/*! \brief Sets the interpolator base registers simultaneously
* \ingroup hardware_interp
*
* The lower 16 bits go to BASE0, upper bits to BASE1 simultaneously.
* Each half is sign-extended to 32 bits if that lane’s SIGNED flag is set.
*
* \param interp Interpolator instance, interp0 or interp1.
* \param val The value to apply to the register
*/
static inline void interp_set_base_both(interp_hw_t *interp, uint32_t val) {
interp->base01 = val;
}
/*! \brief Sets the interpolator accumulator register by lane
* \ingroup hardware_interp
*
* \param interp Interpolator instance, interp0 or interp1.
* \param lane The lane number, 0 or 1
* \param val The value to apply to the register
*/
static inline void interp_set_accumulator(interp_hw_t *interp, uint lane, uint32_t val) {
interp->accum[lane] = val;
}
/*! \brief Gets the content of the interpolator accumulator register by lane
* \ingroup hardware_interp
*
* \param interp Interpolator instance, interp0 or interp1.
* \param lane The lane number, 0 or 1
* \return The current content of the register
*/
static inline uint32_t interp_get_accumulator(interp_hw_t *interp, uint lane) {
return interp->accum[lane];
}
/*! \brief Read lane result, and write lane results to both accumulators to update the interpolator
* \ingroup hardware_interp
*
* \param interp Interpolator instance, interp0 or interp1.
* \param lane The lane number, 0 or 1
* \return The content of the lane result register
*/
static inline uint32_t interp_pop_lane_result(interp_hw_t *interp, uint lane) {
return interp->pop[lane];
}
/*! \brief Read lane result
* \ingroup hardware_interp
*
* \param interp Interpolator instance, interp0 or interp1.
* \param lane The lane number, 0 or 1
* \return The content of the lane result register
*/
static inline uint32_t interp_peek_lane_result(interp_hw_t *interp, uint lane) {
return interp->peek[lane];
}
/*! \brief Read lane result, and write lane results to both accumulators to update the interpolator
* \ingroup hardware_interp
*
* \param interp Interpolator instance, interp0 or interp1.
* \return The content of the FULL register
*/
static inline uint32_t interp_pop_full_result(interp_hw_t *interp) {
return interp->pop[2];
}
/*! \brief Read lane result
* \ingroup hardware_interp
*
* \param interp Interpolator instance, interp0 or interp1.
* \return The content of the FULL register
*/
static inline uint32_t interp_peek_full_result(interp_hw_t *interp) {
return interp->peek[2];
}
/*! \brief Add to accumulator
* \ingroup hardware_interp
*
* Atomically add the specified value to the accumulator on the specified lane
*
* \param interp Interpolator instance, interp0 or interp1.
* \param lane The lane number, 0 or 1
* \param val Value to add
*/
static inline void interp_add_accumulater(interp_hw_t *interp, uint lane, uint32_t val) {
interp->add_raw[lane] = val;
}
/*! \brief Get raw lane value
* \ingroup hardware_interp
*
* Returns the raw shift and mask value from the specified lane, BASE0 is NOT added
*
* \param interp Interpolator instance, interp0 or interp1.
* \param lane The lane number, 0 or 1
* \return The raw shift/mask value
*/
static inline uint32_t interp_get_raw(interp_hw_t *interp, uint lane) {
return interp->add_raw[lane];
}
#ifdef __cplusplus
}
#endif
#endif

496
arch/arm/src/rp23xx/hardware/irq.h
View file

@ -1,496 +0,0 @@
/*
* Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _HARDWARE_IRQ_H
#define _HARDWARE_IRQ_H
// These two config items are also used by assembler, so keeping separate
// PICO_CONFIG: PICO_MAX_SHARED_IRQ_HANDLERS, Maximum number of shared IRQ handlers, default=4, advanced=true, group=hardware_irq
#ifndef PICO_MAX_SHARED_IRQ_HANDLERS
#define PICO_MAX_SHARED_IRQ_HANDLERS 4
#endif
// PICO_CONFIG: PICO_DISABLE_SHARED_IRQ_HANDLERS, Disable shared IRQ handlers, type=bool, default=0, group=hardware_irq
#ifndef PICO_DISABLE_SHARED_IRQ_HANDLERS
#define PICO_DISABLE_SHARED_IRQ_HANDLERS 0
#endif
// PICO_CONFIG: PICO_VTABLE_PER_CORE, user is using separate vector tables per core, type=bool, default=0, group=hardware_irq
#ifndef PICO_VTABLE_PER_CORE
#define PICO_VTABLE_PER_CORE 0
#endif
#ifndef __ASSEMBLER__
#include "pico.h"
#include "hardware/address_mapped.h"
#include "hardware/regs/intctrl.h"
#include "pico/platform/cpu_regs.h"
/** \file irq.h
* \defgroup hardware_irq hardware_irq
*
* \brief Hardware interrupt handling API
*
* The RP2040 uses the standard ARM nested vectored interrupt controller (NVIC).
*
* Interrupts are identified by a number from 0 to 31.
*
* On the RP2040, only the lower 26 IRQ signals are connected on the NVIC; IRQs 26 to 31 are tied to zero (never firing).
*
* There is one NVIC per core, and each core's NVIC has the same hardware interrupt lines routed to it, with the exception of the IO interrupts
* where there is one IO interrupt per bank, per core. These are completely independent, so, for example, processor 0 can be
* interrupted by GPIO 0 in bank 0, and processor 1 by GPIO 1 in the same bank.
*
* \note That all IRQ APIs affect the executing core only (i.e. the core calling the function).
*
* \note You should not enable the same (shared) IRQ number on both cores, as this will lead to race conditions
* or starvation of one of the cores. Additionally, don't forget that disabling interrupts on one core does not disable interrupts
* on the other core.
*
* There are three different ways to set handlers for an IRQ:
* - Calling irq_add_shared_handler() at runtime to add a handler for a multiplexed interrupt (e.g. GPIO bank) on the current core. Each handler, should check and clear the relevant hardware interrupt source
* - Calling irq_set_exclusive_handler() at runtime to install a single handler for the interrupt on the current core
* - Defining the interrupt handler explicitly in your application (e.g. by defining void `isr_dma_0` will make that function the handler for the DMA_IRQ_0 on core 0, and
* you will not be able to change it using the above APIs at runtime). Using this method can cause link conflicts at runtime, and offers no runtime performance benefit (i.e, it should not generally be used).
*
* \note If an IRQ is enabled and fires with no handler installed, a breakpoint will be hit and the IRQ number will
* be in register r0.
*
* \section interrupt_nums Interrupt Numbers
*
* A set of defines is available (intctrl.h) with these names to avoid using the numbers directly.
*
* \if rp2040_specific
* On RP2040 the interrupt numbers are as follows:
*
* IRQ | Interrupt Source
* ----|-----------------
* 0 | TIMER_IRQ_0
* 1 | TIMER_IRQ_1
* 2 | TIMER_IRQ_2
* 3 | TIMER_IRQ_3
* 4 | PWM_IRQ_WRAP
* 5 | USBCTRL_IRQ
* 6 | XIP_IRQ
* 7 | PIO0_IRQ_0
* 8 | PIO0_IRQ_1
* 9 | PIO1_IRQ_0
* 10 | PIO1_IRQ_1
* 11 | DMA_IRQ_0
* 12 | DMA_IRQ_1
* 13 | IO_IRQ_BANK0
* 14 | IO_IRQ_QSPI
* 15 | SIO_IRQ_PROC0
* 16 | SIO_IRQ_PROC1
* 17 | CLOCKS_IRQ
* 18 | SPI0_IRQ
* 19 | SPI1_IRQ
* 20 | UART0_IRQ
* 21 | UART1_IRQ
* 22 | ADC0_IRQ_FIFO
* 23 | I2C0_IRQ
* 24 | I2C1_IRQ
* 25 | RTC_IRQ
* \endif
*
* \if rp2350_specific
* On RP2350 the interrupt numbers are as follows:
*
* IRQ | Interrupt Source
* ----|-----------------
* 0 | TIMER0_IRQ_0
* 1 | TIMER0_IRQ_1
* 2 | TIMER0_IRQ_2
* 3 | TIMER0_IRQ_3
* 4 | TIMER1_IRQ_0
* 5 | TIMER1_IRQ_1
* 6 | TIMER1_IRQ_2
* 7 | TIMER1_IRQ_3
* 8 | PWM_IRQ_WRAP_0
* 9 | PWM_IRQ_WRAP_1
* 10 | DMA_IRQ_0
* 11 | DMA_IRQ_1
* 12 | DMA_IRQ_2
* 13 | DMA_IRQ_3
* 14 | USBCTRL_IRQ
* 15 | PIO0_IRQ_0
* 16 | PIO0_IRQ_1
* 17 | PIO1_IRQ_0
* 18 | PIO1_IRQ_1
* 19 | PIO2_IRQ_0
* 20 | PIO2_IRQ_1
* 21 | IO_IRQ_BANK0
* 22 | IO_IRQ_BANK0_NS
* 23 | IO_IRQ_QSPI
* 24 | IO_IRQ_QSPI_NS
* 25 | SIO_IRQ_FIFO
* 26 | SIO_IRQ_BELL
* 27 | SIO_IRQ_FIFO_NS
* 28 | SIO_IRQ_BELL_NS
* 29 | SIO_IRQ_MTIMECMP
* 30 | CLOCKS_IRQ
* 31 | SPI0_IRQ
* 32 | SPI1_IRQ
* 33 | UART0_IRQ
* 34 | UART1_IRQ
* 35 | ADC_IRQ_FIFO
* 36 | I2C0_IRQ
* 37 | I2C1_IRQ
* 38 | OTP_IRQ
* 39 | TRNG_IRQ
* 40 | PROC0_IRQ_CTI
* 41 | PROC1_IRQ_CTI
* 42 | PLL_SYS_IRQ
* 43 | PLL_USB_IRQ
* 44 | POWMAN_IRQ_POW
* 45 | POWMAN_IRQ_TIMER
* 46 | SPAREIRQ_IRQ_0
* 47 | SPAREIRQ_IRQ_1
* 48 | SPAREIRQ_IRQ_2
* 49 | SPAREIRQ_IRQ_3
* 50 | SPAREIRQ_IRQ_4
* 51 | SPAREIRQ_IRQ_5
* \endif
*/
// PICO_CONFIG: PICO_DEFAULT_IRQ_PRIORITY, Define the default IRQ priority, default=0x80, group=hardware_irq
#ifndef PICO_DEFAULT_IRQ_PRIORITY
#define PICO_DEFAULT_IRQ_PRIORITY 0x80
#endif
#define PICO_LOWEST_IRQ_PRIORITY 0xff
#define PICO_HIGHEST_IRQ_PRIORITY 0x00
// PICO_CONFIG: PICO_SHARED_IRQ_HANDLER_DEFAULT_ORDER_PRIORITY, Set default shared IRQ order priority, default=0x80, group=hardware_irq
#ifndef PICO_SHARED_IRQ_HANDLER_DEFAULT_ORDER_PRIORITY
#define PICO_SHARED_IRQ_HANDLER_DEFAULT_ORDER_PRIORITY 0x80
#endif
#define PICO_SHARED_IRQ_HANDLER_HIGHEST_ORDER_PRIORITY 0xff
#define PICO_SHARED_IRQ_HANDLER_LOWEST_ORDER_PRIORITY 0x00
// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_HARDWARE_IRQ, Enable/disable assertions in the hardware_irq module, type=bool, default=0, group=hardware_irq
#ifndef PARAM_ASSERTIONS_ENABLED_HARDWARE_IRQ
#ifdef PARAM_ASSERTIONS_ENABLED_IRQ // backwards compatibility with SDK < 2.0.0
#define PARAM_ASSERTIONS_ENABLED_HARDWARE_IRQ PARAM_ASSERTIONS_ENABLED_IRQ
#else
#define PARAM_ASSERTIONS_ENABLED_HARDWARE_IRQ 0
#endif
#endif
#ifdef __cplusplus
extern "C" {
#endif
/*! \brief Interrupt handler function type
* \ingroup hardware_irq
*
* All interrupts handlers should be of this type, and follow normal ARM EABI register saving conventions
*/
typedef void (*irq_handler_t)(void);
static inline void check_irq_param(__unused uint num) {
invalid_params_if(HARDWARE_IRQ, num >= NUM_IRQS);
}
/*! \brief Set specified interrupt's priority
* \ingroup hardware_irq
*
* \param num Interrupt number \ref interrupt_nums
* \param hardware_priority Priority to set.
* Numerically-lower values indicate a higher priority. Hardware priorities
* range from 0 (highest priority) to 255 (lowest priority). To make it easier to specify
* higher or lower priorities than the default, all IRQ priorities are
* initialized to PICO_DEFAULT_IRQ_PRIORITY by the SDK runtime at startup.
* PICO_DEFAULT_IRQ_PRIORITY defaults to 0x80
*
* \if rp2040_specific
* Only the top 2 bits are significant on ARM Cortex-M0+ on RP2040.
* \endif
*
* \if rp2350_specific
* Only the top 4 bits are significant on ARM Cortex-M33 or Hazard3 (RISC-V) on RP2350.
* Note that this API uses the same (inverted) ordering as ARM on RISC-V
* \endif
*/
void irq_set_priority(uint num, uint8_t hardware_priority);
/*! \brief Get specified interrupt's priority
* \ingroup hardware_irq
*
* Numerically-lower values indicate a higher priority. Hardware priorities
* range from 0 (highest priority) to 255 (lowest priority). To make it easier to specify
* higher or lower priorities than the default, all IRQ priorities are
* initialized to PICO_DEFAULT_IRQ_PRIORITY by the SDK runtime at startup.
* PICO_DEFAULT_IRQ_PRIORITY defaults to 0x80
*
* \if rp2040_specific
* Only the top 2 bits are significant on ARM Cortex-M0+ on RP2040.
* \endif
*
* \if rp2350_specific
* Only the top 4 bits are significant on ARM Cortex-M33 or Hazard3 (RISC-V) on RP2350.
* Note that this API uses the same (inverted) ordering as ARM on RISC-V
* \endif
*
* \param num Interrupt number \ref interrupt_nums
* \return the IRQ priority
*/
uint irq_get_priority(uint num);
/*! \brief Enable or disable a specific interrupt on the executing core
* \ingroup hardware_irq
*
* \param num Interrupt number \ref interrupt_nums
* \param enabled true to enable the interrupt, false to disable
*/
void irq_set_enabled(uint num, bool enabled);
/*! \brief Determine if a specific interrupt is enabled on the executing core
* \ingroup hardware_irq
*
* \param num Interrupt number \ref interrupt_nums
* \return true if the interrupt is enabled
*/
bool irq_is_enabled(uint num);
/*! \brief Enable/disable multiple interrupts on the executing core
* \ingroup hardware_irq
*
* \param mask 32-bit mask with one bits set for the interrupts to enable/disable \ref interrupt_nums
* \param enabled true to enable the interrupts, false to disable them.
*/
void irq_set_mask_enabled(uint32_t mask, bool enabled);
/*! \brief Enable/disable multiple interrupts on the executing core
* \ingroup hardware_irq
*
* \param n the index of the mask to update. n == 0 means 0->31, n == 1 mean 32->63 etc.
* \param mask 32-bit mask with one bits set for the interrupts to enable/disable \ref interrupt_nums
* \param enabled true to enable the interrupts, false to disable them.
*/
void irq_set_mask_n_enabled(uint n, uint32_t mask, bool enabled);
/*! \brief Set an exclusive interrupt handler for an interrupt on the executing core.
* \ingroup hardware_irq
*
* Use this method to set a handler for single IRQ source interrupts, or when
* your code, use case or performance requirements dictate that there should
* no other handlers for the interrupt.
*
* This method will assert if there is already any sort of interrupt handler installed
* for the specified irq number.
*
* \param num Interrupt number \ref interrupt_nums
* \param handler The handler to set. See \ref irq_handler_t
* \see irq_add_shared_handler()
*/
void irq_set_exclusive_handler(uint num, irq_handler_t handler);
/*! \brief Get the exclusive interrupt handler for an interrupt on the executing core.
* \ingroup hardware_irq
*
* This method will return an exclusive IRQ handler set on this core
* by irq_set_exclusive_handler if there is one.
*
* \param num Interrupt number \ref interrupt_nums
* \see irq_set_exclusive_handler()
* \return handler The handler if an exclusive handler is set for the IRQ,
* NULL if no handler is set or shared/shareable handlers are installed
*/
irq_handler_t irq_get_exclusive_handler(uint num);
/*! \brief Add a shared interrupt handler for an interrupt on the executing core
* \ingroup hardware_irq
*
* Use this method to add a handler on an irq number shared between multiple distinct hardware sources (e.g. GPIO, DMA or PIO IRQs).
* Handlers added by this method will all be called in sequence from highest order_priority to lowest. The
* irq_set_exclusive_handler() method should be used instead if you know there will or should only ever be one handler for the interrupt.
*
* This method will assert if there is an exclusive interrupt handler set for this irq number on this core, or if
* the (total across all IRQs on both cores) maximum (configurable via PICO_MAX_SHARED_IRQ_HANDLERS) number of shared handlers
* would be exceeded.
*
* \param num Interrupt number \ref interrupt_nums
* \param handler The handler to set. See \ref irq_handler_t
* \param order_priority The order priority controls the order that handlers for the same IRQ number on the core are called.
* The shared irq handlers for an interrupt are all called when an IRQ fires, however the order of the calls is based
* on the order_priority (higher priorities are called first, identical priorities are called in undefined order). A good
* rule of thumb is to use PICO_SHARED_IRQ_HANDLER_DEFAULT_ORDER_PRIORITY if you don't much care, as it is in the middle of
* the priority range by default.
*
* \note The order_priority uses \em higher values for higher priorities which is the \em opposite of the CPU interrupt priorities passed
* to irq_set_priority() which use lower values for higher priorities.
*
* \see irq_set_exclusive_handler()
*/
void irq_add_shared_handler(uint num, irq_handler_t handler, uint8_t order_priority);
/*! \brief Remove a specific interrupt handler for the given irq number on the executing core
* \ingroup hardware_irq
*
* This method may be used to remove an irq set via either irq_set_exclusive_handler() or
* irq_add_shared_handler(), and will assert if the handler is not currently installed for the given
* IRQ number
*
* \note This method may *only* be called from user (non IRQ code) or from within the handler
* itself (i.e. an IRQ handler may remove itself as part of handling the IRQ). Attempts to call
* from another IRQ will cause an assertion.
*
* \param num Interrupt number \ref interrupt_nums
* \param handler The handler to removed.
* \see irq_set_exclusive_handler()
* \see irq_add_shared_handler()
*/
void irq_remove_handler(uint num, irq_handler_t handler);
/*! \brief Determine if the current handler for the given number is shared
* \ingroup hardware_irq
*
* \param num Interrupt number \ref interrupt_nums
* \return true if the specified IRQ has a shared handler
*/
bool irq_has_shared_handler(uint num);
/*! \brief Get the current IRQ handler for the specified IRQ from the currently installed hardware vector table (VTOR)
* of the execution core
* \ingroup hardware_irq
*
* \param num Interrupt number \ref interrupt_nums
* \return the address stored in the VTABLE for the given irq number
*/
irq_handler_t irq_get_vtable_handler(uint num);
/*! \brief Clear a specific interrupt on the executing core
* \ingroup hardware_irq
*
* This method is only useful for "software" IRQs that are not connected to hardware (e.g. IRQs 26-31 on RP2040)
* as the the NVIC always reflects the current state of the IRQ state of the hardware for hardware IRQs, and clearing
* of the IRQ state of the hardware is performed via the hardware's registers instead.
*
* \param int_num Interrupt number \ref interrupt_nums
*/
static inline void irq_clear(uint int_num) {
#if PICO_RP2040
*((volatile uint32_t *) (PPB_BASE + M0PLUS_NVIC_ICPR_OFFSET)) = (1u << ((uint32_t) (int_num & 0x1F)));
#elif defined(__riscv)
// External IRQs are not latched, but we should clear the IRQ force bit here
hazard3_irqarray_clear(RVCSR_MEIFA_OFFSET, int_num / 16, 1u << (int_num % 16));
#else
nvic_hw->icpr[int_num/32] = 1 << (int_num % 32);
#endif
}
/*! \brief Force an interrupt to be pending on the executing core
* \ingroup hardware_irq
*
* This should generally not be used for IRQs connected to hardware.
*
* \param num Interrupt number \ref interrupt_nums
*/
void irq_set_pending(uint num);
/*! \brief Perform IRQ priority initialization for the current core
*
* \note This is an internal method and user should generally not call it.
*/
void runtime_init_per_core_irq_priorities(void);
static __force_inline void irq_init_priorities(void) {
runtime_init_per_core_irq_priorities();
}
/*! \brief Claim ownership of a user IRQ on the calling core
* \ingroup hardware_irq
*
* User IRQs starting from FIRST_USER_IRQ are not connected to any hardware, but can be triggered by \ref irq_set_pending.
*
* \note User IRQs are a core local feature; they cannot be used to communicate between cores. Therefore all functions
* dealing with Uer IRQs affect only the calling core
*
* This method explicitly claims ownership of a user IRQ, so other code can know it is being used.
*
* \param irq_num the user IRQ to claim
*/
void user_irq_claim(uint irq_num);
/*! \brief Mark a user IRQ as no longer used on the calling core
* \ingroup hardware_irq
*
* User IRQs starting from FIRST_USER_IRQ are not connected to any hardware, but can be triggered by \ref irq_set_pending.
*
* \note User IRQs are a core local feature; they cannot be used to communicate between cores. Therefore all functions
* dealing with Uer IRQs affect only the calling core
*
* This method explicitly releases ownership of a user IRQ, so other code can know it is free to use.
*
* \note it is customary to have disabled the irq and removed the handler prior to calling this method.
*
* \param irq_num the irq irq_num to unclaim
*/
void user_irq_unclaim(uint irq_num);
/*! \brief Claim ownership of a free user IRQ on the calling core
* \ingroup hardware_irq
*
* User IRQs starting from FIRST_USER_IRQ are not connected to any hardware, but can be triggered by \ref irq_set_pending.
*
* \note User IRQs are a core local feature; they cannot be used to communicate between cores. Therefore all functions
* dealing with Uer IRQs affect only the calling core
*
* This method explicitly claims ownership of an unused user IRQ if there is one, so other code can know it is being used.
*
* \param required if true the function will panic if none are available
* \return the user IRQ number or -1 if required was false, and none were free
*/
int user_irq_claim_unused(bool required);
/*
*! \brief Check if a user IRQ is in use on the calling core
* \ingroup hardware_irq
*
* User IRQs starting from FIRST_USER_IRQ are not connected to any hardware, but can be triggered by \ref irq_set_pending.
*
* \note User IRQs are a core local feature; they cannot be used to communicate between cores. Therefore all functions
* dealing with Uer IRQs affect only the calling core
*
* \param irq_num the irq irq_num
* \return true if the irq_num is claimed, false otherwise
* \sa user_irq_claim
* \sa user_irq_unclaim
* \sa user_irq_claim_unused
*/
bool user_irq_is_claimed(uint irq_num);
void __unhandled_user_irq(void);
#ifdef __riscv
enum riscv_vector_num {
RISCV_VEC_MACHINE_EXCEPTION = 0,
RISCV_VEC_MACHINE_SOFTWARE_IRQ = 3,
RISCV_VEC_MACHINE_TIMER_IRQ = 7,
RISCV_VEC_MACHINE_EXTERNAL_IRQ = 11,
};
irq_handler_t irq_set_riscv_vector_handler(enum riscv_vector_num index, irq_handler_t handler);
#endif
#if PICO_SECURE
static inline void irq_assign_to_ns(uint irq_num, bool ns) {
check_irq_param(irq_num);
if (ns) nvic_hw->itns[irq_num >> 5] |= 1u << (irq_num & 0x1fu);
else nvic_hw->itns[irq_num >> 5] &= ~(1u << (irq_num & 0x1fu));
}
#endif
#ifdef __cplusplus
}
#endif
#endif
#endif

1876
arch/arm/src/rp23xx/hardware/pio.h
View file

File diff suppressed because it is too large Load diff

484
arch/arm/src/rp23xx/hardware/pio_instructions.h
View file

@ -1,484 +0,0 @@
/*
* Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _HARDWARE_PIO_INSTRUCTIONS_H
#define _HARDWARE_PIO_INSTRUCTIONS_H
#include "pico.h"
/** \brief PIO instruction encoding
* \defgroup pio_instructions pio_instructions
* \ingroup hardware_pio
*
* Functions for generating PIO instruction encodings programmatically. In debug builds
*`PARAM_ASSERTIONS_ENABLED_PIO_INSTRUCTIONS` can be set to 1 to enable validation of encoding function
* parameters.
*
* For fuller descriptions of the instructions in question see the "RP2040 Datasheet"
*/
// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_PIO_INSTRUCTIONS, Enable/disable assertions in the PIO instructions, type=bool, default=0, group=pio_instructions
#ifndef PARAM_ASSERTIONS_ENABLED_PIO_INSTRUCTIONS
#define PARAM_ASSERTIONS_ENABLED_PIO_INSTRUCTIONS 0
#endif
#ifdef __cplusplus
extern "C" {
#endif
enum pio_instr_bits {
pio_instr_bits_jmp = 0x0000,
pio_instr_bits_wait = 0x2000,
pio_instr_bits_in = 0x4000,
pio_instr_bits_out = 0x6000,
pio_instr_bits_push = 0x8000,
pio_instr_bits_pull = 0x8080,
pio_instr_bits_mov = 0xa000,
pio_instr_bits_irq = 0xc000,
pio_instr_bits_set = 0xe000,
};
#ifndef NDEBUG
#define _PIO_INVALID_IN_SRC 0x08u
#define _PIO_INVALID_OUT_DEST 0x10u
#define _PIO_INVALID_SET_DEST 0x20u
#define _PIO_INVALID_MOV_SRC 0x40u
#define _PIO_INVALID_MOV_DEST 0x80u
#else
#define _PIO_INVALID_IN_SRC 0u
#define _PIO_INVALID_OUT_DEST 0u
#define _PIO_INVALID_SET_DEST 0u
#define _PIO_INVALID_MOV_SRC 0u
#define _PIO_INVALID_MOV_DEST 0u
#endif
/*! \brief Enumeration of values to pass for source/destination args for instruction encoding functions
* \ingroup pio_instructions
*
* \note Not all values are suitable for all functions. Validity is only checked in debug mode when
* `PARAM_ASSERTIONS_ENABLED_PIO_INSTRUCTIONS` is 1
*/
enum pio_src_dest {
pio_pins = 0u,
pio_x = 1u,
pio_y = 2u,
pio_null = 3u | _PIO_INVALID_SET_DEST | _PIO_INVALID_MOV_DEST,
pio_pindirs = 4u | _PIO_INVALID_IN_SRC | _PIO_INVALID_MOV_SRC | _PIO_INVALID_MOV_DEST,
pio_exec_mov = 4u | _PIO_INVALID_IN_SRC | _PIO_INVALID_OUT_DEST | _PIO_INVALID_SET_DEST | _PIO_INVALID_MOV_SRC,
pio_status = 5u | _PIO_INVALID_IN_SRC | _PIO_INVALID_OUT_DEST | _PIO_INVALID_SET_DEST | _PIO_INVALID_MOV_DEST,
pio_pc = 5u | _PIO_INVALID_IN_SRC | _PIO_INVALID_SET_DEST | _PIO_INVALID_MOV_SRC,
pio_isr = 6u | _PIO_INVALID_SET_DEST,
pio_osr = 7u | _PIO_INVALID_OUT_DEST | _PIO_INVALID_SET_DEST,
pio_exec_out = 7u | _PIO_INVALID_IN_SRC | _PIO_INVALID_SET_DEST | _PIO_INVALID_MOV_SRC | _PIO_INVALID_MOV_DEST,
};
static inline uint _pio_major_instr_bits(uint instr) {
return instr & 0xe000u;
}
static inline uint _pio_encode_instr_and_args(enum pio_instr_bits instr_bits, uint arg1, uint arg2) {
valid_params_if(PIO_INSTRUCTIONS, arg1 <= 0x7);
#if PARAM_ASSERTIONS_ENABLED(PIO_INSTRUCTIONS)
uint32_t major = _pio_major_instr_bits(instr_bits);
if (major == pio_instr_bits_in || major == pio_instr_bits_out) {
assert(arg2 && arg2 <= 32);
} else {
assert(arg2 <= 31);
}
#endif
return instr_bits | (arg1 << 5u) | (arg2 & 0x1fu);
}
static inline uint _pio_encode_instr_and_src_dest(enum pio_instr_bits instr_bits, enum pio_src_dest dest, uint value) {
return _pio_encode_instr_and_args(instr_bits, dest & 7u, value);
}
/*! \brief Encode just the delay slot bits of an instruction
* \ingroup pio_instructions
*
* \note This function does not return a valid instruction encoding; instead it returns an encoding of the delay
* slot suitable for `OR`ing with the result of an encoding function for an actual instruction. Care should be taken when
* combining the results of this function with the results of \ref pio_encode_sideset and \ref pio_encode_sideset_opt
* as they share the same bits within the instruction encoding.
*
* \param cycles the number of cycles 0-31 (or less if side set is being used)
* \return the delay slot bits to be ORed with an instruction encoding
*/
static inline uint pio_encode_delay(uint cycles) {
// note that the maximum cycles will be smaller if sideset_bit_count > 0
valid_params_if(PIO_INSTRUCTIONS, cycles <= 0x1f);
return cycles << 8u;
}
/*! \brief Encode just the side set bits of an instruction (in non optional side set mode)
* \ingroup pio_instructions
*
* \note This function does not return a valid instruction encoding; instead it returns an encoding of the side set bits
* suitable for `OR`ing with the result of an encoding function for an actual instruction. Care should be taken when
* combining the results of this function with the results of \ref pio_encode_delay as they share the same bits
* within the instruction encoding.
*
* \param sideset_bit_count number of side set bits as would be specified via `.sideset` in pioasm
* \param value the value to sideset on the pins
* \return the side set bits to be ORed with an instruction encoding
*/
static inline uint pio_encode_sideset(uint sideset_bit_count, uint value) {
valid_params_if(PIO_INSTRUCTIONS, sideset_bit_count >= 1 && sideset_bit_count <= 5);
valid_params_if(PIO_INSTRUCTIONS, value <= ((1u << sideset_bit_count) - 1));
return value << (13u - sideset_bit_count);
}
/*! \brief Encode just the side set bits of an instruction (in optional -`opt` side set mode)
* \ingroup pio_instructions
*
* \note This function does not return a valid instruction encoding; instead it returns an encoding of the side set bits
* suitable for `OR`ing with the result of an encoding function for an actual instruction. Care should be taken when
* combining the results of this function with the results of \ref pio_encode_delay as they share the same bits
* within the instruction encoding.
*
* \param sideset_bit_count number of side set bits as would be specified via `.sideset <n> opt` in pioasm
* \param value the value to sideset on the pins
* \return the side set bits to be ORed with an instruction encoding
*/
static inline uint pio_encode_sideset_opt(uint sideset_bit_count, uint value) {
valid_params_if(PIO_INSTRUCTIONS, sideset_bit_count >= 1 && sideset_bit_count <= 4);
valid_params_if(PIO_INSTRUCTIONS, value <= ((1u << sideset_bit_count) - 1));
return 0x1000u | value << (12u - sideset_bit_count);
}
/*! \brief Encode an unconditional JMP instruction
* \ingroup pio_instructions
*
* This is the equivalent of `JMP <addr>`
*
* \param addr The target address 0-31 (an absolute address within the PIO instruction memory)
* \return The instruction encoding with 0 delay and no side set value
* \see pio_encode_delay, pio_encode_sideset, pio_encode_sideset_opt
*/
static inline uint pio_encode_jmp(uint addr) {
return _pio_encode_instr_and_args(pio_instr_bits_jmp, 0, addr);
}
/*! \brief Encode a conditional JMP if scratch X zero instruction
* \ingroup pio_instructions
*
* This is the equivalent of `JMP !X <addr>`
*
* \param addr The target address 0-31 (an absolute address within the PIO instruction memory)
* \return The instruction encoding with 0 delay and no side set value
* \see pio_encode_delay, pio_encode_sideset, pio_encode_sideset_opt
*/
static inline uint pio_encode_jmp_not_x(uint addr) {
return _pio_encode_instr_and_args(pio_instr_bits_jmp, 1, addr);
}
/*! \brief Encode a conditional JMP if scratch X non-zero (and post-decrement X) instruction
* \ingroup pio_instructions
*
* This is the equivalent of `JMP X-- <addr>`
*
* \param addr The target address 0-31 (an absolute address within the PIO instruction memory)
* \return The instruction encoding with 0 delay and no side set value
* \see pio_encode_delay, pio_encode_sideset, pio_encode_sideset_opt
*/
static inline uint pio_encode_jmp_x_dec(uint addr) {
return _pio_encode_instr_and_args(pio_instr_bits_jmp, 2, addr);
}
/*! \brief Encode a conditional JMP if scratch Y zero instruction
* \ingroup pio_instructions
*
* This is the equivalent of `JMP !Y <addr>`
*
* \param addr The target address 0-31 (an absolute address within the PIO instruction memory)
* \return The instruction encoding with 0 delay and no side set value
* \see pio_encode_delay, pio_encode_sideset, pio_encode_sideset_opt
*/
static inline uint pio_encode_jmp_not_y(uint addr) {
return _pio_encode_instr_and_args(pio_instr_bits_jmp, 3, addr);
}
/*! \brief Encode a conditional JMP if scratch Y non-zero (and post-decrement Y) instruction
* \ingroup pio_instructions
*
* This is the equivalent of `JMP Y-- <addr>`
*
* \param addr The target address 0-31 (an absolute address within the PIO instruction memory)
* \return The instruction encoding with 0 delay and no side set value
* \see pio_encode_delay, pio_encode_sideset, pio_encode_sideset_opt
*/
static inline uint pio_encode_jmp_y_dec(uint addr) {
return _pio_encode_instr_and_args(pio_instr_bits_jmp, 4, addr);
}
/*! \brief Encode a conditional JMP if scratch X not equal scratch Y instruction
* \ingroup pio_instructions
*
* This is the equivalent of `JMP X!=Y <addr>`
*
* \param addr The target address 0-31 (an absolute address within the PIO instruction memory)
* \return The instruction encoding with 0 delay and no side set value
* \see pio_encode_delay, pio_encode_sideset, pio_encode_sideset_opt
*/
static inline uint pio_encode_jmp_x_ne_y(uint addr) {
return _pio_encode_instr_and_args(pio_instr_bits_jmp, 5, addr);
}
/*! \brief Encode a conditional JMP if input pin high instruction
* \ingroup pio_instructions
*
* This is the equivalent of `JMP PIN <addr>`
*
* \param addr The target address 0-31 (an absolute address within the PIO instruction memory)
* \return The instruction encoding with 0 delay and no side set value
* \see pio_encode_delay, pio_encode_sideset, pio_encode_sideset_opt
*/
static inline uint pio_encode_jmp_pin(uint addr) {
return _pio_encode_instr_and_args(pio_instr_bits_jmp, 6, addr);
}
/*! \brief Encode a conditional JMP if output shift register not empty instruction
* \ingroup pio_instructions
*
* This is the equivalent of `JMP !OSRE <addr>`
*
* \param addr The target address 0-31 (an absolute address within the PIO instruction memory)
* \return The instruction encoding with 0 delay and no side set value
* \see pio_encode_delay, pio_encode_sideset, pio_encode_sideset_opt
*/
static inline uint pio_encode_jmp_not_osre(uint addr) {
return _pio_encode_instr_and_args(pio_instr_bits_jmp, 7, addr);
}
static inline uint _pio_encode_irq(bool relative, uint irq) {
valid_params_if(PIO_INSTRUCTIONS, irq <= 7);
return (relative ? 0x10u : 0x0u) | irq;
}
/*! \brief Encode a WAIT for GPIO pin instruction
* \ingroup pio_instructions
*
* This is the equivalent of `WAIT <polarity> GPIO <gpio>`
*
* \param polarity true for `WAIT 1`, false for `WAIT 0`
* \param gpio The real GPIO number 0-31
* \return The instruction encoding with 0 delay and no side set value
* \see pio_encode_delay, pio_encode_sideset, pio_encode_sideset_opt
*/
static inline uint pio_encode_wait_gpio(bool polarity, uint gpio) {
return _pio_encode_instr_and_args(pio_instr_bits_wait, 0u | (polarity ? 4u : 0u), gpio);
}
/*! \brief Encode a WAIT for pin instruction
* \ingroup pio_instructions
*
* This is the equivalent of `WAIT <polarity> PIN <pin>`
*
* \param polarity true for `WAIT 1`, false for `WAIT 0`
* \param pin The pin number 0-31 relative to the executing SM's input pin mapping
* \return The instruction encoding with 0 delay and no side set value
* \see pio_encode_delay, pio_encode_sideset, pio_encode_sideset_opt
*/
static inline uint pio_encode_wait_pin(bool polarity, uint pin) {
return _pio_encode_instr_and_args(pio_instr_bits_wait, 1u | (polarity ? 4u : 0u), pin);
}
/*! \brief Encode a WAIT for IRQ instruction
* \ingroup pio_instructions
*
* This is the equivalent of `WAIT <polarity> IRQ <irq> <relative>`
*
* \param polarity true for `WAIT 1`, false for `WAIT 0`
* \param relative true for a `WAIT IRQ <irq> REL`, false for regular `WAIT IRQ <irq>`
* \param irq the irq number 0-7
* \return The instruction encoding with 0 delay and no side set value
* \see pio_encode_delay, pio_encode_sideset, pio_encode_sideset_opt
*/
static inline uint pio_encode_wait_irq(bool polarity, bool relative, uint irq) {
valid_params_if(PIO_INSTRUCTIONS, irq <= 7);
return _pio_encode_instr_and_args(pio_instr_bits_wait, 2u | (polarity ? 4u : 0u), _pio_encode_irq(relative, irq));
}
/*! \brief Encode an IN instruction
* \ingroup pio_instructions
*
* This is the equivalent of `IN <src>, <count>`
*
* \param src The source to take data from
* \param count The number of bits 1-32
* \return The instruction encoding with 0 delay and no side set value
* \see pio_encode_delay, pio_encode_sideset, pio_encode_sideset_opt
*/
static inline uint pio_encode_in(enum pio_src_dest src, uint count) {
valid_params_if(PIO_INSTRUCTIONS, !(src & _PIO_INVALID_IN_SRC));
return _pio_encode_instr_and_src_dest(pio_instr_bits_in, src, count);
}
/*! \brief Encode an OUT instruction
* \ingroup pio_instructions
*
* This is the equivalent of `OUT <src>, <count>`
*
* \param dest The destination to write data to
* \param count The number of bits 1-32
* \return The instruction encoding with 0 delay and no side set value
* \see pio_encode_delay, pio_encode_sideset, pio_encode_sideset_opt
*/
static inline uint pio_encode_out(enum pio_src_dest dest, uint count) {
valid_params_if(PIO_INSTRUCTIONS, !(dest & _PIO_INVALID_OUT_DEST));
return _pio_encode_instr_and_src_dest(pio_instr_bits_out, dest, count);
}
/*! \brief Encode a PUSH instruction
* \ingroup pio_instructions
*
* This is the equivalent of `PUSH <if_full>, <block>`
*
* \param if_full true for `PUSH IF_FULL ...`, false for `PUSH ...`
* \param block true for `PUSH ... BLOCK`, false for `PUSH ...`
* \return The instruction encoding with 0 delay and no side set value
* \see pio_encode_delay, pio_encode_sideset, pio_encode_sideset_opt
*/
static inline uint pio_encode_push(bool if_full, bool block) {
return _pio_encode_instr_and_args(pio_instr_bits_push, (if_full ? 2u : 0u) | (block ? 1u : 0u), 0);
}
/*! \brief Encode a PULL instruction
* \ingroup pio_instructions
*
* This is the equivalent of `PULL <if_empty>, <block>`
*
* \param if_empty true for `PULL IF_EMPTY ...`, false for `PULL ...`
* \param block true for `PULL ... BLOCK`, false for `PULL ...`
* \return The instruction encoding with 0 delay and no side set value
* \see pio_encode_delay, pio_encode_sideset, pio_encode_sideset_opt
*/
static inline uint pio_encode_pull(bool if_empty, bool block) {
return _pio_encode_instr_and_args(pio_instr_bits_pull, (if_empty ? 2u : 0u) | (block ? 1u : 0u), 0);
}
/*! \brief Encode a MOV instruction
* \ingroup pio_instructions
*
* This is the equivalent of `MOV <dest>, <src>`
*
* \param dest The destination to write data to
* \param src The source to take data from
* \return The instruction encoding with 0 delay and no side set value
* \see pio_encode_delay, pio_encode_sideset, pio_encode_sideset_opt
*/
static inline uint pio_encode_mov(enum pio_src_dest dest, enum pio_src_dest src) {
valid_params_if(PIO_INSTRUCTIONS, !(dest & _PIO_INVALID_MOV_DEST));
valid_params_if(PIO_INSTRUCTIONS, !(src & _PIO_INVALID_MOV_SRC));
return _pio_encode_instr_and_src_dest(pio_instr_bits_mov, dest, src & 7u);
}
/*! \brief Encode a MOV instruction with bit invert
* \ingroup pio_instructions
*
* This is the equivalent of `MOV <dest>, ~<src>`
*
* \param dest The destination to write inverted data to
* \param src The source to take data from
* \return The instruction encoding with 0 delay and no side set value
* \see pio_encode_delay, pio_encode_sideset, pio_encode_sideset_opt
*/
static inline uint pio_encode_mov_not(enum pio_src_dest dest, enum pio_src_dest src) {
valid_params_if(PIO_INSTRUCTIONS, !(dest & _PIO_INVALID_MOV_DEST));
valid_params_if(PIO_INSTRUCTIONS, !(src & _PIO_INVALID_MOV_SRC));
return _pio_encode_instr_and_src_dest(pio_instr_bits_mov, dest, (1u << 3u) | (src & 7u));
}
/*! \brief Encode a MOV instruction with bit reverse
* \ingroup pio_instructions
*
* This is the equivalent of `MOV <dest>, ::<src>`
*
* \param dest The destination to write bit reversed data to
* \param src The source to take data from
* \return The instruction encoding with 0 delay and no side set value
* \see pio_encode_delay, pio_encode_sideset, pio_encode_sideset_opt
*/
static inline uint pio_encode_mov_reverse(enum pio_src_dest dest, enum pio_src_dest src) {
valid_params_if(PIO_INSTRUCTIONS, !(dest & _PIO_INVALID_MOV_DEST));
valid_params_if(PIO_INSTRUCTIONS, !(src & _PIO_INVALID_MOV_SRC));
return _pio_encode_instr_and_src_dest(pio_instr_bits_mov, dest, (2u << 3u) | (src & 7u));
}
/*! \brief Encode a IRQ SET instruction
* \ingroup pio_instructions
*
* This is the equivalent of `IRQ SET <irq> <relative>`
*
* \param relative true for a `IRQ SET <irq> REL`, false for regular `IRQ SET <irq>`
* \param irq the irq number 0-7
* \return The instruction encoding with 0 delay and no side set value
* \see pio_encode_delay, pio_encode_sideset, pio_encode_sideset_opt
*/
static inline uint pio_encode_irq_set(bool relative, uint irq) {
return _pio_encode_instr_and_args(pio_instr_bits_irq, 0, _pio_encode_irq(relative, irq));
}
/*! \brief Encode a IRQ WAIT instruction
* \ingroup pio_instructions
*
* This is the equivalent of `IRQ WAIT <irq> <relative>`
*
* \param relative true for a `IRQ WAIT <irq> REL`, false for regular `IRQ WAIT <irq>`
* \param irq the irq number 0-7
* \return The instruction encoding with 0 delay and no side set value
* \see pio_encode_delay, pio_encode_sideset, pio_encode_sideset_opt
*/
static inline uint pio_encode_irq_wait(bool relative, uint irq) {
return _pio_encode_instr_and_args(pio_instr_bits_irq, 1, _pio_encode_irq(relative, irq));
}
/*! \brief Encode a IRQ CLEAR instruction
* \ingroup pio_instructions
*
* This is the equivalent of `IRQ CLEAR <irq> <relative>`
*
* \param relative true for a `IRQ CLEAR <irq> REL`, false for regular `IRQ CLEAR <irq>`
* \param irq the irq number 0-7
* \return The instruction encoding with 0 delay and no side set value
* \see pio_encode_delay, pio_encode_sideset, pio_encode_sideset_opt
*/
static inline uint pio_encode_irq_clear(bool relative, uint irq) {
return _pio_encode_instr_and_args(pio_instr_bits_irq, 2, _pio_encode_irq(relative, irq));
}
/*! \brief Encode a SET instruction
* \ingroup pio_instructions
*
* This is the equivalent of `SET <dest>, <value>`
*
* \param dest The destination to apply the value to
* \param value The value 0-31
* \return The instruction encoding with 0 delay and no side set value
* \see pio_encode_delay, pio_encode_sideset, pio_encode_sideset_opt
*/
static inline uint pio_encode_set(enum pio_src_dest dest, uint value) {
valid_params_if(PIO_INSTRUCTIONS, !(dest & _PIO_INVALID_SET_DEST));
return _pio_encode_instr_and_src_dest(pio_instr_bits_set, dest, value);
}
/*! \brief Encode a NOP instruction
* \ingroup pio_instructions
*
* This is the equivalent of `NOP` which is itself encoded as `MOV y, y`
*
* \return The instruction encoding with 0 delay and no side set value
* \see pio_encode_delay, pio_encode_sideset, pio_encode_sideset_opt
*/
static inline uint pio_encode_nop(void) {
return pio_encode_mov(pio_y, pio_y);
}
#ifdef __cplusplus
}
#endif
#endif

163
arch/arm/src/rp23xx/hardware/platform_defs.h
View file

@ -1,163 +0,0 @@
/*
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _HARDWARE_PLATFORM_DEFS_H
#define _HARDWARE_PLATFORM_DEFS_H
// This header is included from C and assembler - intended mostly for #defines; guard other stuff with #ifdef __ASSEMBLER__
#ifndef _u
#ifdef __ASSEMBLER__
#define _u(x) x
#else
#define _u(x) x ## u
#endif
#endif
#define NUM_CORES _u(2)
#define NUM_DMA_CHANNELS _u(16)
#define NUM_DMA_TIMERS _u(4)
#define NUM_DMA_MPU_REGIONS _u(8)
#define NUM_DMA_IRQS _u(4)
#define NUM_IRQS _u(52)
#define NUM_USER_IRQS _u(6)
#define NUM_PIOS _u(3)
#define NUM_PIO_STATE_MACHINES _u(4)
#define NUM_PIO_IRQS _u(2)
#define NUM_PWM_SLICES _u(12)
#define NUM_PWM_IRQS _u(2)
#define NUM_SPIN_LOCKS _u(32)
#define NUM_UARTS _u(2)
#define NUM_I2CS _u(2)
#define NUM_SPIS _u(2)
#define NUM_GENERIC_TIMERS _u(2)
#define NUM_ALARMS _u(4)
#if PICO_RP2350A
#define NUM_ADC_CHANNELS _u(5)
#define ADC_BASE_PIN _u(26)
#else
#define NUM_ADC_CHANNELS _u(9)
#define ADC_BASE_PIN _u(40)
#endif
#define NUM_RESETS _u(28)
#define NUM_DOORBELLS _u(8)
#if PICO_RP2350A
#define NUM_BANK0_GPIOS _u(30)
#else
#define NUM_BANK0_GPIOS _u(48)
#endif
#define NUM_QSPI_GPIOS _u(6)
#define NUM_OTP_PAGES _u(64)
#define NUM_OTP_PAGE_ROWS _u(64)
#define NUM_OTP_ROWS (NUM_OTP_PAGES * NUM_OTP_PAGE_ROWS)
#define PIO_INSTRUCTION_COUNT _u(32)
#define NUM_MPU_REGIONS _u(8)
#define NUM_SAU_REGIONS _u(8)
#define NUM_BOOT_LOCKS _u(8)
#define BOOTRAM_SIZE _u(0x400)
#define USBCTRL_DPRAM_SIZE _u(4096)
#ifndef __riscv
#define HAS_GPIO_COPROCESSOR 1
#define HAS_DOUBLE_COPROCESSOR 1
#define HAS_REDUNDANCY_COPROCESSOR 1
#endif
#define HAS_POWMAN_TIMER 1
#define HAS_RP2350_TRNG 1
#define HAS_HSTX 1
// PICO_CONFIG: XOSC_HZ, The crystal oscillator frequency in Hz, type=int, default=12000000, advanced=true, group=hardware_base
// NOTE: The system and USB clocks are generated from the frequency using two PLLs.
// If you override this define, or SYS_CLK_HZ/USB_CLK_HZ below, you will *also* need to add your own adjusted PLL set-up defines to
// override the defaults which live in src/rp2_common/hardware_clocks/include/hardware/clocks.h
// Please see the comments there about calculating the new PLL setting values.
#ifndef XOSC_HZ
#ifdef XOSC_KHZ
#define XOSC_HZ ((XOSC_KHZ) * _u(1000))
#elif defined(XOSC_MHZ)
#define XOSC_HZ ((XOSC_MHZ) * _u(1000000))
#else
#define XOSC_HZ _u(12000000)
#endif
#endif
// PICO_CONFIG: SYS_CLK_HZ, The system operating frequency in Hz, type=int, default=150000000, advanced=true, group=hardware_base
#ifndef SYS_CLK_HZ
#ifdef SYS_CLK_KHZ
#define SYS_CLK_HZ ((SYS_CLK_KHZ) * _u(1000))
#elif defined(SYS_CLK_MHZ)
#define SYS_CLK_HZ ((SYS_CLK_MHZ) * _u(1000000))
#else
#define SYS_CLK_HZ _u(150000000)
#endif
#endif
// PICO_CONFIG: USB_CLK_HZ, USB clock frequency. Must be 48MHz for the USB interface to operate correctly, type=int, default=48000000, advanced=true, group=hardware_base
#ifndef USB_CLK_HZ
#ifdef USB_CLK_KHZ
#define USB_CLK_HZ ((USB_CLK_KHZ) * _u(1000))
#elif defined(USB_CLK_MHZ)
#define USB_CLK_HZ ((USB_CLK_MHZ) * _u(1000000))
#else
#define USB_CLK_HZ _u(48000000)
#endif
#endif
// For backwards compatibility define XOSC_KHZ if the frequency is indeed an integer number of Khz.
#if defined(XOSC_HZ) && !defined(XOSC_KHZ) && (XOSC_HZ % 1000 == 0)
#define XOSC_KHZ (XOSC_HZ / 1000)
#endif
// For backwards compatibility define XOSC_MHZ if the frequency is indeed an integer number of Mhz.
#if defined(XOSC_KHZ) && !defined(XOSC_MHZ) && (XOSC_KHZ % 1000 == 0)
#define XOSC_MHZ (XOSC_KHZ / 1000)
#endif
// For backwards compatibility define SYS_CLK_KHZ if the frequency is indeed an integer number of Khz.
#if defined(SYS_CLK_HZ) && !defined(SYS_CLK_KHZ) && (SYS_CLK_HZ % 1000 == 0)
#define SYS_CLK_KHZ (SYS_CLK_HZ / 1000)
#endif
// For backwards compatibility define SYS_CLK_MHZ if the frequency is indeed an integer number of Mhz.
#if defined(SYS_CLK_KHZ) && !defined(SYS_CLK_MHZ) && (SYS_CLK_KHZ % 1000 == 0)
#define SYS_CLK_MHZ (SYS_CLK_KHZ / 1000)
#endif
// For backwards compatibility define USB_CLK_KHZ if the frequency is indeed an integer number of Khz.
#if defined(USB_CLK_HZ) && !defined(USB_CLK_KHZ) && (USB_CLK_HZ % 1000 == 0)
#define USB_CLK_KHZ (USB_CLK_HZ / 1000)
#endif
// For backwards compatibility define USB_CLK_MHZ if the frequency is indeed an integer number of Mhz.
#if defined(USB_CLK_KHZ) && !defined(USB_CLK_MHZ) && (USB_CLK_KHZ % 1000 == 0)
#define USB_CLK_MHZ (USB_CLK_KHZ / 1000)
#endif
#define ACCESSCTRL_PASSWORD_BITS _u(0xacce0000)
#define POWMAN_PASSWORD_BITS _u(0x5afe0000)
#ifdef __riscv
// Note the soft-table dispatch code is between the hard and soft vector
// tables, as it's inlined into the last slot of the hard table:
#if defined(__riscv_c) || defined(__riscv_zca)
// RISC-V with compressed instructions: NOTE that this is dependent on the size of the code in crt0_riscv.S
#define VTABLE_FIRST_IRQ 0x34
#else
// RISC-V without compressed instructions:
#define VTABLE_FIRST_IRQ 0x48
#endif
#else
// Armv8-M:
#define VTABLE_FIRST_IRQ 16
#endif
#define FIRST_USER_IRQ (NUM_IRQS - NUM_USER_IRQS)
#endif

90
arch/arm/src/rp23xx/hardware/pll.h
View file

@ -1,90 +0,0 @@
/*
* Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _HARDWARE_PLL_H
#define _HARDWARE_PLL_H
#include "pico.h"
#include "hardware/structs/pll.h"
#ifdef __cplusplus
extern "C" {
#endif
/** \file hardware/pll.h
* \defgroup hardware_pll hardware_pll
*
* \brief Phase Locked Loop control APIs
*
* There are two PLLs in RP2040. They are:
* - pll_sys - Used to generate up to a 133MHz system clock
* - pll_usb - Used to generate a 48MHz USB reference clock
*
* For details on how the PLLs are calculated, please refer to the RP2040 datasheet.
*/
typedef pll_hw_t *PLL;
#define pll_sys pll_sys_hw
#define pll_usb pll_usb_hw
#ifndef PICO_PLL_VCO_MIN_FREQ_HZ
#ifdef PICO_PLL_VCO_MIN_FREQ_MHZ
#define PICO_PLL_VCO_MIN_FREQ_HZ (PICO_PLL_VCO_MIN_FREQ_MHZ * MHZ)
#elif defined(PICO_PLL_VCO_MIN_FREQ_KHZ)
#define PICO_PLL_VCO_MIN_FREQ_HZ (PICO_PLL_VCO_MIN_FREQ_KHZ * KHZ)
#else
#define PICO_PLL_VCO_MIN_FREQ_HZ (750 * MHZ)
#endif
#endif
#ifndef PICO_PLL_VCO_MAX_FREQ_HZ
#ifdef PICO_PLL_VCO_MAX_FREQ_MHZ
#define PICO_PLL_VCO_MAX_FREQ_HZ (PICO_PLL_VCO_MAX_FREQ_MHZ * MHZ)
#elif defined(PICO_PLL_VCO_MAX_FREQ_KHZ)
#define PICO_PLL_VCO_MAX_FREQ_HZ (PICO_PLL_VCO_MAX_FREQ_KHZ * KHZ)
#else
#define PICO_PLL_VCO_MAX_FREQ_HZ (1600 * MHZ)
#endif
#endif
/*! \brief Initialise specified PLL.
* \ingroup hardware_pll
* \param pll pll_sys or pll_usb
* \param ref_div Input clock divider.
* \param vco_freq Requested output from the VCO (voltage controlled oscillator)
* \param post_div1 Post Divider 1 - range 1-7. Must be >= post_div2
* \param post_div2 Post Divider 2 - range 1-7
*/
void pll_init(PLL pll, uint ref_div, uint vco_freq, uint post_div1, uint post_div2);
/*! \brief Release/uninitialise specified PLL.
* \ingroup hardware_pll
*
* This will turn off the power to the specified PLL. Note this function does not currently check if
* the PLL is in use before powering it off so should be used with care.
*
* \param pll pll_sys or pll_usb
*/
void pll_deinit(PLL pll);
/**
* \def PLL_RESET_NUM(pll)
* \ingroup hardware_pll
* \hideinitializer
* \brief Returns the \ref reset_num_t used to reset a given PLL instance
*
* Note this macro is intended to resolve at compile time, and does no parameter checking
*/
#ifndef PLL_RESET_NUM
#define PLL_RESET_NUM(pll) ((pll_usb_hw == (pll)) ? RESET_PLL_USB : RESET_PLL_SYS)
#endif
#ifdef __cplusplus
}
#endif
#endif

275
arch/arm/src/rp23xx/hardware/powman.h
View file

@ -1,275 +0,0 @@
/*
* Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _HARDWARE_POWMAN_H
#define _HARDWARE_POWMAN_H
#include "pico.h"
#include "hardware/structs/powman.h"
/** \file hardware/powman.h
* \defgroup hardware_powman hardware_powman
*
* \brief Power Management API
*
*/
// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_HARDWARE_POWMAN, Enable/disable hardware_powman assertions, type=bool, default=0, group=hardware_powman
#ifndef PARAM_ASSERTIONS_ENABLED_HARDWARE_POWMAN
#define PARAM_ASSERTIONS_ENABLED_HARDWARE_POWMAN 0
#endif
/*! \brief Use the ~32KHz low power oscillator as the powman timer source
* \ingroup hardware_powman
*/
void powman_timer_set_1khz_tick_source_lposc(void);
/*! \brief Use the low power oscillator (specifying frequency) as the powman timer source
* \ingroup hardware_powman
* \param lposc_freq_hz specify an exact lposc freq to trim it
*/
void powman_timer_set_1khz_tick_source_lposc_with_hz(uint32_t lposc_freq_hz);
/*! \brief Use the crystal oscillator as the powman timer source
* \ingroup hardware_powman
*/
void powman_timer_set_1khz_tick_source_xosc(void);
/*! \brief Use the crystal oscillator as the powman timer source
* \ingroup hardware_powman
* \param xosc_freq_hz specify a crystal frequency
*/
void powman_timer_set_1khz_tick_source_xosc_with_hz(uint32_t xosc_freq_hz);
/*! \brief Use a 1KHz external tick as the powman timer source
* \ingroup hardware_powman
* \param gpio the gpio to use. must be 12, 14, 20, 22
*/
void powman_timer_set_1khz_tick_source_gpio(uint32_t gpio);
/*! \brief Use a 1Hz external signal as the powman timer source for seconds only
* \ingroup hardware_powman
*
* Use a 1hz sync signal, such as from a gps for the seconds component of the timer.
* The milliseconds will still come from another configured source such as xosc or lposc
*
* \param gpio the gpio to use. must be 12, 14, 20, 22
*/
void powman_timer_enable_gpio_1hz_sync(uint32_t gpio);
/*! \brief Stop using 1Hz external signal as the powman timer source for seconds
* \ingroup hardware_powman
*/
void powman_timer_disable_gpio_1hz_sync(void);
/*! \brief Returns current time in ms
* \ingroup hardware_powman
*/
uint64_t powman_timer_get_ms(void);
/*! \brief Set current time in ms
* \ingroup hardware_powman
*
* \param time_ms Current time in ms
*/
void powman_timer_set_ms(uint64_t time_ms);
/*! \brief Set an alarm at an absolute time in ms
* \ingroup hardware_powman
*
* Note, the timer is stopped and then restarted as part of this function. This only controls the alarm
* if you want to use the alarm to wake up powman then you should use \ref powman_enable_alarm_wakeup_at_ms
*
* \param alarm_time_ms time at which the alarm will fire
*/
void powman_timer_enable_alarm_at_ms(uint64_t alarm_time_ms);
/*! \brief Disable the alarm
* \ingroup hardware_powman
*
* Once an alarm has fired it must be disabled to stop firing as the alarm
* comparison is alarm = alarm_time >= current_time
*/
void powman_timer_disable_alarm(void);
/*! \brief hw_set_bits helper function
* \ingroup hardware_powman
*
* \param reg register to set
* \param bits bits of register to set
* Powman needs a password for writes, to prevent accidentally writing to it.
* This function implements hw_set_bits with an appropriate password.
*/
static inline void powman_set_bits(volatile uint32_t *reg, uint32_t bits) {
invalid_params_if(HARDWARE_POWMAN, bits >> 16);
hw_set_bits(reg, POWMAN_PASSWORD_BITS | bits);
}
/*! \brief hw_clear_bits helper function
* \ingroup hardware_powman
*
* Powman needs a password for writes, to prevent accidentally writing to it.
* This function implements hw_clear_bits with an appropriate password.
*
* \param reg register to clear
* \param bits bits of register to clear
*/
static inline void powman_clear_bits(volatile uint32_t *reg, uint32_t bits) {
invalid_params_if(HARDWARE_POWMAN, bits >> 16);
hw_clear_bits(reg, POWMAN_PASSWORD_BITS | bits);
}
/*! \brief Determine if the powman timer is running
* \ingroup hardware_powman
*/
static inline bool powman_timer_is_running(void) {
return powman_hw->timer & POWMAN_TIMER_RUN_BITS;
}
/*! \brief Stop the powman timer
* \ingroup hardware_powman
*/
static inline void powman_timer_stop(void) {
powman_clear_bits(&powman_hw->timer, POWMAN_TIMER_RUN_BITS);
}
/*! \brief Start the powman timer
* \ingroup hardware_powman
*/
static inline void powman_timer_start(void) {
powman_set_bits(&powman_hw->timer, POWMAN_TIMER_RUN_BITS);
}
/*! \brief Clears the powman alarm
* \ingroup hardware_powman
*
* Note, the alarm must be disabled (see \ref powman_timer_disable_alarm) before clearing the alarm, as the alarm fires if
* the time is greater than equal to the target, so once the time has passed the alarm will always fire while enabled.
*/
static inline void powman_clear_alarm(void) {
powman_clear_bits(&powman_hw->timer, POWMAN_TIMER_ALARM_BITS);
}
/*! \brief Power domains of powman
* \ingroup hardware_powman
*/
enum powman_power_domains {
POWMAN_POWER_DOMAIN_SRAM_BANK1 = 0, ///< bank1 includes the top 256K of sram plus sram 8 and 9 (scratch x and scratch y)
POWMAN_POWER_DOMAIN_SRAM_BANK0 = 1, ///< bank0 is bottom 256K of sSRAM
POWMAN_POWER_DOMAIN_XIP_CACHE = 2, ///< XIP cache is 2x8K instances
POWMAN_POWER_DOMAIN_SWITCHED_CORE = 3, ///< Switched core logic (processors, busfabric, peris etc)
POWMAN_POWER_DOMAIN_COUNT = 4,
};
typedef uint32_t powman_power_state;
/*! \brief Get the current power state
* \ingroup hardware_powman
*/
powman_power_state powman_get_power_state(void);
/*! \brief Set the power state
* \ingroup hardware_powman
*
* Check the desired state is valid. Powman will go to the state if it is valid and there are no pending power up requests.
*
* Note that if you are turning off the switched core then this function will never return as the processor will have
* been turned off at the end.
*
* \param state the power state to go to
* \returns PICO_OK if the state is valid. Misc PICO_ERRORs are returned if not
*/
int powman_set_power_state(powman_power_state state);
#define POWMAN_POWER_STATE_NONE 0
/*! \brief Helper function modify a powman_power_state to turn a domain on
* \ingroup hardware_powman
* \param orig original state
* \param domain domain to turn on
*/
static inline powman_power_state powman_power_state_with_domain_on(powman_power_state orig, enum powman_power_domains domain) {
invalid_params_if(HARDWARE_POWMAN, domain >= POWMAN_POWER_DOMAIN_COUNT);
return orig | (1u << domain);
}
/*! \brief Helper function modify a powman_power_state to turn a domain off
* \ingroup hardware_powman
* \param orig original state
* \param domain domain to turn off
*/
static inline powman_power_state powman_power_state_with_domain_off(powman_power_state orig, enum powman_power_domains domain) {
invalid_params_if(HARDWARE_POWMAN, domain >= POWMAN_POWER_DOMAIN_COUNT);
return orig &= ~(1u << domain);
}
/*! \brief Helper function to check if a domain is on in a given powman_power_state
* \ingroup hardware_powman
* \param state powman_power_state
* \param domain domain to check is on
*/
static inline bool powman_power_state_is_domain_on(powman_power_state state, enum powman_power_domains domain) {
invalid_params_if(HARDWARE_POWMAN, domain >= POWMAN_POWER_DOMAIN_COUNT);
return state & (1u << domain);
}
/*! \brief Wake up from an alarm at a given time
* \ingroup hardware_powman
* \param alarm_time_ms time to wake up in ms
*/
void powman_enable_alarm_wakeup_at_ms(uint64_t alarm_time_ms);
/*! \brief Wake up from a gpio
* \ingroup hardware_powman
* \param gpio_wakeup_num hardware wakeup instance to use (0-3)
* \param gpio gpio to wake up from (0-47)
* \param edge true for edge sensitive, false for level sensitive
* \param high true for active high, false active low
*/
void powman_enable_gpio_wakeup(uint gpio_wakeup_num, uint32_t gpio, bool edge, bool high);
/*! \brief Disable waking up from alarm
* \ingroup hardware_powman
*/
void powman_disable_alarm_wakeup(void);
/*! \brief Disable wake up from a gpio
* \ingroup hardware_powman
* \param gpio_wakeup_num hardware wakeup instance to use (0-3)
*/
void powman_disable_gpio_wakeup(uint gpio_wakeup_num);
/*! \brief Disable all wakeup sources
* \ingroup hardware_powman
*/
void powman_disable_all_wakeups(void);
/*! \brief Configure sleep state and wakeup state
* \ingroup hardware_powman
* \param sleep_state power state powman will go to when sleeping, used to validate the wakeup state
* \param wakeup_state power state powman will go to when waking up. Note switched core and xip always power up. SRAM bank0 and bank1 can be left powered off
* \returns true if the state is valid, false if not
*/
bool powman_configure_wakeup_state(powman_power_state sleep_state, powman_power_state wakeup_state);
/*! \brief Ignore wake up when the debugger is attached
* \ingroup hardware_powman
*
* Typically, when a debugger is attached it will assert the pwrupreq signal. OpenOCD does not clear this signal, even when you quit.
* This means once you have attached a debugger powman will never go to sleep. This function lets you ignore the debugger
* pwrupreq which means you can go to sleep with a debugger attached. The debugger will error out if you go to turn off the switch core with it attached,
* as the processors have been powered off.
*
* \param ignored should the debugger power up request be ignored
*/
static inline void powman_set_debug_power_request_ignored(bool ignored) {
if (ignored)
powman_set_bits(&powman_hw->dbg_pwrcfg, 1);
else
powman_clear_bits(&powman_hw->dbg_pwrcfg, 0);
}
#endif

822
arch/arm/src/rp23xx/hardware/pwm.h
View file

@ -1,822 +0,0 @@
/*
* Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _HARDWARE_PWM_H
#define _HARDWARE_PWM_H
#include "pico.h"
#include "hardware/structs/pwm.h"
#include "hardware/regs/dreq.h"
#include "hardware/regs/intctrl.h"
#ifdef __cplusplus
extern "C" {
#endif
// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_HARDWARE_PWM, Enable/disable assertions in the hardware_pwm module, type=bool, default=0, group=hardware_pwm
#ifndef PARAM_ASSERTIONS_ENABLED_HARDWARE_PWM
#ifdef PARAM_ASSERTIONS_ENABLED_PWM // backwards compatibility with SDK < 2.0.0
#define PARAM_ASSERTIONS_ENABLED_HARDWARE_PWM PARAM_ASSERTIONS_ENABLED_PWM
#else
#define PARAM_ASSERTIONS_ENABLED_HARDWARE_PWM 0
#endif
#endif
/** \file hardware/pwm.h
* \defgroup hardware_pwm hardware_pwm
*
* \brief Hardware Pulse Width Modulation (PWM) API
*
* The RP2040 PWM block has 8 identical slices, the RP2350 has 12. Each slice can drive two PWM output signals, or
* measure the frequency or duty cycle of an input signal. This gives a total of up to 16/24 controllable
* PWM outputs. All 30 GPIOs can be driven by the PWM block.
*
* The PWM hardware functions by continuously comparing the input value to a free-running counter. This produces a
* toggling output where the amount of time spent at the high output level is proportional to the input value. The fraction of
* time spent at the high signal level is known as the duty cycle of the signal.
*
* The default behaviour of a PWM slice is to count upward until the wrap value (\ref pwm_config_set_wrap) is reached, and then
* immediately wrap to 0. PWM slices also offer a phase-correct mode, where the counter starts to count downward after
* reaching TOP, until it reaches 0 again.
*
* \subsection pwm_example Example
* \addtogroup hardware_pwm
* \include hello_pwm.c
*/
/** \brief PWM Divider mode settings
* \ingroup hardware_pwm
*
*/
enum pwm_clkdiv_mode
{
PWM_DIV_FREE_RUNNING = 0, ///< Free-running counting at rate dictated by fractional divider
PWM_DIV_B_HIGH = 1, ///< Fractional divider is gated by the PWM B pin
PWM_DIV_B_RISING = 2, ///< Fractional divider advances with each rising edge of the PWM B pin
PWM_DIV_B_FALLING = 3 ///< Fractional divider advances with each falling edge of the PWM B pin
};
enum pwm_chan
{
PWM_CHAN_A = 0,
PWM_CHAN_B = 1
};
typedef struct {
uint32_t csr;
uint32_t div;
uint32_t top;
} pwm_config;
/**
* \def PWM_DREQ_NUM(slice_num)
* \ingroup hardware_pwm
* \hideinitializer
* \brief Returns the \ref dreq_num_t used for pacing DMA transfers for a given PWM slice
*
* Note this macro is intended to resolve at compile time, and does no parameter checking
*/
#ifndef PWM_DREQ_NUM
static_assert(DREQ_PWM_WRAP1 == DREQ_PWM_WRAP0 + 1, "");
static_assert(DREQ_PWM_WRAP7 == DREQ_PWM_WRAP0 + 7, "");
#define PWM_DREQ_NUM(slice_num) (DREQ_PWM_WRAP0 + (slice_num))
#endif
/**
* \def PWM_GPIO_SLICE_NUM(gpio)
* \ingroup hardware_pwm
* \hideinitializer
* \brief Returns the PWM slice number for a given GPIO number
*/
#ifndef PWM_GPIO_SLICE_NUM
#define PWM_GPIO_SLICE_NUM(gpio) ({ \
uint slice_num; \
if ((gpio) < 32) { \
slice_num = ((gpio) >> 1u) & 7u; \
} else { \
slice_num = 8u + (((gpio) >> 1u) & 3u); \
} \
slice_num; \
})
#endif
static inline void check_slice_num_param(__unused uint slice_num) {
valid_params_if(HARDWARE_PWM, slice_num < NUM_PWM_SLICES);
}
/** \brief Determine the PWM slice that is attached to the specified GPIO
* \ingroup hardware_pwm
*
* \return The PWM slice number that controls the specified GPIO.
*/
static inline uint pwm_gpio_to_slice_num(uint gpio) {
valid_params_if(HARDWARE_PWM, gpio < NUM_BANK0_GPIOS);
return PWM_GPIO_SLICE_NUM(gpio);
}
/** \brief Determine the PWM channel that is attached to the specified GPIO.
* \ingroup hardware_pwm
*
* Each slice 0 to 7 has two channels, A and B.
*
* \return The PWM channel that controls the specified GPIO.
*/
static inline uint pwm_gpio_to_channel(uint gpio) {
valid_params_if(HARDWARE_PWM, gpio < NUM_BANK0_GPIOS);
return gpio & 1u;
}
/** \brief Set phase correction in a PWM configuration
* \ingroup hardware_pwm
*
* \param c PWM configuration struct to modify
* \param phase_correct true to set phase correct modulation, false to set trailing edge
*
* Setting phase control to true means that instead of wrapping back to zero when the wrap point is reached,
* the PWM starts counting back down. The output frequency is halved when phase-correct mode is enabled.
*/
static inline void pwm_config_set_phase_correct(pwm_config *c, bool phase_correct) {
c->csr = (c->csr & ~PWM_CH0_CSR_PH_CORRECT_BITS)
| (bool_to_bit(phase_correct) << PWM_CH0_CSR_PH_CORRECT_LSB);
}
/** \brief Set PWM clock divider in a PWM configuration
* \ingroup hardware_pwm
*
* \param c PWM configuration struct to modify
* \param div Value to divide counting rate by. Must be greater than or equal to 1.
*
* If the divide mode is free-running, the PWM counter runs at clk_sys / div.
* Otherwise, the divider reduces the rate of events seen on the B pin input (level or edge)
* before passing them on to the PWM counter.
*/
static inline void pwm_config_set_clkdiv(pwm_config *c, float div) {
valid_params_if(HARDWARE_PWM, div >= 1.f && div < 256.f);
c->div = (uint32_t)(div * (float)(1u << PWM_CH0_DIV_INT_LSB));
}
/** \brief Set PWM clock divider in a PWM configuration using an 8:4 fractional value
* \ingroup hardware_pwm
*
* \param c PWM configuration struct to modify
* \param integer 8 bit integer part of the clock divider. Must be greater than or equal to 1.
* \param fract 4 bit fractional part of the clock divider
*
* If the divide mode is free-running, the PWM counter runs at clk_sys / div.
* Otherwise, the divider reduces the rate of events seen on the B pin input (level or edge)
* before passing them on to the PWM counter.
*/
static inline void pwm_config_set_clkdiv_int_frac(pwm_config *c, uint8_t integer, uint8_t fract) {
valid_params_if(HARDWARE_PWM, integer >= 1);
valid_params_if(HARDWARE_PWM, fract < 16);
c->div = (((uint)integer) << PWM_CH0_DIV_INT_LSB) | (((uint)fract) << PWM_CH0_DIV_FRAC_LSB);
}
/** \brief Set PWM clock divider in a PWM configuration
* \ingroup hardware_pwm
*
* \param c PWM configuration struct to modify
* \param div Integer value to reduce counting rate by. Must be greater than or equal to 1.
*
* If the divide mode is free-running, the PWM counter runs at clk_sys / div.
* Otherwise, the divider reduces the rate of events seen on the B pin input (level or edge)
* before passing them on to the PWM counter.
*/
static inline void pwm_config_set_clkdiv_int(pwm_config *c, uint div) {
valid_params_if(HARDWARE_PWM, div >= 1 && div < 256);
pwm_config_set_clkdiv_int_frac(c, (uint8_t)div, 0);
}
/** \brief Set PWM counting mode in a PWM configuration
* \ingroup hardware_pwm
*
* \param c PWM configuration struct to modify
* \param mode PWM divide/count mode
*
* Configure which event gates the operation of the fractional divider.
* The default is always-on (free-running PWM). Can also be configured to count on
* high level, rising edge or falling edge of the B pin input.
*/
static inline void pwm_config_set_clkdiv_mode(pwm_config *c, enum pwm_clkdiv_mode mode) {
valid_params_if(HARDWARE_PWM, mode == PWM_DIV_FREE_RUNNING ||
mode == PWM_DIV_B_RISING ||
mode == PWM_DIV_B_HIGH ||
mode == PWM_DIV_B_FALLING);
c->csr = (c->csr & ~PWM_CH0_CSR_DIVMODE_BITS)
| (((uint)mode) << PWM_CH0_CSR_DIVMODE_LSB);
}
/** \brief Set output polarity in a PWM configuration
* \ingroup hardware_pwm
*
* \param c PWM configuration struct to modify
* \param a true to invert output A
* \param b true to invert output B
*/
static inline void pwm_config_set_output_polarity(pwm_config *c, bool a, bool b) {
c->csr = (c->csr & ~(PWM_CH0_CSR_A_INV_BITS | PWM_CH0_CSR_B_INV_BITS))
| ((bool_to_bit(a) << PWM_CH0_CSR_A_INV_LSB) | (bool_to_bit(b) << PWM_CH0_CSR_B_INV_LSB));
}
/** \brief Set PWM counter wrap value in a PWM configuration
* \ingroup hardware_pwm
*
* Set the highest value the counter will reach before returning to 0. Also known as TOP.
*
* \param c PWM configuration struct to modify
* \param wrap Value to set wrap to
*/
static inline void pwm_config_set_wrap(pwm_config *c, uint16_t wrap) {
c->top = wrap;
}
/** \brief Initialise a PWM with settings from a configuration object
* \ingroup hardware_pwm
*
* Use the \ref pwm_get_default_config() function to initialise a config structure, make changes as
* needed using the pwm_config_* functions, then call this function to set up the PWM.
*
* \param slice_num PWM slice number
* \param c The configuration to use
* \param start If true the PWM will be started running once configured. If false you will need to start
* manually using \ref pwm_set_enabled() or \ref pwm_set_mask_enabled()
*/
static inline void pwm_init(uint slice_num, pwm_config *c, bool start) {
check_slice_num_param(slice_num);
pwm_hw->slice[slice_num].csr = 0;
pwm_hw->slice[slice_num].ctr = PWM_CH0_CTR_RESET;
pwm_hw->slice[slice_num].cc = PWM_CH0_CC_RESET;
pwm_hw->slice[slice_num].top = c->top;
pwm_hw->slice[slice_num].div = c->div;
pwm_hw->slice[slice_num].csr = c->csr | (bool_to_bit(start) << PWM_CH0_CSR_EN_LSB);
}
/** \brief Get a set of default values for PWM configuration
* \ingroup hardware_pwm
*
* PWM config is free-running at system clock speed, no phase correction, wrapping at 0xffff,
* with standard polarities for channels A and B.
*
* \return Set of default values.
*/
static inline pwm_config pwm_get_default_config(void) {
pwm_config c = {0, 0, 0};
pwm_config_set_phase_correct(&c, false);
pwm_config_set_clkdiv_int(&c, 1);
pwm_config_set_clkdiv_mode(&c, PWM_DIV_FREE_RUNNING);
pwm_config_set_output_polarity(&c, false, false);
pwm_config_set_wrap(&c, 0xffffu);
return c;
}
/** \brief Set the current PWM counter wrap value
* \ingroup hardware_pwm
*
* Set the highest value the counter will reach before returning to 0. Also
* known as TOP.
*
* The counter wrap value is double-buffered in hardware. This means that,
* when the PWM is running, a write to the counter wrap value does not take
* effect until after the next time the PWM slice wraps (or, in phase-correct
* mode, the next time the slice reaches 0). If the PWM is not running, the
* write is latched in immediately.
*
* \param slice_num PWM slice number
* \param wrap Value to set wrap to
*/
static inline void pwm_set_wrap(uint slice_num, uint16_t wrap) {
check_slice_num_param(slice_num);
pwm_hw->slice[slice_num].top = wrap;
}
/** \brief Set the current PWM counter compare value for one channel
* \ingroup hardware_pwm
*
* Set the value of the PWM counter compare value, for either channel A or channel B.
*
* The counter compare register is double-buffered in hardware. This means
* that, when the PWM is running, a write to the counter compare values does
* not take effect until the next time the PWM slice wraps (or, in
* phase-correct mode, the next time the slice reaches 0). If the PWM is not
* running, the write is latched in immediately.
*
* \param slice_num PWM slice number
* \param chan Which channel to update. 0 for A, 1 for B.
* \param level new level for the selected output
*/
static inline void pwm_set_chan_level(uint slice_num, uint chan, uint16_t level) {
check_slice_num_param(slice_num);
hw_write_masked(
&pwm_hw->slice[slice_num].cc,
((uint)level) << (chan ? PWM_CH0_CC_B_LSB : PWM_CH0_CC_A_LSB),
chan ? PWM_CH0_CC_B_BITS : PWM_CH0_CC_A_BITS
);
}
/** \brief Set PWM counter compare values
* \ingroup hardware_pwm
*
* Set the value of the PWM counter compare values, A and B.
*
* The counter compare register is double-buffered in hardware. This means
* that, when the PWM is running, a write to the counter compare values does
* not take effect until the next time the PWM slice wraps (or, in
* phase-correct mode, the next time the slice reaches 0). If the PWM is not
* running, the write is latched in immediately.
*
* \param slice_num PWM slice number
* \param level_a Value to set compare A to. When the counter reaches this value the A output is deasserted
* \param level_b Value to set compare B to. When the counter reaches this value the B output is deasserted
*/
static inline void pwm_set_both_levels(uint slice_num, uint16_t level_a, uint16_t level_b) {
check_slice_num_param(slice_num);
pwm_hw->slice[slice_num].cc = (((uint)level_b) << PWM_CH0_CC_B_LSB) | (((uint)level_a) << PWM_CH0_CC_A_LSB);
}
/** \brief Helper function to set the PWM level for the slice and channel associated with a GPIO.
* \ingroup hardware_pwm
*
* Look up the correct slice (0 to 7) and channel (A or B) for a given GPIO, and update the corresponding
* counter compare field.
*
* This PWM slice should already have been configured and set running. Also be careful of multiple GPIOs
* mapping to the same slice and channel (if GPIOs have a difference of 16).
*
* The counter compare register is double-buffered in hardware. This means
* that, when the PWM is running, a write to the counter compare values does
* not take effect until the next time the PWM slice wraps (or, in
* phase-correct mode, the next time the slice reaches 0). If the PWM is not
* running, the write is latched in immediately.
*
* \param gpio GPIO to set level of
* \param level PWM level for this GPIO
*/
static inline void pwm_set_gpio_level(uint gpio, uint16_t level) {
valid_params_if(HARDWARE_PWM, gpio < NUM_BANK0_GPIOS);
pwm_set_chan_level(pwm_gpio_to_slice_num(gpio), pwm_gpio_to_channel(gpio), level);
}
/** \brief Get PWM counter
* \ingroup hardware_pwm
*
* Get current value of PWM counter
*
* \param slice_num PWM slice number
* \return Current value of the PWM counter
*/
static inline uint16_t pwm_get_counter(uint slice_num) {
check_slice_num_param(slice_num);
return (uint16_t)(pwm_hw->slice[slice_num].ctr);
}
/** \brief Set PWM counter
* \ingroup hardware_pwm
*
* Set the value of the PWM counter
*
* \param slice_num PWM slice number
* \param c Value to set the PWM counter to
*
*/
static inline void pwm_set_counter(uint slice_num, uint16_t c) {
check_slice_num_param(slice_num);
pwm_hw->slice[slice_num].ctr = c;
}
/** \brief Advance PWM count
* \ingroup hardware_pwm
*
* Advance the phase of a running the counter by 1 count.
*
* This function will return once the increment is complete.
*
* \param slice_num PWM slice number
*/
static inline void pwm_advance_count(uint slice_num) {
check_slice_num_param(slice_num);
hw_set_bits(&pwm_hw->slice[slice_num].csr, PWM_CH0_CSR_PH_ADV_BITS);
while (pwm_hw->slice[slice_num].csr & PWM_CH0_CSR_PH_ADV_BITS) {
tight_loop_contents();
}
}
/** \brief Retard PWM count
* \ingroup hardware_pwm
*
* Retard the phase of a running counter by 1 count
*
* This function will return once the retardation is complete.
*
* \param slice_num PWM slice number
*/
static inline void pwm_retard_count(uint slice_num) {
check_slice_num_param(slice_num);
hw_set_bits(&pwm_hw->slice[slice_num].csr, PWM_CH0_CSR_PH_RET_BITS);
while (pwm_hw->slice[slice_num].csr & PWM_CH0_CSR_PH_RET_BITS) {
tight_loop_contents();
}
}
/** \brief Set PWM clock divider using an 8:4 fractional value
* \ingroup hardware_pwm
*
* Set the clock divider. Counter increment will be on sysclock divided by this value, taking into account the gating.
*
* \param slice_num PWM slice number
* \param integer 8 bit integer part of the clock divider
* \param fract 4 bit fractional part of the clock divider
*/
static inline void pwm_set_clkdiv_int_frac(uint slice_num, uint8_t integer, uint8_t fract) {
check_slice_num_param(slice_num);
valid_params_if(HARDWARE_PWM, integer >= 1);
valid_params_if(HARDWARE_PWM, fract < 16);
pwm_hw->slice[slice_num].div = (((uint)integer) << PWM_CH0_DIV_INT_LSB) | (((uint)fract) << PWM_CH0_DIV_FRAC_LSB);
}
/** \brief Set PWM clock divider
* \ingroup hardware_pwm
*
* Set the clock divider. Counter increment will be on sysclock divided by this value, taking into account the gating.
*
* \param slice_num PWM slice number
* \param divider Floating point clock divider, 1.f <= value < 256.f
*/
static inline void pwm_set_clkdiv(uint slice_num, float divider) {
check_slice_num_param(slice_num);
valid_params_if(HARDWARE_PWM, divider >= 1.f && divider < 256.f);
uint8_t i = (uint8_t)divider;
uint8_t f = (uint8_t)((divider - i) * (0x01 << 4));
pwm_set_clkdiv_int_frac(slice_num, i, f);
}
/** \brief Set PWM output polarity
* \ingroup hardware_pwm
*
* \param slice_num PWM slice number
* \param a true to invert output A
* \param b true to invert output B
*/
static inline void pwm_set_output_polarity(uint slice_num, bool a, bool b) {
check_slice_num_param(slice_num);
hw_write_masked(&pwm_hw->slice[slice_num].csr, bool_to_bit(a) << PWM_CH0_CSR_A_INV_LSB | bool_to_bit(b) << PWM_CH0_CSR_B_INV_LSB,
PWM_CH0_CSR_A_INV_BITS | PWM_CH0_CSR_B_INV_BITS);
}
/** \brief Set PWM divider mode
* \ingroup hardware_pwm
*
* \param slice_num PWM slice number
* \param mode Required divider mode
*/
static inline void pwm_set_clkdiv_mode(uint slice_num, enum pwm_clkdiv_mode mode) {
check_slice_num_param(slice_num);
valid_params_if(HARDWARE_PWM, mode == PWM_DIV_FREE_RUNNING ||
mode == PWM_DIV_B_RISING ||
mode == PWM_DIV_B_HIGH ||
mode == PWM_DIV_B_FALLING);
hw_write_masked(&pwm_hw->slice[slice_num].csr, ((uint)mode) << PWM_CH0_CSR_DIVMODE_LSB, PWM_CH0_CSR_DIVMODE_BITS);
}
/** \brief Set PWM phase correct on/off
* \ingroup hardware_pwm
*
* \param slice_num PWM slice number
* \param phase_correct true to set phase correct modulation, false to set trailing edge
*
* Setting phase control to true means that instead of wrapping back to zero when the wrap point is reached,
* the PWM starts counting back down. The output frequency is halved when phase-correct mode is enabled.
*/
static inline void pwm_set_phase_correct(uint slice_num, bool phase_correct) {
check_slice_num_param(slice_num);
hw_write_masked(&pwm_hw->slice[slice_num].csr, bool_to_bit(phase_correct) << PWM_CH0_CSR_PH_CORRECT_LSB, PWM_CH0_CSR_PH_CORRECT_BITS);
}
/** \brief Enable/Disable PWM
* \ingroup hardware_pwm
*
* When a PWM is disabled, it halts its counter, and the output pins are left
* high or low depending on exactly when the counter is halted. When
* re-enabled the PWM resumes immediately from where it left off.
*
* If the PWM's output pins need to be low when halted:
*
* - The counter compare can be set to zero whilst the PWM is enabled, and
* then the PWM disabled once both pins are seen to be low
*
* - The GPIO output overrides can be used to force the actual pins low
*
* - The PWM can be run for one cycle (i.e. enabled then immediately disabled)
* with a TOP of 0, count of 0 and counter compare of 0, to force the pins
* low when the PWM has already been halted. The same method can be used
* with a counter compare value of 1 to force a pin high.
*
* Note that, when disabled, the PWM can still be advanced one count at a time
* by pulsing the PH_ADV bit in its CSR. The output pins transition as though
* the PWM were enabled.
*
* \param slice_num PWM slice number
* \param enabled true to enable the specified PWM, false to disable.
*/
static inline void pwm_set_enabled(uint slice_num, bool enabled) {
check_slice_num_param(slice_num);
hw_write_masked(&pwm_hw->slice[slice_num].csr, bool_to_bit(enabled) << PWM_CH0_CSR_EN_LSB, PWM_CH0_CSR_EN_BITS);
}
/** \brief Enable/Disable multiple PWM slices simultaneously
* \ingroup hardware_pwm
*
* \param mask Bitmap of PWMs to enable/disable. Bits 0 to 7 enable slices 0-7 respectively
*/
static inline void pwm_set_mask_enabled(uint32_t mask) {
pwm_hw->en = mask;
}
/**
* \def PWM_DEFAULT_IRQ_NUM()
* \ingroup hardware_pwm
* \hideinitializer
* \brief Returns the \ref irq_num_t for the default PWM IRQ.
*
* \if rp2040_specific
* On RP2040, there is only one PWM irq: PWM_IRQ_WRAP
* \endif
*
* \if rp2350_specific
* On RP2350 this returns to PWM_IRQ_WRAP0
* \endif
*
* Note this macro is intended to resolve at compile time, and does no parameter checking
*/
#ifndef PWM_DEFAULT_IRQ_NUM
#if PICO_RP2040
#define PWM_DEFAULT_IRQ_NUM() PWM_IRQ_WRAP
#else
#define PWM_DEFAULT_IRQ_NUM() PWM_IRQ_WRAP_0
// backwards compatibility with RP2040
#define PWM_IRQ_WRAP PWM_IRQ_WRAP_0
#define isr_pwm_wrap isr_pwm_wrap_0
#endif
#endif
/*! \brief Enable PWM instance interrupt via the default PWM IRQ (PWM_IRQ_WRAP_0 on RP2350)
* \ingroup hardware_pwm
*
* Used to enable a single PWM instance interrupt.
*
* Note there is only one PWM_IRQ_WRAP on RP2040.
*
* \param slice_num PWM block to enable/disable
* \param enabled true to enable, false to disable
*/
static inline void pwm_set_irq_enabled(uint slice_num, bool enabled) {
check_slice_num_param(slice_num);
if (enabled) {
hw_set_bits(&pwm_hw->inte, 1u << slice_num);
} else {
hw_clear_bits(&pwm_hw->inte, 1u << slice_num);
}
}
/*! \brief Enable PWM instance interrupt via PWM_IRQ_WRAP_0
* \ingroup hardware_pwm
*
* Used to enable a single PWM instance interrupt.
*
* \param slice_num PWM block to enable/disable
* \param enabled true to enable, false to disable
*/
static inline void pwm_set_irq0_enabled(uint slice_num, bool enabled) {
// irq0 always corresponds to the default IRQ
pwm_set_irq_enabled(slice_num, enabled);
}
#if NUM_PWM_IRQS > 1
/*! \brief Enable PWM instance interrupt via PWM_IRQ_WRAP_1
* \ingroup hardware_pwm
*
* Used to enable a single PWM instance interrupt.
*
* \param slice_num PWM block to enable/disable
* \param enabled true to enable, false to disable
*/
static inline void pwm_set_irq1_enabled(uint slice_num, bool enabled) {
check_slice_num_param(slice_num);
if (enabled) {
hw_set_bits(&pwm_hw->inte1, 1u << slice_num);
} else {
hw_clear_bits(&pwm_hw->inte1, 1u << slice_num);
}
}
#endif
/*! \brief Enable PWM instance interrupt via either PWM_IRQ_WRAP_0 or PWM_IRQ_WRAP_1
* \ingroup hardware_pwm
*
* Used to enable a single PWM instance interrupt.
*
* Note there is only one PWM_IRQ_WRAP on RP2040.
*
* \param irq_index the IRQ index; either 0 or 1 for PWM_IRQ_WRAP_0 or PWM_IRQ_WRAP_1
* \param slice_num PWM block to enable/disable
* \param enabled true to enable, false to disable
*/
static inline void pwm_irqn_set_slice_enabled(uint irq_index, uint slice_num, bool enabled) {
check_slice_num_param(slice_num);
invalid_params_if(HARDWARE_PWM, irq_index >= NUM_PWM_IRQS);
check_slice_num_param(slice_num);
if (enabled) {
hw_set_bits(&pwm_hw->irq_ctrl[irq_index].inte, 1u << slice_num);
} else {
hw_clear_bits(&pwm_hw->irq_ctrl[irq_index].inte, 1u << slice_num);
}
}
/*! \brief Enable multiple PWM instance interrupts via the default PWM IRQ (PWM_IRQ_WRAP_0 on RP2350)
* \ingroup hardware_pwm
*
* Use this to enable multiple PWM interrupts at once.
*
* Note there is only one PWM_IRQ_WRAP on RP2040.
*
* \param slice_mask Bitmask of all the blocks to enable/disable. Channel 0 = bit 0, channel 1 = bit 1 etc.
* \param enabled true to enable, false to disable
*/
static inline void pwm_set_irq_mask_enabled(uint32_t slice_mask, bool enabled) {
valid_params_if(HARDWARE_PWM, slice_mask < 256);
#if PICO_RP2040
if (enabled) {
hw_set_bits(&pwm_hw->inte, slice_mask);
} else {
hw_clear_bits(&pwm_hw->inte, slice_mask);
}
#else
static_assert(PWM_IRQ_WRAP_1 == PWM_IRQ_WRAP_0 + 1);
uint irq_index = PWM_DEFAULT_IRQ_NUM() - PWM_IRQ_WRAP_0;
if (enabled) {
hw_set_bits(&pwm_hw->irq_ctrl[irq_index].inte, slice_mask);
} else {
hw_clear_bits(&pwm_hw->irq_ctrl[irq_index].inte, slice_mask);
}
#endif
}
/*! \brief Enable multiple PWM instance interrupts via PWM_IRQ_WRAP_0
* \ingroup hardware_pwm
*
* Use this to enable multiple PWM interrupts at once.
*
* \param slice_mask Bitmask of all the blocks to enable/disable. Channel 0 = bit 0, channel 1 = bit 1 etc.
* \param enabled true to enable, false to disable
*/
static inline void pwm_set_irq0_mask_enabled(uint32_t slice_mask, bool enabled) {
// default irq is irq0
pwm_set_irq_mask_enabled(slice_mask, enabled);
}
#if NUM_PWM_IRQS > 1
/*! \brief Enable multiple PWM instance interrupts via PWM_IRQ_WRAP_1
* \ingroup hardware_pwm
*
* Use this to enable multiple PWM interrupts at once.
*
* \param slice_mask Bitmask of all the blocks to enable/disable. Channel 0 = bit 0, channel 1 = bit 1 etc.
* \param enabled true to enable, false to disable
*/
static inline void pwm_set_irq1_mask_enabled(uint32_t slice_mask, bool enabled) {
if (enabled) {
hw_set_bits(&pwm_hw->inte1, slice_mask);
} else {
hw_clear_bits(&pwm_hw->inte1, slice_mask);
}
}
#endif
/*! \brief Enable PWM instance interrupts via either PWM_IRQ_WRAP_0 or PWM_IRQ_WRAP_1
* \ingroup hardware_pwm
*
* Used to enable a single PWM instance interrupt.
*
* Note there is only one PWM_IRQ_WRAP on RP2040.
*
* \param irq_index the IRQ index; either 0 or 1 for PWM_IRQ_WRAP_0 or PWM_IRQ_WRAP_1
* \param slice_mask Bitmask of all the blocks to enable/disable. Channel 0 = bit 0, channel 1 = bit 1 etc.
* \param enabled true to enable, false to disable
*/
static inline void pwm_irqn_set_slice_mask_enabled(uint irq_index, uint slice_mask, bool enabled) {
invalid_params_if(HARDWARE_PWM, irq_index >= NUM_PWM_IRQS);
if (enabled) {
hw_set_bits(&pwm_hw->irq_ctrl[irq_index].inte, slice_mask);
} else {
hw_clear_bits(&pwm_hw->irq_ctrl[irq_index].inte, slice_mask);
}
}
/*! \brief Clear a single PWM channel interrupt
* \ingroup hardware_pwm
*
* \param slice_num PWM slice number
*/
static inline void pwm_clear_irq(uint slice_num) {
pwm_hw->intr = 1u << slice_num;
}
/*! \brief Get PWM interrupt status, raw for the default PWM IRQ (PWM_IRQ_WRAP_0 on RP2350)
* \ingroup hardware_pwm
*
* \return Bitmask of all PWM interrupts currently set
*/
static inline uint32_t pwm_get_irq_status_mask(void) {
return pwm_hw->ints;
}
/*! \brief Get PWM interrupt status, raw for the PWM_IRQ_WRAP_0
* \ingroup hardware_pwm
*
* \return Bitmask of all PWM interrupts currently set
*/
static inline uint32_t pwm_get_irq0_status_mask(void) {
return pwm_get_irq_status_mask();
}
#if NUM_PWM_IRQS > 1
/*! \brief Get PWM interrupt status, raw for the PWM_IRQ_WRAP_1
* \ingroup hardware_pwm
*
* \return Bitmask of all PWM interrupts currently set
*/
static inline uint32_t pwm_get_irq1_status_mask(void) {
return pwm_hw->ints1;
}
#endif
/*! \brief Get PWM interrupt status, raw for either PWM_IRQ_WRAP_0 or PWM_IRQ_WRAP_1
* \ingroup hardware_pwm
*
* \param irq_index the IRQ index; either 0 or 1 for PWM_IRQ_WRAP_0 or PWM_IRQ_WRAP_1
* \return Bitmask of all PWM interrupts currently set
*/
static inline uint32_t pwm_irqn_get_status_mask(uint irq_index) {
invalid_params_if(HARDWARE_PWM, irq_index >= NUM_DMA_IRQS);
return pwm_hw->irq_ctrl[irq_index].ints;
}
/*! \brief Force PWM interrupt for the default PWM IRQ (PWM_IRQ_WRAP_0 on RP2350)
* \ingroup hardware_pwm
*
* \param slice_num PWM slice number
*/
static inline void pwm_force_irq(uint slice_num) {
pwm_hw->intf = 1u << slice_num;
}
/*! \brief Force PWM interrupt via PWM_IRQ_WRAP_0
* \ingroup hardware_pwm
*
* \param slice_num PWM slice number
*/
static inline void pwm_force_irq0(uint slice_num) {
pwm_force_irq(slice_num);
}
#if NUM_PWM_IRQS > 1
/*! \brief Force PWM interrupt via PWM_IRQ_WRAP_0
* \ingroup hardware_pwm
*
* \param slice_num PWM slice number
*/
static inline void pwm_force_irq1(uint slice_num) {
pwm_hw->intf1 = 1u << slice_num;
}
#endif
/*! \brief Force PWM interrupt via PWM_IRQ_WRAP_0 or PWM_IRQ_WRAP_1
* \ingroup hardware_pwm
*
* \param irq_index the IRQ index; either 0 or 1 for PWM_IRQ_WRAP_0 or PWM_IRQ_WRAP_1
* \param slice_num PWM slice number
*/
static inline void pwm_irqn_force(uint irq_index, uint slice_num) {
invalid_params_if(HARDWARE_PWM, irq_index >= NUM_PWM_IRQS);
pwm_hw->irq_ctrl[irq_index].intf = 1u << slice_num;
}
/*! \brief Return the DREQ to use for pacing transfers to a particular PWM slice
* \ingroup hardware_pwm
*
* \param slice_num PWM slice number
*/
static inline uint pwm_get_dreq(uint slice_num) {
check_slice_num_param(slice_num);
return PWM_DREQ_NUM(slice_num);
}
#ifdef __cplusplus
}
#endif
#endif

1005
arch/arm/src/rp23xx/hardware/rcp.h
View file

File diff suppressed because it is too large Load diff

4953
arch/arm/src/rp23xx/hardware/regs/accessctrl.h
View file

File diff suppressed because it is too large Load diff

316
arch/arm/src/rp23xx/hardware/regs/adc.h
View file

@ -1,316 +0,0 @@
// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
// =============================================================================
// Register block : ADC
// Version : 2
// Bus type : apb
// Description : Control and data interface to SAR ADC
// =============================================================================
#ifndef _HARDWARE_REGS_ADC_H
#define _HARDWARE_REGS_ADC_H
// =============================================================================
// Register : ADC_CS
// Description : ADC Control and Status
#define ADC_CS_OFFSET _u(0x00000000)
#define ADC_CS_BITS _u(0x01fff70f)
#define ADC_CS_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : ADC_CS_RROBIN
// Description : Round-robin sampling. 1 bit per channel. Set all bits to 0 to
// disable.
// Otherwise, the ADC will cycle through each enabled channel in a
// round-robin fashion.
// The first channel to be sampled will be the one currently
// indicated by AINSEL.
// AINSEL will be updated after each conversion with the newly-
// selected channel.
#define ADC_CS_RROBIN_RESET _u(0x000)
#define ADC_CS_RROBIN_BITS _u(0x01ff0000)
#define ADC_CS_RROBIN_MSB _u(24)
#define ADC_CS_RROBIN_LSB _u(16)
#define ADC_CS_RROBIN_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : ADC_CS_AINSEL
// Description : Select analog mux input. Updated automatically in round-robin
// mode.
// This is corrected for the package option so only ADC channels
// which are bonded are available, and in the correct order
#define ADC_CS_AINSEL_RESET _u(0x0)
#define ADC_CS_AINSEL_BITS _u(0x0000f000)
#define ADC_CS_AINSEL_MSB _u(15)
#define ADC_CS_AINSEL_LSB _u(12)
#define ADC_CS_AINSEL_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : ADC_CS_ERR_STICKY
// Description : Some past ADC conversion encountered an error. Write 1 to
// clear.
#define ADC_CS_ERR_STICKY_RESET _u(0x0)
#define ADC_CS_ERR_STICKY_BITS _u(0x00000400)
#define ADC_CS_ERR_STICKY_MSB _u(10)
#define ADC_CS_ERR_STICKY_LSB _u(10)
#define ADC_CS_ERR_STICKY_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : ADC_CS_ERR
// Description : The most recent ADC conversion encountered an error; result is
// undefined or noisy.
#define ADC_CS_ERR_RESET _u(0x0)
#define ADC_CS_ERR_BITS _u(0x00000200)
#define ADC_CS_ERR_MSB _u(9)
#define ADC_CS_ERR_LSB _u(9)
#define ADC_CS_ERR_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : ADC_CS_READY
// Description : 1 if the ADC is ready to start a new conversion. Implies any
// previous conversion has completed.
// 0 whilst conversion in progress.
#define ADC_CS_READY_RESET _u(0x0)
#define ADC_CS_READY_BITS _u(0x00000100)
#define ADC_CS_READY_MSB _u(8)
#define ADC_CS_READY_LSB _u(8)
#define ADC_CS_READY_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : ADC_CS_START_MANY
// Description : Continuously perform conversions whilst this bit is 1. A new
// conversion will start immediately after the previous finishes.
#define ADC_CS_START_MANY_RESET _u(0x0)
#define ADC_CS_START_MANY_BITS _u(0x00000008)
#define ADC_CS_START_MANY_MSB _u(3)
#define ADC_CS_START_MANY_LSB _u(3)
#define ADC_CS_START_MANY_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : ADC_CS_START_ONCE
// Description : Start a single conversion. Self-clearing. Ignored if start_many
// is asserted.
#define ADC_CS_START_ONCE_RESET _u(0x0)
#define ADC_CS_START_ONCE_BITS _u(0x00000004)
#define ADC_CS_START_ONCE_MSB _u(2)
#define ADC_CS_START_ONCE_LSB _u(2)
#define ADC_CS_START_ONCE_ACCESS "SC"
// -----------------------------------------------------------------------------
// Field : ADC_CS_TS_EN
// Description : Power on temperature sensor. 1 - enabled. 0 - disabled.
#define ADC_CS_TS_EN_RESET _u(0x0)
#define ADC_CS_TS_EN_BITS _u(0x00000002)
#define ADC_CS_TS_EN_MSB _u(1)
#define ADC_CS_TS_EN_LSB _u(1)
#define ADC_CS_TS_EN_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : ADC_CS_EN
// Description : Power on ADC and enable its clock.
// 1 - enabled. 0 - disabled.
#define ADC_CS_EN_RESET _u(0x0)
#define ADC_CS_EN_BITS _u(0x00000001)
#define ADC_CS_EN_MSB _u(0)
#define ADC_CS_EN_LSB _u(0)
#define ADC_CS_EN_ACCESS "RW"
// =============================================================================
// Register : ADC_RESULT
// Description : Result of most recent ADC conversion
#define ADC_RESULT_OFFSET _u(0x00000004)
#define ADC_RESULT_BITS _u(0x00000fff)
#define ADC_RESULT_RESET _u(0x00000000)
#define ADC_RESULT_MSB _u(11)
#define ADC_RESULT_LSB _u(0)
#define ADC_RESULT_ACCESS "RO"
// =============================================================================
// Register : ADC_FCS
// Description : FIFO control and status
#define ADC_FCS_OFFSET _u(0x00000008)
#define ADC_FCS_BITS _u(0x0f0f0f0f)
#define ADC_FCS_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : ADC_FCS_THRESH
// Description : DREQ/IRQ asserted when level >= threshold
#define ADC_FCS_THRESH_RESET _u(0x0)
#define ADC_FCS_THRESH_BITS _u(0x0f000000)
#define ADC_FCS_THRESH_MSB _u(27)
#define ADC_FCS_THRESH_LSB _u(24)
#define ADC_FCS_THRESH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : ADC_FCS_LEVEL
// Description : The number of conversion results currently waiting in the FIFO
#define ADC_FCS_LEVEL_RESET _u(0x0)
#define ADC_FCS_LEVEL_BITS _u(0x000f0000)
#define ADC_FCS_LEVEL_MSB _u(19)
#define ADC_FCS_LEVEL_LSB _u(16)
#define ADC_FCS_LEVEL_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : ADC_FCS_OVER
// Description : 1 if the FIFO has been overflowed. Write 1 to clear.
#define ADC_FCS_OVER_RESET _u(0x0)
#define ADC_FCS_OVER_BITS _u(0x00000800)
#define ADC_FCS_OVER_MSB _u(11)
#define ADC_FCS_OVER_LSB _u(11)
#define ADC_FCS_OVER_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : ADC_FCS_UNDER
// Description : 1 if the FIFO has been underflowed. Write 1 to clear.
#define ADC_FCS_UNDER_RESET _u(0x0)
#define ADC_FCS_UNDER_BITS _u(0x00000400)
#define ADC_FCS_UNDER_MSB _u(10)
#define ADC_FCS_UNDER_LSB _u(10)
#define ADC_FCS_UNDER_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : ADC_FCS_FULL
#define ADC_FCS_FULL_RESET _u(0x0)
#define ADC_FCS_FULL_BITS _u(0x00000200)
#define ADC_FCS_FULL_MSB _u(9)
#define ADC_FCS_FULL_LSB _u(9)
#define ADC_FCS_FULL_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : ADC_FCS_EMPTY
#define ADC_FCS_EMPTY_RESET _u(0x0)
#define ADC_FCS_EMPTY_BITS _u(0x00000100)
#define ADC_FCS_EMPTY_MSB _u(8)
#define ADC_FCS_EMPTY_LSB _u(8)
#define ADC_FCS_EMPTY_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : ADC_FCS_DREQ_EN
// Description : If 1: assert DMA requests when FIFO contains data
#define ADC_FCS_DREQ_EN_RESET _u(0x0)
#define ADC_FCS_DREQ_EN_BITS _u(0x00000008)
#define ADC_FCS_DREQ_EN_MSB _u(3)
#define ADC_FCS_DREQ_EN_LSB _u(3)
#define ADC_FCS_DREQ_EN_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : ADC_FCS_ERR
// Description : If 1: conversion error bit appears in the FIFO alongside the
// result
#define ADC_FCS_ERR_RESET _u(0x0)
#define ADC_FCS_ERR_BITS _u(0x00000004)
#define ADC_FCS_ERR_MSB _u(2)
#define ADC_FCS_ERR_LSB _u(2)
#define ADC_FCS_ERR_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : ADC_FCS_SHIFT
// Description : If 1: FIFO results are right-shifted to be one byte in size.
// Enables DMA to byte buffers.
#define ADC_FCS_SHIFT_RESET _u(0x0)
#define ADC_FCS_SHIFT_BITS _u(0x00000002)
#define ADC_FCS_SHIFT_MSB _u(1)
#define ADC_FCS_SHIFT_LSB _u(1)
#define ADC_FCS_SHIFT_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : ADC_FCS_EN
// Description : If 1: write result to the FIFO after each conversion.
#define ADC_FCS_EN_RESET _u(0x0)
#define ADC_FCS_EN_BITS _u(0x00000001)
#define ADC_FCS_EN_MSB _u(0)
#define ADC_FCS_EN_LSB _u(0)
#define ADC_FCS_EN_ACCESS "RW"
// =============================================================================
// Register : ADC_FIFO
// Description : Conversion result FIFO
#define ADC_FIFO_OFFSET _u(0x0000000c)
#define ADC_FIFO_BITS _u(0x00008fff)
#define ADC_FIFO_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : ADC_FIFO_ERR
// Description : 1 if this particular sample experienced a conversion error.
// Remains in the same location if the sample is shifted.
#define ADC_FIFO_ERR_RESET "-"
#define ADC_FIFO_ERR_BITS _u(0x00008000)
#define ADC_FIFO_ERR_MSB _u(15)
#define ADC_FIFO_ERR_LSB _u(15)
#define ADC_FIFO_ERR_ACCESS "RF"
// -----------------------------------------------------------------------------
// Field : ADC_FIFO_VAL
#define ADC_FIFO_VAL_RESET "-"
#define ADC_FIFO_VAL_BITS _u(0x00000fff)
#define ADC_FIFO_VAL_MSB _u(11)
#define ADC_FIFO_VAL_LSB _u(0)
#define ADC_FIFO_VAL_ACCESS "RF"
// =============================================================================
// Register : ADC_DIV
// Description : Clock divider. If non-zero, CS_START_MANY will start
// conversions
// at regular intervals rather than back-to-back.
// The divider is reset when either of these fields are written.
// Total period is 1 + INT + FRAC / 256
#define ADC_DIV_OFFSET _u(0x00000010)
#define ADC_DIV_BITS _u(0x00ffffff)
#define ADC_DIV_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : ADC_DIV_INT
// Description : Integer part of clock divisor.
#define ADC_DIV_INT_RESET _u(0x0000)
#define ADC_DIV_INT_BITS _u(0x00ffff00)
#define ADC_DIV_INT_MSB _u(23)
#define ADC_DIV_INT_LSB _u(8)
#define ADC_DIV_INT_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : ADC_DIV_FRAC
// Description : Fractional part of clock divisor. First-order delta-sigma.
#define ADC_DIV_FRAC_RESET _u(0x00)
#define ADC_DIV_FRAC_BITS _u(0x000000ff)
#define ADC_DIV_FRAC_MSB _u(7)
#define ADC_DIV_FRAC_LSB _u(0)
#define ADC_DIV_FRAC_ACCESS "RW"
// =============================================================================
// Register : ADC_INTR
// Description : Raw Interrupts
#define ADC_INTR_OFFSET _u(0x00000014)
#define ADC_INTR_BITS _u(0x00000001)
#define ADC_INTR_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : ADC_INTR_FIFO
// Description : Triggered when the sample FIFO reaches a certain level.
// This level can be programmed via the FCS_THRESH field.
#define ADC_INTR_FIFO_RESET _u(0x0)
#define ADC_INTR_FIFO_BITS _u(0x00000001)
#define ADC_INTR_FIFO_MSB _u(0)
#define ADC_INTR_FIFO_LSB _u(0)
#define ADC_INTR_FIFO_ACCESS "RO"
// =============================================================================
// Register : ADC_INTE
// Description : Interrupt Enable
#define ADC_INTE_OFFSET _u(0x00000018)
#define ADC_INTE_BITS _u(0x00000001)
#define ADC_INTE_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : ADC_INTE_FIFO
// Description : Triggered when the sample FIFO reaches a certain level.
// This level can be programmed via the FCS_THRESH field.
#define ADC_INTE_FIFO_RESET _u(0x0)
#define ADC_INTE_FIFO_BITS _u(0x00000001)
#define ADC_INTE_FIFO_MSB _u(0)
#define ADC_INTE_FIFO_LSB _u(0)
#define ADC_INTE_FIFO_ACCESS "RW"
// =============================================================================
// Register : ADC_INTF
// Description : Interrupt Force
#define ADC_INTF_OFFSET _u(0x0000001c)
#define ADC_INTF_BITS _u(0x00000001)
#define ADC_INTF_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : ADC_INTF_FIFO
// Description : Triggered when the sample FIFO reaches a certain level.
// This level can be programmed via the FCS_THRESH field.
#define ADC_INTF_FIFO_RESET _u(0x0)
#define ADC_INTF_FIFO_BITS _u(0x00000001)
#define ADC_INTF_FIFO_MSB _u(0)
#define ADC_INTF_FIFO_LSB _u(0)
#define ADC_INTF_FIFO_ACCESS "RW"
// =============================================================================
// Register : ADC_INTS
// Description : Interrupt status after masking & forcing
#define ADC_INTS_OFFSET _u(0x00000020)
#define ADC_INTS_BITS _u(0x00000001)
#define ADC_INTS_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : ADC_INTS_FIFO
// Description : Triggered when the sample FIFO reaches a certain level.
// This level can be programmed via the FCS_THRESH field.
#define ADC_INTS_FIFO_RESET _u(0x0)
#define ADC_INTS_FIFO_BITS _u(0x00000001)
#define ADC_INTS_FIFO_MSB _u(0)
#define ADC_INTS_FIFO_LSB _u(0)
#define ADC_INTS_FIFO_ACCESS "RO"
// =============================================================================
#endif // _HARDWARE_REGS_ADC_H

112
arch/arm/src/rp23xx/hardware/regs/addressmap.h
View file

@ -1,112 +0,0 @@
// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _ADDRESSMAP_H
#define _ADDRESSMAP_H
/**
* \file rp2350/addressmap.h
*/
#include "hardware/platform_defs.h"
// Register address offsets for atomic RMW aliases
#define REG_ALIAS_RW_BITS (_u(0x0) << _u(12))
#define REG_ALIAS_XOR_BITS (_u(0x1) << _u(12))
#define REG_ALIAS_SET_BITS (_u(0x2) << _u(12))
#define REG_ALIAS_CLR_BITS (_u(0x3) << _u(12))
#define ROM_BASE _u(0x00000000)
#define XIP_BASE _u(0x10000000)
#define XIP_SRAM_BASE _u(0x13ffc000)
#define XIP_END _u(0x14000000)
#define XIP_NOCACHE_NOALLOC_BASE _u(0x14000000)
#define XIP_SRAM_END _u(0x14000000)
#define XIP_NOCACHE_NOALLOC_END _u(0x18000000)
#define XIP_MAINTENANCE_BASE _u(0x18000000)
#define XIP_NOCACHE_NOALLOC_NOTRANSLATE_BASE _u(0x1c000000)
#define SRAM0_BASE _u(0x20000000)
#define XIP_NOCACHE_NOALLOC_NOTRANSLATE_END _u(0x20000000)
#define SRAM_BASE _u(0x20000000)
#define SRAM_STRIPED_BASE _u(0x20000000)
#define SRAM4_BASE _u(0x20040000)
#define SRAM8_BASE _u(0x20080000)
#define SRAM_STRIPED_END _u(0x20080000)
#define SRAM_SCRATCH_X_BASE _u(0x20080000)
#define SRAM9_BASE _u(0x20081000)
#define SRAM_SCRATCH_Y_BASE _u(0x20081000)
#define SRAM_END _u(0x20082000)
#define SYSINFO_BASE _u(0x40000000)
#define SYSCFG_BASE _u(0x40008000)
#define CLOCKS_BASE _u(0x40010000)
#define PSM_BASE _u(0x40018000)
#define RESETS_BASE _u(0x40020000)
#define IO_BANK0_BASE _u(0x40028000)
#define IO_QSPI_BASE _u(0x40030000)
#define PADS_BANK0_BASE _u(0x40038000)
#define PADS_QSPI_BASE _u(0x40040000)
#define XOSC_BASE _u(0x40048000)
#define PLL_SYS_BASE _u(0x40050000)
#define PLL_USB_BASE _u(0x40058000)
#define ACCESSCTRL_BASE _u(0x40060000)
#define BUSCTRL_BASE _u(0x40068000)
#define UART0_BASE _u(0x40070000)
#define UART1_BASE _u(0x40078000)
#define SPI0_BASE _u(0x40080000)
#define SPI1_BASE _u(0x40088000)
#define I2C0_BASE _u(0x40090000)
#define I2C1_BASE _u(0x40098000)
#define ADC_BASE _u(0x400a0000)
#define PWM_BASE _u(0x400a8000)
#define TIMER0_BASE _u(0x400b0000)
#define TIMER1_BASE _u(0x400b8000)
#define HSTX_CTRL_BASE _u(0x400c0000)
#define XIP_CTRL_BASE _u(0x400c8000)
#define XIP_QMI_BASE _u(0x400d0000)
#define WATCHDOG_BASE _u(0x400d8000)
#define BOOTRAM_BASE _u(0x400e0000)
#define BOOTRAM_END _u(0x400e0400)
#define ROSC_BASE _u(0x400e8000)
#define TRNG_BASE _u(0x400f0000)
#define SHA256_BASE _u(0x400f8000)
#define POWMAN_BASE _u(0x40100000)
#define TICKS_BASE _u(0x40108000)
#define OTP_BASE _u(0x40120000)
#define OTP_DATA_BASE _u(0x40130000)
#define OTP_DATA_RAW_BASE _u(0x40134000)
#define OTP_DATA_GUARDED_BASE _u(0x40138000)
#define OTP_DATA_RAW_GUARDED_BASE _u(0x4013c000)
#define CORESIGHT_PERIPH_BASE _u(0x40140000)
#define CORESIGHT_ROMTABLE_BASE _u(0x40140000)
#define CORESIGHT_AHB_AP_CORE0_BASE _u(0x40142000)
#define CORESIGHT_AHB_AP_CORE1_BASE _u(0x40144000)
#define CORESIGHT_TIMESTAMP_GEN_BASE _u(0x40146000)
#define CORESIGHT_ATB_FUNNEL_BASE _u(0x40147000)
#define CORESIGHT_TPIU_BASE _u(0x40148000)
#define CORESIGHT_CTI_BASE _u(0x40149000)
#define CORESIGHT_APB_AP_RISCV_BASE _u(0x4014a000)
#define DFT_BASE _u(0x40150000)
#define GLITCH_DETECTOR_BASE _u(0x40158000)
#define TBMAN_BASE _u(0x40160000)
#define DMA_BASE _u(0x50000000)
#define USBCTRL_BASE _u(0x50100000)
#define USBCTRL_DPRAM_BASE _u(0x50100000)
#define USBCTRL_REGS_BASE _u(0x50110000)
#define PIO0_BASE _u(0x50200000)
#define PIO1_BASE _u(0x50300000)
#define PIO2_BASE _u(0x50400000)
#define XIP_AUX_BASE _u(0x50500000)
#define HSTX_FIFO_BASE _u(0x50600000)
#define CORESIGHT_TRACE_BASE _u(0x50700000)
#define SIO_BASE _u(0xd0000000)
#define SIO_NONSEC_BASE _u(0xd0020000)
#define PPB_BASE _u(0xe0000000)
#define PPB_NONSEC_BASE _u(0xe0020000)
#define EPPB_BASE _u(0xe0080000)
#endif // _ADDRESSMAP_H

130
arch/arm/src/rp23xx/hardware/regs/bootram.h
View file

@ -1,130 +0,0 @@
// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
// =============================================================================
// Register block : BOOTRAM
// Version : 1
// Bus type : apb
// Description : Additional registers mapped adjacent to the bootram, for use
// by the bootrom.
// =============================================================================
#ifndef _HARDWARE_REGS_BOOTRAM_H
#define _HARDWARE_REGS_BOOTRAM_H
// =============================================================================
// Register : BOOTRAM_WRITE_ONCE0
// Description : This registers always ORs writes into its current contents.
// Once a bit is set, it can only be cleared by a reset.
#define BOOTRAM_WRITE_ONCE0_OFFSET _u(0x00000800)
#define BOOTRAM_WRITE_ONCE0_BITS _u(0xffffffff)
#define BOOTRAM_WRITE_ONCE0_RESET _u(0x00000000)
#define BOOTRAM_WRITE_ONCE0_MSB _u(31)
#define BOOTRAM_WRITE_ONCE0_LSB _u(0)
#define BOOTRAM_WRITE_ONCE0_ACCESS "RW"
// =============================================================================
// Register : BOOTRAM_WRITE_ONCE1
// Description : This registers always ORs writes into its current contents.
// Once a bit is set, it can only be cleared by a reset.
#define BOOTRAM_WRITE_ONCE1_OFFSET _u(0x00000804)
#define BOOTRAM_WRITE_ONCE1_BITS _u(0xffffffff)
#define BOOTRAM_WRITE_ONCE1_RESET _u(0x00000000)
#define BOOTRAM_WRITE_ONCE1_MSB _u(31)
#define BOOTRAM_WRITE_ONCE1_LSB _u(0)
#define BOOTRAM_WRITE_ONCE1_ACCESS "RW"
// =============================================================================
// Register : BOOTRAM_BOOTLOCK_STAT
// Description : Bootlock status register. 1=unclaimed, 0=claimed. These locks
// function identically to the SIO spinlocks, but are reserved for
// bootrom use.
#define BOOTRAM_BOOTLOCK_STAT_OFFSET _u(0x00000808)
#define BOOTRAM_BOOTLOCK_STAT_BITS _u(0x000000ff)
#define BOOTRAM_BOOTLOCK_STAT_RESET _u(0x000000ff)
#define BOOTRAM_BOOTLOCK_STAT_MSB _u(7)
#define BOOTRAM_BOOTLOCK_STAT_LSB _u(0)
#define BOOTRAM_BOOTLOCK_STAT_ACCESS "RW"
// =============================================================================
// Register : BOOTRAM_BOOTLOCK0
// Description : Read to claim and check. Write to unclaim. The value returned
// on successful claim is 1 << n, and on failed claim is zero.
#define BOOTRAM_BOOTLOCK0_OFFSET _u(0x0000080c)
#define BOOTRAM_BOOTLOCK0_BITS _u(0xffffffff)
#define BOOTRAM_BOOTLOCK0_RESET _u(0x00000000)
#define BOOTRAM_BOOTLOCK0_MSB _u(31)
#define BOOTRAM_BOOTLOCK0_LSB _u(0)
#define BOOTRAM_BOOTLOCK0_ACCESS "RW"
// =============================================================================
// Register : BOOTRAM_BOOTLOCK1
// Description : Read to claim and check. Write to unclaim. The value returned
// on successful claim is 1 << n, and on failed claim is zero.
#define BOOTRAM_BOOTLOCK1_OFFSET _u(0x00000810)
#define BOOTRAM_BOOTLOCK1_BITS _u(0xffffffff)
#define BOOTRAM_BOOTLOCK1_RESET _u(0x00000000)
#define BOOTRAM_BOOTLOCK1_MSB _u(31)
#define BOOTRAM_BOOTLOCK1_LSB _u(0)
#define BOOTRAM_BOOTLOCK1_ACCESS "RW"
// =============================================================================
// Register : BOOTRAM_BOOTLOCK2
// Description : Read to claim and check. Write to unclaim. The value returned
// on successful claim is 1 << n, and on failed claim is zero.
#define BOOTRAM_BOOTLOCK2_OFFSET _u(0x00000814)
#define BOOTRAM_BOOTLOCK2_BITS _u(0xffffffff)
#define BOOTRAM_BOOTLOCK2_RESET _u(0x00000000)
#define BOOTRAM_BOOTLOCK2_MSB _u(31)
#define BOOTRAM_BOOTLOCK2_LSB _u(0)
#define BOOTRAM_BOOTLOCK2_ACCESS "RW"
// =============================================================================
// Register : BOOTRAM_BOOTLOCK3
// Description : Read to claim and check. Write to unclaim. The value returned
// on successful claim is 1 << n, and on failed claim is zero.
#define BOOTRAM_BOOTLOCK3_OFFSET _u(0x00000818)
#define BOOTRAM_BOOTLOCK3_BITS _u(0xffffffff)
#define BOOTRAM_BOOTLOCK3_RESET _u(0x00000000)
#define BOOTRAM_BOOTLOCK3_MSB _u(31)
#define BOOTRAM_BOOTLOCK3_LSB _u(0)
#define BOOTRAM_BOOTLOCK3_ACCESS "RW"
// =============================================================================
// Register : BOOTRAM_BOOTLOCK4
// Description : Read to claim and check. Write to unclaim. The value returned
// on successful claim is 1 << n, and on failed claim is zero.
#define BOOTRAM_BOOTLOCK4_OFFSET _u(0x0000081c)
#define BOOTRAM_BOOTLOCK4_BITS _u(0xffffffff)
#define BOOTRAM_BOOTLOCK4_RESET _u(0x00000000)
#define BOOTRAM_BOOTLOCK4_MSB _u(31)
#define BOOTRAM_BOOTLOCK4_LSB _u(0)
#define BOOTRAM_BOOTLOCK4_ACCESS "RW"
// =============================================================================
// Register : BOOTRAM_BOOTLOCK5
// Description : Read to claim and check. Write to unclaim. The value returned
// on successful claim is 1 << n, and on failed claim is zero.
#define BOOTRAM_BOOTLOCK5_OFFSET _u(0x00000820)
#define BOOTRAM_BOOTLOCK5_BITS _u(0xffffffff)
#define BOOTRAM_BOOTLOCK5_RESET _u(0x00000000)
#define BOOTRAM_BOOTLOCK5_MSB _u(31)
#define BOOTRAM_BOOTLOCK5_LSB _u(0)
#define BOOTRAM_BOOTLOCK5_ACCESS "RW"
// =============================================================================
// Register : BOOTRAM_BOOTLOCK6
// Description : Read to claim and check. Write to unclaim. The value returned
// on successful claim is 1 << n, and on failed claim is zero.
#define BOOTRAM_BOOTLOCK6_OFFSET _u(0x00000824)
#define BOOTRAM_BOOTLOCK6_BITS _u(0xffffffff)
#define BOOTRAM_BOOTLOCK6_RESET _u(0x00000000)
#define BOOTRAM_BOOTLOCK6_MSB _u(31)
#define BOOTRAM_BOOTLOCK6_LSB _u(0)
#define BOOTRAM_BOOTLOCK6_ACCESS "RW"
// =============================================================================
// Register : BOOTRAM_BOOTLOCK7
// Description : Read to claim and check. Write to unclaim. The value returned
// on successful claim is 1 << n, and on failed claim is zero.
#define BOOTRAM_BOOTLOCK7_OFFSET _u(0x00000828)
#define BOOTRAM_BOOTLOCK7_BITS _u(0xffffffff)
#define BOOTRAM_BOOTLOCK7_RESET _u(0x00000000)
#define BOOTRAM_BOOTLOCK7_MSB _u(31)
#define BOOTRAM_BOOTLOCK7_LSB _u(0)
#define BOOTRAM_BOOTLOCK7_ACCESS "RW"
// =============================================================================
#endif // _HARDWARE_REGS_BOOTRAM_H

753
arch/arm/src/rp23xx/hardware/regs/busctrl.h
View file

@ -1,753 +0,0 @@
// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
// =============================================================================
// Register block : BUSCTRL
// Version : 1
// Bus type : apb
// Description : Register block for busfabric control signals and performance
// counters
// =============================================================================
#ifndef _HARDWARE_REGS_BUSCTRL_H
#define _HARDWARE_REGS_BUSCTRL_H
// =============================================================================
// Register : BUSCTRL_BUS_PRIORITY
// Description : Set the priority of each master for bus arbitration.
#define BUSCTRL_BUS_PRIORITY_OFFSET _u(0x00000000)
#define BUSCTRL_BUS_PRIORITY_BITS _u(0x00001111)
#define BUSCTRL_BUS_PRIORITY_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : BUSCTRL_BUS_PRIORITY_DMA_W
// Description : 0 - low priority, 1 - high priority
#define BUSCTRL_BUS_PRIORITY_DMA_W_RESET _u(0x0)
#define BUSCTRL_BUS_PRIORITY_DMA_W_BITS _u(0x00001000)
#define BUSCTRL_BUS_PRIORITY_DMA_W_MSB _u(12)
#define BUSCTRL_BUS_PRIORITY_DMA_W_LSB _u(12)
#define BUSCTRL_BUS_PRIORITY_DMA_W_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : BUSCTRL_BUS_PRIORITY_DMA_R
// Description : 0 - low priority, 1 - high priority
#define BUSCTRL_BUS_PRIORITY_DMA_R_RESET _u(0x0)
#define BUSCTRL_BUS_PRIORITY_DMA_R_BITS _u(0x00000100)
#define BUSCTRL_BUS_PRIORITY_DMA_R_MSB _u(8)
#define BUSCTRL_BUS_PRIORITY_DMA_R_LSB _u(8)
#define BUSCTRL_BUS_PRIORITY_DMA_R_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : BUSCTRL_BUS_PRIORITY_PROC1
// Description : 0 - low priority, 1 - high priority
#define BUSCTRL_BUS_PRIORITY_PROC1_RESET _u(0x0)
#define BUSCTRL_BUS_PRIORITY_PROC1_BITS _u(0x00000010)
#define BUSCTRL_BUS_PRIORITY_PROC1_MSB _u(4)
#define BUSCTRL_BUS_PRIORITY_PROC1_LSB _u(4)
#define BUSCTRL_BUS_PRIORITY_PROC1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : BUSCTRL_BUS_PRIORITY_PROC0
// Description : 0 - low priority, 1 - high priority
#define BUSCTRL_BUS_PRIORITY_PROC0_RESET _u(0x0)
#define BUSCTRL_BUS_PRIORITY_PROC0_BITS _u(0x00000001)
#define BUSCTRL_BUS_PRIORITY_PROC0_MSB _u(0)
#define BUSCTRL_BUS_PRIORITY_PROC0_LSB _u(0)
#define BUSCTRL_BUS_PRIORITY_PROC0_ACCESS "RW"
// =============================================================================
// Register : BUSCTRL_BUS_PRIORITY_ACK
// Description : Bus priority acknowledge
// Goes to 1 once all arbiters have registered the new global
// priority levels.
// Arbiters update their local priority when servicing a new
// nonsequential access.
// In normal circumstances this will happen almost immediately.
#define BUSCTRL_BUS_PRIORITY_ACK_OFFSET _u(0x00000004)
#define BUSCTRL_BUS_PRIORITY_ACK_BITS _u(0x00000001)
#define BUSCTRL_BUS_PRIORITY_ACK_RESET _u(0x00000000)
#define BUSCTRL_BUS_PRIORITY_ACK_MSB _u(0)
#define BUSCTRL_BUS_PRIORITY_ACK_LSB _u(0)
#define BUSCTRL_BUS_PRIORITY_ACK_ACCESS "RO"
// =============================================================================
// Register : BUSCTRL_PERFCTR_EN
// Description : Enable the performance counters. If 0, the performance counters
// do not increment. This can be used to precisely start/stop
// event sampling around the profiled section of code.
//
// The performance counters are initially disabled, to save
// energy.
#define BUSCTRL_PERFCTR_EN_OFFSET _u(0x00000008)
#define BUSCTRL_PERFCTR_EN_BITS _u(0x00000001)
#define BUSCTRL_PERFCTR_EN_RESET _u(0x00000000)
#define BUSCTRL_PERFCTR_EN_MSB _u(0)
#define BUSCTRL_PERFCTR_EN_LSB _u(0)
#define BUSCTRL_PERFCTR_EN_ACCESS "RW"
// =============================================================================
// Register : BUSCTRL_PERFCTR0
// Description : Bus fabric performance counter 0
// Busfabric saturating performance counter 0
// Count some event signal from the busfabric arbiters, if
// PERFCTR_EN is set.
// Write any value to clear. Select an event to count using
// PERFSEL0
#define BUSCTRL_PERFCTR0_OFFSET _u(0x0000000c)
#define BUSCTRL_PERFCTR0_BITS _u(0x00ffffff)
#define BUSCTRL_PERFCTR0_RESET _u(0x00000000)
#define BUSCTRL_PERFCTR0_MSB _u(23)
#define BUSCTRL_PERFCTR0_LSB _u(0)
#define BUSCTRL_PERFCTR0_ACCESS "WC"
// =============================================================================
// Register : BUSCTRL_PERFSEL0
// Description : Bus fabric performance event select for PERFCTR0
// Select an event for PERFCTR0. For each downstream port of the
// main crossbar, four events are available: ACCESS, an access
// took place; ACCESS_CONTESTED, an access took place that
// previously stalled due to contention from other masters;
// STALL_DOWNSTREAM, count cycles where any master stalled due to
// a stall on the downstream bus; STALL_UPSTREAM, count cycles
// where any master stalled for any reason, including contention
// from other masters.
// 0x00 -> siob_proc1_stall_upstream
// 0x01 -> siob_proc1_stall_downstream
// 0x02 -> siob_proc1_access_contested
// 0x03 -> siob_proc1_access
// 0x04 -> siob_proc0_stall_upstream
// 0x05 -> siob_proc0_stall_downstream
// 0x06 -> siob_proc0_access_contested
// 0x07 -> siob_proc0_access
// 0x08 -> apb_stall_upstream
// 0x09 -> apb_stall_downstream
// 0x0a -> apb_access_contested
// 0x0b -> apb_access
// 0x0c -> fastperi_stall_upstream
// 0x0d -> fastperi_stall_downstream
// 0x0e -> fastperi_access_contested
// 0x0f -> fastperi_access
// 0x10 -> sram9_stall_upstream
// 0x11 -> sram9_stall_downstream
// 0x12 -> sram9_access_contested
// 0x13 -> sram9_access
// 0x14 -> sram8_stall_upstream
// 0x15 -> sram8_stall_downstream
// 0x16 -> sram8_access_contested
// 0x17 -> sram8_access
// 0x18 -> sram7_stall_upstream
// 0x19 -> sram7_stall_downstream
// 0x1a -> sram7_access_contested
// 0x1b -> sram7_access
// 0x1c -> sram6_stall_upstream
// 0x1d -> sram6_stall_downstream
// 0x1e -> sram6_access_contested
// 0x1f -> sram6_access
// 0x20 -> sram5_stall_upstream
// 0x21 -> sram5_stall_downstream
// 0x22 -> sram5_access_contested
// 0x23 -> sram5_access
// 0x24 -> sram4_stall_upstream
// 0x25 -> sram4_stall_downstream
// 0x26 -> sram4_access_contested
// 0x27 -> sram4_access
// 0x28 -> sram3_stall_upstream
// 0x29 -> sram3_stall_downstream
// 0x2a -> sram3_access_contested
// 0x2b -> sram3_access
// 0x2c -> sram2_stall_upstream
// 0x2d -> sram2_stall_downstream
// 0x2e -> sram2_access_contested
// 0x2f -> sram2_access
// 0x30 -> sram1_stall_upstream
// 0x31 -> sram1_stall_downstream
// 0x32 -> sram1_access_contested
// 0x33 -> sram1_access
// 0x34 -> sram0_stall_upstream
// 0x35 -> sram0_stall_downstream
// 0x36 -> sram0_access_contested
// 0x37 -> sram0_access
// 0x38 -> xip_main1_stall_upstream
// 0x39 -> xip_main1_stall_downstream
// 0x3a -> xip_main1_access_contested
// 0x3b -> xip_main1_access
// 0x3c -> xip_main0_stall_upstream
// 0x3d -> xip_main0_stall_downstream
// 0x3e -> xip_main0_access_contested
// 0x3f -> xip_main0_access
// 0x40 -> rom_stall_upstream
// 0x41 -> rom_stall_downstream
// 0x42 -> rom_access_contested
// 0x43 -> rom_access
#define BUSCTRL_PERFSEL0_OFFSET _u(0x00000010)
#define BUSCTRL_PERFSEL0_BITS _u(0x0000007f)
#define BUSCTRL_PERFSEL0_RESET _u(0x0000001f)
#define BUSCTRL_PERFSEL0_MSB _u(6)
#define BUSCTRL_PERFSEL0_LSB _u(0)
#define BUSCTRL_PERFSEL0_ACCESS "RW"
#define BUSCTRL_PERFSEL0_VALUE_SIOB_PROC1_STALL_UPSTREAM _u(0x00)
#define BUSCTRL_PERFSEL0_VALUE_SIOB_PROC1_STALL_DOWNSTREAM _u(0x01)
#define BUSCTRL_PERFSEL0_VALUE_SIOB_PROC1_ACCESS_CONTESTED _u(0x02)
#define BUSCTRL_PERFSEL0_VALUE_SIOB_PROC1_ACCESS _u(0x03)
#define BUSCTRL_PERFSEL0_VALUE_SIOB_PROC0_STALL_UPSTREAM _u(0x04)
#define BUSCTRL_PERFSEL0_VALUE_SIOB_PROC0_STALL_DOWNSTREAM _u(0x05)
#define BUSCTRL_PERFSEL0_VALUE_SIOB_PROC0_ACCESS_CONTESTED _u(0x06)
#define BUSCTRL_PERFSEL0_VALUE_SIOB_PROC0_ACCESS _u(0x07)
#define BUSCTRL_PERFSEL0_VALUE_APB_STALL_UPSTREAM _u(0x08)
#define BUSCTRL_PERFSEL0_VALUE_APB_STALL_DOWNSTREAM _u(0x09)
#define BUSCTRL_PERFSEL0_VALUE_APB_ACCESS_CONTESTED _u(0x0a)
#define BUSCTRL_PERFSEL0_VALUE_APB_ACCESS _u(0x0b)
#define BUSCTRL_PERFSEL0_VALUE_FASTPERI_STALL_UPSTREAM _u(0x0c)
#define BUSCTRL_PERFSEL0_VALUE_FASTPERI_STALL_DOWNSTREAM _u(0x0d)
#define BUSCTRL_PERFSEL0_VALUE_FASTPERI_ACCESS_CONTESTED _u(0x0e)
#define BUSCTRL_PERFSEL0_VALUE_FASTPERI_ACCESS _u(0x0f)
#define BUSCTRL_PERFSEL0_VALUE_SRAM9_STALL_UPSTREAM _u(0x10)
#define BUSCTRL_PERFSEL0_VALUE_SRAM9_STALL_DOWNSTREAM _u(0x11)
#define BUSCTRL_PERFSEL0_VALUE_SRAM9_ACCESS_CONTESTED _u(0x12)
#define BUSCTRL_PERFSEL0_VALUE_SRAM9_ACCESS _u(0x13)
#define BUSCTRL_PERFSEL0_VALUE_SRAM8_STALL_UPSTREAM _u(0x14)
#define BUSCTRL_PERFSEL0_VALUE_SRAM8_STALL_DOWNSTREAM _u(0x15)
#define BUSCTRL_PERFSEL0_VALUE_SRAM8_ACCESS_CONTESTED _u(0x16)
#define BUSCTRL_PERFSEL0_VALUE_SRAM8_ACCESS _u(0x17)
#define BUSCTRL_PERFSEL0_VALUE_SRAM7_STALL_UPSTREAM _u(0x18)
#define BUSCTRL_PERFSEL0_VALUE_SRAM7_STALL_DOWNSTREAM _u(0x19)
#define BUSCTRL_PERFSEL0_VALUE_SRAM7_ACCESS_CONTESTED _u(0x1a)
#define BUSCTRL_PERFSEL0_VALUE_SRAM7_ACCESS _u(0x1b)
#define BUSCTRL_PERFSEL0_VALUE_SRAM6_STALL_UPSTREAM _u(0x1c)
#define BUSCTRL_PERFSEL0_VALUE_SRAM6_STALL_DOWNSTREAM _u(0x1d)
#define BUSCTRL_PERFSEL0_VALUE_SRAM6_ACCESS_CONTESTED _u(0x1e)
#define BUSCTRL_PERFSEL0_VALUE_SRAM6_ACCESS _u(0x1f)
#define BUSCTRL_PERFSEL0_VALUE_SRAM5_STALL_UPSTREAM _u(0x20)
#define BUSCTRL_PERFSEL0_VALUE_SRAM5_STALL_DOWNSTREAM _u(0x21)
#define BUSCTRL_PERFSEL0_VALUE_SRAM5_ACCESS_CONTESTED _u(0x22)
#define BUSCTRL_PERFSEL0_VALUE_SRAM5_ACCESS _u(0x23)
#define BUSCTRL_PERFSEL0_VALUE_SRAM4_STALL_UPSTREAM _u(0x24)
#define BUSCTRL_PERFSEL0_VALUE_SRAM4_STALL_DOWNSTREAM _u(0x25)
#define BUSCTRL_PERFSEL0_VALUE_SRAM4_ACCESS_CONTESTED _u(0x26)
#define BUSCTRL_PERFSEL0_VALUE_SRAM4_ACCESS _u(0x27)
#define BUSCTRL_PERFSEL0_VALUE_SRAM3_STALL_UPSTREAM _u(0x28)
#define BUSCTRL_PERFSEL0_VALUE_SRAM3_STALL_DOWNSTREAM _u(0x29)
#define BUSCTRL_PERFSEL0_VALUE_SRAM3_ACCESS_CONTESTED _u(0x2a)
#define BUSCTRL_PERFSEL0_VALUE_SRAM3_ACCESS _u(0x2b)
#define BUSCTRL_PERFSEL0_VALUE_SRAM2_STALL_UPSTREAM _u(0x2c)
#define BUSCTRL_PERFSEL0_VALUE_SRAM2_STALL_DOWNSTREAM _u(0x2d)
#define BUSCTRL_PERFSEL0_VALUE_SRAM2_ACCESS_CONTESTED _u(0x2e)
#define BUSCTRL_PERFSEL0_VALUE_SRAM2_ACCESS _u(0x2f)
#define BUSCTRL_PERFSEL0_VALUE_SRAM1_STALL_UPSTREAM _u(0x30)
#define BUSCTRL_PERFSEL0_VALUE_SRAM1_STALL_DOWNSTREAM _u(0x31)
#define BUSCTRL_PERFSEL0_VALUE_SRAM1_ACCESS_CONTESTED _u(0x32)
#define BUSCTRL_PERFSEL0_VALUE_SRAM1_ACCESS _u(0x33)
#define BUSCTRL_PERFSEL0_VALUE_SRAM0_STALL_UPSTREAM _u(0x34)
#define BUSCTRL_PERFSEL0_VALUE_SRAM0_STALL_DOWNSTREAM _u(0x35)
#define BUSCTRL_PERFSEL0_VALUE_SRAM0_ACCESS_CONTESTED _u(0x36)
#define BUSCTRL_PERFSEL0_VALUE_SRAM0_ACCESS _u(0x37)
#define BUSCTRL_PERFSEL0_VALUE_XIP_MAIN1_STALL_UPSTREAM _u(0x38)
#define BUSCTRL_PERFSEL0_VALUE_XIP_MAIN1_STALL_DOWNSTREAM _u(0x39)
#define BUSCTRL_PERFSEL0_VALUE_XIP_MAIN1_ACCESS_CONTESTED _u(0x3a)
#define BUSCTRL_PERFSEL0_VALUE_XIP_MAIN1_ACCESS _u(0x3b)
#define BUSCTRL_PERFSEL0_VALUE_XIP_MAIN0_STALL_UPSTREAM _u(0x3c)
#define BUSCTRL_PERFSEL0_VALUE_XIP_MAIN0_STALL_DOWNSTREAM _u(0x3d)
#define BUSCTRL_PERFSEL0_VALUE_XIP_MAIN0_ACCESS_CONTESTED _u(0x3e)
#define BUSCTRL_PERFSEL0_VALUE_XIP_MAIN0_ACCESS _u(0x3f)
#define BUSCTRL_PERFSEL0_VALUE_ROM_STALL_UPSTREAM _u(0x40)
#define BUSCTRL_PERFSEL0_VALUE_ROM_STALL_DOWNSTREAM _u(0x41)
#define BUSCTRL_PERFSEL0_VALUE_ROM_ACCESS_CONTESTED _u(0x42)
#define BUSCTRL_PERFSEL0_VALUE_ROM_ACCESS _u(0x43)
// =============================================================================
// Register : BUSCTRL_PERFCTR1
// Description : Bus fabric performance counter 1
// Busfabric saturating performance counter 1
// Count some event signal from the busfabric arbiters, if
// PERFCTR_EN is set.
// Write any value to clear. Select an event to count using
// PERFSEL1
#define BUSCTRL_PERFCTR1_OFFSET _u(0x00000014)
#define BUSCTRL_PERFCTR1_BITS _u(0x00ffffff)
#define BUSCTRL_PERFCTR1_RESET _u(0x00000000)
#define BUSCTRL_PERFCTR1_MSB _u(23)
#define BUSCTRL_PERFCTR1_LSB _u(0)
#define BUSCTRL_PERFCTR1_ACCESS "WC"
// =============================================================================
// Register : BUSCTRL_PERFSEL1
// Description : Bus fabric performance event select for PERFCTR1
// Select an event for PERFCTR1. For each downstream port of the
// main crossbar, four events are available: ACCESS, an access
// took place; ACCESS_CONTESTED, an access took place that
// previously stalled due to contention from other masters;
// STALL_DOWNSTREAM, count cycles where any master stalled due to
// a stall on the downstream bus; STALL_UPSTREAM, count cycles
// where any master stalled for any reason, including contention
// from other masters.
// 0x00 -> siob_proc1_stall_upstream
// 0x01 -> siob_proc1_stall_downstream
// 0x02 -> siob_proc1_access_contested
// 0x03 -> siob_proc1_access
// 0x04 -> siob_proc0_stall_upstream
// 0x05 -> siob_proc0_stall_downstream
// 0x06 -> siob_proc0_access_contested
// 0x07 -> siob_proc0_access
// 0x08 -> apb_stall_upstream
// 0x09 -> apb_stall_downstream
// 0x0a -> apb_access_contested
// 0x0b -> apb_access
// 0x0c -> fastperi_stall_upstream
// 0x0d -> fastperi_stall_downstream
// 0x0e -> fastperi_access_contested
// 0x0f -> fastperi_access
// 0x10 -> sram9_stall_upstream
// 0x11 -> sram9_stall_downstream
// 0x12 -> sram9_access_contested
// 0x13 -> sram9_access
// 0x14 -> sram8_stall_upstream
// 0x15 -> sram8_stall_downstream
// 0x16 -> sram8_access_contested
// 0x17 -> sram8_access
// 0x18 -> sram7_stall_upstream
// 0x19 -> sram7_stall_downstream
// 0x1a -> sram7_access_contested
// 0x1b -> sram7_access
// 0x1c -> sram6_stall_upstream
// 0x1d -> sram6_stall_downstream
// 0x1e -> sram6_access_contested
// 0x1f -> sram6_access
// 0x20 -> sram5_stall_upstream
// 0x21 -> sram5_stall_downstream
// 0x22 -> sram5_access_contested
// 0x23 -> sram5_access
// 0x24 -> sram4_stall_upstream
// 0x25 -> sram4_stall_downstream
// 0x26 -> sram4_access_contested
// 0x27 -> sram4_access
// 0x28 -> sram3_stall_upstream
// 0x29 -> sram3_stall_downstream
// 0x2a -> sram3_access_contested
// 0x2b -> sram3_access
// 0x2c -> sram2_stall_upstream
// 0x2d -> sram2_stall_downstream
// 0x2e -> sram2_access_contested
// 0x2f -> sram2_access
// 0x30 -> sram1_stall_upstream
// 0x31 -> sram1_stall_downstream
// 0x32 -> sram1_access_contested
// 0x33 -> sram1_access
// 0x34 -> sram0_stall_upstream
// 0x35 -> sram0_stall_downstream
// 0x36 -> sram0_access_contested
// 0x37 -> sram0_access
// 0x38 -> xip_main1_stall_upstream
// 0x39 -> xip_main1_stall_downstream
// 0x3a -> xip_main1_access_contested
// 0x3b -> xip_main1_access
// 0x3c -> xip_main0_stall_upstream
// 0x3d -> xip_main0_stall_downstream
// 0x3e -> xip_main0_access_contested
// 0x3f -> xip_main0_access
// 0x40 -> rom_stall_upstream
// 0x41 -> rom_stall_downstream
// 0x42 -> rom_access_contested
// 0x43 -> rom_access
#define BUSCTRL_PERFSEL1_OFFSET _u(0x00000018)
#define BUSCTRL_PERFSEL1_BITS _u(0x0000007f)
#define BUSCTRL_PERFSEL1_RESET _u(0x0000001f)
#define BUSCTRL_PERFSEL1_MSB _u(6)
#define BUSCTRL_PERFSEL1_LSB _u(0)
#define BUSCTRL_PERFSEL1_ACCESS "RW"
#define BUSCTRL_PERFSEL1_VALUE_SIOB_PROC1_STALL_UPSTREAM _u(0x00)
#define BUSCTRL_PERFSEL1_VALUE_SIOB_PROC1_STALL_DOWNSTREAM _u(0x01)
#define BUSCTRL_PERFSEL1_VALUE_SIOB_PROC1_ACCESS_CONTESTED _u(0x02)
#define BUSCTRL_PERFSEL1_VALUE_SIOB_PROC1_ACCESS _u(0x03)
#define BUSCTRL_PERFSEL1_VALUE_SIOB_PROC0_STALL_UPSTREAM _u(0x04)
#define BUSCTRL_PERFSEL1_VALUE_SIOB_PROC0_STALL_DOWNSTREAM _u(0x05)
#define BUSCTRL_PERFSEL1_VALUE_SIOB_PROC0_ACCESS_CONTESTED _u(0x06)
#define BUSCTRL_PERFSEL1_VALUE_SIOB_PROC0_ACCESS _u(0x07)
#define BUSCTRL_PERFSEL1_VALUE_APB_STALL_UPSTREAM _u(0x08)
#define BUSCTRL_PERFSEL1_VALUE_APB_STALL_DOWNSTREAM _u(0x09)
#define BUSCTRL_PERFSEL1_VALUE_APB_ACCESS_CONTESTED _u(0x0a)
#define BUSCTRL_PERFSEL1_VALUE_APB_ACCESS _u(0x0b)
#define BUSCTRL_PERFSEL1_VALUE_FASTPERI_STALL_UPSTREAM _u(0x0c)
#define BUSCTRL_PERFSEL1_VALUE_FASTPERI_STALL_DOWNSTREAM _u(0x0d)
#define BUSCTRL_PERFSEL1_VALUE_FASTPERI_ACCESS_CONTESTED _u(0x0e)
#define BUSCTRL_PERFSEL1_VALUE_FASTPERI_ACCESS _u(0x0f)
#define BUSCTRL_PERFSEL1_VALUE_SRAM9_STALL_UPSTREAM _u(0x10)
#define BUSCTRL_PERFSEL1_VALUE_SRAM9_STALL_DOWNSTREAM _u(0x11)
#define BUSCTRL_PERFSEL1_VALUE_SRAM9_ACCESS_CONTESTED _u(0x12)
#define BUSCTRL_PERFSEL1_VALUE_SRAM9_ACCESS _u(0x13)
#define BUSCTRL_PERFSEL1_VALUE_SRAM8_STALL_UPSTREAM _u(0x14)
#define BUSCTRL_PERFSEL1_VALUE_SRAM8_STALL_DOWNSTREAM _u(0x15)
#define BUSCTRL_PERFSEL1_VALUE_SRAM8_ACCESS_CONTESTED _u(0x16)
#define BUSCTRL_PERFSEL1_VALUE_SRAM8_ACCESS _u(0x17)
#define BUSCTRL_PERFSEL1_VALUE_SRAM7_STALL_UPSTREAM _u(0x18)
#define BUSCTRL_PERFSEL1_VALUE_SRAM7_STALL_DOWNSTREAM _u(0x19)
#define BUSCTRL_PERFSEL1_VALUE_SRAM7_ACCESS_CONTESTED _u(0x1a)
#define BUSCTRL_PERFSEL1_VALUE_SRAM7_ACCESS _u(0x1b)
#define BUSCTRL_PERFSEL1_VALUE_SRAM6_STALL_UPSTREAM _u(0x1c)
#define BUSCTRL_PERFSEL1_VALUE_SRAM6_STALL_DOWNSTREAM _u(0x1d)
#define BUSCTRL_PERFSEL1_VALUE_SRAM6_ACCESS_CONTESTED _u(0x1e)
#define BUSCTRL_PERFSEL1_VALUE_SRAM6_ACCESS _u(0x1f)
#define BUSCTRL_PERFSEL1_VALUE_SRAM5_STALL_UPSTREAM _u(0x20)
#define BUSCTRL_PERFSEL1_VALUE_SRAM5_STALL_DOWNSTREAM _u(0x21)
#define BUSCTRL_PERFSEL1_VALUE_SRAM5_ACCESS_CONTESTED _u(0x22)
#define BUSCTRL_PERFSEL1_VALUE_SRAM5_ACCESS _u(0x23)
#define BUSCTRL_PERFSEL1_VALUE_SRAM4_STALL_UPSTREAM _u(0x24)
#define BUSCTRL_PERFSEL1_VALUE_SRAM4_STALL_DOWNSTREAM _u(0x25)
#define BUSCTRL_PERFSEL1_VALUE_SRAM4_ACCESS_CONTESTED _u(0x26)
#define BUSCTRL_PERFSEL1_VALUE_SRAM4_ACCESS _u(0x27)
#define BUSCTRL_PERFSEL1_VALUE_SRAM3_STALL_UPSTREAM _u(0x28)
#define BUSCTRL_PERFSEL1_VALUE_SRAM3_STALL_DOWNSTREAM _u(0x29)
#define BUSCTRL_PERFSEL1_VALUE_SRAM3_ACCESS_CONTESTED _u(0x2a)
#define BUSCTRL_PERFSEL1_VALUE_SRAM3_ACCESS _u(0x2b)
#define BUSCTRL_PERFSEL1_VALUE_SRAM2_STALL_UPSTREAM _u(0x2c)
#define BUSCTRL_PERFSEL1_VALUE_SRAM2_STALL_DOWNSTREAM _u(0x2d)
#define BUSCTRL_PERFSEL1_VALUE_SRAM2_ACCESS_CONTESTED _u(0x2e)
#define BUSCTRL_PERFSEL1_VALUE_SRAM2_ACCESS _u(0x2f)
#define BUSCTRL_PERFSEL1_VALUE_SRAM1_STALL_UPSTREAM _u(0x30)
#define BUSCTRL_PERFSEL1_VALUE_SRAM1_STALL_DOWNSTREAM _u(0x31)
#define BUSCTRL_PERFSEL1_VALUE_SRAM1_ACCESS_CONTESTED _u(0x32)
#define BUSCTRL_PERFSEL1_VALUE_SRAM1_ACCESS _u(0x33)
#define BUSCTRL_PERFSEL1_VALUE_SRAM0_STALL_UPSTREAM _u(0x34)
#define BUSCTRL_PERFSEL1_VALUE_SRAM0_STALL_DOWNSTREAM _u(0x35)
#define BUSCTRL_PERFSEL1_VALUE_SRAM0_ACCESS_CONTESTED _u(0x36)
#define BUSCTRL_PERFSEL1_VALUE_SRAM0_ACCESS _u(0x37)
#define BUSCTRL_PERFSEL1_VALUE_XIP_MAIN1_STALL_UPSTREAM _u(0x38)
#define BUSCTRL_PERFSEL1_VALUE_XIP_MAIN1_STALL_DOWNSTREAM _u(0x39)
#define BUSCTRL_PERFSEL1_VALUE_XIP_MAIN1_ACCESS_CONTESTED _u(0x3a)
#define BUSCTRL_PERFSEL1_VALUE_XIP_MAIN1_ACCESS _u(0x3b)
#define BUSCTRL_PERFSEL1_VALUE_XIP_MAIN0_STALL_UPSTREAM _u(0x3c)
#define BUSCTRL_PERFSEL1_VALUE_XIP_MAIN0_STALL_DOWNSTREAM _u(0x3d)
#define BUSCTRL_PERFSEL1_VALUE_XIP_MAIN0_ACCESS_CONTESTED _u(0x3e)
#define BUSCTRL_PERFSEL1_VALUE_XIP_MAIN0_ACCESS _u(0x3f)
#define BUSCTRL_PERFSEL1_VALUE_ROM_STALL_UPSTREAM _u(0x40)
#define BUSCTRL_PERFSEL1_VALUE_ROM_STALL_DOWNSTREAM _u(0x41)
#define BUSCTRL_PERFSEL1_VALUE_ROM_ACCESS_CONTESTED _u(0x42)
#define BUSCTRL_PERFSEL1_VALUE_ROM_ACCESS _u(0x43)
// =============================================================================
// Register : BUSCTRL_PERFCTR2
// Description : Bus fabric performance counter 2
// Busfabric saturating performance counter 2
// Count some event signal from the busfabric arbiters, if
// PERFCTR_EN is set.
// Write any value to clear. Select an event to count using
// PERFSEL2
#define BUSCTRL_PERFCTR2_OFFSET _u(0x0000001c)
#define BUSCTRL_PERFCTR2_BITS _u(0x00ffffff)
#define BUSCTRL_PERFCTR2_RESET _u(0x00000000)
#define BUSCTRL_PERFCTR2_MSB _u(23)
#define BUSCTRL_PERFCTR2_LSB _u(0)
#define BUSCTRL_PERFCTR2_ACCESS "WC"
// =============================================================================
// Register : BUSCTRL_PERFSEL2
// Description : Bus fabric performance event select for PERFCTR2
// Select an event for PERFCTR2. For each downstream port of the
// main crossbar, four events are available: ACCESS, an access
// took place; ACCESS_CONTESTED, an access took place that
// previously stalled due to contention from other masters;
// STALL_DOWNSTREAM, count cycles where any master stalled due to
// a stall on the downstream bus; STALL_UPSTREAM, count cycles
// where any master stalled for any reason, including contention
// from other masters.
// 0x00 -> siob_proc1_stall_upstream
// 0x01 -> siob_proc1_stall_downstream
// 0x02 -> siob_proc1_access_contested
// 0x03 -> siob_proc1_access
// 0x04 -> siob_proc0_stall_upstream
// 0x05 -> siob_proc0_stall_downstream
// 0x06 -> siob_proc0_access_contested
// 0x07 -> siob_proc0_access
// 0x08 -> apb_stall_upstream
// 0x09 -> apb_stall_downstream
// 0x0a -> apb_access_contested
// 0x0b -> apb_access
// 0x0c -> fastperi_stall_upstream
// 0x0d -> fastperi_stall_downstream
// 0x0e -> fastperi_access_contested
// 0x0f -> fastperi_access
// 0x10 -> sram9_stall_upstream
// 0x11 -> sram9_stall_downstream
// 0x12 -> sram9_access_contested
// 0x13 -> sram9_access
// 0x14 -> sram8_stall_upstream
// 0x15 -> sram8_stall_downstream
// 0x16 -> sram8_access_contested
// 0x17 -> sram8_access
// 0x18 -> sram7_stall_upstream
// 0x19 -> sram7_stall_downstream
// 0x1a -> sram7_access_contested
// 0x1b -> sram7_access
// 0x1c -> sram6_stall_upstream
// 0x1d -> sram6_stall_downstream
// 0x1e -> sram6_access_contested
// 0x1f -> sram6_access
// 0x20 -> sram5_stall_upstream
// 0x21 -> sram5_stall_downstream
// 0x22 -> sram5_access_contested
// 0x23 -> sram5_access
// 0x24 -> sram4_stall_upstream
// 0x25 -> sram4_stall_downstream
// 0x26 -> sram4_access_contested
// 0x27 -> sram4_access
// 0x28 -> sram3_stall_upstream
// 0x29 -> sram3_stall_downstream
// 0x2a -> sram3_access_contested
// 0x2b -> sram3_access
// 0x2c -> sram2_stall_upstream
// 0x2d -> sram2_stall_downstream
// 0x2e -> sram2_access_contested
// 0x2f -> sram2_access
// 0x30 -> sram1_stall_upstream
// 0x31 -> sram1_stall_downstream
// 0x32 -> sram1_access_contested
// 0x33 -> sram1_access
// 0x34 -> sram0_stall_upstream
// 0x35 -> sram0_stall_downstream
// 0x36 -> sram0_access_contested
// 0x37 -> sram0_access
// 0x38 -> xip_main1_stall_upstream
// 0x39 -> xip_main1_stall_downstream
// 0x3a -> xip_main1_access_contested
// 0x3b -> xip_main1_access
// 0x3c -> xip_main0_stall_upstream
// 0x3d -> xip_main0_stall_downstream
// 0x3e -> xip_main0_access_contested
// 0x3f -> xip_main0_access
// 0x40 -> rom_stall_upstream
// 0x41 -> rom_stall_downstream
// 0x42 -> rom_access_contested
// 0x43 -> rom_access
#define BUSCTRL_PERFSEL2_OFFSET _u(0x00000020)
#define BUSCTRL_PERFSEL2_BITS _u(0x0000007f)
#define BUSCTRL_PERFSEL2_RESET _u(0x0000001f)
#define BUSCTRL_PERFSEL2_MSB _u(6)
#define BUSCTRL_PERFSEL2_LSB _u(0)
#define BUSCTRL_PERFSEL2_ACCESS "RW"
#define BUSCTRL_PERFSEL2_VALUE_SIOB_PROC1_STALL_UPSTREAM _u(0x00)
#define BUSCTRL_PERFSEL2_VALUE_SIOB_PROC1_STALL_DOWNSTREAM _u(0x01)
#define BUSCTRL_PERFSEL2_VALUE_SIOB_PROC1_ACCESS_CONTESTED _u(0x02)
#define BUSCTRL_PERFSEL2_VALUE_SIOB_PROC1_ACCESS _u(0x03)
#define BUSCTRL_PERFSEL2_VALUE_SIOB_PROC0_STALL_UPSTREAM _u(0x04)
#define BUSCTRL_PERFSEL2_VALUE_SIOB_PROC0_STALL_DOWNSTREAM _u(0x05)
#define BUSCTRL_PERFSEL2_VALUE_SIOB_PROC0_ACCESS_CONTESTED _u(0x06)
#define BUSCTRL_PERFSEL2_VALUE_SIOB_PROC0_ACCESS _u(0x07)
#define BUSCTRL_PERFSEL2_VALUE_APB_STALL_UPSTREAM _u(0x08)
#define BUSCTRL_PERFSEL2_VALUE_APB_STALL_DOWNSTREAM _u(0x09)
#define BUSCTRL_PERFSEL2_VALUE_APB_ACCESS_CONTESTED _u(0x0a)
#define BUSCTRL_PERFSEL2_VALUE_APB_ACCESS _u(0x0b)
#define BUSCTRL_PERFSEL2_VALUE_FASTPERI_STALL_UPSTREAM _u(0x0c)
#define BUSCTRL_PERFSEL2_VALUE_FASTPERI_STALL_DOWNSTREAM _u(0x0d)
#define BUSCTRL_PERFSEL2_VALUE_FASTPERI_ACCESS_CONTESTED _u(0x0e)
#define BUSCTRL_PERFSEL2_VALUE_FASTPERI_ACCESS _u(0x0f)
#define BUSCTRL_PERFSEL2_VALUE_SRAM9_STALL_UPSTREAM _u(0x10)
#define BUSCTRL_PERFSEL2_VALUE_SRAM9_STALL_DOWNSTREAM _u(0x11)
#define BUSCTRL_PERFSEL2_VALUE_SRAM9_ACCESS_CONTESTED _u(0x12)
#define BUSCTRL_PERFSEL2_VALUE_SRAM9_ACCESS _u(0x13)
#define BUSCTRL_PERFSEL2_VALUE_SRAM8_STALL_UPSTREAM _u(0x14)
#define BUSCTRL_PERFSEL2_VALUE_SRAM8_STALL_DOWNSTREAM _u(0x15)
#define BUSCTRL_PERFSEL2_VALUE_SRAM8_ACCESS_CONTESTED _u(0x16)
#define BUSCTRL_PERFSEL2_VALUE_SRAM8_ACCESS _u(0x17)
#define BUSCTRL_PERFSEL2_VALUE_SRAM7_STALL_UPSTREAM _u(0x18)
#define BUSCTRL_PERFSEL2_VALUE_SRAM7_STALL_DOWNSTREAM _u(0x19)
#define BUSCTRL_PERFSEL2_VALUE_SRAM7_ACCESS_CONTESTED _u(0x1a)
#define BUSCTRL_PERFSEL2_VALUE_SRAM7_ACCESS _u(0x1b)
#define BUSCTRL_PERFSEL2_VALUE_SRAM6_STALL_UPSTREAM _u(0x1c)
#define BUSCTRL_PERFSEL2_VALUE_SRAM6_STALL_DOWNSTREAM _u(0x1d)
#define BUSCTRL_PERFSEL2_VALUE_SRAM6_ACCESS_CONTESTED _u(0x1e)
#define BUSCTRL_PERFSEL2_VALUE_SRAM6_ACCESS _u(0x1f)
#define BUSCTRL_PERFSEL2_VALUE_SRAM5_STALL_UPSTREAM _u(0x20)
#define BUSCTRL_PERFSEL2_VALUE_SRAM5_STALL_DOWNSTREAM _u(0x21)
#define BUSCTRL_PERFSEL2_VALUE_SRAM5_ACCESS_CONTESTED _u(0x22)
#define BUSCTRL_PERFSEL2_VALUE_SRAM5_ACCESS _u(0x23)
#define BUSCTRL_PERFSEL2_VALUE_SRAM4_STALL_UPSTREAM _u(0x24)
#define BUSCTRL_PERFSEL2_VALUE_SRAM4_STALL_DOWNSTREAM _u(0x25)
#define BUSCTRL_PERFSEL2_VALUE_SRAM4_ACCESS_CONTESTED _u(0x26)
#define BUSCTRL_PERFSEL2_VALUE_SRAM4_ACCESS _u(0x27)
#define BUSCTRL_PERFSEL2_VALUE_SRAM3_STALL_UPSTREAM _u(0x28)
#define BUSCTRL_PERFSEL2_VALUE_SRAM3_STALL_DOWNSTREAM _u(0x29)
#define BUSCTRL_PERFSEL2_VALUE_SRAM3_ACCESS_CONTESTED _u(0x2a)
#define BUSCTRL_PERFSEL2_VALUE_SRAM3_ACCESS _u(0x2b)
#define BUSCTRL_PERFSEL2_VALUE_SRAM2_STALL_UPSTREAM _u(0x2c)
#define BUSCTRL_PERFSEL2_VALUE_SRAM2_STALL_DOWNSTREAM _u(0x2d)
#define BUSCTRL_PERFSEL2_VALUE_SRAM2_ACCESS_CONTESTED _u(0x2e)
#define BUSCTRL_PERFSEL2_VALUE_SRAM2_ACCESS _u(0x2f)
#define BUSCTRL_PERFSEL2_VALUE_SRAM1_STALL_UPSTREAM _u(0x30)
#define BUSCTRL_PERFSEL2_VALUE_SRAM1_STALL_DOWNSTREAM _u(0x31)
#define BUSCTRL_PERFSEL2_VALUE_SRAM1_ACCESS_CONTESTED _u(0x32)
#define BUSCTRL_PERFSEL2_VALUE_SRAM1_ACCESS _u(0x33)
#define BUSCTRL_PERFSEL2_VALUE_SRAM0_STALL_UPSTREAM _u(0x34)
#define BUSCTRL_PERFSEL2_VALUE_SRAM0_STALL_DOWNSTREAM _u(0x35)
#define BUSCTRL_PERFSEL2_VALUE_SRAM0_ACCESS_CONTESTED _u(0x36)
#define BUSCTRL_PERFSEL2_VALUE_SRAM0_ACCESS _u(0x37)
#define BUSCTRL_PERFSEL2_VALUE_XIP_MAIN1_STALL_UPSTREAM _u(0x38)
#define BUSCTRL_PERFSEL2_VALUE_XIP_MAIN1_STALL_DOWNSTREAM _u(0x39)
#define BUSCTRL_PERFSEL2_VALUE_XIP_MAIN1_ACCESS_CONTESTED _u(0x3a)
#define BUSCTRL_PERFSEL2_VALUE_XIP_MAIN1_ACCESS _u(0x3b)
#define BUSCTRL_PERFSEL2_VALUE_XIP_MAIN0_STALL_UPSTREAM _u(0x3c)
#define BUSCTRL_PERFSEL2_VALUE_XIP_MAIN0_STALL_DOWNSTREAM _u(0x3d)
#define BUSCTRL_PERFSEL2_VALUE_XIP_MAIN0_ACCESS_CONTESTED _u(0x3e)
#define BUSCTRL_PERFSEL2_VALUE_XIP_MAIN0_ACCESS _u(0x3f)
#define BUSCTRL_PERFSEL2_VALUE_ROM_STALL_UPSTREAM _u(0x40)
#define BUSCTRL_PERFSEL2_VALUE_ROM_STALL_DOWNSTREAM _u(0x41)
#define BUSCTRL_PERFSEL2_VALUE_ROM_ACCESS_CONTESTED _u(0x42)
#define BUSCTRL_PERFSEL2_VALUE_ROM_ACCESS _u(0x43)
// =============================================================================
// Register : BUSCTRL_PERFCTR3
// Description : Bus fabric performance counter 3
// Busfabric saturating performance counter 3
// Count some event signal from the busfabric arbiters, if
// PERFCTR_EN is set.
// Write any value to clear. Select an event to count using
// PERFSEL3
#define BUSCTRL_PERFCTR3_OFFSET _u(0x00000024)
#define BUSCTRL_PERFCTR3_BITS _u(0x00ffffff)
#define BUSCTRL_PERFCTR3_RESET _u(0x00000000)
#define BUSCTRL_PERFCTR3_MSB _u(23)
#define BUSCTRL_PERFCTR3_LSB _u(0)
#define BUSCTRL_PERFCTR3_ACCESS "WC"
// =============================================================================
// Register : BUSCTRL_PERFSEL3
// Description : Bus fabric performance event select for PERFCTR3
// Select an event for PERFCTR3. For each downstream port of the
// main crossbar, four events are available: ACCESS, an access
// took place; ACCESS_CONTESTED, an access took place that
// previously stalled due to contention from other masters;
// STALL_DOWNSTREAM, count cycles where any master stalled due to
// a stall on the downstream bus; STALL_UPSTREAM, count cycles
// where any master stalled for any reason, including contention
// from other masters.
// 0x00 -> siob_proc1_stall_upstream
// 0x01 -> siob_proc1_stall_downstream
// 0x02 -> siob_proc1_access_contested
// 0x03 -> siob_proc1_access
// 0x04 -> siob_proc0_stall_upstream
// 0x05 -> siob_proc0_stall_downstream
// 0x06 -> siob_proc0_access_contested
// 0x07 -> siob_proc0_access
// 0x08 -> apb_stall_upstream
// 0x09 -> apb_stall_downstream
// 0x0a -> apb_access_contested
// 0x0b -> apb_access
// 0x0c -> fastperi_stall_upstream
// 0x0d -> fastperi_stall_downstream
// 0x0e -> fastperi_access_contested
// 0x0f -> fastperi_access
// 0x10 -> sram9_stall_upstream
// 0x11 -> sram9_stall_downstream
// 0x12 -> sram9_access_contested
// 0x13 -> sram9_access
// 0x14 -> sram8_stall_upstream
// 0x15 -> sram8_stall_downstream
// 0x16 -> sram8_access_contested
// 0x17 -> sram8_access
// 0x18 -> sram7_stall_upstream
// 0x19 -> sram7_stall_downstream
// 0x1a -> sram7_access_contested
// 0x1b -> sram7_access
// 0x1c -> sram6_stall_upstream
// 0x1d -> sram6_stall_downstream
// 0x1e -> sram6_access_contested
// 0x1f -> sram6_access
// 0x20 -> sram5_stall_upstream
// 0x21 -> sram5_stall_downstream
// 0x22 -> sram5_access_contested
// 0x23 -> sram5_access
// 0x24 -> sram4_stall_upstream
// 0x25 -> sram4_stall_downstream
// 0x26 -> sram4_access_contested
// 0x27 -> sram4_access
// 0x28 -> sram3_stall_upstream
// 0x29 -> sram3_stall_downstream
// 0x2a -> sram3_access_contested
// 0x2b -> sram3_access
// 0x2c -> sram2_stall_upstream
// 0x2d -> sram2_stall_downstream
// 0x2e -> sram2_access_contested
// 0x2f -> sram2_access
// 0x30 -> sram1_stall_upstream
// 0x31 -> sram1_stall_downstream
// 0x32 -> sram1_access_contested
// 0x33 -> sram1_access
// 0x34 -> sram0_stall_upstream
// 0x35 -> sram0_stall_downstream
// 0x36 -> sram0_access_contested
// 0x37 -> sram0_access
// 0x38 -> xip_main1_stall_upstream
// 0x39 -> xip_main1_stall_downstream
// 0x3a -> xip_main1_access_contested
// 0x3b -> xip_main1_access
// 0x3c -> xip_main0_stall_upstream
// 0x3d -> xip_main0_stall_downstream
// 0x3e -> xip_main0_access_contested
// 0x3f -> xip_main0_access
// 0x40 -> rom_stall_upstream
// 0x41 -> rom_stall_downstream
// 0x42 -> rom_access_contested
// 0x43 -> rom_access
#define BUSCTRL_PERFSEL3_OFFSET _u(0x00000028)
#define BUSCTRL_PERFSEL3_BITS _u(0x0000007f)
#define BUSCTRL_PERFSEL3_RESET _u(0x0000001f)
#define BUSCTRL_PERFSEL3_MSB _u(6)
#define BUSCTRL_PERFSEL3_LSB _u(0)
#define BUSCTRL_PERFSEL3_ACCESS "RW"
#define BUSCTRL_PERFSEL3_VALUE_SIOB_PROC1_STALL_UPSTREAM _u(0x00)
#define BUSCTRL_PERFSEL3_VALUE_SIOB_PROC1_STALL_DOWNSTREAM _u(0x01)
#define BUSCTRL_PERFSEL3_VALUE_SIOB_PROC1_ACCESS_CONTESTED _u(0x02)
#define BUSCTRL_PERFSEL3_VALUE_SIOB_PROC1_ACCESS _u(0x03)
#define BUSCTRL_PERFSEL3_VALUE_SIOB_PROC0_STALL_UPSTREAM _u(0x04)
#define BUSCTRL_PERFSEL3_VALUE_SIOB_PROC0_STALL_DOWNSTREAM _u(0x05)
#define BUSCTRL_PERFSEL3_VALUE_SIOB_PROC0_ACCESS_CONTESTED _u(0x06)
#define BUSCTRL_PERFSEL3_VALUE_SIOB_PROC0_ACCESS _u(0x07)
#define BUSCTRL_PERFSEL3_VALUE_APB_STALL_UPSTREAM _u(0x08)
#define BUSCTRL_PERFSEL3_VALUE_APB_STALL_DOWNSTREAM _u(0x09)
#define BUSCTRL_PERFSEL3_VALUE_APB_ACCESS_CONTESTED _u(0x0a)
#define BUSCTRL_PERFSEL3_VALUE_APB_ACCESS _u(0x0b)
#define BUSCTRL_PERFSEL3_VALUE_FASTPERI_STALL_UPSTREAM _u(0x0c)
#define BUSCTRL_PERFSEL3_VALUE_FASTPERI_STALL_DOWNSTREAM _u(0x0d)
#define BUSCTRL_PERFSEL3_VALUE_FASTPERI_ACCESS_CONTESTED _u(0x0e)
#define BUSCTRL_PERFSEL3_VALUE_FASTPERI_ACCESS _u(0x0f)
#define BUSCTRL_PERFSEL3_VALUE_SRAM9_STALL_UPSTREAM _u(0x10)
#define BUSCTRL_PERFSEL3_VALUE_SRAM9_STALL_DOWNSTREAM _u(0x11)
#define BUSCTRL_PERFSEL3_VALUE_SRAM9_ACCESS_CONTESTED _u(0x12)
#define BUSCTRL_PERFSEL3_VALUE_SRAM9_ACCESS _u(0x13)
#define BUSCTRL_PERFSEL3_VALUE_SRAM8_STALL_UPSTREAM _u(0x14)
#define BUSCTRL_PERFSEL3_VALUE_SRAM8_STALL_DOWNSTREAM _u(0x15)
#define BUSCTRL_PERFSEL3_VALUE_SRAM8_ACCESS_CONTESTED _u(0x16)
#define BUSCTRL_PERFSEL3_VALUE_SRAM8_ACCESS _u(0x17)
#define BUSCTRL_PERFSEL3_VALUE_SRAM7_STALL_UPSTREAM _u(0x18)
#define BUSCTRL_PERFSEL3_VALUE_SRAM7_STALL_DOWNSTREAM _u(0x19)
#define BUSCTRL_PERFSEL3_VALUE_SRAM7_ACCESS_CONTESTED _u(0x1a)
#define BUSCTRL_PERFSEL3_VALUE_SRAM7_ACCESS _u(0x1b)
#define BUSCTRL_PERFSEL3_VALUE_SRAM6_STALL_UPSTREAM _u(0x1c)
#define BUSCTRL_PERFSEL3_VALUE_SRAM6_STALL_DOWNSTREAM _u(0x1d)
#define BUSCTRL_PERFSEL3_VALUE_SRAM6_ACCESS_CONTESTED _u(0x1e)
#define BUSCTRL_PERFSEL3_VALUE_SRAM6_ACCESS _u(0x1f)
#define BUSCTRL_PERFSEL3_VALUE_SRAM5_STALL_UPSTREAM _u(0x20)
#define BUSCTRL_PERFSEL3_VALUE_SRAM5_STALL_DOWNSTREAM _u(0x21)
#define BUSCTRL_PERFSEL3_VALUE_SRAM5_ACCESS_CONTESTED _u(0x22)
#define BUSCTRL_PERFSEL3_VALUE_SRAM5_ACCESS _u(0x23)
#define BUSCTRL_PERFSEL3_VALUE_SRAM4_STALL_UPSTREAM _u(0x24)
#define BUSCTRL_PERFSEL3_VALUE_SRAM4_STALL_DOWNSTREAM _u(0x25)
#define BUSCTRL_PERFSEL3_VALUE_SRAM4_ACCESS_CONTESTED _u(0x26)
#define BUSCTRL_PERFSEL3_VALUE_SRAM4_ACCESS _u(0x27)
#define BUSCTRL_PERFSEL3_VALUE_SRAM3_STALL_UPSTREAM _u(0x28)
#define BUSCTRL_PERFSEL3_VALUE_SRAM3_STALL_DOWNSTREAM _u(0x29)
#define BUSCTRL_PERFSEL3_VALUE_SRAM3_ACCESS_CONTESTED _u(0x2a)
#define BUSCTRL_PERFSEL3_VALUE_SRAM3_ACCESS _u(0x2b)
#define BUSCTRL_PERFSEL3_VALUE_SRAM2_STALL_UPSTREAM _u(0x2c)
#define BUSCTRL_PERFSEL3_VALUE_SRAM2_STALL_DOWNSTREAM _u(0x2d)
#define BUSCTRL_PERFSEL3_VALUE_SRAM2_ACCESS_CONTESTED _u(0x2e)
#define BUSCTRL_PERFSEL3_VALUE_SRAM2_ACCESS _u(0x2f)
#define BUSCTRL_PERFSEL3_VALUE_SRAM1_STALL_UPSTREAM _u(0x30)
#define BUSCTRL_PERFSEL3_VALUE_SRAM1_STALL_DOWNSTREAM _u(0x31)
#define BUSCTRL_PERFSEL3_VALUE_SRAM1_ACCESS_CONTESTED _u(0x32)
#define BUSCTRL_PERFSEL3_VALUE_SRAM1_ACCESS _u(0x33)
#define BUSCTRL_PERFSEL3_VALUE_SRAM0_STALL_UPSTREAM _u(0x34)
#define BUSCTRL_PERFSEL3_VALUE_SRAM0_STALL_DOWNSTREAM _u(0x35)
#define BUSCTRL_PERFSEL3_VALUE_SRAM0_ACCESS_CONTESTED _u(0x36)
#define BUSCTRL_PERFSEL3_VALUE_SRAM0_ACCESS _u(0x37)
#define BUSCTRL_PERFSEL3_VALUE_XIP_MAIN1_STALL_UPSTREAM _u(0x38)
#define BUSCTRL_PERFSEL3_VALUE_XIP_MAIN1_STALL_DOWNSTREAM _u(0x39)
#define BUSCTRL_PERFSEL3_VALUE_XIP_MAIN1_ACCESS_CONTESTED _u(0x3a)
#define BUSCTRL_PERFSEL3_VALUE_XIP_MAIN1_ACCESS _u(0x3b)
#define BUSCTRL_PERFSEL3_VALUE_XIP_MAIN0_STALL_UPSTREAM _u(0x3c)
#define BUSCTRL_PERFSEL3_VALUE_XIP_MAIN0_STALL_DOWNSTREAM _u(0x3d)
#define BUSCTRL_PERFSEL3_VALUE_XIP_MAIN0_ACCESS_CONTESTED _u(0x3e)
#define BUSCTRL_PERFSEL3_VALUE_XIP_MAIN0_ACCESS _u(0x3f)
#define BUSCTRL_PERFSEL3_VALUE_ROM_STALL_UPSTREAM _u(0x40)
#define BUSCTRL_PERFSEL3_VALUE_ROM_STALL_DOWNSTREAM _u(0x41)
#define BUSCTRL_PERFSEL3_VALUE_ROM_ACCESS_CONTESTED _u(0x42)
#define BUSCTRL_PERFSEL3_VALUE_ROM_ACCESS _u(0x43)
// =============================================================================
#endif // _HARDWARE_REGS_BUSCTRL_H

2764
arch/arm/src/rp23xx/hardware/regs/clocks.h
View file

File diff suppressed because it is too large Load diff

85
arch/arm/src/rp23xx/hardware/regs/coresight_trace.h
View file

@ -1,85 +0,0 @@
// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
// =============================================================================
// Register block : CORESIGHT_TRACE
// Version : 1
// Bus type : ahbl
// Description : Coresight block - RP specific registers
// =============================================================================
#ifndef _HARDWARE_REGS_CORESIGHT_TRACE_H
#define _HARDWARE_REGS_CORESIGHT_TRACE_H
// =============================================================================
// Register : CORESIGHT_TRACE_CTRL_STATUS
// Description : Control and status register
#define CORESIGHT_TRACE_CTRL_STATUS_OFFSET _u(0x00000000)
#define CORESIGHT_TRACE_CTRL_STATUS_BITS _u(0x00000003)
#define CORESIGHT_TRACE_CTRL_STATUS_RESET _u(0x00000001)
// -----------------------------------------------------------------------------
// Field : CORESIGHT_TRACE_CTRL_STATUS_TRACE_CAPTURE_FIFO_OVERFLOW
// Description : This status flag is set high when trace data has been dropped
// due to the FIFO being full at the point trace data was sampled.
// Write 1 to acknowledge and clear the bit.
#define CORESIGHT_TRACE_CTRL_STATUS_TRACE_CAPTURE_FIFO_OVERFLOW_RESET _u(0x0)
#define CORESIGHT_TRACE_CTRL_STATUS_TRACE_CAPTURE_FIFO_OVERFLOW_BITS _u(0x00000002)
#define CORESIGHT_TRACE_CTRL_STATUS_TRACE_CAPTURE_FIFO_OVERFLOW_MSB _u(1)
#define CORESIGHT_TRACE_CTRL_STATUS_TRACE_CAPTURE_FIFO_OVERFLOW_LSB _u(1)
#define CORESIGHT_TRACE_CTRL_STATUS_TRACE_CAPTURE_FIFO_OVERFLOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : CORESIGHT_TRACE_CTRL_STATUS_TRACE_CAPTURE_FIFO_FLUSH
// Description : Set to 1 to continuously hold the trace FIFO in a flushed state
// and prevent overflow.
//
// Before clearing this flag, configure and start a DMA channel
// with the correct DREQ for the TRACE_CAPTURE_FIFO register.
//
// Clear this flag to begin sampling trace data, and set once
// again once the trace capture buffer is full. You must configure
// the TPIU in order to generate trace packets to be captured, as
// well as components like the ETM further upstream to generate
// the event stream propagated to the TPIU.
#define CORESIGHT_TRACE_CTRL_STATUS_TRACE_CAPTURE_FIFO_FLUSH_RESET _u(0x1)
#define CORESIGHT_TRACE_CTRL_STATUS_TRACE_CAPTURE_FIFO_FLUSH_BITS _u(0x00000001)
#define CORESIGHT_TRACE_CTRL_STATUS_TRACE_CAPTURE_FIFO_FLUSH_MSB _u(0)
#define CORESIGHT_TRACE_CTRL_STATUS_TRACE_CAPTURE_FIFO_FLUSH_LSB _u(0)
#define CORESIGHT_TRACE_CTRL_STATUS_TRACE_CAPTURE_FIFO_FLUSH_ACCESS "RW"
// =============================================================================
// Register : CORESIGHT_TRACE_TRACE_CAPTURE_FIFO
// Description : FIFO for trace data captured from the TPIU
#define CORESIGHT_TRACE_TRACE_CAPTURE_FIFO_OFFSET _u(0x00000004)
#define CORESIGHT_TRACE_TRACE_CAPTURE_FIFO_BITS _u(0xffffffff)
#define CORESIGHT_TRACE_TRACE_CAPTURE_FIFO_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : CORESIGHT_TRACE_TRACE_CAPTURE_FIFO_RDATA
// Description : Read from an 8 x 32-bit FIFO containing trace data captured
// from the TPIU.
//
// Hardware pushes to the FIFO on rising edges of clk_sys, when
// either of the following is true:
//
// * TPIU TRACECTL output is low (normal trace data)
//
// * TPIU TRACETCL output is high, and TPIU TRACEDATA0 and
// TRACEDATA1 are both low (trigger packet)
//
// These conditions are in accordance with Arm Coresight
// Architecture Spec v3.0 section D3.3.3: Decoding requirements
// for Trace Capture Devices
//
// The data captured into the FIFO is the full 32-bit TRACEDATA
// bus output by the TPIU. Note that the TPIU is a DDR output at
// half of clk_sys, therefore this interface can capture the full
// 32-bit TPIU DDR output bandwidth as it samples once per active
// edge of the TPIU output clock.
#define CORESIGHT_TRACE_TRACE_CAPTURE_FIFO_RDATA_RESET _u(0x00000000)
#define CORESIGHT_TRACE_TRACE_CAPTURE_FIFO_RDATA_BITS _u(0xffffffff)
#define CORESIGHT_TRACE_TRACE_CAPTURE_FIFO_RDATA_MSB _u(31)
#define CORESIGHT_TRACE_TRACE_CAPTURE_FIFO_RDATA_LSB _u(0)
#define CORESIGHT_TRACE_TRACE_CAPTURE_FIFO_RDATA_ACCESS "RF"
// =============================================================================
#endif // _HARDWARE_REGS_CORESIGHT_TRACE_H

9914
arch/arm/src/rp23xx/hardware/regs/dma.h
View file

File diff suppressed because it is too large Load diff

147
arch/arm/src/rp23xx/hardware/regs/dreq.h
View file

@ -1,147 +0,0 @@
// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _DREQ_H
#define _DREQ_H
/**
* \file rp2350/dreq.h
*/
#ifdef __ASSEMBLER__
#define DREQ_PIO0_TX0 0
#define DREQ_PIO0_TX1 1
#define DREQ_PIO0_TX2 2
#define DREQ_PIO0_TX3 3
#define DREQ_PIO0_RX0 4
#define DREQ_PIO0_RX1 5
#define DREQ_PIO0_RX2 6
#define DREQ_PIO0_RX3 7
#define DREQ_PIO1_TX0 8
#define DREQ_PIO1_TX1 9
#define DREQ_PIO1_TX2 10
#define DREQ_PIO1_TX3 11
#define DREQ_PIO1_RX0 12
#define DREQ_PIO1_RX1 13
#define DREQ_PIO1_RX2 14
#define DREQ_PIO1_RX3 15
#define DREQ_PIO2_TX0 16
#define DREQ_PIO2_TX1 17
#define DREQ_PIO2_TX2 18
#define DREQ_PIO2_TX3 19
#define DREQ_PIO2_RX0 20
#define DREQ_PIO2_RX1 21
#define DREQ_PIO2_RX2 22
#define DREQ_PIO2_RX3 23
#define DREQ_SPI0_TX 24
#define DREQ_SPI0_RX 25
#define DREQ_SPI1_TX 26
#define DREQ_SPI1_RX 27
#define DREQ_UART0_TX 28
#define DREQ_UART0_RX 29
#define DREQ_UART1_TX 30
#define DREQ_UART1_RX 31
#define DREQ_PWM_WRAP0 32
#define DREQ_PWM_WRAP1 33
#define DREQ_PWM_WRAP2 34
#define DREQ_PWM_WRAP3 35
#define DREQ_PWM_WRAP4 36
#define DREQ_PWM_WRAP5 37
#define DREQ_PWM_WRAP6 38
#define DREQ_PWM_WRAP7 39
#define DREQ_PWM_WRAP8 40
#define DREQ_PWM_WRAP9 41
#define DREQ_PWM_WRAP10 42
#define DREQ_PWM_WRAP11 43
#define DREQ_I2C0_TX 44
#define DREQ_I2C0_RX 45
#define DREQ_I2C1_TX 46
#define DREQ_I2C1_RX 47
#define DREQ_ADC 48
#define DREQ_XIP_STREAM 49
#define DREQ_XIP_QMITX 50
#define DREQ_XIP_QMIRX 51
#define DREQ_HSTX 52
#define DREQ_CORESIGHT 53
#define DREQ_SHA256 54
#define DREQ_DMA_TIMER0 59
#define DREQ_DMA_TIMER1 60
#define DREQ_DMA_TIMER2 61
#define DREQ_DMA_TIMER3 62
#define DREQ_FORCE 63
#else
/**
* \brief DREQ numbers for DMA pacing on RP2350 (used as typedef \ref dreq_num_t)
* \ingroup hardware_dma
*/
typedef enum dreq_num_rp2350 {
DREQ_PIO0_TX0 = 0, ///< Select PIO0's TX FIFO 0 as DREQ
DREQ_PIO0_TX1 = 1, ///< Select PIO0's TX FIFO 1 as DREQ
DREQ_PIO0_TX2 = 2, ///< Select PIO0's TX FIFO 2 as DREQ
DREQ_PIO0_TX3 = 3, ///< Select PIO0's TX FIFO 3 as DREQ
DREQ_PIO0_RX0 = 4, ///< Select PIO0's RX FIFO 0 as DREQ
DREQ_PIO0_RX1 = 5, ///< Select PIO0's RX FIFO 1 as DREQ
DREQ_PIO0_RX2 = 6, ///< Select PIO0's RX FIFO 2 as DREQ
DREQ_PIO0_RX3 = 7, ///< Select PIO0's RX FIFO 3 as DREQ
DREQ_PIO1_TX0 = 8, ///< Select PIO1's TX FIFO 0 as DREQ
DREQ_PIO1_TX1 = 9, ///< Select PIO1's TX FIFO 1 as DREQ
DREQ_PIO1_TX2 = 10, ///< Select PIO1's TX FIFO 2 as DREQ
DREQ_PIO1_TX3 = 11, ///< Select PIO1's TX FIFO 3 as DREQ
DREQ_PIO1_RX0 = 12, ///< Select PIO1's RX FIFO 0 as DREQ
DREQ_PIO1_RX1 = 13, ///< Select PIO1's RX FIFO 1 as DREQ
DREQ_PIO1_RX2 = 14, ///< Select PIO1's RX FIFO 2 as DREQ
DREQ_PIO1_RX3 = 15, ///< Select PIO1's RX FIFO 3 as DREQ
DREQ_PIO2_TX0 = 16, ///< Select PIO2's TX FIFO 0 as DREQ
DREQ_PIO2_TX1 = 17, ///< Select PIO2's TX FIFO 1 as DREQ
DREQ_PIO2_TX2 = 18, ///< Select PIO2's TX FIFO 2 as DREQ
DREQ_PIO2_TX3 = 19, ///< Select PIO2's TX FIFO 3 as DREQ
DREQ_PIO2_RX0 = 20, ///< Select PIO2's RX FIFO 0 as DREQ
DREQ_PIO2_RX1 = 21, ///< Select PIO2's RX FIFO 1 as DREQ
DREQ_PIO2_RX2 = 22, ///< Select PIO2's RX FIFO 2 as DREQ
DREQ_PIO2_RX3 = 23, ///< Select PIO2's RX FIFO 3 as DREQ
DREQ_SPI0_TX = 24, ///< Select SPI0's TX FIFO as DREQ
DREQ_SPI0_RX = 25, ///< Select SPI0's RX FIFO as DREQ
DREQ_SPI1_TX = 26, ///< Select SPI1's TX FIFO as DREQ
DREQ_SPI1_RX = 27, ///< Select SPI1's RX FIFO as DREQ
DREQ_UART0_TX = 28, ///< Select UART0's TX FIFO as DREQ
DREQ_UART0_RX = 29, ///< Select UART0's RX FIFO as DREQ
DREQ_UART1_TX = 30, ///< Select UART1's TX FIFO as DREQ
DREQ_UART1_RX = 31, ///< Select UART1's RX FIFO as DREQ
DREQ_PWM_WRAP0 = 32, ///< Select PWM Counter 0's Wrap Value as DREQ
DREQ_PWM_WRAP1 = 33, ///< Select PWM Counter 1's Wrap Value as DREQ
DREQ_PWM_WRAP2 = 34, ///< Select PWM Counter 2's Wrap Value as DREQ
DREQ_PWM_WRAP3 = 35, ///< Select PWM Counter 3's Wrap Value as DREQ
DREQ_PWM_WRAP4 = 36, ///< Select PWM Counter 4's Wrap Value as DREQ
DREQ_PWM_WRAP5 = 37, ///< Select PWM Counter 5's Wrap Value as DREQ
DREQ_PWM_WRAP6 = 38, ///< Select PWM Counter 6's Wrap Value as DREQ
DREQ_PWM_WRAP7 = 39, ///< Select PWM Counter 7's Wrap Value as DREQ
DREQ_PWM_WRAP8 = 40, ///< Select PWM Counter 8's Wrap Value as DREQ
DREQ_PWM_WRAP9 = 41, ///< Select PWM Counter 9's Wrap Value as DREQ
DREQ_PWM_WRAP10 = 42, ///< Select PWM Counter 0's Wrap Value as DREQ
DREQ_PWM_WRAP11 = 43, ///< Select PWM Counter 1's Wrap Value as DREQ
DREQ_I2C0_TX = 44, ///< Select I2C0's TX FIFO as DREQ
DREQ_I2C0_RX = 45, ///< Select I2C0's RX FIFO as DREQ
DREQ_I2C1_TX = 46, ///< Select I2C1's TX FIFO as DREQ
DREQ_I2C1_RX = 47, ///< Select I2C1's RX FIFO as DREQ
DREQ_ADC = 48, ///< Select the ADC as DREQ
DREQ_XIP_STREAM = 49, ///< Select the XIP Streaming FIFO as DREQ
DREQ_XIP_QMITX = 50, ///< Select XIP_QMITX as DREQ
DREQ_XIP_QMIRX = 51, ///< Select XIP_QMIRX as DREQ
DREQ_HSTX = 52, ///< Select HSTX as DREQ
DREQ_CORESIGHT = 53, ///< Select CORESIGHT as DREQ
DREQ_SHA256 = 54, ///< Select SHA256 as DREQ
DREQ_DMA_TIMER0 = 59, ///< Select DMA_TIMER0 as DREQ
DREQ_DMA_TIMER1 = 60, ///< Select DMA_TIMER0 as DREQ
DREQ_DMA_TIMER2 = 61, ///< Select DMA_TIMER1 as DREQ
DREQ_DMA_TIMER3 = 62, ///< Select DMA_TIMER3 as DREQ
DREQ_FORCE = 63, ///< Select FORCE as DREQ
DREQ_COUNT
} dreq_num_t;
#endif
#endif // _DREQ_H

213
arch/arm/src/rp23xx/hardware/regs/glitch_detector.h
View file

@ -1,213 +0,0 @@
// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
// =============================================================================
// Register block : GLITCH_DETECTOR
// Version : 1
// Bus type : apb
// Description : Glitch detector controls
// =============================================================================
#ifndef _HARDWARE_REGS_GLITCH_DETECTOR_H
#define _HARDWARE_REGS_GLITCH_DETECTOR_H
// =============================================================================
// Register : GLITCH_DETECTOR_ARM
// Description : Forcibly arm the glitch detectors, if they are not already
// armed by OTP. When armed, any individual detector trigger will
// cause a restart of the switched core power domain's power-on
// reset state machine.
//
// Glitch detector triggers are recorded accumulatively in
// TRIG_STATUS. If the system is reset by a glitch detector
// trigger, this is recorded in POWMAN_CHIP_RESET.
//
// This register is Secure read/write only.
// 0x5bad -> Do not force the glitch detectors to be armed
// 0x0000 -> Force the glitch detectors to be armed. (Any value other than ARM_NO counts as YES)
#define GLITCH_DETECTOR_ARM_OFFSET _u(0x00000000)
#define GLITCH_DETECTOR_ARM_BITS _u(0x0000ffff)
#define GLITCH_DETECTOR_ARM_RESET _u(0x00005bad)
#define GLITCH_DETECTOR_ARM_MSB _u(15)
#define GLITCH_DETECTOR_ARM_LSB _u(0)
#define GLITCH_DETECTOR_ARM_ACCESS "RW"
#define GLITCH_DETECTOR_ARM_VALUE_NO _u(0x5bad)
#define GLITCH_DETECTOR_ARM_VALUE_YES _u(0x0000)
// =============================================================================
// Register : GLITCH_DETECTOR_DISARM
// Description : None
// Forcibly disarm the glitch detectors, if they are armed by OTP.
// Ignored if ARM is YES.
//
// This register is Secure read/write only.
// 0x0000 -> Do not disarm the glitch detectors. (Any value other than DISARM_YES counts as NO)
// 0xdcaf -> Disarm the glitch detectors
#define GLITCH_DETECTOR_DISARM_OFFSET _u(0x00000004)
#define GLITCH_DETECTOR_DISARM_BITS _u(0x0000ffff)
#define GLITCH_DETECTOR_DISARM_RESET _u(0x00000000)
#define GLITCH_DETECTOR_DISARM_MSB _u(15)
#define GLITCH_DETECTOR_DISARM_LSB _u(0)
#define GLITCH_DETECTOR_DISARM_ACCESS "RW"
#define GLITCH_DETECTOR_DISARM_VALUE_NO _u(0x0000)
#define GLITCH_DETECTOR_DISARM_VALUE_YES _u(0xdcaf)
// =============================================================================
// Register : GLITCH_DETECTOR_SENSITIVITY
// Description : Adjust the sensitivity of glitch detectors to values other than
// their OTP-provided defaults.
//
// This register is Secure read/write only.
#define GLITCH_DETECTOR_SENSITIVITY_OFFSET _u(0x00000008)
#define GLITCH_DETECTOR_SENSITIVITY_BITS _u(0xff00ffff)
#define GLITCH_DETECTOR_SENSITIVITY_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : GLITCH_DETECTOR_SENSITIVITY_DEFAULT
// 0x00 -> Use the default sensitivity configured in OTP for all detectors. (Any value other than DEFAULT_NO counts as YES)
// 0xde -> Do not use the default sensitivity configured in OTP. Instead use the value from this register.
#define GLITCH_DETECTOR_SENSITIVITY_DEFAULT_RESET _u(0x00)
#define GLITCH_DETECTOR_SENSITIVITY_DEFAULT_BITS _u(0xff000000)
#define GLITCH_DETECTOR_SENSITIVITY_DEFAULT_MSB _u(31)
#define GLITCH_DETECTOR_SENSITIVITY_DEFAULT_LSB _u(24)
#define GLITCH_DETECTOR_SENSITIVITY_DEFAULT_ACCESS "RW"
#define GLITCH_DETECTOR_SENSITIVITY_DEFAULT_VALUE_YES _u(0x00)
#define GLITCH_DETECTOR_SENSITIVITY_DEFAULT_VALUE_NO _u(0xde)
// -----------------------------------------------------------------------------
// Field : GLITCH_DETECTOR_SENSITIVITY_DET3_INV
// Description : Must be the inverse of DET3, else the default value is used.
#define GLITCH_DETECTOR_SENSITIVITY_DET3_INV_RESET _u(0x0)
#define GLITCH_DETECTOR_SENSITIVITY_DET3_INV_BITS _u(0x0000c000)
#define GLITCH_DETECTOR_SENSITIVITY_DET3_INV_MSB _u(15)
#define GLITCH_DETECTOR_SENSITIVITY_DET3_INV_LSB _u(14)
#define GLITCH_DETECTOR_SENSITIVITY_DET3_INV_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : GLITCH_DETECTOR_SENSITIVITY_DET2_INV
// Description : Must be the inverse of DET2, else the default value is used.
#define GLITCH_DETECTOR_SENSITIVITY_DET2_INV_RESET _u(0x0)
#define GLITCH_DETECTOR_SENSITIVITY_DET2_INV_BITS _u(0x00003000)
#define GLITCH_DETECTOR_SENSITIVITY_DET2_INV_MSB _u(13)
#define GLITCH_DETECTOR_SENSITIVITY_DET2_INV_LSB _u(12)
#define GLITCH_DETECTOR_SENSITIVITY_DET2_INV_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : GLITCH_DETECTOR_SENSITIVITY_DET1_INV
// Description : Must be the inverse of DET1, else the default value is used.
#define GLITCH_DETECTOR_SENSITIVITY_DET1_INV_RESET _u(0x0)
#define GLITCH_DETECTOR_SENSITIVITY_DET1_INV_BITS _u(0x00000c00)
#define GLITCH_DETECTOR_SENSITIVITY_DET1_INV_MSB _u(11)
#define GLITCH_DETECTOR_SENSITIVITY_DET1_INV_LSB _u(10)
#define GLITCH_DETECTOR_SENSITIVITY_DET1_INV_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : GLITCH_DETECTOR_SENSITIVITY_DET0_INV
// Description : Must be the inverse of DET0, else the default value is used.
#define GLITCH_DETECTOR_SENSITIVITY_DET0_INV_RESET _u(0x0)
#define GLITCH_DETECTOR_SENSITIVITY_DET0_INV_BITS _u(0x00000300)
#define GLITCH_DETECTOR_SENSITIVITY_DET0_INV_MSB _u(9)
#define GLITCH_DETECTOR_SENSITIVITY_DET0_INV_LSB _u(8)
#define GLITCH_DETECTOR_SENSITIVITY_DET0_INV_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : GLITCH_DETECTOR_SENSITIVITY_DET3
// Description : Set sensitivity for detector 3. Higher values are more
// sensitive.
#define GLITCH_DETECTOR_SENSITIVITY_DET3_RESET _u(0x0)
#define GLITCH_DETECTOR_SENSITIVITY_DET3_BITS _u(0x000000c0)
#define GLITCH_DETECTOR_SENSITIVITY_DET3_MSB _u(7)
#define GLITCH_DETECTOR_SENSITIVITY_DET3_LSB _u(6)
#define GLITCH_DETECTOR_SENSITIVITY_DET3_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : GLITCH_DETECTOR_SENSITIVITY_DET2
// Description : Set sensitivity for detector 2. Higher values are more
// sensitive.
#define GLITCH_DETECTOR_SENSITIVITY_DET2_RESET _u(0x0)
#define GLITCH_DETECTOR_SENSITIVITY_DET2_BITS _u(0x00000030)
#define GLITCH_DETECTOR_SENSITIVITY_DET2_MSB _u(5)
#define GLITCH_DETECTOR_SENSITIVITY_DET2_LSB _u(4)
#define GLITCH_DETECTOR_SENSITIVITY_DET2_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : GLITCH_DETECTOR_SENSITIVITY_DET1
// Description : Set sensitivity for detector 1. Higher values are more
// sensitive.
#define GLITCH_DETECTOR_SENSITIVITY_DET1_RESET _u(0x0)
#define GLITCH_DETECTOR_SENSITIVITY_DET1_BITS _u(0x0000000c)
#define GLITCH_DETECTOR_SENSITIVITY_DET1_MSB _u(3)
#define GLITCH_DETECTOR_SENSITIVITY_DET1_LSB _u(2)
#define GLITCH_DETECTOR_SENSITIVITY_DET1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : GLITCH_DETECTOR_SENSITIVITY_DET0
// Description : Set sensitivity for detector 0. Higher values are more
// sensitive.
#define GLITCH_DETECTOR_SENSITIVITY_DET0_RESET _u(0x0)
#define GLITCH_DETECTOR_SENSITIVITY_DET0_BITS _u(0x00000003)
#define GLITCH_DETECTOR_SENSITIVITY_DET0_MSB _u(1)
#define GLITCH_DETECTOR_SENSITIVITY_DET0_LSB _u(0)
#define GLITCH_DETECTOR_SENSITIVITY_DET0_ACCESS "RW"
// =============================================================================
// Register : GLITCH_DETECTOR_LOCK
// Description : None
// Write any nonzero value to disable writes to ARM, DISARM,
// SENSITIVITY and LOCK. This register is Secure read/write only.
#define GLITCH_DETECTOR_LOCK_OFFSET _u(0x0000000c)
#define GLITCH_DETECTOR_LOCK_BITS _u(0x000000ff)
#define GLITCH_DETECTOR_LOCK_RESET _u(0x00000000)
#define GLITCH_DETECTOR_LOCK_MSB _u(7)
#define GLITCH_DETECTOR_LOCK_LSB _u(0)
#define GLITCH_DETECTOR_LOCK_ACCESS "RW"
// =============================================================================
// Register : GLITCH_DETECTOR_TRIG_STATUS
// Description : Set when a detector output triggers. Write-1-clear.
//
// (May immediately return high if the detector remains in a
// failed state. Detectors can only be cleared by a full reset of
// the switched core power domain.)
//
// This register is Secure read/write only.
#define GLITCH_DETECTOR_TRIG_STATUS_OFFSET _u(0x00000010)
#define GLITCH_DETECTOR_TRIG_STATUS_BITS _u(0x0000000f)
#define GLITCH_DETECTOR_TRIG_STATUS_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : GLITCH_DETECTOR_TRIG_STATUS_DET3
#define GLITCH_DETECTOR_TRIG_STATUS_DET3_RESET _u(0x0)
#define GLITCH_DETECTOR_TRIG_STATUS_DET3_BITS _u(0x00000008)
#define GLITCH_DETECTOR_TRIG_STATUS_DET3_MSB _u(3)
#define GLITCH_DETECTOR_TRIG_STATUS_DET3_LSB _u(3)
#define GLITCH_DETECTOR_TRIG_STATUS_DET3_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : GLITCH_DETECTOR_TRIG_STATUS_DET2
#define GLITCH_DETECTOR_TRIG_STATUS_DET2_RESET _u(0x0)
#define GLITCH_DETECTOR_TRIG_STATUS_DET2_BITS _u(0x00000004)
#define GLITCH_DETECTOR_TRIG_STATUS_DET2_MSB _u(2)
#define GLITCH_DETECTOR_TRIG_STATUS_DET2_LSB _u(2)
#define GLITCH_DETECTOR_TRIG_STATUS_DET2_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : GLITCH_DETECTOR_TRIG_STATUS_DET1
#define GLITCH_DETECTOR_TRIG_STATUS_DET1_RESET _u(0x0)
#define GLITCH_DETECTOR_TRIG_STATUS_DET1_BITS _u(0x00000002)
#define GLITCH_DETECTOR_TRIG_STATUS_DET1_MSB _u(1)
#define GLITCH_DETECTOR_TRIG_STATUS_DET1_LSB _u(1)
#define GLITCH_DETECTOR_TRIG_STATUS_DET1_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : GLITCH_DETECTOR_TRIG_STATUS_DET0
#define GLITCH_DETECTOR_TRIG_STATUS_DET0_RESET _u(0x0)
#define GLITCH_DETECTOR_TRIG_STATUS_DET0_BITS _u(0x00000001)
#define GLITCH_DETECTOR_TRIG_STATUS_DET0_MSB _u(0)
#define GLITCH_DETECTOR_TRIG_STATUS_DET0_LSB _u(0)
#define GLITCH_DETECTOR_TRIG_STATUS_DET0_ACCESS "WC"
// =============================================================================
// Register : GLITCH_DETECTOR_TRIG_FORCE
// Description : Simulate the firing of one or more detectors. Writing ones to
// this register will set the matching bits in STATUS_TRIG.
//
// If the glitch detectors are currently armed, writing ones will
// also immediately reset the switched core power domain, and set
// the reset reason latches in POWMAN_CHIP_RESET to indicate a
// glitch detector resets.
//
// This register is Secure read/write only.
#define GLITCH_DETECTOR_TRIG_FORCE_OFFSET _u(0x00000014)
#define GLITCH_DETECTOR_TRIG_FORCE_BITS _u(0x0000000f)
#define GLITCH_DETECTOR_TRIG_FORCE_RESET _u(0x00000000)
#define GLITCH_DETECTOR_TRIG_FORCE_MSB _u(3)
#define GLITCH_DETECTOR_TRIG_FORCE_LSB _u(0)
#define GLITCH_DETECTOR_TRIG_FORCE_ACCESS "SC"
// =============================================================================
#endif // _HARDWARE_REGS_GLITCH_DETECTOR_H

609
arch/arm/src/rp23xx/hardware/regs/hstx_ctrl.h
View file

@ -1,609 +0,0 @@
// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
// =============================================================================
// Register block : HSTX_CTRL
// Version : 0
// Bus type : apb
// Description : Control interface to HSTX. For FIFO write access and status,
// see the HSTX_FIFO register block.
// =============================================================================
#ifndef _HARDWARE_REGS_HSTX_CTRL_H
#define _HARDWARE_REGS_HSTX_CTRL_H
// =============================================================================
// Register : HSTX_CTRL_CSR
#define HSTX_CTRL_CSR_OFFSET _u(0x00000000)
#define HSTX_CTRL_CSR_BITS _u(0xff1f1f73)
#define HSTX_CTRL_CSR_RESET _u(0x10050600)
// -----------------------------------------------------------------------------
// Field : HSTX_CTRL_CSR_CLKDIV
// Description : Clock period of the generated clock, measured in HSTX clock
// cycles. Can be odd or even. The generated clock advances only
// on cycles where the shift register shifts.
//
// For example, a clkdiv of 5 would generate a complete output
// clock period for every 5 HSTX clocks (or every 10 half-clocks).
//
// A CLKDIV value of 0 is mapped to a period of 16 HSTX clock
// cycles.
#define HSTX_CTRL_CSR_CLKDIV_RESET _u(0x1)
#define HSTX_CTRL_CSR_CLKDIV_BITS _u(0xf0000000)
#define HSTX_CTRL_CSR_CLKDIV_MSB _u(31)
#define HSTX_CTRL_CSR_CLKDIV_LSB _u(28)
#define HSTX_CTRL_CSR_CLKDIV_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : HSTX_CTRL_CSR_CLKPHASE
// Description : Set the initial phase of the generated clock.
//
// A CLKPHASE of 0 means the clock is initially low, and the first
// rising edge occurs after one half period of the generated clock
// (i.e. CLKDIV/2 cycles of clk_hstx). Incrementing CLKPHASE by 1
// will advance the initial clock phase by one half clk_hstx
// period. For example, if CLKDIV=2 and CLKPHASE=1:
//
// * The clock will be initially low
//
// * The first rising edge will be 0.5 clk_hstx cycles after
// asserting first data
//
// * The first falling edge will be 1.5 clk_hstx cycles after
// asserting first data
//
// This configuration would be suitable for serialising at a bit
// rate of clk_hstx with a centre-aligned DDR clock.
//
// When the HSTX is halted by clearing CSR_EN, the clock generator
// will return to its initial phase as configured by the CLKPHASE
// field.
//
// Note CLKPHASE must be strictly less than double the value of
// CLKDIV (one full period), else its operation is undefined.
#define HSTX_CTRL_CSR_CLKPHASE_RESET _u(0x0)
#define HSTX_CTRL_CSR_CLKPHASE_BITS _u(0x0f000000)
#define HSTX_CTRL_CSR_CLKPHASE_MSB _u(27)
#define HSTX_CTRL_CSR_CLKPHASE_LSB _u(24)
#define HSTX_CTRL_CSR_CLKPHASE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : HSTX_CTRL_CSR_N_SHIFTS
// Description : Number of times to shift the shift register before refilling it
// from the FIFO. (A count of how many times it has been shifted,
// *not* the total shift distance.)
//
// A register value of 0 means shift 32 times.
#define HSTX_CTRL_CSR_N_SHIFTS_RESET _u(0x05)
#define HSTX_CTRL_CSR_N_SHIFTS_BITS _u(0x001f0000)
#define HSTX_CTRL_CSR_N_SHIFTS_MSB _u(20)
#define HSTX_CTRL_CSR_N_SHIFTS_LSB _u(16)
#define HSTX_CTRL_CSR_N_SHIFTS_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : HSTX_CTRL_CSR_SHIFT
// Description : How many bits to right-rotate the shift register by each cycle.
//
// The use of a rotate rather than a shift allows left shifts to
// be emulated, by subtracting the left-shift amount from 32. It
// also allows data to be repeated, when the product of SHIFT and
// N_SHIFTS is greater than 32.
#define HSTX_CTRL_CSR_SHIFT_RESET _u(0x06)
#define HSTX_CTRL_CSR_SHIFT_BITS _u(0x00001f00)
#define HSTX_CTRL_CSR_SHIFT_MSB _u(12)
#define HSTX_CTRL_CSR_SHIFT_LSB _u(8)
#define HSTX_CTRL_CSR_SHIFT_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : HSTX_CTRL_CSR_COUPLED_SEL
// Description : Select which PIO to use for coupled mode operation.
#define HSTX_CTRL_CSR_COUPLED_SEL_RESET _u(0x0)
#define HSTX_CTRL_CSR_COUPLED_SEL_BITS _u(0x00000060)
#define HSTX_CTRL_CSR_COUPLED_SEL_MSB _u(6)
#define HSTX_CTRL_CSR_COUPLED_SEL_LSB _u(5)
#define HSTX_CTRL_CSR_COUPLED_SEL_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : HSTX_CTRL_CSR_COUPLED_MODE
// Description : Enable the PIO-to-HSTX 1:1 connection. The HSTX must be clocked
// *directly* from the system clock (not just from some other
// clock source of the same frequency) for this synchronous
// interface to function correctly.
//
// When COUPLED_MODE is set, BITx_SEL_P and SEL_N indices 24
// through 31 will select bits from the 8-bit PIO-to-HSTX path,
// rather than shifter bits. Indices of 0 through 23 will still
// index the shift register as normal.
//
// The PIO outputs connected to the PIO-to-HSTX bus are those same
// outputs that would appear on the HSTX-capable pins if those
// pins' FUNCSELs were set to PIO instead of HSTX.
//
// For example, if HSTX is on GPIOs 12 through 19, then PIO
// outputs 12 through 19 are connected to the HSTX when coupled
// mode is engaged.
#define HSTX_CTRL_CSR_COUPLED_MODE_RESET _u(0x0)
#define HSTX_CTRL_CSR_COUPLED_MODE_BITS _u(0x00000010)
#define HSTX_CTRL_CSR_COUPLED_MODE_MSB _u(4)
#define HSTX_CTRL_CSR_COUPLED_MODE_LSB _u(4)
#define HSTX_CTRL_CSR_COUPLED_MODE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : HSTX_CTRL_CSR_EXPAND_EN
// Description : Enable the command expander. When 0, raw FIFO data is passed
// directly to the output shift register. When 1, the command
// expander can perform simple operations such as run length
// decoding on data between the FIFO and the shift register.
//
// Do not change CXPD_EN whilst EN is set. It's safe to set
// CXPD_EN simultaneously with setting EN.
#define HSTX_CTRL_CSR_EXPAND_EN_RESET _u(0x0)
#define HSTX_CTRL_CSR_EXPAND_EN_BITS _u(0x00000002)
#define HSTX_CTRL_CSR_EXPAND_EN_MSB _u(1)
#define HSTX_CTRL_CSR_EXPAND_EN_LSB _u(1)
#define HSTX_CTRL_CSR_EXPAND_EN_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : HSTX_CTRL_CSR_EN
// Description : When EN is 1, the HSTX will shift out data as it appears in the
// FIFO. As long as there is data, the HSTX shift register will
// shift once per clock cycle, and the frequency of popping from
// the FIFO is determined by the ratio of SHIFT and SHIFT_THRESH.
//
// When EN is 0, the FIFO is not popped. The shift counter and
// clock generator are also reset to their initial state for as
// long as EN is low. Note the initial phase of the clock
// generator can be configured by the CLKPHASE field.
//
// Once the HSTX is enabled again, and data is pushed to the FIFO,
// the generated clock's first rising edge will be one half-period
// after the first data is launched.
#define HSTX_CTRL_CSR_EN_RESET _u(0x0)
#define HSTX_CTRL_CSR_EN_BITS _u(0x00000001)
#define HSTX_CTRL_CSR_EN_MSB _u(0)
#define HSTX_CTRL_CSR_EN_LSB _u(0)
#define HSTX_CTRL_CSR_EN_ACCESS "RW"
// =============================================================================
// Register : HSTX_CTRL_BIT0
// Description : Data control register for output bit 0
#define HSTX_CTRL_BIT0_OFFSET _u(0x00000004)
#define HSTX_CTRL_BIT0_BITS _u(0x00031f1f)
#define HSTX_CTRL_BIT0_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : HSTX_CTRL_BIT0_CLK
// Description : Connect this output to the generated clock, rather than the
// data shift register. SEL_P and SEL_N are ignored if this bit is
// set, but INV can still be set to generate an antiphase clock.
#define HSTX_CTRL_BIT0_CLK_RESET _u(0x0)
#define HSTX_CTRL_BIT0_CLK_BITS _u(0x00020000)
#define HSTX_CTRL_BIT0_CLK_MSB _u(17)
#define HSTX_CTRL_BIT0_CLK_LSB _u(17)
#define HSTX_CTRL_BIT0_CLK_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : HSTX_CTRL_BIT0_INV
// Description : Invert this data output (logical NOT)
#define HSTX_CTRL_BIT0_INV_RESET _u(0x0)
#define HSTX_CTRL_BIT0_INV_BITS _u(0x00010000)
#define HSTX_CTRL_BIT0_INV_MSB _u(16)
#define HSTX_CTRL_BIT0_INV_LSB _u(16)
#define HSTX_CTRL_BIT0_INV_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : HSTX_CTRL_BIT0_SEL_N
// Description : Shift register data bit select for the second half of the HSTX
// clock cycle
#define HSTX_CTRL_BIT0_SEL_N_RESET _u(0x00)
#define HSTX_CTRL_BIT0_SEL_N_BITS _u(0x00001f00)
#define HSTX_CTRL_BIT0_SEL_N_MSB _u(12)
#define HSTX_CTRL_BIT0_SEL_N_LSB _u(8)
#define HSTX_CTRL_BIT0_SEL_N_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : HSTX_CTRL_BIT0_SEL_P
// Description : Shift register data bit select for the first half of the HSTX
// clock cycle
#define HSTX_CTRL_BIT0_SEL_P_RESET _u(0x00)
#define HSTX_CTRL_BIT0_SEL_P_BITS _u(0x0000001f)
#define HSTX_CTRL_BIT0_SEL_P_MSB _u(4)
#define HSTX_CTRL_BIT0_SEL_P_LSB _u(0)
#define HSTX_CTRL_BIT0_SEL_P_ACCESS "RW"
// =============================================================================
// Register : HSTX_CTRL_BIT1
// Description : Data control register for output bit 1
#define HSTX_CTRL_BIT1_OFFSET _u(0x00000008)
#define HSTX_CTRL_BIT1_BITS _u(0x00031f1f)
#define HSTX_CTRL_BIT1_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : HSTX_CTRL_BIT1_CLK
// Description : Connect this output to the generated clock, rather than the
// data shift register. SEL_P and SEL_N are ignored if this bit is
// set, but INV can still be set to generate an antiphase clock.
#define HSTX_CTRL_BIT1_CLK_RESET _u(0x0)
#define HSTX_CTRL_BIT1_CLK_BITS _u(0x00020000)
#define HSTX_CTRL_BIT1_CLK_MSB _u(17)
#define HSTX_CTRL_BIT1_CLK_LSB _u(17)
#define HSTX_CTRL_BIT1_CLK_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : HSTX_CTRL_BIT1_INV
// Description : Invert this data output (logical NOT)
#define HSTX_CTRL_BIT1_INV_RESET _u(0x0)
#define HSTX_CTRL_BIT1_INV_BITS _u(0x00010000)
#define HSTX_CTRL_BIT1_INV_MSB _u(16)
#define HSTX_CTRL_BIT1_INV_LSB _u(16)
#define HSTX_CTRL_BIT1_INV_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : HSTX_CTRL_BIT1_SEL_N
// Description : Shift register data bit select for the second half of the HSTX
// clock cycle
#define HSTX_CTRL_BIT1_SEL_N_RESET _u(0x00)
#define HSTX_CTRL_BIT1_SEL_N_BITS _u(0x00001f00)
#define HSTX_CTRL_BIT1_SEL_N_MSB _u(12)
#define HSTX_CTRL_BIT1_SEL_N_LSB _u(8)
#define HSTX_CTRL_BIT1_SEL_N_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : HSTX_CTRL_BIT1_SEL_P
// Description : Shift register data bit select for the first half of the HSTX
// clock cycle
#define HSTX_CTRL_BIT1_SEL_P_RESET _u(0x00)
#define HSTX_CTRL_BIT1_SEL_P_BITS _u(0x0000001f)
#define HSTX_CTRL_BIT1_SEL_P_MSB _u(4)
#define HSTX_CTRL_BIT1_SEL_P_LSB _u(0)
#define HSTX_CTRL_BIT1_SEL_P_ACCESS "RW"
// =============================================================================
// Register : HSTX_CTRL_BIT2
// Description : Data control register for output bit 2
#define HSTX_CTRL_BIT2_OFFSET _u(0x0000000c)
#define HSTX_CTRL_BIT2_BITS _u(0x00031f1f)
#define HSTX_CTRL_BIT2_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : HSTX_CTRL_BIT2_CLK
// Description : Connect this output to the generated clock, rather than the
// data shift register. SEL_P and SEL_N are ignored if this bit is
// set, but INV can still be set to generate an antiphase clock.
#define HSTX_CTRL_BIT2_CLK_RESET _u(0x0)
#define HSTX_CTRL_BIT2_CLK_BITS _u(0x00020000)
#define HSTX_CTRL_BIT2_CLK_MSB _u(17)
#define HSTX_CTRL_BIT2_CLK_LSB _u(17)
#define HSTX_CTRL_BIT2_CLK_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : HSTX_CTRL_BIT2_INV
// Description : Invert this data output (logical NOT)
#define HSTX_CTRL_BIT2_INV_RESET _u(0x0)
#define HSTX_CTRL_BIT2_INV_BITS _u(0x00010000)
#define HSTX_CTRL_BIT2_INV_MSB _u(16)
#define HSTX_CTRL_BIT2_INV_LSB _u(16)
#define HSTX_CTRL_BIT2_INV_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : HSTX_CTRL_BIT2_SEL_N
// Description : Shift register data bit select for the second half of the HSTX
// clock cycle
#define HSTX_CTRL_BIT2_SEL_N_RESET _u(0x00)
#define HSTX_CTRL_BIT2_SEL_N_BITS _u(0x00001f00)
#define HSTX_CTRL_BIT2_SEL_N_MSB _u(12)
#define HSTX_CTRL_BIT2_SEL_N_LSB _u(8)
#define HSTX_CTRL_BIT2_SEL_N_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : HSTX_CTRL_BIT2_SEL_P
// Description : Shift register data bit select for the first half of the HSTX
// clock cycle
#define HSTX_CTRL_BIT2_SEL_P_RESET _u(0x00)
#define HSTX_CTRL_BIT2_SEL_P_BITS _u(0x0000001f)
#define HSTX_CTRL_BIT2_SEL_P_MSB _u(4)
#define HSTX_CTRL_BIT2_SEL_P_LSB _u(0)
#define HSTX_CTRL_BIT2_SEL_P_ACCESS "RW"
// =============================================================================
// Register : HSTX_CTRL_BIT3
// Description : Data control register for output bit 3
#define HSTX_CTRL_BIT3_OFFSET _u(0x00000010)
#define HSTX_CTRL_BIT3_BITS _u(0x00031f1f)
#define HSTX_CTRL_BIT3_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : HSTX_CTRL_BIT3_CLK
// Description : Connect this output to the generated clock, rather than the
// data shift register. SEL_P and SEL_N are ignored if this bit is
// set, but INV can still be set to generate an antiphase clock.
#define HSTX_CTRL_BIT3_CLK_RESET _u(0x0)
#define HSTX_CTRL_BIT3_CLK_BITS _u(0x00020000)
#define HSTX_CTRL_BIT3_CLK_MSB _u(17)
#define HSTX_CTRL_BIT3_CLK_LSB _u(17)
#define HSTX_CTRL_BIT3_CLK_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : HSTX_CTRL_BIT3_INV
// Description : Invert this data output (logical NOT)
#define HSTX_CTRL_BIT3_INV_RESET _u(0x0)
#define HSTX_CTRL_BIT3_INV_BITS _u(0x00010000)
#define HSTX_CTRL_BIT3_INV_MSB _u(16)
#define HSTX_CTRL_BIT3_INV_LSB _u(16)
#define HSTX_CTRL_BIT3_INV_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : HSTX_CTRL_BIT3_SEL_N
// Description : Shift register data bit select for the second half of the HSTX
// clock cycle
#define HSTX_CTRL_BIT3_SEL_N_RESET _u(0x00)
#define HSTX_CTRL_BIT3_SEL_N_BITS _u(0x00001f00)
#define HSTX_CTRL_BIT3_SEL_N_MSB _u(12)
#define HSTX_CTRL_BIT3_SEL_N_LSB _u(8)
#define HSTX_CTRL_BIT3_SEL_N_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : HSTX_CTRL_BIT3_SEL_P
// Description : Shift register data bit select for the first half of the HSTX
// clock cycle
#define HSTX_CTRL_BIT3_SEL_P_RESET _u(0x00)
#define HSTX_CTRL_BIT3_SEL_P_BITS _u(0x0000001f)
#define HSTX_CTRL_BIT3_SEL_P_MSB _u(4)
#define HSTX_CTRL_BIT3_SEL_P_LSB _u(0)
#define HSTX_CTRL_BIT3_SEL_P_ACCESS "RW"
// =============================================================================
// Register : HSTX_CTRL_BIT4
// Description : Data control register for output bit 4
#define HSTX_CTRL_BIT4_OFFSET _u(0x00000014)
#define HSTX_CTRL_BIT4_BITS _u(0x00031f1f)
#define HSTX_CTRL_BIT4_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : HSTX_CTRL_BIT4_CLK
// Description : Connect this output to the generated clock, rather than the
// data shift register. SEL_P and SEL_N are ignored if this bit is
// set, but INV can still be set to generate an antiphase clock.
#define HSTX_CTRL_BIT4_CLK_RESET _u(0x0)
#define HSTX_CTRL_BIT4_CLK_BITS _u(0x00020000)
#define HSTX_CTRL_BIT4_CLK_MSB _u(17)
#define HSTX_CTRL_BIT4_CLK_LSB _u(17)
#define HSTX_CTRL_BIT4_CLK_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : HSTX_CTRL_BIT4_INV
// Description : Invert this data output (logical NOT)
#define HSTX_CTRL_BIT4_INV_RESET _u(0x0)
#define HSTX_CTRL_BIT4_INV_BITS _u(0x00010000)
#define HSTX_CTRL_BIT4_INV_MSB _u(16)
#define HSTX_CTRL_BIT4_INV_LSB _u(16)
#define HSTX_CTRL_BIT4_INV_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : HSTX_CTRL_BIT4_SEL_N
// Description : Shift register data bit select for the second half of the HSTX
// clock cycle
#define HSTX_CTRL_BIT4_SEL_N_RESET _u(0x00)
#define HSTX_CTRL_BIT4_SEL_N_BITS _u(0x00001f00)
#define HSTX_CTRL_BIT4_SEL_N_MSB _u(12)
#define HSTX_CTRL_BIT4_SEL_N_LSB _u(8)
#define HSTX_CTRL_BIT4_SEL_N_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : HSTX_CTRL_BIT4_SEL_P
// Description : Shift register data bit select for the first half of the HSTX
// clock cycle
#define HSTX_CTRL_BIT4_SEL_P_RESET _u(0x00)
#define HSTX_CTRL_BIT4_SEL_P_BITS _u(0x0000001f)
#define HSTX_CTRL_BIT4_SEL_P_MSB _u(4)
#define HSTX_CTRL_BIT4_SEL_P_LSB _u(0)
#define HSTX_CTRL_BIT4_SEL_P_ACCESS "RW"
// =============================================================================
// Register : HSTX_CTRL_BIT5
// Description : Data control register for output bit 5
#define HSTX_CTRL_BIT5_OFFSET _u(0x00000018)
#define HSTX_CTRL_BIT5_BITS _u(0x00031f1f)
#define HSTX_CTRL_BIT5_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : HSTX_CTRL_BIT5_CLK
// Description : Connect this output to the generated clock, rather than the
// data shift register. SEL_P and SEL_N are ignored if this bit is
// set, but INV can still be set to generate an antiphase clock.
#define HSTX_CTRL_BIT5_CLK_RESET _u(0x0)
#define HSTX_CTRL_BIT5_CLK_BITS _u(0x00020000)
#define HSTX_CTRL_BIT5_CLK_MSB _u(17)
#define HSTX_CTRL_BIT5_CLK_LSB _u(17)
#define HSTX_CTRL_BIT5_CLK_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : HSTX_CTRL_BIT5_INV
// Description : Invert this data output (logical NOT)
#define HSTX_CTRL_BIT5_INV_RESET _u(0x0)
#define HSTX_CTRL_BIT5_INV_BITS _u(0x00010000)
#define HSTX_CTRL_BIT5_INV_MSB _u(16)
#define HSTX_CTRL_BIT5_INV_LSB _u(16)
#define HSTX_CTRL_BIT5_INV_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : HSTX_CTRL_BIT5_SEL_N
// Description : Shift register data bit select for the second half of the HSTX
// clock cycle
#define HSTX_CTRL_BIT5_SEL_N_RESET _u(0x00)
#define HSTX_CTRL_BIT5_SEL_N_BITS _u(0x00001f00)
#define HSTX_CTRL_BIT5_SEL_N_MSB _u(12)
#define HSTX_CTRL_BIT5_SEL_N_LSB _u(8)
#define HSTX_CTRL_BIT5_SEL_N_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : HSTX_CTRL_BIT5_SEL_P
// Description : Shift register data bit select for the first half of the HSTX
// clock cycle
#define HSTX_CTRL_BIT5_SEL_P_RESET _u(0x00)
#define HSTX_CTRL_BIT5_SEL_P_BITS _u(0x0000001f)
#define HSTX_CTRL_BIT5_SEL_P_MSB _u(4)
#define HSTX_CTRL_BIT5_SEL_P_LSB _u(0)
#define HSTX_CTRL_BIT5_SEL_P_ACCESS "RW"
// =============================================================================
// Register : HSTX_CTRL_BIT6
// Description : Data control register for output bit 6
#define HSTX_CTRL_BIT6_OFFSET _u(0x0000001c)
#define HSTX_CTRL_BIT6_BITS _u(0x00031f1f)
#define HSTX_CTRL_BIT6_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : HSTX_CTRL_BIT6_CLK
// Description : Connect this output to the generated clock, rather than the
// data shift register. SEL_P and SEL_N are ignored if this bit is
// set, but INV can still be set to generate an antiphase clock.
#define HSTX_CTRL_BIT6_CLK_RESET _u(0x0)
#define HSTX_CTRL_BIT6_CLK_BITS _u(0x00020000)
#define HSTX_CTRL_BIT6_CLK_MSB _u(17)
#define HSTX_CTRL_BIT6_CLK_LSB _u(17)
#define HSTX_CTRL_BIT6_CLK_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : HSTX_CTRL_BIT6_INV
// Description : Invert this data output (logical NOT)
#define HSTX_CTRL_BIT6_INV_RESET _u(0x0)
#define HSTX_CTRL_BIT6_INV_BITS _u(0x00010000)
#define HSTX_CTRL_BIT6_INV_MSB _u(16)
#define HSTX_CTRL_BIT6_INV_LSB _u(16)
#define HSTX_CTRL_BIT6_INV_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : HSTX_CTRL_BIT6_SEL_N
// Description : Shift register data bit select for the second half of the HSTX
// clock cycle
#define HSTX_CTRL_BIT6_SEL_N_RESET _u(0x00)
#define HSTX_CTRL_BIT6_SEL_N_BITS _u(0x00001f00)
#define HSTX_CTRL_BIT6_SEL_N_MSB _u(12)
#define HSTX_CTRL_BIT6_SEL_N_LSB _u(8)
#define HSTX_CTRL_BIT6_SEL_N_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : HSTX_CTRL_BIT6_SEL_P
// Description : Shift register data bit select for the first half of the HSTX
// clock cycle
#define HSTX_CTRL_BIT6_SEL_P_RESET _u(0x00)
#define HSTX_CTRL_BIT6_SEL_P_BITS _u(0x0000001f)
#define HSTX_CTRL_BIT6_SEL_P_MSB _u(4)
#define HSTX_CTRL_BIT6_SEL_P_LSB _u(0)
#define HSTX_CTRL_BIT6_SEL_P_ACCESS "RW"
// =============================================================================
// Register : HSTX_CTRL_BIT7
// Description : Data control register for output bit 7
#define HSTX_CTRL_BIT7_OFFSET _u(0x00000020)
#define HSTX_CTRL_BIT7_BITS _u(0x00031f1f)
#define HSTX_CTRL_BIT7_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : HSTX_CTRL_BIT7_CLK
// Description : Connect this output to the generated clock, rather than the
// data shift register. SEL_P and SEL_N are ignored if this bit is
// set, but INV can still be set to generate an antiphase clock.
#define HSTX_CTRL_BIT7_CLK_RESET _u(0x0)
#define HSTX_CTRL_BIT7_CLK_BITS _u(0x00020000)
#define HSTX_CTRL_BIT7_CLK_MSB _u(17)
#define HSTX_CTRL_BIT7_CLK_LSB _u(17)
#define HSTX_CTRL_BIT7_CLK_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : HSTX_CTRL_BIT7_INV
// Description : Invert this data output (logical NOT)
#define HSTX_CTRL_BIT7_INV_RESET _u(0x0)
#define HSTX_CTRL_BIT7_INV_BITS _u(0x00010000)
#define HSTX_CTRL_BIT7_INV_MSB _u(16)
#define HSTX_CTRL_BIT7_INV_LSB _u(16)
#define HSTX_CTRL_BIT7_INV_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : HSTX_CTRL_BIT7_SEL_N
// Description : Shift register data bit select for the second half of the HSTX
// clock cycle
#define HSTX_CTRL_BIT7_SEL_N_RESET _u(0x00)
#define HSTX_CTRL_BIT7_SEL_N_BITS _u(0x00001f00)
#define HSTX_CTRL_BIT7_SEL_N_MSB _u(12)
#define HSTX_CTRL_BIT7_SEL_N_LSB _u(8)
#define HSTX_CTRL_BIT7_SEL_N_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : HSTX_CTRL_BIT7_SEL_P
// Description : Shift register data bit select for the first half of the HSTX
// clock cycle
#define HSTX_CTRL_BIT7_SEL_P_RESET _u(0x00)
#define HSTX_CTRL_BIT7_SEL_P_BITS _u(0x0000001f)
#define HSTX_CTRL_BIT7_SEL_P_MSB _u(4)
#define HSTX_CTRL_BIT7_SEL_P_LSB _u(0)
#define HSTX_CTRL_BIT7_SEL_P_ACCESS "RW"
// =============================================================================
// Register : HSTX_CTRL_EXPAND_SHIFT
// Description : Configure the optional shifter inside the command expander
#define HSTX_CTRL_EXPAND_SHIFT_OFFSET _u(0x00000024)
#define HSTX_CTRL_EXPAND_SHIFT_BITS _u(0x1f1f1f1f)
#define HSTX_CTRL_EXPAND_SHIFT_RESET _u(0x01000100)
// -----------------------------------------------------------------------------
// Field : HSTX_CTRL_EXPAND_SHIFT_ENC_N_SHIFTS
// Description : Number of times to consume from the shift register before
// refilling it from the FIFO, when the current command is an
// encoded data command (e.g. TMDS). A register value of 0 means
// shift 32 times.
#define HSTX_CTRL_EXPAND_SHIFT_ENC_N_SHIFTS_RESET _u(0x01)
#define HSTX_CTRL_EXPAND_SHIFT_ENC_N_SHIFTS_BITS _u(0x1f000000)
#define HSTX_CTRL_EXPAND_SHIFT_ENC_N_SHIFTS_MSB _u(28)
#define HSTX_CTRL_EXPAND_SHIFT_ENC_N_SHIFTS_LSB _u(24)
#define HSTX_CTRL_EXPAND_SHIFT_ENC_N_SHIFTS_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : HSTX_CTRL_EXPAND_SHIFT_ENC_SHIFT
// Description : How many bits to right-rotate the shift register by each time
// data is pushed to the output shifter, when the current command
// is an encoded data command (e.g. TMDS).
#define HSTX_CTRL_EXPAND_SHIFT_ENC_SHIFT_RESET _u(0x00)
#define HSTX_CTRL_EXPAND_SHIFT_ENC_SHIFT_BITS _u(0x001f0000)
#define HSTX_CTRL_EXPAND_SHIFT_ENC_SHIFT_MSB _u(20)
#define HSTX_CTRL_EXPAND_SHIFT_ENC_SHIFT_LSB _u(16)
#define HSTX_CTRL_EXPAND_SHIFT_ENC_SHIFT_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : HSTX_CTRL_EXPAND_SHIFT_RAW_N_SHIFTS
// Description : Number of times to consume from the shift register before
// refilling it from the FIFO, when the current command is a raw
// data command. A register value of 0 means shift 32 times.
#define HSTX_CTRL_EXPAND_SHIFT_RAW_N_SHIFTS_RESET _u(0x01)
#define HSTX_CTRL_EXPAND_SHIFT_RAW_N_SHIFTS_BITS _u(0x00001f00)
#define HSTX_CTRL_EXPAND_SHIFT_RAW_N_SHIFTS_MSB _u(12)
#define HSTX_CTRL_EXPAND_SHIFT_RAW_N_SHIFTS_LSB _u(8)
#define HSTX_CTRL_EXPAND_SHIFT_RAW_N_SHIFTS_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : HSTX_CTRL_EXPAND_SHIFT_RAW_SHIFT
// Description : How many bits to right-rotate the shift register by each time
// data is pushed to the output shifter, when the current command
// is a raw data command.
#define HSTX_CTRL_EXPAND_SHIFT_RAW_SHIFT_RESET _u(0x00)
#define HSTX_CTRL_EXPAND_SHIFT_RAW_SHIFT_BITS _u(0x0000001f)
#define HSTX_CTRL_EXPAND_SHIFT_RAW_SHIFT_MSB _u(4)
#define HSTX_CTRL_EXPAND_SHIFT_RAW_SHIFT_LSB _u(0)
#define HSTX_CTRL_EXPAND_SHIFT_RAW_SHIFT_ACCESS "RW"
// =============================================================================
// Register : HSTX_CTRL_EXPAND_TMDS
// Description : Configure the optional TMDS encoder inside the command expander
#define HSTX_CTRL_EXPAND_TMDS_OFFSET _u(0x00000028)
#define HSTX_CTRL_EXPAND_TMDS_BITS _u(0x00ffffff)
#define HSTX_CTRL_EXPAND_TMDS_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : HSTX_CTRL_EXPAND_TMDS_L2_NBITS
// Description : Number of valid data bits for the lane 2 TMDS encoder, starting
// from bit 7 of the rotated data. Field values of 0 -> 7 encode
// counts of 1 -> 8 bits.
#define HSTX_CTRL_EXPAND_TMDS_L2_NBITS_RESET _u(0x0)
#define HSTX_CTRL_EXPAND_TMDS_L2_NBITS_BITS _u(0x00e00000)
#define HSTX_CTRL_EXPAND_TMDS_L2_NBITS_MSB _u(23)
#define HSTX_CTRL_EXPAND_TMDS_L2_NBITS_LSB _u(21)
#define HSTX_CTRL_EXPAND_TMDS_L2_NBITS_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : HSTX_CTRL_EXPAND_TMDS_L2_ROT
// Description : Right-rotate applied to the current shifter data before the
// lane 2 TMDS encoder.
#define HSTX_CTRL_EXPAND_TMDS_L2_ROT_RESET _u(0x00)
#define HSTX_CTRL_EXPAND_TMDS_L2_ROT_BITS _u(0x001f0000)
#define HSTX_CTRL_EXPAND_TMDS_L2_ROT_MSB _u(20)
#define HSTX_CTRL_EXPAND_TMDS_L2_ROT_LSB _u(16)
#define HSTX_CTRL_EXPAND_TMDS_L2_ROT_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : HSTX_CTRL_EXPAND_TMDS_L1_NBITS
// Description : Number of valid data bits for the lane 1 TMDS encoder, starting
// from bit 7 of the rotated data. Field values of 0 -> 7 encode
// counts of 1 -> 8 bits.
#define HSTX_CTRL_EXPAND_TMDS_L1_NBITS_RESET _u(0x0)
#define HSTX_CTRL_EXPAND_TMDS_L1_NBITS_BITS _u(0x0000e000)
#define HSTX_CTRL_EXPAND_TMDS_L1_NBITS_MSB _u(15)
#define HSTX_CTRL_EXPAND_TMDS_L1_NBITS_LSB _u(13)
#define HSTX_CTRL_EXPAND_TMDS_L1_NBITS_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : HSTX_CTRL_EXPAND_TMDS_L1_ROT
// Description : Right-rotate applied to the current shifter data before the
// lane 1 TMDS encoder.
#define HSTX_CTRL_EXPAND_TMDS_L1_ROT_RESET _u(0x00)
#define HSTX_CTRL_EXPAND_TMDS_L1_ROT_BITS _u(0x00001f00)
#define HSTX_CTRL_EXPAND_TMDS_L1_ROT_MSB _u(12)
#define HSTX_CTRL_EXPAND_TMDS_L1_ROT_LSB _u(8)
#define HSTX_CTRL_EXPAND_TMDS_L1_ROT_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : HSTX_CTRL_EXPAND_TMDS_L0_NBITS
// Description : Number of valid data bits for the lane 0 TMDS encoder, starting
// from bit 7 of the rotated data. Field values of 0 -> 7 encode
// counts of 1 -> 8 bits.
#define HSTX_CTRL_EXPAND_TMDS_L0_NBITS_RESET _u(0x0)
#define HSTX_CTRL_EXPAND_TMDS_L0_NBITS_BITS _u(0x000000e0)
#define HSTX_CTRL_EXPAND_TMDS_L0_NBITS_MSB _u(7)
#define HSTX_CTRL_EXPAND_TMDS_L0_NBITS_LSB _u(5)
#define HSTX_CTRL_EXPAND_TMDS_L0_NBITS_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : HSTX_CTRL_EXPAND_TMDS_L0_ROT
// Description : Right-rotate applied to the current shifter data before the
// lane 0 TMDS encoder.
#define HSTX_CTRL_EXPAND_TMDS_L0_ROT_RESET _u(0x00)
#define HSTX_CTRL_EXPAND_TMDS_L0_ROT_BITS _u(0x0000001f)
#define HSTX_CTRL_EXPAND_TMDS_L0_ROT_MSB _u(4)
#define HSTX_CTRL_EXPAND_TMDS_L0_ROT_LSB _u(0)
#define HSTX_CTRL_EXPAND_TMDS_L0_ROT_ACCESS "RW"
// =============================================================================
#endif // _HARDWARE_REGS_HSTX_CTRL_H

62
arch/arm/src/rp23xx/hardware/regs/hstx_fifo.h
View file

@ -1,62 +0,0 @@
// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
// =============================================================================
// Register block : HSTX_FIFO
// Version : 1
// Bus type : ahbl
// Description : FIFO status and write access for HSTX
// =============================================================================
#ifndef _HARDWARE_REGS_HSTX_FIFO_H
#define _HARDWARE_REGS_HSTX_FIFO_H
// =============================================================================
// Register : HSTX_FIFO_STAT
// Description : FIFO status
#define HSTX_FIFO_STAT_OFFSET _u(0x00000000)
#define HSTX_FIFO_STAT_BITS _u(0x000007ff)
#define HSTX_FIFO_STAT_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : HSTX_FIFO_STAT_WOF
// Description : FIFO was written when full. Write 1 to clear.
#define HSTX_FIFO_STAT_WOF_RESET _u(0x0)
#define HSTX_FIFO_STAT_WOF_BITS _u(0x00000400)
#define HSTX_FIFO_STAT_WOF_MSB _u(10)
#define HSTX_FIFO_STAT_WOF_LSB _u(10)
#define HSTX_FIFO_STAT_WOF_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : HSTX_FIFO_STAT_EMPTY
#define HSTX_FIFO_STAT_EMPTY_RESET "-"
#define HSTX_FIFO_STAT_EMPTY_BITS _u(0x00000200)
#define HSTX_FIFO_STAT_EMPTY_MSB _u(9)
#define HSTX_FIFO_STAT_EMPTY_LSB _u(9)
#define HSTX_FIFO_STAT_EMPTY_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : HSTX_FIFO_STAT_FULL
#define HSTX_FIFO_STAT_FULL_RESET "-"
#define HSTX_FIFO_STAT_FULL_BITS _u(0x00000100)
#define HSTX_FIFO_STAT_FULL_MSB _u(8)
#define HSTX_FIFO_STAT_FULL_LSB _u(8)
#define HSTX_FIFO_STAT_FULL_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : HSTX_FIFO_STAT_LEVEL
#define HSTX_FIFO_STAT_LEVEL_RESET _u(0x00)
#define HSTX_FIFO_STAT_LEVEL_BITS _u(0x000000ff)
#define HSTX_FIFO_STAT_LEVEL_MSB _u(7)
#define HSTX_FIFO_STAT_LEVEL_LSB _u(0)
#define HSTX_FIFO_STAT_LEVEL_ACCESS "RO"
// =============================================================================
// Register : HSTX_FIFO_FIFO
// Description : Write access to FIFO
#define HSTX_FIFO_FIFO_OFFSET _u(0x00000004)
#define HSTX_FIFO_FIFO_BITS _u(0xffffffff)
#define HSTX_FIFO_FIFO_RESET _u(0x00000000)
#define HSTX_FIFO_FIFO_MSB _u(31)
#define HSTX_FIFO_FIFO_LSB _u(0)
#define HSTX_FIFO_FIFO_ACCESS "WF"
// =============================================================================
#endif // _HARDWARE_REGS_HSTX_FIFO_H

2700
arch/arm/src/rp23xx/hardware/regs/i2c.h
View file

File diff suppressed because it is too large Load diff

184
arch/arm/src/rp23xx/hardware/regs/intctrl.h
View file

@ -1,184 +0,0 @@
// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _INTCTRL_H
#define _INTCTRL_H
/**
* \file rp2350/intctrl.h
*/
#ifdef __ASSEMBLER__
#define TIMER0_IRQ_0 0
#define TIMER0_IRQ_1 1
#define TIMER0_IRQ_2 2
#define TIMER0_IRQ_3 3
#define TIMER1_IRQ_0 4
#define TIMER1_IRQ_1 5
#define TIMER1_IRQ_2 6
#define TIMER1_IRQ_3 7
#define PWM_IRQ_WRAP_0 8
#define PWM_IRQ_WRAP_1 9
#define DMA_IRQ_0 10
#define DMA_IRQ_1 11
#define DMA_IRQ_2 12
#define DMA_IRQ_3 13
#define USBCTRL_IRQ 14
#define PIO0_IRQ_0 15
#define PIO0_IRQ_1 16
#define PIO1_IRQ_0 17
#define PIO1_IRQ_1 18
#define PIO2_IRQ_0 19
#define PIO2_IRQ_1 20
#define IO_IRQ_BANK0 21
#define IO_IRQ_BANK0_NS 22
#define IO_IRQ_QSPI 23
#define IO_IRQ_QSPI_NS 24
#define SIO_IRQ_FIFO 25
#define SIO_IRQ_BELL 26
#define SIO_IRQ_FIFO_NS 27
#define SIO_IRQ_BELL_NS 28
#define SIO_IRQ_MTIMECMP 29
#define CLOCKS_IRQ 30
#define SPI0_IRQ 31
#define SPI1_IRQ 32
#define UART0_IRQ 33
#define UART1_IRQ 34
#define ADC_IRQ_FIFO 35
#define I2C0_IRQ 36
#define I2C1_IRQ 37
#define OTP_IRQ 38
#define TRNG_IRQ 39
#define PROC0_IRQ_CTI 40
#define PROC1_IRQ_CTI 41
#define PLL_SYS_IRQ 42
#define PLL_USB_IRQ 43
#define POWMAN_IRQ_POW 44
#define POWMAN_IRQ_TIMER 45
#define SPAREIRQ_IRQ_0 46
#define SPAREIRQ_IRQ_1 47
#define SPAREIRQ_IRQ_2 48
#define SPAREIRQ_IRQ_3 49
#define SPAREIRQ_IRQ_4 50
#define SPAREIRQ_IRQ_5 51
#else
/**
* \brief Interrupt numbers on RP2350 (used as typedef \ref irq_num_t)
* \ingroup hardware_irq
*/
typedef enum irq_num_rp2350 {
TIMER0_IRQ_0 = 0, ///< Select TIMER0's IRQ 0 output
TIMER0_IRQ_1 = 1, ///< Select TIMER0's IRQ 1 output
TIMER0_IRQ_2 = 2, ///< Select TIMER0's IRQ 2 output
TIMER0_IRQ_3 = 3, ///< Select TIMER0's IRQ 3 output
TIMER1_IRQ_0 = 4, ///< Select TIMER1's IRQ 0 output
TIMER1_IRQ_1 = 5, ///< Select TIMER1's IRQ 1 output
TIMER1_IRQ_2 = 6, ///< Select TIMER1's IRQ 2 output
TIMER1_IRQ_3 = 7, ///< Select TIMER1's IRQ 3 output
PWM_IRQ_WRAP_0 = 8, ///< Select PWM's IRQ_WRAP 0 output
PWM_IRQ_WRAP_1 = 9, ///< Select PWM's IRQ_WRAP 1 output
DMA_IRQ_0 = 10, ///< Select DMA's IRQ 0 output
DMA_IRQ_1 = 11, ///< Select DMA's IRQ 1 output
DMA_IRQ_2 = 12, ///< Select DMA's IRQ 2 output
DMA_IRQ_3 = 13, ///< Select DMA's IRQ 3 output
USBCTRL_IRQ = 14, ///< Select USBCTRL's IRQ output
PIO0_IRQ_0 = 15, ///< Select PIO0's IRQ 0 output
PIO0_IRQ_1 = 16, ///< Select PIO0's IRQ 1 output
PIO1_IRQ_0 = 17, ///< Select PIO1's IRQ 0 output
PIO1_IRQ_1 = 18, ///< Select PIO1's IRQ 1 output
PIO2_IRQ_0 = 19, ///< Select PIO2's IRQ 0 output
PIO2_IRQ_1 = 20, ///< Select PIO2's IRQ 1 output
IO_IRQ_BANK0 = 21, ///< Select IO_BANK0's IRQ output
IO_IRQ_BANK0_NS = 22, ///< Select IO_BANK0_NS's IRQ output
IO_IRQ_QSPI = 23, ///< Select IO_QSPI's IRQ output
IO_IRQ_QSPI_NS = 24, ///< Select IO_QSPI_NS's IRQ output
SIO_IRQ_FIFO = 25, ///< Select SIO's IRQ_FIFO output
SIO_IRQ_BELL = 26, ///< Select SIO's IRQ_BELL output
SIO_IRQ_FIFO_NS = 27, ///< Select SIO_NS's IRQ_FIFO output
SIO_IRQ_BELL_NS = 28, ///< Select SIO_NS's IRQ_BELL output
SIO_IRQ_MTIMECMP = 29, ///< Select SIO_IRQ_MTIMECMP's IRQ output
CLOCKS_IRQ = 30, ///< Select CLOCKS's IRQ output
SPI0_IRQ = 31, ///< Select SPI0's IRQ output
SPI1_IRQ = 32, ///< Select SPI1's IRQ output
UART0_IRQ = 33, ///< Select UART0's IRQ output
UART1_IRQ = 34, ///< Select UART1's IRQ output
ADC_IRQ_FIFO = 35, ///< Select ADC's IRQ_FIFO output
I2C0_IRQ = 36, ///< Select I2C0's IRQ output
I2C1_IRQ = 37, ///< Select I2C1's IRQ output
OTP_IRQ = 38, ///< Select OTP's IRQ output
TRNG_IRQ = 39, ///< Select TRNG's IRQ output
PROC0_IRQ_CTI = 40, ///< Select PROC0's IRQ_CTI output
PROC1_IRQ_CTI = 41, ///< Select PROC1's IRQ_CTI output
PLL_SYS_IRQ = 42, ///< Select PLL_SYS's IRQ output
PLL_USB_IRQ = 43, ///< Select PLL_USB's IRQ output
POWMAN_IRQ_POW = 44, ///< Select POWMAN's IRQ_POW output
POWMAN_IRQ_TIMER = 45, ///< Select POWMAN's IRQ_TIMER output
SPARE_IRQ_0 = 46, ///< Select SPARE IRQ 0
SPARE_IRQ_1 = 47, ///< Select SPARE IRQ 1
SPARE_IRQ_2 = 48, ///< Select SPARE IRQ 2
SPARE_IRQ_3 = 49, ///< Select SPARE IRQ 3
SPARE_IRQ_4 = 50, ///< Select SPARE IRQ 4
SPARE_IRQ_5 = 51, ///< Select SPARE IRQ 5
IRQ_COUNT
} irq_num_t;
#endif
#define isr_timer0_0 isr_irq0
#define isr_timer0_1 isr_irq1
#define isr_timer0_2 isr_irq2
#define isr_timer0_3 isr_irq3
#define isr_timer1_0 isr_irq4
#define isr_timer1_1 isr_irq5
#define isr_timer1_2 isr_irq6
#define isr_timer1_3 isr_irq7
#define isr_pwm_wrap_0 isr_irq8
#define isr_pwm_wrap_1 isr_irq9
#define isr_dma_0 isr_irq10
#define isr_dma_1 isr_irq11
#define isr_dma_2 isr_irq12
#define isr_dma_3 isr_irq13
#define isr_usbctrl isr_irq14
#define isr_pio0_0 isr_irq15
#define isr_pio0_1 isr_irq16
#define isr_pio1_0 isr_irq17
#define isr_pio1_1 isr_irq18
#define isr_pio2_0 isr_irq19
#define isr_pio2_1 isr_irq20
#define isr_io_bank0 isr_irq21
#define isr_io_bank0_ns isr_irq22
#define isr_io_qspi isr_irq23
#define isr_io_qspi_ns isr_irq24
#define isr_sio_fifo isr_irq25
#define isr_sio_bell isr_irq26
#define isr_sio_fifo_ns isr_irq27
#define isr_sio_bell_ns isr_irq28
#define isr_sio_mtimecmp isr_irq29
#define isr_clocks isr_irq30
#define isr_spi0 isr_irq31
#define isr_spi1 isr_irq32
#define isr_uart0 isr_irq33
#define isr_uart1 isr_irq34
#define isr_adc_fifo isr_irq35
#define isr_i2c0 isr_irq36
#define isr_i2c1 isr_irq37
#define isr_otp isr_irq38
#define isr_trng isr_irq39
#define isr_proc0_cti isr_irq40
#define isr_proc1_cti isr_irq41
#define isr_pll_sys isr_irq42
#define isr_pll_usb isr_irq43
#define isr_powman_pow isr_irq44
#define isr_powman_timer isr_irq45
#define isr_spare_0 isr_irq46
#define isr_spare_1 isr_irq47
#define isr_spare_2 isr_irq48
#define isr_spare_3 isr_irq49
#define isr_spare_4 isr_irq50
#define isr_spare_5 isr_irq51
#endif // _INTCTRL_H

22339
arch/arm/src/rp23xx/hardware/regs/io_bank0.h
View file

File diff suppressed because it is too large Load diff

3663
arch/arm/src/rp23xx/hardware/regs/io_qspi.h
View file

File diff suppressed because it is too large Load diff

8988
arch/arm/src/rp23xx/hardware/regs/m33.h
View file

File diff suppressed because it is too large Load diff

80
arch/arm/src/rp23xx/hardware/regs/m33_eppb.h
View file

@ -1,80 +0,0 @@
// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
// =============================================================================
// Register block : M33_EPPB
// Version : 1
// Bus type : apb
// Description : Cortex-M33 EPPB vendor register block for RP2350
// =============================================================================
#ifndef _HARDWARE_REGS_M33_EPPB_H
#define _HARDWARE_REGS_M33_EPPB_H
// =============================================================================
// Register : M33_EPPB_NMI_MASK0
// Description : NMI mask for IRQs 0 through 31. This register is core-local,
// and is reset by a processor warm reset.
#define M33_EPPB_NMI_MASK0_OFFSET _u(0x00000000)
#define M33_EPPB_NMI_MASK0_BITS _u(0xffffffff)
#define M33_EPPB_NMI_MASK0_RESET _u(0x00000000)
#define M33_EPPB_NMI_MASK0_MSB _u(31)
#define M33_EPPB_NMI_MASK0_LSB _u(0)
#define M33_EPPB_NMI_MASK0_ACCESS "RW"
// =============================================================================
// Register : M33_EPPB_NMI_MASK1
// Description : NMI mask for IRQs 0 though 51. This register is core-local, and
// is reset by a processor warm reset.
#define M33_EPPB_NMI_MASK1_OFFSET _u(0x00000004)
#define M33_EPPB_NMI_MASK1_BITS _u(0x000fffff)
#define M33_EPPB_NMI_MASK1_RESET _u(0x00000000)
#define M33_EPPB_NMI_MASK1_MSB _u(19)
#define M33_EPPB_NMI_MASK1_LSB _u(0)
#define M33_EPPB_NMI_MASK1_ACCESS "RW"
// =============================================================================
// Register : M33_EPPB_SLEEPCTRL
// Description : Nonstandard sleep control register
#define M33_EPPB_SLEEPCTRL_OFFSET _u(0x00000008)
#define M33_EPPB_SLEEPCTRL_BITS _u(0x00000007)
#define M33_EPPB_SLEEPCTRL_RESET _u(0x00000002)
// -----------------------------------------------------------------------------
// Field : M33_EPPB_SLEEPCTRL_WICENACK
// Description : Status signal from the processor's interrupt controller.
// Changes to WICENREQ are eventually reflected in WICENACK.
#define M33_EPPB_SLEEPCTRL_WICENACK_RESET _u(0x0)
#define M33_EPPB_SLEEPCTRL_WICENACK_BITS _u(0x00000004)
#define M33_EPPB_SLEEPCTRL_WICENACK_MSB _u(2)
#define M33_EPPB_SLEEPCTRL_WICENACK_LSB _u(2)
#define M33_EPPB_SLEEPCTRL_WICENACK_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : M33_EPPB_SLEEPCTRL_WICENREQ
// Description : Request that the next processor deep sleep is a WIC sleep.
// After setting this bit, before sleeping, poll WICENACK to
// ensure the processor interrupt controller has acknowledged the
// change.
#define M33_EPPB_SLEEPCTRL_WICENREQ_RESET _u(0x1)
#define M33_EPPB_SLEEPCTRL_WICENREQ_BITS _u(0x00000002)
#define M33_EPPB_SLEEPCTRL_WICENREQ_MSB _u(1)
#define M33_EPPB_SLEEPCTRL_WICENREQ_LSB _u(1)
#define M33_EPPB_SLEEPCTRL_WICENREQ_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : M33_EPPB_SLEEPCTRL_LIGHT_SLEEP
// Description : By default, any processor sleep will deassert the system-level
// clock request. Reenabling the clocks incurs 5 cycles of
// additional latency on wakeup.
//
// Setting LIGHT_SLEEP to 1 keeps the clock request asserted
// during a normal sleep (Arm SCR.SLEEPDEEP = 0), for faster
// wakeup. Processor deep sleep (Arm SCR.SLEEPDEEP = 1) is not
// affected, and will always deassert the system-level clock
// request.
#define M33_EPPB_SLEEPCTRL_LIGHT_SLEEP_RESET _u(0x0)
#define M33_EPPB_SLEEPCTRL_LIGHT_SLEEP_BITS _u(0x00000001)
#define M33_EPPB_SLEEPCTRL_LIGHT_SLEEP_MSB _u(0)
#define M33_EPPB_SLEEPCTRL_LIGHT_SLEEP_LSB _u(0)
#define M33_EPPB_SLEEPCTRL_LIGHT_SLEEP_ACCESS "RW"
// =============================================================================
#endif // _HARDWARE_REGS_M33_EPPB_H

3467
arch/arm/src/rp23xx/hardware/regs/otp.h
View file

File diff suppressed because it is too large Load diff

12373
arch/arm/src/rp23xx/hardware/regs/otp_data.h
View file

File diff suppressed because it is too large Load diff

3980
arch/arm/src/rp23xx/hardware/regs/pads_bank0.h
View file

File diff suppressed because it is too large Load diff

504
arch/arm/src/rp23xx/hardware/regs/pads_qspi.h
View file

@ -1,504 +0,0 @@
// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
// =============================================================================
// Register block : PADS_QSPI
// Version : 1
// Bus type : apb
// =============================================================================
#ifndef _HARDWARE_REGS_PADS_QSPI_H
#define _HARDWARE_REGS_PADS_QSPI_H
// =============================================================================
// Register : PADS_QSPI_VOLTAGE_SELECT
// Description : Voltage select. Per bank control
// 0x0 -> Set voltage to 3.3V (DVDD >= 2V5)
// 0x1 -> Set voltage to 1.8V (DVDD <= 1V8)
#define PADS_QSPI_VOLTAGE_SELECT_OFFSET _u(0x00000000)
#define PADS_QSPI_VOLTAGE_SELECT_BITS _u(0x00000001)
#define PADS_QSPI_VOLTAGE_SELECT_RESET _u(0x00000000)
#define PADS_QSPI_VOLTAGE_SELECT_MSB _u(0)
#define PADS_QSPI_VOLTAGE_SELECT_LSB _u(0)
#define PADS_QSPI_VOLTAGE_SELECT_ACCESS "RW"
#define PADS_QSPI_VOLTAGE_SELECT_VALUE_3V3 _u(0x0)
#define PADS_QSPI_VOLTAGE_SELECT_VALUE_1V8 _u(0x1)
// =============================================================================
// Register : PADS_QSPI_GPIO_QSPI_SCLK
#define PADS_QSPI_GPIO_QSPI_SCLK_OFFSET _u(0x00000004)
#define PADS_QSPI_GPIO_QSPI_SCLK_BITS _u(0x000001ff)
#define PADS_QSPI_GPIO_QSPI_SCLK_RESET _u(0x00000156)
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SCLK_ISO
// Description : Pad isolation control. Remove this once the pad is configured
// by software.
#define PADS_QSPI_GPIO_QSPI_SCLK_ISO_RESET _u(0x1)
#define PADS_QSPI_GPIO_QSPI_SCLK_ISO_BITS _u(0x00000100)
#define PADS_QSPI_GPIO_QSPI_SCLK_ISO_MSB _u(8)
#define PADS_QSPI_GPIO_QSPI_SCLK_ISO_LSB _u(8)
#define PADS_QSPI_GPIO_QSPI_SCLK_ISO_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SCLK_OD
// Description : Output disable. Has priority over output enable from
// peripherals
#define PADS_QSPI_GPIO_QSPI_SCLK_OD_RESET _u(0x0)
#define PADS_QSPI_GPIO_QSPI_SCLK_OD_BITS _u(0x00000080)
#define PADS_QSPI_GPIO_QSPI_SCLK_OD_MSB _u(7)
#define PADS_QSPI_GPIO_QSPI_SCLK_OD_LSB _u(7)
#define PADS_QSPI_GPIO_QSPI_SCLK_OD_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SCLK_IE
// Description : Input enable
#define PADS_QSPI_GPIO_QSPI_SCLK_IE_RESET _u(0x1)
#define PADS_QSPI_GPIO_QSPI_SCLK_IE_BITS _u(0x00000040)
#define PADS_QSPI_GPIO_QSPI_SCLK_IE_MSB _u(6)
#define PADS_QSPI_GPIO_QSPI_SCLK_IE_LSB _u(6)
#define PADS_QSPI_GPIO_QSPI_SCLK_IE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SCLK_DRIVE
// Description : Drive strength.
// 0x0 -> 2mA
// 0x1 -> 4mA
// 0x2 -> 8mA
// 0x3 -> 12mA
#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_RESET _u(0x1)
#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_BITS _u(0x00000030)
#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_MSB _u(5)
#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_LSB _u(4)
#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_ACCESS "RW"
#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_VALUE_2MA _u(0x0)
#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_VALUE_4MA _u(0x1)
#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_VALUE_8MA _u(0x2)
#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_VALUE_12MA _u(0x3)
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SCLK_PUE
// Description : Pull up enable
#define PADS_QSPI_GPIO_QSPI_SCLK_PUE_RESET _u(0x0)
#define PADS_QSPI_GPIO_QSPI_SCLK_PUE_BITS _u(0x00000008)
#define PADS_QSPI_GPIO_QSPI_SCLK_PUE_MSB _u(3)
#define PADS_QSPI_GPIO_QSPI_SCLK_PUE_LSB _u(3)
#define PADS_QSPI_GPIO_QSPI_SCLK_PUE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SCLK_PDE
// Description : Pull down enable
#define PADS_QSPI_GPIO_QSPI_SCLK_PDE_RESET _u(0x1)
#define PADS_QSPI_GPIO_QSPI_SCLK_PDE_BITS _u(0x00000004)
#define PADS_QSPI_GPIO_QSPI_SCLK_PDE_MSB _u(2)
#define PADS_QSPI_GPIO_QSPI_SCLK_PDE_LSB _u(2)
#define PADS_QSPI_GPIO_QSPI_SCLK_PDE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SCLK_SCHMITT
// Description : Enable schmitt trigger
#define PADS_QSPI_GPIO_QSPI_SCLK_SCHMITT_RESET _u(0x1)
#define PADS_QSPI_GPIO_QSPI_SCLK_SCHMITT_BITS _u(0x00000002)
#define PADS_QSPI_GPIO_QSPI_SCLK_SCHMITT_MSB _u(1)
#define PADS_QSPI_GPIO_QSPI_SCLK_SCHMITT_LSB _u(1)
#define PADS_QSPI_GPIO_QSPI_SCLK_SCHMITT_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SCLK_SLEWFAST
// Description : Slew rate control. 1 = Fast, 0 = Slow
#define PADS_QSPI_GPIO_QSPI_SCLK_SLEWFAST_RESET _u(0x0)
#define PADS_QSPI_GPIO_QSPI_SCLK_SLEWFAST_BITS _u(0x00000001)
#define PADS_QSPI_GPIO_QSPI_SCLK_SLEWFAST_MSB _u(0)
#define PADS_QSPI_GPIO_QSPI_SCLK_SLEWFAST_LSB _u(0)
#define PADS_QSPI_GPIO_QSPI_SCLK_SLEWFAST_ACCESS "RW"
// =============================================================================
// Register : PADS_QSPI_GPIO_QSPI_SD0
#define PADS_QSPI_GPIO_QSPI_SD0_OFFSET _u(0x00000008)
#define PADS_QSPI_GPIO_QSPI_SD0_BITS _u(0x000001ff)
#define PADS_QSPI_GPIO_QSPI_SD0_RESET _u(0x00000156)
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD0_ISO
// Description : Pad isolation control. Remove this once the pad is configured
// by software.
#define PADS_QSPI_GPIO_QSPI_SD0_ISO_RESET _u(0x1)
#define PADS_QSPI_GPIO_QSPI_SD0_ISO_BITS _u(0x00000100)
#define PADS_QSPI_GPIO_QSPI_SD0_ISO_MSB _u(8)
#define PADS_QSPI_GPIO_QSPI_SD0_ISO_LSB _u(8)
#define PADS_QSPI_GPIO_QSPI_SD0_ISO_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD0_OD
// Description : Output disable. Has priority over output enable from
// peripherals
#define PADS_QSPI_GPIO_QSPI_SD0_OD_RESET _u(0x0)
#define PADS_QSPI_GPIO_QSPI_SD0_OD_BITS _u(0x00000080)
#define PADS_QSPI_GPIO_QSPI_SD0_OD_MSB _u(7)
#define PADS_QSPI_GPIO_QSPI_SD0_OD_LSB _u(7)
#define PADS_QSPI_GPIO_QSPI_SD0_OD_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD0_IE
// Description : Input enable
#define PADS_QSPI_GPIO_QSPI_SD0_IE_RESET _u(0x1)
#define PADS_QSPI_GPIO_QSPI_SD0_IE_BITS _u(0x00000040)
#define PADS_QSPI_GPIO_QSPI_SD0_IE_MSB _u(6)
#define PADS_QSPI_GPIO_QSPI_SD0_IE_LSB _u(6)
#define PADS_QSPI_GPIO_QSPI_SD0_IE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD0_DRIVE
// Description : Drive strength.
// 0x0 -> 2mA
// 0x1 -> 4mA
// 0x2 -> 8mA
// 0x3 -> 12mA
#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_RESET _u(0x1)
#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_BITS _u(0x00000030)
#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_MSB _u(5)
#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_LSB _u(4)
#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_ACCESS "RW"
#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_VALUE_2MA _u(0x0)
#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_VALUE_4MA _u(0x1)
#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_VALUE_8MA _u(0x2)
#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_VALUE_12MA _u(0x3)
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD0_PUE
// Description : Pull up enable
#define PADS_QSPI_GPIO_QSPI_SD0_PUE_RESET _u(0x0)
#define PADS_QSPI_GPIO_QSPI_SD0_PUE_BITS _u(0x00000008)
#define PADS_QSPI_GPIO_QSPI_SD0_PUE_MSB _u(3)
#define PADS_QSPI_GPIO_QSPI_SD0_PUE_LSB _u(3)
#define PADS_QSPI_GPIO_QSPI_SD0_PUE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD0_PDE
// Description : Pull down enable
#define PADS_QSPI_GPIO_QSPI_SD0_PDE_RESET _u(0x1)
#define PADS_QSPI_GPIO_QSPI_SD0_PDE_BITS _u(0x00000004)
#define PADS_QSPI_GPIO_QSPI_SD0_PDE_MSB _u(2)
#define PADS_QSPI_GPIO_QSPI_SD0_PDE_LSB _u(2)
#define PADS_QSPI_GPIO_QSPI_SD0_PDE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD0_SCHMITT
// Description : Enable schmitt trigger
#define PADS_QSPI_GPIO_QSPI_SD0_SCHMITT_RESET _u(0x1)
#define PADS_QSPI_GPIO_QSPI_SD0_SCHMITT_BITS _u(0x00000002)
#define PADS_QSPI_GPIO_QSPI_SD0_SCHMITT_MSB _u(1)
#define PADS_QSPI_GPIO_QSPI_SD0_SCHMITT_LSB _u(1)
#define PADS_QSPI_GPIO_QSPI_SD0_SCHMITT_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD0_SLEWFAST
// Description : Slew rate control. 1 = Fast, 0 = Slow
#define PADS_QSPI_GPIO_QSPI_SD0_SLEWFAST_RESET _u(0x0)
#define PADS_QSPI_GPIO_QSPI_SD0_SLEWFAST_BITS _u(0x00000001)
#define PADS_QSPI_GPIO_QSPI_SD0_SLEWFAST_MSB _u(0)
#define PADS_QSPI_GPIO_QSPI_SD0_SLEWFAST_LSB _u(0)
#define PADS_QSPI_GPIO_QSPI_SD0_SLEWFAST_ACCESS "RW"
// =============================================================================
// Register : PADS_QSPI_GPIO_QSPI_SD1
#define PADS_QSPI_GPIO_QSPI_SD1_OFFSET _u(0x0000000c)
#define PADS_QSPI_GPIO_QSPI_SD1_BITS _u(0x000001ff)
#define PADS_QSPI_GPIO_QSPI_SD1_RESET _u(0x00000156)
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD1_ISO
// Description : Pad isolation control. Remove this once the pad is configured
// by software.
#define PADS_QSPI_GPIO_QSPI_SD1_ISO_RESET _u(0x1)
#define PADS_QSPI_GPIO_QSPI_SD1_ISO_BITS _u(0x00000100)
#define PADS_QSPI_GPIO_QSPI_SD1_ISO_MSB _u(8)
#define PADS_QSPI_GPIO_QSPI_SD1_ISO_LSB _u(8)
#define PADS_QSPI_GPIO_QSPI_SD1_ISO_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD1_OD
// Description : Output disable. Has priority over output enable from
// peripherals
#define PADS_QSPI_GPIO_QSPI_SD1_OD_RESET _u(0x0)
#define PADS_QSPI_GPIO_QSPI_SD1_OD_BITS _u(0x00000080)
#define PADS_QSPI_GPIO_QSPI_SD1_OD_MSB _u(7)
#define PADS_QSPI_GPIO_QSPI_SD1_OD_LSB _u(7)
#define PADS_QSPI_GPIO_QSPI_SD1_OD_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD1_IE
// Description : Input enable
#define PADS_QSPI_GPIO_QSPI_SD1_IE_RESET _u(0x1)
#define PADS_QSPI_GPIO_QSPI_SD1_IE_BITS _u(0x00000040)
#define PADS_QSPI_GPIO_QSPI_SD1_IE_MSB _u(6)
#define PADS_QSPI_GPIO_QSPI_SD1_IE_LSB _u(6)
#define PADS_QSPI_GPIO_QSPI_SD1_IE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD1_DRIVE
// Description : Drive strength.
// 0x0 -> 2mA
// 0x1 -> 4mA
// 0x2 -> 8mA
// 0x3 -> 12mA
#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_RESET _u(0x1)
#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_BITS _u(0x00000030)
#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_MSB _u(5)
#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_LSB _u(4)
#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_ACCESS "RW"
#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_VALUE_2MA _u(0x0)
#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_VALUE_4MA _u(0x1)
#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_VALUE_8MA _u(0x2)
#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_VALUE_12MA _u(0x3)
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD1_PUE
// Description : Pull up enable
#define PADS_QSPI_GPIO_QSPI_SD1_PUE_RESET _u(0x0)
#define PADS_QSPI_GPIO_QSPI_SD1_PUE_BITS _u(0x00000008)
#define PADS_QSPI_GPIO_QSPI_SD1_PUE_MSB _u(3)
#define PADS_QSPI_GPIO_QSPI_SD1_PUE_LSB _u(3)
#define PADS_QSPI_GPIO_QSPI_SD1_PUE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD1_PDE
// Description : Pull down enable
#define PADS_QSPI_GPIO_QSPI_SD1_PDE_RESET _u(0x1)
#define PADS_QSPI_GPIO_QSPI_SD1_PDE_BITS _u(0x00000004)
#define PADS_QSPI_GPIO_QSPI_SD1_PDE_MSB _u(2)
#define PADS_QSPI_GPIO_QSPI_SD1_PDE_LSB _u(2)
#define PADS_QSPI_GPIO_QSPI_SD1_PDE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD1_SCHMITT
// Description : Enable schmitt trigger
#define PADS_QSPI_GPIO_QSPI_SD1_SCHMITT_RESET _u(0x1)
#define PADS_QSPI_GPIO_QSPI_SD1_SCHMITT_BITS _u(0x00000002)
#define PADS_QSPI_GPIO_QSPI_SD1_SCHMITT_MSB _u(1)
#define PADS_QSPI_GPIO_QSPI_SD1_SCHMITT_LSB _u(1)
#define PADS_QSPI_GPIO_QSPI_SD1_SCHMITT_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD1_SLEWFAST
// Description : Slew rate control. 1 = Fast, 0 = Slow
#define PADS_QSPI_GPIO_QSPI_SD1_SLEWFAST_RESET _u(0x0)
#define PADS_QSPI_GPIO_QSPI_SD1_SLEWFAST_BITS _u(0x00000001)
#define PADS_QSPI_GPIO_QSPI_SD1_SLEWFAST_MSB _u(0)
#define PADS_QSPI_GPIO_QSPI_SD1_SLEWFAST_LSB _u(0)
#define PADS_QSPI_GPIO_QSPI_SD1_SLEWFAST_ACCESS "RW"
// =============================================================================
// Register : PADS_QSPI_GPIO_QSPI_SD2
#define PADS_QSPI_GPIO_QSPI_SD2_OFFSET _u(0x00000010)
#define PADS_QSPI_GPIO_QSPI_SD2_BITS _u(0x000001ff)
#define PADS_QSPI_GPIO_QSPI_SD2_RESET _u(0x0000015a)
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD2_ISO
// Description : Pad isolation control. Remove this once the pad is configured
// by software.
#define PADS_QSPI_GPIO_QSPI_SD2_ISO_RESET _u(0x1)
#define PADS_QSPI_GPIO_QSPI_SD2_ISO_BITS _u(0x00000100)
#define PADS_QSPI_GPIO_QSPI_SD2_ISO_MSB _u(8)
#define PADS_QSPI_GPIO_QSPI_SD2_ISO_LSB _u(8)
#define PADS_QSPI_GPIO_QSPI_SD2_ISO_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD2_OD
// Description : Output disable. Has priority over output enable from
// peripherals
#define PADS_QSPI_GPIO_QSPI_SD2_OD_RESET _u(0x0)
#define PADS_QSPI_GPIO_QSPI_SD2_OD_BITS _u(0x00000080)
#define PADS_QSPI_GPIO_QSPI_SD2_OD_MSB _u(7)
#define PADS_QSPI_GPIO_QSPI_SD2_OD_LSB _u(7)
#define PADS_QSPI_GPIO_QSPI_SD2_OD_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD2_IE
// Description : Input enable
#define PADS_QSPI_GPIO_QSPI_SD2_IE_RESET _u(0x1)
#define PADS_QSPI_GPIO_QSPI_SD2_IE_BITS _u(0x00000040)
#define PADS_QSPI_GPIO_QSPI_SD2_IE_MSB _u(6)
#define PADS_QSPI_GPIO_QSPI_SD2_IE_LSB _u(6)
#define PADS_QSPI_GPIO_QSPI_SD2_IE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD2_DRIVE
// Description : Drive strength.
// 0x0 -> 2mA
// 0x1 -> 4mA
// 0x2 -> 8mA
// 0x3 -> 12mA
#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_RESET _u(0x1)
#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_BITS _u(0x00000030)
#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_MSB _u(5)
#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_LSB _u(4)
#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_ACCESS "RW"
#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_VALUE_2MA _u(0x0)
#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_VALUE_4MA _u(0x1)
#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_VALUE_8MA _u(0x2)
#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_VALUE_12MA _u(0x3)
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD2_PUE
// Description : Pull up enable
#define PADS_QSPI_GPIO_QSPI_SD2_PUE_RESET _u(0x1)
#define PADS_QSPI_GPIO_QSPI_SD2_PUE_BITS _u(0x00000008)
#define PADS_QSPI_GPIO_QSPI_SD2_PUE_MSB _u(3)
#define PADS_QSPI_GPIO_QSPI_SD2_PUE_LSB _u(3)
#define PADS_QSPI_GPIO_QSPI_SD2_PUE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD2_PDE
// Description : Pull down enable
#define PADS_QSPI_GPIO_QSPI_SD2_PDE_RESET _u(0x0)
#define PADS_QSPI_GPIO_QSPI_SD2_PDE_BITS _u(0x00000004)
#define PADS_QSPI_GPIO_QSPI_SD2_PDE_MSB _u(2)
#define PADS_QSPI_GPIO_QSPI_SD2_PDE_LSB _u(2)
#define PADS_QSPI_GPIO_QSPI_SD2_PDE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD2_SCHMITT
// Description : Enable schmitt trigger
#define PADS_QSPI_GPIO_QSPI_SD2_SCHMITT_RESET _u(0x1)
#define PADS_QSPI_GPIO_QSPI_SD2_SCHMITT_BITS _u(0x00000002)
#define PADS_QSPI_GPIO_QSPI_SD2_SCHMITT_MSB _u(1)
#define PADS_QSPI_GPIO_QSPI_SD2_SCHMITT_LSB _u(1)
#define PADS_QSPI_GPIO_QSPI_SD2_SCHMITT_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD2_SLEWFAST
// Description : Slew rate control. 1 = Fast, 0 = Slow
#define PADS_QSPI_GPIO_QSPI_SD2_SLEWFAST_RESET _u(0x0)
#define PADS_QSPI_GPIO_QSPI_SD2_SLEWFAST_BITS _u(0x00000001)
#define PADS_QSPI_GPIO_QSPI_SD2_SLEWFAST_MSB _u(0)
#define PADS_QSPI_GPIO_QSPI_SD2_SLEWFAST_LSB _u(0)
#define PADS_QSPI_GPIO_QSPI_SD2_SLEWFAST_ACCESS "RW"
// =============================================================================
// Register : PADS_QSPI_GPIO_QSPI_SD3
#define PADS_QSPI_GPIO_QSPI_SD3_OFFSET _u(0x00000014)
#define PADS_QSPI_GPIO_QSPI_SD3_BITS _u(0x000001ff)
#define PADS_QSPI_GPIO_QSPI_SD3_RESET _u(0x0000015a)
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD3_ISO
// Description : Pad isolation control. Remove this once the pad is configured
// by software.
#define PADS_QSPI_GPIO_QSPI_SD3_ISO_RESET _u(0x1)
#define PADS_QSPI_GPIO_QSPI_SD3_ISO_BITS _u(0x00000100)
#define PADS_QSPI_GPIO_QSPI_SD3_ISO_MSB _u(8)
#define PADS_QSPI_GPIO_QSPI_SD3_ISO_LSB _u(8)
#define PADS_QSPI_GPIO_QSPI_SD3_ISO_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD3_OD
// Description : Output disable. Has priority over output enable from
// peripherals
#define PADS_QSPI_GPIO_QSPI_SD3_OD_RESET _u(0x0)
#define PADS_QSPI_GPIO_QSPI_SD3_OD_BITS _u(0x00000080)
#define PADS_QSPI_GPIO_QSPI_SD3_OD_MSB _u(7)
#define PADS_QSPI_GPIO_QSPI_SD3_OD_LSB _u(7)
#define PADS_QSPI_GPIO_QSPI_SD3_OD_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD3_IE
// Description : Input enable
#define PADS_QSPI_GPIO_QSPI_SD3_IE_RESET _u(0x1)
#define PADS_QSPI_GPIO_QSPI_SD3_IE_BITS _u(0x00000040)
#define PADS_QSPI_GPIO_QSPI_SD3_IE_MSB _u(6)
#define PADS_QSPI_GPIO_QSPI_SD3_IE_LSB _u(6)
#define PADS_QSPI_GPIO_QSPI_SD3_IE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD3_DRIVE
// Description : Drive strength.
// 0x0 -> 2mA
// 0x1 -> 4mA
// 0x2 -> 8mA
// 0x3 -> 12mA
#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_RESET _u(0x1)
#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_BITS _u(0x00000030)
#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_MSB _u(5)
#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_LSB _u(4)
#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_ACCESS "RW"
#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_VALUE_2MA _u(0x0)
#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_VALUE_4MA _u(0x1)
#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_VALUE_8MA _u(0x2)
#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_VALUE_12MA _u(0x3)
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD3_PUE
// Description : Pull up enable
#define PADS_QSPI_GPIO_QSPI_SD3_PUE_RESET _u(0x1)
#define PADS_QSPI_GPIO_QSPI_SD3_PUE_BITS _u(0x00000008)
#define PADS_QSPI_GPIO_QSPI_SD3_PUE_MSB _u(3)
#define PADS_QSPI_GPIO_QSPI_SD3_PUE_LSB _u(3)
#define PADS_QSPI_GPIO_QSPI_SD3_PUE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD3_PDE
// Description : Pull down enable
#define PADS_QSPI_GPIO_QSPI_SD3_PDE_RESET _u(0x0)
#define PADS_QSPI_GPIO_QSPI_SD3_PDE_BITS _u(0x00000004)
#define PADS_QSPI_GPIO_QSPI_SD3_PDE_MSB _u(2)
#define PADS_QSPI_GPIO_QSPI_SD3_PDE_LSB _u(2)
#define PADS_QSPI_GPIO_QSPI_SD3_PDE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD3_SCHMITT
// Description : Enable schmitt trigger
#define PADS_QSPI_GPIO_QSPI_SD3_SCHMITT_RESET _u(0x1)
#define PADS_QSPI_GPIO_QSPI_SD3_SCHMITT_BITS _u(0x00000002)
#define PADS_QSPI_GPIO_QSPI_SD3_SCHMITT_MSB _u(1)
#define PADS_QSPI_GPIO_QSPI_SD3_SCHMITT_LSB _u(1)
#define PADS_QSPI_GPIO_QSPI_SD3_SCHMITT_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD3_SLEWFAST
// Description : Slew rate control. 1 = Fast, 0 = Slow
#define PADS_QSPI_GPIO_QSPI_SD3_SLEWFAST_RESET _u(0x0)
#define PADS_QSPI_GPIO_QSPI_SD3_SLEWFAST_BITS _u(0x00000001)
#define PADS_QSPI_GPIO_QSPI_SD3_SLEWFAST_MSB _u(0)
#define PADS_QSPI_GPIO_QSPI_SD3_SLEWFAST_LSB _u(0)
#define PADS_QSPI_GPIO_QSPI_SD3_SLEWFAST_ACCESS "RW"
// =============================================================================
// Register : PADS_QSPI_GPIO_QSPI_SS
#define PADS_QSPI_GPIO_QSPI_SS_OFFSET _u(0x00000018)
#define PADS_QSPI_GPIO_QSPI_SS_BITS _u(0x000001ff)
#define PADS_QSPI_GPIO_QSPI_SS_RESET _u(0x0000015a)
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SS_ISO
// Description : Pad isolation control. Remove this once the pad is configured
// by software.
#define PADS_QSPI_GPIO_QSPI_SS_ISO_RESET _u(0x1)
#define PADS_QSPI_GPIO_QSPI_SS_ISO_BITS _u(0x00000100)
#define PADS_QSPI_GPIO_QSPI_SS_ISO_MSB _u(8)
#define PADS_QSPI_GPIO_QSPI_SS_ISO_LSB _u(8)
#define PADS_QSPI_GPIO_QSPI_SS_ISO_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SS_OD
// Description : Output disable. Has priority over output enable from
// peripherals
#define PADS_QSPI_GPIO_QSPI_SS_OD_RESET _u(0x0)
#define PADS_QSPI_GPIO_QSPI_SS_OD_BITS _u(0x00000080)
#define PADS_QSPI_GPIO_QSPI_SS_OD_MSB _u(7)
#define PADS_QSPI_GPIO_QSPI_SS_OD_LSB _u(7)
#define PADS_QSPI_GPIO_QSPI_SS_OD_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SS_IE
// Description : Input enable
#define PADS_QSPI_GPIO_QSPI_SS_IE_RESET _u(0x1)
#define PADS_QSPI_GPIO_QSPI_SS_IE_BITS _u(0x00000040)
#define PADS_QSPI_GPIO_QSPI_SS_IE_MSB _u(6)
#define PADS_QSPI_GPIO_QSPI_SS_IE_LSB _u(6)
#define PADS_QSPI_GPIO_QSPI_SS_IE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SS_DRIVE
// Description : Drive strength.
// 0x0 -> 2mA
// 0x1 -> 4mA
// 0x2 -> 8mA
// 0x3 -> 12mA
#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_RESET _u(0x1)
#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_BITS _u(0x00000030)
#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_MSB _u(5)
#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_LSB _u(4)
#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_ACCESS "RW"
#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_VALUE_2MA _u(0x0)
#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_VALUE_4MA _u(0x1)
#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_VALUE_8MA _u(0x2)
#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_VALUE_12MA _u(0x3)
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SS_PUE
// Description : Pull up enable
#define PADS_QSPI_GPIO_QSPI_SS_PUE_RESET _u(0x1)
#define PADS_QSPI_GPIO_QSPI_SS_PUE_BITS _u(0x00000008)
#define PADS_QSPI_GPIO_QSPI_SS_PUE_MSB _u(3)
#define PADS_QSPI_GPIO_QSPI_SS_PUE_LSB _u(3)
#define PADS_QSPI_GPIO_QSPI_SS_PUE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SS_PDE
// Description : Pull down enable
#define PADS_QSPI_GPIO_QSPI_SS_PDE_RESET _u(0x0)
#define PADS_QSPI_GPIO_QSPI_SS_PDE_BITS _u(0x00000004)
#define PADS_QSPI_GPIO_QSPI_SS_PDE_MSB _u(2)
#define PADS_QSPI_GPIO_QSPI_SS_PDE_LSB _u(2)
#define PADS_QSPI_GPIO_QSPI_SS_PDE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SS_SCHMITT
// Description : Enable schmitt trigger
#define PADS_QSPI_GPIO_QSPI_SS_SCHMITT_RESET _u(0x1)
#define PADS_QSPI_GPIO_QSPI_SS_SCHMITT_BITS _u(0x00000002)
#define PADS_QSPI_GPIO_QSPI_SS_SCHMITT_MSB _u(1)
#define PADS_QSPI_GPIO_QSPI_SS_SCHMITT_LSB _u(1)
#define PADS_QSPI_GPIO_QSPI_SS_SCHMITT_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SS_SLEWFAST
// Description : Slew rate control. 1 = Fast, 0 = Slow
#define PADS_QSPI_GPIO_QSPI_SS_SLEWFAST_RESET _u(0x0)
#define PADS_QSPI_GPIO_QSPI_SS_SLEWFAST_BITS _u(0x00000001)
#define PADS_QSPI_GPIO_QSPI_SS_SLEWFAST_MSB _u(0)
#define PADS_QSPI_GPIO_QSPI_SS_SLEWFAST_LSB _u(0)
#define PADS_QSPI_GPIO_QSPI_SS_SLEWFAST_ACCESS "RW"
// =============================================================================
#endif // _HARDWARE_REGS_PADS_QSPI_H

3417
arch/arm/src/rp23xx/hardware/regs/pio.h
View file

File diff suppressed because it is too large Load diff

199
arch/arm/src/rp23xx/hardware/regs/pll.h
View file

@ -1,199 +0,0 @@
// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
// =============================================================================
// Register block : PLL
// Version : 1
// Bus type : apb
// =============================================================================
#ifndef _HARDWARE_REGS_PLL_H
#define _HARDWARE_REGS_PLL_H
// =============================================================================
// Register : PLL_CS
// Description : Control and Status
// GENERAL CONSTRAINTS:
// Reference clock frequency min=5MHz, max=800MHz
// Feedback divider min=16, max=320
// VCO frequency min=750MHz, max=1600MHz
#define PLL_CS_OFFSET _u(0x00000000)
#define PLL_CS_BITS _u(0xc000013f)
#define PLL_CS_RESET _u(0x00000001)
// -----------------------------------------------------------------------------
// Field : PLL_CS_LOCK
// Description : PLL is locked
#define PLL_CS_LOCK_RESET _u(0x0)
#define PLL_CS_LOCK_BITS _u(0x80000000)
#define PLL_CS_LOCK_MSB _u(31)
#define PLL_CS_LOCK_LSB _u(31)
#define PLL_CS_LOCK_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PLL_CS_LOCK_N
// Description : PLL is not locked
// Ideally this is cleared when PLL lock is seen and this should
// never normally be set
#define PLL_CS_LOCK_N_RESET _u(0x0)
#define PLL_CS_LOCK_N_BITS _u(0x40000000)
#define PLL_CS_LOCK_N_MSB _u(30)
#define PLL_CS_LOCK_N_LSB _u(30)
#define PLL_CS_LOCK_N_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : PLL_CS_BYPASS
// Description : Passes the reference clock to the output instead of the divided
// VCO. The VCO continues to run so the user can switch between
// the reference clock and the divided VCO but the output will
// glitch when doing so.
#define PLL_CS_BYPASS_RESET _u(0x0)
#define PLL_CS_BYPASS_BITS _u(0x00000100)
#define PLL_CS_BYPASS_MSB _u(8)
#define PLL_CS_BYPASS_LSB _u(8)
#define PLL_CS_BYPASS_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PLL_CS_REFDIV
// Description : Divides the PLL input reference clock.
// Behaviour is undefined for div=0.
// PLL output will be unpredictable during refdiv changes, wait
// for lock=1 before using it.
#define PLL_CS_REFDIV_RESET _u(0x01)
#define PLL_CS_REFDIV_BITS _u(0x0000003f)
#define PLL_CS_REFDIV_MSB _u(5)
#define PLL_CS_REFDIV_LSB _u(0)
#define PLL_CS_REFDIV_ACCESS "RW"
// =============================================================================
// Register : PLL_PWR
// Description : Controls the PLL power modes.
#define PLL_PWR_OFFSET _u(0x00000004)
#define PLL_PWR_BITS _u(0x0000002d)
#define PLL_PWR_RESET _u(0x0000002d)
// -----------------------------------------------------------------------------
// Field : PLL_PWR_VCOPD
// Description : PLL VCO powerdown
// To save power set high when PLL output not required or
// bypass=1.
#define PLL_PWR_VCOPD_RESET _u(0x1)
#define PLL_PWR_VCOPD_BITS _u(0x00000020)
#define PLL_PWR_VCOPD_MSB _u(5)
#define PLL_PWR_VCOPD_LSB _u(5)
#define PLL_PWR_VCOPD_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PLL_PWR_POSTDIVPD
// Description : PLL post divider powerdown
// To save power set high when PLL output not required or
// bypass=1.
#define PLL_PWR_POSTDIVPD_RESET _u(0x1)
#define PLL_PWR_POSTDIVPD_BITS _u(0x00000008)
#define PLL_PWR_POSTDIVPD_MSB _u(3)
#define PLL_PWR_POSTDIVPD_LSB _u(3)
#define PLL_PWR_POSTDIVPD_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PLL_PWR_DSMPD
// Description : PLL DSM powerdown
// Nothing is achieved by setting this low.
#define PLL_PWR_DSMPD_RESET _u(0x1)
#define PLL_PWR_DSMPD_BITS _u(0x00000004)
#define PLL_PWR_DSMPD_MSB _u(2)
#define PLL_PWR_DSMPD_LSB _u(2)
#define PLL_PWR_DSMPD_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PLL_PWR_PD
// Description : PLL powerdown
// To save power set high when PLL output not required.
#define PLL_PWR_PD_RESET _u(0x1)
#define PLL_PWR_PD_BITS _u(0x00000001)
#define PLL_PWR_PD_MSB _u(0)
#define PLL_PWR_PD_LSB _u(0)
#define PLL_PWR_PD_ACCESS "RW"
// =============================================================================
// Register : PLL_FBDIV_INT
// Description : Feedback divisor
// (note: this PLL does not support fractional division)
// see ctrl reg description for constraints
#define PLL_FBDIV_INT_OFFSET _u(0x00000008)
#define PLL_FBDIV_INT_BITS _u(0x00000fff)
#define PLL_FBDIV_INT_RESET _u(0x00000000)
#define PLL_FBDIV_INT_MSB _u(11)
#define PLL_FBDIV_INT_LSB _u(0)
#define PLL_FBDIV_INT_ACCESS "RW"
// =============================================================================
// Register : PLL_PRIM
// Description : Controls the PLL post dividers for the primary output
// (note: this PLL does not have a secondary output)
// the primary output is driven from VCO divided by
// postdiv1*postdiv2
#define PLL_PRIM_OFFSET _u(0x0000000c)
#define PLL_PRIM_BITS _u(0x00077000)
#define PLL_PRIM_RESET _u(0x00077000)
// -----------------------------------------------------------------------------
// Field : PLL_PRIM_POSTDIV1
// Description : divide by 1-7
#define PLL_PRIM_POSTDIV1_RESET _u(0x7)
#define PLL_PRIM_POSTDIV1_BITS _u(0x00070000)
#define PLL_PRIM_POSTDIV1_MSB _u(18)
#define PLL_PRIM_POSTDIV1_LSB _u(16)
#define PLL_PRIM_POSTDIV1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PLL_PRIM_POSTDIV2
// Description : divide by 1-7
#define PLL_PRIM_POSTDIV2_RESET _u(0x7)
#define PLL_PRIM_POSTDIV2_BITS _u(0x00007000)
#define PLL_PRIM_POSTDIV2_MSB _u(14)
#define PLL_PRIM_POSTDIV2_LSB _u(12)
#define PLL_PRIM_POSTDIV2_ACCESS "RW"
// =============================================================================
// Register : PLL_INTR
// Description : Raw Interrupts
#define PLL_INTR_OFFSET _u(0x00000010)
#define PLL_INTR_BITS _u(0x00000001)
#define PLL_INTR_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : PLL_INTR_LOCK_N_STICKY
#define PLL_INTR_LOCK_N_STICKY_RESET _u(0x0)
#define PLL_INTR_LOCK_N_STICKY_BITS _u(0x00000001)
#define PLL_INTR_LOCK_N_STICKY_MSB _u(0)
#define PLL_INTR_LOCK_N_STICKY_LSB _u(0)
#define PLL_INTR_LOCK_N_STICKY_ACCESS "WC"
// =============================================================================
// Register : PLL_INTE
// Description : Interrupt Enable
#define PLL_INTE_OFFSET _u(0x00000014)
#define PLL_INTE_BITS _u(0x00000001)
#define PLL_INTE_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : PLL_INTE_LOCK_N_STICKY
#define PLL_INTE_LOCK_N_STICKY_RESET _u(0x0)
#define PLL_INTE_LOCK_N_STICKY_BITS _u(0x00000001)
#define PLL_INTE_LOCK_N_STICKY_MSB _u(0)
#define PLL_INTE_LOCK_N_STICKY_LSB _u(0)
#define PLL_INTE_LOCK_N_STICKY_ACCESS "RW"
// =============================================================================
// Register : PLL_INTF
// Description : Interrupt Force
#define PLL_INTF_OFFSET _u(0x00000018)
#define PLL_INTF_BITS _u(0x00000001)
#define PLL_INTF_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : PLL_INTF_LOCK_N_STICKY
#define PLL_INTF_LOCK_N_STICKY_RESET _u(0x0)
#define PLL_INTF_LOCK_N_STICKY_BITS _u(0x00000001)
#define PLL_INTF_LOCK_N_STICKY_MSB _u(0)
#define PLL_INTF_LOCK_N_STICKY_LSB _u(0)
#define PLL_INTF_LOCK_N_STICKY_ACCESS "RW"
// =============================================================================
// Register : PLL_INTS
// Description : Interrupt status after masking & forcing
#define PLL_INTS_OFFSET _u(0x0000001c)
#define PLL_INTS_BITS _u(0x00000001)
#define PLL_INTS_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : PLL_INTS_LOCK_N_STICKY
#define PLL_INTS_LOCK_N_STICKY_RESET _u(0x0)
#define PLL_INTS_LOCK_N_STICKY_BITS _u(0x00000001)
#define PLL_INTS_LOCK_N_STICKY_MSB _u(0)
#define PLL_INTS_LOCK_N_STICKY_LSB _u(0)
#define PLL_INTS_LOCK_N_STICKY_ACCESS "RO"
// =============================================================================
#endif // _HARDWARE_REGS_PLL_H

2194
arch/arm/src/rp23xx/hardware/regs/powman.h
View file

File diff suppressed because it is too large Load diff

741
arch/arm/src/rp23xx/hardware/regs/psm.h
View file

@ -1,741 +0,0 @@
// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
// =============================================================================
// Register block : PSM
// Version : 1
// Bus type : apb
// =============================================================================
#ifndef _HARDWARE_REGS_PSM_H
#define _HARDWARE_REGS_PSM_H
// =============================================================================
// Register : PSM_FRCE_ON
// Description : Force block out of reset (i.e. power it on)
#define PSM_FRCE_ON_OFFSET _u(0x00000000)
#define PSM_FRCE_ON_BITS _u(0x01ffffff)
#define PSM_FRCE_ON_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_ON_PROC1
#define PSM_FRCE_ON_PROC1_RESET _u(0x0)
#define PSM_FRCE_ON_PROC1_BITS _u(0x01000000)
#define PSM_FRCE_ON_PROC1_MSB _u(24)
#define PSM_FRCE_ON_PROC1_LSB _u(24)
#define PSM_FRCE_ON_PROC1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_ON_PROC0
#define PSM_FRCE_ON_PROC0_RESET _u(0x0)
#define PSM_FRCE_ON_PROC0_BITS _u(0x00800000)
#define PSM_FRCE_ON_PROC0_MSB _u(23)
#define PSM_FRCE_ON_PROC0_LSB _u(23)
#define PSM_FRCE_ON_PROC0_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_ON_ACCESSCTRL
#define PSM_FRCE_ON_ACCESSCTRL_RESET _u(0x0)
#define PSM_FRCE_ON_ACCESSCTRL_BITS _u(0x00400000)
#define PSM_FRCE_ON_ACCESSCTRL_MSB _u(22)
#define PSM_FRCE_ON_ACCESSCTRL_LSB _u(22)
#define PSM_FRCE_ON_ACCESSCTRL_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_ON_SIO
#define PSM_FRCE_ON_SIO_RESET _u(0x0)
#define PSM_FRCE_ON_SIO_BITS _u(0x00200000)
#define PSM_FRCE_ON_SIO_MSB _u(21)
#define PSM_FRCE_ON_SIO_LSB _u(21)
#define PSM_FRCE_ON_SIO_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_ON_XIP
#define PSM_FRCE_ON_XIP_RESET _u(0x0)
#define PSM_FRCE_ON_XIP_BITS _u(0x00100000)
#define PSM_FRCE_ON_XIP_MSB _u(20)
#define PSM_FRCE_ON_XIP_LSB _u(20)
#define PSM_FRCE_ON_XIP_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_ON_SRAM9
#define PSM_FRCE_ON_SRAM9_RESET _u(0x0)
#define PSM_FRCE_ON_SRAM9_BITS _u(0x00080000)
#define PSM_FRCE_ON_SRAM9_MSB _u(19)
#define PSM_FRCE_ON_SRAM9_LSB _u(19)
#define PSM_FRCE_ON_SRAM9_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_ON_SRAM8
#define PSM_FRCE_ON_SRAM8_RESET _u(0x0)
#define PSM_FRCE_ON_SRAM8_BITS _u(0x00040000)
#define PSM_FRCE_ON_SRAM8_MSB _u(18)
#define PSM_FRCE_ON_SRAM8_LSB _u(18)
#define PSM_FRCE_ON_SRAM8_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_ON_SRAM7
#define PSM_FRCE_ON_SRAM7_RESET _u(0x0)
#define PSM_FRCE_ON_SRAM7_BITS _u(0x00020000)
#define PSM_FRCE_ON_SRAM7_MSB _u(17)
#define PSM_FRCE_ON_SRAM7_LSB _u(17)
#define PSM_FRCE_ON_SRAM7_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_ON_SRAM6
#define PSM_FRCE_ON_SRAM6_RESET _u(0x0)
#define PSM_FRCE_ON_SRAM6_BITS _u(0x00010000)
#define PSM_FRCE_ON_SRAM6_MSB _u(16)
#define PSM_FRCE_ON_SRAM6_LSB _u(16)
#define PSM_FRCE_ON_SRAM6_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_ON_SRAM5
#define PSM_FRCE_ON_SRAM5_RESET _u(0x0)
#define PSM_FRCE_ON_SRAM5_BITS _u(0x00008000)
#define PSM_FRCE_ON_SRAM5_MSB _u(15)
#define PSM_FRCE_ON_SRAM5_LSB _u(15)
#define PSM_FRCE_ON_SRAM5_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_ON_SRAM4
#define PSM_FRCE_ON_SRAM4_RESET _u(0x0)
#define PSM_FRCE_ON_SRAM4_BITS _u(0x00004000)
#define PSM_FRCE_ON_SRAM4_MSB _u(14)
#define PSM_FRCE_ON_SRAM4_LSB _u(14)
#define PSM_FRCE_ON_SRAM4_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_ON_SRAM3
#define PSM_FRCE_ON_SRAM3_RESET _u(0x0)
#define PSM_FRCE_ON_SRAM3_BITS _u(0x00002000)
#define PSM_FRCE_ON_SRAM3_MSB _u(13)
#define PSM_FRCE_ON_SRAM3_LSB _u(13)
#define PSM_FRCE_ON_SRAM3_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_ON_SRAM2
#define PSM_FRCE_ON_SRAM2_RESET _u(0x0)
#define PSM_FRCE_ON_SRAM2_BITS _u(0x00001000)
#define PSM_FRCE_ON_SRAM2_MSB _u(12)
#define PSM_FRCE_ON_SRAM2_LSB _u(12)
#define PSM_FRCE_ON_SRAM2_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_ON_SRAM1
#define PSM_FRCE_ON_SRAM1_RESET _u(0x0)
#define PSM_FRCE_ON_SRAM1_BITS _u(0x00000800)
#define PSM_FRCE_ON_SRAM1_MSB _u(11)
#define PSM_FRCE_ON_SRAM1_LSB _u(11)
#define PSM_FRCE_ON_SRAM1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_ON_SRAM0
#define PSM_FRCE_ON_SRAM0_RESET _u(0x0)
#define PSM_FRCE_ON_SRAM0_BITS _u(0x00000400)
#define PSM_FRCE_ON_SRAM0_MSB _u(10)
#define PSM_FRCE_ON_SRAM0_LSB _u(10)
#define PSM_FRCE_ON_SRAM0_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_ON_BOOTRAM
#define PSM_FRCE_ON_BOOTRAM_RESET _u(0x0)
#define PSM_FRCE_ON_BOOTRAM_BITS _u(0x00000200)
#define PSM_FRCE_ON_BOOTRAM_MSB _u(9)
#define PSM_FRCE_ON_BOOTRAM_LSB _u(9)
#define PSM_FRCE_ON_BOOTRAM_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_ON_ROM
#define PSM_FRCE_ON_ROM_RESET _u(0x0)
#define PSM_FRCE_ON_ROM_BITS _u(0x00000100)
#define PSM_FRCE_ON_ROM_MSB _u(8)
#define PSM_FRCE_ON_ROM_LSB _u(8)
#define PSM_FRCE_ON_ROM_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_ON_BUSFABRIC
#define PSM_FRCE_ON_BUSFABRIC_RESET _u(0x0)
#define PSM_FRCE_ON_BUSFABRIC_BITS _u(0x00000080)
#define PSM_FRCE_ON_BUSFABRIC_MSB _u(7)
#define PSM_FRCE_ON_BUSFABRIC_LSB _u(7)
#define PSM_FRCE_ON_BUSFABRIC_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_ON_PSM_READY
#define PSM_FRCE_ON_PSM_READY_RESET _u(0x0)
#define PSM_FRCE_ON_PSM_READY_BITS _u(0x00000040)
#define PSM_FRCE_ON_PSM_READY_MSB _u(6)
#define PSM_FRCE_ON_PSM_READY_LSB _u(6)
#define PSM_FRCE_ON_PSM_READY_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_ON_CLOCKS
#define PSM_FRCE_ON_CLOCKS_RESET _u(0x0)
#define PSM_FRCE_ON_CLOCKS_BITS _u(0x00000020)
#define PSM_FRCE_ON_CLOCKS_MSB _u(5)
#define PSM_FRCE_ON_CLOCKS_LSB _u(5)
#define PSM_FRCE_ON_CLOCKS_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_ON_RESETS
#define PSM_FRCE_ON_RESETS_RESET _u(0x0)
#define PSM_FRCE_ON_RESETS_BITS _u(0x00000010)
#define PSM_FRCE_ON_RESETS_MSB _u(4)
#define PSM_FRCE_ON_RESETS_LSB _u(4)
#define PSM_FRCE_ON_RESETS_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_ON_XOSC
#define PSM_FRCE_ON_XOSC_RESET _u(0x0)
#define PSM_FRCE_ON_XOSC_BITS _u(0x00000008)
#define PSM_FRCE_ON_XOSC_MSB _u(3)
#define PSM_FRCE_ON_XOSC_LSB _u(3)
#define PSM_FRCE_ON_XOSC_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_ON_ROSC
#define PSM_FRCE_ON_ROSC_RESET _u(0x0)
#define PSM_FRCE_ON_ROSC_BITS _u(0x00000004)
#define PSM_FRCE_ON_ROSC_MSB _u(2)
#define PSM_FRCE_ON_ROSC_LSB _u(2)
#define PSM_FRCE_ON_ROSC_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_ON_OTP
#define PSM_FRCE_ON_OTP_RESET _u(0x0)
#define PSM_FRCE_ON_OTP_BITS _u(0x00000002)
#define PSM_FRCE_ON_OTP_MSB _u(1)
#define PSM_FRCE_ON_OTP_LSB _u(1)
#define PSM_FRCE_ON_OTP_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_ON_PROC_COLD
#define PSM_FRCE_ON_PROC_COLD_RESET _u(0x0)
#define PSM_FRCE_ON_PROC_COLD_BITS _u(0x00000001)
#define PSM_FRCE_ON_PROC_COLD_MSB _u(0)
#define PSM_FRCE_ON_PROC_COLD_LSB _u(0)
#define PSM_FRCE_ON_PROC_COLD_ACCESS "RW"
// =============================================================================
// Register : PSM_FRCE_OFF
// Description : Force into reset (i.e. power it off)
#define PSM_FRCE_OFF_OFFSET _u(0x00000004)
#define PSM_FRCE_OFF_BITS _u(0x01ffffff)
#define PSM_FRCE_OFF_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_OFF_PROC1
#define PSM_FRCE_OFF_PROC1_RESET _u(0x0)
#define PSM_FRCE_OFF_PROC1_BITS _u(0x01000000)
#define PSM_FRCE_OFF_PROC1_MSB _u(24)
#define PSM_FRCE_OFF_PROC1_LSB _u(24)
#define PSM_FRCE_OFF_PROC1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_OFF_PROC0
#define PSM_FRCE_OFF_PROC0_RESET _u(0x0)
#define PSM_FRCE_OFF_PROC0_BITS _u(0x00800000)
#define PSM_FRCE_OFF_PROC0_MSB _u(23)
#define PSM_FRCE_OFF_PROC0_LSB _u(23)
#define PSM_FRCE_OFF_PROC0_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_OFF_ACCESSCTRL
#define PSM_FRCE_OFF_ACCESSCTRL_RESET _u(0x0)
#define PSM_FRCE_OFF_ACCESSCTRL_BITS _u(0x00400000)
#define PSM_FRCE_OFF_ACCESSCTRL_MSB _u(22)
#define PSM_FRCE_OFF_ACCESSCTRL_LSB _u(22)
#define PSM_FRCE_OFF_ACCESSCTRL_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_OFF_SIO
#define PSM_FRCE_OFF_SIO_RESET _u(0x0)
#define PSM_FRCE_OFF_SIO_BITS _u(0x00200000)
#define PSM_FRCE_OFF_SIO_MSB _u(21)
#define PSM_FRCE_OFF_SIO_LSB _u(21)
#define PSM_FRCE_OFF_SIO_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_OFF_XIP
#define PSM_FRCE_OFF_XIP_RESET _u(0x0)
#define PSM_FRCE_OFF_XIP_BITS _u(0x00100000)
#define PSM_FRCE_OFF_XIP_MSB _u(20)
#define PSM_FRCE_OFF_XIP_LSB _u(20)
#define PSM_FRCE_OFF_XIP_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_OFF_SRAM9
#define PSM_FRCE_OFF_SRAM9_RESET _u(0x0)
#define PSM_FRCE_OFF_SRAM9_BITS _u(0x00080000)
#define PSM_FRCE_OFF_SRAM9_MSB _u(19)
#define PSM_FRCE_OFF_SRAM9_LSB _u(19)
#define PSM_FRCE_OFF_SRAM9_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_OFF_SRAM8
#define PSM_FRCE_OFF_SRAM8_RESET _u(0x0)
#define PSM_FRCE_OFF_SRAM8_BITS _u(0x00040000)
#define PSM_FRCE_OFF_SRAM8_MSB _u(18)
#define PSM_FRCE_OFF_SRAM8_LSB _u(18)
#define PSM_FRCE_OFF_SRAM8_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_OFF_SRAM7
#define PSM_FRCE_OFF_SRAM7_RESET _u(0x0)
#define PSM_FRCE_OFF_SRAM7_BITS _u(0x00020000)
#define PSM_FRCE_OFF_SRAM7_MSB _u(17)
#define PSM_FRCE_OFF_SRAM7_LSB _u(17)
#define PSM_FRCE_OFF_SRAM7_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_OFF_SRAM6
#define PSM_FRCE_OFF_SRAM6_RESET _u(0x0)
#define PSM_FRCE_OFF_SRAM6_BITS _u(0x00010000)
#define PSM_FRCE_OFF_SRAM6_MSB _u(16)
#define PSM_FRCE_OFF_SRAM6_LSB _u(16)
#define PSM_FRCE_OFF_SRAM6_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_OFF_SRAM5
#define PSM_FRCE_OFF_SRAM5_RESET _u(0x0)
#define PSM_FRCE_OFF_SRAM5_BITS _u(0x00008000)
#define PSM_FRCE_OFF_SRAM5_MSB _u(15)
#define PSM_FRCE_OFF_SRAM5_LSB _u(15)
#define PSM_FRCE_OFF_SRAM5_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_OFF_SRAM4
#define PSM_FRCE_OFF_SRAM4_RESET _u(0x0)
#define PSM_FRCE_OFF_SRAM4_BITS _u(0x00004000)
#define PSM_FRCE_OFF_SRAM4_MSB _u(14)
#define PSM_FRCE_OFF_SRAM4_LSB _u(14)
#define PSM_FRCE_OFF_SRAM4_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_OFF_SRAM3
#define PSM_FRCE_OFF_SRAM3_RESET _u(0x0)
#define PSM_FRCE_OFF_SRAM3_BITS _u(0x00002000)
#define PSM_FRCE_OFF_SRAM3_MSB _u(13)
#define PSM_FRCE_OFF_SRAM3_LSB _u(13)
#define PSM_FRCE_OFF_SRAM3_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_OFF_SRAM2
#define PSM_FRCE_OFF_SRAM2_RESET _u(0x0)
#define PSM_FRCE_OFF_SRAM2_BITS _u(0x00001000)
#define PSM_FRCE_OFF_SRAM2_MSB _u(12)
#define PSM_FRCE_OFF_SRAM2_LSB _u(12)
#define PSM_FRCE_OFF_SRAM2_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_OFF_SRAM1
#define PSM_FRCE_OFF_SRAM1_RESET _u(0x0)
#define PSM_FRCE_OFF_SRAM1_BITS _u(0x00000800)
#define PSM_FRCE_OFF_SRAM1_MSB _u(11)
#define PSM_FRCE_OFF_SRAM1_LSB _u(11)
#define PSM_FRCE_OFF_SRAM1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_OFF_SRAM0
#define PSM_FRCE_OFF_SRAM0_RESET _u(0x0)
#define PSM_FRCE_OFF_SRAM0_BITS _u(0x00000400)
#define PSM_FRCE_OFF_SRAM0_MSB _u(10)
#define PSM_FRCE_OFF_SRAM0_LSB _u(10)
#define PSM_FRCE_OFF_SRAM0_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_OFF_BOOTRAM
#define PSM_FRCE_OFF_BOOTRAM_RESET _u(0x0)
#define PSM_FRCE_OFF_BOOTRAM_BITS _u(0x00000200)
#define PSM_FRCE_OFF_BOOTRAM_MSB _u(9)
#define PSM_FRCE_OFF_BOOTRAM_LSB _u(9)
#define PSM_FRCE_OFF_BOOTRAM_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_OFF_ROM
#define PSM_FRCE_OFF_ROM_RESET _u(0x0)
#define PSM_FRCE_OFF_ROM_BITS _u(0x00000100)
#define PSM_FRCE_OFF_ROM_MSB _u(8)
#define PSM_FRCE_OFF_ROM_LSB _u(8)
#define PSM_FRCE_OFF_ROM_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_OFF_BUSFABRIC
#define PSM_FRCE_OFF_BUSFABRIC_RESET _u(0x0)
#define PSM_FRCE_OFF_BUSFABRIC_BITS _u(0x00000080)
#define PSM_FRCE_OFF_BUSFABRIC_MSB _u(7)
#define PSM_FRCE_OFF_BUSFABRIC_LSB _u(7)
#define PSM_FRCE_OFF_BUSFABRIC_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_OFF_PSM_READY
#define PSM_FRCE_OFF_PSM_READY_RESET _u(0x0)
#define PSM_FRCE_OFF_PSM_READY_BITS _u(0x00000040)
#define PSM_FRCE_OFF_PSM_READY_MSB _u(6)
#define PSM_FRCE_OFF_PSM_READY_LSB _u(6)
#define PSM_FRCE_OFF_PSM_READY_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_OFF_CLOCKS
#define PSM_FRCE_OFF_CLOCKS_RESET _u(0x0)
#define PSM_FRCE_OFF_CLOCKS_BITS _u(0x00000020)
#define PSM_FRCE_OFF_CLOCKS_MSB _u(5)
#define PSM_FRCE_OFF_CLOCKS_LSB _u(5)
#define PSM_FRCE_OFF_CLOCKS_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_OFF_RESETS
#define PSM_FRCE_OFF_RESETS_RESET _u(0x0)
#define PSM_FRCE_OFF_RESETS_BITS _u(0x00000010)
#define PSM_FRCE_OFF_RESETS_MSB _u(4)
#define PSM_FRCE_OFF_RESETS_LSB _u(4)
#define PSM_FRCE_OFF_RESETS_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_OFF_XOSC
#define PSM_FRCE_OFF_XOSC_RESET _u(0x0)
#define PSM_FRCE_OFF_XOSC_BITS _u(0x00000008)
#define PSM_FRCE_OFF_XOSC_MSB _u(3)
#define PSM_FRCE_OFF_XOSC_LSB _u(3)
#define PSM_FRCE_OFF_XOSC_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_OFF_ROSC
#define PSM_FRCE_OFF_ROSC_RESET _u(0x0)
#define PSM_FRCE_OFF_ROSC_BITS _u(0x00000004)
#define PSM_FRCE_OFF_ROSC_MSB _u(2)
#define PSM_FRCE_OFF_ROSC_LSB _u(2)
#define PSM_FRCE_OFF_ROSC_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_OFF_OTP
#define PSM_FRCE_OFF_OTP_RESET _u(0x0)
#define PSM_FRCE_OFF_OTP_BITS _u(0x00000002)
#define PSM_FRCE_OFF_OTP_MSB _u(1)
#define PSM_FRCE_OFF_OTP_LSB _u(1)
#define PSM_FRCE_OFF_OTP_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_OFF_PROC_COLD
#define PSM_FRCE_OFF_PROC_COLD_RESET _u(0x0)
#define PSM_FRCE_OFF_PROC_COLD_BITS _u(0x00000001)
#define PSM_FRCE_OFF_PROC_COLD_MSB _u(0)
#define PSM_FRCE_OFF_PROC_COLD_LSB _u(0)
#define PSM_FRCE_OFF_PROC_COLD_ACCESS "RW"
// =============================================================================
// Register : PSM_WDSEL
// Description : Set to 1 if the watchdog should reset this
#define PSM_WDSEL_OFFSET _u(0x00000008)
#define PSM_WDSEL_BITS _u(0x01ffffff)
#define PSM_WDSEL_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : PSM_WDSEL_PROC1
#define PSM_WDSEL_PROC1_RESET _u(0x0)
#define PSM_WDSEL_PROC1_BITS _u(0x01000000)
#define PSM_WDSEL_PROC1_MSB _u(24)
#define PSM_WDSEL_PROC1_LSB _u(24)
#define PSM_WDSEL_PROC1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_WDSEL_PROC0
#define PSM_WDSEL_PROC0_RESET _u(0x0)
#define PSM_WDSEL_PROC0_BITS _u(0x00800000)
#define PSM_WDSEL_PROC0_MSB _u(23)
#define PSM_WDSEL_PROC0_LSB _u(23)
#define PSM_WDSEL_PROC0_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_WDSEL_ACCESSCTRL
#define PSM_WDSEL_ACCESSCTRL_RESET _u(0x0)
#define PSM_WDSEL_ACCESSCTRL_BITS _u(0x00400000)
#define PSM_WDSEL_ACCESSCTRL_MSB _u(22)
#define PSM_WDSEL_ACCESSCTRL_LSB _u(22)
#define PSM_WDSEL_ACCESSCTRL_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_WDSEL_SIO
#define PSM_WDSEL_SIO_RESET _u(0x0)
#define PSM_WDSEL_SIO_BITS _u(0x00200000)
#define PSM_WDSEL_SIO_MSB _u(21)
#define PSM_WDSEL_SIO_LSB _u(21)
#define PSM_WDSEL_SIO_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_WDSEL_XIP
#define PSM_WDSEL_XIP_RESET _u(0x0)
#define PSM_WDSEL_XIP_BITS _u(0x00100000)
#define PSM_WDSEL_XIP_MSB _u(20)
#define PSM_WDSEL_XIP_LSB _u(20)
#define PSM_WDSEL_XIP_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_WDSEL_SRAM9
#define PSM_WDSEL_SRAM9_RESET _u(0x0)
#define PSM_WDSEL_SRAM9_BITS _u(0x00080000)
#define PSM_WDSEL_SRAM9_MSB _u(19)
#define PSM_WDSEL_SRAM9_LSB _u(19)
#define PSM_WDSEL_SRAM9_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_WDSEL_SRAM8
#define PSM_WDSEL_SRAM8_RESET _u(0x0)
#define PSM_WDSEL_SRAM8_BITS _u(0x00040000)
#define PSM_WDSEL_SRAM8_MSB _u(18)
#define PSM_WDSEL_SRAM8_LSB _u(18)
#define PSM_WDSEL_SRAM8_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_WDSEL_SRAM7
#define PSM_WDSEL_SRAM7_RESET _u(0x0)
#define PSM_WDSEL_SRAM7_BITS _u(0x00020000)
#define PSM_WDSEL_SRAM7_MSB _u(17)
#define PSM_WDSEL_SRAM7_LSB _u(17)
#define PSM_WDSEL_SRAM7_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_WDSEL_SRAM6
#define PSM_WDSEL_SRAM6_RESET _u(0x0)
#define PSM_WDSEL_SRAM6_BITS _u(0x00010000)
#define PSM_WDSEL_SRAM6_MSB _u(16)
#define PSM_WDSEL_SRAM6_LSB _u(16)
#define PSM_WDSEL_SRAM6_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_WDSEL_SRAM5
#define PSM_WDSEL_SRAM5_RESET _u(0x0)
#define PSM_WDSEL_SRAM5_BITS _u(0x00008000)
#define PSM_WDSEL_SRAM5_MSB _u(15)
#define PSM_WDSEL_SRAM5_LSB _u(15)
#define PSM_WDSEL_SRAM5_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_WDSEL_SRAM4
#define PSM_WDSEL_SRAM4_RESET _u(0x0)
#define PSM_WDSEL_SRAM4_BITS _u(0x00004000)
#define PSM_WDSEL_SRAM4_MSB _u(14)
#define PSM_WDSEL_SRAM4_LSB _u(14)
#define PSM_WDSEL_SRAM4_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_WDSEL_SRAM3
#define PSM_WDSEL_SRAM3_RESET _u(0x0)
#define PSM_WDSEL_SRAM3_BITS _u(0x00002000)
#define PSM_WDSEL_SRAM3_MSB _u(13)
#define PSM_WDSEL_SRAM3_LSB _u(13)
#define PSM_WDSEL_SRAM3_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_WDSEL_SRAM2
#define PSM_WDSEL_SRAM2_RESET _u(0x0)
#define PSM_WDSEL_SRAM2_BITS _u(0x00001000)
#define PSM_WDSEL_SRAM2_MSB _u(12)
#define PSM_WDSEL_SRAM2_LSB _u(12)
#define PSM_WDSEL_SRAM2_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_WDSEL_SRAM1
#define PSM_WDSEL_SRAM1_RESET _u(0x0)
#define PSM_WDSEL_SRAM1_BITS _u(0x00000800)
#define PSM_WDSEL_SRAM1_MSB _u(11)
#define PSM_WDSEL_SRAM1_LSB _u(11)
#define PSM_WDSEL_SRAM1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_WDSEL_SRAM0
#define PSM_WDSEL_SRAM0_RESET _u(0x0)
#define PSM_WDSEL_SRAM0_BITS _u(0x00000400)
#define PSM_WDSEL_SRAM0_MSB _u(10)
#define PSM_WDSEL_SRAM0_LSB _u(10)
#define PSM_WDSEL_SRAM0_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_WDSEL_BOOTRAM
#define PSM_WDSEL_BOOTRAM_RESET _u(0x0)
#define PSM_WDSEL_BOOTRAM_BITS _u(0x00000200)
#define PSM_WDSEL_BOOTRAM_MSB _u(9)
#define PSM_WDSEL_BOOTRAM_LSB _u(9)
#define PSM_WDSEL_BOOTRAM_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_WDSEL_ROM
#define PSM_WDSEL_ROM_RESET _u(0x0)
#define PSM_WDSEL_ROM_BITS _u(0x00000100)
#define PSM_WDSEL_ROM_MSB _u(8)
#define PSM_WDSEL_ROM_LSB _u(8)
#define PSM_WDSEL_ROM_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_WDSEL_BUSFABRIC
#define PSM_WDSEL_BUSFABRIC_RESET _u(0x0)
#define PSM_WDSEL_BUSFABRIC_BITS _u(0x00000080)
#define PSM_WDSEL_BUSFABRIC_MSB _u(7)
#define PSM_WDSEL_BUSFABRIC_LSB _u(7)
#define PSM_WDSEL_BUSFABRIC_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_WDSEL_PSM_READY
#define PSM_WDSEL_PSM_READY_RESET _u(0x0)
#define PSM_WDSEL_PSM_READY_BITS _u(0x00000040)
#define PSM_WDSEL_PSM_READY_MSB _u(6)
#define PSM_WDSEL_PSM_READY_LSB _u(6)
#define PSM_WDSEL_PSM_READY_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_WDSEL_CLOCKS
#define PSM_WDSEL_CLOCKS_RESET _u(0x0)
#define PSM_WDSEL_CLOCKS_BITS _u(0x00000020)
#define PSM_WDSEL_CLOCKS_MSB _u(5)
#define PSM_WDSEL_CLOCKS_LSB _u(5)
#define PSM_WDSEL_CLOCKS_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_WDSEL_RESETS
#define PSM_WDSEL_RESETS_RESET _u(0x0)
#define PSM_WDSEL_RESETS_BITS _u(0x00000010)
#define PSM_WDSEL_RESETS_MSB _u(4)
#define PSM_WDSEL_RESETS_LSB _u(4)
#define PSM_WDSEL_RESETS_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_WDSEL_XOSC
#define PSM_WDSEL_XOSC_RESET _u(0x0)
#define PSM_WDSEL_XOSC_BITS _u(0x00000008)
#define PSM_WDSEL_XOSC_MSB _u(3)
#define PSM_WDSEL_XOSC_LSB _u(3)
#define PSM_WDSEL_XOSC_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_WDSEL_ROSC
#define PSM_WDSEL_ROSC_RESET _u(0x0)
#define PSM_WDSEL_ROSC_BITS _u(0x00000004)
#define PSM_WDSEL_ROSC_MSB _u(2)
#define PSM_WDSEL_ROSC_LSB _u(2)
#define PSM_WDSEL_ROSC_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_WDSEL_OTP
#define PSM_WDSEL_OTP_RESET _u(0x0)
#define PSM_WDSEL_OTP_BITS _u(0x00000002)
#define PSM_WDSEL_OTP_MSB _u(1)
#define PSM_WDSEL_OTP_LSB _u(1)
#define PSM_WDSEL_OTP_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_WDSEL_PROC_COLD
#define PSM_WDSEL_PROC_COLD_RESET _u(0x0)
#define PSM_WDSEL_PROC_COLD_BITS _u(0x00000001)
#define PSM_WDSEL_PROC_COLD_MSB _u(0)
#define PSM_WDSEL_PROC_COLD_LSB _u(0)
#define PSM_WDSEL_PROC_COLD_ACCESS "RW"
// =============================================================================
// Register : PSM_DONE
// Description : Is the subsystem ready?
#define PSM_DONE_OFFSET _u(0x0000000c)
#define PSM_DONE_BITS _u(0x01ffffff)
#define PSM_DONE_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : PSM_DONE_PROC1
#define PSM_DONE_PROC1_RESET _u(0x0)
#define PSM_DONE_PROC1_BITS _u(0x01000000)
#define PSM_DONE_PROC1_MSB _u(24)
#define PSM_DONE_PROC1_LSB _u(24)
#define PSM_DONE_PROC1_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PSM_DONE_PROC0
#define PSM_DONE_PROC0_RESET _u(0x0)
#define PSM_DONE_PROC0_BITS _u(0x00800000)
#define PSM_DONE_PROC0_MSB _u(23)
#define PSM_DONE_PROC0_LSB _u(23)
#define PSM_DONE_PROC0_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PSM_DONE_ACCESSCTRL
#define PSM_DONE_ACCESSCTRL_RESET _u(0x0)
#define PSM_DONE_ACCESSCTRL_BITS _u(0x00400000)
#define PSM_DONE_ACCESSCTRL_MSB _u(22)
#define PSM_DONE_ACCESSCTRL_LSB _u(22)
#define PSM_DONE_ACCESSCTRL_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PSM_DONE_SIO
#define PSM_DONE_SIO_RESET _u(0x0)
#define PSM_DONE_SIO_BITS _u(0x00200000)
#define PSM_DONE_SIO_MSB _u(21)
#define PSM_DONE_SIO_LSB _u(21)
#define PSM_DONE_SIO_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PSM_DONE_XIP
#define PSM_DONE_XIP_RESET _u(0x0)
#define PSM_DONE_XIP_BITS _u(0x00100000)
#define PSM_DONE_XIP_MSB _u(20)
#define PSM_DONE_XIP_LSB _u(20)
#define PSM_DONE_XIP_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PSM_DONE_SRAM9
#define PSM_DONE_SRAM9_RESET _u(0x0)
#define PSM_DONE_SRAM9_BITS _u(0x00080000)
#define PSM_DONE_SRAM9_MSB _u(19)
#define PSM_DONE_SRAM9_LSB _u(19)
#define PSM_DONE_SRAM9_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PSM_DONE_SRAM8
#define PSM_DONE_SRAM8_RESET _u(0x0)
#define PSM_DONE_SRAM8_BITS _u(0x00040000)
#define PSM_DONE_SRAM8_MSB _u(18)
#define PSM_DONE_SRAM8_LSB _u(18)
#define PSM_DONE_SRAM8_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PSM_DONE_SRAM7
#define PSM_DONE_SRAM7_RESET _u(0x0)
#define PSM_DONE_SRAM7_BITS _u(0x00020000)
#define PSM_DONE_SRAM7_MSB _u(17)
#define PSM_DONE_SRAM7_LSB _u(17)
#define PSM_DONE_SRAM7_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PSM_DONE_SRAM6
#define PSM_DONE_SRAM6_RESET _u(0x0)
#define PSM_DONE_SRAM6_BITS _u(0x00010000)
#define PSM_DONE_SRAM6_MSB _u(16)
#define PSM_DONE_SRAM6_LSB _u(16)
#define PSM_DONE_SRAM6_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PSM_DONE_SRAM5
#define PSM_DONE_SRAM5_RESET _u(0x0)
#define PSM_DONE_SRAM5_BITS _u(0x00008000)
#define PSM_DONE_SRAM5_MSB _u(15)
#define PSM_DONE_SRAM5_LSB _u(15)
#define PSM_DONE_SRAM5_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PSM_DONE_SRAM4
#define PSM_DONE_SRAM4_RESET _u(0x0)
#define PSM_DONE_SRAM4_BITS _u(0x00004000)
#define PSM_DONE_SRAM4_MSB _u(14)
#define PSM_DONE_SRAM4_LSB _u(14)
#define PSM_DONE_SRAM4_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PSM_DONE_SRAM3
#define PSM_DONE_SRAM3_RESET _u(0x0)
#define PSM_DONE_SRAM3_BITS _u(0x00002000)
#define PSM_DONE_SRAM3_MSB _u(13)
#define PSM_DONE_SRAM3_LSB _u(13)
#define PSM_DONE_SRAM3_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PSM_DONE_SRAM2
#define PSM_DONE_SRAM2_RESET _u(0x0)
#define PSM_DONE_SRAM2_BITS _u(0x00001000)
#define PSM_DONE_SRAM2_MSB _u(12)
#define PSM_DONE_SRAM2_LSB _u(12)
#define PSM_DONE_SRAM2_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PSM_DONE_SRAM1
#define PSM_DONE_SRAM1_RESET _u(0x0)
#define PSM_DONE_SRAM1_BITS _u(0x00000800)
#define PSM_DONE_SRAM1_MSB _u(11)
#define PSM_DONE_SRAM1_LSB _u(11)
#define PSM_DONE_SRAM1_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PSM_DONE_SRAM0
#define PSM_DONE_SRAM0_RESET _u(0x0)
#define PSM_DONE_SRAM0_BITS _u(0x00000400)
#define PSM_DONE_SRAM0_MSB _u(10)
#define PSM_DONE_SRAM0_LSB _u(10)
#define PSM_DONE_SRAM0_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PSM_DONE_BOOTRAM
#define PSM_DONE_BOOTRAM_RESET _u(0x0)
#define PSM_DONE_BOOTRAM_BITS _u(0x00000200)
#define PSM_DONE_BOOTRAM_MSB _u(9)
#define PSM_DONE_BOOTRAM_LSB _u(9)
#define PSM_DONE_BOOTRAM_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PSM_DONE_ROM
#define PSM_DONE_ROM_RESET _u(0x0)
#define PSM_DONE_ROM_BITS _u(0x00000100)
#define PSM_DONE_ROM_MSB _u(8)
#define PSM_DONE_ROM_LSB _u(8)
#define PSM_DONE_ROM_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PSM_DONE_BUSFABRIC
#define PSM_DONE_BUSFABRIC_RESET _u(0x0)
#define PSM_DONE_BUSFABRIC_BITS _u(0x00000080)
#define PSM_DONE_BUSFABRIC_MSB _u(7)
#define PSM_DONE_BUSFABRIC_LSB _u(7)
#define PSM_DONE_BUSFABRIC_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PSM_DONE_PSM_READY
#define PSM_DONE_PSM_READY_RESET _u(0x0)
#define PSM_DONE_PSM_READY_BITS _u(0x00000040)
#define PSM_DONE_PSM_READY_MSB _u(6)
#define PSM_DONE_PSM_READY_LSB _u(6)
#define PSM_DONE_PSM_READY_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PSM_DONE_CLOCKS
#define PSM_DONE_CLOCKS_RESET _u(0x0)
#define PSM_DONE_CLOCKS_BITS _u(0x00000020)
#define PSM_DONE_CLOCKS_MSB _u(5)
#define PSM_DONE_CLOCKS_LSB _u(5)
#define PSM_DONE_CLOCKS_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PSM_DONE_RESETS
#define PSM_DONE_RESETS_RESET _u(0x0)
#define PSM_DONE_RESETS_BITS _u(0x00000010)
#define PSM_DONE_RESETS_MSB _u(4)
#define PSM_DONE_RESETS_LSB _u(4)
#define PSM_DONE_RESETS_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PSM_DONE_XOSC
#define PSM_DONE_XOSC_RESET _u(0x0)
#define PSM_DONE_XOSC_BITS _u(0x00000008)
#define PSM_DONE_XOSC_MSB _u(3)
#define PSM_DONE_XOSC_LSB _u(3)
#define PSM_DONE_XOSC_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PSM_DONE_ROSC
#define PSM_DONE_ROSC_RESET _u(0x0)
#define PSM_DONE_ROSC_BITS _u(0x00000004)
#define PSM_DONE_ROSC_MSB _u(2)
#define PSM_DONE_ROSC_LSB _u(2)
#define PSM_DONE_ROSC_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PSM_DONE_OTP
#define PSM_DONE_OTP_RESET _u(0x0)
#define PSM_DONE_OTP_BITS _u(0x00000002)
#define PSM_DONE_OTP_MSB _u(1)
#define PSM_DONE_OTP_LSB _u(1)
#define PSM_DONE_OTP_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PSM_DONE_PROC_COLD
#define PSM_DONE_PROC_COLD_RESET _u(0x0)
#define PSM_DONE_PROC_COLD_BITS _u(0x00000001)
#define PSM_DONE_PROC_COLD_MSB _u(0)
#define PSM_DONE_PROC_COLD_LSB _u(0)
#define PSM_DONE_PROC_COLD_ACCESS "RO"
// =============================================================================
#endif // _HARDWARE_REGS_PSM_H

2374
arch/arm/src/rp23xx/hardware/regs/pwm.h
View file

File diff suppressed because it is too large Load diff

1781
arch/arm/src/rp23xx/hardware/regs/qmi.h
View file

File diff suppressed because it is too large Load diff

641
arch/arm/src/rp23xx/hardware/regs/resets.h
View file

@ -1,641 +0,0 @@
// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
// =============================================================================
// Register block : RESETS
// Version : 1
// Bus type : apb
// =============================================================================
#ifndef _HARDWARE_REGS_RESETS_H
#define _HARDWARE_REGS_RESETS_H
// =============================================================================
// Register : RESETS_RESET
#define RESETS_RESET_OFFSET _u(0x00000000)
#define RESETS_RESET_BITS _u(0x1fffffff)
#define RESETS_RESET_RESET _u(0x1fffffff)
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_USBCTRL
#define RESETS_RESET_USBCTRL_RESET _u(0x1)
#define RESETS_RESET_USBCTRL_BITS _u(0x10000000)
#define RESETS_RESET_USBCTRL_MSB _u(28)
#define RESETS_RESET_USBCTRL_LSB _u(28)
#define RESETS_RESET_USBCTRL_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_UART1
#define RESETS_RESET_UART1_RESET _u(0x1)
#define RESETS_RESET_UART1_BITS _u(0x08000000)
#define RESETS_RESET_UART1_MSB _u(27)
#define RESETS_RESET_UART1_LSB _u(27)
#define RESETS_RESET_UART1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_UART0
#define RESETS_RESET_UART0_RESET _u(0x1)
#define RESETS_RESET_UART0_BITS _u(0x04000000)
#define RESETS_RESET_UART0_MSB _u(26)
#define RESETS_RESET_UART0_LSB _u(26)
#define RESETS_RESET_UART0_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_TRNG
#define RESETS_RESET_TRNG_RESET _u(0x1)
#define RESETS_RESET_TRNG_BITS _u(0x02000000)
#define RESETS_RESET_TRNG_MSB _u(25)
#define RESETS_RESET_TRNG_LSB _u(25)
#define RESETS_RESET_TRNG_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_TIMER1
#define RESETS_RESET_TIMER1_RESET _u(0x1)
#define RESETS_RESET_TIMER1_BITS _u(0x01000000)
#define RESETS_RESET_TIMER1_MSB _u(24)
#define RESETS_RESET_TIMER1_LSB _u(24)
#define RESETS_RESET_TIMER1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_TIMER0
#define RESETS_RESET_TIMER0_RESET _u(0x1)
#define RESETS_RESET_TIMER0_BITS _u(0x00800000)
#define RESETS_RESET_TIMER0_MSB _u(23)
#define RESETS_RESET_TIMER0_LSB _u(23)
#define RESETS_RESET_TIMER0_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_TBMAN
#define RESETS_RESET_TBMAN_RESET _u(0x1)
#define RESETS_RESET_TBMAN_BITS _u(0x00400000)
#define RESETS_RESET_TBMAN_MSB _u(22)
#define RESETS_RESET_TBMAN_LSB _u(22)
#define RESETS_RESET_TBMAN_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_SYSINFO
#define RESETS_RESET_SYSINFO_RESET _u(0x1)
#define RESETS_RESET_SYSINFO_BITS _u(0x00200000)
#define RESETS_RESET_SYSINFO_MSB _u(21)
#define RESETS_RESET_SYSINFO_LSB _u(21)
#define RESETS_RESET_SYSINFO_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_SYSCFG
#define RESETS_RESET_SYSCFG_RESET _u(0x1)
#define RESETS_RESET_SYSCFG_BITS _u(0x00100000)
#define RESETS_RESET_SYSCFG_MSB _u(20)
#define RESETS_RESET_SYSCFG_LSB _u(20)
#define RESETS_RESET_SYSCFG_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_SPI1
#define RESETS_RESET_SPI1_RESET _u(0x1)
#define RESETS_RESET_SPI1_BITS _u(0x00080000)
#define RESETS_RESET_SPI1_MSB _u(19)
#define RESETS_RESET_SPI1_LSB _u(19)
#define RESETS_RESET_SPI1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_SPI0
#define RESETS_RESET_SPI0_RESET _u(0x1)
#define RESETS_RESET_SPI0_BITS _u(0x00040000)
#define RESETS_RESET_SPI0_MSB _u(18)
#define RESETS_RESET_SPI0_LSB _u(18)
#define RESETS_RESET_SPI0_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_SHA256
#define RESETS_RESET_SHA256_RESET _u(0x1)
#define RESETS_RESET_SHA256_BITS _u(0x00020000)
#define RESETS_RESET_SHA256_MSB _u(17)
#define RESETS_RESET_SHA256_LSB _u(17)
#define RESETS_RESET_SHA256_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_PWM
#define RESETS_RESET_PWM_RESET _u(0x1)
#define RESETS_RESET_PWM_BITS _u(0x00010000)
#define RESETS_RESET_PWM_MSB _u(16)
#define RESETS_RESET_PWM_LSB _u(16)
#define RESETS_RESET_PWM_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_PLL_USB
#define RESETS_RESET_PLL_USB_RESET _u(0x1)
#define RESETS_RESET_PLL_USB_BITS _u(0x00008000)
#define RESETS_RESET_PLL_USB_MSB _u(15)
#define RESETS_RESET_PLL_USB_LSB _u(15)
#define RESETS_RESET_PLL_USB_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_PLL_SYS
#define RESETS_RESET_PLL_SYS_RESET _u(0x1)
#define RESETS_RESET_PLL_SYS_BITS _u(0x00004000)
#define RESETS_RESET_PLL_SYS_MSB _u(14)
#define RESETS_RESET_PLL_SYS_LSB _u(14)
#define RESETS_RESET_PLL_SYS_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_PIO2
#define RESETS_RESET_PIO2_RESET _u(0x1)
#define RESETS_RESET_PIO2_BITS _u(0x00002000)
#define RESETS_RESET_PIO2_MSB _u(13)
#define RESETS_RESET_PIO2_LSB _u(13)
#define RESETS_RESET_PIO2_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_PIO1
#define RESETS_RESET_PIO1_RESET _u(0x1)
#define RESETS_RESET_PIO1_BITS _u(0x00001000)
#define RESETS_RESET_PIO1_MSB _u(12)
#define RESETS_RESET_PIO1_LSB _u(12)
#define RESETS_RESET_PIO1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_PIO0
#define RESETS_RESET_PIO0_RESET _u(0x1)
#define RESETS_RESET_PIO0_BITS _u(0x00000800)
#define RESETS_RESET_PIO0_MSB _u(11)
#define RESETS_RESET_PIO0_LSB _u(11)
#define RESETS_RESET_PIO0_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_PADS_QSPI
#define RESETS_RESET_PADS_QSPI_RESET _u(0x1)
#define RESETS_RESET_PADS_QSPI_BITS _u(0x00000400)
#define RESETS_RESET_PADS_QSPI_MSB _u(10)
#define RESETS_RESET_PADS_QSPI_LSB _u(10)
#define RESETS_RESET_PADS_QSPI_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_PADS_BANK0
#define RESETS_RESET_PADS_BANK0_RESET _u(0x1)
#define RESETS_RESET_PADS_BANK0_BITS _u(0x00000200)
#define RESETS_RESET_PADS_BANK0_MSB _u(9)
#define RESETS_RESET_PADS_BANK0_LSB _u(9)
#define RESETS_RESET_PADS_BANK0_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_JTAG
#define RESETS_RESET_JTAG_RESET _u(0x1)
#define RESETS_RESET_JTAG_BITS _u(0x00000100)
#define RESETS_RESET_JTAG_MSB _u(8)
#define RESETS_RESET_JTAG_LSB _u(8)
#define RESETS_RESET_JTAG_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_IO_QSPI
#define RESETS_RESET_IO_QSPI_RESET _u(0x1)
#define RESETS_RESET_IO_QSPI_BITS _u(0x00000080)
#define RESETS_RESET_IO_QSPI_MSB _u(7)
#define RESETS_RESET_IO_QSPI_LSB _u(7)
#define RESETS_RESET_IO_QSPI_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_IO_BANK0
#define RESETS_RESET_IO_BANK0_RESET _u(0x1)
#define RESETS_RESET_IO_BANK0_BITS _u(0x00000040)
#define RESETS_RESET_IO_BANK0_MSB _u(6)
#define RESETS_RESET_IO_BANK0_LSB _u(6)
#define RESETS_RESET_IO_BANK0_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_I2C1
#define RESETS_RESET_I2C1_RESET _u(0x1)
#define RESETS_RESET_I2C1_BITS _u(0x00000020)
#define RESETS_RESET_I2C1_MSB _u(5)
#define RESETS_RESET_I2C1_LSB _u(5)
#define RESETS_RESET_I2C1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_I2C0
#define RESETS_RESET_I2C0_RESET _u(0x1)
#define RESETS_RESET_I2C0_BITS _u(0x00000010)
#define RESETS_RESET_I2C0_MSB _u(4)
#define RESETS_RESET_I2C0_LSB _u(4)
#define RESETS_RESET_I2C0_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_HSTX
#define RESETS_RESET_HSTX_RESET _u(0x1)
#define RESETS_RESET_HSTX_BITS _u(0x00000008)
#define RESETS_RESET_HSTX_MSB _u(3)
#define RESETS_RESET_HSTX_LSB _u(3)
#define RESETS_RESET_HSTX_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DMA
#define RESETS_RESET_DMA_RESET _u(0x1)
#define RESETS_RESET_DMA_BITS _u(0x00000004)
#define RESETS_RESET_DMA_MSB _u(2)
#define RESETS_RESET_DMA_LSB _u(2)
#define RESETS_RESET_DMA_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_BUSCTRL
#define RESETS_RESET_BUSCTRL_RESET _u(0x1)
#define RESETS_RESET_BUSCTRL_BITS _u(0x00000002)
#define RESETS_RESET_BUSCTRL_MSB _u(1)
#define RESETS_RESET_BUSCTRL_LSB _u(1)
#define RESETS_RESET_BUSCTRL_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_ADC
#define RESETS_RESET_ADC_RESET _u(0x1)
#define RESETS_RESET_ADC_BITS _u(0x00000001)
#define RESETS_RESET_ADC_MSB _u(0)
#define RESETS_RESET_ADC_LSB _u(0)
#define RESETS_RESET_ADC_ACCESS "RW"
// =============================================================================
// Register : RESETS_WDSEL
#define RESETS_WDSEL_OFFSET _u(0x00000004)
#define RESETS_WDSEL_BITS _u(0x1fffffff)
#define RESETS_WDSEL_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_USBCTRL
#define RESETS_WDSEL_USBCTRL_RESET _u(0x0)
#define RESETS_WDSEL_USBCTRL_BITS _u(0x10000000)
#define RESETS_WDSEL_USBCTRL_MSB _u(28)
#define RESETS_WDSEL_USBCTRL_LSB _u(28)
#define RESETS_WDSEL_USBCTRL_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_UART1
#define RESETS_WDSEL_UART1_RESET _u(0x0)
#define RESETS_WDSEL_UART1_BITS _u(0x08000000)
#define RESETS_WDSEL_UART1_MSB _u(27)
#define RESETS_WDSEL_UART1_LSB _u(27)
#define RESETS_WDSEL_UART1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_UART0
#define RESETS_WDSEL_UART0_RESET _u(0x0)
#define RESETS_WDSEL_UART0_BITS _u(0x04000000)
#define RESETS_WDSEL_UART0_MSB _u(26)
#define RESETS_WDSEL_UART0_LSB _u(26)
#define RESETS_WDSEL_UART0_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_TRNG
#define RESETS_WDSEL_TRNG_RESET _u(0x0)
#define RESETS_WDSEL_TRNG_BITS _u(0x02000000)
#define RESETS_WDSEL_TRNG_MSB _u(25)
#define RESETS_WDSEL_TRNG_LSB _u(25)
#define RESETS_WDSEL_TRNG_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_TIMER1
#define RESETS_WDSEL_TIMER1_RESET _u(0x0)
#define RESETS_WDSEL_TIMER1_BITS _u(0x01000000)
#define RESETS_WDSEL_TIMER1_MSB _u(24)
#define RESETS_WDSEL_TIMER1_LSB _u(24)
#define RESETS_WDSEL_TIMER1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_TIMER0
#define RESETS_WDSEL_TIMER0_RESET _u(0x0)
#define RESETS_WDSEL_TIMER0_BITS _u(0x00800000)
#define RESETS_WDSEL_TIMER0_MSB _u(23)
#define RESETS_WDSEL_TIMER0_LSB _u(23)
#define RESETS_WDSEL_TIMER0_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_TBMAN
#define RESETS_WDSEL_TBMAN_RESET _u(0x0)
#define RESETS_WDSEL_TBMAN_BITS _u(0x00400000)
#define RESETS_WDSEL_TBMAN_MSB _u(22)
#define RESETS_WDSEL_TBMAN_LSB _u(22)
#define RESETS_WDSEL_TBMAN_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_SYSINFO
#define RESETS_WDSEL_SYSINFO_RESET _u(0x0)
#define RESETS_WDSEL_SYSINFO_BITS _u(0x00200000)
#define RESETS_WDSEL_SYSINFO_MSB _u(21)
#define RESETS_WDSEL_SYSINFO_LSB _u(21)
#define RESETS_WDSEL_SYSINFO_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_SYSCFG
#define RESETS_WDSEL_SYSCFG_RESET _u(0x0)
#define RESETS_WDSEL_SYSCFG_BITS _u(0x00100000)
#define RESETS_WDSEL_SYSCFG_MSB _u(20)
#define RESETS_WDSEL_SYSCFG_LSB _u(20)
#define RESETS_WDSEL_SYSCFG_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_SPI1
#define RESETS_WDSEL_SPI1_RESET _u(0x0)
#define RESETS_WDSEL_SPI1_BITS _u(0x00080000)
#define RESETS_WDSEL_SPI1_MSB _u(19)
#define RESETS_WDSEL_SPI1_LSB _u(19)
#define RESETS_WDSEL_SPI1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_SPI0
#define RESETS_WDSEL_SPI0_RESET _u(0x0)
#define RESETS_WDSEL_SPI0_BITS _u(0x00040000)
#define RESETS_WDSEL_SPI0_MSB _u(18)
#define RESETS_WDSEL_SPI0_LSB _u(18)
#define RESETS_WDSEL_SPI0_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_SHA256
#define RESETS_WDSEL_SHA256_RESET _u(0x0)
#define RESETS_WDSEL_SHA256_BITS _u(0x00020000)
#define RESETS_WDSEL_SHA256_MSB _u(17)
#define RESETS_WDSEL_SHA256_LSB _u(17)
#define RESETS_WDSEL_SHA256_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_PWM
#define RESETS_WDSEL_PWM_RESET _u(0x0)
#define RESETS_WDSEL_PWM_BITS _u(0x00010000)
#define RESETS_WDSEL_PWM_MSB _u(16)
#define RESETS_WDSEL_PWM_LSB _u(16)
#define RESETS_WDSEL_PWM_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_PLL_USB
#define RESETS_WDSEL_PLL_USB_RESET _u(0x0)
#define RESETS_WDSEL_PLL_USB_BITS _u(0x00008000)
#define RESETS_WDSEL_PLL_USB_MSB _u(15)
#define RESETS_WDSEL_PLL_USB_LSB _u(15)
#define RESETS_WDSEL_PLL_USB_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_PLL_SYS
#define RESETS_WDSEL_PLL_SYS_RESET _u(0x0)
#define RESETS_WDSEL_PLL_SYS_BITS _u(0x00004000)
#define RESETS_WDSEL_PLL_SYS_MSB _u(14)
#define RESETS_WDSEL_PLL_SYS_LSB _u(14)
#define RESETS_WDSEL_PLL_SYS_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_PIO2
#define RESETS_WDSEL_PIO2_RESET _u(0x0)
#define RESETS_WDSEL_PIO2_BITS _u(0x00002000)
#define RESETS_WDSEL_PIO2_MSB _u(13)
#define RESETS_WDSEL_PIO2_LSB _u(13)
#define RESETS_WDSEL_PIO2_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_PIO1
#define RESETS_WDSEL_PIO1_RESET _u(0x0)
#define RESETS_WDSEL_PIO1_BITS _u(0x00001000)
#define RESETS_WDSEL_PIO1_MSB _u(12)
#define RESETS_WDSEL_PIO1_LSB _u(12)
#define RESETS_WDSEL_PIO1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_PIO0
#define RESETS_WDSEL_PIO0_RESET _u(0x0)
#define RESETS_WDSEL_PIO0_BITS _u(0x00000800)
#define RESETS_WDSEL_PIO0_MSB _u(11)
#define RESETS_WDSEL_PIO0_LSB _u(11)
#define RESETS_WDSEL_PIO0_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_PADS_QSPI
#define RESETS_WDSEL_PADS_QSPI_RESET _u(0x0)
#define RESETS_WDSEL_PADS_QSPI_BITS _u(0x00000400)
#define RESETS_WDSEL_PADS_QSPI_MSB _u(10)
#define RESETS_WDSEL_PADS_QSPI_LSB _u(10)
#define RESETS_WDSEL_PADS_QSPI_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_PADS_BANK0
#define RESETS_WDSEL_PADS_BANK0_RESET _u(0x0)
#define RESETS_WDSEL_PADS_BANK0_BITS _u(0x00000200)
#define RESETS_WDSEL_PADS_BANK0_MSB _u(9)
#define RESETS_WDSEL_PADS_BANK0_LSB _u(9)
#define RESETS_WDSEL_PADS_BANK0_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_JTAG
#define RESETS_WDSEL_JTAG_RESET _u(0x0)
#define RESETS_WDSEL_JTAG_BITS _u(0x00000100)
#define RESETS_WDSEL_JTAG_MSB _u(8)
#define RESETS_WDSEL_JTAG_LSB _u(8)
#define RESETS_WDSEL_JTAG_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_IO_QSPI
#define RESETS_WDSEL_IO_QSPI_RESET _u(0x0)
#define RESETS_WDSEL_IO_QSPI_BITS _u(0x00000080)
#define RESETS_WDSEL_IO_QSPI_MSB _u(7)
#define RESETS_WDSEL_IO_QSPI_LSB _u(7)
#define RESETS_WDSEL_IO_QSPI_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_IO_BANK0
#define RESETS_WDSEL_IO_BANK0_RESET _u(0x0)
#define RESETS_WDSEL_IO_BANK0_BITS _u(0x00000040)
#define RESETS_WDSEL_IO_BANK0_MSB _u(6)
#define RESETS_WDSEL_IO_BANK0_LSB _u(6)
#define RESETS_WDSEL_IO_BANK0_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_I2C1
#define RESETS_WDSEL_I2C1_RESET _u(0x0)
#define RESETS_WDSEL_I2C1_BITS _u(0x00000020)
#define RESETS_WDSEL_I2C1_MSB _u(5)
#define RESETS_WDSEL_I2C1_LSB _u(5)
#define RESETS_WDSEL_I2C1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_I2C0
#define RESETS_WDSEL_I2C0_RESET _u(0x0)
#define RESETS_WDSEL_I2C0_BITS _u(0x00000010)
#define RESETS_WDSEL_I2C0_MSB _u(4)
#define RESETS_WDSEL_I2C0_LSB _u(4)
#define RESETS_WDSEL_I2C0_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_HSTX
#define RESETS_WDSEL_HSTX_RESET _u(0x0)
#define RESETS_WDSEL_HSTX_BITS _u(0x00000008)
#define RESETS_WDSEL_HSTX_MSB _u(3)
#define RESETS_WDSEL_HSTX_LSB _u(3)
#define RESETS_WDSEL_HSTX_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_DMA
#define RESETS_WDSEL_DMA_RESET _u(0x0)
#define RESETS_WDSEL_DMA_BITS _u(0x00000004)
#define RESETS_WDSEL_DMA_MSB _u(2)
#define RESETS_WDSEL_DMA_LSB _u(2)
#define RESETS_WDSEL_DMA_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_BUSCTRL
#define RESETS_WDSEL_BUSCTRL_RESET _u(0x0)
#define RESETS_WDSEL_BUSCTRL_BITS _u(0x00000002)
#define RESETS_WDSEL_BUSCTRL_MSB _u(1)
#define RESETS_WDSEL_BUSCTRL_LSB _u(1)
#define RESETS_WDSEL_BUSCTRL_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_ADC
#define RESETS_WDSEL_ADC_RESET _u(0x0)
#define RESETS_WDSEL_ADC_BITS _u(0x00000001)
#define RESETS_WDSEL_ADC_MSB _u(0)
#define RESETS_WDSEL_ADC_LSB _u(0)
#define RESETS_WDSEL_ADC_ACCESS "RW"
// =============================================================================
// Register : RESETS_RESET_DONE
#define RESETS_RESET_DONE_OFFSET _u(0x00000008)
#define RESETS_RESET_DONE_BITS _u(0x1fffffff)
#define RESETS_RESET_DONE_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_USBCTRL
#define RESETS_RESET_DONE_USBCTRL_RESET _u(0x0)
#define RESETS_RESET_DONE_USBCTRL_BITS _u(0x10000000)
#define RESETS_RESET_DONE_USBCTRL_MSB _u(28)
#define RESETS_RESET_DONE_USBCTRL_LSB _u(28)
#define RESETS_RESET_DONE_USBCTRL_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_UART1
#define RESETS_RESET_DONE_UART1_RESET _u(0x0)
#define RESETS_RESET_DONE_UART1_BITS _u(0x08000000)
#define RESETS_RESET_DONE_UART1_MSB _u(27)
#define RESETS_RESET_DONE_UART1_LSB _u(27)
#define RESETS_RESET_DONE_UART1_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_UART0
#define RESETS_RESET_DONE_UART0_RESET _u(0x0)
#define RESETS_RESET_DONE_UART0_BITS _u(0x04000000)
#define RESETS_RESET_DONE_UART0_MSB _u(26)
#define RESETS_RESET_DONE_UART0_LSB _u(26)
#define RESETS_RESET_DONE_UART0_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_TRNG
#define RESETS_RESET_DONE_TRNG_RESET _u(0x0)
#define RESETS_RESET_DONE_TRNG_BITS _u(0x02000000)
#define RESETS_RESET_DONE_TRNG_MSB _u(25)
#define RESETS_RESET_DONE_TRNG_LSB _u(25)
#define RESETS_RESET_DONE_TRNG_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_TIMER1
#define RESETS_RESET_DONE_TIMER1_RESET _u(0x0)
#define RESETS_RESET_DONE_TIMER1_BITS _u(0x01000000)
#define RESETS_RESET_DONE_TIMER1_MSB _u(24)
#define RESETS_RESET_DONE_TIMER1_LSB _u(24)
#define RESETS_RESET_DONE_TIMER1_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_TIMER0
#define RESETS_RESET_DONE_TIMER0_RESET _u(0x0)
#define RESETS_RESET_DONE_TIMER0_BITS _u(0x00800000)
#define RESETS_RESET_DONE_TIMER0_MSB _u(23)
#define RESETS_RESET_DONE_TIMER0_LSB _u(23)
#define RESETS_RESET_DONE_TIMER0_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_TBMAN
#define RESETS_RESET_DONE_TBMAN_RESET _u(0x0)
#define RESETS_RESET_DONE_TBMAN_BITS _u(0x00400000)
#define RESETS_RESET_DONE_TBMAN_MSB _u(22)
#define RESETS_RESET_DONE_TBMAN_LSB _u(22)
#define RESETS_RESET_DONE_TBMAN_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_SYSINFO
#define RESETS_RESET_DONE_SYSINFO_RESET _u(0x0)
#define RESETS_RESET_DONE_SYSINFO_BITS _u(0x00200000)
#define RESETS_RESET_DONE_SYSINFO_MSB _u(21)
#define RESETS_RESET_DONE_SYSINFO_LSB _u(21)
#define RESETS_RESET_DONE_SYSINFO_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_SYSCFG
#define RESETS_RESET_DONE_SYSCFG_RESET _u(0x0)
#define RESETS_RESET_DONE_SYSCFG_BITS _u(0x00100000)
#define RESETS_RESET_DONE_SYSCFG_MSB _u(20)
#define RESETS_RESET_DONE_SYSCFG_LSB _u(20)
#define RESETS_RESET_DONE_SYSCFG_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_SPI1
#define RESETS_RESET_DONE_SPI1_RESET _u(0x0)
#define RESETS_RESET_DONE_SPI1_BITS _u(0x00080000)
#define RESETS_RESET_DONE_SPI1_MSB _u(19)
#define RESETS_RESET_DONE_SPI1_LSB _u(19)
#define RESETS_RESET_DONE_SPI1_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_SPI0
#define RESETS_RESET_DONE_SPI0_RESET _u(0x0)
#define RESETS_RESET_DONE_SPI0_BITS _u(0x00040000)
#define RESETS_RESET_DONE_SPI0_MSB _u(18)
#define RESETS_RESET_DONE_SPI0_LSB _u(18)
#define RESETS_RESET_DONE_SPI0_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_SHA256
#define RESETS_RESET_DONE_SHA256_RESET _u(0x0)
#define RESETS_RESET_DONE_SHA256_BITS _u(0x00020000)
#define RESETS_RESET_DONE_SHA256_MSB _u(17)
#define RESETS_RESET_DONE_SHA256_LSB _u(17)
#define RESETS_RESET_DONE_SHA256_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_PWM
#define RESETS_RESET_DONE_PWM_RESET _u(0x0)
#define RESETS_RESET_DONE_PWM_BITS _u(0x00010000)
#define RESETS_RESET_DONE_PWM_MSB _u(16)
#define RESETS_RESET_DONE_PWM_LSB _u(16)
#define RESETS_RESET_DONE_PWM_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_PLL_USB
#define RESETS_RESET_DONE_PLL_USB_RESET _u(0x0)
#define RESETS_RESET_DONE_PLL_USB_BITS _u(0x00008000)
#define RESETS_RESET_DONE_PLL_USB_MSB _u(15)
#define RESETS_RESET_DONE_PLL_USB_LSB _u(15)
#define RESETS_RESET_DONE_PLL_USB_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_PLL_SYS
#define RESETS_RESET_DONE_PLL_SYS_RESET _u(0x0)
#define RESETS_RESET_DONE_PLL_SYS_BITS _u(0x00004000)
#define RESETS_RESET_DONE_PLL_SYS_MSB _u(14)
#define RESETS_RESET_DONE_PLL_SYS_LSB _u(14)
#define RESETS_RESET_DONE_PLL_SYS_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_PIO2
#define RESETS_RESET_DONE_PIO2_RESET _u(0x0)
#define RESETS_RESET_DONE_PIO2_BITS _u(0x00002000)
#define RESETS_RESET_DONE_PIO2_MSB _u(13)
#define RESETS_RESET_DONE_PIO2_LSB _u(13)
#define RESETS_RESET_DONE_PIO2_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_PIO1
#define RESETS_RESET_DONE_PIO1_RESET _u(0x0)
#define RESETS_RESET_DONE_PIO1_BITS _u(0x00001000)
#define RESETS_RESET_DONE_PIO1_MSB _u(12)
#define RESETS_RESET_DONE_PIO1_LSB _u(12)
#define RESETS_RESET_DONE_PIO1_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_PIO0
#define RESETS_RESET_DONE_PIO0_RESET _u(0x0)
#define RESETS_RESET_DONE_PIO0_BITS _u(0x00000800)
#define RESETS_RESET_DONE_PIO0_MSB _u(11)
#define RESETS_RESET_DONE_PIO0_LSB _u(11)
#define RESETS_RESET_DONE_PIO0_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_PADS_QSPI
#define RESETS_RESET_DONE_PADS_QSPI_RESET _u(0x0)
#define RESETS_RESET_DONE_PADS_QSPI_BITS _u(0x00000400)
#define RESETS_RESET_DONE_PADS_QSPI_MSB _u(10)
#define RESETS_RESET_DONE_PADS_QSPI_LSB _u(10)
#define RESETS_RESET_DONE_PADS_QSPI_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_PADS_BANK0
#define RESETS_RESET_DONE_PADS_BANK0_RESET _u(0x0)
#define RESETS_RESET_DONE_PADS_BANK0_BITS _u(0x00000200)
#define RESETS_RESET_DONE_PADS_BANK0_MSB _u(9)
#define RESETS_RESET_DONE_PADS_BANK0_LSB _u(9)
#define RESETS_RESET_DONE_PADS_BANK0_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_JTAG
#define RESETS_RESET_DONE_JTAG_RESET _u(0x0)
#define RESETS_RESET_DONE_JTAG_BITS _u(0x00000100)
#define RESETS_RESET_DONE_JTAG_MSB _u(8)
#define RESETS_RESET_DONE_JTAG_LSB _u(8)
#define RESETS_RESET_DONE_JTAG_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_IO_QSPI
#define RESETS_RESET_DONE_IO_QSPI_RESET _u(0x0)
#define RESETS_RESET_DONE_IO_QSPI_BITS _u(0x00000080)
#define RESETS_RESET_DONE_IO_QSPI_MSB _u(7)
#define RESETS_RESET_DONE_IO_QSPI_LSB _u(7)
#define RESETS_RESET_DONE_IO_QSPI_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_IO_BANK0
#define RESETS_RESET_DONE_IO_BANK0_RESET _u(0x0)
#define RESETS_RESET_DONE_IO_BANK0_BITS _u(0x00000040)
#define RESETS_RESET_DONE_IO_BANK0_MSB _u(6)
#define RESETS_RESET_DONE_IO_BANK0_LSB _u(6)
#define RESETS_RESET_DONE_IO_BANK0_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_I2C1
#define RESETS_RESET_DONE_I2C1_RESET _u(0x0)
#define RESETS_RESET_DONE_I2C1_BITS _u(0x00000020)
#define RESETS_RESET_DONE_I2C1_MSB _u(5)
#define RESETS_RESET_DONE_I2C1_LSB _u(5)
#define RESETS_RESET_DONE_I2C1_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_I2C0
#define RESETS_RESET_DONE_I2C0_RESET _u(0x0)
#define RESETS_RESET_DONE_I2C0_BITS _u(0x00000010)
#define RESETS_RESET_DONE_I2C0_MSB _u(4)
#define RESETS_RESET_DONE_I2C0_LSB _u(4)
#define RESETS_RESET_DONE_I2C0_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_HSTX
#define RESETS_RESET_DONE_HSTX_RESET _u(0x0)
#define RESETS_RESET_DONE_HSTX_BITS _u(0x00000008)
#define RESETS_RESET_DONE_HSTX_MSB _u(3)
#define RESETS_RESET_DONE_HSTX_LSB _u(3)
#define RESETS_RESET_DONE_HSTX_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_DMA
#define RESETS_RESET_DONE_DMA_RESET _u(0x0)
#define RESETS_RESET_DONE_DMA_BITS _u(0x00000004)
#define RESETS_RESET_DONE_DMA_MSB _u(2)
#define RESETS_RESET_DONE_DMA_LSB _u(2)
#define RESETS_RESET_DONE_DMA_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_BUSCTRL
#define RESETS_RESET_DONE_BUSCTRL_RESET _u(0x0)
#define RESETS_RESET_DONE_BUSCTRL_BITS _u(0x00000002)
#define RESETS_RESET_DONE_BUSCTRL_MSB _u(1)
#define RESETS_RESET_DONE_BUSCTRL_LSB _u(1)
#define RESETS_RESET_DONE_BUSCTRL_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_ADC
#define RESETS_RESET_DONE_ADC_RESET _u(0x0)
#define RESETS_RESET_DONE_ADC_BITS _u(0x00000001)
#define RESETS_RESET_DONE_ADC_MSB _u(0)
#define RESETS_RESET_DONE_ADC_LSB _u(0)
#define RESETS_RESET_DONE_ADC_ACCESS "RO"
// =============================================================================
#endif // _HARDWARE_REGS_RESETS_H

1025
arch/arm/src/rp23xx/hardware/regs/riscv_dm.h
View file

File diff suppressed because it is too large Load diff

345
arch/arm/src/rp23xx/hardware/regs/rosc.h
View file

@ -1,345 +0,0 @@
// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
// =============================================================================
// Register block : ROSC
// Version : 1
// Bus type : apb
// =============================================================================
#ifndef _HARDWARE_REGS_ROSC_H
#define _HARDWARE_REGS_ROSC_H
// =============================================================================
// Register : ROSC_CTRL
// Description : Ring Oscillator control
#define ROSC_CTRL_OFFSET _u(0x00000000)
#define ROSC_CTRL_BITS _u(0x00ffffff)
#define ROSC_CTRL_RESET _u(0x00000aa0)
// -----------------------------------------------------------------------------
// Field : ROSC_CTRL_ENABLE
// Description : On power-up this field is initialised to ENABLE
// The system clock must be switched to another source before
// setting this field to DISABLE otherwise the chip will lock up
// The 12-bit code is intended to give some protection against
// accidental writes. An invalid setting will enable the
// oscillator.
// 0xd1e -> DISABLE
// 0xfab -> ENABLE
#define ROSC_CTRL_ENABLE_RESET "-"
#define ROSC_CTRL_ENABLE_BITS _u(0x00fff000)
#define ROSC_CTRL_ENABLE_MSB _u(23)
#define ROSC_CTRL_ENABLE_LSB _u(12)
#define ROSC_CTRL_ENABLE_ACCESS "RW"
#define ROSC_CTRL_ENABLE_VALUE_DISABLE _u(0xd1e)
#define ROSC_CTRL_ENABLE_VALUE_ENABLE _u(0xfab)
// -----------------------------------------------------------------------------
// Field : ROSC_CTRL_FREQ_RANGE
// Description : Controls the number of delay stages in the ROSC ring
// LOW uses stages 0 to 7
// MEDIUM uses stages 2 to 7
// HIGH uses stages 4 to 7
// TOOHIGH uses stages 6 to 7 and should not be used because its
// frequency exceeds design specifications
// The clock output will not glitch when changing the range up one
// step at a time
// The clock output will glitch when changing the range down
// Note: the values here are gray coded which is why HIGH comes
// before TOOHIGH
// 0xfa4 -> LOW
// 0xfa5 -> MEDIUM
// 0xfa7 -> HIGH
// 0xfa6 -> TOOHIGH
#define ROSC_CTRL_FREQ_RANGE_RESET _u(0xaa0)
#define ROSC_CTRL_FREQ_RANGE_BITS _u(0x00000fff)
#define ROSC_CTRL_FREQ_RANGE_MSB _u(11)
#define ROSC_CTRL_FREQ_RANGE_LSB _u(0)
#define ROSC_CTRL_FREQ_RANGE_ACCESS "RW"
#define ROSC_CTRL_FREQ_RANGE_VALUE_LOW _u(0xfa4)
#define ROSC_CTRL_FREQ_RANGE_VALUE_MEDIUM _u(0xfa5)
#define ROSC_CTRL_FREQ_RANGE_VALUE_HIGH _u(0xfa7)
#define ROSC_CTRL_FREQ_RANGE_VALUE_TOOHIGH _u(0xfa6)
// =============================================================================
// Register : ROSC_FREQA
// Description : The FREQA & FREQB registers control the frequency by
// controlling the drive strength of each stage
// The drive strength has 4 levels determined by the number of
// bits set
// Increasing the number of bits set increases the drive strength
// and increases the oscillation frequency
// 0 bits set is the default drive strength
// 1 bit set doubles the drive strength
// 2 bits set triples drive strength
// 3 bits set quadruples drive strength
// For frequency randomisation set both DS0_RANDOM=1 &
// DS1_RANDOM=1
#define ROSC_FREQA_OFFSET _u(0x00000004)
#define ROSC_FREQA_BITS _u(0xffff77ff)
#define ROSC_FREQA_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : ROSC_FREQA_PASSWD
// Description : Set to 0x9696 to apply the settings
// Any other value in this field will set all drive strengths to 0
// 0x9696 -> PASS
#define ROSC_FREQA_PASSWD_RESET _u(0x0000)
#define ROSC_FREQA_PASSWD_BITS _u(0xffff0000)
#define ROSC_FREQA_PASSWD_MSB _u(31)
#define ROSC_FREQA_PASSWD_LSB _u(16)
#define ROSC_FREQA_PASSWD_ACCESS "RW"
#define ROSC_FREQA_PASSWD_VALUE_PASS _u(0x9696)
// -----------------------------------------------------------------------------
// Field : ROSC_FREQA_DS3
// Description : Stage 3 drive strength
#define ROSC_FREQA_DS3_RESET _u(0x0)
#define ROSC_FREQA_DS3_BITS _u(0x00007000)
#define ROSC_FREQA_DS3_MSB _u(14)
#define ROSC_FREQA_DS3_LSB _u(12)
#define ROSC_FREQA_DS3_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : ROSC_FREQA_DS2
// Description : Stage 2 drive strength
#define ROSC_FREQA_DS2_RESET _u(0x0)
#define ROSC_FREQA_DS2_BITS _u(0x00000700)
#define ROSC_FREQA_DS2_MSB _u(10)
#define ROSC_FREQA_DS2_LSB _u(8)
#define ROSC_FREQA_DS2_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : ROSC_FREQA_DS1_RANDOM
// Description : Randomises the stage 1 drive strength
#define ROSC_FREQA_DS1_RANDOM_RESET _u(0x0)
#define ROSC_FREQA_DS1_RANDOM_BITS _u(0x00000080)
#define ROSC_FREQA_DS1_RANDOM_MSB _u(7)
#define ROSC_FREQA_DS1_RANDOM_LSB _u(7)
#define ROSC_FREQA_DS1_RANDOM_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : ROSC_FREQA_DS1
// Description : Stage 1 drive strength
#define ROSC_FREQA_DS1_RESET _u(0x0)
#define ROSC_FREQA_DS1_BITS _u(0x00000070)
#define ROSC_FREQA_DS1_MSB _u(6)
#define ROSC_FREQA_DS1_LSB _u(4)
#define ROSC_FREQA_DS1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : ROSC_FREQA_DS0_RANDOM
// Description : Randomises the stage 0 drive strength
#define ROSC_FREQA_DS0_RANDOM_RESET _u(0x0)
#define ROSC_FREQA_DS0_RANDOM_BITS _u(0x00000008)
#define ROSC_FREQA_DS0_RANDOM_MSB _u(3)
#define ROSC_FREQA_DS0_RANDOM_LSB _u(3)
#define ROSC_FREQA_DS0_RANDOM_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : ROSC_FREQA_DS0
// Description : Stage 0 drive strength
#define ROSC_FREQA_DS0_RESET _u(0x0)
#define ROSC_FREQA_DS0_BITS _u(0x00000007)
#define ROSC_FREQA_DS0_MSB _u(2)
#define ROSC_FREQA_DS0_LSB _u(0)
#define ROSC_FREQA_DS0_ACCESS "RW"
// =============================================================================
// Register : ROSC_FREQB
// Description : For a detailed description see freqa register
#define ROSC_FREQB_OFFSET _u(0x00000008)
#define ROSC_FREQB_BITS _u(0xffff7777)
#define ROSC_FREQB_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : ROSC_FREQB_PASSWD
// Description : Set to 0x9696 to apply the settings
// Any other value in this field will set all drive strengths to 0
// 0x9696 -> PASS
#define ROSC_FREQB_PASSWD_RESET _u(0x0000)
#define ROSC_FREQB_PASSWD_BITS _u(0xffff0000)
#define ROSC_FREQB_PASSWD_MSB _u(31)
#define ROSC_FREQB_PASSWD_LSB _u(16)
#define ROSC_FREQB_PASSWD_ACCESS "RW"
#define ROSC_FREQB_PASSWD_VALUE_PASS _u(0x9696)
// -----------------------------------------------------------------------------
// Field : ROSC_FREQB_DS7
// Description : Stage 7 drive strength
#define ROSC_FREQB_DS7_RESET _u(0x0)
#define ROSC_FREQB_DS7_BITS _u(0x00007000)
#define ROSC_FREQB_DS7_MSB _u(14)
#define ROSC_FREQB_DS7_LSB _u(12)
#define ROSC_FREQB_DS7_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : ROSC_FREQB_DS6
// Description : Stage 6 drive strength
#define ROSC_FREQB_DS6_RESET _u(0x0)
#define ROSC_FREQB_DS6_BITS _u(0x00000700)
#define ROSC_FREQB_DS6_MSB _u(10)
#define ROSC_FREQB_DS6_LSB _u(8)
#define ROSC_FREQB_DS6_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : ROSC_FREQB_DS5
// Description : Stage 5 drive strength
#define ROSC_FREQB_DS5_RESET _u(0x0)
#define ROSC_FREQB_DS5_BITS _u(0x00000070)
#define ROSC_FREQB_DS5_MSB _u(6)
#define ROSC_FREQB_DS5_LSB _u(4)
#define ROSC_FREQB_DS5_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : ROSC_FREQB_DS4
// Description : Stage 4 drive strength
#define ROSC_FREQB_DS4_RESET _u(0x0)
#define ROSC_FREQB_DS4_BITS _u(0x00000007)
#define ROSC_FREQB_DS4_MSB _u(2)
#define ROSC_FREQB_DS4_LSB _u(0)
#define ROSC_FREQB_DS4_ACCESS "RW"
// =============================================================================
// Register : ROSC_RANDOM
// Description : Loads a value to the LFSR randomiser
#define ROSC_RANDOM_OFFSET _u(0x0000000c)
#define ROSC_RANDOM_BITS _u(0xffffffff)
#define ROSC_RANDOM_RESET _u(0x3f04b16d)
// -----------------------------------------------------------------------------
// Field : ROSC_RANDOM_SEED
#define ROSC_RANDOM_SEED_RESET _u(0x3f04b16d)
#define ROSC_RANDOM_SEED_BITS _u(0xffffffff)
#define ROSC_RANDOM_SEED_MSB _u(31)
#define ROSC_RANDOM_SEED_LSB _u(0)
#define ROSC_RANDOM_SEED_ACCESS "RW"
// =============================================================================
// Register : ROSC_DORMANT
// Description : Ring Oscillator pause control
// This is used to save power by pausing the ROSC
// On power-up this field is initialised to WAKE
// An invalid write will also select WAKE
// Warning: setup the irq before selecting dormant mode
// 0x636f6d61 -> dormant
// 0x77616b65 -> WAKE
#define ROSC_DORMANT_OFFSET _u(0x00000010)
#define ROSC_DORMANT_BITS _u(0xffffffff)
#define ROSC_DORMANT_RESET "-"
#define ROSC_DORMANT_MSB _u(31)
#define ROSC_DORMANT_LSB _u(0)
#define ROSC_DORMANT_ACCESS "RW"
#define ROSC_DORMANT_VALUE_DORMANT _u(0x636f6d61)
#define ROSC_DORMANT_VALUE_WAKE _u(0x77616b65)
// =============================================================================
// Register : ROSC_DIV
// Description : Controls the output divider
// set to 0xaa00 + div where
// div = 0 divides by 128
// div = 1-127 divides by div
// any other value sets div=128
// this register resets to div=32
// 0xaa00 -> PASS
#define ROSC_DIV_OFFSET _u(0x00000014)
#define ROSC_DIV_BITS _u(0x0000ffff)
#define ROSC_DIV_RESET "-"
#define ROSC_DIV_MSB _u(15)
#define ROSC_DIV_LSB _u(0)
#define ROSC_DIV_ACCESS "RW"
#define ROSC_DIV_VALUE_PASS _u(0xaa00)
// =============================================================================
// Register : ROSC_PHASE
// Description : Controls the phase shifted output
#define ROSC_PHASE_OFFSET _u(0x00000018)
#define ROSC_PHASE_BITS _u(0x00000fff)
#define ROSC_PHASE_RESET _u(0x00000008)
// -----------------------------------------------------------------------------
// Field : ROSC_PHASE_PASSWD
// Description : set to 0xaa
// any other value enables the output with shift=0
#define ROSC_PHASE_PASSWD_RESET _u(0x00)
#define ROSC_PHASE_PASSWD_BITS _u(0x00000ff0)
#define ROSC_PHASE_PASSWD_MSB _u(11)
#define ROSC_PHASE_PASSWD_LSB _u(4)
#define ROSC_PHASE_PASSWD_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : ROSC_PHASE_ENABLE
// Description : enable the phase-shifted output
// this can be changed on-the-fly
#define ROSC_PHASE_ENABLE_RESET _u(0x1)
#define ROSC_PHASE_ENABLE_BITS _u(0x00000008)
#define ROSC_PHASE_ENABLE_MSB _u(3)
#define ROSC_PHASE_ENABLE_LSB _u(3)
#define ROSC_PHASE_ENABLE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : ROSC_PHASE_FLIP
// Description : invert the phase-shifted output
// this is ignored when div=1
#define ROSC_PHASE_FLIP_RESET _u(0x0)
#define ROSC_PHASE_FLIP_BITS _u(0x00000004)
#define ROSC_PHASE_FLIP_MSB _u(2)
#define ROSC_PHASE_FLIP_LSB _u(2)
#define ROSC_PHASE_FLIP_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : ROSC_PHASE_SHIFT
// Description : phase shift the phase-shifted output by SHIFT input clocks
// this can be changed on-the-fly
// must be set to 0 before setting div=1
#define ROSC_PHASE_SHIFT_RESET _u(0x0)
#define ROSC_PHASE_SHIFT_BITS _u(0x00000003)
#define ROSC_PHASE_SHIFT_MSB _u(1)
#define ROSC_PHASE_SHIFT_LSB _u(0)
#define ROSC_PHASE_SHIFT_ACCESS "RW"
// =============================================================================
// Register : ROSC_STATUS
// Description : Ring Oscillator Status
#define ROSC_STATUS_OFFSET _u(0x0000001c)
#define ROSC_STATUS_BITS _u(0x81011000)
#define ROSC_STATUS_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : ROSC_STATUS_STABLE
// Description : Oscillator is running and stable
#define ROSC_STATUS_STABLE_RESET _u(0x0)
#define ROSC_STATUS_STABLE_BITS _u(0x80000000)
#define ROSC_STATUS_STABLE_MSB _u(31)
#define ROSC_STATUS_STABLE_LSB _u(31)
#define ROSC_STATUS_STABLE_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : ROSC_STATUS_BADWRITE
// Description : An invalid value has been written to CTRL_ENABLE or
// CTRL_FREQ_RANGE or FREQA or FREQB or DIV or PHASE or DORMANT
#define ROSC_STATUS_BADWRITE_RESET _u(0x0)
#define ROSC_STATUS_BADWRITE_BITS _u(0x01000000)
#define ROSC_STATUS_BADWRITE_MSB _u(24)
#define ROSC_STATUS_BADWRITE_LSB _u(24)
#define ROSC_STATUS_BADWRITE_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : ROSC_STATUS_DIV_RUNNING
// Description : post-divider is running
// this resets to 0 but transitions to 1 during chip startup
#define ROSC_STATUS_DIV_RUNNING_RESET "-"
#define ROSC_STATUS_DIV_RUNNING_BITS _u(0x00010000)
#define ROSC_STATUS_DIV_RUNNING_MSB _u(16)
#define ROSC_STATUS_DIV_RUNNING_LSB _u(16)
#define ROSC_STATUS_DIV_RUNNING_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : ROSC_STATUS_ENABLED
// Description : Oscillator is enabled but not necessarily running and stable
// this resets to 0 but transitions to 1 during chip startup
#define ROSC_STATUS_ENABLED_RESET "-"
#define ROSC_STATUS_ENABLED_BITS _u(0x00001000)
#define ROSC_STATUS_ENABLED_MSB _u(12)
#define ROSC_STATUS_ENABLED_LSB _u(12)
#define ROSC_STATUS_ENABLED_ACCESS "RO"
// =============================================================================
// Register : ROSC_RANDOMBIT
// Description : This just reads the state of the oscillator output so
// randomness is compromised if the ring oscillator is stopped or
// run at a harmonic of the bus frequency
#define ROSC_RANDOMBIT_OFFSET _u(0x00000020)
#define ROSC_RANDOMBIT_BITS _u(0x00000001)
#define ROSC_RANDOMBIT_RESET _u(0x00000001)
#define ROSC_RANDOMBIT_MSB _u(0)
#define ROSC_RANDOMBIT_LSB _u(0)
#define ROSC_RANDOMBIT_ACCESS "RO"
// =============================================================================
// Register : ROSC_COUNT
// Description : A down counter running at the ROSC frequency which counts to
// zero and stops.
// To start the counter write a non-zero value.
// Can be used for short software pauses when setting up time
// sensitive hardware.
#define ROSC_COUNT_OFFSET _u(0x00000024)
#define ROSC_COUNT_BITS _u(0x0000ffff)
#define ROSC_COUNT_RESET _u(0x00000000)
#define ROSC_COUNT_MSB _u(15)
#define ROSC_COUNT_LSB _u(0)
#define ROSC_COUNT_ACCESS "RW"
// =============================================================================
#endif // _HARDWARE_REGS_ROSC_H

729
arch/arm/src/rp23xx/hardware/regs/rp_ap.h
View file

@ -1,729 +0,0 @@
// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
// =============================================================================
// Register block : RP_AP
// Version : 1
// Bus type : apb
// =============================================================================
#ifndef _HARDWARE_REGS_RP_AP_H
#define _HARDWARE_REGS_RP_AP_H
// =============================================================================
// Register : RP_AP_CTRL
// Description : This register is primarily used for DFT but can also be used to
// overcome some power up problems. However, it should not be used
// to force power up of domains. Use DBG_POW_OVRD for that.
#define RP_AP_CTRL_OFFSET _u(0x00000000)
#define RP_AP_CTRL_BITS _u(0xc000007f)
#define RP_AP_CTRL_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : RP_AP_CTRL_RESCUE_RESTART
// Description : Allows debug of boot problems by restarting the chip with
// minimal boot code execution. Write to 1 to put the chip in
// reset then write to 0 to restart the chip with the rescue flag
// set. The rescue flag is in the POWMAN_CHIP_RESET register and
// is read by boot code. The rescue flag is cleared by writing 0
// to POWMAN_CHIP_RESET_RESCUE_FLAG or by resetting the chip by
// any means other than RESCUE_RESTART.
#define RP_AP_CTRL_RESCUE_RESTART_RESET _u(0x0)
#define RP_AP_CTRL_RESCUE_RESTART_BITS _u(0x80000000)
#define RP_AP_CTRL_RESCUE_RESTART_MSB _u(31)
#define RP_AP_CTRL_RESCUE_RESTART_LSB _u(31)
#define RP_AP_CTRL_RESCUE_RESTART_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RP_AP_CTRL_SPARE
// Description : Unused
#define RP_AP_CTRL_SPARE_RESET _u(0x0)
#define RP_AP_CTRL_SPARE_BITS _u(0x40000000)
#define RP_AP_CTRL_SPARE_MSB _u(30)
#define RP_AP_CTRL_SPARE_LSB _u(30)
#define RP_AP_CTRL_SPARE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RP_AP_CTRL_DBG_FRCE_GPIO_LPCK
// Description : Allows chip start-up when the Low Power Oscillator (LPOSC) is
// inoperative or malfunctioning and also allows the initial power
// sequencing rate to be adjusted. Write to 1 to force the LPOSC
// output to be driven from a GPIO (gpio20 on 80-pin package,
// gpio34 on the 60-pin package). If the LPOSC is inoperative or
// malfunctioning it may also be necessary to set the
// LPOSC_STABLE_FRCE bit in this register. The user must provide a
// clock on the GPIO. For normal operation use a clock running at
// around 32kHz. Adjusting the frequency will speed up or slow
// down the initial power-up sequence.
#define RP_AP_CTRL_DBG_FRCE_GPIO_LPCK_RESET _u(0x0)
#define RP_AP_CTRL_DBG_FRCE_GPIO_LPCK_BITS _u(0x00000040)
#define RP_AP_CTRL_DBG_FRCE_GPIO_LPCK_MSB _u(6)
#define RP_AP_CTRL_DBG_FRCE_GPIO_LPCK_LSB _u(6)
#define RP_AP_CTRL_DBG_FRCE_GPIO_LPCK_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RP_AP_CTRL_LPOSC_STABLE_FRCE
// Description : Allows the chip to start-up even though the Low Power
// Oscillator (LPOSC) is failing to set its stable flag. Initial
// power sequencing is clocked by LPOSC at around 32kHz but does
// not start until the LPOSC declares itself to be stable. If the
// LPOSC is otherwise working correctly the chip will boot when
// this bit is set. If the LPOSC is not working then
// DBG_FRCE_GPIO_LPCK must be set and an external clock provided.
#define RP_AP_CTRL_LPOSC_STABLE_FRCE_RESET _u(0x0)
#define RP_AP_CTRL_LPOSC_STABLE_FRCE_BITS _u(0x00000020)
#define RP_AP_CTRL_LPOSC_STABLE_FRCE_MSB _u(5)
#define RP_AP_CTRL_LPOSC_STABLE_FRCE_LSB _u(5)
#define RP_AP_CTRL_LPOSC_STABLE_FRCE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RP_AP_CTRL_POWMAN_DFT_ISO_OFF
// Description : Holds the isolation gates between power domains in the open
// state. This is intended to hold the gates open for DFT and
// power manager debug. It is not intended to force the isolation
// gates open. Use the overrides in DBG_POW_OVRD to force the
// isolation gates open or closed.
#define RP_AP_CTRL_POWMAN_DFT_ISO_OFF_RESET _u(0x0)
#define RP_AP_CTRL_POWMAN_DFT_ISO_OFF_BITS _u(0x00000010)
#define RP_AP_CTRL_POWMAN_DFT_ISO_OFF_MSB _u(4)
#define RP_AP_CTRL_POWMAN_DFT_ISO_OFF_LSB _u(4)
#define RP_AP_CTRL_POWMAN_DFT_ISO_OFF_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RP_AP_CTRL_POWMAN_DFT_PWRON
// Description : Holds the power switches on for all domains. This is intended
// to keep the power on for DFT and debug, rather than for
// switching the power on. The power switches are not sequenced
// and the sudden demand for current could cause the always-on
// power domain to brown out. This register is in the always-on
// domain therefore chaos could ensue. It is recommended to use
// the DBG_POW_OVRD controls instead.
#define RP_AP_CTRL_POWMAN_DFT_PWRON_RESET _u(0x0)
#define RP_AP_CTRL_POWMAN_DFT_PWRON_BITS _u(0x00000008)
#define RP_AP_CTRL_POWMAN_DFT_PWRON_MSB _u(3)
#define RP_AP_CTRL_POWMAN_DFT_PWRON_LSB _u(3)
#define RP_AP_CTRL_POWMAN_DFT_PWRON_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RP_AP_CTRL_POWMAN_DBGMODE
// Description : This prevents the power manager from powering down and
// resetting the switched-core power domain. It is intended for
// DFT and for debugging the power manager after the chip has
// booted. It cannot be used to force initial power on because it
// simultaneously deasserts the reset.
#define RP_AP_CTRL_POWMAN_DBGMODE_RESET _u(0x0)
#define RP_AP_CTRL_POWMAN_DBGMODE_BITS _u(0x00000004)
#define RP_AP_CTRL_POWMAN_DBGMODE_MSB _u(2)
#define RP_AP_CTRL_POWMAN_DBGMODE_LSB _u(2)
#define RP_AP_CTRL_POWMAN_DBGMODE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RP_AP_CTRL_JTAG_FUNCSEL
// Description : Multiplexes the JTAG ports onto GPIO0-3
#define RP_AP_CTRL_JTAG_FUNCSEL_RESET _u(0x0)
#define RP_AP_CTRL_JTAG_FUNCSEL_BITS _u(0x00000002)
#define RP_AP_CTRL_JTAG_FUNCSEL_MSB _u(1)
#define RP_AP_CTRL_JTAG_FUNCSEL_LSB _u(1)
#define RP_AP_CTRL_JTAG_FUNCSEL_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RP_AP_CTRL_JTAG_TRSTN
// Description : Resets the JTAG module. Active low.
#define RP_AP_CTRL_JTAG_TRSTN_RESET _u(0x0)
#define RP_AP_CTRL_JTAG_TRSTN_BITS _u(0x00000001)
#define RP_AP_CTRL_JTAG_TRSTN_MSB _u(0)
#define RP_AP_CTRL_JTAG_TRSTN_LSB _u(0)
#define RP_AP_CTRL_JTAG_TRSTN_ACCESS "RW"
// =============================================================================
// Register : RP_AP_DBGKEY
// Description : Serial key load interface (write-only)
#define RP_AP_DBGKEY_OFFSET _u(0x00000004)
#define RP_AP_DBGKEY_BITS _u(0x00000007)
#define RP_AP_DBGKEY_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : RP_AP_DBGKEY_RESET
// Description : Reset (before sending a new key)
#define RP_AP_DBGKEY_RESET_RESET _u(0x0)
#define RP_AP_DBGKEY_RESET_BITS _u(0x00000004)
#define RP_AP_DBGKEY_RESET_MSB _u(2)
#define RP_AP_DBGKEY_RESET_LSB _u(2)
#define RP_AP_DBGKEY_RESET_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RP_AP_DBGKEY_PUSH
#define RP_AP_DBGKEY_PUSH_RESET _u(0x0)
#define RP_AP_DBGKEY_PUSH_BITS _u(0x00000002)
#define RP_AP_DBGKEY_PUSH_MSB _u(1)
#define RP_AP_DBGKEY_PUSH_LSB _u(1)
#define RP_AP_DBGKEY_PUSH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RP_AP_DBGKEY_DATA
#define RP_AP_DBGKEY_DATA_RESET _u(0x0)
#define RP_AP_DBGKEY_DATA_BITS _u(0x00000001)
#define RP_AP_DBGKEY_DATA_MSB _u(0)
#define RP_AP_DBGKEY_DATA_LSB _u(0)
#define RP_AP_DBGKEY_DATA_ACCESS "RW"
// =============================================================================
// Register : RP_AP_DBG_POW_STATE_SWCORE
// Description : This register indicates the state of the power sequencer for
// the switched-core domain.
// The sequencer timing is managed by the POWMAN_SEQ_* registers.
// See the header file for those registers for more information on
// the timing.
// Power up of the domain commences by clearing bit 0 (IS_PD) then
// bits 1-8 are set in sequence. Bit 8 (IS_PU) indicates the
// sequence is complete.
// Power down of the domain commences by clearing bit 8 (IS_PU)
// then bits 7-1 are cleared in sequence. Bit 0 (IS_PU) is then
// set to indicate the sequence is complete.
// Bits 9-11 describe the states of the power manager clocks which
// change as clock generators in the switched-core become
// available following switched-core power up.
// This bus can be sent to GPIO for debug. See
// DBG_POW_OUTPUT_TO_GPIO in the DBG_POW_OVRD register.
#define RP_AP_DBG_POW_STATE_SWCORE_OFFSET _u(0x00000008)
#define RP_AP_DBG_POW_STATE_SWCORE_BITS _u(0x00000fff)
#define RP_AP_DBG_POW_STATE_SWCORE_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : RP_AP_DBG_POW_STATE_SWCORE_USING_FAST_POWCK
// Description : Indicates the source of the power manager clock. On switched-
// core power up the clock switches from the LPOSC to clk_ref and
// this flag will be set. clk_ref will be running from the ROSC
// initially but will switch to XOSC when it comes available. On
// switched-core power down the clock switches to LPOSC and this
// flag will be cleared.
#define RP_AP_DBG_POW_STATE_SWCORE_USING_FAST_POWCK_RESET _u(0x0)
#define RP_AP_DBG_POW_STATE_SWCORE_USING_FAST_POWCK_BITS _u(0x00000800)
#define RP_AP_DBG_POW_STATE_SWCORE_USING_FAST_POWCK_MSB _u(11)
#define RP_AP_DBG_POW_STATE_SWCORE_USING_FAST_POWCK_LSB _u(11)
#define RP_AP_DBG_POW_STATE_SWCORE_USING_FAST_POWCK_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RP_AP_DBG_POW_STATE_SWCORE_WAITING_POWCK
// Description : Indicates the switched-core power sequencer is waiting for the
// power manager clock to update. On switched-core power up the
// clock switches from the LPOSC to clk_ref. clk_ref will be
// running from the ROSC initially but will switch to XOSC when it
// comes available. On switched-core power down the clock switches
// to LPOSC.
// If the switched-core power up sequence stalls with this flag
// active then it means clk_ref is not running which indicates a
// problem with the ROSC. If that happens then set
// DBG_POW_RESTART_FROM_XOSC in the DBG_POW_OVRD register to avoid
// using the ROSC.
// If the switched-core power down sequence stalls with this flag
// active then it means LPOSC is not running. The solution is to
// not stop LPOSC when the switched-core power domain is powered.
#define RP_AP_DBG_POW_STATE_SWCORE_WAITING_POWCK_RESET _u(0x0)
#define RP_AP_DBG_POW_STATE_SWCORE_WAITING_POWCK_BITS _u(0x00000400)
#define RP_AP_DBG_POW_STATE_SWCORE_WAITING_POWCK_MSB _u(10)
#define RP_AP_DBG_POW_STATE_SWCORE_WAITING_POWCK_LSB _u(10)
#define RP_AP_DBG_POW_STATE_SWCORE_WAITING_POWCK_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RP_AP_DBG_POW_STATE_SWCORE_WAITING_TIMCK
// Description : Indicates that the switched-core power sequencer is waiting for
// the AON-Timer to update. On switched-core power-up there is
// nothing to be done. The AON-Timer continues to run from the
// LPOSC so this flag will not be set. Software decides whether to
// switch the AON-Timer clock to XOSC (via clk_ref). On switched-
// core power-down the sequencer will switch the AON-Timer back to
// LPOSC if software switched it to XOSC. During the switchover
// the WAITING_TIMCK flag will be set. If the switched-core power
// down sequence stalls with this flag active then the only
// recourse is to reset the chip and change software to not select
// XOSC as the AON-Timer source.
#define RP_AP_DBG_POW_STATE_SWCORE_WAITING_TIMCK_RESET _u(0x0)
#define RP_AP_DBG_POW_STATE_SWCORE_WAITING_TIMCK_BITS _u(0x00000200)
#define RP_AP_DBG_POW_STATE_SWCORE_WAITING_TIMCK_MSB _u(9)
#define RP_AP_DBG_POW_STATE_SWCORE_WAITING_TIMCK_LSB _u(9)
#define RP_AP_DBG_POW_STATE_SWCORE_WAITING_TIMCK_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RP_AP_DBG_POW_STATE_SWCORE_IS_PU
// Description : Indicates the power somain is fully powered up.
#define RP_AP_DBG_POW_STATE_SWCORE_IS_PU_RESET _u(0x0)
#define RP_AP_DBG_POW_STATE_SWCORE_IS_PU_BITS _u(0x00000100)
#define RP_AP_DBG_POW_STATE_SWCORE_IS_PU_MSB _u(8)
#define RP_AP_DBG_POW_STATE_SWCORE_IS_PU_LSB _u(8)
#define RP_AP_DBG_POW_STATE_SWCORE_IS_PU_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RP_AP_DBG_POW_STATE_SWCORE_RESET_FROM_SEQ
// Description : Indicates the state of the reset to the power domain.
#define RP_AP_DBG_POW_STATE_SWCORE_RESET_FROM_SEQ_RESET _u(0x0)
#define RP_AP_DBG_POW_STATE_SWCORE_RESET_FROM_SEQ_BITS _u(0x00000080)
#define RP_AP_DBG_POW_STATE_SWCORE_RESET_FROM_SEQ_MSB _u(7)
#define RP_AP_DBG_POW_STATE_SWCORE_RESET_FROM_SEQ_LSB _u(7)
#define RP_AP_DBG_POW_STATE_SWCORE_RESET_FROM_SEQ_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RP_AP_DBG_POW_STATE_SWCORE_ENAB_ACK
// Description : Indicates the state of the enable to the power domain.
#define RP_AP_DBG_POW_STATE_SWCORE_ENAB_ACK_RESET _u(0x0)
#define RP_AP_DBG_POW_STATE_SWCORE_ENAB_ACK_BITS _u(0x00000040)
#define RP_AP_DBG_POW_STATE_SWCORE_ENAB_ACK_MSB _u(6)
#define RP_AP_DBG_POW_STATE_SWCORE_ENAB_ACK_LSB _u(6)
#define RP_AP_DBG_POW_STATE_SWCORE_ENAB_ACK_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RP_AP_DBG_POW_STATE_SWCORE_ISOLATE_FROM_SEQ
// Description : Indicates the state of the isolation control to the power
// domain.
#define RP_AP_DBG_POW_STATE_SWCORE_ISOLATE_FROM_SEQ_RESET _u(0x0)
#define RP_AP_DBG_POW_STATE_SWCORE_ISOLATE_FROM_SEQ_BITS _u(0x00000020)
#define RP_AP_DBG_POW_STATE_SWCORE_ISOLATE_FROM_SEQ_MSB _u(5)
#define RP_AP_DBG_POW_STATE_SWCORE_ISOLATE_FROM_SEQ_LSB _u(5)
#define RP_AP_DBG_POW_STATE_SWCORE_ISOLATE_FROM_SEQ_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RP_AP_DBG_POW_STATE_SWCORE_LARGE_ACK
// Description : Indicates the state of the large power switches for the power
// domain.
#define RP_AP_DBG_POW_STATE_SWCORE_LARGE_ACK_RESET _u(0x0)
#define RP_AP_DBG_POW_STATE_SWCORE_LARGE_ACK_BITS _u(0x00000010)
#define RP_AP_DBG_POW_STATE_SWCORE_LARGE_ACK_MSB _u(4)
#define RP_AP_DBG_POW_STATE_SWCORE_LARGE_ACK_LSB _u(4)
#define RP_AP_DBG_POW_STATE_SWCORE_LARGE_ACK_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RP_AP_DBG_POW_STATE_SWCORE_SMALL_ACK2
// Description : The small switches are split into 3 chains. In the power up
// sequence they are switched on separately to allow management of
// the VDD rise time. In the power down sequence they switch off
// simultaneously with the large power switches.
// This bit indicates the state of the last element in small power
// switch chain 2.
#define RP_AP_DBG_POW_STATE_SWCORE_SMALL_ACK2_RESET _u(0x0)
#define RP_AP_DBG_POW_STATE_SWCORE_SMALL_ACK2_BITS _u(0x00000008)
#define RP_AP_DBG_POW_STATE_SWCORE_SMALL_ACK2_MSB _u(3)
#define RP_AP_DBG_POW_STATE_SWCORE_SMALL_ACK2_LSB _u(3)
#define RP_AP_DBG_POW_STATE_SWCORE_SMALL_ACK2_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RP_AP_DBG_POW_STATE_SWCORE_SMALL_ACK1
// Description : This bit indicates the state of the last element in small power
// switch chain 1.
#define RP_AP_DBG_POW_STATE_SWCORE_SMALL_ACK1_RESET _u(0x0)
#define RP_AP_DBG_POW_STATE_SWCORE_SMALL_ACK1_BITS _u(0x00000004)
#define RP_AP_DBG_POW_STATE_SWCORE_SMALL_ACK1_MSB _u(2)
#define RP_AP_DBG_POW_STATE_SWCORE_SMALL_ACK1_LSB _u(2)
#define RP_AP_DBG_POW_STATE_SWCORE_SMALL_ACK1_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RP_AP_DBG_POW_STATE_SWCORE_SMALL_ACK0
// Description : This bit indicates the state of the last element in small power
// switch chain 0.
#define RP_AP_DBG_POW_STATE_SWCORE_SMALL_ACK0_RESET _u(0x0)
#define RP_AP_DBG_POW_STATE_SWCORE_SMALL_ACK0_BITS _u(0x00000002)
#define RP_AP_DBG_POW_STATE_SWCORE_SMALL_ACK0_MSB _u(1)
#define RP_AP_DBG_POW_STATE_SWCORE_SMALL_ACK0_LSB _u(1)
#define RP_AP_DBG_POW_STATE_SWCORE_SMALL_ACK0_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RP_AP_DBG_POW_STATE_SWCORE_IS_PD
// Description : Indicates the power somain is fully powered down.
#define RP_AP_DBG_POW_STATE_SWCORE_IS_PD_RESET _u(0x0)
#define RP_AP_DBG_POW_STATE_SWCORE_IS_PD_BITS _u(0x00000001)
#define RP_AP_DBG_POW_STATE_SWCORE_IS_PD_MSB _u(0)
#define RP_AP_DBG_POW_STATE_SWCORE_IS_PD_LSB _u(0)
#define RP_AP_DBG_POW_STATE_SWCORE_IS_PD_ACCESS "RO"
// =============================================================================
// Register : RP_AP_DBG_POW_STATE_XIP
// Description : This register indicates the state of the power sequencer for
// the XIP domain.
// The sequencer timing is managed by the POWMAN_SEQ_* registers.
// See the header file for those registers for more information on
// the timing.
// Power up of the domain commences by clearing bit 0 (IS_PD) then
// bits 1-8 are set in sequence. Bit 8 (IS_PU) indicates the
// sequence is complete.
// Power down of the domain commences by clearing bit 8 (IS_PU)
// then bits 7-1 are cleared in sequence. Bit 0 (IS_PU) is then
// set to indicate the sequence is complete.
#define RP_AP_DBG_POW_STATE_XIP_OFFSET _u(0x0000000c)
#define RP_AP_DBG_POW_STATE_XIP_BITS _u(0x000001ff)
#define RP_AP_DBG_POW_STATE_XIP_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : RP_AP_DBG_POW_STATE_XIP_IS_PU
// Description : Indicates the power somain is fully powered up.
#define RP_AP_DBG_POW_STATE_XIP_IS_PU_RESET _u(0x0)
#define RP_AP_DBG_POW_STATE_XIP_IS_PU_BITS _u(0x00000100)
#define RP_AP_DBG_POW_STATE_XIP_IS_PU_MSB _u(8)
#define RP_AP_DBG_POW_STATE_XIP_IS_PU_LSB _u(8)
#define RP_AP_DBG_POW_STATE_XIP_IS_PU_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RP_AP_DBG_POW_STATE_XIP_RESET_FROM_SEQ
// Description : Indicates the state of the reset to the power domain.
#define RP_AP_DBG_POW_STATE_XIP_RESET_FROM_SEQ_RESET _u(0x0)
#define RP_AP_DBG_POW_STATE_XIP_RESET_FROM_SEQ_BITS _u(0x00000080)
#define RP_AP_DBG_POW_STATE_XIP_RESET_FROM_SEQ_MSB _u(7)
#define RP_AP_DBG_POW_STATE_XIP_RESET_FROM_SEQ_LSB _u(7)
#define RP_AP_DBG_POW_STATE_XIP_RESET_FROM_SEQ_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RP_AP_DBG_POW_STATE_XIP_ENAB_ACK
// Description : Indicates the state of the enable to the power domain.
#define RP_AP_DBG_POW_STATE_XIP_ENAB_ACK_RESET _u(0x0)
#define RP_AP_DBG_POW_STATE_XIP_ENAB_ACK_BITS _u(0x00000040)
#define RP_AP_DBG_POW_STATE_XIP_ENAB_ACK_MSB _u(6)
#define RP_AP_DBG_POW_STATE_XIP_ENAB_ACK_LSB _u(6)
#define RP_AP_DBG_POW_STATE_XIP_ENAB_ACK_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RP_AP_DBG_POW_STATE_XIP_ISOLATE_FROM_SEQ
// Description : Indicates the state of the isolation control to the power
// domain.
#define RP_AP_DBG_POW_STATE_XIP_ISOLATE_FROM_SEQ_RESET _u(0x0)
#define RP_AP_DBG_POW_STATE_XIP_ISOLATE_FROM_SEQ_BITS _u(0x00000020)
#define RP_AP_DBG_POW_STATE_XIP_ISOLATE_FROM_SEQ_MSB _u(5)
#define RP_AP_DBG_POW_STATE_XIP_ISOLATE_FROM_SEQ_LSB _u(5)
#define RP_AP_DBG_POW_STATE_XIP_ISOLATE_FROM_SEQ_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RP_AP_DBG_POW_STATE_XIP_LARGE_ACK
// Description : Indicates the state of the large power switches for the power
// domain.
#define RP_AP_DBG_POW_STATE_XIP_LARGE_ACK_RESET _u(0x0)
#define RP_AP_DBG_POW_STATE_XIP_LARGE_ACK_BITS _u(0x00000010)
#define RP_AP_DBG_POW_STATE_XIP_LARGE_ACK_MSB _u(4)
#define RP_AP_DBG_POW_STATE_XIP_LARGE_ACK_LSB _u(4)
#define RP_AP_DBG_POW_STATE_XIP_LARGE_ACK_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RP_AP_DBG_POW_STATE_XIP_SMALL_ACK2
// Description : The small switches are split into 3 chains. In the power up
// sequence they are switched on separately to allow management of
// the VDD rise time. In the power down sequence they switch off
// simultaneously with the large power switches.
// This bit indicates the state of the last element in small power
// switch chain 2.
#define RP_AP_DBG_POW_STATE_XIP_SMALL_ACK2_RESET _u(0x0)
#define RP_AP_DBG_POW_STATE_XIP_SMALL_ACK2_BITS _u(0x00000008)
#define RP_AP_DBG_POW_STATE_XIP_SMALL_ACK2_MSB _u(3)
#define RP_AP_DBG_POW_STATE_XIP_SMALL_ACK2_LSB _u(3)
#define RP_AP_DBG_POW_STATE_XIP_SMALL_ACK2_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RP_AP_DBG_POW_STATE_XIP_SMALL_ACK1
// Description : This bit indicates the state of the last element in small power
// switch chain 1.
#define RP_AP_DBG_POW_STATE_XIP_SMALL_ACK1_RESET _u(0x0)
#define RP_AP_DBG_POW_STATE_XIP_SMALL_ACK1_BITS _u(0x00000004)
#define RP_AP_DBG_POW_STATE_XIP_SMALL_ACK1_MSB _u(2)
#define RP_AP_DBG_POW_STATE_XIP_SMALL_ACK1_LSB _u(2)
#define RP_AP_DBG_POW_STATE_XIP_SMALL_ACK1_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RP_AP_DBG_POW_STATE_XIP_SMALL_ACK0
// Description : This bit indicates the state of the last element in small power
// switch chain 0.
#define RP_AP_DBG_POW_STATE_XIP_SMALL_ACK0_RESET _u(0x0)
#define RP_AP_DBG_POW_STATE_XIP_SMALL_ACK0_BITS _u(0x00000002)
#define RP_AP_DBG_POW_STATE_XIP_SMALL_ACK0_MSB _u(1)
#define RP_AP_DBG_POW_STATE_XIP_SMALL_ACK0_LSB _u(1)
#define RP_AP_DBG_POW_STATE_XIP_SMALL_ACK0_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RP_AP_DBG_POW_STATE_XIP_IS_PD
// Description : Indicates the power somain is fully powered down.
#define RP_AP_DBG_POW_STATE_XIP_IS_PD_RESET _u(0x0)
#define RP_AP_DBG_POW_STATE_XIP_IS_PD_BITS _u(0x00000001)
#define RP_AP_DBG_POW_STATE_XIP_IS_PD_MSB _u(0)
#define RP_AP_DBG_POW_STATE_XIP_IS_PD_LSB _u(0)
#define RP_AP_DBG_POW_STATE_XIP_IS_PD_ACCESS "RO"
// =============================================================================
// Register : RP_AP_DBG_POW_STATE_SRAM0
// Description : This register indicates the state of the power sequencer for
// the SRAM0 domain.
// The sequencer timing is managed by the POWMAN_SEQ_* registers.
// See the header file for those registers for more information on
// the timing.
// Power up of the domain commences by clearing bit 0 (IS_PD) then
// bits 1-8 are set in sequence. Bit 8 (IS_PU) indicates the
// sequence is complete.
// Power down of the domain commences by clearing bit 8 (IS_PU)
// then bits 7-1 are cleared in sequence. Bit 0 (IS_PU) is then
// set to indicate the sequence is complete.
#define RP_AP_DBG_POW_STATE_SRAM0_OFFSET _u(0x00000010)
#define RP_AP_DBG_POW_STATE_SRAM0_BITS _u(0x000001ff)
#define RP_AP_DBG_POW_STATE_SRAM0_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : RP_AP_DBG_POW_STATE_SRAM0_IS_PU
// Description : Indicates the power somain is fully powered up.
#define RP_AP_DBG_POW_STATE_SRAM0_IS_PU_RESET _u(0x0)
#define RP_AP_DBG_POW_STATE_SRAM0_IS_PU_BITS _u(0x00000100)
#define RP_AP_DBG_POW_STATE_SRAM0_IS_PU_MSB _u(8)
#define RP_AP_DBG_POW_STATE_SRAM0_IS_PU_LSB _u(8)
#define RP_AP_DBG_POW_STATE_SRAM0_IS_PU_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RP_AP_DBG_POW_STATE_SRAM0_RESET_FROM_SEQ
// Description : Indicates the state of the reset to the power domain.
#define RP_AP_DBG_POW_STATE_SRAM0_RESET_FROM_SEQ_RESET _u(0x0)
#define RP_AP_DBG_POW_STATE_SRAM0_RESET_FROM_SEQ_BITS _u(0x00000080)
#define RP_AP_DBG_POW_STATE_SRAM0_RESET_FROM_SEQ_MSB _u(7)
#define RP_AP_DBG_POW_STATE_SRAM0_RESET_FROM_SEQ_LSB _u(7)
#define RP_AP_DBG_POW_STATE_SRAM0_RESET_FROM_SEQ_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RP_AP_DBG_POW_STATE_SRAM0_ENAB_ACK
// Description : Indicates the state of the enable to the power domain.
#define RP_AP_DBG_POW_STATE_SRAM0_ENAB_ACK_RESET _u(0x0)
#define RP_AP_DBG_POW_STATE_SRAM0_ENAB_ACK_BITS _u(0x00000040)
#define RP_AP_DBG_POW_STATE_SRAM0_ENAB_ACK_MSB _u(6)
#define RP_AP_DBG_POW_STATE_SRAM0_ENAB_ACK_LSB _u(6)
#define RP_AP_DBG_POW_STATE_SRAM0_ENAB_ACK_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RP_AP_DBG_POW_STATE_SRAM0_ISOLATE_FROM_SEQ
// Description : Indicates the state of the isolation control to the power
// domain.
#define RP_AP_DBG_POW_STATE_SRAM0_ISOLATE_FROM_SEQ_RESET _u(0x0)
#define RP_AP_DBG_POW_STATE_SRAM0_ISOLATE_FROM_SEQ_BITS _u(0x00000020)
#define RP_AP_DBG_POW_STATE_SRAM0_ISOLATE_FROM_SEQ_MSB _u(5)
#define RP_AP_DBG_POW_STATE_SRAM0_ISOLATE_FROM_SEQ_LSB _u(5)
#define RP_AP_DBG_POW_STATE_SRAM0_ISOLATE_FROM_SEQ_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RP_AP_DBG_POW_STATE_SRAM0_LARGE_ACK
// Description : Indicates the state of the large power switches for the power
// domain.
#define RP_AP_DBG_POW_STATE_SRAM0_LARGE_ACK_RESET _u(0x0)
#define RP_AP_DBG_POW_STATE_SRAM0_LARGE_ACK_BITS _u(0x00000010)
#define RP_AP_DBG_POW_STATE_SRAM0_LARGE_ACK_MSB _u(4)
#define RP_AP_DBG_POW_STATE_SRAM0_LARGE_ACK_LSB _u(4)
#define RP_AP_DBG_POW_STATE_SRAM0_LARGE_ACK_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RP_AP_DBG_POW_STATE_SRAM0_SMALL_ACK2
// Description : The small switches are split into 3 chains. In the power up
// sequence they are switched on separately to allow management of
// the VDD rise time. In the power down sequence they switch off
// simultaneously with the large power switches.
// This bit indicates the state of the last element in small power
// switch chain 2.
#define RP_AP_DBG_POW_STATE_SRAM0_SMALL_ACK2_RESET _u(0x0)
#define RP_AP_DBG_POW_STATE_SRAM0_SMALL_ACK2_BITS _u(0x00000008)
#define RP_AP_DBG_POW_STATE_SRAM0_SMALL_ACK2_MSB _u(3)
#define RP_AP_DBG_POW_STATE_SRAM0_SMALL_ACK2_LSB _u(3)
#define RP_AP_DBG_POW_STATE_SRAM0_SMALL_ACK2_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RP_AP_DBG_POW_STATE_SRAM0_SMALL_ACK1
// Description : This bit indicates the state of the last element in small power
// switch chain 1.
#define RP_AP_DBG_POW_STATE_SRAM0_SMALL_ACK1_RESET _u(0x0)
#define RP_AP_DBG_POW_STATE_SRAM0_SMALL_ACK1_BITS _u(0x00000004)
#define RP_AP_DBG_POW_STATE_SRAM0_SMALL_ACK1_MSB _u(2)
#define RP_AP_DBG_POW_STATE_SRAM0_SMALL_ACK1_LSB _u(2)
#define RP_AP_DBG_POW_STATE_SRAM0_SMALL_ACK1_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RP_AP_DBG_POW_STATE_SRAM0_SMALL_ACK0
// Description : This bit indicates the state of the last element in small power
// switch chain 0.
#define RP_AP_DBG_POW_STATE_SRAM0_SMALL_ACK0_RESET _u(0x0)
#define RP_AP_DBG_POW_STATE_SRAM0_SMALL_ACK0_BITS _u(0x00000002)
#define RP_AP_DBG_POW_STATE_SRAM0_SMALL_ACK0_MSB _u(1)
#define RP_AP_DBG_POW_STATE_SRAM0_SMALL_ACK0_LSB _u(1)
#define RP_AP_DBG_POW_STATE_SRAM0_SMALL_ACK0_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RP_AP_DBG_POW_STATE_SRAM0_IS_PD
// Description : Indicates the power somain is fully powered down.
#define RP_AP_DBG_POW_STATE_SRAM0_IS_PD_RESET _u(0x0)
#define RP_AP_DBG_POW_STATE_SRAM0_IS_PD_BITS _u(0x00000001)
#define RP_AP_DBG_POW_STATE_SRAM0_IS_PD_MSB _u(0)
#define RP_AP_DBG_POW_STATE_SRAM0_IS_PD_LSB _u(0)
#define RP_AP_DBG_POW_STATE_SRAM0_IS_PD_ACCESS "RO"
// =============================================================================
// Register : RP_AP_DBG_POW_STATE_SRAM1
// Description : This register indicates the state of the power sequencer for
// the SRAM1 domain.
// The sequencer timing is managed by the POWMAN_SEQ_* registers.
// See the header file for those registers for more information on
// the timing.
// Power up of the domain commences by clearing bit 0 (IS_PD) then
// bits 1-8 are set in sequence. Bit 8 (IS_PU) indicates the
// sequence is complete.
// Power down of the domain commences by clearing bit 8 (IS_PU)
// then bits 7-1 are cleared in sequence. Bit 0 (IS_PU) is then
// set to indicate the sequence is complete.
#define RP_AP_DBG_POW_STATE_SRAM1_OFFSET _u(0x00000014)
#define RP_AP_DBG_POW_STATE_SRAM1_BITS _u(0x000001ff)
#define RP_AP_DBG_POW_STATE_SRAM1_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : RP_AP_DBG_POW_STATE_SRAM1_IS_PU
// Description : Indicates the power somain is fully powered up.
#define RP_AP_DBG_POW_STATE_SRAM1_IS_PU_RESET _u(0x0)
#define RP_AP_DBG_POW_STATE_SRAM1_IS_PU_BITS _u(0x00000100)
#define RP_AP_DBG_POW_STATE_SRAM1_IS_PU_MSB _u(8)
#define RP_AP_DBG_POW_STATE_SRAM1_IS_PU_LSB _u(8)
#define RP_AP_DBG_POW_STATE_SRAM1_IS_PU_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RP_AP_DBG_POW_STATE_SRAM1_RESET_FROM_SEQ
// Description : Indicates the state of the reset to the power domain.
#define RP_AP_DBG_POW_STATE_SRAM1_RESET_FROM_SEQ_RESET _u(0x0)
#define RP_AP_DBG_POW_STATE_SRAM1_RESET_FROM_SEQ_BITS _u(0x00000080)
#define RP_AP_DBG_POW_STATE_SRAM1_RESET_FROM_SEQ_MSB _u(7)
#define RP_AP_DBG_POW_STATE_SRAM1_RESET_FROM_SEQ_LSB _u(7)
#define RP_AP_DBG_POW_STATE_SRAM1_RESET_FROM_SEQ_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RP_AP_DBG_POW_STATE_SRAM1_ENAB_ACK
// Description : Indicates the state of the enable to the power domain.
#define RP_AP_DBG_POW_STATE_SRAM1_ENAB_ACK_RESET _u(0x0)
#define RP_AP_DBG_POW_STATE_SRAM1_ENAB_ACK_BITS _u(0x00000040)
#define RP_AP_DBG_POW_STATE_SRAM1_ENAB_ACK_MSB _u(6)
#define RP_AP_DBG_POW_STATE_SRAM1_ENAB_ACK_LSB _u(6)
#define RP_AP_DBG_POW_STATE_SRAM1_ENAB_ACK_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RP_AP_DBG_POW_STATE_SRAM1_ISOLATE_FROM_SEQ
// Description : Indicates the state of the isolation control to the power
// domain.
#define RP_AP_DBG_POW_STATE_SRAM1_ISOLATE_FROM_SEQ_RESET _u(0x0)
#define RP_AP_DBG_POW_STATE_SRAM1_ISOLATE_FROM_SEQ_BITS _u(0x00000020)
#define RP_AP_DBG_POW_STATE_SRAM1_ISOLATE_FROM_SEQ_MSB _u(5)
#define RP_AP_DBG_POW_STATE_SRAM1_ISOLATE_FROM_SEQ_LSB _u(5)
#define RP_AP_DBG_POW_STATE_SRAM1_ISOLATE_FROM_SEQ_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RP_AP_DBG_POW_STATE_SRAM1_LARGE_ACK
// Description : Indicates the state of the large power switches for the power
// domain.
#define RP_AP_DBG_POW_STATE_SRAM1_LARGE_ACK_RESET _u(0x0)
#define RP_AP_DBG_POW_STATE_SRAM1_LARGE_ACK_BITS _u(0x00000010)
#define RP_AP_DBG_POW_STATE_SRAM1_LARGE_ACK_MSB _u(4)
#define RP_AP_DBG_POW_STATE_SRAM1_LARGE_ACK_LSB _u(4)
#define RP_AP_DBG_POW_STATE_SRAM1_LARGE_ACK_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RP_AP_DBG_POW_STATE_SRAM1_SMALL_ACK2
// Description : The small switches are split into 3 chains. In the power up
// sequence they are switched on separately to allow management of
// the VDD rise time. In the power down sequence they switch off
// simultaneously with the large power switches.
// This bit indicates the state of the last element in small power
// switch chain 2.
#define RP_AP_DBG_POW_STATE_SRAM1_SMALL_ACK2_RESET _u(0x0)
#define RP_AP_DBG_POW_STATE_SRAM1_SMALL_ACK2_BITS _u(0x00000008)
#define RP_AP_DBG_POW_STATE_SRAM1_SMALL_ACK2_MSB _u(3)
#define RP_AP_DBG_POW_STATE_SRAM1_SMALL_ACK2_LSB _u(3)
#define RP_AP_DBG_POW_STATE_SRAM1_SMALL_ACK2_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RP_AP_DBG_POW_STATE_SRAM1_SMALL_ACK1
// Description : This bit indicates the state of the last element in small power
// switch chain 1.
#define RP_AP_DBG_POW_STATE_SRAM1_SMALL_ACK1_RESET _u(0x0)
#define RP_AP_DBG_POW_STATE_SRAM1_SMALL_ACK1_BITS _u(0x00000004)
#define RP_AP_DBG_POW_STATE_SRAM1_SMALL_ACK1_MSB _u(2)
#define RP_AP_DBG_POW_STATE_SRAM1_SMALL_ACK1_LSB _u(2)
#define RP_AP_DBG_POW_STATE_SRAM1_SMALL_ACK1_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RP_AP_DBG_POW_STATE_SRAM1_SMALL_ACK0
// Description : This bit indicates the state of the last element in small power
// switch chain 0.
#define RP_AP_DBG_POW_STATE_SRAM1_SMALL_ACK0_RESET _u(0x0)
#define RP_AP_DBG_POW_STATE_SRAM1_SMALL_ACK0_BITS _u(0x00000002)
#define RP_AP_DBG_POW_STATE_SRAM1_SMALL_ACK0_MSB _u(1)
#define RP_AP_DBG_POW_STATE_SRAM1_SMALL_ACK0_LSB _u(1)
#define RP_AP_DBG_POW_STATE_SRAM1_SMALL_ACK0_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RP_AP_DBG_POW_STATE_SRAM1_IS_PD
// Description : Indicates the power somain is fully powered down.
#define RP_AP_DBG_POW_STATE_SRAM1_IS_PD_RESET _u(0x0)
#define RP_AP_DBG_POW_STATE_SRAM1_IS_PD_BITS _u(0x00000001)
#define RP_AP_DBG_POW_STATE_SRAM1_IS_PD_MSB _u(0)
#define RP_AP_DBG_POW_STATE_SRAM1_IS_PD_LSB _u(0)
#define RP_AP_DBG_POW_STATE_SRAM1_IS_PD_ACCESS "RO"
// =============================================================================
// Register : RP_AP_DBG_POW_OVRD
// Description : This register allows external control of the power sequencer
// outputs for all the switched power domains. If any of the power
// sequencers stall at any stage then force power up operation of
// all domains by running this sequence:
// - set DBG_POW_OVRD = 0x3b to force small power switches on,
// large power switches off, resets on and isolation on
// - allow time for the domain power supplies to reach full rail
// - set DBG_POW_OVRD = 0x3b to force large power switches on
// - set DBG_POW_OVRD = 0x37 to remove isolation
// - set DBG_POW_OVRD = 0x17 to remove resets
#define RP_AP_DBG_POW_OVRD_OFFSET _u(0x00000018)
#define RP_AP_DBG_POW_OVRD_BITS _u(0x0000007f)
#define RP_AP_DBG_POW_OVRD_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : RP_AP_DBG_POW_OVRD_DBG_POW_RESTART_FROM_XOSC
// Description : By default the system begins boot as soon as a clock is
// available from the ROSC, then it switches to the XOSC when it
// is available. This is done because the XOSC takes several ms to
// start up. If there is a problem with the ROSC then the default
// behaviour can be changed to not use the ROSC and wait for XOSC.
// However, this requires a mask change to modify the reset value
// of the Power Manager START_FROM_XOSC register. To allow
// experimentation the default can be temporarily changed by
// setting this register bit to 1. After setting this bit the core
// must be reset by a Coresight dprst or a rescue reset (see
// RESCUE_RESTART in the RP_AP_CTRL register above). A power-on
// reset, brown-out reset or RUN pin reset will reset this control
// and revert to the default behaviour.
#define RP_AP_DBG_POW_OVRD_DBG_POW_RESTART_FROM_XOSC_RESET _u(0x0)
#define RP_AP_DBG_POW_OVRD_DBG_POW_RESTART_FROM_XOSC_BITS _u(0x00000040)
#define RP_AP_DBG_POW_OVRD_DBG_POW_RESTART_FROM_XOSC_MSB _u(6)
#define RP_AP_DBG_POW_OVRD_DBG_POW_RESTART_FROM_XOSC_LSB _u(6)
#define RP_AP_DBG_POW_OVRD_DBG_POW_RESTART_FROM_XOSC_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RP_AP_DBG_POW_OVRD_DBG_POW_RESET
// Description : When DBG_POW_OVRD_RESET=1 this register bit controls the resets
// for all domains. 1 = reset. 0 = not reset.
#define RP_AP_DBG_POW_OVRD_DBG_POW_RESET_RESET _u(0x0)
#define RP_AP_DBG_POW_OVRD_DBG_POW_RESET_BITS _u(0x00000020)
#define RP_AP_DBG_POW_OVRD_DBG_POW_RESET_MSB _u(5)
#define RP_AP_DBG_POW_OVRD_DBG_POW_RESET_LSB _u(5)
#define RP_AP_DBG_POW_OVRD_DBG_POW_RESET_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_RESET
// Description : Enables DBG_POW_RESET to control the resets for the power
// manager and the switched-core. Essentially that is everythjing
// except the Coresight 2-wire interface and the RP_AP registers.
#define RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_RESET_RESET _u(0x0)
#define RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_RESET_BITS _u(0x00000010)
#define RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_RESET_MSB _u(4)
#define RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_RESET_LSB _u(4)
#define RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_RESET_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RP_AP_DBG_POW_OVRD_DBG_POW_ISO
// Description : When DBG_POW_OVRD_ISO=1 this register bit controls the
// isolation gates for all domains. 1 = isolated. 0 = not
// isolated.
#define RP_AP_DBG_POW_OVRD_DBG_POW_ISO_RESET _u(0x0)
#define RP_AP_DBG_POW_OVRD_DBG_POW_ISO_BITS _u(0x00000008)
#define RP_AP_DBG_POW_OVRD_DBG_POW_ISO_MSB _u(3)
#define RP_AP_DBG_POW_OVRD_DBG_POW_ISO_LSB _u(3)
#define RP_AP_DBG_POW_OVRD_DBG_POW_ISO_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_ISO
// Description : Enables DBG_POW_ISO to control the isolation gates between
// domains.
#define RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_ISO_RESET _u(0x0)
#define RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_ISO_BITS _u(0x00000004)
#define RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_ISO_MSB _u(2)
#define RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_ISO_LSB _u(2)
#define RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_ISO_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_LARGE_REQ
// Description : Turn on the large power switches for all domains. This should
// not be done until sufficient time has been allowed for the
// small switches to bring the supplies up. Switching the large
// switches on too soon risks browning out the always-on domain
// and corrupting these very registers.
#define RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_LARGE_REQ_RESET _u(0x0)
#define RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_LARGE_REQ_BITS _u(0x00000002)
#define RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_LARGE_REQ_MSB _u(1)
#define RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_LARGE_REQ_LSB _u(1)
#define RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_LARGE_REQ_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_SMALL_REQ
// Description : Turn on the small power switches for all domains. This switches
// on chain 0 for each domain and switches off chains 2 & 3 and
// the large power switch chain. This will bring the power up for
// all domains without browning out the always-on power domain.
#define RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_SMALL_REQ_RESET _u(0x0)
#define RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_SMALL_REQ_BITS _u(0x00000001)
#define RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_SMALL_REQ_MSB _u(0)
#define RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_SMALL_REQ_LSB _u(0)
#define RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_SMALL_REQ_ACCESS "RW"
// =============================================================================
// Register : RP_AP_DBG_POW_OUTPUT_TO_GPIO
// Description : Send some, or all, bits of DBG_POW_STATE_SWCORE to gpios.
// Bit 0 sends bit 0 of DBG_POW_STATE_SWCORE to GPIO 34
// Bit 1 sends bit 1 of DBG_POW_STATE_SWCORE to GPIO 35
// Bit 2 sends bit 2 of DBG_POW_STATE_SWCORE to GPIO 36
// .
// .
// Bit 11 sends bit 11 of DBG_POW_STATE_SWCORE to GPIO 45
#define RP_AP_DBG_POW_OUTPUT_TO_GPIO_OFFSET _u(0x0000001c)
#define RP_AP_DBG_POW_OUTPUT_TO_GPIO_BITS _u(0x00000fff)
#define RP_AP_DBG_POW_OUTPUT_TO_GPIO_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : RP_AP_DBG_POW_OUTPUT_TO_GPIO_ENABLE
#define RP_AP_DBG_POW_OUTPUT_TO_GPIO_ENABLE_RESET _u(0x000)
#define RP_AP_DBG_POW_OUTPUT_TO_GPIO_ENABLE_BITS _u(0x00000fff)
#define RP_AP_DBG_POW_OUTPUT_TO_GPIO_ENABLE_MSB _u(11)
#define RP_AP_DBG_POW_OUTPUT_TO_GPIO_ENABLE_LSB _u(0)
#define RP_AP_DBG_POW_OUTPUT_TO_GPIO_ENABLE_ACCESS "RW"
// =============================================================================
// Register : RP_AP_IDR
// Description : Standard Coresight ID Register
#define RP_AP_IDR_OFFSET _u(0x00000dfc)
#define RP_AP_IDR_BITS _u(0xffffffff)
#define RP_AP_IDR_RESET "-"
#define RP_AP_IDR_MSB _u(31)
#define RP_AP_IDR_LSB _u(0)
#define RP_AP_IDR_ACCESS "RO"
// =============================================================================
#endif // _HARDWARE_REGS_RP_AP_H

3154
arch/arm/src/rp23xx/hardware/regs/rvcsr.h
View file

File diff suppressed because it is too large Load diff

228
arch/arm/src/rp23xx/hardware/regs/sha256.h
View file

@ -1,228 +0,0 @@
// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
// =============================================================================
// Register block : SHA256
// Version : 1
// Bus type : apb
// Description : SHA-256 hash function implementation
// =============================================================================
#ifndef _HARDWARE_REGS_SHA256_H
#define _HARDWARE_REGS_SHA256_H
// =============================================================================
// Register : SHA256_CSR
// Description : Control and status register
#define SHA256_CSR_OFFSET _u(0x00000000)
#define SHA256_CSR_BITS _u(0x00001317)
#define SHA256_CSR_RESET _u(0x00001206)
// -----------------------------------------------------------------------------
// Field : SHA256_CSR_BSWAP
// Description : Enable byte swapping of 32-bit values at the point they are
// committed to the SHA message scheduler.
//
// This block's bus interface assembles byte/halfword data into
// message words in little-endian order, so that DMAing the same
// buffer with different transfer sizes always gives the same
// result on a little-endian system like RP2350.
//
// However, when marshalling bytes into blocks, SHA expects that
// the first byte is the *most significant* in each message word.
// To resolve this, once the bus interface has accumulated 32 bits
// of data (either a word write, two halfword writes in little-
// endian order, or four byte writes in little-endian order) the
// final value can be byte-swapped before passing to the actual
// SHA core.
//
// This feature is enabled by default because using the SHA core
// to checksum byte buffers is expected to be more common than
// having preformatted SHA message words lying around.
#define SHA256_CSR_BSWAP_RESET _u(0x1)
#define SHA256_CSR_BSWAP_BITS _u(0x00001000)
#define SHA256_CSR_BSWAP_MSB _u(12)
#define SHA256_CSR_BSWAP_LSB _u(12)
#define SHA256_CSR_BSWAP_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SHA256_CSR_DMA_SIZE
// Description : Configure DREQ logic for the correct DMA data size. Must be
// configured before the DMA channel is triggered.
//
// The SHA-256 core's DREQ logic requests one entire block of data
// at once, since there is no FIFO, and data goes straight into
// the core's message schedule and digest hardware. Therefore,
// when transferring data with DMA, CSR_DMA_SIZE must be
// configured in advance so that the correct number of transfers
// can be requested per block.
// 0x0 -> 8bit
// 0x1 -> 16bit
// 0x2 -> 32bit
#define SHA256_CSR_DMA_SIZE_RESET _u(0x2)
#define SHA256_CSR_DMA_SIZE_BITS _u(0x00000300)
#define SHA256_CSR_DMA_SIZE_MSB _u(9)
#define SHA256_CSR_DMA_SIZE_LSB _u(8)
#define SHA256_CSR_DMA_SIZE_ACCESS "RW"
#define SHA256_CSR_DMA_SIZE_VALUE_8BIT _u(0x0)
#define SHA256_CSR_DMA_SIZE_VALUE_16BIT _u(0x1)
#define SHA256_CSR_DMA_SIZE_VALUE_32BIT _u(0x2)
// -----------------------------------------------------------------------------
// Field : SHA256_CSR_ERR_WDATA_NOT_RDY
// Description : Set when a write occurs whilst the SHA-256 core is not ready
// for data (WDATA_RDY is low). Write one to clear.
#define SHA256_CSR_ERR_WDATA_NOT_RDY_RESET _u(0x0)
#define SHA256_CSR_ERR_WDATA_NOT_RDY_BITS _u(0x00000010)
#define SHA256_CSR_ERR_WDATA_NOT_RDY_MSB _u(4)
#define SHA256_CSR_ERR_WDATA_NOT_RDY_LSB _u(4)
#define SHA256_CSR_ERR_WDATA_NOT_RDY_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : SHA256_CSR_SUM_VLD
// Description : If 1, the SHA-256 checksum presented in registers SUM0 through
// SUM7 is currently valid.
//
// Goes low when WDATA is first written, then returns high once 16
// words have been written and the digest of the current 512-bit
// block has subsequently completed.
#define SHA256_CSR_SUM_VLD_RESET _u(0x1)
#define SHA256_CSR_SUM_VLD_BITS _u(0x00000004)
#define SHA256_CSR_SUM_VLD_MSB _u(2)
#define SHA256_CSR_SUM_VLD_LSB _u(2)
#define SHA256_CSR_SUM_VLD_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : SHA256_CSR_WDATA_RDY
// Description : If 1, the SHA-256 core is ready to accept more data through the
// WDATA register.
//
// After writing 16 words, this flag will go low for 57 cycles
// whilst the core completes its digest.
#define SHA256_CSR_WDATA_RDY_RESET _u(0x1)
#define SHA256_CSR_WDATA_RDY_BITS _u(0x00000002)
#define SHA256_CSR_WDATA_RDY_MSB _u(1)
#define SHA256_CSR_WDATA_RDY_LSB _u(1)
#define SHA256_CSR_WDATA_RDY_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : SHA256_CSR_START
// Description : Write 1 to prepare the SHA-256 core for a new checksum.
//
// The SUMx registers are initialised to the proper values
// (fractional bits of square roots of first 8 primes) and
// internal counters are cleared. This immediately forces
// WDATA_RDY and SUM_VLD high.
//
// START must be written before initiating a DMA transfer to the
// SHA-256 core, because the core will always request 16 transfers
// at a time (1 512-bit block). Additionally, the DMA channel
// should be configured for a multiple of 16 32-bit transfers.
#define SHA256_CSR_START_RESET _u(0x0)
#define SHA256_CSR_START_BITS _u(0x00000001)
#define SHA256_CSR_START_MSB _u(0)
#define SHA256_CSR_START_LSB _u(0)
#define SHA256_CSR_START_ACCESS "SC"
// =============================================================================
// Register : SHA256_WDATA
// Description : Write data register
// After pulsing START and writing 16 words of data to this
// register, WDATA_RDY will go low and the SHA-256 core will
// complete the digest of the current 512-bit block.
//
// Software is responsible for ensuring the data is correctly
// padded and terminated to a whole number of 512-bit blocks.
//
// After this, WDATA_RDY will return high, and more data can be
// written (if any).
//
// This register supports word, halfword and byte writes, so that
// DMA from non-word-aligned buffers can be supported. The total
// amount of data per block remains the same (16 words, 32
// halfwords or 64 bytes) and byte/halfword transfers must not be
// mixed within a block.
#define SHA256_WDATA_OFFSET _u(0x00000004)
#define SHA256_WDATA_BITS _u(0xffffffff)
#define SHA256_WDATA_RESET _u(0x00000000)
#define SHA256_WDATA_MSB _u(31)
#define SHA256_WDATA_LSB _u(0)
#define SHA256_WDATA_ACCESS "WF"
// =============================================================================
// Register : SHA256_SUM0
// Description : 256-bit checksum result. Contents are undefined when
// CSR_SUM_VLD is 0.
#define SHA256_SUM0_OFFSET _u(0x00000008)
#define SHA256_SUM0_BITS _u(0xffffffff)
#define SHA256_SUM0_RESET _u(0x00000000)
#define SHA256_SUM0_MSB _u(31)
#define SHA256_SUM0_LSB _u(0)
#define SHA256_SUM0_ACCESS "RO"
// =============================================================================
// Register : SHA256_SUM1
// Description : 256-bit checksum result. Contents are undefined when
// CSR_SUM_VLD is 0.
#define SHA256_SUM1_OFFSET _u(0x0000000c)
#define SHA256_SUM1_BITS _u(0xffffffff)
#define SHA256_SUM1_RESET _u(0x00000000)
#define SHA256_SUM1_MSB _u(31)
#define SHA256_SUM1_LSB _u(0)
#define SHA256_SUM1_ACCESS "RO"
// =============================================================================
// Register : SHA256_SUM2
// Description : 256-bit checksum result. Contents are undefined when
// CSR_SUM_VLD is 0.
#define SHA256_SUM2_OFFSET _u(0x00000010)
#define SHA256_SUM2_BITS _u(0xffffffff)
#define SHA256_SUM2_RESET _u(0x00000000)
#define SHA256_SUM2_MSB _u(31)
#define SHA256_SUM2_LSB _u(0)
#define SHA256_SUM2_ACCESS "RO"
// =============================================================================
// Register : SHA256_SUM3
// Description : 256-bit checksum result. Contents are undefined when
// CSR_SUM_VLD is 0.
#define SHA256_SUM3_OFFSET _u(0x00000014)
#define SHA256_SUM3_BITS _u(0xffffffff)
#define SHA256_SUM3_RESET _u(0x00000000)
#define SHA256_SUM3_MSB _u(31)
#define SHA256_SUM3_LSB _u(0)
#define SHA256_SUM3_ACCESS "RO"
// =============================================================================
// Register : SHA256_SUM4
// Description : 256-bit checksum result. Contents are undefined when
// CSR_SUM_VLD is 0.
#define SHA256_SUM4_OFFSET _u(0x00000018)
#define SHA256_SUM4_BITS _u(0xffffffff)
#define SHA256_SUM4_RESET _u(0x00000000)
#define SHA256_SUM4_MSB _u(31)
#define SHA256_SUM4_LSB _u(0)
#define SHA256_SUM4_ACCESS "RO"
// =============================================================================
// Register : SHA256_SUM5
// Description : 256-bit checksum result. Contents are undefined when
// CSR_SUM_VLD is 0.
#define SHA256_SUM5_OFFSET _u(0x0000001c)
#define SHA256_SUM5_BITS _u(0xffffffff)
#define SHA256_SUM5_RESET _u(0x00000000)
#define SHA256_SUM5_MSB _u(31)
#define SHA256_SUM5_LSB _u(0)
#define SHA256_SUM5_ACCESS "RO"
// =============================================================================
// Register : SHA256_SUM6
// Description : 256-bit checksum result. Contents are undefined when
// CSR_SUM_VLD is 0.
#define SHA256_SUM6_OFFSET _u(0x00000020)
#define SHA256_SUM6_BITS _u(0xffffffff)
#define SHA256_SUM6_RESET _u(0x00000000)
#define SHA256_SUM6_MSB _u(31)
#define SHA256_SUM6_LSB _u(0)
#define SHA256_SUM6_ACCESS "RO"
// =============================================================================
// Register : SHA256_SUM7
// Description : 256-bit checksum result. Contents are undefined when
// CSR_SUM_VLD is 0.
#define SHA256_SUM7_OFFSET _u(0x00000024)
#define SHA256_SUM7_BITS _u(0xffffffff)
#define SHA256_SUM7_RESET _u(0x00000000)
#define SHA256_SUM7_MSB _u(31)
#define SHA256_SUM7_LSB _u(0)
#define SHA256_SUM7_ACCESS "RO"
// =============================================================================
#endif // _HARDWARE_REGS_SHA256_H

2461
arch/arm/src/rp23xx/hardware/regs/sio.h
View file

File diff suppressed because it is too large Load diff

523
arch/arm/src/rp23xx/hardware/regs/spi.h
View file

@ -1,523 +0,0 @@
// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
// =============================================================================
// Register block : SPI
// Version : 1
// Bus type : apb
// =============================================================================
#ifndef _HARDWARE_REGS_SPI_H
#define _HARDWARE_REGS_SPI_H
// =============================================================================
// Register : SPI_SSPCR0
// Description : Control register 0, SSPCR0 on page 3-4
#define SPI_SSPCR0_OFFSET _u(0x00000000)
#define SPI_SSPCR0_BITS _u(0x0000ffff)
#define SPI_SSPCR0_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : SPI_SSPCR0_SCR
// Description : Serial clock rate. The value SCR is used to generate the
// transmit and receive bit rate of the PrimeCell SSP. The bit
// rate is: F SSPCLK CPSDVSR x (1+SCR) where CPSDVSR is an even
// value from 2-254, programmed through the SSPCPSR register and
// SCR is a value from 0-255.
#define SPI_SSPCR0_SCR_RESET _u(0x00)
#define SPI_SSPCR0_SCR_BITS _u(0x0000ff00)
#define SPI_SSPCR0_SCR_MSB _u(15)
#define SPI_SSPCR0_SCR_LSB _u(8)
#define SPI_SSPCR0_SCR_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SPI_SSPCR0_SPH
// Description : SSPCLKOUT phase, applicable to Motorola SPI frame format only.
// See Motorola SPI frame format on page 2-10.
#define SPI_SSPCR0_SPH_RESET _u(0x0)
#define SPI_SSPCR0_SPH_BITS _u(0x00000080)
#define SPI_SSPCR0_SPH_MSB _u(7)
#define SPI_SSPCR0_SPH_LSB _u(7)
#define SPI_SSPCR0_SPH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SPI_SSPCR0_SPO
// Description : SSPCLKOUT polarity, applicable to Motorola SPI frame format
// only. See Motorola SPI frame format on page 2-10.
#define SPI_SSPCR0_SPO_RESET _u(0x0)
#define SPI_SSPCR0_SPO_BITS _u(0x00000040)
#define SPI_SSPCR0_SPO_MSB _u(6)
#define SPI_SSPCR0_SPO_LSB _u(6)
#define SPI_SSPCR0_SPO_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SPI_SSPCR0_FRF
// Description : Frame format: 00 Motorola SPI frame format. 01 TI synchronous
// serial frame format. 10 National Microwire frame format. 11
// Reserved, undefined operation.
#define SPI_SSPCR0_FRF_RESET _u(0x0)
#define SPI_SSPCR0_FRF_BITS _u(0x00000030)
#define SPI_SSPCR0_FRF_MSB _u(5)
#define SPI_SSPCR0_FRF_LSB _u(4)
#define SPI_SSPCR0_FRF_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SPI_SSPCR0_DSS
// Description : Data Size Select: 0000 Reserved, undefined operation. 0001
// Reserved, undefined operation. 0010 Reserved, undefined
// operation. 0011 4-bit data. 0100 5-bit data. 0101 6-bit data.
// 0110 7-bit data. 0111 8-bit data. 1000 9-bit data. 1001 10-bit
// data. 1010 11-bit data. 1011 12-bit data. 1100 13-bit data.
// 1101 14-bit data. 1110 15-bit data. 1111 16-bit data.
#define SPI_SSPCR0_DSS_RESET _u(0x0)
#define SPI_SSPCR0_DSS_BITS _u(0x0000000f)
#define SPI_SSPCR0_DSS_MSB _u(3)
#define SPI_SSPCR0_DSS_LSB _u(0)
#define SPI_SSPCR0_DSS_ACCESS "RW"
// =============================================================================
// Register : SPI_SSPCR1
// Description : Control register 1, SSPCR1 on page 3-5
#define SPI_SSPCR1_OFFSET _u(0x00000004)
#define SPI_SSPCR1_BITS _u(0x0000000f)
#define SPI_SSPCR1_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : SPI_SSPCR1_SOD
// Description : Slave-mode output disable. This bit is relevant only in the
// slave mode, MS=1. In multiple-slave systems, it is possible for
// an PrimeCell SSP master to broadcast a message to all slaves in
// the system while ensuring that only one slave drives data onto
// its serial output line. In such systems the RXD lines from
// multiple slaves could be tied together. To operate in such
// systems, the SOD bit can be set if the PrimeCell SSP slave is
// not supposed to drive the SSPTXD line: 0 SSP can drive the
// SSPTXD output in slave mode. 1 SSP must not drive the SSPTXD
// output in slave mode.
#define SPI_SSPCR1_SOD_RESET _u(0x0)
#define SPI_SSPCR1_SOD_BITS _u(0x00000008)
#define SPI_SSPCR1_SOD_MSB _u(3)
#define SPI_SSPCR1_SOD_LSB _u(3)
#define SPI_SSPCR1_SOD_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SPI_SSPCR1_MS
// Description : Master or slave mode select. This bit can be modified only when
// the PrimeCell SSP is disabled, SSE=0: 0 Device configured as
// master, default. 1 Device configured as slave.
#define SPI_SSPCR1_MS_RESET _u(0x0)
#define SPI_SSPCR1_MS_BITS _u(0x00000004)
#define SPI_SSPCR1_MS_MSB _u(2)
#define SPI_SSPCR1_MS_LSB _u(2)
#define SPI_SSPCR1_MS_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SPI_SSPCR1_SSE
// Description : Synchronous serial port enable: 0 SSP operation disabled. 1 SSP
// operation enabled.
#define SPI_SSPCR1_SSE_RESET _u(0x0)
#define SPI_SSPCR1_SSE_BITS _u(0x00000002)
#define SPI_SSPCR1_SSE_MSB _u(1)
#define SPI_SSPCR1_SSE_LSB _u(1)
#define SPI_SSPCR1_SSE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SPI_SSPCR1_LBM
// Description : Loop back mode: 0 Normal serial port operation enabled. 1
// Output of transmit serial shifter is connected to input of
// receive serial shifter internally.
#define SPI_SSPCR1_LBM_RESET _u(0x0)
#define SPI_SSPCR1_LBM_BITS _u(0x00000001)
#define SPI_SSPCR1_LBM_MSB _u(0)
#define SPI_SSPCR1_LBM_LSB _u(0)
#define SPI_SSPCR1_LBM_ACCESS "RW"
// =============================================================================
// Register : SPI_SSPDR
// Description : Data register, SSPDR on page 3-6
#define SPI_SSPDR_OFFSET _u(0x00000008)
#define SPI_SSPDR_BITS _u(0x0000ffff)
#define SPI_SSPDR_RESET "-"
// -----------------------------------------------------------------------------
// Field : SPI_SSPDR_DATA
// Description : Transmit/Receive FIFO: Read Receive FIFO. Write Transmit FIFO.
// You must right-justify data when the PrimeCell SSP is
// programmed for a data size that is less than 16 bits. Unused
// bits at the top are ignored by transmit logic. The receive
// logic automatically right-justifies.
#define SPI_SSPDR_DATA_RESET "-"
#define SPI_SSPDR_DATA_BITS _u(0x0000ffff)
#define SPI_SSPDR_DATA_MSB _u(15)
#define SPI_SSPDR_DATA_LSB _u(0)
#define SPI_SSPDR_DATA_ACCESS "RWF"
// =============================================================================
// Register : SPI_SSPSR
// Description : Status register, SSPSR on page 3-7
#define SPI_SSPSR_OFFSET _u(0x0000000c)
#define SPI_SSPSR_BITS _u(0x0000001f)
#define SPI_SSPSR_RESET _u(0x00000003)
// -----------------------------------------------------------------------------
// Field : SPI_SSPSR_BSY
// Description : PrimeCell SSP busy flag, RO: 0 SSP is idle. 1 SSP is currently
// transmitting and/or receiving a frame or the transmit FIFO is
// not empty.
#define SPI_SSPSR_BSY_RESET _u(0x0)
#define SPI_SSPSR_BSY_BITS _u(0x00000010)
#define SPI_SSPSR_BSY_MSB _u(4)
#define SPI_SSPSR_BSY_LSB _u(4)
#define SPI_SSPSR_BSY_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : SPI_SSPSR_RFF
// Description : Receive FIFO full, RO: 0 Receive FIFO is not full. 1 Receive
// FIFO is full.
#define SPI_SSPSR_RFF_RESET _u(0x0)
#define SPI_SSPSR_RFF_BITS _u(0x00000008)
#define SPI_SSPSR_RFF_MSB _u(3)
#define SPI_SSPSR_RFF_LSB _u(3)
#define SPI_SSPSR_RFF_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : SPI_SSPSR_RNE
// Description : Receive FIFO not empty, RO: 0 Receive FIFO is empty. 1 Receive
// FIFO is not empty.
#define SPI_SSPSR_RNE_RESET _u(0x0)
#define SPI_SSPSR_RNE_BITS _u(0x00000004)
#define SPI_SSPSR_RNE_MSB _u(2)
#define SPI_SSPSR_RNE_LSB _u(2)
#define SPI_SSPSR_RNE_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : SPI_SSPSR_TNF
// Description : Transmit FIFO not full, RO: 0 Transmit FIFO is full. 1 Transmit
// FIFO is not full.
#define SPI_SSPSR_TNF_RESET _u(0x1)
#define SPI_SSPSR_TNF_BITS _u(0x00000002)
#define SPI_SSPSR_TNF_MSB _u(1)
#define SPI_SSPSR_TNF_LSB _u(1)
#define SPI_SSPSR_TNF_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : SPI_SSPSR_TFE
// Description : Transmit FIFO empty, RO: 0 Transmit FIFO is not empty. 1
// Transmit FIFO is empty.
#define SPI_SSPSR_TFE_RESET _u(0x1)
#define SPI_SSPSR_TFE_BITS _u(0x00000001)
#define SPI_SSPSR_TFE_MSB _u(0)
#define SPI_SSPSR_TFE_LSB _u(0)
#define SPI_SSPSR_TFE_ACCESS "RO"
// =============================================================================
// Register : SPI_SSPCPSR
// Description : Clock prescale register, SSPCPSR on page 3-8
#define SPI_SSPCPSR_OFFSET _u(0x00000010)
#define SPI_SSPCPSR_BITS _u(0x000000ff)
#define SPI_SSPCPSR_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : SPI_SSPCPSR_CPSDVSR
// Description : Clock prescale divisor. Must be an even number from 2-254,
// depending on the frequency of SSPCLK. The least significant bit
// always returns zero on reads.
#define SPI_SSPCPSR_CPSDVSR_RESET _u(0x00)
#define SPI_SSPCPSR_CPSDVSR_BITS _u(0x000000ff)
#define SPI_SSPCPSR_CPSDVSR_MSB _u(7)
#define SPI_SSPCPSR_CPSDVSR_LSB _u(0)
#define SPI_SSPCPSR_CPSDVSR_ACCESS "RW"
// =============================================================================
// Register : SPI_SSPIMSC
// Description : Interrupt mask set or clear register, SSPIMSC on page 3-9
#define SPI_SSPIMSC_OFFSET _u(0x00000014)
#define SPI_SSPIMSC_BITS _u(0x0000000f)
#define SPI_SSPIMSC_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : SPI_SSPIMSC_TXIM
// Description : Transmit FIFO interrupt mask: 0 Transmit FIFO half empty or
// less condition interrupt is masked. 1 Transmit FIFO half empty
// or less condition interrupt is not masked.
#define SPI_SSPIMSC_TXIM_RESET _u(0x0)
#define SPI_SSPIMSC_TXIM_BITS _u(0x00000008)
#define SPI_SSPIMSC_TXIM_MSB _u(3)
#define SPI_SSPIMSC_TXIM_LSB _u(3)
#define SPI_SSPIMSC_TXIM_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SPI_SSPIMSC_RXIM
// Description : Receive FIFO interrupt mask: 0 Receive FIFO half full or less
// condition interrupt is masked. 1 Receive FIFO half full or less
// condition interrupt is not masked.
#define SPI_SSPIMSC_RXIM_RESET _u(0x0)
#define SPI_SSPIMSC_RXIM_BITS _u(0x00000004)
#define SPI_SSPIMSC_RXIM_MSB _u(2)
#define SPI_SSPIMSC_RXIM_LSB _u(2)
#define SPI_SSPIMSC_RXIM_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SPI_SSPIMSC_RTIM
// Description : Receive timeout interrupt mask: 0 Receive FIFO not empty and no
// read prior to timeout period interrupt is masked. 1 Receive
// FIFO not empty and no read prior to timeout period interrupt is
// not masked.
#define SPI_SSPIMSC_RTIM_RESET _u(0x0)
#define SPI_SSPIMSC_RTIM_BITS _u(0x00000002)
#define SPI_SSPIMSC_RTIM_MSB _u(1)
#define SPI_SSPIMSC_RTIM_LSB _u(1)
#define SPI_SSPIMSC_RTIM_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SPI_SSPIMSC_RORIM
// Description : Receive overrun interrupt mask: 0 Receive FIFO written to while
// full condition interrupt is masked. 1 Receive FIFO written to
// while full condition interrupt is not masked.
#define SPI_SSPIMSC_RORIM_RESET _u(0x0)
#define SPI_SSPIMSC_RORIM_BITS _u(0x00000001)
#define SPI_SSPIMSC_RORIM_MSB _u(0)
#define SPI_SSPIMSC_RORIM_LSB _u(0)
#define SPI_SSPIMSC_RORIM_ACCESS "RW"
// =============================================================================
// Register : SPI_SSPRIS
// Description : Raw interrupt status register, SSPRIS on page 3-10
#define SPI_SSPRIS_OFFSET _u(0x00000018)
#define SPI_SSPRIS_BITS _u(0x0000000f)
#define SPI_SSPRIS_RESET _u(0x00000008)
// -----------------------------------------------------------------------------
// Field : SPI_SSPRIS_TXRIS
// Description : Gives the raw interrupt state, prior to masking, of the
// SSPTXINTR interrupt
#define SPI_SSPRIS_TXRIS_RESET _u(0x1)
#define SPI_SSPRIS_TXRIS_BITS _u(0x00000008)
#define SPI_SSPRIS_TXRIS_MSB _u(3)
#define SPI_SSPRIS_TXRIS_LSB _u(3)
#define SPI_SSPRIS_TXRIS_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : SPI_SSPRIS_RXRIS
// Description : Gives the raw interrupt state, prior to masking, of the
// SSPRXINTR interrupt
#define SPI_SSPRIS_RXRIS_RESET _u(0x0)
#define SPI_SSPRIS_RXRIS_BITS _u(0x00000004)
#define SPI_SSPRIS_RXRIS_MSB _u(2)
#define SPI_SSPRIS_RXRIS_LSB _u(2)
#define SPI_SSPRIS_RXRIS_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : SPI_SSPRIS_RTRIS
// Description : Gives the raw interrupt state, prior to masking, of the
// SSPRTINTR interrupt
#define SPI_SSPRIS_RTRIS_RESET _u(0x0)
#define SPI_SSPRIS_RTRIS_BITS _u(0x00000002)
#define SPI_SSPRIS_RTRIS_MSB _u(1)
#define SPI_SSPRIS_RTRIS_LSB _u(1)
#define SPI_SSPRIS_RTRIS_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : SPI_SSPRIS_RORRIS
// Description : Gives the raw interrupt state, prior to masking, of the
// SSPRORINTR interrupt
#define SPI_SSPRIS_RORRIS_RESET _u(0x0)
#define SPI_SSPRIS_RORRIS_BITS _u(0x00000001)
#define SPI_SSPRIS_RORRIS_MSB _u(0)
#define SPI_SSPRIS_RORRIS_LSB _u(0)
#define SPI_SSPRIS_RORRIS_ACCESS "RO"
// =============================================================================
// Register : SPI_SSPMIS
// Description : Masked interrupt status register, SSPMIS on page 3-11
#define SPI_SSPMIS_OFFSET _u(0x0000001c)
#define SPI_SSPMIS_BITS _u(0x0000000f)
#define SPI_SSPMIS_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : SPI_SSPMIS_TXMIS
// Description : Gives the transmit FIFO masked interrupt state, after masking,
// of the SSPTXINTR interrupt
#define SPI_SSPMIS_TXMIS_RESET _u(0x0)
#define SPI_SSPMIS_TXMIS_BITS _u(0x00000008)
#define SPI_SSPMIS_TXMIS_MSB _u(3)
#define SPI_SSPMIS_TXMIS_LSB _u(3)
#define SPI_SSPMIS_TXMIS_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : SPI_SSPMIS_RXMIS
// Description : Gives the receive FIFO masked interrupt state, after masking,
// of the SSPRXINTR interrupt
#define SPI_SSPMIS_RXMIS_RESET _u(0x0)
#define SPI_SSPMIS_RXMIS_BITS _u(0x00000004)
#define SPI_SSPMIS_RXMIS_MSB _u(2)
#define SPI_SSPMIS_RXMIS_LSB _u(2)
#define SPI_SSPMIS_RXMIS_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : SPI_SSPMIS_RTMIS
// Description : Gives the receive timeout masked interrupt state, after
// masking, of the SSPRTINTR interrupt
#define SPI_SSPMIS_RTMIS_RESET _u(0x0)
#define SPI_SSPMIS_RTMIS_BITS _u(0x00000002)
#define SPI_SSPMIS_RTMIS_MSB _u(1)
#define SPI_SSPMIS_RTMIS_LSB _u(1)
#define SPI_SSPMIS_RTMIS_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : SPI_SSPMIS_RORMIS
// Description : Gives the receive over run masked interrupt status, after
// masking, of the SSPRORINTR interrupt
#define SPI_SSPMIS_RORMIS_RESET _u(0x0)
#define SPI_SSPMIS_RORMIS_BITS _u(0x00000001)
#define SPI_SSPMIS_RORMIS_MSB _u(0)
#define SPI_SSPMIS_RORMIS_LSB _u(0)
#define SPI_SSPMIS_RORMIS_ACCESS "RO"
// =============================================================================
// Register : SPI_SSPICR
// Description : Interrupt clear register, SSPICR on page 3-11
#define SPI_SSPICR_OFFSET _u(0x00000020)
#define SPI_SSPICR_BITS _u(0x00000003)
#define SPI_SSPICR_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : SPI_SSPICR_RTIC
// Description : Clears the SSPRTINTR interrupt
#define SPI_SSPICR_RTIC_RESET _u(0x0)
#define SPI_SSPICR_RTIC_BITS _u(0x00000002)
#define SPI_SSPICR_RTIC_MSB _u(1)
#define SPI_SSPICR_RTIC_LSB _u(1)
#define SPI_SSPICR_RTIC_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : SPI_SSPICR_RORIC
// Description : Clears the SSPRORINTR interrupt
#define SPI_SSPICR_RORIC_RESET _u(0x0)
#define SPI_SSPICR_RORIC_BITS _u(0x00000001)
#define SPI_SSPICR_RORIC_MSB _u(0)
#define SPI_SSPICR_RORIC_LSB _u(0)
#define SPI_SSPICR_RORIC_ACCESS "WC"
// =============================================================================
// Register : SPI_SSPDMACR
// Description : DMA control register, SSPDMACR on page 3-12
#define SPI_SSPDMACR_OFFSET _u(0x00000024)
#define SPI_SSPDMACR_BITS _u(0x00000003)
#define SPI_SSPDMACR_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : SPI_SSPDMACR_TXDMAE
// Description : Transmit DMA Enable. If this bit is set to 1, DMA for the
// transmit FIFO is enabled.
#define SPI_SSPDMACR_TXDMAE_RESET _u(0x0)
#define SPI_SSPDMACR_TXDMAE_BITS _u(0x00000002)
#define SPI_SSPDMACR_TXDMAE_MSB _u(1)
#define SPI_SSPDMACR_TXDMAE_LSB _u(1)
#define SPI_SSPDMACR_TXDMAE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SPI_SSPDMACR_RXDMAE
// Description : Receive DMA Enable. If this bit is set to 1, DMA for the
// receive FIFO is enabled.
#define SPI_SSPDMACR_RXDMAE_RESET _u(0x0)
#define SPI_SSPDMACR_RXDMAE_BITS _u(0x00000001)
#define SPI_SSPDMACR_RXDMAE_MSB _u(0)
#define SPI_SSPDMACR_RXDMAE_LSB _u(0)
#define SPI_SSPDMACR_RXDMAE_ACCESS "RW"
// =============================================================================
// Register : SPI_SSPPERIPHID0
// Description : Peripheral identification registers, SSPPeriphID0-3 on page
// 3-13
#define SPI_SSPPERIPHID0_OFFSET _u(0x00000fe0)
#define SPI_SSPPERIPHID0_BITS _u(0x000000ff)
#define SPI_SSPPERIPHID0_RESET _u(0x00000022)
// -----------------------------------------------------------------------------
// Field : SPI_SSPPERIPHID0_PARTNUMBER0
// Description : These bits read back as 0x22
#define SPI_SSPPERIPHID0_PARTNUMBER0_RESET _u(0x22)
#define SPI_SSPPERIPHID0_PARTNUMBER0_BITS _u(0x000000ff)
#define SPI_SSPPERIPHID0_PARTNUMBER0_MSB _u(7)
#define SPI_SSPPERIPHID0_PARTNUMBER0_LSB _u(0)
#define SPI_SSPPERIPHID0_PARTNUMBER0_ACCESS "RO"
// =============================================================================
// Register : SPI_SSPPERIPHID1
// Description : Peripheral identification registers, SSPPeriphID0-3 on page
// 3-13
#define SPI_SSPPERIPHID1_OFFSET _u(0x00000fe4)
#define SPI_SSPPERIPHID1_BITS _u(0x000000ff)
#define SPI_SSPPERIPHID1_RESET _u(0x00000010)
// -----------------------------------------------------------------------------
// Field : SPI_SSPPERIPHID1_DESIGNER0
// Description : These bits read back as 0x1
#define SPI_SSPPERIPHID1_DESIGNER0_RESET _u(0x1)
#define SPI_SSPPERIPHID1_DESIGNER0_BITS _u(0x000000f0)
#define SPI_SSPPERIPHID1_DESIGNER0_MSB _u(7)
#define SPI_SSPPERIPHID1_DESIGNER0_LSB _u(4)
#define SPI_SSPPERIPHID1_DESIGNER0_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : SPI_SSPPERIPHID1_PARTNUMBER1
// Description : These bits read back as 0x0
#define SPI_SSPPERIPHID1_PARTNUMBER1_RESET _u(0x0)
#define SPI_SSPPERIPHID1_PARTNUMBER1_BITS _u(0x0000000f)
#define SPI_SSPPERIPHID1_PARTNUMBER1_MSB _u(3)
#define SPI_SSPPERIPHID1_PARTNUMBER1_LSB _u(0)
#define SPI_SSPPERIPHID1_PARTNUMBER1_ACCESS "RO"
// =============================================================================
// Register : SPI_SSPPERIPHID2
// Description : Peripheral identification registers, SSPPeriphID0-3 on page
// 3-13
#define SPI_SSPPERIPHID2_OFFSET _u(0x00000fe8)
#define SPI_SSPPERIPHID2_BITS _u(0x000000ff)
#define SPI_SSPPERIPHID2_RESET _u(0x00000034)
// -----------------------------------------------------------------------------
// Field : SPI_SSPPERIPHID2_REVISION
// Description : These bits return the peripheral revision
#define SPI_SSPPERIPHID2_REVISION_RESET _u(0x3)
#define SPI_SSPPERIPHID2_REVISION_BITS _u(0x000000f0)
#define SPI_SSPPERIPHID2_REVISION_MSB _u(7)
#define SPI_SSPPERIPHID2_REVISION_LSB _u(4)
#define SPI_SSPPERIPHID2_REVISION_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : SPI_SSPPERIPHID2_DESIGNER1
// Description : These bits read back as 0x4
#define SPI_SSPPERIPHID2_DESIGNER1_RESET _u(0x4)
#define SPI_SSPPERIPHID2_DESIGNER1_BITS _u(0x0000000f)
#define SPI_SSPPERIPHID2_DESIGNER1_MSB _u(3)
#define SPI_SSPPERIPHID2_DESIGNER1_LSB _u(0)
#define SPI_SSPPERIPHID2_DESIGNER1_ACCESS "RO"
// =============================================================================
// Register : SPI_SSPPERIPHID3
// Description : Peripheral identification registers, SSPPeriphID0-3 on page
// 3-13
#define SPI_SSPPERIPHID3_OFFSET _u(0x00000fec)
#define SPI_SSPPERIPHID3_BITS _u(0x000000ff)
#define SPI_SSPPERIPHID3_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : SPI_SSPPERIPHID3_CONFIGURATION
// Description : These bits read back as 0x00
#define SPI_SSPPERIPHID3_CONFIGURATION_RESET _u(0x00)
#define SPI_SSPPERIPHID3_CONFIGURATION_BITS _u(0x000000ff)
#define SPI_SSPPERIPHID3_CONFIGURATION_MSB _u(7)
#define SPI_SSPPERIPHID3_CONFIGURATION_LSB _u(0)
#define SPI_SSPPERIPHID3_CONFIGURATION_ACCESS "RO"
// =============================================================================
// Register : SPI_SSPPCELLID0
// Description : PrimeCell identification registers, SSPPCellID0-3 on page 3-16
#define SPI_SSPPCELLID0_OFFSET _u(0x00000ff0)
#define SPI_SSPPCELLID0_BITS _u(0x000000ff)
#define SPI_SSPPCELLID0_RESET _u(0x0000000d)
// -----------------------------------------------------------------------------
// Field : SPI_SSPPCELLID0_SSPPCELLID0
// Description : These bits read back as 0x0D
#define SPI_SSPPCELLID0_SSPPCELLID0_RESET _u(0x0d)
#define SPI_SSPPCELLID0_SSPPCELLID0_BITS _u(0x000000ff)
#define SPI_SSPPCELLID0_SSPPCELLID0_MSB _u(7)
#define SPI_SSPPCELLID0_SSPPCELLID0_LSB _u(0)
#define SPI_SSPPCELLID0_SSPPCELLID0_ACCESS "RO"
// =============================================================================
// Register : SPI_SSPPCELLID1
// Description : PrimeCell identification registers, SSPPCellID0-3 on page 3-16
#define SPI_SSPPCELLID1_OFFSET _u(0x00000ff4)
#define SPI_SSPPCELLID1_BITS _u(0x000000ff)
#define SPI_SSPPCELLID1_RESET _u(0x000000f0)
// -----------------------------------------------------------------------------
// Field : SPI_SSPPCELLID1_SSPPCELLID1
// Description : These bits read back as 0xF0
#define SPI_SSPPCELLID1_SSPPCELLID1_RESET _u(0xf0)
#define SPI_SSPPCELLID1_SSPPCELLID1_BITS _u(0x000000ff)
#define SPI_SSPPCELLID1_SSPPCELLID1_MSB _u(7)
#define SPI_SSPPCELLID1_SSPPCELLID1_LSB _u(0)
#define SPI_SSPPCELLID1_SSPPCELLID1_ACCESS "RO"
// =============================================================================
// Register : SPI_SSPPCELLID2
// Description : PrimeCell identification registers, SSPPCellID0-3 on page 3-16
#define SPI_SSPPCELLID2_OFFSET _u(0x00000ff8)
#define SPI_SSPPCELLID2_BITS _u(0x000000ff)
#define SPI_SSPPCELLID2_RESET _u(0x00000005)
// -----------------------------------------------------------------------------
// Field : SPI_SSPPCELLID2_SSPPCELLID2
// Description : These bits read back as 0x05
#define SPI_SSPPCELLID2_SSPPCELLID2_RESET _u(0x05)
#define SPI_SSPPCELLID2_SSPPCELLID2_BITS _u(0x000000ff)
#define SPI_SSPPCELLID2_SSPPCELLID2_MSB _u(7)
#define SPI_SSPPCELLID2_SSPPCELLID2_LSB _u(0)
#define SPI_SSPPCELLID2_SSPPCELLID2_ACCESS "RO"
// =============================================================================
// Register : SPI_SSPPCELLID3
// Description : PrimeCell identification registers, SSPPCellID0-3 on page 3-16
#define SPI_SSPPCELLID3_OFFSET _u(0x00000ffc)
#define SPI_SSPPCELLID3_BITS _u(0x000000ff)
#define SPI_SSPPCELLID3_RESET _u(0x000000b1)
// -----------------------------------------------------------------------------
// Field : SPI_SSPPCELLID3_SSPPCELLID3
// Description : These bits read back as 0xB1
#define SPI_SSPPCELLID3_SSPPCELLID3_RESET _u(0xb1)
#define SPI_SSPPCELLID3_SSPPCELLID3_BITS _u(0x000000ff)
#define SPI_SSPPCELLID3_SSPPCELLID3_MSB _u(7)
#define SPI_SSPPCELLID3_SSPPCELLID3_LSB _u(0)
#define SPI_SSPPCELLID3_SSPPCELLID3_ACCESS "RO"
// =============================================================================
#endif // _HARDWARE_REGS_SPI_H

279
arch/arm/src/rp23xx/hardware/regs/syscfg.h
View file

@ -1,279 +0,0 @@
// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
// =============================================================================
// Register block : SYSCFG
// Version : 1
// Bus type : apb
// Description : Register block for various chip control signals
// =============================================================================
#ifndef _HARDWARE_REGS_SYSCFG_H
#define _HARDWARE_REGS_SYSCFG_H
// =============================================================================
// Register : SYSCFG_PROC_CONFIG
// Description : Configuration for processors
#define SYSCFG_PROC_CONFIG_OFFSET _u(0x00000000)
#define SYSCFG_PROC_CONFIG_BITS _u(0x00000003)
#define SYSCFG_PROC_CONFIG_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : SYSCFG_PROC_CONFIG_PROC1_HALTED
// Description : Indication that proc1 has halted
#define SYSCFG_PROC_CONFIG_PROC1_HALTED_RESET _u(0x0)
#define SYSCFG_PROC_CONFIG_PROC1_HALTED_BITS _u(0x00000002)
#define SYSCFG_PROC_CONFIG_PROC1_HALTED_MSB _u(1)
#define SYSCFG_PROC_CONFIG_PROC1_HALTED_LSB _u(1)
#define SYSCFG_PROC_CONFIG_PROC1_HALTED_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : SYSCFG_PROC_CONFIG_PROC0_HALTED
// Description : Indication that proc0 has halted
#define SYSCFG_PROC_CONFIG_PROC0_HALTED_RESET _u(0x0)
#define SYSCFG_PROC_CONFIG_PROC0_HALTED_BITS _u(0x00000001)
#define SYSCFG_PROC_CONFIG_PROC0_HALTED_MSB _u(0)
#define SYSCFG_PROC_CONFIG_PROC0_HALTED_LSB _u(0)
#define SYSCFG_PROC_CONFIG_PROC0_HALTED_ACCESS "RO"
// =============================================================================
// Register : SYSCFG_PROC_IN_SYNC_BYPASS
// Description : For each bit, if 1, bypass the input synchronizer between that
// GPIO
// and the GPIO input register in the SIO. The input synchronizers
// should
// generally be unbypassed, to avoid injecting metastabilities
// into processors.
// If you're feeling brave, you can bypass to save two cycles of
// input
// latency. This register applies to GPIO 0...31.
#define SYSCFG_PROC_IN_SYNC_BYPASS_OFFSET _u(0x00000004)
#define SYSCFG_PROC_IN_SYNC_BYPASS_BITS _u(0xffffffff)
#define SYSCFG_PROC_IN_SYNC_BYPASS_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : SYSCFG_PROC_IN_SYNC_BYPASS_GPIO
#define SYSCFG_PROC_IN_SYNC_BYPASS_GPIO_RESET _u(0x00000000)
#define SYSCFG_PROC_IN_SYNC_BYPASS_GPIO_BITS _u(0xffffffff)
#define SYSCFG_PROC_IN_SYNC_BYPASS_GPIO_MSB _u(31)
#define SYSCFG_PROC_IN_SYNC_BYPASS_GPIO_LSB _u(0)
#define SYSCFG_PROC_IN_SYNC_BYPASS_GPIO_ACCESS "RW"
// =============================================================================
// Register : SYSCFG_PROC_IN_SYNC_BYPASS_HI
// Description : For each bit, if 1, bypass the input synchronizer between that
// GPIO
// and the GPIO input register in the SIO. The input synchronizers
// should
// generally be unbypassed, to avoid injecting metastabilities
// into processors.
// If you're feeling brave, you can bypass to save two cycles of
// input
// latency. This register applies to GPIO 32...47. USB GPIO 56..57
// QSPI GPIO 58..63
#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_OFFSET _u(0x00000008)
#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_BITS _u(0xff00ffff)
#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : SYSCFG_PROC_IN_SYNC_BYPASS_HI_QSPI_SD
#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_QSPI_SD_RESET _u(0x0)
#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_QSPI_SD_BITS _u(0xf0000000)
#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_QSPI_SD_MSB _u(31)
#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_QSPI_SD_LSB _u(28)
#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_QSPI_SD_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SYSCFG_PROC_IN_SYNC_BYPASS_HI_QSPI_CSN
#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_QSPI_CSN_RESET _u(0x0)
#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_QSPI_CSN_BITS _u(0x08000000)
#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_QSPI_CSN_MSB _u(27)
#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_QSPI_CSN_LSB _u(27)
#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_QSPI_CSN_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SYSCFG_PROC_IN_SYNC_BYPASS_HI_QSPI_SCK
#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_QSPI_SCK_RESET _u(0x0)
#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_QSPI_SCK_BITS _u(0x04000000)
#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_QSPI_SCK_MSB _u(26)
#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_QSPI_SCK_LSB _u(26)
#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_QSPI_SCK_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SYSCFG_PROC_IN_SYNC_BYPASS_HI_USB_DM
#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_USB_DM_RESET _u(0x0)
#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_USB_DM_BITS _u(0x02000000)
#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_USB_DM_MSB _u(25)
#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_USB_DM_LSB _u(25)
#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_USB_DM_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SYSCFG_PROC_IN_SYNC_BYPASS_HI_USB_DP
#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_USB_DP_RESET _u(0x0)
#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_USB_DP_BITS _u(0x01000000)
#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_USB_DP_MSB _u(24)
#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_USB_DP_LSB _u(24)
#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_USB_DP_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SYSCFG_PROC_IN_SYNC_BYPASS_HI_GPIO
#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_GPIO_RESET _u(0x0000)
#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_GPIO_BITS _u(0x0000ffff)
#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_GPIO_MSB _u(15)
#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_GPIO_LSB _u(0)
#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_GPIO_ACCESS "RW"
// =============================================================================
// Register : SYSCFG_DBGFORCE
// Description : Directly control the chip SWD debug port
#define SYSCFG_DBGFORCE_OFFSET _u(0x0000000c)
#define SYSCFG_DBGFORCE_BITS _u(0x0000000f)
#define SYSCFG_DBGFORCE_RESET _u(0x00000006)
// -----------------------------------------------------------------------------
// Field : SYSCFG_DBGFORCE_ATTACH
// Description : Attach chip debug port to syscfg controls, and disconnect it
// from external SWD pads.
#define SYSCFG_DBGFORCE_ATTACH_RESET _u(0x0)
#define SYSCFG_DBGFORCE_ATTACH_BITS _u(0x00000008)
#define SYSCFG_DBGFORCE_ATTACH_MSB _u(3)
#define SYSCFG_DBGFORCE_ATTACH_LSB _u(3)
#define SYSCFG_DBGFORCE_ATTACH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SYSCFG_DBGFORCE_SWCLK
// Description : Directly drive SWCLK, if ATTACH is set
#define SYSCFG_DBGFORCE_SWCLK_RESET _u(0x1)
#define SYSCFG_DBGFORCE_SWCLK_BITS _u(0x00000004)
#define SYSCFG_DBGFORCE_SWCLK_MSB _u(2)
#define SYSCFG_DBGFORCE_SWCLK_LSB _u(2)
#define SYSCFG_DBGFORCE_SWCLK_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SYSCFG_DBGFORCE_SWDI
// Description : Directly drive SWDIO input, if ATTACH is set
#define SYSCFG_DBGFORCE_SWDI_RESET _u(0x1)
#define SYSCFG_DBGFORCE_SWDI_BITS _u(0x00000002)
#define SYSCFG_DBGFORCE_SWDI_MSB _u(1)
#define SYSCFG_DBGFORCE_SWDI_LSB _u(1)
#define SYSCFG_DBGFORCE_SWDI_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SYSCFG_DBGFORCE_SWDO
// Description : Observe the value of SWDIO output.
#define SYSCFG_DBGFORCE_SWDO_RESET "-"
#define SYSCFG_DBGFORCE_SWDO_BITS _u(0x00000001)
#define SYSCFG_DBGFORCE_SWDO_MSB _u(0)
#define SYSCFG_DBGFORCE_SWDO_LSB _u(0)
#define SYSCFG_DBGFORCE_SWDO_ACCESS "RO"
// =============================================================================
// Register : SYSCFG_MEMPOWERDOWN
// Description : Control PD pins to memories.
// Set high to put memories to a low power state. In this state
// the memories will retain contents but not be accessible
// Use with caution
#define SYSCFG_MEMPOWERDOWN_OFFSET _u(0x00000010)
#define SYSCFG_MEMPOWERDOWN_BITS _u(0x00001fff)
#define SYSCFG_MEMPOWERDOWN_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : SYSCFG_MEMPOWERDOWN_BOOTRAM
#define SYSCFG_MEMPOWERDOWN_BOOTRAM_RESET _u(0x0)
#define SYSCFG_MEMPOWERDOWN_BOOTRAM_BITS _u(0x00001000)
#define SYSCFG_MEMPOWERDOWN_BOOTRAM_MSB _u(12)
#define SYSCFG_MEMPOWERDOWN_BOOTRAM_LSB _u(12)
#define SYSCFG_MEMPOWERDOWN_BOOTRAM_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SYSCFG_MEMPOWERDOWN_ROM
#define SYSCFG_MEMPOWERDOWN_ROM_RESET _u(0x0)
#define SYSCFG_MEMPOWERDOWN_ROM_BITS _u(0x00000800)
#define SYSCFG_MEMPOWERDOWN_ROM_MSB _u(11)
#define SYSCFG_MEMPOWERDOWN_ROM_LSB _u(11)
#define SYSCFG_MEMPOWERDOWN_ROM_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SYSCFG_MEMPOWERDOWN_USB
#define SYSCFG_MEMPOWERDOWN_USB_RESET _u(0x0)
#define SYSCFG_MEMPOWERDOWN_USB_BITS _u(0x00000400)
#define SYSCFG_MEMPOWERDOWN_USB_MSB _u(10)
#define SYSCFG_MEMPOWERDOWN_USB_LSB _u(10)
#define SYSCFG_MEMPOWERDOWN_USB_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SYSCFG_MEMPOWERDOWN_SRAM9
#define SYSCFG_MEMPOWERDOWN_SRAM9_RESET _u(0x0)
#define SYSCFG_MEMPOWERDOWN_SRAM9_BITS _u(0x00000200)
#define SYSCFG_MEMPOWERDOWN_SRAM9_MSB _u(9)
#define SYSCFG_MEMPOWERDOWN_SRAM9_LSB _u(9)
#define SYSCFG_MEMPOWERDOWN_SRAM9_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SYSCFG_MEMPOWERDOWN_SRAM8
#define SYSCFG_MEMPOWERDOWN_SRAM8_RESET _u(0x0)
#define SYSCFG_MEMPOWERDOWN_SRAM8_BITS _u(0x00000100)
#define SYSCFG_MEMPOWERDOWN_SRAM8_MSB _u(8)
#define SYSCFG_MEMPOWERDOWN_SRAM8_LSB _u(8)
#define SYSCFG_MEMPOWERDOWN_SRAM8_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SYSCFG_MEMPOWERDOWN_SRAM7
#define SYSCFG_MEMPOWERDOWN_SRAM7_RESET _u(0x0)
#define SYSCFG_MEMPOWERDOWN_SRAM7_BITS _u(0x00000080)
#define SYSCFG_MEMPOWERDOWN_SRAM7_MSB _u(7)
#define SYSCFG_MEMPOWERDOWN_SRAM7_LSB _u(7)
#define SYSCFG_MEMPOWERDOWN_SRAM7_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SYSCFG_MEMPOWERDOWN_SRAM6
#define SYSCFG_MEMPOWERDOWN_SRAM6_RESET _u(0x0)
#define SYSCFG_MEMPOWERDOWN_SRAM6_BITS _u(0x00000040)
#define SYSCFG_MEMPOWERDOWN_SRAM6_MSB _u(6)
#define SYSCFG_MEMPOWERDOWN_SRAM6_LSB _u(6)
#define SYSCFG_MEMPOWERDOWN_SRAM6_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SYSCFG_MEMPOWERDOWN_SRAM5
#define SYSCFG_MEMPOWERDOWN_SRAM5_RESET _u(0x0)
#define SYSCFG_MEMPOWERDOWN_SRAM5_BITS _u(0x00000020)
#define SYSCFG_MEMPOWERDOWN_SRAM5_MSB _u(5)
#define SYSCFG_MEMPOWERDOWN_SRAM5_LSB _u(5)
#define SYSCFG_MEMPOWERDOWN_SRAM5_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SYSCFG_MEMPOWERDOWN_SRAM4
#define SYSCFG_MEMPOWERDOWN_SRAM4_RESET _u(0x0)
#define SYSCFG_MEMPOWERDOWN_SRAM4_BITS _u(0x00000010)
#define SYSCFG_MEMPOWERDOWN_SRAM4_MSB _u(4)
#define SYSCFG_MEMPOWERDOWN_SRAM4_LSB _u(4)
#define SYSCFG_MEMPOWERDOWN_SRAM4_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SYSCFG_MEMPOWERDOWN_SRAM3
#define SYSCFG_MEMPOWERDOWN_SRAM3_RESET _u(0x0)
#define SYSCFG_MEMPOWERDOWN_SRAM3_BITS _u(0x00000008)
#define SYSCFG_MEMPOWERDOWN_SRAM3_MSB _u(3)
#define SYSCFG_MEMPOWERDOWN_SRAM3_LSB _u(3)
#define SYSCFG_MEMPOWERDOWN_SRAM3_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SYSCFG_MEMPOWERDOWN_SRAM2
#define SYSCFG_MEMPOWERDOWN_SRAM2_RESET _u(0x0)
#define SYSCFG_MEMPOWERDOWN_SRAM2_BITS _u(0x00000004)
#define SYSCFG_MEMPOWERDOWN_SRAM2_MSB _u(2)
#define SYSCFG_MEMPOWERDOWN_SRAM2_LSB _u(2)
#define SYSCFG_MEMPOWERDOWN_SRAM2_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SYSCFG_MEMPOWERDOWN_SRAM1
#define SYSCFG_MEMPOWERDOWN_SRAM1_RESET _u(0x0)
#define SYSCFG_MEMPOWERDOWN_SRAM1_BITS _u(0x00000002)
#define SYSCFG_MEMPOWERDOWN_SRAM1_MSB _u(1)
#define SYSCFG_MEMPOWERDOWN_SRAM1_LSB _u(1)
#define SYSCFG_MEMPOWERDOWN_SRAM1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SYSCFG_MEMPOWERDOWN_SRAM0
#define SYSCFG_MEMPOWERDOWN_SRAM0_RESET _u(0x0)
#define SYSCFG_MEMPOWERDOWN_SRAM0_BITS _u(0x00000001)
#define SYSCFG_MEMPOWERDOWN_SRAM0_MSB _u(0)
#define SYSCFG_MEMPOWERDOWN_SRAM0_LSB _u(0)
#define SYSCFG_MEMPOWERDOWN_SRAM0_ACCESS "RW"
// =============================================================================
// Register : SYSCFG_AUXCTRL
// Description : Auxiliary system control register
// * Bits 7:2: Reserved
//
// * Bit 1: When clear, the LPOSC output is XORed into the TRNG
// ROSC output as an additional, uncorrelated entropy source. When
// set, this behaviour is disabled.
//
// * Bit 0: Force POWMAN clock to switch to LPOSC, by asserting
// its WDRESET input. This must be set before initiating a
// watchdog reset of the RSM from a stage that includes CLOCKS, if
// POWMAN is running from clk_ref at the point that the watchdog
// reset takes place. Otherwise, the short pulse generated on
// clk_ref by the reset of the CLOCKS block may affect POWMAN
// register state.
#define SYSCFG_AUXCTRL_OFFSET _u(0x00000014)
#define SYSCFG_AUXCTRL_BITS _u(0x000000ff)
#define SYSCFG_AUXCTRL_RESET _u(0x00000000)
#define SYSCFG_AUXCTRL_MSB _u(7)
#define SYSCFG_AUXCTRL_LSB _u(0)
#define SYSCFG_AUXCTRL_ACCESS "RW"
// =============================================================================
#endif // _HARDWARE_REGS_SYSCFG_H

111
arch/arm/src/rp23xx/hardware/regs/sysinfo.h
View file

@ -1,111 +0,0 @@
// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
// =============================================================================
// Register block : SYSINFO
// Version : 1
// Bus type : apb
// =============================================================================
#ifndef _HARDWARE_REGS_SYSINFO_H
#define _HARDWARE_REGS_SYSINFO_H
// =============================================================================
// Register : SYSINFO_CHIP_ID
// Description : JEDEC JEP-106 compliant chip identifier.
#define SYSINFO_CHIP_ID_OFFSET _u(0x00000000)
#define SYSINFO_CHIP_ID_BITS _u(0xffffffff)
#define SYSINFO_CHIP_ID_RESET _u(0x00000001)
// -----------------------------------------------------------------------------
// Field : SYSINFO_CHIP_ID_REVISION
#define SYSINFO_CHIP_ID_REVISION_RESET "-"
#define SYSINFO_CHIP_ID_REVISION_BITS _u(0xf0000000)
#define SYSINFO_CHIP_ID_REVISION_MSB _u(31)
#define SYSINFO_CHIP_ID_REVISION_LSB _u(28)
#define SYSINFO_CHIP_ID_REVISION_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : SYSINFO_CHIP_ID_PART
#define SYSINFO_CHIP_ID_PART_RESET "-"
#define SYSINFO_CHIP_ID_PART_BITS _u(0x0ffff000)
#define SYSINFO_CHIP_ID_PART_MSB _u(27)
#define SYSINFO_CHIP_ID_PART_LSB _u(12)
#define SYSINFO_CHIP_ID_PART_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : SYSINFO_CHIP_ID_MANUFACTURER
#define SYSINFO_CHIP_ID_MANUFACTURER_RESET "-"
#define SYSINFO_CHIP_ID_MANUFACTURER_BITS _u(0x00000ffe)
#define SYSINFO_CHIP_ID_MANUFACTURER_MSB _u(11)
#define SYSINFO_CHIP_ID_MANUFACTURER_LSB _u(1)
#define SYSINFO_CHIP_ID_MANUFACTURER_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : SYSINFO_CHIP_ID_STOP_BIT
#define SYSINFO_CHIP_ID_STOP_BIT_RESET _u(0x1)
#define SYSINFO_CHIP_ID_STOP_BIT_BITS _u(0x00000001)
#define SYSINFO_CHIP_ID_STOP_BIT_MSB _u(0)
#define SYSINFO_CHIP_ID_STOP_BIT_LSB _u(0)
#define SYSINFO_CHIP_ID_STOP_BIT_ACCESS "RO"
// =============================================================================
// Register : SYSINFO_PACKAGE_SEL
#define SYSINFO_PACKAGE_SEL_OFFSET _u(0x00000004)
#define SYSINFO_PACKAGE_SEL_BITS _u(0x00000001)
#define SYSINFO_PACKAGE_SEL_RESET _u(0x00000000)
#define SYSINFO_PACKAGE_SEL_MSB _u(0)
#define SYSINFO_PACKAGE_SEL_LSB _u(0)
#define SYSINFO_PACKAGE_SEL_ACCESS "RO"
// =============================================================================
// Register : SYSINFO_PLATFORM
// Description : Platform register. Allows software to know what environment it
// is running in during pre-production development. Post-
// production, the PLATFORM is always ASIC, non-SIM.
#define SYSINFO_PLATFORM_OFFSET _u(0x00000008)
#define SYSINFO_PLATFORM_BITS _u(0x0000001f)
#define SYSINFO_PLATFORM_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : SYSINFO_PLATFORM_GATESIM
#define SYSINFO_PLATFORM_GATESIM_RESET "-"
#define SYSINFO_PLATFORM_GATESIM_BITS _u(0x00000010)
#define SYSINFO_PLATFORM_GATESIM_MSB _u(4)
#define SYSINFO_PLATFORM_GATESIM_LSB _u(4)
#define SYSINFO_PLATFORM_GATESIM_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : SYSINFO_PLATFORM_BATCHSIM
#define SYSINFO_PLATFORM_BATCHSIM_RESET "-"
#define SYSINFO_PLATFORM_BATCHSIM_BITS _u(0x00000008)
#define SYSINFO_PLATFORM_BATCHSIM_MSB _u(3)
#define SYSINFO_PLATFORM_BATCHSIM_LSB _u(3)
#define SYSINFO_PLATFORM_BATCHSIM_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : SYSINFO_PLATFORM_HDLSIM
#define SYSINFO_PLATFORM_HDLSIM_RESET "-"
#define SYSINFO_PLATFORM_HDLSIM_BITS _u(0x00000004)
#define SYSINFO_PLATFORM_HDLSIM_MSB _u(2)
#define SYSINFO_PLATFORM_HDLSIM_LSB _u(2)
#define SYSINFO_PLATFORM_HDLSIM_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : SYSINFO_PLATFORM_ASIC
#define SYSINFO_PLATFORM_ASIC_RESET "-"
#define SYSINFO_PLATFORM_ASIC_BITS _u(0x00000002)
#define SYSINFO_PLATFORM_ASIC_MSB _u(1)
#define SYSINFO_PLATFORM_ASIC_LSB _u(1)
#define SYSINFO_PLATFORM_ASIC_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : SYSINFO_PLATFORM_FPGA
#define SYSINFO_PLATFORM_FPGA_RESET "-"
#define SYSINFO_PLATFORM_FPGA_BITS _u(0x00000001)
#define SYSINFO_PLATFORM_FPGA_MSB _u(0)
#define SYSINFO_PLATFORM_FPGA_LSB _u(0)
#define SYSINFO_PLATFORM_FPGA_ACCESS "RO"
// =============================================================================
// Register : SYSINFO_GITREF_RP2350
// Description : Git hash of the chip source. Used to identify chip version.
#define SYSINFO_GITREF_RP2350_OFFSET _u(0x00000014)
#define SYSINFO_GITREF_RP2350_BITS _u(0xffffffff)
#define SYSINFO_GITREF_RP2350_RESET "-"
#define SYSINFO_GITREF_RP2350_MSB _u(31)
#define SYSINFO_GITREF_RP2350_LSB _u(0)
#define SYSINFO_GITREF_RP2350_ACCESS "RO"
// =============================================================================
#endif // _HARDWARE_REGS_SYSINFO_H

48
arch/arm/src/rp23xx/hardware/regs/tbman.h
View file

@ -1,48 +0,0 @@
// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
// =============================================================================
// Register block : TBMAN
// Version : 1
// Bus type : apb
// Description : For managing simulation testbenches
// =============================================================================
#ifndef _HARDWARE_REGS_TBMAN_H
#define _HARDWARE_REGS_TBMAN_H
// =============================================================================
// Register : TBMAN_PLATFORM
// Description : Indicates the type of platform in use
#define TBMAN_PLATFORM_OFFSET _u(0x00000000)
#define TBMAN_PLATFORM_BITS _u(0x00000007)
#define TBMAN_PLATFORM_RESET _u(0x00000001)
// -----------------------------------------------------------------------------
// Field : TBMAN_PLATFORM_HDLSIM
// Description : Indicates the platform is a simulation
#define TBMAN_PLATFORM_HDLSIM_RESET _u(0x0)
#define TBMAN_PLATFORM_HDLSIM_BITS _u(0x00000004)
#define TBMAN_PLATFORM_HDLSIM_MSB _u(2)
#define TBMAN_PLATFORM_HDLSIM_LSB _u(2)
#define TBMAN_PLATFORM_HDLSIM_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : TBMAN_PLATFORM_FPGA
// Description : Indicates the platform is an FPGA
#define TBMAN_PLATFORM_FPGA_RESET _u(0x0)
#define TBMAN_PLATFORM_FPGA_BITS _u(0x00000002)
#define TBMAN_PLATFORM_FPGA_MSB _u(1)
#define TBMAN_PLATFORM_FPGA_LSB _u(1)
#define TBMAN_PLATFORM_FPGA_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : TBMAN_PLATFORM_ASIC
// Description : Indicates the platform is an ASIC
#define TBMAN_PLATFORM_ASIC_RESET _u(0x1)
#define TBMAN_PLATFORM_ASIC_BITS _u(0x00000001)
#define TBMAN_PLATFORM_ASIC_MSB _u(0)
#define TBMAN_PLATFORM_ASIC_LSB _u(0)
#define TBMAN_PLATFORM_ASIC_ACCESS "RO"
// =============================================================================
#endif // _HARDWARE_REGS_TBMAN_H

275
arch/arm/src/rp23xx/hardware/regs/ticks.h
View file

@ -1,275 +0,0 @@
// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
// =============================================================================
// Register block : TICKS
// Version : 1
// Bus type : apb
// =============================================================================
#ifndef _HARDWARE_REGS_TICKS_H
#define _HARDWARE_REGS_TICKS_H
// =============================================================================
// Register : TICKS_PROC0_CTRL
// Description : Controls the tick generator
#define TICKS_PROC0_CTRL_OFFSET _u(0x00000000)
#define TICKS_PROC0_CTRL_BITS _u(0x00000003)
#define TICKS_PROC0_CTRL_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : TICKS_PROC0_CTRL_RUNNING
// Description : Is the tick generator running?
#define TICKS_PROC0_CTRL_RUNNING_RESET "-"
#define TICKS_PROC0_CTRL_RUNNING_BITS _u(0x00000002)
#define TICKS_PROC0_CTRL_RUNNING_MSB _u(1)
#define TICKS_PROC0_CTRL_RUNNING_LSB _u(1)
#define TICKS_PROC0_CTRL_RUNNING_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : TICKS_PROC0_CTRL_ENABLE
// Description : start / stop tick generation
#define TICKS_PROC0_CTRL_ENABLE_RESET _u(0x0)
#define TICKS_PROC0_CTRL_ENABLE_BITS _u(0x00000001)
#define TICKS_PROC0_CTRL_ENABLE_MSB _u(0)
#define TICKS_PROC0_CTRL_ENABLE_LSB _u(0)
#define TICKS_PROC0_CTRL_ENABLE_ACCESS "RW"
// =============================================================================
// Register : TICKS_PROC0_CYCLES
// Description : None
// Total number of clk_tick cycles before the next tick.
#define TICKS_PROC0_CYCLES_OFFSET _u(0x00000004)
#define TICKS_PROC0_CYCLES_BITS _u(0x000001ff)
#define TICKS_PROC0_CYCLES_RESET _u(0x00000000)
#define TICKS_PROC0_CYCLES_MSB _u(8)
#define TICKS_PROC0_CYCLES_LSB _u(0)
#define TICKS_PROC0_CYCLES_ACCESS "RW"
// =============================================================================
// Register : TICKS_PROC0_COUNT
// Description : None
// Count down timer: the remaining number clk_tick cycles before
// the next tick is generated.
#define TICKS_PROC0_COUNT_OFFSET _u(0x00000008)
#define TICKS_PROC0_COUNT_BITS _u(0x000001ff)
#define TICKS_PROC0_COUNT_RESET "-"
#define TICKS_PROC0_COUNT_MSB _u(8)
#define TICKS_PROC0_COUNT_LSB _u(0)
#define TICKS_PROC0_COUNT_ACCESS "RO"
// =============================================================================
// Register : TICKS_PROC1_CTRL
// Description : Controls the tick generator
#define TICKS_PROC1_CTRL_OFFSET _u(0x0000000c)
#define TICKS_PROC1_CTRL_BITS _u(0x00000003)
#define TICKS_PROC1_CTRL_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : TICKS_PROC1_CTRL_RUNNING
// Description : Is the tick generator running?
#define TICKS_PROC1_CTRL_RUNNING_RESET "-"
#define TICKS_PROC1_CTRL_RUNNING_BITS _u(0x00000002)
#define TICKS_PROC1_CTRL_RUNNING_MSB _u(1)
#define TICKS_PROC1_CTRL_RUNNING_LSB _u(1)
#define TICKS_PROC1_CTRL_RUNNING_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : TICKS_PROC1_CTRL_ENABLE
// Description : start / stop tick generation
#define TICKS_PROC1_CTRL_ENABLE_RESET _u(0x0)
#define TICKS_PROC1_CTRL_ENABLE_BITS _u(0x00000001)
#define TICKS_PROC1_CTRL_ENABLE_MSB _u(0)
#define TICKS_PROC1_CTRL_ENABLE_LSB _u(0)
#define TICKS_PROC1_CTRL_ENABLE_ACCESS "RW"
// =============================================================================
// Register : TICKS_PROC1_CYCLES
// Description : None
// Total number of clk_tick cycles before the next tick.
#define TICKS_PROC1_CYCLES_OFFSET _u(0x00000010)
#define TICKS_PROC1_CYCLES_BITS _u(0x000001ff)
#define TICKS_PROC1_CYCLES_RESET _u(0x00000000)
#define TICKS_PROC1_CYCLES_MSB _u(8)
#define TICKS_PROC1_CYCLES_LSB _u(0)
#define TICKS_PROC1_CYCLES_ACCESS "RW"
// =============================================================================
// Register : TICKS_PROC1_COUNT
// Description : None
// Count down timer: the remaining number clk_tick cycles before
// the next tick is generated.
#define TICKS_PROC1_COUNT_OFFSET _u(0x00000014)
#define TICKS_PROC1_COUNT_BITS _u(0x000001ff)
#define TICKS_PROC1_COUNT_RESET "-"
#define TICKS_PROC1_COUNT_MSB _u(8)
#define TICKS_PROC1_COUNT_LSB _u(0)
#define TICKS_PROC1_COUNT_ACCESS "RO"
// =============================================================================
// Register : TICKS_TIMER0_CTRL
// Description : Controls the tick generator
#define TICKS_TIMER0_CTRL_OFFSET _u(0x00000018)
#define TICKS_TIMER0_CTRL_BITS _u(0x00000003)
#define TICKS_TIMER0_CTRL_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : TICKS_TIMER0_CTRL_RUNNING
// Description : Is the tick generator running?
#define TICKS_TIMER0_CTRL_RUNNING_RESET "-"
#define TICKS_TIMER0_CTRL_RUNNING_BITS _u(0x00000002)
#define TICKS_TIMER0_CTRL_RUNNING_MSB _u(1)
#define TICKS_TIMER0_CTRL_RUNNING_LSB _u(1)
#define TICKS_TIMER0_CTRL_RUNNING_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : TICKS_TIMER0_CTRL_ENABLE
// Description : start / stop tick generation
#define TICKS_TIMER0_CTRL_ENABLE_RESET _u(0x0)
#define TICKS_TIMER0_CTRL_ENABLE_BITS _u(0x00000001)
#define TICKS_TIMER0_CTRL_ENABLE_MSB _u(0)
#define TICKS_TIMER0_CTRL_ENABLE_LSB _u(0)
#define TICKS_TIMER0_CTRL_ENABLE_ACCESS "RW"
// =============================================================================
// Register : TICKS_TIMER0_CYCLES
// Description : None
// Total number of clk_tick cycles before the next tick.
#define TICKS_TIMER0_CYCLES_OFFSET _u(0x0000001c)
#define TICKS_TIMER0_CYCLES_BITS _u(0x000001ff)
#define TICKS_TIMER0_CYCLES_RESET _u(0x00000000)
#define TICKS_TIMER0_CYCLES_MSB _u(8)
#define TICKS_TIMER0_CYCLES_LSB _u(0)
#define TICKS_TIMER0_CYCLES_ACCESS "RW"
// =============================================================================
// Register : TICKS_TIMER0_COUNT
// Description : None
// Count down timer: the remaining number clk_tick cycles before
// the next tick is generated.
#define TICKS_TIMER0_COUNT_OFFSET _u(0x00000020)
#define TICKS_TIMER0_COUNT_BITS _u(0x000001ff)
#define TICKS_TIMER0_COUNT_RESET "-"
#define TICKS_TIMER0_COUNT_MSB _u(8)
#define TICKS_TIMER0_COUNT_LSB _u(0)
#define TICKS_TIMER0_COUNT_ACCESS "RO"
// =============================================================================
// Register : TICKS_TIMER1_CTRL
// Description : Controls the tick generator
#define TICKS_TIMER1_CTRL_OFFSET _u(0x00000024)
#define TICKS_TIMER1_CTRL_BITS _u(0x00000003)
#define TICKS_TIMER1_CTRL_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : TICKS_TIMER1_CTRL_RUNNING
// Description : Is the tick generator running?
#define TICKS_TIMER1_CTRL_RUNNING_RESET "-"
#define TICKS_TIMER1_CTRL_RUNNING_BITS _u(0x00000002)
#define TICKS_TIMER1_CTRL_RUNNING_MSB _u(1)
#define TICKS_TIMER1_CTRL_RUNNING_LSB _u(1)
#define TICKS_TIMER1_CTRL_RUNNING_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : TICKS_TIMER1_CTRL_ENABLE
// Description : start / stop tick generation
#define TICKS_TIMER1_CTRL_ENABLE_RESET _u(0x0)
#define TICKS_TIMER1_CTRL_ENABLE_BITS _u(0x00000001)
#define TICKS_TIMER1_CTRL_ENABLE_MSB _u(0)
#define TICKS_TIMER1_CTRL_ENABLE_LSB _u(0)
#define TICKS_TIMER1_CTRL_ENABLE_ACCESS "RW"
// =============================================================================
// Register : TICKS_TIMER1_CYCLES
// Description : None
// Total number of clk_tick cycles before the next tick.
#define TICKS_TIMER1_CYCLES_OFFSET _u(0x00000028)
#define TICKS_TIMER1_CYCLES_BITS _u(0x000001ff)
#define TICKS_TIMER1_CYCLES_RESET _u(0x00000000)
#define TICKS_TIMER1_CYCLES_MSB _u(8)
#define TICKS_TIMER1_CYCLES_LSB _u(0)
#define TICKS_TIMER1_CYCLES_ACCESS "RW"
// =============================================================================
// Register : TICKS_TIMER1_COUNT
// Description : None
// Count down timer: the remaining number clk_tick cycles before
// the next tick is generated.
#define TICKS_TIMER1_COUNT_OFFSET _u(0x0000002c)
#define TICKS_TIMER1_COUNT_BITS _u(0x000001ff)
#define TICKS_TIMER1_COUNT_RESET "-"
#define TICKS_TIMER1_COUNT_MSB _u(8)
#define TICKS_TIMER1_COUNT_LSB _u(0)
#define TICKS_TIMER1_COUNT_ACCESS "RO"
// =============================================================================
// Register : TICKS_WATCHDOG_CTRL
// Description : Controls the tick generator
#define TICKS_WATCHDOG_CTRL_OFFSET _u(0x00000030)
#define TICKS_WATCHDOG_CTRL_BITS _u(0x00000003)
#define TICKS_WATCHDOG_CTRL_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : TICKS_WATCHDOG_CTRL_RUNNING
// Description : Is the tick generator running?
#define TICKS_WATCHDOG_CTRL_RUNNING_RESET "-"
#define TICKS_WATCHDOG_CTRL_RUNNING_BITS _u(0x00000002)
#define TICKS_WATCHDOG_CTRL_RUNNING_MSB _u(1)
#define TICKS_WATCHDOG_CTRL_RUNNING_LSB _u(1)
#define TICKS_WATCHDOG_CTRL_RUNNING_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : TICKS_WATCHDOG_CTRL_ENABLE
// Description : start / stop tick generation
#define TICKS_WATCHDOG_CTRL_ENABLE_RESET _u(0x0)
#define TICKS_WATCHDOG_CTRL_ENABLE_BITS _u(0x00000001)
#define TICKS_WATCHDOG_CTRL_ENABLE_MSB _u(0)
#define TICKS_WATCHDOG_CTRL_ENABLE_LSB _u(0)
#define TICKS_WATCHDOG_CTRL_ENABLE_ACCESS "RW"
// =============================================================================
// Register : TICKS_WATCHDOG_CYCLES
// Description : None
// Total number of clk_tick cycles before the next tick.
#define TICKS_WATCHDOG_CYCLES_OFFSET _u(0x00000034)
#define TICKS_WATCHDOG_CYCLES_BITS _u(0x000001ff)
#define TICKS_WATCHDOG_CYCLES_RESET _u(0x00000000)
#define TICKS_WATCHDOG_CYCLES_MSB _u(8)
#define TICKS_WATCHDOG_CYCLES_LSB _u(0)
#define TICKS_WATCHDOG_CYCLES_ACCESS "RW"
// =============================================================================
// Register : TICKS_WATCHDOG_COUNT
// Description : None
// Count down timer: the remaining number clk_tick cycles before
// the next tick is generated.
#define TICKS_WATCHDOG_COUNT_OFFSET _u(0x00000038)
#define TICKS_WATCHDOG_COUNT_BITS _u(0x000001ff)
#define TICKS_WATCHDOG_COUNT_RESET "-"
#define TICKS_WATCHDOG_COUNT_MSB _u(8)
#define TICKS_WATCHDOG_COUNT_LSB _u(0)
#define TICKS_WATCHDOG_COUNT_ACCESS "RO"
// =============================================================================
// Register : TICKS_RISCV_CTRL
// Description : Controls the tick generator
#define TICKS_RISCV_CTRL_OFFSET _u(0x0000003c)
#define TICKS_RISCV_CTRL_BITS _u(0x00000003)
#define TICKS_RISCV_CTRL_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : TICKS_RISCV_CTRL_RUNNING
// Description : Is the tick generator running?
#define TICKS_RISCV_CTRL_RUNNING_RESET "-"
#define TICKS_RISCV_CTRL_RUNNING_BITS _u(0x00000002)
#define TICKS_RISCV_CTRL_RUNNING_MSB _u(1)
#define TICKS_RISCV_CTRL_RUNNING_LSB _u(1)
#define TICKS_RISCV_CTRL_RUNNING_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : TICKS_RISCV_CTRL_ENABLE
// Description : start / stop tick generation
#define TICKS_RISCV_CTRL_ENABLE_RESET _u(0x0)
#define TICKS_RISCV_CTRL_ENABLE_BITS _u(0x00000001)
#define TICKS_RISCV_CTRL_ENABLE_MSB _u(0)
#define TICKS_RISCV_CTRL_ENABLE_LSB _u(0)
#define TICKS_RISCV_CTRL_ENABLE_ACCESS "RW"
// =============================================================================
// Register : TICKS_RISCV_CYCLES
// Description : None
// Total number of clk_tick cycles before the next tick.
#define TICKS_RISCV_CYCLES_OFFSET _u(0x00000040)
#define TICKS_RISCV_CYCLES_BITS _u(0x000001ff)
#define TICKS_RISCV_CYCLES_RESET _u(0x00000000)
#define TICKS_RISCV_CYCLES_MSB _u(8)
#define TICKS_RISCV_CYCLES_LSB _u(0)
#define TICKS_RISCV_CYCLES_ACCESS "RW"
// =============================================================================
// Register : TICKS_RISCV_COUNT
// Description : None
// Count down timer: the remaining number clk_tick cycles before
// the next tick is generated.
#define TICKS_RISCV_COUNT_OFFSET _u(0x00000044)
#define TICKS_RISCV_COUNT_BITS _u(0x000001ff)
#define TICKS_RISCV_COUNT_RESET "-"
#define TICKS_RISCV_COUNT_MSB _u(8)
#define TICKS_RISCV_COUNT_LSB _u(0)
#define TICKS_RISCV_COUNT_ACCESS "RO"
// =============================================================================
#endif // _HARDWARE_REGS_TICKS_H

346
arch/arm/src/rp23xx/hardware/regs/timer.h
View file

@ -1,346 +0,0 @@
// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
// =============================================================================
// Register block : TIMER
// Version : 1
// Bus type : apb
// Description : Controls time and alarms
//
// time is a 64 bit value indicating the time since power-on
//
// timeh is the top 32 bits of time & timel is the bottom 32
// bits to change time write to timelw before timehw to read
// time read from timelr before timehr
//
// An alarm is set by setting alarm_enable and writing to the
// corresponding alarm register When an alarm is pending, the
// corresponding alarm_running signal will be high An alarm can
// be cancelled before it has finished by clearing the
// alarm_enable When an alarm fires, the corresponding
// alarm_irq is set and alarm_running is cleared To clear the
// interrupt write a 1 to the corresponding alarm_irq The timer
// can be locked to prevent writing
// =============================================================================
#ifndef _HARDWARE_REGS_TIMER_H
#define _HARDWARE_REGS_TIMER_H
// =============================================================================
// Register : TIMER_TIMEHW
// Description : Write to bits 63:32 of time always write timelw before timehw
#define TIMER_TIMEHW_OFFSET _u(0x00000000)
#define TIMER_TIMEHW_BITS _u(0xffffffff)
#define TIMER_TIMEHW_RESET _u(0x00000000)
#define TIMER_TIMEHW_MSB _u(31)
#define TIMER_TIMEHW_LSB _u(0)
#define TIMER_TIMEHW_ACCESS "WF"
// =============================================================================
// Register : TIMER_TIMELW
// Description : Write to bits 31:0 of time writes do not get copied to time
// until timehw is written
#define TIMER_TIMELW_OFFSET _u(0x00000004)
#define TIMER_TIMELW_BITS _u(0xffffffff)
#define TIMER_TIMELW_RESET _u(0x00000000)
#define TIMER_TIMELW_MSB _u(31)
#define TIMER_TIMELW_LSB _u(0)
#define TIMER_TIMELW_ACCESS "WF"
// =============================================================================
// Register : TIMER_TIMEHR
// Description : Read from bits 63:32 of time always read timelr before timehr
#define TIMER_TIMEHR_OFFSET _u(0x00000008)
#define TIMER_TIMEHR_BITS _u(0xffffffff)
#define TIMER_TIMEHR_RESET _u(0x00000000)
#define TIMER_TIMEHR_MSB _u(31)
#define TIMER_TIMEHR_LSB _u(0)
#define TIMER_TIMEHR_ACCESS "RO"
// =============================================================================
// Register : TIMER_TIMELR
// Description : Read from bits 31:0 of time
#define TIMER_TIMELR_OFFSET _u(0x0000000c)
#define TIMER_TIMELR_BITS _u(0xffffffff)
#define TIMER_TIMELR_RESET _u(0x00000000)
#define TIMER_TIMELR_MSB _u(31)
#define TIMER_TIMELR_LSB _u(0)
#define TIMER_TIMELR_ACCESS "RO"
// =============================================================================
// Register : TIMER_ALARM0
// Description : Arm alarm 0, and configure the time it will fire. Once armed,
// the alarm fires when TIMER_ALARM0 == TIMELR. The alarm will
// disarm itself once it fires, and can be disarmed early using
// the ARMED status register.
#define TIMER_ALARM0_OFFSET _u(0x00000010)
#define TIMER_ALARM0_BITS _u(0xffffffff)
#define TIMER_ALARM0_RESET _u(0x00000000)
#define TIMER_ALARM0_MSB _u(31)
#define TIMER_ALARM0_LSB _u(0)
#define TIMER_ALARM0_ACCESS "RW"
// =============================================================================
// Register : TIMER_ALARM1
// Description : Arm alarm 1, and configure the time it will fire. Once armed,
// the alarm fires when TIMER_ALARM1 == TIMELR. The alarm will
// disarm itself once it fires, and can be disarmed early using
// the ARMED status register.
#define TIMER_ALARM1_OFFSET _u(0x00000014)
#define TIMER_ALARM1_BITS _u(0xffffffff)
#define TIMER_ALARM1_RESET _u(0x00000000)
#define TIMER_ALARM1_MSB _u(31)
#define TIMER_ALARM1_LSB _u(0)
#define TIMER_ALARM1_ACCESS "RW"
// =============================================================================
// Register : TIMER_ALARM2
// Description : Arm alarm 2, and configure the time it will fire. Once armed,
// the alarm fires when TIMER_ALARM2 == TIMELR. The alarm will
// disarm itself once it fires, and can be disarmed early using
// the ARMED status register.
#define TIMER_ALARM2_OFFSET _u(0x00000018)
#define TIMER_ALARM2_BITS _u(0xffffffff)
#define TIMER_ALARM2_RESET _u(0x00000000)
#define TIMER_ALARM2_MSB _u(31)
#define TIMER_ALARM2_LSB _u(0)
#define TIMER_ALARM2_ACCESS "RW"
// =============================================================================
// Register : TIMER_ALARM3
// Description : Arm alarm 3, and configure the time it will fire. Once armed,
// the alarm fires when TIMER_ALARM3 == TIMELR. The alarm will
// disarm itself once it fires, and can be disarmed early using
// the ARMED status register.
#define TIMER_ALARM3_OFFSET _u(0x0000001c)
#define TIMER_ALARM3_BITS _u(0xffffffff)
#define TIMER_ALARM3_RESET _u(0x00000000)
#define TIMER_ALARM3_MSB _u(31)
#define TIMER_ALARM3_LSB _u(0)
#define TIMER_ALARM3_ACCESS "RW"
// =============================================================================
// Register : TIMER_ARMED
// Description : Indicates the armed/disarmed status of each alarm. A write to
// the corresponding ALARMx register arms the alarm. Alarms
// automatically disarm upon firing, but writing ones here will
// disarm immediately without waiting to fire.
#define TIMER_ARMED_OFFSET _u(0x00000020)
#define TIMER_ARMED_BITS _u(0x0000000f)
#define TIMER_ARMED_RESET _u(0x00000000)
#define TIMER_ARMED_MSB _u(3)
#define TIMER_ARMED_LSB _u(0)
#define TIMER_ARMED_ACCESS "WC"
// =============================================================================
// Register : TIMER_TIMERAWH
// Description : Raw read from bits 63:32 of time (no side effects)
#define TIMER_TIMERAWH_OFFSET _u(0x00000024)
#define TIMER_TIMERAWH_BITS _u(0xffffffff)
#define TIMER_TIMERAWH_RESET _u(0x00000000)
#define TIMER_TIMERAWH_MSB _u(31)
#define TIMER_TIMERAWH_LSB _u(0)
#define TIMER_TIMERAWH_ACCESS "RO"
// =============================================================================
// Register : TIMER_TIMERAWL
// Description : Raw read from bits 31:0 of time (no side effects)
#define TIMER_TIMERAWL_OFFSET _u(0x00000028)
#define TIMER_TIMERAWL_BITS _u(0xffffffff)
#define TIMER_TIMERAWL_RESET _u(0x00000000)
#define TIMER_TIMERAWL_MSB _u(31)
#define TIMER_TIMERAWL_LSB _u(0)
#define TIMER_TIMERAWL_ACCESS "RO"
// =============================================================================
// Register : TIMER_DBGPAUSE
// Description : Set bits high to enable pause when the corresponding debug
// ports are active
#define TIMER_DBGPAUSE_OFFSET _u(0x0000002c)
#define TIMER_DBGPAUSE_BITS _u(0x00000006)
#define TIMER_DBGPAUSE_RESET _u(0x00000007)
// -----------------------------------------------------------------------------
// Field : TIMER_DBGPAUSE_DBG1
// Description : Pause when processor 1 is in debug mode
#define TIMER_DBGPAUSE_DBG1_RESET _u(0x1)
#define TIMER_DBGPAUSE_DBG1_BITS _u(0x00000004)
#define TIMER_DBGPAUSE_DBG1_MSB _u(2)
#define TIMER_DBGPAUSE_DBG1_LSB _u(2)
#define TIMER_DBGPAUSE_DBG1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : TIMER_DBGPAUSE_DBG0
// Description : Pause when processor 0 is in debug mode
#define TIMER_DBGPAUSE_DBG0_RESET _u(0x1)
#define TIMER_DBGPAUSE_DBG0_BITS _u(0x00000002)
#define TIMER_DBGPAUSE_DBG0_MSB _u(1)
#define TIMER_DBGPAUSE_DBG0_LSB _u(1)
#define TIMER_DBGPAUSE_DBG0_ACCESS "RW"
// =============================================================================
// Register : TIMER_PAUSE
// Description : Set high to pause the timer
#define TIMER_PAUSE_OFFSET _u(0x00000030)
#define TIMER_PAUSE_BITS _u(0x00000001)
#define TIMER_PAUSE_RESET _u(0x00000000)
#define TIMER_PAUSE_MSB _u(0)
#define TIMER_PAUSE_LSB _u(0)
#define TIMER_PAUSE_ACCESS "RW"
// =============================================================================
// Register : TIMER_LOCKED
// Description : Set locked bit to disable write access to timer Once set,
// cannot be cleared (without a reset)
#define TIMER_LOCKED_OFFSET _u(0x00000034)
#define TIMER_LOCKED_BITS _u(0x00000001)
#define TIMER_LOCKED_RESET _u(0x00000000)
#define TIMER_LOCKED_MSB _u(0)
#define TIMER_LOCKED_LSB _u(0)
#define TIMER_LOCKED_ACCESS "RW"
// =============================================================================
// Register : TIMER_SOURCE
// Description : Selects the source for the timer. Defaults to the normal tick
// configured in the ticks block (typically configured to 1
// microsecond). Writing to 1 will ignore the tick and count
// clk_sys cycles instead.
#define TIMER_SOURCE_OFFSET _u(0x00000038)
#define TIMER_SOURCE_BITS _u(0x00000001)
#define TIMER_SOURCE_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : TIMER_SOURCE_CLK_SYS
// 0x0 -> TICK
// 0x1 -> CLK_SYS
#define TIMER_SOURCE_CLK_SYS_RESET _u(0x0)
#define TIMER_SOURCE_CLK_SYS_BITS _u(0x00000001)
#define TIMER_SOURCE_CLK_SYS_MSB _u(0)
#define TIMER_SOURCE_CLK_SYS_LSB _u(0)
#define TIMER_SOURCE_CLK_SYS_ACCESS "RW"
#define TIMER_SOURCE_CLK_SYS_VALUE_TICK _u(0x0)
#define TIMER_SOURCE_CLK_SYS_VALUE_CLK_SYS _u(0x1)
// =============================================================================
// Register : TIMER_INTR
// Description : Raw Interrupts
#define TIMER_INTR_OFFSET _u(0x0000003c)
#define TIMER_INTR_BITS _u(0x0000000f)
#define TIMER_INTR_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : TIMER_INTR_ALARM_3
#define TIMER_INTR_ALARM_3_RESET _u(0x0)
#define TIMER_INTR_ALARM_3_BITS _u(0x00000008)
#define TIMER_INTR_ALARM_3_MSB _u(3)
#define TIMER_INTR_ALARM_3_LSB _u(3)
#define TIMER_INTR_ALARM_3_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : TIMER_INTR_ALARM_2
#define TIMER_INTR_ALARM_2_RESET _u(0x0)
#define TIMER_INTR_ALARM_2_BITS _u(0x00000004)
#define TIMER_INTR_ALARM_2_MSB _u(2)
#define TIMER_INTR_ALARM_2_LSB _u(2)
#define TIMER_INTR_ALARM_2_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : TIMER_INTR_ALARM_1
#define TIMER_INTR_ALARM_1_RESET _u(0x0)
#define TIMER_INTR_ALARM_1_BITS _u(0x00000002)
#define TIMER_INTR_ALARM_1_MSB _u(1)
#define TIMER_INTR_ALARM_1_LSB _u(1)
#define TIMER_INTR_ALARM_1_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : TIMER_INTR_ALARM_0
#define TIMER_INTR_ALARM_0_RESET _u(0x0)
#define TIMER_INTR_ALARM_0_BITS _u(0x00000001)
#define TIMER_INTR_ALARM_0_MSB _u(0)
#define TIMER_INTR_ALARM_0_LSB _u(0)
#define TIMER_INTR_ALARM_0_ACCESS "WC"
// =============================================================================
// Register : TIMER_INTE
// Description : Interrupt Enable
#define TIMER_INTE_OFFSET _u(0x00000040)
#define TIMER_INTE_BITS _u(0x0000000f)
#define TIMER_INTE_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : TIMER_INTE_ALARM_3
#define TIMER_INTE_ALARM_3_RESET _u(0x0)
#define TIMER_INTE_ALARM_3_BITS _u(0x00000008)
#define TIMER_INTE_ALARM_3_MSB _u(3)
#define TIMER_INTE_ALARM_3_LSB _u(3)
#define TIMER_INTE_ALARM_3_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : TIMER_INTE_ALARM_2
#define TIMER_INTE_ALARM_2_RESET _u(0x0)
#define TIMER_INTE_ALARM_2_BITS _u(0x00000004)
#define TIMER_INTE_ALARM_2_MSB _u(2)
#define TIMER_INTE_ALARM_2_LSB _u(2)
#define TIMER_INTE_ALARM_2_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : TIMER_INTE_ALARM_1
#define TIMER_INTE_ALARM_1_RESET _u(0x0)
#define TIMER_INTE_ALARM_1_BITS _u(0x00000002)
#define TIMER_INTE_ALARM_1_MSB _u(1)
#define TIMER_INTE_ALARM_1_LSB _u(1)
#define TIMER_INTE_ALARM_1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : TIMER_INTE_ALARM_0
#define TIMER_INTE_ALARM_0_RESET _u(0x0)
#define TIMER_INTE_ALARM_0_BITS _u(0x00000001)
#define TIMER_INTE_ALARM_0_MSB _u(0)
#define TIMER_INTE_ALARM_0_LSB _u(0)
#define TIMER_INTE_ALARM_0_ACCESS "RW"
// =============================================================================
// Register : TIMER_INTF
// Description : Interrupt Force
#define TIMER_INTF_OFFSET _u(0x00000044)
#define TIMER_INTF_BITS _u(0x0000000f)
#define TIMER_INTF_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : TIMER_INTF_ALARM_3
#define TIMER_INTF_ALARM_3_RESET _u(0x0)
#define TIMER_INTF_ALARM_3_BITS _u(0x00000008)
#define TIMER_INTF_ALARM_3_MSB _u(3)
#define TIMER_INTF_ALARM_3_LSB _u(3)
#define TIMER_INTF_ALARM_3_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : TIMER_INTF_ALARM_2
#define TIMER_INTF_ALARM_2_RESET _u(0x0)
#define TIMER_INTF_ALARM_2_BITS _u(0x00000004)
#define TIMER_INTF_ALARM_2_MSB _u(2)
#define TIMER_INTF_ALARM_2_LSB _u(2)
#define TIMER_INTF_ALARM_2_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : TIMER_INTF_ALARM_1
#define TIMER_INTF_ALARM_1_RESET _u(0x0)
#define TIMER_INTF_ALARM_1_BITS _u(0x00000002)
#define TIMER_INTF_ALARM_1_MSB _u(1)
#define TIMER_INTF_ALARM_1_LSB _u(1)
#define TIMER_INTF_ALARM_1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : TIMER_INTF_ALARM_0
#define TIMER_INTF_ALARM_0_RESET _u(0x0)
#define TIMER_INTF_ALARM_0_BITS _u(0x00000001)
#define TIMER_INTF_ALARM_0_MSB _u(0)
#define TIMER_INTF_ALARM_0_LSB _u(0)
#define TIMER_INTF_ALARM_0_ACCESS "RW"
// =============================================================================
// Register : TIMER_INTS
// Description : Interrupt status after masking & forcing
#define TIMER_INTS_OFFSET _u(0x00000048)
#define TIMER_INTS_BITS _u(0x0000000f)
#define TIMER_INTS_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : TIMER_INTS_ALARM_3
#define TIMER_INTS_ALARM_3_RESET _u(0x0)
#define TIMER_INTS_ALARM_3_BITS _u(0x00000008)
#define TIMER_INTS_ALARM_3_MSB _u(3)
#define TIMER_INTS_ALARM_3_LSB _u(3)
#define TIMER_INTS_ALARM_3_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : TIMER_INTS_ALARM_2
#define TIMER_INTS_ALARM_2_RESET _u(0x0)
#define TIMER_INTS_ALARM_2_BITS _u(0x00000004)
#define TIMER_INTS_ALARM_2_MSB _u(2)
#define TIMER_INTS_ALARM_2_LSB _u(2)
#define TIMER_INTS_ALARM_2_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : TIMER_INTS_ALARM_1
#define TIMER_INTS_ALARM_1_RESET _u(0x0)
#define TIMER_INTS_ALARM_1_BITS _u(0x00000002)
#define TIMER_INTS_ALARM_1_MSB _u(1)
#define TIMER_INTS_ALARM_1_LSB _u(1)
#define TIMER_INTS_ALARM_1_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : TIMER_INTS_ALARM_0
#define TIMER_INTS_ALARM_0_RESET _u(0x0)
#define TIMER_INTS_ALARM_0_BITS _u(0x00000001)
#define TIMER_INTS_ALARM_0_MSB _u(0)
#define TIMER_INTS_ALARM_0_LSB _u(0)
#define TIMER_INTS_ALARM_0_ACCESS "RO"
// =============================================================================
#endif // _HARDWARE_REGS_TIMER_H

625
arch/arm/src/rp23xx/hardware/regs/trng.h
View file

@ -1,625 +0,0 @@
// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
// =============================================================================
// Register block : TRNG
// Version : 1
// Bus type : apb
// Description : ARM TrustZone RNG register block
// =============================================================================
#ifndef _HARDWARE_REGS_TRNG_H
#define _HARDWARE_REGS_TRNG_H
// =============================================================================
// Register : TRNG_RNG_IMR
// Description : Interrupt masking.
#define TRNG_RNG_IMR_OFFSET _u(0x00000100)
#define TRNG_RNG_IMR_BITS _u(0xffffffff)
#define TRNG_RNG_IMR_RESET _u(0x0000000f)
// -----------------------------------------------------------------------------
// Field : TRNG_RNG_IMR_RESERVED
// Description : RESERVED
#define TRNG_RNG_IMR_RESERVED_RESET _u(0x0000000)
#define TRNG_RNG_IMR_RESERVED_BITS _u(0xfffffff0)
#define TRNG_RNG_IMR_RESERVED_MSB _u(31)
#define TRNG_RNG_IMR_RESERVED_LSB _u(4)
#define TRNG_RNG_IMR_RESERVED_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : TRNG_RNG_IMR_VN_ERR_INT_MASK
// Description : 1'b1-mask interrupt, no interrupt will be generated. See
// RNG_ISR for an explanation on this interrupt.
#define TRNG_RNG_IMR_VN_ERR_INT_MASK_RESET _u(0x1)
#define TRNG_RNG_IMR_VN_ERR_INT_MASK_BITS _u(0x00000008)
#define TRNG_RNG_IMR_VN_ERR_INT_MASK_MSB _u(3)
#define TRNG_RNG_IMR_VN_ERR_INT_MASK_LSB _u(3)
#define TRNG_RNG_IMR_VN_ERR_INT_MASK_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : TRNG_RNG_IMR_CRNGT_ERR_INT_MASK
// Description : 1'b1-mask interrupt, no interrupt will be generated. See
// RNG_ISR for an explanation on this interrupt.
#define TRNG_RNG_IMR_CRNGT_ERR_INT_MASK_RESET _u(0x1)
#define TRNG_RNG_IMR_CRNGT_ERR_INT_MASK_BITS _u(0x00000004)
#define TRNG_RNG_IMR_CRNGT_ERR_INT_MASK_MSB _u(2)
#define TRNG_RNG_IMR_CRNGT_ERR_INT_MASK_LSB _u(2)
#define TRNG_RNG_IMR_CRNGT_ERR_INT_MASK_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : TRNG_RNG_IMR_AUTOCORR_ERR_INT_MASK
// Description : 1'b1-mask interrupt, no interrupt will be generated. See
// RNG_ISR for an explanation on this interrupt.
#define TRNG_RNG_IMR_AUTOCORR_ERR_INT_MASK_RESET _u(0x1)
#define TRNG_RNG_IMR_AUTOCORR_ERR_INT_MASK_BITS _u(0x00000002)
#define TRNG_RNG_IMR_AUTOCORR_ERR_INT_MASK_MSB _u(1)
#define TRNG_RNG_IMR_AUTOCORR_ERR_INT_MASK_LSB _u(1)
#define TRNG_RNG_IMR_AUTOCORR_ERR_INT_MASK_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : TRNG_RNG_IMR_EHR_VALID_INT_MASK
// Description : 1'b1-mask interrupt, no interrupt will be generated. See
// RNG_ISR for an explanation on this interrupt.
#define TRNG_RNG_IMR_EHR_VALID_INT_MASK_RESET _u(0x1)
#define TRNG_RNG_IMR_EHR_VALID_INT_MASK_BITS _u(0x00000001)
#define TRNG_RNG_IMR_EHR_VALID_INT_MASK_MSB _u(0)
#define TRNG_RNG_IMR_EHR_VALID_INT_MASK_LSB _u(0)
#define TRNG_RNG_IMR_EHR_VALID_INT_MASK_ACCESS "RW"
// =============================================================================
// Register : TRNG_RNG_ISR
// Description : RNG status register. If corresponding RNG_IMR bit is unmasked,
// an interrupt will be generated.
#define TRNG_RNG_ISR_OFFSET _u(0x00000104)
#define TRNG_RNG_ISR_BITS _u(0xffffffff)
#define TRNG_RNG_ISR_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : TRNG_RNG_ISR_RESERVED
// Description : RESERVED
#define TRNG_RNG_ISR_RESERVED_RESET _u(0x0000000)
#define TRNG_RNG_ISR_RESERVED_BITS _u(0xfffffff0)
#define TRNG_RNG_ISR_RESERVED_MSB _u(31)
#define TRNG_RNG_ISR_RESERVED_LSB _u(4)
#define TRNG_RNG_ISR_RESERVED_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : TRNG_RNG_ISR_VN_ERR
// Description : 1'b1 indicates Von Neuman error. Error in von Neuman occurs if
// 32 consecutive collected bits are identical, ZERO or ONE.
#define TRNG_RNG_ISR_VN_ERR_RESET _u(0x0)
#define TRNG_RNG_ISR_VN_ERR_BITS _u(0x00000008)
#define TRNG_RNG_ISR_VN_ERR_MSB _u(3)
#define TRNG_RNG_ISR_VN_ERR_LSB _u(3)
#define TRNG_RNG_ISR_VN_ERR_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : TRNG_RNG_ISR_CRNGT_ERR
// Description : 1'b1 indicates CRNGT in the RNG test failed. Failure occurs
// when two consecutive blocks of 16 collected bits are equal.
#define TRNG_RNG_ISR_CRNGT_ERR_RESET _u(0x0)
#define TRNG_RNG_ISR_CRNGT_ERR_BITS _u(0x00000004)
#define TRNG_RNG_ISR_CRNGT_ERR_MSB _u(2)
#define TRNG_RNG_ISR_CRNGT_ERR_LSB _u(2)
#define TRNG_RNG_ISR_CRNGT_ERR_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : TRNG_RNG_ISR_AUTOCORR_ERR
// Description : 1'b1 indicates Autocorrelation test failed four times in a row.
// When set, RNG cease from functioning until next reset.
#define TRNG_RNG_ISR_AUTOCORR_ERR_RESET _u(0x0)
#define TRNG_RNG_ISR_AUTOCORR_ERR_BITS _u(0x00000002)
#define TRNG_RNG_ISR_AUTOCORR_ERR_MSB _u(1)
#define TRNG_RNG_ISR_AUTOCORR_ERR_LSB _u(1)
#define TRNG_RNG_ISR_AUTOCORR_ERR_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : TRNG_RNG_ISR_EHR_VALID
// Description : 1'b1 indicates that 192 bits have been collected in the RNG,
// and are ready to be read.
#define TRNG_RNG_ISR_EHR_VALID_RESET _u(0x0)
#define TRNG_RNG_ISR_EHR_VALID_BITS _u(0x00000001)
#define TRNG_RNG_ISR_EHR_VALID_MSB _u(0)
#define TRNG_RNG_ISR_EHR_VALID_LSB _u(0)
#define TRNG_RNG_ISR_EHR_VALID_ACCESS "RO"
// =============================================================================
// Register : TRNG_RNG_ICR
// Description : Interrupt/status bit clear Register.
#define TRNG_RNG_ICR_OFFSET _u(0x00000108)
#define TRNG_RNG_ICR_BITS _u(0xffffffff)
#define TRNG_RNG_ICR_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : TRNG_RNG_ICR_RESERVED
// Description : RESERVED
#define TRNG_RNG_ICR_RESERVED_RESET _u(0x0000000)
#define TRNG_RNG_ICR_RESERVED_BITS _u(0xfffffff0)
#define TRNG_RNG_ICR_RESERVED_MSB _u(31)
#define TRNG_RNG_ICR_RESERVED_LSB _u(4)
#define TRNG_RNG_ICR_RESERVED_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : TRNG_RNG_ICR_VN_ERR
// Description : Write 1'b1 - clear corresponding bit in RNG_ISR.
#define TRNG_RNG_ICR_VN_ERR_RESET _u(0x0)
#define TRNG_RNG_ICR_VN_ERR_BITS _u(0x00000008)
#define TRNG_RNG_ICR_VN_ERR_MSB _u(3)
#define TRNG_RNG_ICR_VN_ERR_LSB _u(3)
#define TRNG_RNG_ICR_VN_ERR_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : TRNG_RNG_ICR_CRNGT_ERR
// Description : Write 1'b1 - clear corresponding bit in RNG_ISR.
#define TRNG_RNG_ICR_CRNGT_ERR_RESET _u(0x0)
#define TRNG_RNG_ICR_CRNGT_ERR_BITS _u(0x00000004)
#define TRNG_RNG_ICR_CRNGT_ERR_MSB _u(2)
#define TRNG_RNG_ICR_CRNGT_ERR_LSB _u(2)
#define TRNG_RNG_ICR_CRNGT_ERR_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : TRNG_RNG_ICR_AUTOCORR_ERR
// Description : Cannot be cleared by SW! Only RNG reset clears this bit.
#define TRNG_RNG_ICR_AUTOCORR_ERR_RESET _u(0x0)
#define TRNG_RNG_ICR_AUTOCORR_ERR_BITS _u(0x00000002)
#define TRNG_RNG_ICR_AUTOCORR_ERR_MSB _u(1)
#define TRNG_RNG_ICR_AUTOCORR_ERR_LSB _u(1)
#define TRNG_RNG_ICR_AUTOCORR_ERR_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : TRNG_RNG_ICR_EHR_VALID
// Description : Write 1'b1 - clear corresponding bit in RNG_ISR.
#define TRNG_RNG_ICR_EHR_VALID_RESET _u(0x0)
#define TRNG_RNG_ICR_EHR_VALID_BITS _u(0x00000001)
#define TRNG_RNG_ICR_EHR_VALID_MSB _u(0)
#define TRNG_RNG_ICR_EHR_VALID_LSB _u(0)
#define TRNG_RNG_ICR_EHR_VALID_ACCESS "RW"
// =============================================================================
// Register : TRNG_TRNG_CONFIG
// Description : Selecting the inverter-chain length.
#define TRNG_TRNG_CONFIG_OFFSET _u(0x0000010c)
#define TRNG_TRNG_CONFIG_BITS _u(0xffffffff)
#define TRNG_TRNG_CONFIG_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : TRNG_TRNG_CONFIG_RESERVED
// Description : RESERVED
#define TRNG_TRNG_CONFIG_RESERVED_RESET _u(0x00000000)
#define TRNG_TRNG_CONFIG_RESERVED_BITS _u(0xfffffffc)
#define TRNG_TRNG_CONFIG_RESERVED_MSB _u(31)
#define TRNG_TRNG_CONFIG_RESERVED_LSB _u(2)
#define TRNG_TRNG_CONFIG_RESERVED_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : TRNG_TRNG_CONFIG_RND_SRC_SEL
// Description : Selects the number of inverters (out of four possible
// selections) in the ring oscillator (the entropy source).
#define TRNG_TRNG_CONFIG_RND_SRC_SEL_RESET _u(0x0)
#define TRNG_TRNG_CONFIG_RND_SRC_SEL_BITS _u(0x00000003)
#define TRNG_TRNG_CONFIG_RND_SRC_SEL_MSB _u(1)
#define TRNG_TRNG_CONFIG_RND_SRC_SEL_LSB _u(0)
#define TRNG_TRNG_CONFIG_RND_SRC_SEL_ACCESS "RW"
// =============================================================================
// Register : TRNG_TRNG_VALID
// Description : 192 bit collection indication.
#define TRNG_TRNG_VALID_OFFSET _u(0x00000110)
#define TRNG_TRNG_VALID_BITS _u(0xffffffff)
#define TRNG_TRNG_VALID_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : TRNG_TRNG_VALID_RESERVED
// Description : RESERVED
#define TRNG_TRNG_VALID_RESERVED_RESET _u(0x00000000)
#define TRNG_TRNG_VALID_RESERVED_BITS _u(0xfffffffe)
#define TRNG_TRNG_VALID_RESERVED_MSB _u(31)
#define TRNG_TRNG_VALID_RESERVED_LSB _u(1)
#define TRNG_TRNG_VALID_RESERVED_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : TRNG_TRNG_VALID_EHR_VALID
// Description : 1'b1 indicates that collection of bits in the RNG is completed,
// and data can be read from EHR_DATA register.
#define TRNG_TRNG_VALID_EHR_VALID_RESET _u(0x0)
#define TRNG_TRNG_VALID_EHR_VALID_BITS _u(0x00000001)
#define TRNG_TRNG_VALID_EHR_VALID_MSB _u(0)
#define TRNG_TRNG_VALID_EHR_VALID_LSB _u(0)
#define TRNG_TRNG_VALID_EHR_VALID_ACCESS "RO"
// =============================================================================
// Register : TRNG_EHR_DATA0
// Description : RNG collected bits.
// Bits [31:0] of Entropy Holding Register (EHR) - RNG output
// register
#define TRNG_EHR_DATA0_OFFSET _u(0x00000114)
#define TRNG_EHR_DATA0_BITS _u(0xffffffff)
#define TRNG_EHR_DATA0_RESET _u(0x00000000)
#define TRNG_EHR_DATA0_MSB _u(31)
#define TRNG_EHR_DATA0_LSB _u(0)
#define TRNG_EHR_DATA0_ACCESS "RO"
// =============================================================================
// Register : TRNG_EHR_DATA1
// Description : RNG collected bits.
// Bits [63:32] of Entropy Holding Register (EHR) - RNG output
// register
#define TRNG_EHR_DATA1_OFFSET _u(0x00000118)
#define TRNG_EHR_DATA1_BITS _u(0xffffffff)
#define TRNG_EHR_DATA1_RESET _u(0x00000000)
#define TRNG_EHR_DATA1_MSB _u(31)
#define TRNG_EHR_DATA1_LSB _u(0)
#define TRNG_EHR_DATA1_ACCESS "RO"
// =============================================================================
// Register : TRNG_EHR_DATA2
// Description : RNG collected bits.
// Bits [95:64] of Entropy Holding Register (EHR) - RNG output
// register
#define TRNG_EHR_DATA2_OFFSET _u(0x0000011c)
#define TRNG_EHR_DATA2_BITS _u(0xffffffff)
#define TRNG_EHR_DATA2_RESET _u(0x00000000)
#define TRNG_EHR_DATA2_MSB _u(31)
#define TRNG_EHR_DATA2_LSB _u(0)
#define TRNG_EHR_DATA2_ACCESS "RO"
// =============================================================================
// Register : TRNG_EHR_DATA3
// Description : RNG collected bits.
// Bits [127:96] of Entropy Holding Register (EHR) - RNG output
// register
#define TRNG_EHR_DATA3_OFFSET _u(0x00000120)
#define TRNG_EHR_DATA3_BITS _u(0xffffffff)
#define TRNG_EHR_DATA3_RESET _u(0x00000000)
#define TRNG_EHR_DATA3_MSB _u(31)
#define TRNG_EHR_DATA3_LSB _u(0)
#define TRNG_EHR_DATA3_ACCESS "RO"
// =============================================================================
// Register : TRNG_EHR_DATA4
// Description : RNG collected bits.
// Bits [159:128] of Entropy Holding Register (EHR) - RNG output
// register
#define TRNG_EHR_DATA4_OFFSET _u(0x00000124)
#define TRNG_EHR_DATA4_BITS _u(0xffffffff)
#define TRNG_EHR_DATA4_RESET _u(0x00000000)
#define TRNG_EHR_DATA4_MSB _u(31)
#define TRNG_EHR_DATA4_LSB _u(0)
#define TRNG_EHR_DATA4_ACCESS "RO"
// =============================================================================
// Register : TRNG_EHR_DATA5
// Description : RNG collected bits.
// Bits [191:160] of Entropy Holding Register (EHR) - RNG output
// register
#define TRNG_EHR_DATA5_OFFSET _u(0x00000128)
#define TRNG_EHR_DATA5_BITS _u(0xffffffff)
#define TRNG_EHR_DATA5_RESET _u(0x00000000)
#define TRNG_EHR_DATA5_MSB _u(31)
#define TRNG_EHR_DATA5_LSB _u(0)
#define TRNG_EHR_DATA5_ACCESS "RO"
// =============================================================================
// Register : TRNG_RND_SOURCE_ENABLE
// Description : Enable signal for the random source.
#define TRNG_RND_SOURCE_ENABLE_OFFSET _u(0x0000012c)
#define TRNG_RND_SOURCE_ENABLE_BITS _u(0xffffffff)
#define TRNG_RND_SOURCE_ENABLE_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : TRNG_RND_SOURCE_ENABLE_RESERVED
// Description : RESERVED
#define TRNG_RND_SOURCE_ENABLE_RESERVED_RESET _u(0x00000000)
#define TRNG_RND_SOURCE_ENABLE_RESERVED_BITS _u(0xfffffffe)
#define TRNG_RND_SOURCE_ENABLE_RESERVED_MSB _u(31)
#define TRNG_RND_SOURCE_ENABLE_RESERVED_LSB _u(1)
#define TRNG_RND_SOURCE_ENABLE_RESERVED_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : TRNG_RND_SOURCE_ENABLE_RND_SRC_EN
// Description : * 1'b1 - entropy source is enabled. *1'b0 - entropy source is
// disabled
#define TRNG_RND_SOURCE_ENABLE_RND_SRC_EN_RESET _u(0x0)
#define TRNG_RND_SOURCE_ENABLE_RND_SRC_EN_BITS _u(0x00000001)
#define TRNG_RND_SOURCE_ENABLE_RND_SRC_EN_MSB _u(0)
#define TRNG_RND_SOURCE_ENABLE_RND_SRC_EN_LSB _u(0)
#define TRNG_RND_SOURCE_ENABLE_RND_SRC_EN_ACCESS "RW"
// =============================================================================
// Register : TRNG_SAMPLE_CNT1
// Description : Counts clocks between sampling of random bit.
#define TRNG_SAMPLE_CNT1_OFFSET _u(0x00000130)
#define TRNG_SAMPLE_CNT1_BITS _u(0xffffffff)
#define TRNG_SAMPLE_CNT1_RESET _u(0x0000ffff)
// -----------------------------------------------------------------------------
// Field : TRNG_SAMPLE_CNT1_SAMPLE_CNTR1
// Description : Sets the number of rng_clk cycles between two consecutive ring
// oscillator samples. Note! If the Von-Neuman is bypassed, the
// minimum value for sample counter must not be less then decimal
// seventeen
#define TRNG_SAMPLE_CNT1_SAMPLE_CNTR1_RESET _u(0x0000ffff)
#define TRNG_SAMPLE_CNT1_SAMPLE_CNTR1_BITS _u(0xffffffff)
#define TRNG_SAMPLE_CNT1_SAMPLE_CNTR1_MSB _u(31)
#define TRNG_SAMPLE_CNT1_SAMPLE_CNTR1_LSB _u(0)
#define TRNG_SAMPLE_CNT1_SAMPLE_CNTR1_ACCESS "RW"
// =============================================================================
// Register : TRNG_AUTOCORR_STATISTIC
// Description : Statistic about Autocorrelation test activations.
#define TRNG_AUTOCORR_STATISTIC_OFFSET _u(0x00000134)
#define TRNG_AUTOCORR_STATISTIC_BITS _u(0xffffffff)
#define TRNG_AUTOCORR_STATISTIC_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : TRNG_AUTOCORR_STATISTIC_RESERVED
// Description : RESERVED
#define TRNG_AUTOCORR_STATISTIC_RESERVED_RESET _u(0x000)
#define TRNG_AUTOCORR_STATISTIC_RESERVED_BITS _u(0xffc00000)
#define TRNG_AUTOCORR_STATISTIC_RESERVED_MSB _u(31)
#define TRNG_AUTOCORR_STATISTIC_RESERVED_LSB _u(22)
#define TRNG_AUTOCORR_STATISTIC_RESERVED_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : TRNG_AUTOCORR_STATISTIC_AUTOCORR_FAILS
// Description : Count each time an autocorrelation test fails. Any write to the
// register reset the counter. Stop collecting statistic if one of
// the counters reached the limit.
#define TRNG_AUTOCORR_STATISTIC_AUTOCORR_FAILS_RESET _u(0x00)
#define TRNG_AUTOCORR_STATISTIC_AUTOCORR_FAILS_BITS _u(0x003fc000)
#define TRNG_AUTOCORR_STATISTIC_AUTOCORR_FAILS_MSB _u(21)
#define TRNG_AUTOCORR_STATISTIC_AUTOCORR_FAILS_LSB _u(14)
#define TRNG_AUTOCORR_STATISTIC_AUTOCORR_FAILS_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : TRNG_AUTOCORR_STATISTIC_AUTOCORR_TRYS
// Description : Count each time an autocorrelation test starts. Any write to
// the register reset the counter. Stop collecting statistic if
// one of the counters reached the limit.
#define TRNG_AUTOCORR_STATISTIC_AUTOCORR_TRYS_RESET _u(0x0000)
#define TRNG_AUTOCORR_STATISTIC_AUTOCORR_TRYS_BITS _u(0x00003fff)
#define TRNG_AUTOCORR_STATISTIC_AUTOCORR_TRYS_MSB _u(13)
#define TRNG_AUTOCORR_STATISTIC_AUTOCORR_TRYS_LSB _u(0)
#define TRNG_AUTOCORR_STATISTIC_AUTOCORR_TRYS_ACCESS "RW"
// =============================================================================
// Register : TRNG_TRNG_DEBUG_CONTROL
// Description : Debug register.
#define TRNG_TRNG_DEBUG_CONTROL_OFFSET _u(0x00000138)
#define TRNG_TRNG_DEBUG_CONTROL_BITS _u(0x0000000f)
#define TRNG_TRNG_DEBUG_CONTROL_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : TRNG_TRNG_DEBUG_CONTROL_AUTO_CORRELATE_BYPASS
// Description : When set, the autocorrelation test in the TRNG module is
// bypassed.
#define TRNG_TRNG_DEBUG_CONTROL_AUTO_CORRELATE_BYPASS_RESET _u(0x0)
#define TRNG_TRNG_DEBUG_CONTROL_AUTO_CORRELATE_BYPASS_BITS _u(0x00000008)
#define TRNG_TRNG_DEBUG_CONTROL_AUTO_CORRELATE_BYPASS_MSB _u(3)
#define TRNG_TRNG_DEBUG_CONTROL_AUTO_CORRELATE_BYPASS_LSB _u(3)
#define TRNG_TRNG_DEBUG_CONTROL_AUTO_CORRELATE_BYPASS_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : TRNG_TRNG_DEBUG_CONTROL_TRNG_CRNGT_BYPASS
// Description : When set, the CRNGT test in the RNG is bypassed.
#define TRNG_TRNG_DEBUG_CONTROL_TRNG_CRNGT_BYPASS_RESET _u(0x0)
#define TRNG_TRNG_DEBUG_CONTROL_TRNG_CRNGT_BYPASS_BITS _u(0x00000004)
#define TRNG_TRNG_DEBUG_CONTROL_TRNG_CRNGT_BYPASS_MSB _u(2)
#define TRNG_TRNG_DEBUG_CONTROL_TRNG_CRNGT_BYPASS_LSB _u(2)
#define TRNG_TRNG_DEBUG_CONTROL_TRNG_CRNGT_BYPASS_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : TRNG_TRNG_DEBUG_CONTROL_VNC_BYPASS
// Description : When set, the Von-Neuman balancer is bypassed (including the 32
// consecutive bits test).
#define TRNG_TRNG_DEBUG_CONTROL_VNC_BYPASS_RESET _u(0x0)
#define TRNG_TRNG_DEBUG_CONTROL_VNC_BYPASS_BITS _u(0x00000002)
#define TRNG_TRNG_DEBUG_CONTROL_VNC_BYPASS_MSB _u(1)
#define TRNG_TRNG_DEBUG_CONTROL_VNC_BYPASS_LSB _u(1)
#define TRNG_TRNG_DEBUG_CONTROL_VNC_BYPASS_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : TRNG_TRNG_DEBUG_CONTROL_RESERVED
// Description : N/A
#define TRNG_TRNG_DEBUG_CONTROL_RESERVED_RESET _u(0x0)
#define TRNG_TRNG_DEBUG_CONTROL_RESERVED_BITS _u(0x00000001)
#define TRNG_TRNG_DEBUG_CONTROL_RESERVED_MSB _u(0)
#define TRNG_TRNG_DEBUG_CONTROL_RESERVED_LSB _u(0)
#define TRNG_TRNG_DEBUG_CONTROL_RESERVED_ACCESS "RO"
// =============================================================================
// Register : TRNG_TRNG_SW_RESET
// Description : Generate internal SW reset within the RNG block.
#define TRNG_TRNG_SW_RESET_OFFSET _u(0x00000140)
#define TRNG_TRNG_SW_RESET_BITS _u(0xffffffff)
#define TRNG_TRNG_SW_RESET_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : TRNG_TRNG_SW_RESET_RESERVED
// Description : RESERVED
#define TRNG_TRNG_SW_RESET_RESERVED_RESET _u(0x00000000)
#define TRNG_TRNG_SW_RESET_RESERVED_BITS _u(0xfffffffe)
#define TRNG_TRNG_SW_RESET_RESERVED_MSB _u(31)
#define TRNG_TRNG_SW_RESET_RESERVED_LSB _u(1)
#define TRNG_TRNG_SW_RESET_RESERVED_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : TRNG_TRNG_SW_RESET_TRNG_SW_RESET
// Description : Writing 1'b1 to this register causes an internal RNG reset.
#define TRNG_TRNG_SW_RESET_TRNG_SW_RESET_RESET _u(0x0)
#define TRNG_TRNG_SW_RESET_TRNG_SW_RESET_BITS _u(0x00000001)
#define TRNG_TRNG_SW_RESET_TRNG_SW_RESET_MSB _u(0)
#define TRNG_TRNG_SW_RESET_TRNG_SW_RESET_LSB _u(0)
#define TRNG_TRNG_SW_RESET_TRNG_SW_RESET_ACCESS "RW"
// =============================================================================
// Register : TRNG_RNG_DEBUG_EN_INPUT
// Description : Enable the RNG debug mode
#define TRNG_RNG_DEBUG_EN_INPUT_OFFSET _u(0x000001b4)
#define TRNG_RNG_DEBUG_EN_INPUT_BITS _u(0xffffffff)
#define TRNG_RNG_DEBUG_EN_INPUT_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : TRNG_RNG_DEBUG_EN_INPUT_RESERVED
// Description : RESERVED
#define TRNG_RNG_DEBUG_EN_INPUT_RESERVED_RESET _u(0x00000000)
#define TRNG_RNG_DEBUG_EN_INPUT_RESERVED_BITS _u(0xfffffffe)
#define TRNG_RNG_DEBUG_EN_INPUT_RESERVED_MSB _u(31)
#define TRNG_RNG_DEBUG_EN_INPUT_RESERVED_LSB _u(1)
#define TRNG_RNG_DEBUG_EN_INPUT_RESERVED_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : TRNG_RNG_DEBUG_EN_INPUT_RNG_DEBUG_EN
// Description : * 1'b1 - debug mode is enabled. *1'b0 - debug mode is disabled
#define TRNG_RNG_DEBUG_EN_INPUT_RNG_DEBUG_EN_RESET _u(0x0)
#define TRNG_RNG_DEBUG_EN_INPUT_RNG_DEBUG_EN_BITS _u(0x00000001)
#define TRNG_RNG_DEBUG_EN_INPUT_RNG_DEBUG_EN_MSB _u(0)
#define TRNG_RNG_DEBUG_EN_INPUT_RNG_DEBUG_EN_LSB _u(0)
#define TRNG_RNG_DEBUG_EN_INPUT_RNG_DEBUG_EN_ACCESS "RW"
// =============================================================================
// Register : TRNG_TRNG_BUSY
// Description : RNG Busy indication.
#define TRNG_TRNG_BUSY_OFFSET _u(0x000001b8)
#define TRNG_TRNG_BUSY_BITS _u(0xffffffff)
#define TRNG_TRNG_BUSY_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : TRNG_TRNG_BUSY_RESERVED
// Description : RESERVED
#define TRNG_TRNG_BUSY_RESERVED_RESET _u(0x00000000)
#define TRNG_TRNG_BUSY_RESERVED_BITS _u(0xfffffffe)
#define TRNG_TRNG_BUSY_RESERVED_MSB _u(31)
#define TRNG_TRNG_BUSY_RESERVED_LSB _u(1)
#define TRNG_TRNG_BUSY_RESERVED_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : TRNG_TRNG_BUSY_TRNG_BUSY
// Description : Reflects rng_busy status.
#define TRNG_TRNG_BUSY_TRNG_BUSY_RESET _u(0x0)
#define TRNG_TRNG_BUSY_TRNG_BUSY_BITS _u(0x00000001)
#define TRNG_TRNG_BUSY_TRNG_BUSY_MSB _u(0)
#define TRNG_TRNG_BUSY_TRNG_BUSY_LSB _u(0)
#define TRNG_TRNG_BUSY_TRNG_BUSY_ACCESS "RO"
// =============================================================================
// Register : TRNG_RST_BITS_COUNTER
// Description : Reset the counter of collected bits in the RNG.
#define TRNG_RST_BITS_COUNTER_OFFSET _u(0x000001bc)
#define TRNG_RST_BITS_COUNTER_BITS _u(0xffffffff)
#define TRNG_RST_BITS_COUNTER_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : TRNG_RST_BITS_COUNTER_RESERVED
// Description : RESERVED
#define TRNG_RST_BITS_COUNTER_RESERVED_RESET _u(0x00000000)
#define TRNG_RST_BITS_COUNTER_RESERVED_BITS _u(0xfffffffe)
#define TRNG_RST_BITS_COUNTER_RESERVED_MSB _u(31)
#define TRNG_RST_BITS_COUNTER_RESERVED_LSB _u(1)
#define TRNG_RST_BITS_COUNTER_RESERVED_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : TRNG_RST_BITS_COUNTER_RST_BITS_COUNTER
// Description : Writing any value to this address will reset the bits counter
// and RNG valid registers. RND_SORCE_ENABLE register must be
// unset in order for the reset to take place.
#define TRNG_RST_BITS_COUNTER_RST_BITS_COUNTER_RESET _u(0x0)
#define TRNG_RST_BITS_COUNTER_RST_BITS_COUNTER_BITS _u(0x00000001)
#define TRNG_RST_BITS_COUNTER_RST_BITS_COUNTER_MSB _u(0)
#define TRNG_RST_BITS_COUNTER_RST_BITS_COUNTER_LSB _u(0)
#define TRNG_RST_BITS_COUNTER_RST_BITS_COUNTER_ACCESS "RW"
// =============================================================================
// Register : TRNG_RNG_VERSION
// Description : Displays the version settings of the TRNG.
#define TRNG_RNG_VERSION_OFFSET _u(0x000001c0)
#define TRNG_RNG_VERSION_BITS _u(0xffffffff)
#define TRNG_RNG_VERSION_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : TRNG_RNG_VERSION_RESERVED
// Description : RESERVED
#define TRNG_RNG_VERSION_RESERVED_RESET _u(0x000000)
#define TRNG_RNG_VERSION_RESERVED_BITS _u(0xffffff00)
#define TRNG_RNG_VERSION_RESERVED_MSB _u(31)
#define TRNG_RNG_VERSION_RESERVED_LSB _u(8)
#define TRNG_RNG_VERSION_RESERVED_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : TRNG_RNG_VERSION_RNG_USE_5_SBOXES
// Description : * 1'b1 - 5 SBOX AES. *1'b0 - 20 SBOX AES
#define TRNG_RNG_VERSION_RNG_USE_5_SBOXES_RESET _u(0x0)
#define TRNG_RNG_VERSION_RNG_USE_5_SBOXES_BITS _u(0x00000080)
#define TRNG_RNG_VERSION_RNG_USE_5_SBOXES_MSB _u(7)
#define TRNG_RNG_VERSION_RNG_USE_5_SBOXES_LSB _u(7)
#define TRNG_RNG_VERSION_RNG_USE_5_SBOXES_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : TRNG_RNG_VERSION_RESEEDING_EXISTS
// Description : * 1'b1 - Exists. *1'b0 - Does not exist
#define TRNG_RNG_VERSION_RESEEDING_EXISTS_RESET _u(0x0)
#define TRNG_RNG_VERSION_RESEEDING_EXISTS_BITS _u(0x00000040)
#define TRNG_RNG_VERSION_RESEEDING_EXISTS_MSB _u(6)
#define TRNG_RNG_VERSION_RESEEDING_EXISTS_LSB _u(6)
#define TRNG_RNG_VERSION_RESEEDING_EXISTS_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : TRNG_RNG_VERSION_KAT_EXISTS
// Description : * 1'b1 - Exists. *1'b0 - Does not exist
#define TRNG_RNG_VERSION_KAT_EXISTS_RESET _u(0x0)
#define TRNG_RNG_VERSION_KAT_EXISTS_BITS _u(0x00000020)
#define TRNG_RNG_VERSION_KAT_EXISTS_MSB _u(5)
#define TRNG_RNG_VERSION_KAT_EXISTS_LSB _u(5)
#define TRNG_RNG_VERSION_KAT_EXISTS_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : TRNG_RNG_VERSION_PRNG_EXISTS
// Description : * 1'b1 - Exists. *1'b0 - Does not exist
#define TRNG_RNG_VERSION_PRNG_EXISTS_RESET _u(0x0)
#define TRNG_RNG_VERSION_PRNG_EXISTS_BITS _u(0x00000010)
#define TRNG_RNG_VERSION_PRNG_EXISTS_MSB _u(4)
#define TRNG_RNG_VERSION_PRNG_EXISTS_LSB _u(4)
#define TRNG_RNG_VERSION_PRNG_EXISTS_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : TRNG_RNG_VERSION_TRNG_TESTS_BYPASS_EN
// Description : * 1'b1 - Exists. *1'b0 - Does not exist
#define TRNG_RNG_VERSION_TRNG_TESTS_BYPASS_EN_RESET _u(0x0)
#define TRNG_RNG_VERSION_TRNG_TESTS_BYPASS_EN_BITS _u(0x00000008)
#define TRNG_RNG_VERSION_TRNG_TESTS_BYPASS_EN_MSB _u(3)
#define TRNG_RNG_VERSION_TRNG_TESTS_BYPASS_EN_LSB _u(3)
#define TRNG_RNG_VERSION_TRNG_TESTS_BYPASS_EN_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : TRNG_RNG_VERSION_AUTOCORR_EXISTS
// Description : * 1'b1 - Exists. *1'b0 - Does not exist
#define TRNG_RNG_VERSION_AUTOCORR_EXISTS_RESET _u(0x0)
#define TRNG_RNG_VERSION_AUTOCORR_EXISTS_BITS _u(0x00000004)
#define TRNG_RNG_VERSION_AUTOCORR_EXISTS_MSB _u(2)
#define TRNG_RNG_VERSION_AUTOCORR_EXISTS_LSB _u(2)
#define TRNG_RNG_VERSION_AUTOCORR_EXISTS_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : TRNG_RNG_VERSION_CRNGT_EXISTS
// Description : * 1'b1 - Exists. *1'b0 - Does not exist
#define TRNG_RNG_VERSION_CRNGT_EXISTS_RESET _u(0x0)
#define TRNG_RNG_VERSION_CRNGT_EXISTS_BITS _u(0x00000002)
#define TRNG_RNG_VERSION_CRNGT_EXISTS_MSB _u(1)
#define TRNG_RNG_VERSION_CRNGT_EXISTS_LSB _u(1)
#define TRNG_RNG_VERSION_CRNGT_EXISTS_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : TRNG_RNG_VERSION_EHR_WIDTH_192
// Description : * 1'b1 - 192-bit EHR. *1'b0 - 128-bit EHR
#define TRNG_RNG_VERSION_EHR_WIDTH_192_RESET _u(0x0)
#define TRNG_RNG_VERSION_EHR_WIDTH_192_BITS _u(0x00000001)
#define TRNG_RNG_VERSION_EHR_WIDTH_192_MSB _u(0)
#define TRNG_RNG_VERSION_EHR_WIDTH_192_LSB _u(0)
#define TRNG_RNG_VERSION_EHR_WIDTH_192_ACCESS "RO"
// =============================================================================
// Register : TRNG_RNG_BIST_CNTR_0
// Description : Collected BIST results.
#define TRNG_RNG_BIST_CNTR_0_OFFSET _u(0x000001e0)
#define TRNG_RNG_BIST_CNTR_0_BITS _u(0xffffffff)
#define TRNG_RNG_BIST_CNTR_0_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : TRNG_RNG_BIST_CNTR_0_RESERVED
// Description : RESERVED
#define TRNG_RNG_BIST_CNTR_0_RESERVED_RESET _u(0x000)
#define TRNG_RNG_BIST_CNTR_0_RESERVED_BITS _u(0xffc00000)
#define TRNG_RNG_BIST_CNTR_0_RESERVED_MSB _u(31)
#define TRNG_RNG_BIST_CNTR_0_RESERVED_LSB _u(22)
#define TRNG_RNG_BIST_CNTR_0_RESERVED_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : TRNG_RNG_BIST_CNTR_0_ROSC_CNTR_VAL
// Description : Reflects the results of RNG BIST counter.
#define TRNG_RNG_BIST_CNTR_0_ROSC_CNTR_VAL_RESET _u(0x000000)
#define TRNG_RNG_BIST_CNTR_0_ROSC_CNTR_VAL_BITS _u(0x003fffff)
#define TRNG_RNG_BIST_CNTR_0_ROSC_CNTR_VAL_MSB _u(21)
#define TRNG_RNG_BIST_CNTR_0_ROSC_CNTR_VAL_LSB _u(0)
#define TRNG_RNG_BIST_CNTR_0_ROSC_CNTR_VAL_ACCESS "RO"
// =============================================================================
// Register : TRNG_RNG_BIST_CNTR_1
// Description : Collected BIST results.
#define TRNG_RNG_BIST_CNTR_1_OFFSET _u(0x000001e4)
#define TRNG_RNG_BIST_CNTR_1_BITS _u(0xffffffff)
#define TRNG_RNG_BIST_CNTR_1_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : TRNG_RNG_BIST_CNTR_1_RESERVED
// Description : RESERVED
#define TRNG_RNG_BIST_CNTR_1_RESERVED_RESET _u(0x000)
#define TRNG_RNG_BIST_CNTR_1_RESERVED_BITS _u(0xffc00000)
#define TRNG_RNG_BIST_CNTR_1_RESERVED_MSB _u(31)
#define TRNG_RNG_BIST_CNTR_1_RESERVED_LSB _u(22)
#define TRNG_RNG_BIST_CNTR_1_RESERVED_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : TRNG_RNG_BIST_CNTR_1_ROSC_CNTR_VAL
// Description : Reflects the results of RNG BIST counter.
#define TRNG_RNG_BIST_CNTR_1_ROSC_CNTR_VAL_RESET _u(0x000000)
#define TRNG_RNG_BIST_CNTR_1_ROSC_CNTR_VAL_BITS _u(0x003fffff)
#define TRNG_RNG_BIST_CNTR_1_ROSC_CNTR_VAL_MSB _u(21)
#define TRNG_RNG_BIST_CNTR_1_ROSC_CNTR_VAL_LSB _u(0)
#define TRNG_RNG_BIST_CNTR_1_ROSC_CNTR_VAL_ACCESS "RO"
// =============================================================================
// Register : TRNG_RNG_BIST_CNTR_2
// Description : Collected BIST results.
#define TRNG_RNG_BIST_CNTR_2_OFFSET _u(0x000001e8)
#define TRNG_RNG_BIST_CNTR_2_BITS _u(0xffffffff)
#define TRNG_RNG_BIST_CNTR_2_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : TRNG_RNG_BIST_CNTR_2_RESERVED
// Description : RESERVED
#define TRNG_RNG_BIST_CNTR_2_RESERVED_RESET _u(0x000)
#define TRNG_RNG_BIST_CNTR_2_RESERVED_BITS _u(0xffc00000)
#define TRNG_RNG_BIST_CNTR_2_RESERVED_MSB _u(31)
#define TRNG_RNG_BIST_CNTR_2_RESERVED_LSB _u(22)
#define TRNG_RNG_BIST_CNTR_2_RESERVED_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : TRNG_RNG_BIST_CNTR_2_ROSC_CNTR_VAL
// Description : Reflects the results of RNG BIST counter.
#define TRNG_RNG_BIST_CNTR_2_ROSC_CNTR_VAL_RESET _u(0x000000)
#define TRNG_RNG_BIST_CNTR_2_ROSC_CNTR_VAL_BITS _u(0x003fffff)
#define TRNG_RNG_BIST_CNTR_2_ROSC_CNTR_VAL_MSB _u(21)
#define TRNG_RNG_BIST_CNTR_2_ROSC_CNTR_VAL_LSB _u(0)
#define TRNG_RNG_BIST_CNTR_2_ROSC_CNTR_VAL_ACCESS "RO"
// =============================================================================
#endif // _HARDWARE_REGS_TRNG_H

1150
arch/arm/src/rp23xx/hardware/regs/uart.h
View file

File diff suppressed because it is too large Load diff

4209
arch/arm/src/rp23xx/hardware/regs/usb.h
View file

File diff suppressed because it is too large Load diff

6753
arch/arm/src/rp23xx/hardware/regs/usb_device_dpram.h
View file

File diff suppressed because it is too large Load diff

192
arch/arm/src/rp23xx/hardware/regs/watchdog.h
View file

@ -1,192 +0,0 @@
// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
// =============================================================================
// Register block : WATCHDOG
// Version : 1
// Bus type : apb
// =============================================================================
#ifndef _HARDWARE_REGS_WATCHDOG_H
#define _HARDWARE_REGS_WATCHDOG_H
// =============================================================================
// Register : WATCHDOG_CTRL
// Description : Watchdog control
// The rst_wdsel register determines which subsystems are reset
// when the watchdog is triggered.
// The watchdog can be triggered in software.
#define WATCHDOG_CTRL_OFFSET _u(0x00000000)
#define WATCHDOG_CTRL_BITS _u(0xc7ffffff)
#define WATCHDOG_CTRL_RESET _u(0x07000000)
// -----------------------------------------------------------------------------
// Field : WATCHDOG_CTRL_TRIGGER
// Description : Trigger a watchdog reset
#define WATCHDOG_CTRL_TRIGGER_RESET _u(0x0)
#define WATCHDOG_CTRL_TRIGGER_BITS _u(0x80000000)
#define WATCHDOG_CTRL_TRIGGER_MSB _u(31)
#define WATCHDOG_CTRL_TRIGGER_LSB _u(31)
#define WATCHDOG_CTRL_TRIGGER_ACCESS "SC"
// -----------------------------------------------------------------------------
// Field : WATCHDOG_CTRL_ENABLE
// Description : When not enabled the watchdog timer is paused
#define WATCHDOG_CTRL_ENABLE_RESET _u(0x0)
#define WATCHDOG_CTRL_ENABLE_BITS _u(0x40000000)
#define WATCHDOG_CTRL_ENABLE_MSB _u(30)
#define WATCHDOG_CTRL_ENABLE_LSB _u(30)
#define WATCHDOG_CTRL_ENABLE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : WATCHDOG_CTRL_PAUSE_DBG1
// Description : Pause the watchdog timer when processor 1 is in debug mode
#define WATCHDOG_CTRL_PAUSE_DBG1_RESET _u(0x1)
#define WATCHDOG_CTRL_PAUSE_DBG1_BITS _u(0x04000000)
#define WATCHDOG_CTRL_PAUSE_DBG1_MSB _u(26)
#define WATCHDOG_CTRL_PAUSE_DBG1_LSB _u(26)
#define WATCHDOG_CTRL_PAUSE_DBG1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : WATCHDOG_CTRL_PAUSE_DBG0
// Description : Pause the watchdog timer when processor 0 is in debug mode
#define WATCHDOG_CTRL_PAUSE_DBG0_RESET _u(0x1)
#define WATCHDOG_CTRL_PAUSE_DBG0_BITS _u(0x02000000)
#define WATCHDOG_CTRL_PAUSE_DBG0_MSB _u(25)
#define WATCHDOG_CTRL_PAUSE_DBG0_LSB _u(25)
#define WATCHDOG_CTRL_PAUSE_DBG0_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : WATCHDOG_CTRL_PAUSE_JTAG
// Description : Pause the watchdog timer when JTAG is accessing the bus fabric
#define WATCHDOG_CTRL_PAUSE_JTAG_RESET _u(0x1)
#define WATCHDOG_CTRL_PAUSE_JTAG_BITS _u(0x01000000)
#define WATCHDOG_CTRL_PAUSE_JTAG_MSB _u(24)
#define WATCHDOG_CTRL_PAUSE_JTAG_LSB _u(24)
#define WATCHDOG_CTRL_PAUSE_JTAG_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : WATCHDOG_CTRL_TIME
// Description : Indicates the time in usec before a watchdog reset will be
// triggered
#define WATCHDOG_CTRL_TIME_RESET _u(0x000000)
#define WATCHDOG_CTRL_TIME_BITS _u(0x00ffffff)
#define WATCHDOG_CTRL_TIME_MSB _u(23)
#define WATCHDOG_CTRL_TIME_LSB _u(0)
#define WATCHDOG_CTRL_TIME_ACCESS "RO"
// =============================================================================
// Register : WATCHDOG_LOAD
// Description : Load the watchdog timer. The maximum setting is 0xffffff which
// corresponds to approximately 16 seconds.
#define WATCHDOG_LOAD_OFFSET _u(0x00000004)
#define WATCHDOG_LOAD_BITS _u(0x00ffffff)
#define WATCHDOG_LOAD_RESET _u(0x00000000)
#define WATCHDOG_LOAD_MSB _u(23)
#define WATCHDOG_LOAD_LSB _u(0)
#define WATCHDOG_LOAD_ACCESS "WF"
// =============================================================================
// Register : WATCHDOG_REASON
// Description : Logs the reason for the last reset. Both bits are zero for the
// case of a hardware reset.
//
// Additionally, as of RP2350, a debugger warm reset of either
// core (SYSRESETREQ or hartreset) will also clear the watchdog
// reason register, so that software loaded under the debugger
// following a watchdog timeout will not continue to see the
// timeout condition.
#define WATCHDOG_REASON_OFFSET _u(0x00000008)
#define WATCHDOG_REASON_BITS _u(0x00000003)
#define WATCHDOG_REASON_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : WATCHDOG_REASON_FORCE
#define WATCHDOG_REASON_FORCE_RESET _u(0x0)
#define WATCHDOG_REASON_FORCE_BITS _u(0x00000002)
#define WATCHDOG_REASON_FORCE_MSB _u(1)
#define WATCHDOG_REASON_FORCE_LSB _u(1)
#define WATCHDOG_REASON_FORCE_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : WATCHDOG_REASON_TIMER
#define WATCHDOG_REASON_TIMER_RESET _u(0x0)
#define WATCHDOG_REASON_TIMER_BITS _u(0x00000001)
#define WATCHDOG_REASON_TIMER_MSB _u(0)
#define WATCHDOG_REASON_TIMER_LSB _u(0)
#define WATCHDOG_REASON_TIMER_ACCESS "RO"
// =============================================================================
// Register : WATCHDOG_SCRATCH0
// Description : Scratch register. Information persists through soft reset of
// the chip.
#define WATCHDOG_SCRATCH0_OFFSET _u(0x0000000c)
#define WATCHDOG_SCRATCH0_BITS _u(0xffffffff)
#define WATCHDOG_SCRATCH0_RESET _u(0x00000000)
#define WATCHDOG_SCRATCH0_MSB _u(31)
#define WATCHDOG_SCRATCH0_LSB _u(0)
#define WATCHDOG_SCRATCH0_ACCESS "RW"
// =============================================================================
// Register : WATCHDOG_SCRATCH1
// Description : Scratch register. Information persists through soft reset of
// the chip.
#define WATCHDOG_SCRATCH1_OFFSET _u(0x00000010)
#define WATCHDOG_SCRATCH1_BITS _u(0xffffffff)
#define WATCHDOG_SCRATCH1_RESET _u(0x00000000)
#define WATCHDOG_SCRATCH1_MSB _u(31)
#define WATCHDOG_SCRATCH1_LSB _u(0)
#define WATCHDOG_SCRATCH1_ACCESS "RW"
// =============================================================================
// Register : WATCHDOG_SCRATCH2
// Description : Scratch register. Information persists through soft reset of
// the chip.
#define WATCHDOG_SCRATCH2_OFFSET _u(0x00000014)
#define WATCHDOG_SCRATCH2_BITS _u(0xffffffff)
#define WATCHDOG_SCRATCH2_RESET _u(0x00000000)
#define WATCHDOG_SCRATCH2_MSB _u(31)
#define WATCHDOG_SCRATCH2_LSB _u(0)
#define WATCHDOG_SCRATCH2_ACCESS "RW"
// =============================================================================
// Register : WATCHDOG_SCRATCH3
// Description : Scratch register. Information persists through soft reset of
// the chip.
#define WATCHDOG_SCRATCH3_OFFSET _u(0x00000018)
#define WATCHDOG_SCRATCH3_BITS _u(0xffffffff)
#define WATCHDOG_SCRATCH3_RESET _u(0x00000000)
#define WATCHDOG_SCRATCH3_MSB _u(31)
#define WATCHDOG_SCRATCH3_LSB _u(0)
#define WATCHDOG_SCRATCH3_ACCESS "RW"
// =============================================================================
// Register : WATCHDOG_SCRATCH4
// Description : Scratch register. Information persists through soft reset of
// the chip.
#define WATCHDOG_SCRATCH4_OFFSET _u(0x0000001c)
#define WATCHDOG_SCRATCH4_BITS _u(0xffffffff)
#define WATCHDOG_SCRATCH4_RESET _u(0x00000000)
#define WATCHDOG_SCRATCH4_MSB _u(31)
#define WATCHDOG_SCRATCH4_LSB _u(0)
#define WATCHDOG_SCRATCH4_ACCESS "RW"
// =============================================================================
// Register : WATCHDOG_SCRATCH5
// Description : Scratch register. Information persists through soft reset of
// the chip.
#define WATCHDOG_SCRATCH5_OFFSET _u(0x00000020)
#define WATCHDOG_SCRATCH5_BITS _u(0xffffffff)
#define WATCHDOG_SCRATCH5_RESET _u(0x00000000)
#define WATCHDOG_SCRATCH5_MSB _u(31)
#define WATCHDOG_SCRATCH5_LSB _u(0)
#define WATCHDOG_SCRATCH5_ACCESS "RW"
// =============================================================================
// Register : WATCHDOG_SCRATCH6
// Description : Scratch register. Information persists through soft reset of
// the chip.
#define WATCHDOG_SCRATCH6_OFFSET _u(0x00000024)
#define WATCHDOG_SCRATCH6_BITS _u(0xffffffff)
#define WATCHDOG_SCRATCH6_RESET _u(0x00000000)
#define WATCHDOG_SCRATCH6_MSB _u(31)
#define WATCHDOG_SCRATCH6_LSB _u(0)
#define WATCHDOG_SCRATCH6_ACCESS "RW"
// =============================================================================
// Register : WATCHDOG_SCRATCH7
// Description : Scratch register. Information persists through soft reset of
// the chip.
#define WATCHDOG_SCRATCH7_OFFSET _u(0x00000028)
#define WATCHDOG_SCRATCH7_BITS _u(0xffffffff)
#define WATCHDOG_SCRATCH7_RESET _u(0x00000000)
#define WATCHDOG_SCRATCH7_MSB _u(31)
#define WATCHDOG_SCRATCH7_LSB _u(0)
#define WATCHDOG_SCRATCH7_ACCESS "RW"
// =============================================================================
#endif // _HARDWARE_REGS_WATCHDOG_H

313
arch/arm/src/rp23xx/hardware/regs/xip.h
View file

@ -1,313 +0,0 @@
// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
// =============================================================================
// Register block : XIP
// Version : 1
// Bus type : ahb
// Description : QSPI flash execute-in-place block
// =============================================================================
#ifndef _HARDWARE_REGS_XIP_H
#define _HARDWARE_REGS_XIP_H
// =============================================================================
// Register : XIP_CTRL
// Description : Cache control register. Read-only from a Non-secure context.
#define XIP_CTRL_OFFSET _u(0x00000000)
#define XIP_CTRL_BITS _u(0x00000ffb)
#define XIP_CTRL_RESET _u(0x00000083)
// -----------------------------------------------------------------------------
// Field : XIP_CTRL_WRITABLE_M1
// Description : If 1, enable writes to XIP memory window 1 (addresses
// 0x11000000 through 0x11ffffff, and their uncached mirrors). If
// 0, this region is read-only.
//
// XIP memory is *read-only by default*. This bit must be set to
// enable writes if a RAM device is attached on QSPI chip select
// 1.
//
// The default read-only behaviour avoids two issues with writing
// to a read-only QSPI device (e.g. flash). First, a write will
// initially appear to succeed due to caching, but the data will
// eventually be lost when the written line is evicted, causing
// unpredictable behaviour.
//
// Second, when a written line is evicted, it will cause a write
// command to be issued to the flash, which can break the flash
// out of its continuous read mode. After this point, flash reads
// will return garbage. This is a security concern, as it allows
// Non-secure software to break Secure flash reads if it has
// permission to write to any flash address.
//
// Note the read-only behaviour is implemented by downgrading
// writes to reads, so writes will still cause allocation of an
// address, but have no other effect.
#define XIP_CTRL_WRITABLE_M1_RESET _u(0x0)
#define XIP_CTRL_WRITABLE_M1_BITS _u(0x00000800)
#define XIP_CTRL_WRITABLE_M1_MSB _u(11)
#define XIP_CTRL_WRITABLE_M1_LSB _u(11)
#define XIP_CTRL_WRITABLE_M1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : XIP_CTRL_WRITABLE_M0
// Description : If 1, enable writes to XIP memory window 0 (addresses
// 0x10000000 through 0x10ffffff, and their uncached mirrors). If
// 0, this region is read-only.
//
// XIP memory is *read-only by default*. This bit must be set to
// enable writes if a RAM device is attached on QSPI chip select
// 0.
//
// The default read-only behaviour avoids two issues with writing
// to a read-only QSPI device (e.g. flash). First, a write will
// initially appear to succeed due to caching, but the data will
// eventually be lost when the written line is evicted, causing
// unpredictable behaviour.
//
// Second, when a written line is evicted, it will cause a write
// command to be issued to the flash, which can break the flash
// out of its continuous read mode. After this point, flash reads
// will return garbage. This is a security concern, as it allows
// Non-secure software to break Secure flash reads if it has
// permission to write to any flash address.
//
// Note the read-only behaviour is implemented by downgrading
// writes to reads, so writes will still cause allocation of an
// address, but have no other effect.
#define XIP_CTRL_WRITABLE_M0_RESET _u(0x0)
#define XIP_CTRL_WRITABLE_M0_BITS _u(0x00000400)
#define XIP_CTRL_WRITABLE_M0_MSB _u(10)
#define XIP_CTRL_WRITABLE_M0_LSB _u(10)
#define XIP_CTRL_WRITABLE_M0_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : XIP_CTRL_SPLIT_WAYS
// Description : When 1, route all cached+Secure accesses to way 0 of the cache,
// and route all cached+Non-secure accesses to way 1 of the cache.
//
// This partitions the cache into two half-sized direct-mapped
// regions, such that Non-secure code can not observe cache line
// state changes caused by Secure execution.
//
// A full cache flush is required when changing the value of
// SPLIT_WAYS. The flush should be performed whilst SPLIT_WAYS is
// 0, so that both cache ways are accessible for invalidation.
#define XIP_CTRL_SPLIT_WAYS_RESET _u(0x0)
#define XIP_CTRL_SPLIT_WAYS_BITS _u(0x00000200)
#define XIP_CTRL_SPLIT_WAYS_MSB _u(9)
#define XIP_CTRL_SPLIT_WAYS_LSB _u(9)
#define XIP_CTRL_SPLIT_WAYS_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : XIP_CTRL_MAINT_NONSEC
// Description : When 0, Non-secure accesses to the cache maintenance address
// window (addr[27] == 1, addr[26] == 0) will generate a bus
// error. When 1, Non-secure accesses can perform cache
// maintenance operations by writing to the cache maintenance
// address window.
//
// Cache maintenance operations may be used to corrupt Secure data
// by invalidating cache lines inappropriately, or map Secure
// content into a Non-secure region by pinning cache lines.
// Therefore this bit should generally be set to 0, unless Secure
// code is not using the cache.
//
// Care should also be taken to clear the cache data memory and
// tag memory before granting maintenance operations to Non-secure
// code.
#define XIP_CTRL_MAINT_NONSEC_RESET _u(0x0)
#define XIP_CTRL_MAINT_NONSEC_BITS _u(0x00000100)
#define XIP_CTRL_MAINT_NONSEC_MSB _u(8)
#define XIP_CTRL_MAINT_NONSEC_LSB _u(8)
#define XIP_CTRL_MAINT_NONSEC_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : XIP_CTRL_NO_UNTRANSLATED_NONSEC
// Description : When 1, Non-secure accesses to the uncached, untranslated
// window (addr[27:26] == 3) will generate a bus error.
#define XIP_CTRL_NO_UNTRANSLATED_NONSEC_RESET _u(0x1)
#define XIP_CTRL_NO_UNTRANSLATED_NONSEC_BITS _u(0x00000080)
#define XIP_CTRL_NO_UNTRANSLATED_NONSEC_MSB _u(7)
#define XIP_CTRL_NO_UNTRANSLATED_NONSEC_LSB _u(7)
#define XIP_CTRL_NO_UNTRANSLATED_NONSEC_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : XIP_CTRL_NO_UNTRANSLATED_SEC
// Description : When 1, Secure accesses to the uncached, untranslated window
// (addr[27:26] == 3) will generate a bus error.
#define XIP_CTRL_NO_UNTRANSLATED_SEC_RESET _u(0x0)
#define XIP_CTRL_NO_UNTRANSLATED_SEC_BITS _u(0x00000040)
#define XIP_CTRL_NO_UNTRANSLATED_SEC_MSB _u(6)
#define XIP_CTRL_NO_UNTRANSLATED_SEC_LSB _u(6)
#define XIP_CTRL_NO_UNTRANSLATED_SEC_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : XIP_CTRL_NO_UNCACHED_NONSEC
// Description : When 1, Non-secure accesses to the uncached window (addr[27:26]
// == 1) will generate a bus error. This may reduce the number of
// SAU/MPU/PMP regions required to protect flash contents.
//
// Note this does not disable access to the uncached, untranslated
// window -- see NO_UNTRANSLATED_SEC.
#define XIP_CTRL_NO_UNCACHED_NONSEC_RESET _u(0x0)
#define XIP_CTRL_NO_UNCACHED_NONSEC_BITS _u(0x00000020)
#define XIP_CTRL_NO_UNCACHED_NONSEC_MSB _u(5)
#define XIP_CTRL_NO_UNCACHED_NONSEC_LSB _u(5)
#define XIP_CTRL_NO_UNCACHED_NONSEC_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : XIP_CTRL_NO_UNCACHED_SEC
// Description : When 1, Secure accesses to the uncached window (addr[27:26] ==
// 1) will generate a bus error. This may reduce the number of
// SAU/MPU/PMP regions required to protect flash contents.
//
// Note this does not disable access to the uncached, untranslated
// window -- see NO_UNTRANSLATED_SEC.
#define XIP_CTRL_NO_UNCACHED_SEC_RESET _u(0x0)
#define XIP_CTRL_NO_UNCACHED_SEC_BITS _u(0x00000010)
#define XIP_CTRL_NO_UNCACHED_SEC_MSB _u(4)
#define XIP_CTRL_NO_UNCACHED_SEC_LSB _u(4)
#define XIP_CTRL_NO_UNCACHED_SEC_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : XIP_CTRL_POWER_DOWN
// Description : When 1, the cache memories are powered down. They retain state,
// but can not be accessed. This reduces static power dissipation.
// Writing 1 to this bit forces CTRL_EN_SECURE and
// CTRL_EN_NONSECURE to 0, i.e. the cache cannot be enabled when
// powered down.
#define XIP_CTRL_POWER_DOWN_RESET _u(0x0)
#define XIP_CTRL_POWER_DOWN_BITS _u(0x00000008)
#define XIP_CTRL_POWER_DOWN_MSB _u(3)
#define XIP_CTRL_POWER_DOWN_LSB _u(3)
#define XIP_CTRL_POWER_DOWN_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : XIP_CTRL_EN_NONSECURE
// Description : When 1, enable the cache for Non-secure accesses. When enabled,
// Non-secure XIP accesses to the cached (addr[26] == 0) window
// will query the cache, and QSPI accesses are performed only if
// the requested data is not present. When disabled, Secure access
// ignore the cache contents, and always access the QSPI
// interface.
//
// Accesses to the uncached (addr[26] == 1) window will never
// query the cache, irrespective of this bit.
#define XIP_CTRL_EN_NONSECURE_RESET _u(0x1)
#define XIP_CTRL_EN_NONSECURE_BITS _u(0x00000002)
#define XIP_CTRL_EN_NONSECURE_MSB _u(1)
#define XIP_CTRL_EN_NONSECURE_LSB _u(1)
#define XIP_CTRL_EN_NONSECURE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : XIP_CTRL_EN_SECURE
// Description : When 1, enable the cache for Secure accesses. When enabled,
// Secure XIP accesses to the cached (addr[26] == 0) window will
// query the cache, and QSPI accesses are performed only if the
// requested data is not present. When disabled, Secure access
// ignore the cache contents, and always access the QSPI
// interface.
//
// Accesses to the uncached (addr[26] == 1) window will never
// query the cache, irrespective of this bit.
//
// There is no cache-as-SRAM address window. Cache lines are
// allocated for SRAM-like use by individually pinning them, and
// keeping the cache enabled.
#define XIP_CTRL_EN_SECURE_RESET _u(0x1)
#define XIP_CTRL_EN_SECURE_BITS _u(0x00000001)
#define XIP_CTRL_EN_SECURE_MSB _u(0)
#define XIP_CTRL_EN_SECURE_LSB _u(0)
#define XIP_CTRL_EN_SECURE_ACCESS "RW"
// =============================================================================
// Register : XIP_STAT
#define XIP_STAT_OFFSET _u(0x00000008)
#define XIP_STAT_BITS _u(0x00000006)
#define XIP_STAT_RESET _u(0x00000002)
// -----------------------------------------------------------------------------
// Field : XIP_STAT_FIFO_FULL
// Description : When 1, indicates the XIP streaming FIFO is completely full.
// The streaming FIFO is 2 entries deep, so the full and empty
// flag allow its level to be ascertained.
#define XIP_STAT_FIFO_FULL_RESET _u(0x0)
#define XIP_STAT_FIFO_FULL_BITS _u(0x00000004)
#define XIP_STAT_FIFO_FULL_MSB _u(2)
#define XIP_STAT_FIFO_FULL_LSB _u(2)
#define XIP_STAT_FIFO_FULL_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : XIP_STAT_FIFO_EMPTY
// Description : When 1, indicates the XIP streaming FIFO is completely empty.
#define XIP_STAT_FIFO_EMPTY_RESET _u(0x1)
#define XIP_STAT_FIFO_EMPTY_BITS _u(0x00000002)
#define XIP_STAT_FIFO_EMPTY_MSB _u(1)
#define XIP_STAT_FIFO_EMPTY_LSB _u(1)
#define XIP_STAT_FIFO_EMPTY_ACCESS "RO"
// =============================================================================
// Register : XIP_CTR_HIT
// Description : Cache Hit counter
// A 32 bit saturating counter that increments upon each cache
// hit,
// i.e. when an XIP access is serviced directly from cached data.
// Write any value to clear.
#define XIP_CTR_HIT_OFFSET _u(0x0000000c)
#define XIP_CTR_HIT_BITS _u(0xffffffff)
#define XIP_CTR_HIT_RESET _u(0x00000000)
#define XIP_CTR_HIT_MSB _u(31)
#define XIP_CTR_HIT_LSB _u(0)
#define XIP_CTR_HIT_ACCESS "WC"
// =============================================================================
// Register : XIP_CTR_ACC
// Description : Cache Access counter
// A 32 bit saturating counter that increments upon each XIP
// access,
// whether the cache is hit or not. This includes noncacheable
// accesses.
// Write any value to clear.
#define XIP_CTR_ACC_OFFSET _u(0x00000010)
#define XIP_CTR_ACC_BITS _u(0xffffffff)
#define XIP_CTR_ACC_RESET _u(0x00000000)
#define XIP_CTR_ACC_MSB _u(31)
#define XIP_CTR_ACC_LSB _u(0)
#define XIP_CTR_ACC_ACCESS "WC"
// =============================================================================
// Register : XIP_STREAM_ADDR
// Description : FIFO stream address
// The address of the next word to be streamed from flash to the
// streaming FIFO.
// Increments automatically after each flash access.
// Write the initial access address here before starting a
// streaming read.
#define XIP_STREAM_ADDR_OFFSET _u(0x00000014)
#define XIP_STREAM_ADDR_BITS _u(0xfffffffc)
#define XIP_STREAM_ADDR_RESET _u(0x00000000)
#define XIP_STREAM_ADDR_MSB _u(31)
#define XIP_STREAM_ADDR_LSB _u(2)
#define XIP_STREAM_ADDR_ACCESS "RW"
// =============================================================================
// Register : XIP_STREAM_CTR
// Description : FIFO stream control
// Write a nonzero value to start a streaming read. This will then
// progress in the background, using flash idle cycles to transfer
// a linear data block from flash to the streaming FIFO.
// Decrements automatically (1 at a time) as the stream
// progresses, and halts on reaching 0.
// Write 0 to halt an in-progress stream, and discard any in-
// flight
// read, so that a new stream can immediately be started (after
// draining the FIFO and reinitialising STREAM_ADDR)
#define XIP_STREAM_CTR_OFFSET _u(0x00000018)
#define XIP_STREAM_CTR_BITS _u(0x003fffff)
#define XIP_STREAM_CTR_RESET _u(0x00000000)
#define XIP_STREAM_CTR_MSB _u(21)
#define XIP_STREAM_CTR_LSB _u(0)
#define XIP_STREAM_CTR_ACCESS "RW"
// =============================================================================
// Register : XIP_STREAM_FIFO
// Description : FIFO stream data
// Streamed data is buffered here, for retrieval by the system
// DMA.
// This FIFO can also be accessed via the XIP_AUX slave, to avoid
// exposing
// the DMA to bus stalls caused by other XIP traffic.
#define XIP_STREAM_FIFO_OFFSET _u(0x0000001c)
#define XIP_STREAM_FIFO_BITS _u(0xffffffff)
#define XIP_STREAM_FIFO_RESET _u(0x00000000)
#define XIP_STREAM_FIFO_MSB _u(31)
#define XIP_STREAM_FIFO_LSB _u(0)
#define XIP_STREAM_FIFO_ACCESS "RF"
// =============================================================================
#endif // _HARDWARE_REGS_XIP_H

123
arch/arm/src/rp23xx/hardware/regs/xip_aux.h
View file

@ -1,123 +0,0 @@
// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
// =============================================================================
// Register block : XIP_AUX
// Version : 1
// Bus type : ahb
// Description : Auxiliary DMA access to XIP FIFOs, via fast AHB bus access
// =============================================================================
#ifndef _HARDWARE_REGS_XIP_AUX_H
#define _HARDWARE_REGS_XIP_AUX_H
// =============================================================================
// Register : XIP_AUX_STREAM
// Description : Read the XIP stream FIFO (fast bus access to
// XIP_CTRL_STREAM_FIFO)
#define XIP_AUX_STREAM_OFFSET _u(0x00000000)
#define XIP_AUX_STREAM_BITS _u(0xffffffff)
#define XIP_AUX_STREAM_RESET _u(0x00000000)
#define XIP_AUX_STREAM_MSB _u(31)
#define XIP_AUX_STREAM_LSB _u(0)
#define XIP_AUX_STREAM_ACCESS "RF"
// =============================================================================
// Register : XIP_AUX_QMI_DIRECT_TX
// Description : Write to the QMI direct-mode TX FIFO (fast bus access to
// QMI_DIRECT_TX)
#define XIP_AUX_QMI_DIRECT_TX_OFFSET _u(0x00000004)
#define XIP_AUX_QMI_DIRECT_TX_BITS _u(0x001fffff)
#define XIP_AUX_QMI_DIRECT_TX_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : XIP_AUX_QMI_DIRECT_TX_NOPUSH
// Description : Inhibit the RX FIFO push that would correspond to this TX FIFO
// entry.
//
// Useful to avoid garbage appearing in the RX FIFO when pushing
// the command at the beginning of a SPI transfer.
#define XIP_AUX_QMI_DIRECT_TX_NOPUSH_RESET _u(0x0)
#define XIP_AUX_QMI_DIRECT_TX_NOPUSH_BITS _u(0x00100000)
#define XIP_AUX_QMI_DIRECT_TX_NOPUSH_MSB _u(20)
#define XIP_AUX_QMI_DIRECT_TX_NOPUSH_LSB _u(20)
#define XIP_AUX_QMI_DIRECT_TX_NOPUSH_ACCESS "WF"
// -----------------------------------------------------------------------------
// Field : XIP_AUX_QMI_DIRECT_TX_OE
// Description : Output enable (active-high). For single width (SPI), this field
// is ignored, and SD0 is always set to output, with SD1 always
// set to input.
//
// For dual and quad width (DSPI/QSPI), this sets whether the
// relevant SDx pads are set to output whilst transferring this
// FIFO record. In this case the command/address should have OE
// set, and the data transfer should have OE set or clear
// depending on the direction of the transfer.
#define XIP_AUX_QMI_DIRECT_TX_OE_RESET _u(0x0)
#define XIP_AUX_QMI_DIRECT_TX_OE_BITS _u(0x00080000)
#define XIP_AUX_QMI_DIRECT_TX_OE_MSB _u(19)
#define XIP_AUX_QMI_DIRECT_TX_OE_LSB _u(19)
#define XIP_AUX_QMI_DIRECT_TX_OE_ACCESS "WF"
// -----------------------------------------------------------------------------
// Field : XIP_AUX_QMI_DIRECT_TX_DWIDTH
// Description : Data width. If 0, hardware will transmit the 8 LSBs of the
// DIRECT_TX DATA field, and return an 8-bit value in the 8 LSBs
// of DIRECT_RX. If 1, the full 16-bit width is used. 8-bit and
// 16-bit transfers can be mixed freely.
#define XIP_AUX_QMI_DIRECT_TX_DWIDTH_RESET _u(0x0)
#define XIP_AUX_QMI_DIRECT_TX_DWIDTH_BITS _u(0x00040000)
#define XIP_AUX_QMI_DIRECT_TX_DWIDTH_MSB _u(18)
#define XIP_AUX_QMI_DIRECT_TX_DWIDTH_LSB _u(18)
#define XIP_AUX_QMI_DIRECT_TX_DWIDTH_ACCESS "WF"
// -----------------------------------------------------------------------------
// Field : XIP_AUX_QMI_DIRECT_TX_IWIDTH
// Description : Configure whether this FIFO record is transferred with
// single/dual/quad interface width (0/1/2). Different widths can
// be mixed freely.
// 0x0 -> Single width
// 0x1 -> Dual width
// 0x2 -> Quad width
#define XIP_AUX_QMI_DIRECT_TX_IWIDTH_RESET _u(0x0)
#define XIP_AUX_QMI_DIRECT_TX_IWIDTH_BITS _u(0x00030000)
#define XIP_AUX_QMI_DIRECT_TX_IWIDTH_MSB _u(17)
#define XIP_AUX_QMI_DIRECT_TX_IWIDTH_LSB _u(16)
#define XIP_AUX_QMI_DIRECT_TX_IWIDTH_ACCESS "WF"
#define XIP_AUX_QMI_DIRECT_TX_IWIDTH_VALUE_S _u(0x0)
#define XIP_AUX_QMI_DIRECT_TX_IWIDTH_VALUE_D _u(0x1)
#define XIP_AUX_QMI_DIRECT_TX_IWIDTH_VALUE_Q _u(0x2)
// -----------------------------------------------------------------------------
// Field : XIP_AUX_QMI_DIRECT_TX_DATA
// Description : Data pushed here will be clocked out falling edges of SCK (or
// before the very first rising edge of SCK, if this is the first
// pulse). For each byte clocked out, the interface will
// simultaneously sample one byte, on rising edges of SCK, and
// push this to the DIRECT_RX FIFO.
//
// For 16-bit data, the least-significant byte is transmitted
// first.
#define XIP_AUX_QMI_DIRECT_TX_DATA_RESET _u(0x0000)
#define XIP_AUX_QMI_DIRECT_TX_DATA_BITS _u(0x0000ffff)
#define XIP_AUX_QMI_DIRECT_TX_DATA_MSB _u(15)
#define XIP_AUX_QMI_DIRECT_TX_DATA_LSB _u(0)
#define XIP_AUX_QMI_DIRECT_TX_DATA_ACCESS "WF"
// =============================================================================
// Register : XIP_AUX_QMI_DIRECT_RX
// Description : Read from the QMI direct-mode RX FIFO (fast bus access to
// QMI_DIRECT_RX)
// With each byte clocked out on the serial interface, one byte
// will simultaneously be clocked in, and will appear in this
// FIFO. The serial interface will stall when this FIFO is full,
// to avoid dropping data.
//
// When 16-bit data is pushed into the TX FIFO, the corresponding
// RX FIFO push will also contain 16 bits of data. The least-
// significant byte is the first one received.
#define XIP_AUX_QMI_DIRECT_RX_OFFSET _u(0x00000008)
#define XIP_AUX_QMI_DIRECT_RX_BITS _u(0x0000ffff)
#define XIP_AUX_QMI_DIRECT_RX_RESET _u(0x00000000)
#define XIP_AUX_QMI_DIRECT_RX_MSB _u(15)
#define XIP_AUX_QMI_DIRECT_RX_LSB _u(0)
#define XIP_AUX_QMI_DIRECT_RX_ACCESS "RF"
// =============================================================================
#endif // _HARDWARE_REGS_XIP_AUX_H

175
arch/arm/src/rp23xx/hardware/regs/xosc.h
View file

@ -1,175 +0,0 @@
// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
// =============================================================================
// Register block : XOSC
// Version : 1
// Bus type : apb
// Description : Controls the crystal oscillator
// =============================================================================
#ifndef _HARDWARE_REGS_XOSC_H
#define _HARDWARE_REGS_XOSC_H
// =============================================================================
// Register : XOSC_CTRL
// Description : Crystal Oscillator Control
#define XOSC_CTRL_OFFSET _u(0x00000000)
#define XOSC_CTRL_BITS _u(0x00ffffff)
#define XOSC_CTRL_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : XOSC_CTRL_ENABLE
// Description : On power-up this field is initialised to DISABLE and the chip
// runs from the ROSC.
// If the chip has subsequently been programmed to run from the
// XOSC then setting this field to DISABLE may lock-up the chip.
// If this is a concern then run the clk_ref from the ROSC and
// enable the clk_sys RESUS feature.
// The 12-bit code is intended to give some protection against
// accidental writes. An invalid setting will retain the previous
// value. The actual value being used can be read from
// STATUS_ENABLED
// 0xd1e -> DISABLE
// 0xfab -> ENABLE
#define XOSC_CTRL_ENABLE_RESET "-"
#define XOSC_CTRL_ENABLE_BITS _u(0x00fff000)
#define XOSC_CTRL_ENABLE_MSB _u(23)
#define XOSC_CTRL_ENABLE_LSB _u(12)
#define XOSC_CTRL_ENABLE_ACCESS "RW"
#define XOSC_CTRL_ENABLE_VALUE_DISABLE _u(0xd1e)
#define XOSC_CTRL_ENABLE_VALUE_ENABLE _u(0xfab)
// -----------------------------------------------------------------------------
// Field : XOSC_CTRL_FREQ_RANGE
// Description : The 12-bit code is intended to give some protection against
// accidental writes. An invalid setting will retain the previous
// value. The actual value being used can be read from
// STATUS_FREQ_RANGE
// 0xaa0 -> 1_15MHZ
// 0xaa1 -> 10_30MHZ
// 0xaa2 -> 25_60MHZ
// 0xaa3 -> 40_100MHZ
#define XOSC_CTRL_FREQ_RANGE_RESET "-"
#define XOSC_CTRL_FREQ_RANGE_BITS _u(0x00000fff)
#define XOSC_CTRL_FREQ_RANGE_MSB _u(11)
#define XOSC_CTRL_FREQ_RANGE_LSB _u(0)
#define XOSC_CTRL_FREQ_RANGE_ACCESS "RW"
#define XOSC_CTRL_FREQ_RANGE_VALUE_1_15MHZ _u(0xaa0)
#define XOSC_CTRL_FREQ_RANGE_VALUE_10_30MHZ _u(0xaa1)
#define XOSC_CTRL_FREQ_RANGE_VALUE_25_60MHZ _u(0xaa2)
#define XOSC_CTRL_FREQ_RANGE_VALUE_40_100MHZ _u(0xaa3)
// =============================================================================
// Register : XOSC_STATUS
// Description : Crystal Oscillator Status
#define XOSC_STATUS_OFFSET _u(0x00000004)
#define XOSC_STATUS_BITS _u(0x81001003)
#define XOSC_STATUS_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : XOSC_STATUS_STABLE
// Description : Oscillator is running and stable
#define XOSC_STATUS_STABLE_RESET _u(0x0)
#define XOSC_STATUS_STABLE_BITS _u(0x80000000)
#define XOSC_STATUS_STABLE_MSB _u(31)
#define XOSC_STATUS_STABLE_LSB _u(31)
#define XOSC_STATUS_STABLE_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : XOSC_STATUS_BADWRITE
// Description : An invalid value has been written to CTRL_ENABLE or
// CTRL_FREQ_RANGE or DORMANT
#define XOSC_STATUS_BADWRITE_RESET _u(0x0)
#define XOSC_STATUS_BADWRITE_BITS _u(0x01000000)
#define XOSC_STATUS_BADWRITE_MSB _u(24)
#define XOSC_STATUS_BADWRITE_LSB _u(24)
#define XOSC_STATUS_BADWRITE_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : XOSC_STATUS_ENABLED
// Description : Oscillator is enabled but not necessarily running and stable,
// resets to 0
#define XOSC_STATUS_ENABLED_RESET "-"
#define XOSC_STATUS_ENABLED_BITS _u(0x00001000)
#define XOSC_STATUS_ENABLED_MSB _u(12)
#define XOSC_STATUS_ENABLED_LSB _u(12)
#define XOSC_STATUS_ENABLED_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : XOSC_STATUS_FREQ_RANGE
// Description : The current frequency range setting
// 0x0 -> 1_15MHZ
// 0x1 -> 10_30MHZ
// 0x2 -> 25_60MHZ
// 0x3 -> 40_100MHZ
#define XOSC_STATUS_FREQ_RANGE_RESET "-"
#define XOSC_STATUS_FREQ_RANGE_BITS _u(0x00000003)
#define XOSC_STATUS_FREQ_RANGE_MSB _u(1)
#define XOSC_STATUS_FREQ_RANGE_LSB _u(0)
#define XOSC_STATUS_FREQ_RANGE_ACCESS "RO"
#define XOSC_STATUS_FREQ_RANGE_VALUE_1_15MHZ _u(0x0)
#define XOSC_STATUS_FREQ_RANGE_VALUE_10_30MHZ _u(0x1)
#define XOSC_STATUS_FREQ_RANGE_VALUE_25_60MHZ _u(0x2)
#define XOSC_STATUS_FREQ_RANGE_VALUE_40_100MHZ _u(0x3)
// =============================================================================
// Register : XOSC_DORMANT
// Description : Crystal Oscillator pause control
// This is used to save power by pausing the XOSC
// On power-up this field is initialised to WAKE
// An invalid write will also select WAKE
// Warning: stop the PLLs before selecting dormant mode
// Warning: setup the irq before selecting dormant mode
// 0x636f6d61 -> dormant
// 0x77616b65 -> WAKE
#define XOSC_DORMANT_OFFSET _u(0x00000008)
#define XOSC_DORMANT_BITS _u(0xffffffff)
#define XOSC_DORMANT_RESET "-"
#define XOSC_DORMANT_MSB _u(31)
#define XOSC_DORMANT_LSB _u(0)
#define XOSC_DORMANT_ACCESS "RW"
#define XOSC_DORMANT_VALUE_DORMANT _u(0x636f6d61)
#define XOSC_DORMANT_VALUE_WAKE _u(0x77616b65)
// =============================================================================
// Register : XOSC_STARTUP
// Description : Controls the startup delay
#define XOSC_STARTUP_OFFSET _u(0x0000000c)
#define XOSC_STARTUP_BITS _u(0x00103fff)
#define XOSC_STARTUP_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : XOSC_STARTUP_X4
// Description : Multiplies the startup_delay by 4, just in case. The reset
// value is controlled by a mask-programmable tiecell and is
// provided in case we are booting from XOSC and the default
// startup delay is insufficient. The reset value is 0x0.
#define XOSC_STARTUP_X4_RESET "-"
#define XOSC_STARTUP_X4_BITS _u(0x00100000)
#define XOSC_STARTUP_X4_MSB _u(20)
#define XOSC_STARTUP_X4_LSB _u(20)
#define XOSC_STARTUP_X4_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : XOSC_STARTUP_DELAY
// Description : in multiples of 256*xtal_period. The reset value of 0xc4
// corresponds to approx 50 000 cycles.
#define XOSC_STARTUP_DELAY_RESET "-"
#define XOSC_STARTUP_DELAY_BITS _u(0x00003fff)
#define XOSC_STARTUP_DELAY_MSB _u(13)
#define XOSC_STARTUP_DELAY_LSB _u(0)
#define XOSC_STARTUP_DELAY_ACCESS "RW"
// =============================================================================
// Register : XOSC_COUNT
// Description : A down counter running at the xosc frequency which counts to
// zero and stops.
// Can be used for short software pauses when setting up time
// sensitive hardware.
// To start the counter, write a non-zero value. Reads will return
// 1 while the count is running and 0 when it has finished.
// Minimum count value is 4. Count values <4 will be treated as
// count value =4.
// Note that synchronisation to the register clock domain costs 2
// register clock cycles and the counter cannot compensate for
// that.
#define XOSC_COUNT_OFFSET _u(0x00000010)
#define XOSC_COUNT_BITS _u(0x0000ffff)
#define XOSC_COUNT_RESET _u(0x00000000)
#define XOSC_COUNT_MSB _u(15)
#define XOSC_COUNT_LSB _u(0)
#define XOSC_COUNT_ACCESS "RW"
// =============================================================================
#endif // _HARDWARE_REGS_XOSC_H

178
arch/arm/src/rp23xx/hardware/resets.h
View file

@ -1,178 +0,0 @@
/*
* Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _HARDWARE_RESETS_H
#define _HARDWARE_RESETS_H
#include "pico.h"
#include "hardware/structs/resets.h"
/** \file hardware/resets.h
* \defgroup hardware_resets hardware_resets
*
* \brief Hardware Reset API
*
* The reset controller allows software control of the resets to all of the peripherals that are not
* critical to boot the processor in the RP-series microcontroller.
*
* \subsubsection reset_bitmask
* \addtogroup hardware_resets
*
* Multiple blocks are referred to using a bitmask as follows:
*
* Block to reset | Bit
* ---------------|----
* USB | 24
* UART 1 | 23
* UART 0 | 22
* Timer | 21
* TB Manager | 20
* SysInfo | 19
* System Config | 18
* SPI 1 | 17
* SPI 0 | 16
* RTC | 15
* PWM | 14
* PLL USB | 13
* PLL System | 12
* PIO 1 | 11
* PIO 0 | 10
* Pads - QSPI | 9
* Pads - bank 0 | 8
* JTAG | 7
* IO Bank 1 | 6
* IO Bank 0 | 5
* I2C 1 | 4
* I2C 0 | 3
* DMA | 2
* Bus Control | 1
* ADC 0 | 0
*
* \subsection reset_example Example
* \addtogroup hardware_resets
* \include hello_reset.c
*/
// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_HARDWARE_RESETS, Enable/disable assertions in the hardware_resets module, type=bool, default=0, group=hardware_adc
#ifndef PARAM_ASSERTIONS_ENABLED_HARDWARE_RESETS
#ifdef PARAM_ASSERTIONS_ENABLED_RESET // backwards compatibility with SDK < 2.0.0
#define PARAM_ASSERTIONS_ENABLED_HARDWARE_RESETS PARAM_ASSERTIONS_ENABLED_RESET
#else
#define PARAM_ASSERTIONS_ENABLED_HARDWARE_RESETS 0
#endif
#endif
#ifdef __cplusplus
extern "C" {
#endif
static __force_inline void reset_block_reg_mask(io_rw_32 *reset, uint32_t mask) {
hw_set_bits(reset, mask);
}
static __force_inline void unreset_block_reg_mask(io_rw_32 *reset, uint32_t mask) {
hw_clear_bits(reset, mask);
}
static __force_inline void unreset_block_reg_mask_wait_blocking(io_rw_32 *reset, io_ro_32 *reset_done, uint32_t mask) {
hw_clear_bits(reset, mask);
while (~*reset_done & mask)
tight_loop_contents();
}
/// \tag::reset_funcs[]
/*! \brief Reset the specified HW blocks
* \ingroup hardware_resets
*
* \param bits Bit pattern indicating blocks to reset. See \ref reset_bitmask
*/
static __force_inline void reset_block_mask(uint32_t bits) {
reset_block_reg_mask(&resets_hw->reset, bits);
}
/*! \brief bring specified HW blocks out of reset
* \ingroup hardware_resets
*
* \param bits Bit pattern indicating blocks to unreset. See \ref reset_bitmask
*/
static __force_inline void unreset_block_mask(uint32_t bits) {
unreset_block_reg_mask(&resets_hw->reset, bits);
}
/*! \brief Bring specified HW blocks out of reset and wait for completion
* \ingroup hardware_resets
*
* \param bits Bit pattern indicating blocks to unreset. See \ref reset_bitmask
*/
static __force_inline void unreset_block_mask_wait_blocking(uint32_t bits) {
unreset_block_reg_mask_wait_blocking(&resets_hw->reset, &resets_hw->reset_done, bits);
}
/// \end::reset_funcs[]
#ifndef HARDWARE_RESETS_ENABLE_SDK1XX_COMPATIBILITY
#define HARDWARE_RESETS_ENABLE_SDK1XX_COMPATIBILITY 1
#endif
#if HARDWARE_RESETS_ENABLE_SDK1XX_COMPATIBILITY
static __force_inline void reset_block(uint32_t bits) {
reset_block_mask(bits);
}
static __force_inline void unreset_block(uint32_t bits) {
unreset_block_mask(bits);
}
static __force_inline void unreset_block_wait(uint32_t bits) {
return unreset_block_mask_wait_blocking(bits);
}
#endif
/*! \brief Reset the specified HW block
* \ingroup hardware_resets
*
* \param block_num the block number
*/
static inline void reset_block_num(uint32_t block_num) {
reset_block_reg_mask(&resets_hw->reset, 1u << block_num);
}
/*! \brief bring specified HW block out of reset
* \ingroup hardware_resets
*
* \param block_num the block number
*/
static inline void unreset_block_num(uint block_num) {
invalid_params_if(HARDWARE_RESETS, block_num > NUM_RESETS);
unreset_block_reg_mask(&resets_hw->reset, 1u << block_num);
}
/*! \brief Bring specified HW block out of reset and wait for completion
* \ingroup hardware_resets
*
* \param block_num the block number
*/
static inline void unreset_block_num_wait_blocking(uint block_num) {
invalid_params_if(HARDWARE_RESETS, block_num > NUM_RESETS);
unreset_block_reg_mask_wait_blocking(&resets_hw->reset, &resets_hw->reset_done, 1u << block_num);
}
/*! \brief Reset the specified HW block, and then bring at back out of reset and wait for completion
* \ingroup hardware_resets
*
* \param block_num the block number
*/
static inline void reset_unreset_block_num_wait_blocking(uint block_num) {
invalid_params_if(HARDWARE_RESETS, block_num > NUM_RESETS);
reset_block_reg_mask(&resets_hw->reset, 1u << block_num);
unreset_block_reg_mask_wait_blocking(&resets_hw->reset, &resets_hw->reset_done, 1u << block_num);
}
#ifdef __cplusplus
}
#endif
#endif

179
arch/arm/src/rp23xx/hardware/riscv.h
View file

@ -1,179 +0,0 @@
/*
* Copyright (c) 2022 Raspberry Pi (Trading) Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _HARDWARE_RISCV_
#define _HARDWARE_RISCV_
#include "pico.h"
#include "hardware/regs/rvcsr.h"
#ifndef __ASSEMBLER__
#ifdef __cplusplus
extern "C" {
#endif
/** \file hardware/riscv.h
* \defgroup hardware_riscv hardware_riscv
*
* \brief Accessors for standard RISC-V hardware (mainly CSRs)
*
*/
#define _riscv_read_csr(csrname) ({ \
uint32_t __csr_tmp_u32; \
asm volatile ("csrr %0, " #csrname : "=r" (__csr_tmp_u32)); \
__csr_tmp_u32; \
})
#define _riscv_write_csr(csrname, data) ({ \
if (__builtin_constant_p(data) && !((data) & -32u)) { \
asm volatile ("csrwi " #csrname ", %0" : : "i" (data)); \
} else { \
asm volatile ("csrw " #csrname ", %0" : : "r" (data)); \
} \
})
#define _riscv_set_csr(csrname, data) ({ \
if (__builtin_constant_p(data) && !((data) & -32u)) { \
asm volatile ("csrsi " #csrname ", %0" : : "i" (data)); \
} else { \
asm volatile ("csrs " #csrname ", %0" : : "r" (data)); \
} \
})
#define _riscv_clear_csr(csrname, data) ({ \
if (__builtin_constant_p(data) && !((data) & -32u)) { \
asm volatile ("csrci " #csrname ", %0" : : "i" (data)); \
} else { \
asm volatile ("csrc " #csrname ", %0" : : "r" (data)); \
} \
})
#define _riscv_read_write_csr(csrname, data) ({ \
uint32_t __csr_tmp_u32; \
if (__builtin_constant_p(data) && !((data) & -32u)) { \
asm volatile ("csrrwi %0, " #csrname ", %1": "=r" (__csr_tmp_u32) : "i" (data)); \
} else { \
asm volatile ("csrrw %0, " #csrname ", %1": "=r" (__csr_tmp_u32) : "r" (data)); \
} \
__csr_tmp_u32; \
})
#define _riscv_read_set_csr(csrname, data) ({ \
uint32_t __csr_tmp_u32; \
if (__builtin_constant_p(data) && !((data) & -32u)) { \
asm volatile ("csrrsi %0, " #csrname ", %1": "=r" (__csr_tmp_u32) : "i" (data)); \
} else { \
asm volatile ("csrrs %0, " #csrname ", %1": "=r" (__csr_tmp_u32) : "r" (data)); \
} \
__csr_tmp_u32; \
})
#define _riscv_read_clear_csr(csrname, data) ({ \
uint32_t __csr_tmp_u32; \
if (__builtin_constant_p(data) && !((data) & -32u)) { \
asm volatile ("csrrci %0, " #csrname ", %1": "=r" (__csr_tmp_u32) : "i" (data)); \
} else { \
asm volatile ("csrrc %0, " #csrname ", %1": "=r" (__csr_tmp_u32) : "r" (data)); \
} \
__csr_tmp_u32; \
})
// Argument macro expansion layer (CSR name may be a macro that expands to a
// CSR number, or it may be a bare name that the assembler knows about.)
#define riscv_read_csr(csrname) _riscv_read_csr(csrname)
#define riscv_write_csr(csrname, data) _riscv_write_csr(csrname, data)
#define riscv_set_csr(csrname, data) _riscv_set_csr(csrname, data)
#define riscv_clear_csr(csrname, data) _riscv_clear_csr(csrname, data)
#define riscv_read_write_csr(csrname, data) _riscv_read_write_csr(csrname, data)
#define riscv_read_set_csr(csrname, data) _riscv_read_set_csr(csrname, data)
#define riscv_read_clear_csr(csrname, data) _riscv_read_clear_csr(csrname, data)
// Helpers for encoding RISC-V immediates
// U format, e.g. lui
static inline uint32_t riscv_encode_imm_u(uint32_t x) {
return (x >> 12) << 12;
}
// I format, e.g. addi
static inline uint32_t riscv_encode_imm_i(uint32_t x) {
return (x & 0xfff) << 20;
}
// The U-format part of a U+I 32-bit immediate:
static inline uint32_t riscv_encode_imm_u_hi(uint32_t x) {
// We will add a signed 12 bit constant to the "lui" value,
// so we need to correct for the carry here.
x += (x & 0x800) << 1;
return riscv_encode_imm_u(x);
}
// B format, e.g. bgeu
static inline uint32_t riscv_encode_imm_b(uint32_t x) {
return
(((x >> 12) & 0x01) << 31) |
(((x >> 5) & 0x3f) << 25) |
(((x >> 1) & 0x0f) << 8) |
(((x >> 11) & 0x01) << 7);
}
// S format, e.g. sw
static inline uint32_t riscv_encode_imm_s(uint32_t x) {
return
(((x >> 5) & 0x7f) << 25) |
(((x >> 0) & 0x1f) << 7);
}
// J format, e.g. jal
static inline uint32_t riscv_encode_imm_j(uint32_t x) {
return
(((x >> 20) & 0x001) << 31) |
(((x >> 1) & 0x3ff) << 21) |
(((x >> 11) & 0x001) << 20) |
(((x >> 12) & 0x0ff) << 12);
}
// CJ format, e.g. c.jal
static inline uint16_t riscv_encode_imm_cj(uint32_t x) {
return (uint16_t)(
(((x >> 11) & 0x1) << 12) |
(((x >> 4) & 0x1) << 11) |
(((x >> 8) & 0x3) << 9) |
(((x >> 10) & 0x1) << 8) |
(((x >> 6) & 0x1) << 7) |
(((x >> 7) & 0x1) << 6) |
(((x >> 1) & 0x7) << 3) |
(((x >> 5) & 0x1) << 2)
);
}
// CB format, e.g. c.beqz
static inline uint16_t riscv_encode_imm_cb(uint32_t x) {
return (uint16_t)(
(((x >> 8) & 0x1) << 12) |
(((x >> 3) & 0x3) << 10) |
(((x >> 6) & 0x3) << 5) |
(((x >> 1) & 0x3) << 3) |
(((x >> 5) & 0x1) << 2)
);
}
// CI format, e.g. c.addi
static inline uint16_t riscv_encode_imm_ci(uint32_t x) {
return (uint16_t)(
(((x >> 5) & 0x01) << 12) |
(((x >> 0) & 0x1f) << 2)
);
}
#ifdef __cplusplus
}
#endif
#endif
#endif

145
arch/arm/src/rp23xx/hardware/riscv_platform_timer.h
View file

@ -1,145 +0,0 @@
#ifndef _HARDWARE_RISCV_PLATFORM_TIMER_
#define _HARDWARE_RISCV_PLATFORM_TIMER_
#ifdef __cplusplus
extern "C" {
#endif
#include "pico.h"
#include "hardware/structs/sio.h"
/** \file hardware/riscv_platform_timer.h
* \defgroup hardware_riscv_platform_timer hardware_riscv_platform_timer
*
* \brief Accessors for standard RISC-V platform timer (mtime/mtimecmp), available on
* Raspberry Pi microcontrollers with RISC-V processors
*
* Note this header can be used by Arm as well as RISC-V processors, as the
* timer is a memory-mapped peripheral external to the processors. The name
* refers to this timer being a standard RISC-V peripheral.
*
*/
/*! \brief Enable or disable the RISC-V platform timer
* \ingroup hardware_riscv_platform_timer
*
* This enables and disables the counting of the RISC-V platform timer. It
* does not enable or disable the interrupts, which are asserted
* unconditionally when a given core's mtimecmp/mtimecmph registers are
* greater than the current 64-bit value of the mtime/mtimeh registers.
*
* \param enabled Pass true to enable, false to disable
*/
static inline void riscv_timer_set_enabled(bool enabled) {
if (enabled) {
// Note atomic rwtype is not supported on SIO
sio_hw->mtime_ctrl |= SIO_MTIME_CTRL_EN_BITS;
} else {
sio_hw->mtime_ctrl &= ~SIO_MTIME_CTRL_EN_BITS;
}
}
/*! \brief Configure the RISC-V platform timer to run at full system clock speed
* \ingroup hardware_riscv_platform_timer
*
* \param fullspeed Pass true to increment at system clock speed, false to
* increment at the frequency defined by the system tick generator
* (the `ticks` block)
*/
static inline void riscv_timer_set_fullspeed(bool fullspeed) {
if (fullspeed) {
sio_hw->mtime_ctrl |= SIO_MTIME_CTRL_FULLSPEED_BITS;
} else {
sio_hw->mtime_ctrl &= ~SIO_MTIME_CTRL_FULLSPEED_BITS;
}
}
/*! \brief Read the RISC-V platform timer
* \ingroup hardware_riscv_platform_timer
*
* \return Current 64-bit mtime value
*/
static inline uint64_t riscv_timer_get_mtime(void) {
// Read procedure from RISC-V ISA manual to avoid being off by 2**32 on
// low half rollover -- note this loop generally executes only once, and
// should never execute more than twice:
uint32_t h0, l, h1;
do {
h0 = sio_hw->mtimeh;
l = sio_hw->mtime;
h1 = sio_hw->mtimeh;
} while (h0 != h1);
return l | (uint64_t)h1 << 32;
}
/*! \brief Update the RISC-V platform timer
* \ingroup hardware_riscv_platform_timer
*
* This function should only be called when the timer is disabled via
* riscv_timer_set_enabled(). Note also that unlike the mtimecmp comparison
* values, mtime is *not* core-local, so updates on one core will be visible
* to the other core.
*
* \param mtime New value to set the RISC-V platform timer to
*/
static inline void riscv_timer_set_mtime(uint64_t mtime) {
// This ought really only be done when the timer is stopped, but we can
// make things a bit safer by clearing the low half of the counter, then
// writing high half, then low half. This protects against the low half
// rolling over, and largely avoids getting an intermediate value that is
// higher than either the original or new value, if the timer is running.
//
// Note that on RP2350, mtime is shared between the two cores!(mtimcemp is
// core-local however.)
sio_hw->mtime = 0;
sio_hw->mtimeh = mtime >> 32;
sio_hw->mtime = mtime & 0xffffffffu;
}
/*! \brief Get the current RISC-V platform timer mtimecmp value for this core
* \ingroup hardware_riscv_platform_timer
*
* Get the current mtimecmp value for the calling core. This function is
* interrupt-safe as long as timer interrupts only increase the value of
* mtimecmp. Otherwise, it must be called with timer interrupts disabled.
*
* \return Current value of mtimecmp
*/
static inline uint64_t riscv_timer_get_mtimecmp(void) {
// Use the same procedure as reading mtime, which should be safe assuming
// mtimecmp increases monotonically with successive interrupts.
uint32_t h0, l, h1;
do {
h0 = sio_hw->mtimecmph;
l = sio_hw->mtimecmp;
h1 = sio_hw->mtimecmph;
} while (h0 != h1);
return l | (uint64_t)h1 << 32;
}
/*! \brief Set a new RISC-V platform timer interrupt comparison value (mtimecmp) for this core
* \ingroup hardware_riscv_platform_timer
*
* This function updates the mtimecmp value for the current core. The calling
* core's RISC-V platform timer interrupt is asserted whenever the 64-bit
* mtime value (stored in 32-bit mtime/mtimeh registers) is greater than or
* equal to this core's current mtime/mtimecmph value.
*
* \param mtime New value to set the RISC-V platform timer to
*/
static inline void riscv_timer_set_mtimecmp(uint64_t mtimecmp) {
// Use write procedure from RISC-V ISA manual to avoid causing a spurious
// interrupt when updating the two halves of mtimecmp.
// No lower than original:
sio_hw->mtimecmp = -1u;
// No lower than original, no lower than new (assuming new >= original):
sio_hw->mtimecmph = mtimecmp >> 32;
// Equal to new:
sio_hw->mtimecmp = mtimecmp & 0xffffffffu;
}
#ifdef __cplusplus
}
#endif
#endif

663
arch/arm/src/rp23xx/hardware/rp23xx_accessctrl.h Normal file
View file

@ -0,0 +1,663 @@
/****************************************************************************
* arch/arm/src/rp23xx/hardware/rp23xx_accessctrl.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_RP23XX_HARDWARE_RP23XX_ACCESSCTRL_H
#define __ARCH_ARM_SRC_RP23XX_HARDWARE_RP23XX_ACCESSCTRL_H
/****************************************************************************
* Included Files
****************************************************************************/
#include "hardware/rp23xx_memorymap.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Register offsets *********************************************************/
#define RP23XX_ACCESSCTRL_LOCK_OFFSET 0x00000000
#define RP23XX_ACCESSCTRL_FORCE_CORE_NS_OFFSET 0x00000004
#define RP23XX_ACCESSCTRL_CFGRESET_OFFSET 0x00000008
#define RP23XX_ACCESSCTRL_GPIO_NSMASK0_OFFSET 0x0000000c
#define RP23XX_ACCESSCTRL_GPIO_NSMASK1_OFFSET 0x00000010
#define RP23XX_ACCESSCTRL_ROM_OFFSET 0x00000014
#define RP23XX_ACCESSCTRL_XIP_MAIN_OFFSET 0x00000018
#define RP23XX_ACCESSCTRL_SRAM0_OFFSET 0x0000001c
#define RP23XX_ACCESSCTRL_SRAM1_OFFSET 0x00000020
#define RP23XX_ACCESSCTRL_SRAM2_OFFSET 0x00000024
#define RP23XX_ACCESSCTRL_SRAM3_OFFSET 0x00000028
#define RP23XX_ACCESSCTRL_SRAM4_OFFSET 0x0000002c
#define RP23XX_ACCESSCTRL_SRAM5_OFFSET 0x00000030
#define RP23XX_ACCESSCTRL_SRAM6_OFFSET 0x00000034
#define RP23XX_ACCESSCTRL_SRAM7_OFFSET 0x00000038
#define RP23XX_ACCESSCTRL_SRAM8_OFFSET 0x0000003c
#define RP23XX_ACCESSCTRL_SRAM9_OFFSET 0x00000040
#define RP23XX_ACCESSCTRL_DMA_OFFSET 0x00000044
#define RP23XX_ACCESSCTRL_USBCTRL_OFFSET 0x00000048
#define RP23XX_ACCESSCTRL_PIO0_OFFSET 0x0000004c
#define RP23XX_ACCESSCTRL_PIO1_OFFSET 0x00000050
#define RP23XX_ACCESSCTRL_PIO2_OFFSET 0x00000054
#define RP23XX_ACCESSCTRL_CORESIGHT_TRACE_OFFSET 0x00000058
#define RP23XX_ACCESSCTRL_CORESIGHT_PERIPH_OFFSET 0x0000005c
#define RP23XX_ACCESSCTRL_SYSINFO_OFFSET 0x00000060
#define RP23XX_ACCESSCTRL_RESETS_OFFSET 0x00000064
#define RP23XX_ACCESSCTRL_IO_BANK0_OFFSET 0x00000068
#define RP23XX_ACCESSCTRL_IO_BANK1_OFFSET 0x0000006c
#define RP23XX_ACCESSCTRL_PADS_BANK0_OFFSET 0x00000070
#define RP23XX_ACCESSCTRL_PADS_QSPI_OFFSET 0x00000074
#define RP23XX_ACCESSCTRL_BUSCTRL_OFFSET 0x00000078
#define RP23XX_ACCESSCTRL_ADC0_OFFSET 0x0000007c
#define RP23XX_ACCESSCTRL_HSTX_OFFSET 0x00000080
#define RP23XX_ACCESSCTRL_I2C0_OFFSET 0x00000084
#define RP23XX_ACCESSCTRL_I2C1_OFFSET 0x00000088
#define RP23XX_ACCESSCTRL_PWM_OFFSET 0x0000008c
#define RP23XX_ACCESSCTRL_SPI0_OFFSET 0x00000090
#define RP23XX_ACCESSCTRL_SPI1_OFFSET 0x00000094
#define RP23XX_ACCESSCTRL_TIMER0_OFFSET 0x00000098
#define RP23XX_ACCESSCTRL_TIMER1_OFFSET 0x0000009c
#define RP23XX_ACCESSCTRL_UART0_OFFSET 0x000000a0
#define RP23XX_ACCESSCTRL_UART1_OFFSET 0x000000a4
#define RP23XX_ACCESSCTRL_OTP_OFFSET 0x000000a8
#define RP23XX_ACCESSCTRL_TBMAN_OFFSET 0x000000ac
#define RP23XX_ACCESSCTRL_POWMAN_OFFSET 0x000000b0
#define RP23XX_ACCESSCTRL_TRNG_OFFSET 0x000000b4
#define RP23XX_ACCESSCTRL_SHA256_OFFSET 0x000000b8
#define RP23XX_ACCESSCTRL_SYSCFG_OFFSET 0x000000bc
#define RP23XX_ACCESSCTRL_CLOCKS_OFFSET 0x000000c0
#define RP23XX_ACCESSCTRL_XOSC_OFFSET 0x000000c4
#define RP23XX_ACCESSCTRL_ROSC_OFFSET 0x000000c8
#define RP23XX_ACCESSCTRL_PLL_SYS_OFFSET 0x000000cc
#define RP23XX_ACCESSCTRL_PLL_USB_OFFSET 0x000000d0
#define RP23XX_ACCESSCTRL_TICKS_OFFSET 0x000000d4
#define RP23XX_ACCESSCTRL_WATCHDOG_OFFSET 0x000000d8
#define RP23XX_ACCESSCTRL_RSM_OFFSET 0x000000dc
#define RP23XX_ACCESSCTRL_XIP_CTRL_OFFSET 0x000000e0
#define RP23XX_ACCESSCTRL_XIP_QMI_OFFSET 0x000000e4
#define RP23XX_ACCESSCTRL_XIP_AUX_OFFSET 0x000000e8
/* Register definitions *****************************************************/
#define RP23XX_ACCESSCTRL_LOCK (RP23XX_ACCESSCTRL_BASE + RP23XX_ACCESSCTRL_LOCK_OFFSET)
#define RP23XX_ACCESSCTRL_FORCE_CORE_NS (RP23XX_ACCESSCTRL_BASE + RP23XX_ACCESSCTRL_FORCE_CORE_NS_OFFSET)
#define RP23XX_ACCESSCTRL_CFGRESET (RP23XX_ACCESSCTRL_BASE + RP23XX_ACCESSCTRL_CFGRESET_OFFSET)
#define RP23XX_ACCESSCTRL_GPIO_NSMASK0 (RP23XX_ACCESSCTRL_BASE + RP23XX_ACCESSCTRL_GPIO_NSMASK0_OFFSET)
#define RP23XX_ACCESSCTRL_GPIO_NSMASK1 (RP23XX_ACCESSCTRL_BASE + RP23XX_ACCESSCTRL_GPIO_NSMASK1_OFFSET)
#define RP23XX_ACCESSCTRL_ROM (RP23XX_ACCESSCTRL_BASE + RP23XX_ACCESSCTRL_ROM_OFFSET)
#define RP23XX_ACCESSCTRL_XIP_MAIN (RP23XX_ACCESSCTRL_BASE + RP23XX_ACCESSCTRL_XIP_MAIN_OFFSET)
#define RP23XX_ACCESSCTRL_SRAM0 (RP23XX_ACCESSCTRL_BASE + RP23XX_ACCESSCTRL_SRAM0_OFFSET)
#define RP23XX_ACCESSCTRL_SRAM1 (RP23XX_ACCESSCTRL_BASE + RP23XX_ACCESSCTRL_SRAM1_OFFSET)
#define RP23XX_ACCESSCTRL_SRAM2 (RP23XX_ACCESSCTRL_BASE + RP23XX_ACCESSCTRL_SRAM2_OFFSET)
#define RP23XX_ACCESSCTRL_SRAM3 (RP23XX_ACCESSCTRL_BASE + RP23XX_ACCESSCTRL_SRAM3_OFFSET)
#define RP23XX_ACCESSCTRL_SRAM4 (RP23XX_ACCESSCTRL_BASE + RP23XX_ACCESSCTRL_SRAM4_OFFSET)
#define RP23XX_ACCESSCTRL_SRAM5 (RP23XX_ACCESSCTRL_BASE + RP23XX_ACCESSCTRL_SRAM5_OFFSET)
#define RP23XX_ACCESSCTRL_SRAM6 (RP23XX_ACCESSCTRL_BASE + RP23XX_ACCESSCTRL_SRAM6_OFFSET)
#define RP23XX_ACCESSCTRL_SRAM7 (RP23XX_ACCESSCTRL_BASE + RP23XX_ACCESSCTRL_SRAM7_OFFSET)
#define RP23XX_ACCESSCTRL_SRAM8 (RP23XX_ACCESSCTRL_BASE + RP23XX_ACCESSCTRL_SRAM8_OFFSET)
#define RP23XX_ACCESSCTRL_SRAM9 (RP23XX_ACCESSCTRL_BASE + RP23XX_ACCESSCTRL_SRAM9_OFFSET)
#define RP23XX_ACCESSCTRL_DMA (RP23XX_ACCESSCTRL_BASE + RP23XX_ACCESSCTRL_DMA_OFFSET)
#define RP23XX_ACCESSCTRL_USBCTRL (RP23XX_ACCESSCTRL_BASE + RP23XX_ACCESSCTRL_USBCTRL_OFFSET)
#define RP23XX_ACCESSCTRL_PIO0 (RP23XX_ACCESSCTRL_BASE + RP23XX_ACCESSCTRL_PIO0_OFFSET)
#define RP23XX_ACCESSCTRL_PIO1 (RP23XX_ACCESSCTRL_BASE + RP23XX_ACCESSCTRL_PIO1_OFFSET)
#define RP23XX_ACCESSCTRL_PIO2 (RP23XX_ACCESSCTRL_BASE + RP23XX_ACCESSCTRL_PIO2_OFFSET)
#define RP23XX_ACCESSCTRL_CORESIGHT_TRACE (RP23XX_ACCESSCTRL_BASE + RP23XX_ACCESSCTRL_CORESIGHT_TRACE_OFFSET)
#define RP23XX_ACCESSCTRL_CORESIGHT_PERIPH (RP23XX_ACCESSCTRL_BASE + RP23XX_ACCESSCTRL_CORESIGHT_PERIPH_OFFSET)
#define RP23XX_ACCESSCTRL_SYSINFO (RP23XX_ACCESSCTRL_BASE + RP23XX_ACCESSCTRL_SYSINFO_OFFSET)
#define RP23XX_ACCESSCTRL_RESETS (RP23XX_ACCESSCTRL_BASE + RP23XX_ACCESSCTRL_RESETS_OFFSET)
#define RP23XX_ACCESSCTRL_IO_BANK0 (RP23XX_ACCESSCTRL_BASE + RP23XX_ACCESSCTRL_IO_BANK0_OFFSET)
#define RP23XX_ACCESSCTRL_IO_BANK1 (RP23XX_ACCESSCTRL_BASE + RP23XX_ACCESSCTRL_IO_BANK1_OFFSET)
#define RP23XX_ACCESSCTRL_PADS_BANK0 (RP23XX_ACCESSCTRL_BASE + RP23XX_ACCESSCTRL_PADS_BANK0_OFFSET)
#define RP23XX_ACCESSCTRL_PADS_QSPI (RP23XX_ACCESSCTRL_BASE + RP23XX_ACCESSCTRL_PADS_QSPI_OFFSET)
#define RP23XX_ACCESSCTRL_BUSCTRL (RP23XX_ACCESSCTRL_BASE + RP23XX_ACCESSCTRL_BUSCTRL_OFFSET)
#define RP23XX_ACCESSCTRL_ADC0 (RP23XX_ACCESSCTRL_BASE + RP23XX_ACCESSCTRL_ADC0_OFFSET)
#define RP23XX_ACCESSCTRL_HSTX (RP23XX_ACCESSCTRL_BASE + RP23XX_ACCESSCTRL_HSTX_OFFSET)
#define RP23XX_ACCESSCTRL_I2C0 (RP23XX_ACCESSCTRL_BASE + RP23XX_ACCESSCTRL_I2C0_OFFSET)
#define RP23XX_ACCESSCTRL_I2C1 (RP23XX_ACCESSCTRL_BASE + RP23XX_ACCESSCTRL_I2C1_OFFSET)
#define RP23XX_ACCESSCTRL_PWM (RP23XX_ACCESSCTRL_BASE + RP23XX_ACCESSCTRL_PWM_OFFSET)
#define RP23XX_ACCESSCTRL_SPI0 (RP23XX_ACCESSCTRL_BASE + RP23XX_ACCESSCTRL_SPI0_OFFSET)
#define RP23XX_ACCESSCTRL_SPI1 (RP23XX_ACCESSCTRL_BASE + RP23XX_ACCESSCTRL_SPI1_OFFSET)
#define RP23XX_ACCESSCTRL_TIMER0 (RP23XX_ACCESSCTRL_BASE + RP23XX_ACCESSCTRL_TIMER0_OFFSET)
#define RP23XX_ACCESSCTRL_TIMER1 (RP23XX_ACCESSCTRL_BASE + RP23XX_ACCESSCTRL_TIMER1_OFFSET)
#define RP23XX_ACCESSCTRL_UART0 (RP23XX_ACCESSCTRL_BASE + RP23XX_ACCESSCTRL_UART0_OFFSET)
#define RP23XX_ACCESSCTRL_UART1 (RP23XX_ACCESSCTRL_BASE + RP23XX_ACCESSCTRL_UART1_OFFSET)
#define RP23XX_ACCESSCTRL_OTP (RP23XX_ACCESSCTRL_BASE + RP23XX_ACCESSCTRL_OTP_OFFSET)
#define RP23XX_ACCESSCTRL_TBMAN (RP23XX_ACCESSCTRL_BASE + RP23XX_ACCESSCTRL_TBMAN_OFFSET)
#define RP23XX_ACCESSCTRL_POWMAN (RP23XX_ACCESSCTRL_BASE + RP23XX_ACCESSCTRL_POWMAN_OFFSET)
#define RP23XX_ACCESSCTRL_TRNG (RP23XX_ACCESSCTRL_BASE + RP23XX_ACCESSCTRL_TRNG_OFFSET)
#define RP23XX_ACCESSCTRL_SHA256 (RP23XX_ACCESSCTRL_BASE + RP23XX_ACCESSCTRL_SHA256_OFFSET)
#define RP23XX_ACCESSCTRL_SYSCFG (RP23XX_ACCESSCTRL_BASE + RP23XX_ACCESSCTRL_SYSCFG_OFFSET)
#define RP23XX_ACCESSCTRL_CLOCKS (RP23XX_ACCESSCTRL_BASE + RP23XX_ACCESSCTRL_CLOCKS_OFFSET)
#define RP23XX_ACCESSCTRL_XOSC (RP23XX_ACCESSCTRL_BASE + RP23XX_ACCESSCTRL_XOSC_OFFSET)
#define RP23XX_ACCESSCTRL_ROSC (RP23XX_ACCESSCTRL_BASE + RP23XX_ACCESSCTRL_ROSC_OFFSET)
#define RP23XX_ACCESSCTRL_PLL_SYS (RP23XX_ACCESSCTRL_BASE + RP23XX_ACCESSCTRL_PLL_SYS_OFFSET)
#define RP23XX_ACCESSCTRL_PLL_USB (RP23XX_ACCESSCTRL_BASE + RP23XX_ACCESSCTRL_PLL_USB_OFFSET)
#define RP23XX_ACCESSCTRL_TICKS (RP23XX_ACCESSCTRL_BASE + RP23XX_ACCESSCTRL_TICKS_OFFSET)
#define RP23XX_ACCESSCTRL_WATCHDOG (RP23XX_ACCESSCTRL_BASE + RP23XX_ACCESSCTRL_WATCHDOG_OFFSET)
#define RP23XX_ACCESSCTRL_RSM (RP23XX_ACCESSCTRL_BASE + RP23XX_ACCESSCTRL_RSM_OFFSET)
#define RP23XX_ACCESSCTRL_XIP_CTRL (RP23XX_ACCESSCTRL_BASE + RP23XX_ACCESSCTRL_XIP_CTRL_OFFSET)
#define RP23XX_ACCESSCTRL_XIP_QMI (RP23XX_ACCESSCTRL_BASE + RP23XX_ACCESSCTRL_XIP_QMI_OFFSET)
#define RP23XX_ACCESSCTRL_XIP_AUX (RP23XX_ACCESSCTRL_BASE + RP23XX_ACCESSCTRL_XIP_AUX_OFFSET)
/* Register bit definitions *************************************************/
#define RP23XX_ACCESSCTRL_LOCK_MASK (0x0000000f)
#define RP23XX_ACCESSCTRL_LOCK_DEBUG_MASK (1 << 3)
#define RP23XX_ACCESSCTRL_LOCK_DMA_MASK (1 << 2)
#define RP23XX_ACCESSCTRL_LOCK_CORE1_MASK (1 << 1)
#define RP23XX_ACCESSCTRL_LOCK_CORE0_MASK (1 << 0)
#define RP23XX_ACCESSCTRL_FORCE_CORE_NS_MASK (1 << 1)
#define RP23XX_ACCESSCTRL_FORCE_CORE_NS_CORE1_MASK (1 << 1)
#define RP23XX_ACCESSCTRL_CFGRESET_MASK (1 << 0)
#define RP23XX_ACCESSCTRL_GPIO_NSMASK0_MASK (0xffffffff)
#define RP23XX_ACCESSCTRL_GPIO_NSMASK1_MASK (0xff00ffff)
#define RP23XX_ACCESSCTRL_GPIO_NSMASK1_QSPI_SD_MASK (0xf0000000)
#define RP23XX_ACCESSCTRL_GPIO_NSMASK1_QSPI_CSN_MASK (1 << 27)
#define RP23XX_ACCESSCTRL_GPIO_NSMASK1_QSPI_SCK_MASK (1 << 26)
#define RP23XX_ACCESSCTRL_GPIO_NSMASK1_USB_DM_MASK (1 << 25)
#define RP23XX_ACCESSCTRL_GPIO_NSMASK1_USB_DP_MASK (1 << 24)
#define RP23XX_ACCESSCTRL_GPIO_NSMASK1_GPIO_MASK (0x0000ffff)
#define RP23XX_ACCESSCTRL_ROM_MASK (0x000000ff)
#define RP23XX_ACCESSCTRL_ROM_DBG_MASK (1 << 7)
#define RP23XX_ACCESSCTRL_ROM_DMA_MASK (1 << 6)
#define RP23XX_ACCESSCTRL_ROM_CORE1_MASK (1 << 5)
#define RP23XX_ACCESSCTRL_ROM_CORE0_MASK (1 << 4)
#define RP23XX_ACCESSCTRL_ROM_SP_MASK (1 << 3)
#define RP23XX_ACCESSCTRL_ROM_SU_MASK (1 << 2)
#define RP23XX_ACCESSCTRL_ROM_NSP_MASK (1 << 1)
#define RP23XX_ACCESSCTRL_ROM_NSU_MASK (1 << 0)
#define RP23XX_ACCESSCTRL_XIP_MAIN_MASK (0x000000ff)
#define RP23XX_ACCESSCTRL_XIP_MAIN_DBG_MASK (1 << 7)
#define RP23XX_ACCESSCTRL_XIP_MAIN_DMA_MASK (1 << 6)
#define RP23XX_ACCESSCTRL_XIP_MAIN_CORE1_MASK (1 << 5)
#define RP23XX_ACCESSCTRL_XIP_MAIN_CORE0_MASK (1 << 4)
#define RP23XX_ACCESSCTRL_XIP_MAIN_SP_MASK (1 << 3)
#define RP23XX_ACCESSCTRL_XIP_MAIN_SU_MASK (1 << 2)
#define RP23XX_ACCESSCTRL_XIP_MAIN_NSP_MASK (1 << 1)
#define RP23XX_ACCESSCTRL_XIP_MAIN_NSU_MASK (1 << 0)
#define RP23XX_ACCESSCTRL_SRAM0_MASK (0x000000ff)
#define RP23XX_ACCESSCTRL_SRAM0_DBG_MASK (1 << 7)
#define RP23XX_ACCESSCTRL_SRAM0_DMA_MASK (1 << 6)
#define RP23XX_ACCESSCTRL_SRAM0_CORE1_MASK (1 << 5)
#define RP23XX_ACCESSCTRL_SRAM0_CORE0_MASK (1 << 4)
#define RP23XX_ACCESSCTRL_SRAM0_SP_MASK (1 << 3)
#define RP23XX_ACCESSCTRL_SRAM0_SU_MASK (1 << 2)
#define RP23XX_ACCESSCTRL_SRAM0_NSP_MASK (1 << 1)
#define RP23XX_ACCESSCTRL_SRAM0_NSU_MASK (1 << 0)
#define RP23XX_ACCESSCTRL_SRAM1_MASK (0x000000ff)
#define RP23XX_ACCESSCTRL_SRAM1_DBG_MASK (1 << 7)
#define RP23XX_ACCESSCTRL_SRAM1_DMA_MASK (1 << 6)
#define RP23XX_ACCESSCTRL_SRAM1_CORE1_MASK (1 << 5)
#define RP23XX_ACCESSCTRL_SRAM1_CORE0_MASK (1 << 4)
#define RP23XX_ACCESSCTRL_SRAM1_SP_MASK (1 << 3)
#define RP23XX_ACCESSCTRL_SRAM1_SU_MASK (1 << 2)
#define RP23XX_ACCESSCTRL_SRAM1_NSP_MASK (1 << 1)
#define RP23XX_ACCESSCTRL_SRAM1_NSU_MASK (1 << 0)
#define RP23XX_ACCESSCTRL_SRAM2_MASK (0x000000ff)
#define RP23XX_ACCESSCTRL_SRAM2_DBG_MASK (1 << 7)
#define RP23XX_ACCESSCTRL_SRAM2_DMA_MASK (1 << 6)
#define RP23XX_ACCESSCTRL_SRAM2_CORE1_MASK (1 << 5)
#define RP23XX_ACCESSCTRL_SRAM2_CORE0_MASK (1 << 4)
#define RP23XX_ACCESSCTRL_SRAM2_SP_MASK (1 << 3)
#define RP23XX_ACCESSCTRL_SRAM2_SU_MASK (1 << 2)
#define RP23XX_ACCESSCTRL_SRAM2_NSP_MASK (1 << 1)
#define RP23XX_ACCESSCTRL_SRAM2_NSU_MASK (1 << 0)
#define RP23XX_ACCESSCTRL_SRAM3_MASK (0x000000ff)
#define RP23XX_ACCESSCTRL_SRAM3_DBG_MASK (1 << 7)
#define RP23XX_ACCESSCTRL_SRAM3_DMA_MASK (1 << 6)
#define RP23XX_ACCESSCTRL_SRAM3_CORE1_MASK (1 << 5)
#define RP23XX_ACCESSCTRL_SRAM3_CORE0_MASK (1 << 4)
#define RP23XX_ACCESSCTRL_SRAM3_SP_MASK (1 << 3)
#define RP23XX_ACCESSCTRL_SRAM3_SU_MASK (1 << 2)
#define RP23XX_ACCESSCTRL_SRAM3_NSP_MASK (1 << 1)
#define RP23XX_ACCESSCTRL_SRAM3_NSU_MASK (1 << 0)
#define RP23XX_ACCESSCTRL_SRAM4_MASK (0x000000ff)
#define RP23XX_ACCESSCTRL_SRAM4_DBG_MASK (1 << 7)
#define RP23XX_ACCESSCTRL_SRAM4_DMA_MASK (1 << 6)
#define RP23XX_ACCESSCTRL_SRAM4_CORE1_MASK (1 << 5)
#define RP23XX_ACCESSCTRL_SRAM4_CORE0_MASK (1 << 4)
#define RP23XX_ACCESSCTRL_SRAM4_SP_MASK (1 << 3)
#define RP23XX_ACCESSCTRL_SRAM4_SU_MASK (1 << 2)
#define RP23XX_ACCESSCTRL_SRAM4_NSP_MASK (1 << 1)
#define RP23XX_ACCESSCTRL_SRAM4_NSU_MASK (1 << 0)
#define RP23XX_ACCESSCTRL_SRAM5_MASK (0x000000ff)
#define RP23XX_ACCESSCTRL_SRAM5_DBG_MASK (1 << 7)
#define RP23XX_ACCESSCTRL_SRAM5_DMA_MASK (1 << 6)
#define RP23XX_ACCESSCTRL_SRAM5_CORE1_MASK (1 << 5)
#define RP23XX_ACCESSCTRL_SRAM5_CORE0_MASK (1 << 4)
#define RP23XX_ACCESSCTRL_SRAM5_SP_MASK (1 << 3)
#define RP23XX_ACCESSCTRL_SRAM5_SU_MASK (1 << 2)
#define RP23XX_ACCESSCTRL_SRAM5_NSP_MASK (1 << 1)
#define RP23XX_ACCESSCTRL_SRAM5_NSU_MASK (1 << 0)
#define RP23XX_ACCESSCTRL_SRAM6_MASK (0x000000ff)
#define RP23XX_ACCESSCTRL_SRAM6_DBG_MASK (1 << 7)
#define RP23XX_ACCESSCTRL_SRAM6_DMA_MASK (1 << 6)
#define RP23XX_ACCESSCTRL_SRAM6_CORE1_MASK (1 << 5)
#define RP23XX_ACCESSCTRL_SRAM6_CORE0_MASK (1 << 4)
#define RP23XX_ACCESSCTRL_SRAM6_SP_MASK (1 << 3)
#define RP23XX_ACCESSCTRL_SRAM6_SU_MASK (1 << 2)
#define RP23XX_ACCESSCTRL_SRAM6_NSP_MASK (1 << 1)
#define RP23XX_ACCESSCTRL_SRAM6_NSU_MASK (1 << 0)
#define RP23XX_ACCESSCTRL_SRAM7_MASK (0x000000ff)
#define RP23XX_ACCESSCTRL_SRAM7_DBG_MASK (1 << 7)
#define RP23XX_ACCESSCTRL_SRAM7_DMA_MASK (1 << 6)
#define RP23XX_ACCESSCTRL_SRAM7_CORE1_MASK (1 << 5)
#define RP23XX_ACCESSCTRL_SRAM7_CORE0_MASK (1 << 4)
#define RP23XX_ACCESSCTRL_SRAM7_SP_MASK (1 << 3)
#define RP23XX_ACCESSCTRL_SRAM7_SU_MASK (1 << 2)
#define RP23XX_ACCESSCTRL_SRAM7_NSP_MASK (1 << 1)
#define RP23XX_ACCESSCTRL_SRAM7_NSU_MASK (1 << 0)
#define RP23XX_ACCESSCTRL_SRAM8_MASK (0x000000ff)
#define RP23XX_ACCESSCTRL_SRAM8_DBG_MASK (1 << 7)
#define RP23XX_ACCESSCTRL_SRAM8_DMA_MASK (1 << 6)
#define RP23XX_ACCESSCTRL_SRAM8_CORE1_MASK (1 << 5)
#define RP23XX_ACCESSCTRL_SRAM8_CORE0_MASK (1 << 4)
#define RP23XX_ACCESSCTRL_SRAM8_SP_MASK (1 << 3)
#define RP23XX_ACCESSCTRL_SRAM8_SU_MASK (1 << 2)
#define RP23XX_ACCESSCTRL_SRAM8_NSP_MASK (1 << 1)
#define RP23XX_ACCESSCTRL_SRAM8_NSU_MASK (1 << 0)
#define RP23XX_ACCESSCTRL_SRAM9_MASK (0x000000ff)
#define RP23XX_ACCESSCTRL_SRAM9_DBG_MASK (1 << 7)
#define RP23XX_ACCESSCTRL_SRAM9_DMA_MASK (1 << 6)
#define RP23XX_ACCESSCTRL_SRAM9_CORE1_MASK (1 << 5)
#define RP23XX_ACCESSCTRL_SRAM9_CORE0_MASK (1 << 4)
#define RP23XX_ACCESSCTRL_SRAM9_SP_MASK (1 << 3)
#define RP23XX_ACCESSCTRL_SRAM9_SU_MASK (1 << 2)
#define RP23XX_ACCESSCTRL_SRAM9_NSP_MASK (1 << 1)
#define RP23XX_ACCESSCTRL_SRAM9_NSU_MASK (1 << 0)
#define RP23XX_ACCESSCTRL_DMA_MASK (0x000000ff)
#define RP23XX_ACCESSCTRL_DMA_DBG_MASK (1 << 7)
#define RP23XX_ACCESSCTRL_DMA_DMA_MASK (1 << 6)
#define RP23XX_ACCESSCTRL_DMA_CORE1_MASK (1 << 5)
#define RP23XX_ACCESSCTRL_DMA_CORE0_MASK (1 << 4)
#define RP23XX_ACCESSCTRL_DMA_SP_MASK (1 << 3)
#define RP23XX_ACCESSCTRL_DMA_SU_MASK (1 << 2)
#define RP23XX_ACCESSCTRL_DMA_NSP_MASK (1 << 1)
#define RP23XX_ACCESSCTRL_DMA_NSU_MASK (1 << 0)
#define RP23XX_ACCESSCTRL_USBCTRL_MASK (0x000000ff)
#define RP23XX_ACCESSCTRL_USBCTRL_DBG_MASK (1 << 7)
#define RP23XX_ACCESSCTRL_USBCTRL_DMA_MASK (1 << 6)
#define RP23XX_ACCESSCTRL_USBCTRL_CORE1_MASK (1 << 5)
#define RP23XX_ACCESSCTRL_USBCTRL_CORE0_MASK (1 << 4)
#define RP23XX_ACCESSCTRL_USBCTRL_SP_MASK (1 << 3)
#define RP23XX_ACCESSCTRL_USBCTRL_SU_MASK (1 << 2)
#define RP23XX_ACCESSCTRL_USBCTRL_NSP_MASK (1 << 1)
#define RP23XX_ACCESSCTRL_USBCTRL_NSU_MASK (1 << 0)
#define RP23XX_ACCESSCTRL_PIO0_MASK (0x000000ff)
#define RP23XX_ACCESSCTRL_PIO0_DBG_MASK (1 << 7)
#define RP23XX_ACCESSCTRL_PIO0_DMA_MASK (1 << 6)
#define RP23XX_ACCESSCTRL_PIO0_CORE1_MASK (1 << 5)
#define RP23XX_ACCESSCTRL_PIO0_CORE0_MASK (1 << 4)
#define RP23XX_ACCESSCTRL_PIO0_SP_MASK (1 << 3)
#define RP23XX_ACCESSCTRL_PIO0_SU_MASK (1 << 2)
#define RP23XX_ACCESSCTRL_PIO0_NSP_MASK (1 << 1)
#define RP23XX_ACCESSCTRL_PIO0_NSU_MASK (1 << 0)
#define RP23XX_ACCESSCTRL_PIO1_MASK (0x000000ff)
#define RP23XX_ACCESSCTRL_PIO1_DBG_MASK (1 << 7)
#define RP23XX_ACCESSCTRL_PIO1_DMA_MASK (1 << 6)
#define RP23XX_ACCESSCTRL_PIO1_CORE1_MASK (1 << 5)
#define RP23XX_ACCESSCTRL_PIO1_CORE0_MASK (1 << 4)
#define RP23XX_ACCESSCTRL_PIO1_SP_MASK (1 << 3)
#define RP23XX_ACCESSCTRL_PIO1_SU_MASK (1 << 2)
#define RP23XX_ACCESSCTRL_PIO1_NSP_MASK (1 << 1)
#define RP23XX_ACCESSCTRL_PIO1_NSU_MASK (1 << 0)
#define RP23XX_ACCESSCTRL_PIO2_MASK (0x000000ff)
#define RP23XX_ACCESSCTRL_PIO2_DBG_MASK (1 << 7)
#define RP23XX_ACCESSCTRL_PIO2_DMA_MASK (1 << 6)
#define RP23XX_ACCESSCTRL_PIO2_CORE1_MASK (1 << 5)
#define RP23XX_ACCESSCTRL_PIO2_CORE0_MASK (1 << 4)
#define RP23XX_ACCESSCTRL_PIO2_SP_MASK (1 << 3)
#define RP23XX_ACCESSCTRL_PIO2_SU_MASK (1 << 2)
#define RP23XX_ACCESSCTRL_PIO2_NSP_MASK (1 << 1)
#define RP23XX_ACCESSCTRL_PIO2_NSU_MASK (1 << 0)
#define RP23XX_ACCESSCTRL_CORESIGHT_TRACE_MASK (0x000000ff)
#define RP23XX_ACCESSCTRL_CORESIGHT_TRACE_DBG_MASK (1 << 7)
#define RP23XX_ACCESSCTRL_CORESIGHT_TRACE_DMA_MASK (1 << 6)
#define RP23XX_ACCESSCTRL_CORESIGHT_TRACE_CORE1_MASK (1 << 5)
#define RP23XX_ACCESSCTRL_CORESIGHT_TRACE_CORE0_MASK (1 << 4)
#define RP23XX_ACCESSCTRL_CORESIGHT_TRACE_SP_MASK (1 << 3)
#define RP23XX_ACCESSCTRL_CORESIGHT_TRACE_SU_MASK (1 << 2)
#define RP23XX_ACCESSCTRL_CORESIGHT_TRACE_NSP_MASK (1 << 1)
#define RP23XX_ACCESSCTRL_CORESIGHT_TRACE_NSU_MASK (1 << 0)
#define RP23XX_ACCESSCTRL_CORESIGHT_PERIPH_MASK (0x000000ff)
#define RP23XX_ACCESSCTRL_CORESIGHT_PERIPH_DBG_MASK (1 << 7)
#define RP23XX_ACCESSCTRL_CORESIGHT_PERIPH_DMA_MASK (1 << 6)
#define RP23XX_ACCESSCTRL_CORESIGHT_PERIPH_CORE1_MASK (1 << 5)
#define RP23XX_ACCESSCTRL_CORESIGHT_PERIPH_CORE0_MASK (1 << 4)
#define RP23XX_ACCESSCTRL_CORESIGHT_PERIPH_SP_MASK (1 << 3)
#define RP23XX_ACCESSCTRL_CORESIGHT_PERIPH_SU_MASK (1 << 2)
#define RP23XX_ACCESSCTRL_CORESIGHT_PERIPH_NSP_MASK (1 << 1)
#define RP23XX_ACCESSCTRL_CORESIGHT_PERIPH_NSU_MASK (1 << 0)
#define RP23XX_ACCESSCTRL_SYSINFO_MASK (0x000000ff)
#define RP23XX_ACCESSCTRL_SYSINFO_DBG_MASK (1 << 7)
#define RP23XX_ACCESSCTRL_SYSINFO_DMA_MASK (1 << 6)
#define RP23XX_ACCESSCTRL_SYSINFO_CORE1_MASK (1 << 5)
#define RP23XX_ACCESSCTRL_SYSINFO_CORE0_MASK (1 << 4)
#define RP23XX_ACCESSCTRL_SYSINFO_SP_MASK (1 << 3)
#define RP23XX_ACCESSCTRL_SYSINFO_SU_MASK (1 << 2)
#define RP23XX_ACCESSCTRL_SYSINFO_NSP_MASK (1 << 1)
#define RP23XX_ACCESSCTRL_SYSINFO_NSU_MASK (1 << 0)
#define RP23XX_ACCESSCTRL_RESETS_MASK (0x000000ff)
#define RP23XX_ACCESSCTRL_RESETS_DBG_MASK (1 << 7)
#define RP23XX_ACCESSCTRL_RESETS_DMA_MASK (1 << 6)
#define RP23XX_ACCESSCTRL_RESETS_CORE1_MASK (1 << 5)
#define RP23XX_ACCESSCTRL_RESETS_CORE0_MASK (1 << 4)
#define RP23XX_ACCESSCTRL_RESETS_SP_MASK (1 << 3)
#define RP23XX_ACCESSCTRL_RESETS_SU_MASK (1 << 2)
#define RP23XX_ACCESSCTRL_RESETS_NSP_MASK (1 << 1)
#define RP23XX_ACCESSCTRL_RESETS_NSU_MASK (1 << 0)
#define RP23XX_ACCESSCTRL_IO_BANK0_MASK (0x000000ff)
#define RP23XX_ACCESSCTRL_IO_BANK0_DBG_MASK (1 << 7)
#define RP23XX_ACCESSCTRL_IO_BANK0_DMA_MASK (1 << 6)
#define RP23XX_ACCESSCTRL_IO_BANK0_CORE1_MASK (1 << 5)
#define RP23XX_ACCESSCTRL_IO_BANK0_CORE0_MASK (1 << 4)
#define RP23XX_ACCESSCTRL_IO_BANK0_SP_MASK (1 << 3)
#define RP23XX_ACCESSCTRL_IO_BANK0_SU_MASK (1 << 2)
#define RP23XX_ACCESSCTRL_IO_BANK0_NSP_MASK (1 << 1)
#define RP23XX_ACCESSCTRL_IO_BANK0_NSU_MASK (1 << 0)
#define RP23XX_ACCESSCTRL_IO_BANK1_MASK (0x000000ff)
#define RP23XX_ACCESSCTRL_IO_BANK1_DBG_MASK (1 << 7)
#define RP23XX_ACCESSCTRL_IO_BANK1_DMA_MASK (1 << 6)
#define RP23XX_ACCESSCTRL_IO_BANK1_CORE1_MASK (1 << 5)
#define RP23XX_ACCESSCTRL_IO_BANK1_CORE0_MASK (1 << 4)
#define RP23XX_ACCESSCTRL_IO_BANK1_SP_MASK (1 << 3)
#define RP23XX_ACCESSCTRL_IO_BANK1_SU_MASK (1 << 2)
#define RP23XX_ACCESSCTRL_IO_BANK1_NSP_MASK (1 << 1)
#define RP23XX_ACCESSCTRL_IO_BANK1_NSU_MASK (1 << 0)
#define RP23XX_ACCESSCTRL_PADS_BANK0_MASK (0x000000ff)
#define RP23XX_ACCESSCTRL_PADS_BANK0_DBG_MASK (1 << 7)
#define RP23XX_ACCESSCTRL_PADS_BANK0_DMA_MASK (1 << 6)
#define RP23XX_ACCESSCTRL_PADS_BANK0_CORE1_MASK (1 << 5)
#define RP23XX_ACCESSCTRL_PADS_BANK0_CORE0_MASK (1 << 4)
#define RP23XX_ACCESSCTRL_PADS_BANK0_SP_MASK (1 << 3)
#define RP23XX_ACCESSCTRL_PADS_BANK0_SU_MASK (1 << 2)
#define RP23XX_ACCESSCTRL_PADS_BANK0_NSP_MASK (1 << 1)
#define RP23XX_ACCESSCTRL_PADS_BANK0_NSU_MASK (1 << 0)
#define RP23XX_ACCESSCTRL_PADS_QSPI_MASK (0x000000ff)
#define RP23XX_ACCESSCTRL_PADS_QSPI_DBG_MASK (1 << 7)
#define RP23XX_ACCESSCTRL_PADS_QSPI_DMA_MASK (1 << 6)
#define RP23XX_ACCESSCTRL_PADS_QSPI_CORE1_MASK (1 << 5)
#define RP23XX_ACCESSCTRL_PADS_QSPI_CORE0_MASK (1 << 4)
#define RP23XX_ACCESSCTRL_PADS_QSPI_SP_MASK (1 << 3)
#define RP23XX_ACCESSCTRL_PADS_QSPI_SU_MASK (1 << 2)
#define RP23XX_ACCESSCTRL_PADS_QSPI_NSP_MASK (1 << 1)
#define RP23XX_ACCESSCTRL_PADS_QSPI_NSU_MASK (1 << 0)
#define RP23XX_ACCESSCTRL_BUSCTRL_MASK (0x000000ff)
#define RP23XX_ACCESSCTRL_BUSCTRL_DBG_MASK (1 << 7)
#define RP23XX_ACCESSCTRL_BUSCTRL_DMA_MASK (1 << 6)
#define RP23XX_ACCESSCTRL_BUSCTRL_CORE1_MASK (1 << 5)
#define RP23XX_ACCESSCTRL_BUSCTRL_CORE0_MASK (1 << 4)
#define RP23XX_ACCESSCTRL_BUSCTRL_SP_MASK (1 << 3)
#define RP23XX_ACCESSCTRL_BUSCTRL_SU_MASK (1 << 2)
#define RP23XX_ACCESSCTRL_BUSCTRL_NSP_MASK (1 << 1)
#define RP23XX_ACCESSCTRL_BUSCTRL_NSU_MASK (1 << 0)
#define RP23XX_ACCESSCTRL_ADC0_MASK (0x000000ff)
#define RP23XX_ACCESSCTRL_ADC0_DBG_MASK (1 << 7)
#define RP23XX_ACCESSCTRL_ADC0_DMA_MASK (1 << 6)
#define RP23XX_ACCESSCTRL_ADC0_CORE1_MASK (1 << 5)
#define RP23XX_ACCESSCTRL_ADC0_CORE0_MASK (1 << 4)
#define RP23XX_ACCESSCTRL_ADC0_SP_MASK (1 << 3)
#define RP23XX_ACCESSCTRL_ADC0_SU_MASK (1 << 2)
#define RP23XX_ACCESSCTRL_ADC0_NSP_MASK (1 << 1)
#define RP23XX_ACCESSCTRL_ADC0_NSU_MASK (1 << 0)
#define RP23XX_ACCESSCTRL_HSTX_MASK (0x000000ff)
#define RP23XX_ACCESSCTRL_HSTX_DBG_MASK (1 << 7)
#define RP23XX_ACCESSCTRL_HSTX_DMA_MASK (1 << 6)
#define RP23XX_ACCESSCTRL_HSTX_CORE1_MASK (1 << 5)
#define RP23XX_ACCESSCTRL_HSTX_CORE0_MASK (1 << 4)
#define RP23XX_ACCESSCTRL_HSTX_SP_MASK (1 << 3)
#define RP23XX_ACCESSCTRL_HSTX_SU_MASK (1 << 2)
#define RP23XX_ACCESSCTRL_HSTX_NSP_MASK (1 << 1)
#define RP23XX_ACCESSCTRL_HSTX_NSU_MASK (1 << 0)
#define RP23XX_ACCESSCTRL_I2C0_MASK (0x000000ff)
#define RP23XX_ACCESSCTRL_I2C0_DBG_MASK (1 << 7)
#define RP23XX_ACCESSCTRL_I2C0_DMA_MASK (1 << 6)
#define RP23XX_ACCESSCTRL_I2C0_CORE1_MASK (1 << 5)
#define RP23XX_ACCESSCTRL_I2C0_CORE0_MASK (1 << 4)
#define RP23XX_ACCESSCTRL_I2C0_SP_MASK (1 << 3)
#define RP23XX_ACCESSCTRL_I2C0_SU_MASK (1 << 2)
#define RP23XX_ACCESSCTRL_I2C0_NSP_MASK (1 << 1)
#define RP23XX_ACCESSCTRL_I2C0_NSU_MASK (1 << 0)
#define RP23XX_ACCESSCTRL_I2C1_MASK (0x000000ff)
#define RP23XX_ACCESSCTRL_I2C1_DBG_MASK (1 << 7)
#define RP23XX_ACCESSCTRL_I2C1_DMA_MASK (1 << 6)
#define RP23XX_ACCESSCTRL_I2C1_CORE1_MASK (1 << 5)
#define RP23XX_ACCESSCTRL_I2C1_CORE0_MASK (1 << 4)
#define RP23XX_ACCESSCTRL_I2C1_SP_MASK (1 << 3)
#define RP23XX_ACCESSCTRL_I2C1_SU_MASK (1 << 2)
#define RP23XX_ACCESSCTRL_I2C1_NSP_MASK (1 << 1)
#define RP23XX_ACCESSCTRL_I2C1_NSU_MASK (1 << 0)
#define RP23XX_ACCESSCTRL_PWM_MASK (0x000000ff)
#define RP23XX_ACCESSCTRL_PWM_DBG_MASK (1 << 7)
#define RP23XX_ACCESSCTRL_PWM_DMA_MASK (1 << 6)
#define RP23XX_ACCESSCTRL_PWM_CORE1_MASK (1 << 5)
#define RP23XX_ACCESSCTRL_PWM_CORE0_MASK (1 << 4)
#define RP23XX_ACCESSCTRL_PWM_SP_MASK (1 << 3)
#define RP23XX_ACCESSCTRL_PWM_SU_MASK (1 << 2)
#define RP23XX_ACCESSCTRL_PWM_NSP_MASK (1 << 1)
#define RP23XX_ACCESSCTRL_PWM_NSU_MASK (1 << 0)
#define RP23XX_ACCESSCTRL_SPI0_MASK (0x000000ff)
#define RP23XX_ACCESSCTRL_SPI0_DBG_MASK (1 << 7)
#define RP23XX_ACCESSCTRL_SPI0_DMA_MASK (1 << 6)
#define RP23XX_ACCESSCTRL_SPI0_CORE1_MASK (1 << 5)
#define RP23XX_ACCESSCTRL_SPI0_CORE0_MASK (1 << 4)
#define RP23XX_ACCESSCTRL_SPI0_SP_MASK (1 << 3)
#define RP23XX_ACCESSCTRL_SPI0_SU_MASK (1 << 2)
#define RP23XX_ACCESSCTRL_SPI0_NSP_MASK (1 << 1)
#define RP23XX_ACCESSCTRL_SPI0_NSU_MASK (1 << 0)
#define RP23XX_ACCESSCTRL_SPI1_MASK (0x000000ff)
#define RP23XX_ACCESSCTRL_SPI1_DBG_MASK (1 << 7)
#define RP23XX_ACCESSCTRL_SPI1_DMA_MASK (1 << 6)
#define RP23XX_ACCESSCTRL_SPI1_CORE1_MASK (1 << 5)
#define RP23XX_ACCESSCTRL_SPI1_CORE0_MASK (1 << 4)
#define RP23XX_ACCESSCTRL_SPI1_SP_MASK (1 << 3)
#define RP23XX_ACCESSCTRL_SPI1_SU_MASK (1 << 2)
#define RP23XX_ACCESSCTRL_SPI1_NSP_MASK (1 << 1)
#define RP23XX_ACCESSCTRL_SPI1_NSU_MASK (1 << 0)
#define RP23XX_ACCESSCTRL_TIMER0_MASK (0x000000ff)
#define RP23XX_ACCESSCTRL_TIMER0_DBG_MASK (1 << 7)
#define RP23XX_ACCESSCTRL_TIMER0_DMA_MASK (1 << 6)
#define RP23XX_ACCESSCTRL_TIMER0_CORE1_MASK (1 << 5)
#define RP23XX_ACCESSCTRL_TIMER0_CORE0_MASK (1 << 4)
#define RP23XX_ACCESSCTRL_TIMER0_SP_MASK (1 << 3)
#define RP23XX_ACCESSCTRL_TIMER0_SU_MASK (1 << 2)
#define RP23XX_ACCESSCTRL_TIMER0_NSP_MASK (1 << 1)
#define RP23XX_ACCESSCTRL_TIMER0_NSU_MASK (1 << 0)
#define RP23XX_ACCESSCTRL_TIMER1_MASK (0x000000ff)
#define RP23XX_ACCESSCTRL_TIMER1_DBG_MASK (1 << 7)
#define RP23XX_ACCESSCTRL_TIMER1_DMA_MASK (1 << 6)
#define RP23XX_ACCESSCTRL_TIMER1_CORE1_MASK (1 << 5)
#define RP23XX_ACCESSCTRL_TIMER1_CORE0_MASK (1 << 4)
#define RP23XX_ACCESSCTRL_TIMER1_SP_MASK (1 << 3)
#define RP23XX_ACCESSCTRL_TIMER1_SU_MASK (1 << 2)
#define RP23XX_ACCESSCTRL_TIMER1_NSP_MASK (1 << 1)
#define RP23XX_ACCESSCTRL_TIMER1_NSU_MASK (1 << 0)
#define RP23XX_ACCESSCTRL_UART0_MASK (0x000000ff)
#define RP23XX_ACCESSCTRL_UART0_DBG_MASK (1 << 7)
#define RP23XX_ACCESSCTRL_UART0_DMA_MASK (1 << 6)
#define RP23XX_ACCESSCTRL_UART0_CORE1_MASK (1 << 5)
#define RP23XX_ACCESSCTRL_UART0_CORE0_MASK (1 << 4)
#define RP23XX_ACCESSCTRL_UART0_SP_MASK (1 << 3)
#define RP23XX_ACCESSCTRL_UART0_SU_MASK (1 << 2)
#define RP23XX_ACCESSCTRL_UART0_NSP_MASK (1 << 1)
#define RP23XX_ACCESSCTRL_UART0_NSU_MASK (1 << 0)
#define RP23XX_ACCESSCTRL_UART1_MASK (0x000000ff)
#define RP23XX_ACCESSCTRL_UART1_DBG_MASK (1 << 7)
#define RP23XX_ACCESSCTRL_UART1_DMA_MASK (1 << 6)
#define RP23XX_ACCESSCTRL_UART1_CORE1_MASK (1 << 5)
#define RP23XX_ACCESSCTRL_UART1_CORE0_MASK (1 << 4)
#define RP23XX_ACCESSCTRL_UART1_SP_MASK (1 << 3)
#define RP23XX_ACCESSCTRL_UART1_SU_MASK (1 << 2)
#define RP23XX_ACCESSCTRL_UART1_NSP_MASK (1 << 1)
#define RP23XX_ACCESSCTRL_UART1_NSU_MASK (1 << 0)
#define RP23XX_ACCESSCTRL_OTP_MASK (0x000000ff)
#define RP23XX_ACCESSCTRL_OTP_DBG_MASK (1 << 7)
#define RP23XX_ACCESSCTRL_OTP_DMA_MASK (1 << 6)
#define RP23XX_ACCESSCTRL_OTP_CORE1_MASK (1 << 5)
#define RP23XX_ACCESSCTRL_OTP_CORE0_MASK (1 << 4)
#define RP23XX_ACCESSCTRL_OTP_SP_MASK (1 << 3)
#define RP23XX_ACCESSCTRL_OTP_SU_MASK (1 << 2)
#define RP23XX_ACCESSCTRL_OTP_NSP_MASK (1 << 1)
#define RP23XX_ACCESSCTRL_OTP_NSU_MASK (1 << 0)
#define RP23XX_ACCESSCTRL_TBMAN_MASK (0x000000ff)
#define RP23XX_ACCESSCTRL_TBMAN_DBG_MASK (1 << 7)
#define RP23XX_ACCESSCTRL_TBMAN_DMA_MASK (1 << 6)
#define RP23XX_ACCESSCTRL_TBMAN_CORE1_MASK (1 << 5)
#define RP23XX_ACCESSCTRL_TBMAN_CORE0_MASK (1 << 4)
#define RP23XX_ACCESSCTRL_TBMAN_SP_MASK (1 << 3)
#define RP23XX_ACCESSCTRL_TBMAN_SU_MASK (1 << 2)
#define RP23XX_ACCESSCTRL_TBMAN_NSP_MASK (1 << 1)
#define RP23XX_ACCESSCTRL_TBMAN_NSU_MASK (1 << 0)
#define RP23XX_ACCESSCTRL_POWMAN_MASK (0x000000ff)
#define RP23XX_ACCESSCTRL_POWMAN_DBG_MASK (1 << 7)
#define RP23XX_ACCESSCTRL_POWMAN_DMA_MASK (1 << 6)
#define RP23XX_ACCESSCTRL_POWMAN_CORE1_MASK (1 << 5)
#define RP23XX_ACCESSCTRL_POWMAN_CORE0_MASK (1 << 4)
#define RP23XX_ACCESSCTRL_POWMAN_SP_MASK (1 << 3)
#define RP23XX_ACCESSCTRL_POWMAN_SU_MASK (1 << 2)
#define RP23XX_ACCESSCTRL_POWMAN_NSP_MASK (1 << 1)
#define RP23XX_ACCESSCTRL_POWMAN_NSU_MASK (1 << 0)
#define RP23XX_ACCESSCTRL_TRNG_MASK (0x000000ff)
#define RP23XX_ACCESSCTRL_TRNG_DBG_MASK (1 << 7)
#define RP23XX_ACCESSCTRL_TRNG_DMA_MASK (1 << 6)
#define RP23XX_ACCESSCTRL_TRNG_CORE1_MASK (1 << 5)
#define RP23XX_ACCESSCTRL_TRNG_CORE0_MASK (1 << 4)
#define RP23XX_ACCESSCTRL_TRNG_SP_MASK (1 << 3)
#define RP23XX_ACCESSCTRL_TRNG_SU_MASK (1 << 2)
#define RP23XX_ACCESSCTRL_TRNG_NSP_MASK (1 << 1)
#define RP23XX_ACCESSCTRL_TRNG_NSU_MASK (1 << 0)
#define RP23XX_ACCESSCTRL_SHA256_MASK (0x000000ff)
#define RP23XX_ACCESSCTRL_SHA256_DBG_MASK (1 << 7)
#define RP23XX_ACCESSCTRL_SHA256_DMA_MASK (1 << 6)
#define RP23XX_ACCESSCTRL_SHA256_CORE1_MASK (1 << 5)
#define RP23XX_ACCESSCTRL_SHA256_CORE0_MASK (1 << 4)
#define RP23XX_ACCESSCTRL_SHA256_SP_MASK (1 << 3)
#define RP23XX_ACCESSCTRL_SHA256_SU_MASK (1 << 2)
#define RP23XX_ACCESSCTRL_SHA256_NSP_MASK (1 << 1)
#define RP23XX_ACCESSCTRL_SHA256_NSU_MASK (1 << 0)
#define RP23XX_ACCESSCTRL_SYSCFG_MASK (0x000000ff)
#define RP23XX_ACCESSCTRL_SYSCFG_DBG_MASK (1 << 7)
#define RP23XX_ACCESSCTRL_SYSCFG_DMA_MASK (1 << 6)
#define RP23XX_ACCESSCTRL_SYSCFG_CORE1_MASK (1 << 5)
#define RP23XX_ACCESSCTRL_SYSCFG_CORE0_MASK (1 << 4)
#define RP23XX_ACCESSCTRL_SYSCFG_SP_MASK (1 << 3)
#define RP23XX_ACCESSCTRL_SYSCFG_SU_MASK (1 << 2)
#define RP23XX_ACCESSCTRL_SYSCFG_NSP_MASK (1 << 1)
#define RP23XX_ACCESSCTRL_SYSCFG_NSU_MASK (1 << 0)
#define RP23XX_ACCESSCTRL_CLOCKS_MASK (0x000000ff)
#define RP23XX_ACCESSCTRL_CLOCKS_DBG_MASK (1 << 7)
#define RP23XX_ACCESSCTRL_CLOCKS_DMA_MASK (1 << 6)
#define RP23XX_ACCESSCTRL_CLOCKS_CORE1_MASK (1 << 5)
#define RP23XX_ACCESSCTRL_CLOCKS_CORE0_MASK (1 << 4)
#define RP23XX_ACCESSCTRL_CLOCKS_SP_MASK (1 << 3)
#define RP23XX_ACCESSCTRL_CLOCKS_SU_MASK (1 << 2)
#define RP23XX_ACCESSCTRL_CLOCKS_NSP_MASK (1 << 1)
#define RP23XX_ACCESSCTRL_CLOCKS_NSU_MASK (1 << 0)
#define RP23XX_ACCESSCTRL_XOSC_MASK (0x000000ff)
#define RP23XX_ACCESSCTRL_XOSC_DBG_MASK (1 << 7)
#define RP23XX_ACCESSCTRL_XOSC_DMA_MASK (1 << 6)
#define RP23XX_ACCESSCTRL_XOSC_CORE1_MASK (1 << 5)
#define RP23XX_ACCESSCTRL_XOSC_CORE0_MASK (1 << 4)
#define RP23XX_ACCESSCTRL_XOSC_SP_MASK (1 << 3)
#define RP23XX_ACCESSCTRL_XOSC_SU_MASK (1 << 2)
#define RP23XX_ACCESSCTRL_XOSC_NSP_MASK (1 << 1)
#define RP23XX_ACCESSCTRL_XOSC_NSU_MASK (1 << 0)
#define RP23XX_ACCESSCTRL_ROSC_MASK (0x000000ff)
#define RP23XX_ACCESSCTRL_ROSC_DBG_MASK (1 << 7)
#define RP23XX_ACCESSCTRL_ROSC_DMA_MASK (1 << 6)
#define RP23XX_ACCESSCTRL_ROSC_CORE1_MASK (1 << 5)
#define RP23XX_ACCESSCTRL_ROSC_CORE0_MASK (1 << 4)
#define RP23XX_ACCESSCTRL_ROSC_SP_MASK (1 << 3)
#define RP23XX_ACCESSCTRL_ROSC_SU_MASK (1 << 2)
#define RP23XX_ACCESSCTRL_ROSC_NSP_MASK (1 << 1)
#define RP23XX_ACCESSCTRL_ROSC_NSU_MASK (1 << 0)
#define RP23XX_ACCESSCTRL_PLL_SYS_MASK (0x000000ff)
#define RP23XX_ACCESSCTRL_PLL_SYS_DBG_MASK (1 << 7)
#define RP23XX_ACCESSCTRL_PLL_SYS_DMA_MASK (1 << 6)
#define RP23XX_ACCESSCTRL_PLL_SYS_CORE1_MASK (1 << 5)
#define RP23XX_ACCESSCTRL_PLL_SYS_CORE0_MASK (1 << 4)
#define RP23XX_ACCESSCTRL_PLL_SYS_SP_MASK (1 << 3)
#define RP23XX_ACCESSCTRL_PLL_SYS_SU_MASK (1 << 2)
#define RP23XX_ACCESSCTRL_PLL_SYS_NSP_MASK (1 << 1)
#define RP23XX_ACCESSCTRL_PLL_SYS_NSU_MASK (1 << 0)
#define RP23XX_ACCESSCTRL_PLL_USB_MASK (0x000000ff)
#define RP23XX_ACCESSCTRL_PLL_USB_DBG_MASK (1 << 7)
#define RP23XX_ACCESSCTRL_PLL_USB_DMA_MASK (1 << 6)
#define RP23XX_ACCESSCTRL_PLL_USB_CORE1_MASK (1 << 5)
#define RP23XX_ACCESSCTRL_PLL_USB_CORE0_MASK (1 << 4)
#define RP23XX_ACCESSCTRL_PLL_USB_SP_MASK (1 << 3)
#define RP23XX_ACCESSCTRL_PLL_USB_SU_MASK (1 << 2)
#define RP23XX_ACCESSCTRL_PLL_USB_NSP_MASK (1 << 1)
#define RP23XX_ACCESSCTRL_PLL_USB_NSU_MASK (1 << 0)
#define RP23XX_ACCESSCTRL_TICKS_MASK (0x000000ff)
#define RP23XX_ACCESSCTRL_TICKS_DBG_MASK (1 << 7)
#define RP23XX_ACCESSCTRL_TICKS_DMA_MASK (1 << 6)
#define RP23XX_ACCESSCTRL_TICKS_CORE1_MASK (1 << 5)
#define RP23XX_ACCESSCTRL_TICKS_CORE0_MASK (1 << 4)
#define RP23XX_ACCESSCTRL_TICKS_SP_MASK (1 << 3)
#define RP23XX_ACCESSCTRL_TICKS_SU_MASK (1 << 2)
#define RP23XX_ACCESSCTRL_TICKS_NSP_MASK (1 << 1)
#define RP23XX_ACCESSCTRL_TICKS_NSU_MASK (1 << 0)
#define RP23XX_ACCESSCTRL_WATCHDOG_MASK (0x000000ff)
#define RP23XX_ACCESSCTRL_WATCHDOG_DBG_MASK (1 << 7)
#define RP23XX_ACCESSCTRL_WATCHDOG_DMA_MASK (1 << 6)
#define RP23XX_ACCESSCTRL_WATCHDOG_CORE1_MASK (1 << 5)
#define RP23XX_ACCESSCTRL_WATCHDOG_CORE0_MASK (1 << 4)
#define RP23XX_ACCESSCTRL_WATCHDOG_SP_MASK (1 << 3)
#define RP23XX_ACCESSCTRL_WATCHDOG_SU_MASK (1 << 2)
#define RP23XX_ACCESSCTRL_WATCHDOG_NSP_MASK (1 << 1)
#define RP23XX_ACCESSCTRL_WATCHDOG_NSU_MASK (1 << 0)
#define RP23XX_ACCESSCTRL_RSM_MASK (0x000000ff)
#define RP23XX_ACCESSCTRL_RSM_DBG_MASK (1 << 7)
#define RP23XX_ACCESSCTRL_RSM_DMA_MASK (1 << 6)
#define RP23XX_ACCESSCTRL_RSM_CORE1_MASK (1 << 5)
#define RP23XX_ACCESSCTRL_RSM_CORE0_MASK (1 << 4)
#define RP23XX_ACCESSCTRL_RSM_SP_MASK (1 << 3)
#define RP23XX_ACCESSCTRL_RSM_SU_MASK (1 << 2)
#define RP23XX_ACCESSCTRL_RSM_NSP_MASK (1 << 1)
#define RP23XX_ACCESSCTRL_RSM_NSU_MASK (1 << 0)
#define RP23XX_ACCESSCTRL_XIP_CTRL_MASK (0x000000ff)
#define RP23XX_ACCESSCTRL_XIP_CTRL_DBG_MASK (1 << 7)
#define RP23XX_ACCESSCTRL_XIP_CTRL_DMA_MASK (1 << 6)
#define RP23XX_ACCESSCTRL_XIP_CTRL_CORE1_MASK (1 << 5)
#define RP23XX_ACCESSCTRL_XIP_CTRL_CORE0_MASK (1 << 4)
#define RP23XX_ACCESSCTRL_XIP_CTRL_SP_MASK (1 << 3)
#define RP23XX_ACCESSCTRL_XIP_CTRL_SU_MASK (1 << 2)
#define RP23XX_ACCESSCTRL_XIP_CTRL_NSP_MASK (1 << 1)
#define RP23XX_ACCESSCTRL_XIP_CTRL_NSU_MASK (1 << 0)
#define RP23XX_ACCESSCTRL_XIP_QMI_MASK (0x000000ff)
#define RP23XX_ACCESSCTRL_XIP_QMI_DBG_MASK (1 << 7)
#define RP23XX_ACCESSCTRL_XIP_QMI_DMA_MASK (1 << 6)
#define RP23XX_ACCESSCTRL_XIP_QMI_CORE1_MASK (1 << 5)
#define RP23XX_ACCESSCTRL_XIP_QMI_CORE0_MASK (1 << 4)
#define RP23XX_ACCESSCTRL_XIP_QMI_SP_MASK (1 << 3)
#define RP23XX_ACCESSCTRL_XIP_QMI_SU_MASK (1 << 2)
#define RP23XX_ACCESSCTRL_XIP_QMI_NSP_MASK (1 << 1)
#define RP23XX_ACCESSCTRL_XIP_QMI_NSU_MASK (1 << 0)
#define RP23XX_ACCESSCTRL_XIP_AUX_MASK (0x000000ff)
#define RP23XX_ACCESSCTRL_XIP_AUX_DBG_MASK (1 << 7)
#define RP23XX_ACCESSCTRL_XIP_AUX_DMA_MASK (1 << 6)
#define RP23XX_ACCESSCTRL_XIP_AUX_CORE1_MASK (1 << 5)
#define RP23XX_ACCESSCTRL_XIP_AUX_CORE0_MASK (1 << 4)
#define RP23XX_ACCESSCTRL_XIP_AUX_SP_MASK (1 << 3)
#define RP23XX_ACCESSCTRL_XIP_AUX_SU_MASK (1 << 2)
#define RP23XX_ACCESSCTRL_XIP_AUX_NSP_MASK (1 << 1)
#define RP23XX_ACCESSCTRL_XIP_AUX_NSU_MASK (1 << 0)
#endif /* __ARCH_ARM_SRC_RP23XX_HARDWARE_RP23XX_ACCESSCTRL_H */

98
arch/arm/src/rp23xx/hardware/rp23xx_adc.h Normal file
View file

@ -0,0 +1,98 @@
/****************************************************************************
* arch/arm/src/rp23xx/hardware/rp23xx_adc.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_RP23XX_HARDWARE_RP23XX_ADC_H
#define __ARCH_ARM_SRC_RP23XX_HARDWARE_RP23XX_ADC_H
/****************************************************************************
* Included Files
****************************************************************************/
#include "hardware/rp23xx_memorymap.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Register offsets *********************************************************/
#define RP23XX_ADC_CS_OFFSET 0x00000000
#define RP23XX_ADC_RESULT_OFFSET 0x00000004
#define RP23XX_ADC_FCS_OFFSET 0x00000008
#define RP23XX_ADC_FIFO_OFFSET 0x0000000c
#define RP23XX_ADC_DIV_OFFSET 0x00000010
#define RP23XX_ADC_INTR_OFFSET 0x00000014
#define RP23XX_ADC_INTE_OFFSET 0x00000018
#define RP23XX_ADC_INTF_OFFSET 0x0000001c
#define RP23XX_ADC_INTS_OFFSET 0x00000020
/* Register definitions *****************************************************/
#define RP23XX_ADC_CS (RP23XX_ADC_BASE + RP23XX_ADC_CS_OFFSET)
#define RP23XX_ADC_RESULT (RP23XX_ADC_BASE + RP23XX_ADC_RESULT_OFFSET)
#define RP23XX_ADC_FCS (RP23XX_ADC_BASE + RP23XX_ADC_FCS_OFFSET)
#define RP23XX_ADC_FIFO (RP23XX_ADC_BASE + RP23XX_ADC_FIFO_OFFSET)
#define RP23XX_ADC_DIV (RP23XX_ADC_BASE + RP23XX_ADC_DIV_OFFSET)
#define RP23XX_ADC_INTR (RP23XX_ADC_BASE + RP23XX_ADC_INTR_OFFSET)
#define RP23XX_ADC_INTE (RP23XX_ADC_BASE + RP23XX_ADC_INTE_OFFSET)
#define RP23XX_ADC_INTF (RP23XX_ADC_BASE + RP23XX_ADC_INTF_OFFSET)
#define RP23XX_ADC_INTS (RP23XX_ADC_BASE + RP23XX_ADC_INTS_OFFSET)
/* Register bit definitions *************************************************/
#define RP23XX_ADC_CS_MASK (0x01fff70f)
#define RP23XX_ADC_CS_RROBIN_SHIFT (16)
#define RP23XX_ADC_CS_RROBIN_MASK (0x01ff << RP23XX_ADC_CS_RROBIN_SHIFT)
#define RP23XX_ADC_CS_AINSEL_SHIFT (12)
#define RP23XX_ADC_CS_AINSEL_MASK (0x000fl << RP23XX_ADC_CS_AINSEL_SHIFT)
#define RP23XX_ADC_CS_ERR_STICKY (1 << 10)
#define RP23XX_ADC_CS_ERR (1 << 9)
#define RP23XX_ADC_CS_READY (1 << 8)
#define RP23XX_ADC_CS_START_MANY (1 << 3)
#define RP23XX_ADC_CS_START_ONCE (1 << 2)
#define RP23XX_ADC_CS_TS_EN (1 << 1)
#define RP23XX_ADC_CS_EN (1 << 0)
#define RP23XX_ADC_RESULT_MASK (0x00000fff)
#define RP23XX_ADC_FCS_MASK (0x0f0f0f0f)
#define RP23XX_ADC_FCS_THRESH_SHIFT (24)
#define RP23XX_ADC_FCS_THRESH_MASK (0x000fl << RP23XX_ADC_FCS_THRESH_SHIFT)
#define RP23XX_ADC_FCS_LEVEL_SHIFT (16)
#define RP23XX_ADC_FCS_LEVEL_MASK (0x000f << RP23XX_ADC_FCS_LEVEL_SHIFT)
#define RP23XX_ADC_FCS_OVER (1 << 11)
#define RP23XX_ADC_FCS_UNDER (1 << 10)
#define RP23XX_ADC_FCS_FULL (1 << 9)
#define RP23XX_ADC_FCS_EMPTY (1 << 8)
#define RP23XX_ADC_FCS_DREQ_EN (1 << 3)
#define RP23XX_ADC_FCS_ERR (1 << 2)
#define RP23XX_ADC_FCS_SHIFT (1 << 1)
#define RP23XX_ADC_FCS_EN (1 << 0)
#define RP23XX_ADC_FIFO_MASK (0x00008fff)
#define RP23XX_ADC_FIFO_ERR (1 << 15)
#define RP23XX_ADC_FIFO_VAL_MASK (0x00000fff)
#define RP23XX_ADC_DIV_MASK (0x00ffffff)
#define RP23XX_ADC_DIV_INT_MASK (0x00ffff00)
#define RP23XX_ADC_DIV_FRAC_MASK (0x000000ff)
#define RP23XX_ADC_INTR_FIFO (1 << 0)
#define RP23XX_ADC_INTE_FIFO (1 << 0)
#define RP23XX_ADC_INTF_FIFO (1 << 0)
#define RP23XX_ADC_INTS_FIFO (1 << 0)
#endif /* __ARCH_ARM_SRC_RP23XX_HARDWARE_RP23XX_ADC_H */

52
arch/arm/src/rp23xx/hardware/rp23xx_bootram.h Normal file
View file

@ -0,0 +1,52 @@
/****************************************************************************
* arch/arm/src/rp23xx/hardware/rp23xx_bootram.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_RP23XX_HARDWARE_RP23XX_BOOTRAM_H
#define __ARCH_ARM_SRC_RP23XX_HARDWARE_RP23XX_BOOTRAM_H
/****************************************************************************
* Included Files
****************************************************************************/
#include "hardware/rp23xx_memorymap.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Register offsets *********************************************************/
#define RP23XX_BOOTRAM_WRITE_ONCE_OFFSET(n) ((n) * 4 + 0x000800)
#define RP23XX_BOOTRAM_BOOTLOCK_STAT_OFFSET 0x00000808
#define RP23XX_BOOTRAM_BOOTLOCK_OFFSET(n) ((n) * 4 + 0x00080c)
/* Register definitions *****************************************************/
#define RP23XX_BOOTRAM_WRITE_ONCE(n) (RP23XX_BOOTRAM_BASE + RP23XX_BOOTRAM_WRITE_ONCE_OFFSET(n))
#define RP23XX_BOOTRAM_BOOTLOCK_STAT (RP23XX_BOOTRAM_BASE + RP23XX_BOOTRAM_BOOTLOCK_STAT_OFFSET)
#define RP23XX_BOOTRAM_BOOTLOCK(n) (RP23XX_BOOTRAM_BASE + RP23XX_BOOTRAM_BOOTLOCK_OFFSET(n))
/* Register bit definitions *************************************************/
#define RP23XX_BOOTRAM_WRITE_ONCE_MASK 0xffffffff
#define RP23XX_BOOTRAM_BOOTLOCK_STAT_MASK 0x000000ff
#define RP23XX_BOOTRAM_BOOTLOCK_MASK 0xffffffff
#endif /* __ARCH_ARM_SRC_RP23XX_HARDWARE_RP23XX_BOOTRAM_H */

62
arch/arm/src/rp23xx/hardware/rp23xx_busctrl.h Normal file
View file

@ -0,0 +1,62 @@
/****************************************************************************
* arch/arm/src/rp23xx/hardware/rp23xx_busctrl.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_RP23XX_HARDWARE_RP23XX_BUSCTRL_H
#define __ARCH_ARM_SRC_RP23XX_HARDWARE_RP23XX_BUSCTRL_H
/****************************************************************************
* Included Files
****************************************************************************/
#include "hardware/rp23xx_memorymap.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Register offsets *********************************************************/
#define RP23XX_BUSCTRL_BUS_PRIORITY_OFFSET 0x00000000
#define RP23XX_BUSCTRL_BUS_PRIORITY_ACK_OFFSET 0x00000004
#define RP23XX_BUSCTRL_PERFCTR_EN_OFFSET 0x00000008
#define RP23XX_BUSCTRL_PERFCTR_OFFSET(n) ((n) * 8 + 0x00000c)
#define RP23XX_BUSCTRL_PERFSEL_OFFSET(n) ((n) * 8 + 0x000010)
/* Register definitions *****************************************************/
#define RP23XX_BUSCTRL_BUS_PRIORITY (RP23XX_BUSCTRL_BASE + RP23XX_BUSCTRL_BUS_PRIORITY_OFFSET)
#define RP23XX_BUSCTRL_BUS_PRIORITY_ACK (RP23XX_BUSCTRL_BASE + RP23XX_BUSCTRL_BUS_PRIORITY_ACK_OFFSET)
#define RP23XX_BUSCTRL_PERFCTR_EN (RP23XX_BUSCTRL_BASE + RP23XX_BUSCTRL_PERFCTR_EN_OFFSET)
#define RP23XX_BUSCTRL_PERFCTR(n) (RP23XX_BUSCTRL_BASE + RP23XX_BUSCTRL_PERFCTR_OFFSET(n))
#define RP23XX_BUSCTRL_PERFSEL(n) (RP23XX_BUSCTRL_BASE + RP23XX_BUSCTRL_PERFSEL_OFFSET(n))
/* Register bit definitions *************************************************/
#define RP23XX_BUSCTRL_BUS_PRIORITY_MASK 0x00001111
#define RP23XX_BUSCTRL_BUS_PRIORITY_DMA_W (1 << 12)
#define RP23XX_BUSCTRL_BUS_PRIORITY_DMA_R (1 << 8)
#define RP23XX_BUSCTRL_BUS_PRIORITY_PROC1 (1 << 4)
#define RP23XX_BUSCTRL_BUS_PRIORITY_PROC0 (1 << 0)
#define RP23XX_BUSCTRL_BUS_PRIORITY_ACK (1 << 0)
#define RP23XX_BUSCTRL_PERFCTR_EN (1 << 0)
#define RP23XX_BUSCTRL_PERFCTR_MASK 0x00ffffff
#define RP23XX_BUSCTRL_PERFSEL_MASK 0x0000007f
#endif /* __ARCH_ARM_SRC_RP23XX_HARDWARE_RP23XX_BUSCTRL_H */

616
arch/arm/src/rp23xx/hardware/rp23xx_clocks.h Normal file
View file

@ -0,0 +1,616 @@
/****************************************************************************
* arch/arm/src/rp23xx/hardware/rp23xx_clocks.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_RP23XX_HARDWARE_RP23XX_CLOCKS_H
#define __ARCH_ARM_SRC_RP23XX_HARDWARE_RP23XX_CLOCKS_H
/****************************************************************************
* Included Files
****************************************************************************/
#include "hardware/rp23xx_memorymap.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Clock index **************************************************************/
#define RP23XX_CLOCKS_NDX_GPOUT0 0 /* Clock output to GPIO 21 */
#define RP23XX_CLOCKS_NDX_GPOUT1 1 /* Clock output to GPIO 23 */
#define RP23XX_CLOCKS_NDX_GPOUT2 2 /* Clock output to GPIO 24 */
#define RP23XX_CLOCKS_NDX_GPOUT3 3 /* Clock output to GPIO 25 */
#define RP23XX_CLOCKS_NDX_REF 4 /* Reference clock */
#define RP23XX_CLOCKS_NDX_SYS 5 /* System clock */
#define RP23XX_CLOCKS_NDX_PERI 6 /* Peripheral clock */
#define RP23XX_CLOCKS_NDX_HSTX 7 /* HSTX clock */
#define RP23XX_CLOCKS_NDX_USB 8 /* USB clock */
#define RP23XX_CLOCKS_NDX_ADC 9 /* ADC clock */
#define RP23XX_CLOCKS_NDX_MAX 10
/* Register offsets *********************************************************/
#define RP23XX_CLOCKS_CLK_CTRL_OFFSET 0x000000 /* Clock control */
#define RP23XX_CLOCKS_CLK_DIV_OFFSET 0x000004 /* Clock divisor */
#define RP23XX_CLOCKS_CLK_SELECTED_OFFSET 0x000008 /* Indicates which src is currently selected */
#define RP23XX_CLOCKS_CLK_NDX_CTRL_OFFSET(n) ((n) * 12 + RP23XX_CLOCKS_CLK_CTRL_OFFSET)
#define RP23XX_CLOCKS_CLK_NDX_DIV_OFFSET(n) ((n) * 12 + RP23XX_CLOCKS_CLK_DIV_OFFSET)
#define RP23XX_CLOCKS_CLK_NDX_SELECTED_OFFSET(n) ((n) * 12 + RP23XX_CLOCKS_CLK_SELECTED_OFFSET)
#define RP23XX_CLOCKS_DFTCLK_XOSC_CTRL_OFFSET 0x000078
#define RP23XX_CLOCKS_DFTCLK_ROSC_CTRL_OFFSET 0x00007c
#define RP23XX_CLOCKS_DFTCLK_LPOSC_CTRL_OFFSET 0x000080
#define RP23XX_CLOCKS_CLK_SYS_RESUS_CTRL_OFFSET 0x000084
#define RP23XX_CLOCKS_CLK_SYS_RESUS_STATUS_OFFSET 0x000088
#define RP23XX_CLOCKS_FC0_REF_KHZ_OFFSET 0x00008c /* Reference clock frequency in kHz */
#define RP23XX_CLOCKS_FC0_MIN_KHZ_OFFSET 0x000090 /* Minimum pass frequency in kHz. This is optional. Set to 0 if you are not using the pass/fail flags */
#define RP23XX_CLOCKS_FC0_MAX_KHZ_OFFSET 0x000094 /* Maximum pass frequency in kHz. This is optional. Set to 0x1ffffff if you are not using the pass/fail flags */
#define RP23XX_CLOCKS_FC0_DELAY_OFFSET 0x000098 /* Delays the start of frequency counting to allow the mux to settle Delay is measured in multiples of the reference clock period */
#define RP23XX_CLOCKS_FC0_INTERVAL_OFFSET 0x00009c /* The test interval is 0.98us * 2**interval, but let's call it 1us * 2**interval The default gives a test interval of 250us */
#define RP23XX_CLOCKS_FC0_SRC_OFFSET 0x0000a0 /* Clock sent to frequency counter, set to 0 when not required Writing to this register initiates the frequency count */
#define RP23XX_CLOCKS_FC0_STATUS_OFFSET 0x0000a4 /* Frequency counter status */
#define RP23XX_CLOCKS_FC0_RESULT_OFFSET 0x0000a8 /* Result of frequency measurement, only valid when status_done=1 */
#define RP23XX_CLOCKS_WAKE_EN0_OFFSET 0x0000ac /* enable clock in wake mode */
#define RP23XX_CLOCKS_WAKE_EN1_OFFSET 0x0000b0 /* enable clock in wake mode */
#define RP23XX_CLOCKS_SLEEP_EN0_OFFSET 0x0000b4 /* enable clock in sleep mode */
#define RP23XX_CLOCKS_SLEEP_EN1_OFFSET 0x0000b8 /* enable clock in sleep mode */
#define RP23XX_CLOCKS_ENABLED0_OFFSET 0x0000bc /* indicates the state of the clock enable */
#define RP23XX_CLOCKS_ENABLED1_OFFSET 0x0000c0 /* indicates the state of the clock enable */
#define RP23XX_CLOCKS_INTR_OFFSET 0x0000c4 /* Raw Interrupts */
#define RP23XX_CLOCKS_INTE_OFFSET 0x0000c8 /* Interrupt Enable */
#define RP23XX_CLOCKS_INTF_OFFSET 0x0000cc /* Interrupt Force */
#define RP23XX_CLOCKS_INTS_OFFSET 0x0000d0 /* Interrupt status after masking & forcing */
/* Register definitions *****************************************************/
#define RP23XX_CLOCKS_CLK_NDX_CTRL(n) (RP23XX_CLOCKS_BASE + RP23XX_CLOCKS_CLK_NDX_CTRL_OFFSET(n))
#define RP23XX_CLOCKS_CLK_NDX_DIV(n) (RP23XX_CLOCKS_BASE + RP23XX_CLOCKS_CLK_NDX_DIV_OFFSET(n))
#define RP23XX_CLOCKS_CLK_NDX_SELECTED(n) (RP23XX_CLOCKS_BASE + RP23XX_CLOCKS_CLK_NDX_SELECTED_OFFSET(n))
#define RP23XX_CLOCKS_CLK_GPOUT0_CTRL (RP23XX_CLOCKS_CLK_NDX_CTRL(RP23XX_CLOCKS_NDX_GPOUT0))
#define RP23XX_CLOCKS_CLK_GPOUT0_DIV (RP23XX_CLOCKS_CLK_NDX_DIV(RP23XX_CLOCKS_NDX_GPOUT0))
#define RP23XX_CLOCKS_CLK_GPOUT0_SELECTED (RP23XX_CLOCKS_CLK_NDX_SELECTED(RP23XX_CLOCKS_NDX_GPOUT0))
#define RP23XX_CLOCKS_CLK_GPOUT1_CTRL (RP23XX_CLOCKS_CLK_NDX_CTRL(RP23XX_CLOCKS_NDX_GPOUT1))
#define RP23XX_CLOCKS_CLK_GPOUT1_DIV (RP23XX_CLOCKS_CLK_NDX_DIV(RP23XX_CLOCKS_NDX_GPOUT1))
#define RP23XX_CLOCKS_CLK_GPOUT1_SELECTED (RP23XX_CLOCKS_CLK_NDX_SELECTED(RP23XX_CLOCKS_NDX_GPOUT1))
#define RP23XX_CLOCKS_CLK_GPOUT2_CTRL (RP23XX_CLOCKS_CLK_NDX_CTRL(RP23XX_CLOCKS_NDX_GPOUT2))
#define RP23XX_CLOCKS_CLK_GPOUT2_DIV (RP23XX_CLOCKS_CLK_NDX_DIV(RP23XX_CLOCKS_NDX_GPOUT2))
#define RP23XX_CLOCKS_CLK_GPOUT2_SELECTED (RP23XX_CLOCKS_CLK_NDX_SELECTED(RP23XX_CLOCKS_NDX_GPOUT2))
#define RP23XX_CLOCKS_CLK_GPOUT3_CTRL (RP23XX_CLOCKS_CLK_NDX_CTRL(RP23XX_CLOCKS_NDX_GPOUT3))
#define RP23XX_CLOCKS_CLK_GPOUT3_DIV (RP23XX_CLOCKS_CLK_NDX_DIV(RP23XX_CLOCKS_NDX_GPOUT3))
#define RP23XX_CLOCKS_CLK_GPOUT3_SELECTED (RP23XX_CLOCKS_CLK_NDX_SELECTED(RP23XX_CLOCKS_NDX_GPOUT3))
#define RP23XX_CLOCKS_CLK_REF_CTRL (RP23XX_CLOCKS_CLK_NDX_CTRL(RP23XX_CLOCKS_NDX_REF))
#define RP23XX_CLOCKS_CLK_REF_DIV (RP23XX_CLOCKS_CLK_NDX_DIV(RP23XX_CLOCKS_NDX_REF))
#define RP23XX_CLOCKS_CLK_REF_SELECTED (RP23XX_CLOCKS_CLK_NDX_SELECTED(RP23XX_CLOCKS_NDX_REF))
#define RP23XX_CLOCKS_CLK_SYS_CTRL (RP23XX_CLOCKS_CLK_NDX_CTRL(RP23XX_CLOCKS_NDX_SYS))
#define RP23XX_CLOCKS_CLK_SYS_DIV (RP23XX_CLOCKS_CLK_NDX_DIV(RP23XX_CLOCKS_NDX_SYS))
#define RP23XX_CLOCKS_CLK_SYS_SELECTED (RP23XX_CLOCKS_CLK_NDX_SELECTED(RP23XX_CLOCKS_NDX_SYS))
#define RP23XX_CLOCKS_CLK_PERI_CTRL (RP23XX_CLOCKS_CLK_NDX_CTRL(RP23XX_CLOCKS_NDX_PERI))
#define RP23XX_CLOCKS_CLK_PERI_SELECTED (RP23XX_CLOCKS_CLK_NDX_SELECTED(RP23XX_CLOCKS_NDX_PERI))
#define RP23XX_CLOCKS_CLK_HSTX_CTRL (RP23XX_CLOCKS_CLK_NDX_CTRL(RP23XX_CLOCKS_NDX_HSTX))
#define RP23XX_CLOCKS_CLK_HSTX_DIV (RP23XX_CLOCKS_CLK_NDX_DIV(RP23XX_CLOCKS_NDX_HSTX))
#define RP23XX_CLOCKS_CLK_HSTX_SELECTED (RP23XX_CLOCKS_CLK_NDX_SELECTED(RP23XX_CLOCKS_NDX_HSTX))
#define RP23XX_CLOCKS_CLK_USB_CTRL (RP23XX_CLOCKS_CLK_NDX_CTRL(RP23XX_CLOCKS_NDX_USB))
#define RP23XX_CLOCKS_CLK_USB_DIV (RP23XX_CLOCKS_CLK_NDX_DIV(RP23XX_CLOCKS_NDX_USB))
#define RP23XX_CLOCKS_CLK_USB_SELECTED (RP23XX_CLOCKS_CLK_NDX_SELECTED(RP23XX_CLOCKS_NDX_USB))
#define RP23XX_CLOCKS_CLK_ADC_CTRL (RP23XX_CLOCKS_CLK_NDX_CTRL(RP23XX_CLOCKS_NDX_ADC))
#define RP23XX_CLOCKS_CLK_ADC_DIV (RP23XX_CLOCKS_CLK_NDX_DIV(RP23XX_CLOCKS_NDX_ADC))
#define RP23XX_CLOCKS_CLK_ADC_SELECTED (RP23XX_CLOCKS_CLK_NDX_SELECTED(RP23XX_CLOCKS_NDX_ADC))
#define RP23XX_CLOCKS_DFTCLK_XOSC_CTRL (RP23XX_CLOCKS_BASE + RP23XX_CLOCKS_DFTCLK_XOSC_CTRL_OFFSET)
#define RP23XX_CLOCKS_DFTCLK_ROSC_CTRL (RP23XX_CLOCKS_BASE + RP23XX_CLOCKS_DFTCLK_ROSC_CTRL_OFFSET)
#define RP23XX_CLOCKS_DFTCLK_LPOSC_CTRL (RP23XX_CLOCKS_BASE + RP23XX_CLOCKS_DFTCLK_LPOSC_CTRL_OFFSET)
#define RP23XX_CLOCKS_CLK_SYS_RESUS_CTRL (RP23XX_CLOCKS_BASE + RP23XX_CLOCKS_CLK_SYS_RESUS_CTRL_OFFSET)
#define RP23XX_CLOCKS_CLK_SYS_RESUS_STATUS (RP23XX_CLOCKS_BASE + RP23XX_CLOCKS_CLK_SYS_RESUS_STATUS_OFFSET)
#define RP23XX_CLOCKS_FC0_REF_KHZ (RP23XX_CLOCKS_BASE + RP23XX_CLOCKS_FC0_REF_KHZ_OFFSET)
#define RP23XX_CLOCKS_FC0_MIN_KHZ (RP23XX_CLOCKS_BASE + RP23XX_CLOCKS_FC0_MIN_KHZ_OFFSET)
#define RP23XX_CLOCKS_FC0_MAX_KHZ (RP23XX_CLOCKS_BASE + RP23XX_CLOCKS_FC0_MAX_KHZ_OFFSET)
#define RP23XX_CLOCKS_FC0_DELAY (RP23XX_CLOCKS_BASE + RP23XX_CLOCKS_FC0_DELAY_OFFSET)
#define RP23XX_CLOCKS_FC0_INTERVAL (RP23XX_CLOCKS_BASE + RP23XX_CLOCKS_FC0_INTERVAL_OFFSET)
#define RP23XX_CLOCKS_FC0_SRC (RP23XX_CLOCKS_BASE + RP23XX_CLOCKS_FC0_SRC_OFFSET)
#define RP23XX_CLOCKS_FC0_STATUS (RP23XX_CLOCKS_BASE + RP23XX_CLOCKS_FC0_STATUS_OFFSET)
#define RP23XX_CLOCKS_FC0_RESULT (RP23XX_CLOCKS_BASE + RP23XX_CLOCKS_FC0_RESULT_OFFSET)
#define RP23XX_CLOCKS_WAKE_EN0 (RP23XX_CLOCKS_BASE + RP23XX_CLOCKS_WAKE_EN0_OFFSET)
#define RP23XX_CLOCKS_WAKE_EN1 (RP23XX_CLOCKS_BASE + RP23XX_CLOCKS_WAKE_EN1_OFFSET)
#define RP23XX_CLOCKS_SLEEP_EN0 (RP23XX_CLOCKS_BASE + RP23XX_CLOCKS_SLEEP_EN0_OFFSET)
#define RP23XX_CLOCKS_SLEEP_EN1 (RP23XX_CLOCKS_BASE + RP23XX_CLOCKS_SLEEP_EN1_OFFSET)
#define RP23XX_CLOCKS_ENABLED0 (RP23XX_CLOCKS_BASE + RP23XX_CLOCKS_ENABLED0_OFFSET)
#define RP23XX_CLOCKS_ENABLED1 (RP23XX_CLOCKS_BASE + RP23XX_CLOCKS_ENABLED1_OFFSET)
#define RP23XX_CLOCKS_INTR (RP23XX_CLOCKS_BASE + RP23XX_CLOCKS_INTR_OFFSET)
#define RP23XX_CLOCKS_INTE (RP23XX_CLOCKS_BASE + RP23XX_CLOCKS_INTE_OFFSET)
#define RP23XX_CLOCKS_INTF (RP23XX_CLOCKS_BASE + RP23XX_CLOCKS_INTF_OFFSET)
#define RP23XX_CLOCKS_INTS (RP23XX_CLOCKS_BASE + RP23XX_CLOCKS_INTS_OFFSET)
/* Register bit definitions *************************************************/
#define RP23XX_CLOCKS_CLK_GPOUT0_CTRL_NUDGE (1 << 20) /* An edge on this signal shifts the phase of the output by 1 cycle of the input clock This can be done at any time */
#define RP23XX_CLOCKS_CLK_GPOUT0_CTRL_PHASE_SHIFT (16) /* This delays the enable signal by up to 3 cycles of the input clock This must be set before the clock is enabled to have any effect */
#define RP23XX_CLOCKS_CLK_GPOUT0_CTRL_PHASE_MASK (0x03 << RP23XX_CLOCKS_CLK_GPOUT0_CTRL_PHASE_SHIFT)
#define RP23XX_CLOCKS_CLK_GPOUT0_CTRL_DC50 (1 << 12) /* Enables duty cycle correction for odd divisors */
#define RP23XX_CLOCKS_CLK_GPOUT0_CTRL_ENABLE (1 << 11) /* Starts and stops the clock generator cleanly */
#define RP23XX_CLOCKS_CLK_GPOUT0_CTRL_KILL (1 << 10) /* Asynchronously kills the clock generator */
#define RP23XX_CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_SHIFT (5) /* Selects the auxiliary clock source, will glitch when switching */
#define RP23XX_CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_MASK (0x0f << RP23XX_CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_CLKSRC_PLL_SYS (0x0 << RP23XX_CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_CLKSRC_GPIN0 (0x1 << RP23XX_CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_CLKSRC_GPIN1 (0x2 << RP23XX_CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_CLKSRC_PLL_USB (0x3 << RP23XX_CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_CLKSRC_PLL_USB_PRIMARY_REF_OPCG (0x4 << RP23XX_CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_ROSC_CLKSRC (0x5 << RP23XX_CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_XOSC_CLKSRC (0x6 << RP23XX_CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_LPOSC_CLKSRC (0x7 << RP23XX_CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_CLK_SYS (0x8 << RP23XX_CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_CLK_USB (0x9 << RP23XX_CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_CLK_ADC (0xa << RP23XX_CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_CLK_REF (0xb << RP23XX_CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_CLK_PERI (0xc << RP23XX_CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_CLK_HSTX (0xd << RP23XX_CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_CLK_CLK2FC (0xe << RP23XX_CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_GPOUT0_DIV_INT_SHIFT (16) /* Integer component of the divisor, 0 -> divide by 2^16 */
#define RP23XX_CLOCKS_CLK_GPOUT0_DIV_INT_MASK (0xffff << RP23XX_CLOCKS_CLK_GPOUT0_DIV_INT_SHIFT)
#define RP23XX_CLOCKS_CLK_GPOUT0_DIV_FRAC_MASK (0xffff) /* Fractional component of the divisor */
#define RP23XX_CLOCKS_CLK_GPOUT1_CTRL_NUDGE (1 << 20) /* An edge on this signal shifts the phase of the output by 1 cycle of the input clock This can be done at any time */
#define RP23XX_CLOCKS_CLK_GPOUT1_CTRL_PHASE_SHIFT (16) /* This delays the enable signal by up to 3 cycles of the input clock This must be set before the clock is enabled to have any effect */
#define RP23XX_CLOCKS_CLK_GPOUT1_CTRL_PHASE_MASK (0x03 << RP23XX_CLOCKS_CLK_GPOUT1_CTRL_PHASE_SHIFT)
#define RP23XX_CLOCKS_CLK_GPOUT1_CTRL_DC50 (1 << 12) /* Enables duty cycle correction for odd divisors */
#define RP23XX_CLOCKS_CLK_GPOUT1_CTRL_ENABLE (1 << 11) /* Starts and stops the clock generator cleanly */
#define RP23XX_CLOCKS_CLK_GPOUT1_CTRL_KILL (1 << 10) /* Asynchronously kills the clock generator */
#define RP23XX_CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_SHIFT (5) /* Selects the auxiliary clock source, will glitch when switching */
#define RP23XX_CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_MASK (0x0f << RP23XX_CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_CLKSRC_PLL_SYS (0x0 << RP23XX_CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_CLKSRC_GPIN0 (0x1 << RP23XX_CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_CLKSRC_GPIN1 (0x2 << RP23XX_CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_CLKSRC_PLL_USB (0x3 << RP23XX_CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_CLKSRC_PLL_USB_PRIMARY_REF_OPCG (0x4 << RP23XX_CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_ROSC_CLKSRC (0x5 << RP23XX_CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_XOSC_CLKSRC (0x6 << RP23XX_CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_LPOSC_CLKSRC (0x7 << RP23XX_CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_CLK_SYS (0x8 << RP23XX_CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_CLK_USB (0x9 << RP23XX_CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_CLK_ADC (0xa << RP23XX_CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_CLK_REF (0xb << RP23XX_CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_CLK_PERI (0xc << RP23XX_CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_CLK_HSTX (0xd << RP23XX_CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_CLK_CLK2FC (0xe << RP23XX_CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_GPOUT1_DIV_INT_SHIFT (16) /* Integer component of the divisor, 0 -> divide by 2^16 */
#define RP23XX_CLOCKS_CLK_GPOUT1_DIV_INT_MASK (0xffff << RP23XX_CLOCKS_CLK_GPOUT1_DIV_INT_SHIFT)
#define RP23XX_CLOCKS_CLK_GPOUT1_DIV_FRAC_MASK (0xffff) /* Fractional component of the divisor */
#define RP23XX_CLOCKS_CLK_GPOUT2_CTRL_NUDGE (1 << 20) /* An edge on this signal shifts the phase of the output by 1 cycle of the input clock This can be done at any time */
#define RP23XX_CLOCKS_CLK_GPOUT2_CTRL_PHASE_SHIFT (16) /* This delays the enable signal by up to 3 cycles of the input clock This must be set before the clock is enabled to have any effect */
#define RP23XX_CLOCKS_CLK_GPOUT2_CTRL_PHASE_MASK (0x03 << RP23XX_CLOCKS_CLK_GPOUT2_CTRL_PHASE_SHIFT)
#define RP23XX_CLOCKS_CLK_GPOUT2_CTRL_DC50 (1 << 12) /* Enables duty cycle correction for odd divisors */
#define RP23XX_CLOCKS_CLK_GPOUT2_CTRL_ENABLE (1 << 11) /* Starts and stops the clock generator cleanly */
#define RP23XX_CLOCKS_CLK_GPOUT2_CTRL_KILL (1 << 10) /* Asynchronously kills the clock generator */
#define RP23XX_CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_SHIFT (5) /* Selects the auxiliary clock source, will glitch when switching */
#define RP23XX_CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_MASK (0x0f << RP23XX_CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_CLKSRC_PLL_SYS (0x0 << RP23XX_CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_CLKSRC_GPIN0 (0x1 << RP23XX_CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_CLKSRC_GPIN1 (0x2 << RP23XX_CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_CLKSRC_PLL_USB (0x3 << RP23XX_CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_CLKSRC_PLL_USB_PRIMARY_REF_OPCG (0x4 << RP23XX_CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_ROSC_CLKSRC_PH (0x5 << RP23XX_CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_XOSC_CLKSRC (0x6 << RP23XX_CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_LPOSC_CLKSRC (0x7 << RP23XX_CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_CLK_SYS (0x8 << RP23XX_CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_CLK_USB (0x9 << RP23XX_CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_CLK_ADC (0xa << RP23XX_CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_CLK_REF (0xb << RP23XX_CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_CLK_PERI (0xc << RP23XX_CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_CLK_HSTX (0xd << RP23XX_CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_CLK_CLK2FC (0xe << RP23XX_CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_GPOUT2_DIV_INT_SHIFT (16) /* Integer component of the divisor, 0 -> divide by 2^16 */
#define RP23XX_CLOCKS_CLK_GPOUT2_DIV_INT_MASK (0xffff << RP23XX_CLOCKS_CLK_GPOUT2_DIV_INT_SHIFT)
#define RP23XX_CLOCKS_CLK_GPOUT2_DIV_FRAC_MASK (0xffff) /* Fractional component of the divisor */
#define RP23XX_CLOCKS_CLK_GPOUT3_CTRL_NUDGE (1 << 20) /* An edge on this signal shifts the phase of the output by 1 cycle of the input clock This can be done at any time */
#define RP23XX_CLOCKS_CLK_GPOUT3_CTRL_PHASE_SHIFT (16) /* This delays the enable signal by up to 3 cycles of the input clock This must be set before the clock is enabled to have any effect */
#define RP23XX_CLOCKS_CLK_GPOUT3_CTRL_PHASE_MASK (0x03 << RP23XX_CLOCKS_CLK_GPOUT3_CTRL_PHASE_SHIFT)
#define RP23XX_CLOCKS_CLK_GPOUT3_CTRL_DC50 (1 << 12) /* Enables duty cycle correction for odd divisors */
#define RP23XX_CLOCKS_CLK_GPOUT3_CTRL_ENABLE (1 << 11) /* Starts and stops the clock generator cleanly */
#define RP23XX_CLOCKS_CLK_GPOUT3_CTRL_KILL (1 << 10) /* Asynchronously kills the clock generator */
#define RP23XX_CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_SHIFT (5) /* Selects the auxiliary clock source, will glitch when switching */
#define RP23XX_CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_MASK (0x0f << RP23XX_CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_CLKSRC_PLL_SYS (0x0 << RP23XX_CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_CLKSRC_GPIN0 (0x1 << RP23XX_CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_CLKSRC_GPIN1 (0x2 << RP23XX_CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_CLKSRC_PLL_USB (0x3 << RP23XX_CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_CLKSRC_PLL_USB_PRIMARY_REF_OPCG (0x4 << RP23XX_CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_ROSC_CLKSRC_PH (0x5 << RP23XX_CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_XOSC_CLKSRC (0x6 << RP23XX_CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_LPOSC_CLKSRC (0x7 << RP23XX_CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_CLK_SYS (0x8 << RP23XX_CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_CLK_USB (0x9 << RP23XX_CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_CLK_ADC (0xa << RP23XX_CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_CLK_REF (0xb << RP23XX_CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_CLK_PERI (0xc << RP23XX_CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_CLK_HSTX (0xd << RP23XX_CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_CLK_CLK2FC (0xe << RP23XX_CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_GPOUT3_DIV_INT_SHIFT (16) /* Integer component of the divisor, 0 -> divide by 2^16 */
#define RP23XX_CLOCKS_CLK_GPOUT3_DIV_INT_MASK (0xffff << RP23XX_CLOCKS_CLK_GPOUT3_DIV_INT_SHIFT)
#define RP23XX_CLOCKS_CLK_GPOUT3_DIV_FRAC_MASK (0xffff) /* Fractional component of the divisor */
#define RP23XX_CLOCKS_CLK_REF_CTRL_AUXSRC_SHIFT (5) /* Selects the auxiliary clock source, will glitch when switching */
#define RP23XX_CLOCKS_CLK_REF_CTRL_AUXSRC_MASK (0x03 << RP23XX_CLOCKS_CLK_REF_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_REF_CTRL_AUXSRC_CLKSRC_PLL_USB (0x0 << RP23XX_CLOCKS_CLK_REF_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_REF_CTRL_AUXSRC_CLKSRC_GPIN0 (0x1 << RP23XX_CLOCKS_CLK_REF_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_REF_CTRL_AUXSRC_CLKSRC_GPIN1 (0x2 << RP23XX_CLOCKS_CLK_REF_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_REF_CTRL_AUXSRC_CLKSRC_PLL_USB_PRIMARY_REF_OPCG (0x3 << RP23XX_CLOCKS_CLK_REF_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_REF_CTRL_SRC_MASK (0x03)
#define RP23XX_CLOCKS_CLK_REF_CTRL_SRC_ROSC_CLKSRC_PH (0x0)
#define RP23XX_CLOCKS_CLK_REF_CTRL_SRC_CLKSRC_CLK_REF_AUX (0x1)
#define RP23XX_CLOCKS_CLK_REF_CTRL_SRC_XOSC_CLKSRC (0x2)
#define RP23XX_CLOCKS_CLK_REF_CTRL_SRC_LPOSC_CLKSRC (0x3)
#define RP23XX_CLOCKS_CLK_REF_DIV_INT_SHIFT (8) /* Integer component of the divisor, 0 -> divide by 2^2 */
#define RP23XX_CLOCKS_CLK_REF_DIV_INT_MASK (0x03 << RP23XX_CLOCKS_CLK_REF_DIV_INT_SHIFT)
#define RP23XX_CLOCKS_CLK_SYS_CTRL_AUXSRC_SHIFT (5) /* Selects the auxiliary clock source, will glitch when switching */
#define RP23XX_CLOCKS_CLK_SYS_CTRL_AUXSRC_MASK (0x07 << RP23XX_CLOCKS_CLK_SYS_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_SYS_CTRL_AUXSRC_CLKSRC_PLL_SYS (0x0 << RP23XX_CLOCKS_CLK_SYS_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_SYS_CTRL_AUXSRC_CLKSRC_PLL_USB (0x1 << RP23XX_CLOCKS_CLK_SYS_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_SYS_CTRL_AUXSRC_ROSC_CLKSRC (0x2 << RP23XX_CLOCKS_CLK_SYS_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_SYS_CTRL_AUXSRC_XOSC_CLKSRC (0x3 << RP23XX_CLOCKS_CLK_SYS_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_SYS_CTRL_AUXSRC_CLKSRC_GPIN0 (0x4 << RP23XX_CLOCKS_CLK_SYS_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_SYS_CTRL_AUXSRC_CLKSRC_GPIN1 (0x5 << RP23XX_CLOCKS_CLK_SYS_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_SYS_CTRL_SRC (1 << 0)
#define RP23XX_CLOCKS_CLK_SYS_CTRL_SRC_CLKSRC_CLK_SYS_AUX (0x1)
#define RP23XX_CLOCKS_CLK_SYS_DIV_INT_SHIFT (16) /* Integer component of the divisor, 0 -> divide by 2^16 */
#define RP23XX_CLOCKS_CLK_SYS_DIV_INT_MASK (0xffff << RP23XX_CLOCKS_CLK_SYS_DIV_INT_SHIFT)
#define RP23XX_CLOCKS_CLK_SYS_DIV_FRAC_MASK (0xffff) /* Fractional component of the divisor */
#define RP23XX_CLOCKS_CLK_PERI_CTRL_ENABLE (1 << 11) /* Starts and stops the clock generator cleanly */
#define RP23XX_CLOCKS_CLK_PERI_CTRL_KILL (1 << 10) /* Asynchronously kills the clock generator */
#define RP23XX_CLOCKS_CLK_PERI_CTRL_AUXSRC_SHIFT (5) /* Selects the auxiliary clock source, will glitch when switching */
#define RP23XX_CLOCKS_CLK_PERI_CTRL_AUXSRC_MASK (0x07 << RP23XX_CLOCKS_CLK_PERI_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_PERI_CTRL_AUXSRC_CLK_SYS (0x0 << RP23XX_CLOCKS_CLK_PERI_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_PERI_CTRL_AUXSRC_CLKSRC_PLL_SYS (0x1 << RP23XX_CLOCKS_CLK_PERI_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_PERI_CTRL_AUXSRC_CLKSRC_PLL_USB (0x2 << RP23XX_CLOCKS_CLK_PERI_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_PERI_CTRL_AUXSRC_ROSC_CLKSRC_PH (0x3 << RP23XX_CLOCKS_CLK_PERI_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_PERI_CTRL_AUXSRC_XOSC_CLKSRC (0x4 << RP23XX_CLOCKS_CLK_PERI_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_PERI_CTRL_AUXSRC_CLKSRC_GPIN0 (0x5 << RP23XX_CLOCKS_CLK_PERI_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_PERI_CTRL_AUXSRC_CLKSRC_GPIN1 (0x6 << RP23XX_CLOCKS_CLK_PERI_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_PERI_DIV_INT_SHIFT (16) /* Integer component of the divisor, 0 -> divide by 2^2 */
#define RP23XX_CLOCKS_CLK_PERI_DIV_INT_MASK (0x03 << RP23XX_CLOCKS_CLK_PERI_DIV_INT_SHIFT)
#define RP23XX_CLOCKS_CLK_HSTX_CTRL_NUDGE (1 << 20) /* An edge on this signal shifts the phase of the output by 1 cycle of the input clock This can be done at any time */
#define RP23XX_CLOCKS_CLK_HSTX_CTRL_PHASE_SHIFT (16) /* This delays the enable signal by up to 3 cycles of the input clock This must be set before the clock is enabled to have any effect */
#define RP23XX_CLOCKS_CLK_HSTX_CTRL_PHASE_MASK (0x03 << RP23XX_CLOCKS_CLK_HSTX_CTRL_PHASE_SHIFT)
#define RP23XX_CLOCKS_CLK_HSTX_CTRL_ENABLE (1 << 11) /* Starts and stops the clock generator cleanly */
#define RP23XX_CLOCKS_CLK_HSTX_CTRL_KILL (1 << 10) /* Asynchronously kills the clock generator */
#define RP23XX_CLOCKS_CLK_HSTX_CTRL_AUXSRC_SHIFT (5) /* Selects the auxiliary clock source, will glitch when switching */
#define RP23XX_CLOCKS_CLK_HSTX_CTRL_AUXSRC_MASK (0x07 << RP23XX_CLOCKS_CLK_HSTX_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_HSTX_CTRL_AUXSRC_CLK_SYS (0x0 << RP23XX_CLOCKS_CLK_HSTX_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_HSTX_CTRL_AUXSRC_CLKSRC_PLL_SYS (0x1 << RP23XX_CLOCKS_CLK_HSTX_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_HSTX_CTRL_AUXSRC_CLKSRC_PLL_USB (0x2 << RP23XX_CLOCKS_CLK_HSTX_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_HSTX_CTRL_AUXSRC_CLKSRC_GPIN0 (0x3 << RP23XX_CLOCKS_CLK_HSTX_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_HSTX_CTRL_AUXSRC_CLKSRC_GPIN1 (0x4 << RP23XX_CLOCKS_CLK_HSTX_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_HSTX_DIV_INT_SHIFT (16) /* Integer component of the divisor, 0 -> divide by 2^2 */
#define RP23XX_CLOCKS_CLK_HSTX_DIV_INT_MASK (0x03 << RP23XX_CLOCKS_CLK_HSTX_DIV_INT_SHIFT)
#define RP23XX_CLOCKS_CLK_USB_CTRL_NUDGE (1 << 20) /* An edge on this signal shifts the phase of the output by 1 cycle of the input clock This can be done at any time */
#define RP23XX_CLOCKS_CLK_USB_CTRL_PHASE_SHIFT (16) /* This delays the enable signal by up to 3 cycles of the input clock This must be set before the clock is enabled to have any effect */
#define RP23XX_CLOCKS_CLK_USB_CTRL_PHASE_MASK (0x03 << RP23XX_CLOCKS_CLK_USB_CTRL_PHASE_SHIFT)
#define RP23XX_CLOCKS_CLK_USB_CTRL_ENABLE (1 << 11) /* Starts and stops the clock generator cleanly */
#define RP23XX_CLOCKS_CLK_USB_CTRL_KILL (1 << 10) /* Asynchronously kills the clock generator */
#define RP23XX_CLOCKS_CLK_USB_CTRL_AUXSRC_SHIFT (5) /* Selects the auxiliary clock source, will glitch when switching */
#define RP23XX_CLOCKS_CLK_USB_CTRL_AUXSRC_MASK (0x07 << RP23XX_CLOCKS_CLK_USB_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_USB_CTRL_AUXSRC_CLKSRC_PLL_USB (0x0 << RP23XX_CLOCKS_CLK_USB_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_USB_CTRL_AUXSRC_CLKSRC_PLL_SYS (0x1 << RP23XX_CLOCKS_CLK_USB_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_USB_CTRL_AUXSRC_ROSC_CLKSRC_PH (0x2 << RP23XX_CLOCKS_CLK_USB_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_USB_CTRL_AUXSRC_XOSC_CLKSRC (0x3 << RP23XX_CLOCKS_CLK_USB_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_USB_CTRL_AUXSRC_CLKSRC_GPIN0 (0x4 << RP23XX_CLOCKS_CLK_USB_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_USB_CTRL_AUXSRC_CLKSRC_GPIN1 (0x5 << RP23XX_CLOCKS_CLK_USB_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_USB_DIV_INT_SHIFT (16) /* Integer component of the divisor, 0 -> divide by 2^4 */
#define RP23XX_CLOCKS_CLK_USB_DIV_INT_MASK (0x0f << RP23XX_CLOCKS_CLK_USB_DIV_INT_SHIFT)
#define RP23XX_CLOCKS_CLK_ADC_CTRL_NUDGE (1 << 20) /* An edge on this signal shifts the phase of the output by 1 cycle of the input clock This can be done at any time */
#define RP23XX_CLOCKS_CLK_ADC_CTRL_PHASE_SHIFT (16) /* This delays the enable signal by up to 3 cycles of the input clock This must be set before the clock is enabled to have any effect */
#define RP23XX_CLOCKS_CLK_ADC_CTRL_PHASE_MASK (0x03 << RP23XX_CLOCKS_CLK_ADC_CTRL_PHASE_SHIFT)
#define RP23XX_CLOCKS_CLK_ADC_CTRL_ENABLE (1 << 11) /* Starts and stops the clock generator cleanly */
#define RP23XX_CLOCKS_CLK_ADC_CTRL_KILL (1 << 10) /* Asynchronously kills the clock generator */
#define RP23XX_CLOCKS_CLK_ADC_CTRL_AUXSRC_SHIFT (5) /* Selects the auxiliary clock source, will glitch when switching */
#define RP23XX_CLOCKS_CLK_ADC_CTRL_AUXSRC_MASK (0x07 << RP23XX_CLOCKS_CLK_ADC_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_ADC_CTRL_AUXSRC_CLKSRC_PLL_USB (0x0 << RP23XX_CLOCKS_CLK_ADC_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_ADC_CTRL_AUXSRC_CLKSRC_PLL_SYS (0x1 << RP23XX_CLOCKS_CLK_ADC_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_ADC_CTRL_AUXSRC_ROSC_CLKSRC_PH (0x2 << RP23XX_CLOCKS_CLK_ADC_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_ADC_CTRL_AUXSRC_XOSC_CLKSRC (0x3 << RP23XX_CLOCKS_CLK_ADC_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_ADC_CTRL_AUXSRC_CLKSRC_GPIN0 (0x4 << RP23XX_CLOCKS_CLK_ADC_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_ADC_CTRL_AUXSRC_CLKSRC_GPIN1 (0x5 << RP23XX_CLOCKS_CLK_ADC_CTRL_AUXSRC_SHIFT)
#define RP23XX_CLOCKS_CLK_ADC_DIV_INT_SHIFT (16) /* Integer component of the divisor, 0 -> divide by 2^4 */
#define RP23XX_CLOCKS_CLK_ADC_DIV_INT_MASK (0x0f << RP23XX_CLOCKS_CLK_ADC_DIV_INT_SHIFT)
#define RP23XX_CLOCKS_DFTCLK_XOSC_CTRL_MASK (0x03)
#define RP23XX_CLOCKS_DFTCLK_XOSC_CTRL_SRC_NULL (0x0)
#define RP23XX_CLOCKS_DFTCLK_XOSC_CTRL_SRC_CLKSRC_PLL_USB_PRIMARY (0x1)
#define RP23XX_CLOCKS_DFTCLK_XOSC_CTRL_SRC_CLKSRC_GPIN0 (0x2)
#define RP23XX_CLOCKS_DFTCLK_ROSC_CTRL_MASK (0x03)
#define RP23XX_CLOCKS_DFTCLK_ROSC_CTRL_SRC_NULL (0x0)
#define RP23XX_CLOCKS_DFTCLK_ROSC_CTRL_SRC_CLKSRC_PLL_SYS_PRIMARY_ROSC (0x1)
#define RP23XX_CLOCKS_DFTCLK_ROSC_CTRL_SRC_CLKSRC_GPIN1 (0x2)
#define RP23XX_CLOCKS_DFTCLK_LPOSC_CTRL_MASK (0x03)
#define RP23XX_CLOCKS_DFTCLK_LPOSC_CTRL_SRC_NULL (0x0)
#define RP23XX_CLOCKS_DFTCLK_LPOSC_CTRL_SRC_CLKSRC_PLL_USB_PRIMARY_LPOSC (0x1)
#define RP23XX_CLOCKS_DFTCLK_LPOSC_CTRL_SRC_CLKSRC_GPIN1 (0x2)
#define RP23XX_CLOCKS_CLK_SYS_RESUS_CTRL_CLEAR (1 << 16) /* For clearing the resus after the fault that triggered it has been corrected */
#define RP23XX_CLOCKS_CLK_SYS_RESUS_CTRL_FRCE (1 << 12) /* Force a resus, for test purposes only */
#define RP23XX_CLOCKS_CLK_SYS_RESUS_CTRL_ENABLE (1 << 8) /* Enable resus */
#define RP23XX_CLOCKS_CLK_SYS_RESUS_CTRL_TIMEOUT_MASK (0xff) /* This is expressed as a number of clk_ref cycles and must be >= 2x /min_ */
#define RP23XX_CLOCKS_CLK_SYS_RESUS_STATUS_RESUSSED (1 << 0) /* Clock has been resuscitated, correct the error then send ctrl_clear=1 */
#define RP23XX_CLOCKS_FC0_REF_KHZ_MASK (0xfffff)
#define RP23XX_CLOCKS_FC0_MIN_KHZ_MASK (0x1ffffff)
#define RP23XX_CLOCKS_FC0_MAX_KHZ_MASK (0x1ffffff)
#define RP23XX_CLOCKS_FC0_DELAY_MASK (0x07)
#define RP23XX_CLOCKS_FC0_INTERVAL_MASK (0x0f)
#define RP23XX_CLOCKS_FC0_SRC_MASK (0xff)
#define RP23XX_CLOCKS_FC0_SRC_NULL (0x0)
#define RP23XX_CLOCKS_FC0_SRC_PLL_SYS_CLKSRC_PRIMARY (0x1)
#define RP23XX_CLOCKS_FC0_SRC_PLL_USB_CLKSRC_PRIMARY (0x2)
#define RP23XX_CLOCKS_FC0_SRC_ROSC_CLKSRC (0x3)
#define RP23XX_CLOCKS_FC0_SRC_ROSC_CLKSRC_PH (0x4)
#define RP23XX_CLOCKS_FC0_SRC_XOSC_CLKSRC (0x5)
#define RP23XX_CLOCKS_FC0_SRC_CLKSRC_GPIN0 (0x6)
#define RP23XX_CLOCKS_FC0_SRC_CLKSRC_GPIN1 (0x7)
#define RP23XX_CLOCKS_FC0_SRC_CLK_REF (0x8)
#define RP23XX_CLOCKS_FC0_SRC_CLK_SYS (0x9)
#define RP23XX_CLOCKS_FC0_SRC_CLK_PERI (0xa)
#define RP23XX_CLOCKS_FC0_SRC_CLK_USB (0xb)
#define RP23XX_CLOCKS_FC0_SRC_CLK_ADC (0xc)
#define RP23XX_CLOCKS_FC0_SRC_CLK_HSTX (0xd)
#define RP23XX_CLOCKS_FC0_SRC_CLK_LPOSC_CLKSRC (0xe)
#define RP23XX_CLOCKS_FC0_SRC_CLK_OTP_CLK2FC (0xf)
#define RP23XX_CLOCKS_FC0_SRC_CLK_PLL_USB_CLKSRC_PRIMARY_DFT (0x10)
#define RP23XX_CLOCKS_FC0_STATUS_DIED (1 << 28) /* Test clock stopped during test */
#define RP23XX_CLOCKS_FC0_STATUS_FAST (1 << 24) /* Test clock faster than expected, only valid when status_done=1 */
#define RP23XX_CLOCKS_FC0_STATUS_SLOW (1 << 20) /* Test clock slower than expected, only valid when status_done=1 */
#define RP23XX_CLOCKS_FC0_STATUS_FAIL (1 << 16) /* Test failed */
#define RP23XX_CLOCKS_FC0_STATUS_WAITING (1 << 12) /* Waiting for test clock to start */
#define RP23XX_CLOCKS_FC0_STATUS_RUNNING (1 << 8) /* Test running */
#define RP23XX_CLOCKS_FC0_STATUS_DONE (1 << 4) /* Test complete */
#define RP23XX_CLOCKS_FC0_STATUS_PASS (1 << 0) /* Test passed */
#define RP23XX_CLOCKS_FC0_RESULT_KHZ_SHIFT (5)
#define RP23XX_CLOCKS_FC0_RESULT_KHZ_MASK (0x1ffffff << RP23XX_CLOCKS_FC0_RESULT_KHZ_SHIFT)
#define RP23XX_CLOCKS_FC0_RESULT_FRAC_MASK (0x1f)
#define RP23XX_CLOCKS_WAKE_EN0_CLK_SYS_SIO (1 << 31)
#define RP23XX_CLOCKS_WAKE_EN0_CLK_SYS_SHA256 (1 << 30)
#define RP23XX_CLOCKS_WAKE_EN0_CLK_SYS_PSM (1 << 29)
#define RP23XX_CLOCKS_WAKE_EN0_CLK_SYS_ROSC (1 << 28)
#define RP23XX_CLOCKS_WAKE_EN0_CLK_SYS_ROM (1 << 27)
#define RP23XX_CLOCKS_WAKE_EN0_CLK_SYS_RESETS (1 << 26)
#define RP23XX_CLOCKS_WAKE_EN0_CLK_SYS_PWM (1 << 25)
#define RP23XX_CLOCKS_WAKE_EN0_CLK_SYS_POWMAN (1 << 24)
#define RP23XX_CLOCKS_WAKE_EN0_CLK_REF_POWMAN (1 << 23)
#define RP23XX_CLOCKS_WAKE_EN0_CLK_SYS_PLL_USB (1 << 22)
#define RP23XX_CLOCKS_WAKE_EN0_CLK_SYS_PLL_SYS (1 << 21)
#define RP23XX_CLOCKS_WAKE_EN0_CLK_SYS_PIO2 (1 << 20)
#define RP23XX_CLOCKS_WAKE_EN0_CLK_SYS_PIO1 (1 << 19)
#define RP23XX_CLOCKS_WAKE_EN0_CLK_SYS_PIO0 (1 << 18)
#define RP23XX_CLOCKS_WAKE_EN0_CLK_SYS_PADS (1 << 17)
#define RP23XX_CLOCKS_WAKE_EN0_CLK_SYS_OTP (1 << 16)
#define RP23XX_CLOCKS_WAKE_EN0_CLK_REF_OTP (1 << 15)
#define RP23XX_CLOCKS_WAKE_EN0_CLK_SYS_JTAG (1 << 14)
#define RP23XX_CLOCKS_WAKE_EN0_CLK_SYS_IO (1 << 13)
#define RP23XX_CLOCKS_WAKE_EN0_CLK_SYS_I2C1 (1 << 12)
#define RP23XX_CLOCKS_WAKE_EN0_CLK_SYS_I2C0 (1 << 11)
#define RP23XX_CLOCKS_WAKE_EN0_CLK_SYS_HSTX (1 << 10)
#define RP23XX_CLOCKS_WAKE_EN0_CLK_HSTX (1 << 9)
#define RP23XX_CLOCKS_WAKE_EN0_CLK_SYS_GLITCH_DETECTOR (1 << 8)
#define RP23XX_CLOCKS_WAKE_EN0_CLK_SYS_DMA (1 << 7)
#define RP23XX_CLOCKS_WAKE_EN0_CLK_SYS_BUSFABRIC (1 << 6)
#define RP23XX_CLOCKS_WAKE_EN0_CLK_SYS_BUSCTRL (1 << 5)
#define RP23XX_CLOCKS_WAKE_EN0_CLK_SYS_BOOTRAM (1 << 4)
#define RP23XX_CLOCKS_WAKE_EN0_CLK_SYS_ADC (1 << 3)
#define RP23XX_CLOCKS_WAKE_EN0_CLK_ADC_ADC (1 << 2)
#define RP23XX_CLOCKS_WAKE_EN0_CLK_SYS_ACCESSCTRL (1 << 1)
#define RP23XX_CLOCKS_WAKE_EN0_CLK_SYS_CLOCKS (1 << 0)
#define RP23XX_CLOCKS_WAKE_EN1_CLK_SYS_XOSC (1 << 30)
#define RP23XX_CLOCKS_WAKE_EN1_CLK_SYS_XIP (1 << 29)
#define RP23XX_CLOCKS_WAKE_EN1_CLK_SYS_WATCHDOG (1 << 28)
#define RP23XX_CLOCKS_WAKE_EN1_CLK_USB (1 << 27)
#define RP23XX_CLOCKS_WAKE_EN1_CLK_SYS_USBCTRL (1 << 26)
#define RP23XX_CLOCKS_WAKE_EN1_CLK_SYS_UART1 (1 << 25)
#define RP23XX_CLOCKS_WAKE_EN1_CLK_PERI_UART1 (1 << 24)
#define RP23XX_CLOCKS_WAKE_EN1_CLK_SYS_UART0 (1 << 23)
#define RP23XX_CLOCKS_WAKE_EN1_CLK_PERI_UART0 (1 << 22)
#define RP23XX_CLOCKS_WAKE_EN1_CLK_SYS_TRNG (1 << 21)
#define RP23XX_CLOCKS_WAKE_EN1_CLK_SYS_TIMER1 (1 << 20)
#define RP23XX_CLOCKS_WAKE_EN1_CLK_SYS_TIMER0 (1 << 19)
#define RP23XX_CLOCKS_WAKE_EN1_CLK_SYS_TICKS (1 << 18)
#define RP23XX_CLOCKS_WAKE_EN1_CLK_REF_TICKS (1 << 17)
#define RP23XX_CLOCKS_WAKE_EN1_CLK_SYS_TBMAN (1 << 16)
#define RP23XX_CLOCKS_WAKE_EN1_CLK_SYS_SYSINFO (1 << 15)
#define RP23XX_CLOCKS_WAKE_EN1_CLK_SYS_SYSCFG (1 << 14)
#define RP23XX_CLOCKS_WAKE_EN1_CLK_SYS_SRAM9 (1 << 13)
#define RP23XX_CLOCKS_WAKE_EN1_CLK_SYS_SRAM8 (1 << 12)
#define RP23XX_CLOCKS_WAKE_EN1_CLK_SYS_SRAM7 (1 << 11)
#define RP23XX_CLOCKS_WAKE_EN1_CLK_SYS_SRAM6 (1 << 10)
#define RP23XX_CLOCKS_WAKE_EN1_CLK_SYS_SRAM5 (1 << 9)
#define RP23XX_CLOCKS_WAKE_EN1_CLK_SYS_SRAM4 (1 << 8)
#define RP23XX_CLOCKS_WAKE_EN1_CLK_SYS_SRAM3 (1 << 7)
#define RP23XX_CLOCKS_WAKE_EN1_CLK_SYS_SRAM2 (1 << 6)
#define RP23XX_CLOCKS_WAKE_EN1_CLK_SYS_SRAM1 (1 << 5)
#define RP23XX_CLOCKS_WAKE_EN1_CLK_SYS_SRAM0 (1 << 4)
#define RP23XX_CLOCKS_WAKE_EN1_CLK_SYS_SPI1 (1 << 3)
#define RP23XX_CLOCKS_WAKE_EN1_CLK_PERI_SPI1 (1 << 2)
#define RP23XX_CLOCKS_WAKE_EN1_CLK_SYS_SPI0 (1 << 1)
#define RP23XX_CLOCKS_WAKE_EN1_CLK_PERI_SPI0 (1 << 0)
#define RP23XX_CLOCKS_SLEEP_EN0_CLK_SYS_SIO (1 << 31)
#define RP23XX_CLOCKS_SLEEP_EN0_CLK_SYS_SHA256 (1 << 30)
#define RP23XX_CLOCKS_SLEEP_EN0_CLK_SYS_PSM (1 << 29)
#define RP23XX_CLOCKS_SLEEP_EN0_CLK_SYS_ROSC (1 << 28)
#define RP23XX_CLOCKS_SLEEP_EN0_CLK_SYS_ROM (1 << 27)
#define RP23XX_CLOCKS_SLEEP_EN0_CLK_SYS_RESETS (1 << 26)
#define RP23XX_CLOCKS_SLEEP_EN0_CLK_SYS_PWM (1 << 25)
#define RP23XX_CLOCKS_SLEEP_EN0_CLK_SYS_POWMAN (1 << 24)
#define RP23XX_CLOCKS_SLEEP_EN0_CLK_REF_POWMAN (1 << 23)
#define RP23XX_CLOCKS_SLEEP_EN0_CLK_SYS_PLL_USB (1 << 22)
#define RP23XX_CLOCKS_SLEEP_EN0_CLK_SYS_PLL_SYS (1 << 21)
#define RP23XX_CLOCKS_SLEEP_EN0_CLK_SYS_PIO2 (1 << 20)
#define RP23XX_CLOCKS_SLEEP_EN0_CLK_SYS_PIO1 (1 << 19)
#define RP23XX_CLOCKS_SLEEP_EN0_CLK_SYS_PIO0 (1 << 18)
#define RP23XX_CLOCKS_SLEEP_EN0_CLK_SYS_PADS (1 << 17)
#define RP23XX_CLOCKS_SLEEP_EN0_CLK_SYS_OTP (1 << 16)
#define RP23XX_CLOCKS_SLEEP_EN0_CLK_REF_OTP (1 << 15)
#define RP23XX_CLOCKS_SLEEP_EN0_CLK_SYS_JTAG (1 << 14)
#define RP23XX_CLOCKS_SLEEP_EN0_CLK_SYS_IO (1 << 13)
#define RP23XX_CLOCKS_SLEEP_EN0_CLK_SYS_I2C1 (1 << 12)
#define RP23XX_CLOCKS_SLEEP_EN0_CLK_SYS_I2C0 (1 << 11)
#define RP23XX_CLOCKS_SLEEP_EN0_CLK_SYS_HSTX (1 << 10)
#define RP23XX_CLOCKS_SLEEP_EN0_CLK_HSTX (1 << 9)
#define RP23XX_CLOCKS_SLEEP_EN0_CLK_SYS_GLITCH_DETECTOR (1 << 8)
#define RP23XX_CLOCKS_SLEEP_EN0_CLK_SYS_DMA (1 << 7)
#define RP23XX_CLOCKS_SLEEP_EN0_CLK_SYS_BUSFABRIC (1 << 6)
#define RP23XX_CLOCKS_SLEEP_EN0_CLK_SYS_BUSCTRL (1 << 5)
#define RP23XX_CLOCKS_SLEEP_EN0_CLK_SYS_BOOTRAM (1 << 4)
#define RP23XX_CLOCKS_SLEEP_EN0_CLK_SYS_ADC (1 << 3)
#define RP23XX_CLOCKS_SLEEP_EN0_CLK_ADC_ADC (1 << 2)
#define RP23XX_CLOCKS_SLEEP_EN0_CLK_SYS_ACCESSCTRL (1 << 1)
#define RP23XX_CLOCKS_SLEEP_EN0_CLK_SYS_CLOCKS (1 << 0)
#define RP23XX_CLOCKS_SLEEP_EN1_CLK_SYS_XOSC (1 << 30)
#define RP23XX_CLOCKS_SLEEP_EN1_CLK_SYS_XIP (1 << 29)
#define RP23XX_CLOCKS_SLEEP_EN1_CLK_SYS_WATCHDOG (1 << 28)
#define RP23XX_CLOCKS_SLEEP_EN1_CLK_USB (1 << 27)
#define RP23XX_CLOCKS_SLEEP_EN1_CLK_SYS_USBCTRL (1 << 26)
#define RP23XX_CLOCKS_SLEEP_EN1_CLK_SYS_UART1 (1 << 25)
#define RP23XX_CLOCKS_SLEEP_EN1_CLK_PERI_UART1 (1 << 24)
#define RP23XX_CLOCKS_SLEEP_EN1_CLK_SYS_UART0 (1 << 23)
#define RP23XX_CLOCKS_SLEEP_EN1_CLK_PERI_UART0 (1 << 22)
#define RP23XX_CLOCKS_SLEEP_EN1_CLK_SYS_TRNG (1 << 21)
#define RP23XX_CLOCKS_SLEEP_EN1_CLK_SYS_TIMER1 (1 << 20)
#define RP23XX_CLOCKS_SLEEP_EN1_CLK_SYS_TIMER0 (1 << 19)
#define RP23XX_CLOCKS_SLEEP_EN1_CLK_SYS_TICKS (1 << 18)
#define RP23XX_CLOCKS_SLEEP_EN1_CLK_REF_TICKS (1 << 17)
#define RP23XX_CLOCKS_SLEEP_EN1_CLK_SYS_TBMAN (1 << 16)
#define RP23XX_CLOCKS_SLEEP_EN1_CLK_SYS_SYSINFO (1 << 15)
#define RP23XX_CLOCKS_SLEEP_EN1_CLK_SYS_SYSCFG (1 << 14)
#define RP23XX_CLOCKS_SLEEP_EN1_CLK_SYS_SRAM9 (1 << 13)
#define RP23XX_CLOCKS_SLEEP_EN1_CLK_SYS_SRAM8 (1 << 12)
#define RP23XX_CLOCKS_SLEEP_EN1_CLK_SYS_SRAM7 (1 << 11)
#define RP23XX_CLOCKS_SLEEP_EN1_CLK_SYS_SRAM6 (1 << 10)
#define RP23XX_CLOCKS_SLEEP_EN1_CLK_SYS_SRAM5 (1 << 9)
#define RP23XX_CLOCKS_SLEEP_EN1_CLK_SYS_SRAM4 (1 << 8)
#define RP23XX_CLOCKS_SLEEP_EN1_CLK_SYS_SRAM3 (1 << 7)
#define RP23XX_CLOCKS_SLEEP_EN1_CLK_SYS_SRAM2 (1 << 6)
#define RP23XX_CLOCKS_SLEEP_EN1_CLK_SYS_SRAM1 (1 << 5)
#define RP23XX_CLOCKS_SLEEP_EN1_CLK_SYS_SRAM0 (1 << 4)
#define RP23XX_CLOCKS_SLEEP_EN1_CLK_SYS_SPI1 (1 << 3)
#define RP23XX_CLOCKS_SLEEP_EN1_CLK_PERI_SPI1 (1 << 2)
#define RP23XX_CLOCKS_SLEEP_EN1_CLK_SYS_SPI0 (1 << 1)
#define RP23XX_CLOCKS_SLEEP_EN1_CLK_PERI_SPI0 (1 << 0)
#define RP23XX_CLOCKS_ENABLED0_CLK_SYS_SIO (1 << 31)
#define RP23XX_CLOCKS_ENABLED0_CLK_SYS_SHA256 (1 << 30)
#define RP23XX_CLOCKS_ENABLED0_CLK_SYS_PSM (1 << 29)
#define RP23XX_CLOCKS_ENABLED0_CLK_SYS_ROSC (1 << 28)
#define RP23XX_CLOCKS_ENABLED0_CLK_SYS_ROM (1 << 27)
#define RP23XX_CLOCKS_ENABLED0_CLK_SYS_RESETS (1 << 26)
#define RP23XX_CLOCKS_ENABLED0_CLK_SYS_PWM (1 << 25)
#define RP23XX_CLOCKS_ENABLED0_CLK_SYS_POWMAN (1 << 24)
#define RP23XX_CLOCKS_ENABLED0_CLK_REF_POWMAN (1 << 23)
#define RP23XX_CLOCKS_ENABLED0_CLK_SYS_PLL_USB (1 << 22)
#define RP23XX_CLOCKS_ENABLED0_CLK_SYS_PLL_SYS (1 << 21)
#define RP23XX_CLOCKS_ENABLED0_CLK_SYS_PIO2 (1 << 20)
#define RP23XX_CLOCKS_ENABLED0_CLK_SYS_PIO1 (1 << 19)
#define RP23XX_CLOCKS_ENABLED0_CLK_SYS_PIO0 (1 << 18)
#define RP23XX_CLOCKS_ENABLED0_CLK_SYS_PADS (1 << 17)
#define RP23XX_CLOCKS_ENABLED0_CLK_SYS_OTP (1 << 16)
#define RP23XX_CLOCKS_ENABLED0_CLK_REF_OTP (1 << 15)
#define RP23XX_CLOCKS_ENABLED0_CLK_SYS_JTAG (1 << 14)
#define RP23XX_CLOCKS_ENABLED0_CLK_SYS_IO (1 << 13)
#define RP23XX_CLOCKS_ENABLED0_CLK_SYS_I2C1 (1 << 12)
#define RP23XX_CLOCKS_ENABLED0_CLK_SYS_I2C0 (1 << 11)
#define RP23XX_CLOCKS_ENABLED0_CLK_SYS_HSTX (1 << 10)
#define RP23XX_CLOCKS_ENABLED0_CLK_HSTX (1 << 9)
#define RP23XX_CLOCKS_ENABLED0_CLK_SYS_GLITCH_DETECTOR (1 << 8)
#define RP23XX_CLOCKS_ENABLED0_CLK_SYS_DMA (1 << 7)
#define RP23XX_CLOCKS_ENABLED0_CLK_SYS_BUSFABRIC (1 << 6)
#define RP23XX_CLOCKS_ENABLED0_CLK_SYS_BUSCTRL (1 << 5)
#define RP23XX_CLOCKS_ENABLED0_CLK_SYS_BOOTRAM (1 << 4)
#define RP23XX_CLOCKS_ENABLED0_CLK_SYS_ADC (1 << 3)
#define RP23XX_CLOCKS_ENABLED0_CLK_ADC_ADC (1 << 2)
#define RP23XX_CLOCKS_ENABLED0_CLK_SYS_ACCESSCTRL (1 << 1)
#define RP23XX_CLOCKS_ENABLED0_CLK_SYS_CLOCKS (1 << 0)
#define RP23XX_CLOCKS_ENABLED1_CLK_SYS_XOSC (1 << 30)
#define RP23XX_CLOCKS_ENABLED1_CLK_SYS_XIP (1 << 29)
#define RP23XX_CLOCKS_ENABLED1_CLK_SYS_WATCHDOG (1 << 28)
#define RP23XX_CLOCKS_ENABLED1_CLK_USB (1 << 27)
#define RP23XX_CLOCKS_ENABLED1_CLK_SYS_USBCTRL (1 << 26)
#define RP23XX_CLOCKS_ENABLED1_CLK_SYS_UART1 (1 << 25)
#define RP23XX_CLOCKS_ENABLED1_CLK_PERI_UART1 (1 << 24)
#define RP23XX_CLOCKS_ENABLED1_CLK_SYS_UART0 (1 << 23)
#define RP23XX_CLOCKS_ENABLED1_CLK_PERI_UART0 (1 << 22)
#define RP23XX_CLOCKS_ENABLED1_CLK_SYS_TRNG (1 << 21)
#define RP23XX_CLOCKS_ENABLED1_CLK_SYS_TIMER1 (1 << 20)
#define RP23XX_CLOCKS_ENABLED1_CLK_SYS_TIMER0 (1 << 19)
#define RP23XX_CLOCKS_ENABLED1_CLK_SYS_TICKS (1 << 18)
#define RP23XX_CLOCKS_ENABLED1_CLK_REF_TICKS (1 << 17)
#define RP23XX_CLOCKS_ENABLED1_CLK_SYS_TBMAN (1 << 16)
#define RP23XX_CLOCKS_ENABLED1_CLK_SYS_SYSINFO (1 << 15)
#define RP23XX_CLOCKS_ENABLED1_CLK_SYS_SYSCFG (1 << 14)
#define RP23XX_CLOCKS_ENABLED1_CLK_SYS_SRAM9 (1 << 13)
#define RP23XX_CLOCKS_ENABLED1_CLK_SYS_SRAM8 (1 << 12)
#define RP23XX_CLOCKS_ENABLED1_CLK_SYS_SRAM7 (1 << 11)
#define RP23XX_CLOCKS_ENABLED1_CLK_SYS_SRAM6 (1 << 10)
#define RP23XX_CLOCKS_ENABLED1_CLK_SYS_SRAM5 (1 << 9)
#define RP23XX_CLOCKS_ENABLED1_CLK_SYS_SRAM4 (1 << 8)
#define RP23XX_CLOCKS_ENABLED1_CLK_SYS_SRAM3 (1 << 7)
#define RP23XX_CLOCKS_ENABLED1_CLK_SYS_SRAM2 (1 << 6)
#define RP23XX_CLOCKS_ENABLED1_CLK_SYS_SRAM1 (1 << 5)
#define RP23XX_CLOCKS_ENABLED1_CLK_SYS_SRAM0 (1 << 4)
#define RP23XX_CLOCKS_ENABLED1_CLK_SYS_SPI1 (1 << 3)
#define RP23XX_CLOCKS_ENABLED1_CLK_PERI_SPI1 (1 << 2)
#define RP23XX_CLOCKS_ENABLED1_CLK_SYS_SPI0 (1 << 1)
#define RP23XX_CLOCKS_ENABLED1_CLK_PERI_SPI0 (1 << 0)
#define RP23XX_CLOCKS_INTR_CLK_SYS_RESUS (1 << 0)
#define RP23XX_CLOCKS_INTE_CLK_SYS_RESUS (1 << 0)
#define RP23XX_CLOCKS_INTF_CLK_SYS_RESUS (1 << 0)
#define RP23XX_CLOCKS_INTS_CLK_SYS_RESUS (1 << 0)
#endif /* __ARCH_ARM_SRC_RP23XX_HARDWARE_RP23XX_CLOCKS_H */

52
arch/arm/src/rp23xx/hardware/rp23xx_coresight_trace.h Normal file
View file

@ -0,0 +1,52 @@
/****************************************************************************
* arch/arm/src/rp23xx/hardware/rp23xx_coresight_trace.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_RP23XX_HARDWARE_RP23XX_CORESIGHT_TRACE_H
#define __ARCH_ARM_SRC_RP23XX_HARDWARE_RP23XX_CORESIGHT_TRACE_H
/****************************************************************************
* Included Files
****************************************************************************/
#include "hardware/rp23xx_memorymap.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Register offsets *********************************************************/
#define RP23XX_CORESIGHT_TRACE_CTRL_STATUS_OFFSET 0x00000000
#define RP23XX_CORESIGHT_TRACE_TRACE_CAPTURE_FIFO_OFFSET 0x00000004
/* Register definitions *****************************************************/
#define RP23XX_CORESIGHT_TRACE_CTRL_STATUS (RP23XX_CORESIGHT_TRACE_BASE + RP23XX_CORESIGHT_TRACE_CTRL_STATUS_OFFSET)
#define RP23XX_CORESIGHT_TRACE_TRACE_CAPTURE_FIFO (RP23XX_CORESIGHT_TRACE_BASE + RP23XX_CORESIGHT_TRACE_TRACE_CAPTURE_FIFO_OFFSET)
/* Register bit definitions *************************************************/
#define RP23XX_CORESIGHT_TRACE_CTRL_STATUS_MASK (0x00000003)
#define RP23XX_CORESIGHT_TRACE_CTRL_STATUS_TRACE_CAPTURE_FIFO_OVERFLOW (1 << 1)
#define RP23XX_CORESIGHT_TRACE_CTRL_STATUS_TRACE_CAPTURE_FIFO_FLUSH (1 << 0)
#define RP23XX_CORESIGHT_TRACE_TRACE_CAPTURE_FIFO_MASK (0xffffffff)
#define RP23XX_CORESIGHT_TRACE_TRACE_CAPTURE_FIFO_RDATA_MASK (0xffffffff)
#endif /* __ARCH_ARM_SRC_RP23XX_HARDWARE_RP23XX_CORESIGHT_TRACE_H */

243
arch/arm/src/rp23xx/hardware/rp23xx_dma.h Normal file
View file

@ -0,0 +1,243 @@
/****************************************************************************
* arch/arm/src/rp23xx/hardware/rp23xx_dma.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_RP23XX_HARDWARE_RP23XX_DMA_H
#define __ARCH_ARM_SRC_RP23XX_HARDWARE_RP23XX_DMA_H
/****************************************************************************
* Included Files
****************************************************************************/
#include "hardware/rp23xx_memorymap.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Register offsets *********************************************************/
#define RP23XX_DMA_READ_ADDR_OFFSET 0x000000 /* DMA Read Address pointer */
#define RP23XX_DMA_WRITE_ADDR_OFFSET 0x000004 /* DMA Write Address pointer */
#define RP23XX_DMA_TRANS_COUNT_OFFSET 0x000008 /* DMA Transfer Count */
#define RP23XX_DMA_CTRL_TRIG_OFFSET 0x00000c /* DMA Control and Status */
#define RP23XX_DMA_AL1_CTRL_OFFSET 0x000010 /* Alias for CTRL register */
#define RP23XX_DMA_AL1_READ_ADDR_OFFSET 0x000014 /* Alias for READ_ADDR register */
#define RP23XX_DMA_AL1_WRITE_ADDR_OFFSET 0x000018 /* Alias for WRITE_ADDR register */
#define RP23XX_DMA_AL1_TRANS_COUNT_TRIG_OFFSET 0x00001c /* Alias for TRANS_COUNT register */
#define RP23XX_DMA_AL2_CTRL_OFFSET 0x000020 /* Alias for CTRL register */
#define RP23XX_DMA_AL2_TRANS_COUNT_OFFSET 0x000024 /* Alias for TRANS_COUNT register */
#define RP23XX_DMA_AL2_READ_ADDR_OFFSET 0x000028 /* Alias for READ_ADDR register */
#define RP23XX_DMA_AL2_WRITE_ADDR_TRIG_OFFSET 0x00002c /* Alias for WRITE_ADDR register */
#define RP23XX_DMA_AL3_CTRL_OFFSET 0x000030 /* Alias for CTRL register */
#define RP23XX_DMA_AL3_WRITE_ADDR_OFFSET 0x000034 /* Alias for WRITE_ADDR register */
#define RP23XX_DMA_AL3_TRANS_COUNT_OFFSET 0x000038 /* Alias for TRANS_COUNT register */
#define RP23XX_DMA_AL3_READ_ADDR_TRIG_OFFSET 0x00003c /* Alias for READ_ADDR register */
#define RP23XX_DMA_INTR_OFFSET 0x000400 /* Interrupt Status (raw) */
#define RP23XX_DMA_INTE0_OFFSET 0x000404 /* Interrupt Enables for IRQ 0 */
#define RP23XX_DMA_INTF0_OFFSET 0x000408 /* Force Interrupts */
#define RP23XX_DMA_INTS0_OFFSET 0x00040c /* Interrupt Status for IRQ 0 */
#define RP23XX_DMA_INTE1_OFFSET 0x000414 /* Interrupt Enables for IRQ 1 */
#define RP23XX_DMA_INTF1_OFFSET 0x000418 /* Force Interrupts for IRQ 1 */
#define RP23XX_DMA_INTS1_OFFSET 0x00041c /* Interrupt Status (masked) for IRQ 1 */
#define RP23XX_DMA_INTE2_OFFSET 0x000424 /* Interrupt Enables for IRQ 1 */
#define RP23XX_DMA_INTF2_OFFSET 0x000428 /* Force Interrupts for IRQ 1 */
#define RP23XX_DMA_INTS2_OFFSET 0x00042c /* Interrupt Status (masked) for IRQ 1 */
#define RP23XX_DMA_INTE3_OFFSET 0x000434 /* Interrupt Enables for IRQ 1 */
#define RP23XX_DMA_INTF3_OFFSET 0x000438 /* Force Interrupts for IRQ 1 */
#define RP23XX_DMA_INTS3_OFFSET 0x00043c /* Interrupt Status (masked) for IRQ 1 */
#define RP23XX_DMA_TIMER0_OFFSET 0x000440 /* Pacing (X/Y) Fractional Timer The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less. */
#define RP23XX_DMA_TIMER1_OFFSET 0x000444 /* Pacing (X/Y) Fractional Timer The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less. */
#define RP23XX_DMA_TIMER2_OFFSET 0x000448 /* Pacing (X/Y) Fractional Timer The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less. */
#define RP23XX_DMA_TIMER3_OFFSET 0x00044c /* Pacing (X/Y) Fractional Timer The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less. */
#define RP23XX_DMA_MULTI_CHAN_TRIGGER_OFFSET 0x000450 /* Trigger one or more channels simultaneously */
#define RP23XX_DMA_SNIFF_CTRL_OFFSET 0x000454 /* Sniffer Control */
#define RP23XX_DMA_SNIFF_DATA_OFFSET 0x000458 /* Data accumulator for sniff hardware Write an initial seed value here before starting a DMA transfer on the channel indicated by SNIFF_CTRL_DMACH. The hardware will update this register each time it observes a read from the indicated channel. Once the channel completes, the final result can be read from this register. */
#define RP23XX_DMA_FIFO_LEVELS_OFFSET 0x000460 /* Debug RAF, WAF, TDF levels */
#define RP23XX_DMA_CHAN_ABORT_OFFSET 0x000464 /* Abort an in-progress transfer sequence on one or more channels */
#define RP23XX_DMA_N_CHANNELS_OFFSET 0x000468 /* The number of channels this DMA instance is equipped with. This DMA supports up to 16 hardware channels, but can be configured with as few as one, to minimise silicon area. */
#define RP23XX_DMA_SECCFG_OFFSET(n) (0x000480 + (n) * 0x0004)
#define RP23XX_DMA_DBG_SECCFG_IRQ_OFFSET(n) (0x0004c4 + (n) * 0x0004)
#define RP23XX_DMA_SECCFG_MISC_OFFSET 0x0004d0
#define RP23XX_DMA_DBG_CTDREQ_OFFSET(n) (0x000800 + (n) * 0x0040)
#define RP23XX_DMA_DBG_TCR_OFFSET(n) (0x000804 + (n) * 0x0040)
#define RP23XX_DMA_MPU_CTRL_OFFSET 0x000500
#define RP23XX_DMA_MPU_BAR_OFFSET(n) (0x000504 + (n) * 0x0008)
#define RP23XX_DMA_MPU_LAR_OFFSET(n) (0x000508 + (n) * 0x0008)
/* Register definitions *****************************************************/
#define RP23XX_DMA_CH(n) (RP23XX_DMA_BASE + (0x0040 * (n)))
#define RP23XX_DMA_READ_ADDR(n) (RP23XX_DMA_CH(n) + RP23XX_DMA_READ_ADDR_OFFSET)
#define RP23XX_DMA_WRITE_ADDR(n) (RP23XX_DMA_CH(n) + RP23XX_DMA_WRITE_ADDR_OFFSET)
#define RP23XX_DMA_TRANS_COUNT(n) (RP23XX_DMA_CH(n) + RP23XX_DMA_TRANS_COUNT_OFFSET)
#define RP23XX_DMA_CTRL_TRIG(n) (RP23XX_DMA_CH(n) + RP23XX_DMA_CTRL_TRIG_OFFSET)
#define RP23XX_DMA_AL1_CTRL(n) (RP23XX_DMA_CH(n) + RP23XX_DMA_AL1_CTRL_OFFSET)
#define RP23XX_DMA_AL1_READ_ADDR(n) (RP23XX_DMA_CH(n) + RP23XX_DMA_AL1_READ_ADDR_OFFSET)
#define RP23XX_DMA_AL1_WRITE_ADDR(n) (RP23XX_DMA_CH(n) + RP23XX_DMA_AL1_WRITE_ADDR_OFFSET)
#define RP23XX_DMA_AL1_TRANS_COUNT_TRIG(n) (RP23XX_DMA_CH(n) + RP23XX_DMA_AL1_TRANS_COUNT_TRIG_OFFSET)
#define RP23XX_DMA_AL2_CTRL(n) (RP23XX_DMA_CH(n) + RP23XX_DMA_AL2_CTRL_OFFSET)
#define RP23XX_DMA_AL2_TRANS_COUNT(n) (RP23XX_DMA_CH(n) + RP23XX_DMA_AL2_TRANS_COUNT_OFFSET)
#define RP23XX_DMA_AL2_READ_ADDR(n) (RP23XX_DMA_CH(n) + RP23XX_DMA_AL2_READ_ADDR_OFFSET)
#define RP23XX_DMA_AL2_WRITE_ADDR_TRIG(n) (RP23XX_DMA_CH(n) + RP23XX_DMA_AL2_WRITE_ADDR_TRIG_OFFSET)
#define RP23XX_DMA_AL3_CTRL(n) (RP23XX_DMA_CH(n) + RP23XX_DMA_AL3_CTRL_OFFSET)
#define RP23XX_DMA_AL3_WRITE_ADDR(n) (RP23XX_DMA_CH(n) + RP23XX_DMA_AL3_WRITE_ADDR_OFFSET)
#define RP23XX_DMA_AL3_TRANS_COUNT(n) (RP23XX_DMA_CH(n) + RP23XX_DMA_AL3_TRANS_COUNT_OFFSET)
#define RP23XX_DMA_AL3_READ_ADDR_TRIG(n) (RP23XX_DMA_CH(n) + RP23XX_DMA_AL3_READ_ADDR_TRIG_OFFSET)
#define RP23XX_DMA_INTR (RP23XX_DMA_BASE + RP23XX_DMA_INTR_OFFSET)
#define RP23XX_DMA_INTE0 (RP23XX_DMA_BASE + RP23XX_DMA_INTE0_OFFSET)
#define RP23XX_DMA_INTF0 (RP23XX_DMA_BASE + RP23XX_DMA_INTF0_OFFSET)
#define RP23XX_DMA_INTS0 (RP23XX_DMA_BASE + RP23XX_DMA_INTS0_OFFSET)
#define RP23XX_DMA_INTE1 (RP23XX_DMA_BASE + RP23XX_DMA_INTE1_OFFSET)
#define RP23XX_DMA_INTF1 (RP23XX_DMA_BASE + RP23XX_DMA_INTF1_OFFSET)
#define RP23XX_DMA_INTS1 (RP23XX_DMA_BASE + RP23XX_DMA_INTS1_OFFSET)
#define RP23XX_DMA_INTE2 (RP23XX_DMA_BASE + RP23XX_DMA_INTE2_OFFSET)
#define RP23XX_DMA_INTF2 (RP23XX_DMA_BASE + RP23XX_DMA_INTF2_OFFSET)
#define RP23XX_DMA_INTS2 (RP23XX_DMA_BASE + RP23XX_DMA_INTS2_OFFSET)
#define RP23XX_DMA_INTE3 (RP23XX_DMA_BASE + RP23XX_DMA_INTE3_OFFSET)
#define RP23XX_DMA_INTF3 (RP23XX_DMA_BASE + RP23XX_DMA_INTF3_OFFSET)
#define RP23XX_DMA_INTS3 (RP23XX_DMA_BASE + RP23XX_DMA_INTS3_OFFSET)
#define RP23XX_DMA_TIMER0 (RP23XX_DMA_BASE + RP23XX_DMA_TIMER0_OFFSET)
#define RP23XX_DMA_TIMER1 (RP23XX_DMA_BASE + RP23XX_DMA_TIMER1_OFFSET)
#define RP23XX_DMA_TIMER2 (RP23XX_DMA_BASE + RP23XX_DMA_TIMER2_OFFSET)
#define RP23XX_DMA_TIMER3 (RP23XX_DMA_BASE + RP23XX_DMA_TIMER3_OFFSET)
#define RP23XX_DMA_MULTI_CHAN_TRIGGER (RP23XX_DMA_BASE + RP23XX_DMA_MULTI_CHAN_TRIGGER_OFFSET)
#define RP23XX_DMA_SNIFF_CTRL (RP23XX_DMA_BASE + RP23XX_DMA_SNIFF_CTRL_OFFSET)
#define RP23XX_DMA_SNIFF_DATA (RP23XX_DMA_BASE + RP23XX_DMA_SNIFF_DATA_OFFSET)
#define RP23XX_DMA_FIFO_LEVELS (RP23XX_DMA_BASE + RP23XX_DMA_FIFO_LEVELS_OFFSET)
#define RP23XX_DMA_CHAN_ABORT (RP23XX_DMA_BASE + RP23XX_DMA_CHAN_ABORT_OFFSET)
#define RP23XX_DMA_N_CHANNELS (RP23XX_DMA_BASE + RP23XX_DMA_N_CHANNELS_OFFSET)
#define RP23XX_DMA_SECCFG(n) (RP23XX_DMA_BASE + RP23XX_DMA_SECCFG_OFFSET(n))
#define RP23XX_DMA_SECCFG_IRQ(n) (RP23XX_DMA_BASE + RP23XX_DMA_SECCFG_IRQ_OFFSET(n))
#define RP23XX_DMA_SECCFG_MISC (RP23XX_DMA_BASE + RP23XX_DMA_SECCFG_MISC_OFFSET)
#define RP23XX_DMA_DBG_CTDREQ(n) (RP23XX_DMA_BASE + RP23XX_DMA_DBG_CTDREQ_OFFSET(n))
#define RP23XX_DMA_DBG_TCR(n) (RP23XX_DMA_BASE + RP23XX_DMA_DBG_TCR_OFFSET(n))
#define RP23XX_DMA_MPU_CTRL (RP23XX_DMA_BASE + RP23XX_DMA_MPU_CTRL_OFFSET)
#define RP23XX_DMA_MPU_BAR(n) (RP23XX_DMA_BASE + RP23XX_DMA_MPU_BAR_OFFSET(n))
#define RP23XX_DMA_MPU_LAR(n) (RP23XX_DMA_BASE + RP23XX_DMA_MPU_LAR_OFFSET(n))
/* Register bit definitions *************************************************/
#define RP23XX_DMA_CTRL_TRIG_AHB_ERROR (1 << 31) /* Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. */
#define RP23XX_DMA_CTRL_TRIG_READ_ERROR (1 << 30) /* If 1, the channel received a read bus error. Write one to clear. READ_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 3 transfers later) */
#define RP23XX_DMA_CTRL_TRIG_WRITE_ERROR (1 << 29) /* If 1, the channel received a write bus error. Write one to clear. WRITE_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 5 transfers later) */
#define RP23XX_DMA_CTRL_TRIG_BUSY (1 << 26) /* This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused. To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. */
#define RP23XX_DMA_CTRL_TRIG_SNIFF_EN (1 << 25) /* If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. This allows checksum to be enabled or disabled on a per-control- block basis. */
#define RP23XX_DMA_CTRL_TRIG_BSWAP (1 << 24) /* Apply byte-swap transformation to DMA data. For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order. */
#define RP23XX_DMA_CTRL_TRIG_IRQ_QUIET (1 << 23) /* In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks. */
#define RP23XX_DMA_CTRL_TRIG_TREQ_SEL_SHIFT (17) /* Select a Transfer Request signal. The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). 0x0 to 0x3a -> select DREQ n as TREQ */
#define RP23XX_DMA_CTRL_TRIG_TREQ_SEL_MASK (0x3f << RP23XX_DMA_CTRL_TRIG_TREQ_SEL_SHIFT)
#define RP23XX_DMA_CTRL_TRIG_TREQ_SEL_TIMER0 (0x3b << RP23XX_DMA_CTRL_TRIG_TREQ_SEL_SHIFT) /* Select Timer 0 as TREQ */
#define RP23XX_DMA_CTRL_TRIG_TREQ_SEL_TIMER1 (0x3c << RP23XX_DMA_CTRL_TRIG_TREQ_SEL_SHIFT) /* Select Timer 1 as TREQ */
#define RP23XX_DMA_CTRL_TRIG_TREQ_SEL_TIMER2 (0x3d << RP23XX_DMA_CTRL_TRIG_TREQ_SEL_SHIFT) /* Select Timer 2 as TREQ (Optional) */
#define RP23XX_DMA_CTRL_TRIG_TREQ_SEL_TIMER3 (0x3e << RP23XX_DMA_CTRL_TRIG_TREQ_SEL_SHIFT) /* Select Timer 3 as TREQ (Optional) */
#define RP23XX_DMA_CTRL_TRIG_TREQ_SEL_PERMANENT (0x3f << RP23XX_DMA_CTRL_TRIG_TREQ_SEL_SHIFT) /* Permanent request, for unpaced transfers. */
#define RP23XX_DMA_CTRL_TRIG_CHAIN_TO_SHIFT (13) /* When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. Reset value is equal to channel number (0). */
#define RP23XX_DMA_CTRL_TRIG_CHAIN_TO_MASK (0x0f << RP23XX_DMA_CTRL_TRIG_CHAIN_TO_SHIFT)
#define RP23XX_DMA_CTRL_TRIG_RING_SEL (1 << 12) /* Select whether RING_SIZE applies to read or write addresses. If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped. */
#define RP23XX_DMA_CTRL_TRIG_RING_SIZE_SHIFT (8) /* Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. */
#define RP23XX_DMA_CTRL_TRIG_RING_SIZE_MASK (0x0f << RP23XX_DMA_CTRL_TRIG_RING_SIZE_SHIFT)
#define RP23XX_DMA_CTRL_TRIG_RING_SIZE_RING_NONE (0x0 << RP23XX_DMA_CTRL_TRIG_RING_SIZE_SHIFT)
#define RP23XX_DMA_CTRL_TRIG_INCR_WRITE_REV (1 << 7) /* If 1, and INCR_WRITE is 1, the write address is decremented rather than incremented with each transfer. If 1, and INCR_WRITE is 0, this otherwise-unused combination causes the write address to be incremented by twice the transfer size, i.e. skipping over alternate addresses.*/
#define RP23XX_DMA_CTRL_TRIG_INCR_WRITE (1 << 6) /* If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. Generally this should be disabled for memory-to-peripheral transfers. */
#define RP23XX_DMA_CTRL_TRIG_INCR_READ_REV (1 << 5) /* If 1, and INCR_READ is 1, the read address is decremented rather than incremented with each transfer. If 1, and INCR_READ is 0, this otherwise-unused combination causes the read address to be incremented by twice the transfer size, i.e. skipping over alternate addresses. */
#define RP23XX_DMA_CTRL_TRIG_INCR_READ (1 << 4) /* If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. Generally this should be disabled for peripheral-to-memory transfers. */
#define RP23XX_DMA_CTRL_TRIG_DATA_SIZE_SHIFT (2) /* Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. */
#define RP23XX_DMA_CTRL_TRIG_DATA_SIZE_MASK (0x03 << RP23XX_DMA_CTRL_TRIG_DATA_SIZE_SHIFT)
#define RP23XX_DMA_CTRL_TRIG_DATA_SIZE_SIZE_BYTE (0x0 << RP23XX_DMA_CTRL_TRIG_DATA_SIZE_SHIFT)
#define RP23XX_DMA_CTRL_TRIG_DATA_SIZE_SIZE_HALFWORD (0x1 << RP23XX_DMA_CTRL_TRIG_DATA_SIZE_SHIFT)
#define RP23XX_DMA_CTRL_TRIG_DATA_SIZE_SIZE_WORD (0x2 << RP23XX_DMA_CTRL_TRIG_DATA_SIZE_SHIFT)
#define RP23XX_DMA_CTRL_TRIG_HIGH_PRIORITY (1 << 1) /* HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput. */
#define RP23XX_DMA_CTRL_TRIG_EN (1 << 0) /* DMA Channel Enable. When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high) */
#define RP23XX_DMA_INTR_MASK (0xffff) /* Raw interrupt status for DMA Channels 0..15. Bit n corresponds to channel n. Ignores any masking or forcing. Channel interrupts can be cleared by writing a bit mask to INTR, INTS0 or INTS1. Channel interrupts can be routed to either of two system-level IRQs based on INTE0 and INTE1. This can be used vector different channel interrupts to different ISRs: this might be done to allow NVIC IRQ preemption for more time-critical channels, or to spread IRQ load across different cores. It is also valid to ignore this behaviour and just use INTE0/INTS0/IRQ 0. */
#define RP23XX_DMA_INTE0_MASK (0xffff) /* Set bit n to pass interrupts from channel n to DMA IRQ 0. */
#define RP23XX_DMA_INTF0_MASK (0xffff) /* Write 1s to force the corresponding bits in INTE0. The interrupt remains asserted until INTF0 is cleared. */
#define RP23XX_DMA_INTS0_MASK (0xffff) /* Indicates active channel interrupt requests which are currently causing IRQ 0 to be asserted. Channel interrupts can be cleared by writing a bit mask here. */
#define RP23XX_DMA_INTE1_MASK (0xffff) /* Set bit n to pass interrupts from channel n to DMA IRQ 1. */
#define RP23XX_DMA_INTF1_MASK (0xffff) /* Write 1s to force the corresponding bits in INTE1. The interrupt remains asserted until INTF0 is cleared. */
#define RP23XX_DMA_INTS1_MASK (0xffff) /* Indicates active channel interrupt requests which are currently causing IRQ 1 to be asserted. Channel interrupts can be cleared by writing a bit mask here. */
#define RP23XX_DMA_INTE2_MASK (0xffff) /* Set bit n to pass interrupts from channel n to DMA IRQ 2. */
#define RP23XX_DMA_INTF2_MASK (0xffff) /* Write 1s to force the corresponding bits in INTE2. The interrupt remains asserted until INTF0 is cleared. */
#define RP23XX_DMA_INTS2_MASK (0xffff) /* Indicates active channel interrupt requests which are currently causing IRQ 2 to be asserted. Channel interrupts can be cleared by writing a bit mask here. */
#define RP23XX_DMA_INTE3_MASK (0xffff) /* Set bit n to pass interrupts from channel n to DMA IRQ 3. */
#define RP23XX_DMA_INTF3_MASK (0xffff) /* Write 1s to force the corresponding bits in INTE3. The interrupt remains asserted until INTF0 is cleared. */
#define RP23XX_DMA_INTS3_MASK (0xffff) /* Indicates active channel interrupt requests which are currently causing IRQ 3 to be asserted. Channel interrupts can be cleared by writing a bit mask here. */
#define RP23XX_DMA_TIMER0_X_SHIFT (16) /* Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer. */
#define RP23XX_DMA_TIMER0_X_MASK (0xffff << RP23XX_DMA_TIMER0_X_SHIFT)
#define RP23XX_DMA_TIMER0_Y_MASK (0xffff) /* Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer. */
#define RP23XX_DMA_TIMER1_X_SHIFT (16) /* Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer. */
#define RP23XX_DMA_TIMER1_X_MASK (0xffff << RP23XX_DMA_TIMER1_X_SHIFT)
#define RP23XX_DMA_TIMER1_Y_MASK (0xffff) /* Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer. */
#define RP23XX_DMA_TIMER2_X_SHIFT (16) /* Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer. */
#define RP23XX_DMA_TIMER2_X_MASK (0xffff << RP23XX_DMA_TIMER2_X_SHIFT)
#define RP23XX_DMA_TIMER2_Y_MASK (0xffff) /* Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer. */
#define RP23XX_DMA_TIMER3_X_SHIFT (16) /* Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer. */
#define RP23XX_DMA_TIMER3_X_MASK (0xffff << RP23XX_DMA_TIMER3_X_SHIFT)
#define RP23XX_DMA_TIMER3_Y_MASK (0xffff) /* Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer. */
#define RP23XX_DMA_MULTI_CHAN_TRIGGER_MASK (0xffff) /* Each bit in this register corresponds to a DMA channel. Writing a 1 to the relevant bit is the same as writing to that channel's trigger register; the channel will start if it is currently enabled and not already busy. */
#define RP23XX_DMA_SNIFF_CTRL_OUT_INV (1 << 11) /* If set, the result appears inverted (bitwise complement) when read. This does not affect the way the checksum is calculated; the result is transformed on-the-fly between the result register and the bus. */
#define RP23XX_DMA_SNIFF_CTRL_OUT_REV (1 << 10) /* If set, the result appears bit-reversed when read. This does not affect the way the checksum is calculated; the result is transformed on-the-fly between the result register and the bus. */
#define RP23XX_DMA_SNIFF_CTRL_BSWAP (1 << 9) /* Locally perform a byte reverse on the sniffed data, before feeding into checksum. Note that the sniff hardware is downstream of the DMA channel byteswap performed in the read master: if channel CTRL_BSWAP and SNIFF_CTRL_BSWAP are both enabled, their effects cancel from the sniffer's point of view. */
#define RP23XX_DMA_SNIFF_CTRL_CALC_SHIFT (5)
#define RP23XX_DMA_SNIFF_CTRL_CALC_MASK (0x0f << RP23XX_DMA_SNIFF_CTRL_CALC_SHIFT)
#define RP23XX_DMA_SNIFF_CTRL_CALC_CRC32 (0x0 << RP23XX_DMA_SNIFF_CTRL_CALC_SHIFT) /* Calculate a CRC-32 (IEEE802.3 polynomial) */
#define RP23XX_DMA_SNIFF_CTRL_CALC_CRC32R (0x1 << RP23XX_DMA_SNIFF_CTRL_CALC_SHIFT) /* Calculate a CRC-32 (IEEE802.3 polynomial) with bit reversed data */
#define RP23XX_DMA_SNIFF_CTRL_CALC_CRC16 (0x2 << RP23XX_DMA_SNIFF_CTRL_CALC_SHIFT) /* Calculate a CRC-16-CCITT */
#define RP23XX_DMA_SNIFF_CTRL_CALC_CRC16R (0x3 << RP23XX_DMA_SNIFF_CTRL_CALC_SHIFT) /* Calculate a CRC-16-CCITT with bit reversed data */
#define RP23XX_DMA_SNIFF_CTRL_CALC_EVEN (0xe << RP23XX_DMA_SNIFF_CTRL_CALC_SHIFT) /* XOR reduction over all data. == 1 if the total 1 population count is odd. */
#define RP23XX_DMA_SNIFF_CTRL_CALC_SUM (0xf << RP23XX_DMA_SNIFF_CTRL_CALC_SHIFT) /* Calculate a simple 32-bit checksum (addition with a 32 bit accumulator) */
#define RP23XX_DMA_SNIFF_CTRL_DMACH_SHIFT (1) /* DMA channel for Sniffer to observe */
#define RP23XX_DMA_SNIFF_CTRL_DMACH_MASK (0x0f << RP23XX_DMA_SNIFF_CTRL_DMACH_SHIFT)
#define RP23XX_DMA_SNIFF_CTRL_EN (1 << 0) /* Enable sniffer */
#define RP23XX_DMA_FIFO_LEVELS_RAF_LVL_SHIFT (16) /* Current Read-Address-FIFO fill level */
#define RP23XX_DMA_FIFO_LEVELS_RAF_LVL_MASK (0xff << RP23XX_DMA_FIFO_LEVELS_RAF_LVL_SHIFT)
#define RP23XX_DMA_FIFO_LEVELS_WAF_LVL_SHIFT (8) /* Current Write-Address-FIFO fill level */
#define RP23XX_DMA_FIFO_LEVELS_WAF_LVL_MASK (0xff << RP23XX_DMA_FIFO_LEVELS_WAF_LVL_SHIFT)
#define RP23XX_DMA_FIFO_LEVELS_TDF_LVL_MASK (0xff) /* Current Transfer-Data-FIFO fill level */
#define RP23XX_DMA_CHAN_ABORT_MASK (0xffff) /* Each bit corresponds to a channel. Writing a 1 aborts whatever transfer sequence is in progress on that channel. The bit will remain high until any in-flight transfers have been flushed through the address and data FIFOs. After writing, this register must be polled until it returns all-zero. Until this point, it is unsafe to restart the channel. */
#define RP23XX_DMA_N_CHANNELS_MASK (0x1f)
#define RP23XX_DMA_SECCFG_MASK (0x00000007)
#define RP23XX_DMA_SECCFG_LOCK (1 << 2) /* LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel’s control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. */
#define RP23XX_DMA_SECCFG_S (1 << 1) /* Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. If 1, this channel is controllable only from a Secure context. */
#define RP23XX_DMA_SECCFG_P (1 << 0) /* Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level. */
#define RP23XX_DMA_SECCFG_IRQ_MASK (0x00000003)
#define RP23XX_DMA_SECCFG_IRQ_S (1 << 1) /* Secure IRQ. If 1, this IRQ’s control registers can only be accessed from a Secure context. If 0, this IRQ’s control registers can be accessed from a Non-secure context, but Secure channels (as per SECCFG_CHx) are masked from the IRQ status, and this IRQ’s registers can not be used to acknowledge the channel interrupts of Secure channels. */
#define RP23XX_DMA_SECCFG_IRQ_P (1 << 0) /* Privileged IRQ. If 1, this IRQ’s control registers can only be accessed from a Privileged context. If 0, this IRQ’s control registers can be accessed from an Unprivileged context, but Privileged channels (as per SECCFG_CHx) are masked from the IRQ status, and this IRQ’s registers can not be used to acknowledge the channel interrupts of Privileged channels. */
#define RP23XX_DMA_SECCFG_MISC_MASK (0x000003ff)
#define RP23XX_DMA_SECCFG_MISC_TIMER3_S (1 << 9) /* If 1, the TIMER3 register is only accessible from a Secure context, and timer DREQ 3 is only visible to Secure channels. */
#define RP23XX_DMA_SECCFG_MISC_TIMER3_S (1 << 9)
#define RP23XX_DMA_DBG_CTDREQ_MASK (0x3f)
#endif /*__ARCH_ARM_SRC_RP23XX_HARDWARE_RP23XX_DMA_H*/

96
arch/arm/src/rp23xx/hardware/rp23xx_dreq.h Normal file
View file

@ -0,0 +1,96 @@
/****************************************************************************
* arch/arm/src/rp23xx/hardware/rp23xx_dreq.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_RP23XX_HARDWARE_RP23XX_DREQ_H
#define __ARCH_ARM_SRC_RP23XX_HARDWARE_RP23XX_DREQ_H
/****************************************************************************
* Included Files
****************************************************************************/
#include "hardware/rp23xx_memorymap.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#define RP23XX_DMA_DREQ_PIO0_TX0 0
#define RP23XX_DMA_DREQ_PIO0_TX1 1
#define RP23XX_DMA_DREQ_PIO0_TX2 2
#define RP23XX_DMA_DREQ_PIO0_TX3 3
#define RP23XX_DMA_DREQ_PIO0_RX0 4
#define RP23XX_DMA_DREQ_PIO0_RX1 5
#define RP23XX_DMA_DREQ_PIO0_RX2 6
#define RP23XX_DMA_DREQ_PIO0_RX3 7
#define RP23XX_DMA_DREQ_PIO1_TX0 8
#define RP23XX_DMA_DREQ_PIO1_TX1 9
#define RP23XX_DMA_DREQ_PIO1_TX2 10
#define RP23XX_DMA_DREQ_PIO1_TX3 11
#define RP23XX_DMA_DREQ_PIO1_RX0 12
#define RP23XX_DMA_DREQ_PIO1_RX1 13
#define RP23XX_DMA_DREQ_PIO1_RX2 14
#define RP23XX_DMA_DREQ_PIO1_RX3 15
#define RP23XX_DMA_DREQ_PIO2_TX0 16
#define RP23XX_DMA_DREQ_PIO2_TX1 17
#define RP23XX_DMA_DREQ_PIO2_TX2 18
#define RP23XX_DMA_DREQ_PIO2_TX3 19
#define RP23XX_DMA_DREQ_PIO2_RX0 20
#define RP23XX_DMA_DREQ_PIO2_RX1 21
#define RP23XX_DMA_DREQ_PIO2_RX2 22
#define RP23XX_DMA_DREQ_PIO2_RX3 23
#define RP23XX_DMA_DREQ_SPI0_TX 24
#define RP23XX_DMA_DREQ_SPI0_RX 25
#define RP23XX_DMA_DREQ_SPI1_TX 26
#define RP23XX_DMA_DREQ_SPI1_RX 27
#define RP23XX_DMA_DREQ_UART0_TX 28
#define RP23XX_DMA_DREQ_UART0_RX 29
#define RP23XX_DMA_DREQ_UART1_TX 30
#define RP23XX_DMA_DREQ_UART1_RX 31
#define RP23XX_DMA_DREQ_PWM_WRAP0 32
#define RP23XX_DMA_DREQ_PWM_WRAP1 33
#define RP23XX_DMA_DREQ_PWM_WRAP2 34
#define RP23XX_DMA_DREQ_PWM_WRAP3 35
#define RP23XX_DMA_DREQ_PWM_WRAP4 36
#define RP23XX_DMA_DREQ_PWM_WRAP5 37
#define RP23XX_DMA_DREQ_PWM_WRAP6 38
#define RP23XX_DMA_DREQ_PWM_WRAP7 39
#define RP23XX_DMA_DREQ_PWM_WRAP8 40
#define RP23XX_DMA_DREQ_PWM_WRAP9 41
#define RP23XX_DMA_DREQ_PWM_WRAP10 42
#define RP23XX_DMA_DREQ_PWM_WRAP11 43
#define RP23XX_DMA_DREQ_I2C0_TX 44
#define RP23XX_DMA_DREQ_I2C0_RX 45
#define RP23XX_DMA_DREQ_I2C1_TX 46
#define RP23XX_DMA_DREQ_I2C1_RX 47
#define RP23XX_DMA_DREQ_ADC 48
#define RP23XX_DMA_DREQ_XIP_STREAM 49
#define RP23XX_DMA_DREQ_XIP_QMITX 50
#define RP23XX_DMA_DREQ_XIP_QMIRX 51
#define RP23XX_DMA_DREQ_HSTX 52
#define RP23XX_DMA_DREQ_CORESIGHT 53
#define RP23XX_DMA_DREQ_SHA256 54
#define RP23XX_DMA_DREQ_DMA_TIMER0 59
#define RP23XX_DMA_DREQ_DMA_TIMER1 60
#define RP23XX_DMA_DREQ_DMA_TIMER2 61
#define RP23XX_DMA_DREQ_DMA_TIMER3 62
#define RP23XX_DMA_DREQ_FORCE 63
#define RP23XX_DMA_DREQ_COUNT 64
#endif /* __ARCH_ARM_SRC_RP23XX_HARDWARE_RP23XX_DREQ_H */

74
arch/arm/src/rp23xx/hardware/rp23xx_glitch_detector.h Normal file
View file

@ -0,0 +1,74 @@
/****************************************************************************
* arch/arm/src/rp23xx/hardware/rp23xx_glitch_detector.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_RP23XX_HARDWARE_RP23XX_GLITCH_DETECTOR_H
#define __ARCH_ARM_SRC_RP23XX_HARDWARE_RP23XX_GLITCH_DETECTOR_H
/****************************************************************************
* Included Files
****************************************************************************/
#include "hardware/rp23xx_memorymap.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Register offsets *********************************************************/
#define RP23XX_GLITCH_DETECTOR_ARM_OFFSET 0x00000000
#define RP23XX_GLITCH_DETECTOR_DISARM_OFFSET 0x00000004
#define RP23XX_GLITCH_DETECTOR_SENSITIVITY_OFFSET 0x00000008
#define RP23XX_GLITCH_DETECTOR_LOCK_OFFSET 0x0000000c
#define RP23XX_GLITCH_DETECTOR_TRIG_STATUS_OFFSET 0x00000010
#define RP23XX_GLITCH_DETECTOR_TRIG_FORCE_OFFSET 0x00000014
/* Register definitions *****************************************************/
#define RP23XX_GLITCH_DETECTOR_ARM (RP23XX_GLITCH_DETECTOR_BASE + RP23XX_GLITCH_DETECTOR_ARM_OFFSET)
#define RP23XX_GLITCH_DETECTOR_DISARM (RP23XX_GLITCH_DETECTOR_BASE + RP23XX_GLITCH_DETECTOR_DISARM_OFFSET)
#define RP23XX_GLITCH_DETECTOR_SENSITIVITY (RP23XX_GLITCH_DETECTOR_BASE + RP23XX_GLITCH_DETECTOR_SENSITIVITY_OFFSET)
#define RP23XX_GLITCH_DETECTOR_LOCK (RP23XX_GLITCH_DETECTOR_BASE + RP23XX_GLITCH_DETECTOR_LOCK_OFFSET)
#define RP23XX_GLITCH_DETECTOR_TRIG_STATUS (RP23XX_GLITCH_DETECTOR_BASE + RP23XX_GLITCH_DETECTOR_TRIG_STATUS_OFFSET)
#define RP23XX_GLITCH_DETECTOR_TRIG_FORCE (RP23XX_GLITCH_DETECTOR_BASE + RP23XX_GLITCH_DETECTOR_TRIG_FORCE_OFFSET)
/* Register bit definitions *************************************************/
#define RP23XX_GLITCH_DETECTOR_ARM_MASK 0x0000ffff
#define RP23XX_GLITCH_DETECTOR_DISARM_MASK 0x0000ffff
#define RP23XX_GLITCH_DETECTOR_SENSITIVITY_MASK 0xff00ffff
#define RP23XX_GLITCH_DETECTOR_SENSITIVITY_DEFAULT_MASK 0xff000000
#define RP23XX_GLITCH_DETECTOR_SENSITIVITY_DET3_INV_MASK 0x0000c000
#define RP23XX_GLITCH_DETECTOR_SENSITIVITY_DET2_INV_MASK 0x00003000
#define RP23XX_GLITCH_DETECTOR_SENSITIVITY_DET1_INV_MASK 0x00000c00
#define RP23XX_GLITCH_DETECTOR_SENSITIVITY_DET0_INV_MASK 0x00000300
#define RP23XX_GLITCH_DETECTOR_SENSITIVITY_DET3_MASK 0x000000c0
#define RP23XX_GLITCH_DETECTOR_SENSITIVITY_DET2_MASK 0x00000030
#define RP23XX_GLITCH_DETECTOR_SENSITIVITY_DET1_MASK 0x0000000c
#define RP23XX_GLITCH_DETECTOR_SENSITIVITY_DET0_MASK 0x00000003
#define RP23XX_GLITCH_DETECTOR_LOCK_MASK 0x000000ff
#define RP23XX_GLITCH_DETECTOR_TRIG_STATUS_MASK 0x0000000f
#define RP23XX_GLITCH_DETECTOR_TRIG_STATUS_DET3_MASK 0x00000008
#define RP23XX_GLITCH_DETECTOR_TRIG_STATUS_DET2_MASK 0x00000004
#define RP23XX_GLITCH_DETECTOR_TRIG_STATUS_DET1_MASK 0x00000002
#define RP23XX_GLITCH_DETECTOR_TRIG_STATUS_DET0_MASK 0x00000001
#define RP23XX_GLITCH_DETECTOR_TRIG_FORCE_MASK 0x0000000f
#endif /* __ARCH_ARM_SRC_RP23XX_HARDWARE_RP23XX_GLITCH_DETECTOR_H */

77
arch/arm/src/rp23xx/hardware/rp23xx_hstx_ctrl.h Normal file
View file

@ -0,0 +1,77 @@
/****************************************************************************
* arch/arm/src/rp23xx/hardware/rp23xx_hstx_ctrl.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_RP23XX_HARDWARE_RP23XX_HSTX_CTRL_H
#define __ARCH_ARM_SRC_RP23XX_HARDWARE_RP23XX_HSTX_CTRL_H
/****************************************************************************
* Included Files
****************************************************************************/
#include "hardware/rp23xx_memorymap.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Register offsets *********************************************************/
#define RP23XX_HSTX_CTRL_CSR_OFFSET 0x00000000
#define RP23XX_HSTX_CTRL_BIT_OFFSET(n) ((n) * 4 + 0x000004)
#define RP23XX_HSTX_CTRL_EXPAND_SHIFT_OFFSET 0x00000024
#define RP23XX_HSTX_CTRL_EXPAND_TMDS_OFFSET 0x00000028
/* Register definitions *****************************************************/
#define RP23XX_HSTX_CTRL_CSR (RP23XX_HSTX_CTRL_BASE + RP23XX_HSTX_CTRL_CSR_OFFSET)
#define RP23XX_HSTX_CTRL_BIT(n) (RP23XX_HSTX_CTRL_BASE + RP23XX_HSTX_CTRL_BIT_OFFSET(n))
#define RP23XX_HSTX_CTRL_EXPAND_SHIFT (RP23XX_HSTX_CTRL_BASE + RP23XX_HSTX_CTRL_EXPAND_SHIFT_OFFSET)
#define RP23XX_HSTX_CTRL_EXPAND_TMDS (RP23XX_HSTX_CTRL_BASE + RP23XX_HSTX_CTRL_EXPAND_TMDS_OFFSET)
/* Register bit definitions *************************************************/
#define RP23XX_HSTX_CTRL_CSR_MASK (0xff1f1f73)
#define RP23XX_HSTX_CTRL_CSR_CLKDIV_MASK (0xf0000000)
#define RP23XX_HSTX_CTRL_CSR_CLKPHASE_MASK (0x0f000000)
#define RP23XX_HSTX_CTRL_CSR_N_SHIFTS_MASK (0x001f0000)
#define RP23XX_HSTX_CTRL_CSR_SHIFT_MASK (0x00001f00)
#define RP23XX_HSTX_CTRL_CSR_COUPLED_SEL_MASK (0x00000060)
#define RP23XX_HSTX_CTRL_CSR_COUPLED_MODE (1 << 4)
#define RP23XX_HSTX_CTRL_CSR_EXPAND_EN (1 << 1)
#define RP23XX_HSTX_CTRL_CSR_EN (1 << 0)
#define RP23XX_HSTX_CTRL_BIT_MASK (0x00031f1f)
#define RP23XX_HSTX_CTRL_BIT_CLK_MASK (1 << 25)
#define RP23XX_HSTX_CTRL_BIT_INV_MASK (1 << 24)
#define RP23XX_HSTX_CTRL_BIT_SEL_N_MASK (0x00001f00)
#define RP23XX_HSTX_CTRL_BIT_SEL_P_MASK (0x0000001f)
#define RP23XX_HSTX_CTRL_EXPAND_SHIFT_MASK (0x1f1f1f1f)
#define RP23XX_HSTX_CTRL_EXPAND_SHIFT_ENC_N_SHIFTS_MASK (0x1f000000)
#define RP23XX_HSTX_CTRL_EXPAND_SHIFT_ENC_SHIFT_MASK (0x001f0000)
#define RP23XX_HSTX_CTRL_EXPAND_SHIFT_RAW_N_SHIFTS_MASK (0x00001f00)
#define RP23XX_HSTX_CTRL_EXPAND_SHIFT_RAW_SHIFT_MASK (0x0000001f)
#define RP23XX_HSTX_CTRL_EXPAND_TMDS_MASK (0x00ffffff)
#define RP23XX_HSTX_CTRL_EXPAND_TMDS_L2_NBITS_MASK (0x00e00000)
#define RP23XX_HSTX_CTRL_EXPAND_TMDS_L2_ROT_MASK (0x001f0000)
#define RP23XX_HSTX_CTRL_EXPAND_TMDS_L1_NBITS_MASK (0x0000e000)
#define RP23XX_HSTX_CTRL_EXPAND_TMDS_L1_ROT_MASK (0x00001f00)
#define RP23XX_HSTX_CTRL_EXPAND_TMDS_L0_NBITS_MASK (0x000000e0)
#define RP23XX_HSTX_CTRL_EXPAND_TMDS_L0_ROT_MASK (0x0000001f)
#endif /* __ARCH_ARM_SRC_RP23XX_HARDWARE_RP23XX_HSTX_CTRL_H */

53
arch/arm/src/rp23xx/hardware/rp23xx_hstx_fifo.h Normal file
View file

@ -0,0 +1,53 @@
/****************************************************************************
* arch/arm/src/rp23xx/hardware/rp23xx_hstx_fifo.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_RP23XX_HARDWARE_RP23XX_HSTX_FIFO_H
#define __ARCH_ARM_SRC_RP23XX_HARDWARE_RP23XX_HSTX_FIFO_H
/****************************************************************************
* Included Files
****************************************************************************/
#include "hardware/rp23xx_memorymap.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Register offsets *********************************************************/
#define RP23XX_HSTX_FIFO_STAT_OFFSET 0x00000000
#define RP23XX_HSTX_FIFO_FIFO_OFFSET 0x00000004
/* Register definitions *****************************************************/
#define RP23XX_HSTX_FIFO_STAT (RP23XX_HSTX_FIFO_BASE + RP23XX_HSTX_FIFO_STAT_OFFSET)
#define RP23XX_HSTX_FIFO_FIFO (RP23XX_HSTX_FIFO_BASE + RP23XX_HSTX_FIFO_FIFO_OFFSET)
/* Register bit definitions *************************************************/
#define RP23XX_HSTX_FIFO_STAT_MASK (0x000007ff)
#define RP23XX_HSTX_FIFO_STAT_WOF (1 << 10)
#define RP23XX_HSTX_FIFO_STAT_EMPTY (1 << 9)
#define RP23XX_HSTX_FIFO_STAT_FULL (1 << 8)
#define RP23XX_HSTX_FIFO_STAT_LEVEL_MASK (0x000000ff)
#define RP23XX_HSTX_FIFO_FIFO_MASK (0xffffffff)
#endif /* __ARCH_ARM_SRC_RP23XX_HARDWARE_RP23XX_HSTX_FIFO_H */

Some files were not shown because too many files have changed in this diff Show more