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drivers/wireless: Run all wireless drivers through tools/nxstyle, correcting as many complaints as possible.

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This commit is contained in:
Gregory Nutt 2019-12-05 11:49:12 -06:00
parent febf226992
commit 504b0e8b5b
39 changed files with 514 additions and 385 deletions
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36
drivers/wireless/ISM1_868MHzGFSK100kbps.c
View file

@ -53,8 +53,11 @@
* Frequency ERP Duty Cycle Bandwidth Remarks
* 868 – 868.6 MHz +14 dBm < 1% No limits
* 868.7 – 869.2 MHz +14 dBm < 0.1% No limits
* 869.3 – 869.4 MHz +10 dBm No limits < 25 kHz Appropriate access protocol required
* 869.4 – 869.65 MHz +27 dBm < 10% < 25 kHz Channels may be combined to one high speed channel
* 869.3 – 869.4 MHz +10 dBm No limits < 25 kHz Appropriate access
* protocol required
* 869.4 – 869.65 MHz +27 dBm < 10% < 25 kHz Channels may be
* combined to one
* high speed channel
* 869.7 -870 MHz +7 dBm No limits No limits
*
* Deviation = 46.142578
@ -89,35 +92,38 @@ const struct c1101_rfsettings_s cc1101_rfsettings_ISM1_868MHzGFSK100kbps =
.FREQ2 = 0x20, /* FREQ2 Frequency Control Word, High Byte */
.FREQ1 = 0x25, /* FREQ1 Frequency Control Word, Middle Byte */
.FREQ0 = 0xED, /* FREQ0 Frequency Control Word, Low Byte */
.FREQ0 = 0xed, /* FREQ0 Frequency Control Word, Low Byte */
.MDMCFG4 = 0x8B, /* MDMCFG4 Modem Configuration */
.MDMCFG3 = 0xE5, /* MDMCFG3 Modem Configuration */
.MDMCFG4 = 0x8b, /* MDMCFG4 Modem Configuration */
.MDMCFG3 = 0xe5, /* MDMCFG3 Modem Configuration */
.MDMCFG2 = 0x13, /* MDMCFG2 Modem Configuration */
.MDMCFG1 = 0x22, /* MDMCFG1 Modem Configuration */
.MDMCFG0 = 0xE5, /* MDMCFG0 Modem Configuration */
.MDMCFG0 = 0xe5, /* MDMCFG0 Modem Configuration */
.DEVIATN = 0x46, /* DEVIATN Modem Deviation Setting */
.FOCCFG = 0x1D, /* FOCCFG Frequency Offset Compensation Configuration */
.FOCCFG = 0x1d, /* FOCCFG Frequency Offset Compensation Configuration */
.BSCFG = 0x1C, /* BSCFG Bit Synchronization Configuration */
.BSCFG = 0x1c, /* BSCFG Bit Synchronization Configuration */
.AGCCTRL2 = 0xC7, /* AGCCTRL2 AGC Control */
.AGCCTRL2 = 0xc7, /* AGCCTRL2 AGC Control */
.AGCCTRL1 = 0x00, /* AGCCTRL1 AGC Control */
.AGCCTRL0 = 0xB2, /* AGCCTRL0 AGC Control */
.AGCCTRL0 = 0xb2, /* AGCCTRL0 AGC Control */
.FREND1 = 0xB6, /* FREND1 Front End RX Configuration */
.FREND1 = 0xb6, /* FREND1 Front End RX Configuration */
.FREND0 = 0x10, /* FREND0 Front End TX Configuration */
.FSCAL3 = 0xEA, /* FSCAL3 Frequency Synthesizer Calibration */
.FSCAL2 = 0x2A, /* FSCAL2 Frequency Synthesizer Calibration */
.FSCAL3 = 0xea, /* FSCAL3 Frequency Synthesizer Calibration */
.FSCAL2 = 0x2a, /* FSCAL2 Frequency Synthesizer Calibration */
.FSCAL1 = 0x00, /* FSCAL1 Frequency Synthesizer Calibration */
.FSCAL0 = 0x1F, /* FSCAL0 Frequency Synthesizer Calibration */
.FSCAL0 = 0x1f, /* FSCAL0 Frequency Synthesizer Calibration */
.CHMIN = 0, /* Fix at 9th channel: 869.80 MHz +- 100 kHz RF Bandwidth */
.CHMAX = 9, /* single channel */
.PAMAX = 8, /* 0 means power OFF, 8 represents PA[7] */
.PA = {0x03, 0x0F, 0x1E, 0x27, 0x67, 0x50, 0x81, 0xC2}
.PA =
{
0x03, 0x0f, 0x1e, 0x27, 0x67, 0x50, 0x81, 0xc2
}
};

2
drivers/wireless/ISM2_433MHzMSK500kbps.c
View file

@ -118,7 +118,7 @@ const struct c1101_rfsettings_s cc1101_rfsettings_ISM2_433MHzMSK500kbps =
.FREND0 = 0x10, /* FREND0 Front End TX Configuration */
.FSCAL3 = 0xea, /* FSCAL3 Frequency Synthesizer Calibration */
.FSCAL2 = 0x2A, /* FSCAL2 Frequency Synthesizer Calibration */
.FSCAL2 = 0x2a, /* FSCAL2 Frequency Synthesizer Calibration */
.FSCAL1 = 0x00, /* FSCAL1 Frequency Synthesizer Calibration */
.FSCAL0 = 0x1f, /* FSCAL0 Frequency Synthesizer Calibration */

38
drivers/wireless/ISM2_905MHzGFSK250kbps.c
View file

@ -70,7 +70,8 @@
* Data rate = 249.939
* RX filter BW = 541.666667
* Data format = Normal mode
* Length config = Variable packet length mode. Packet length configured by the first byte after sync word
* Length config = Variable packet length mode. Packet length configured
* by the first byte after sync word
* CRC enable = true
* Packet length = 61
* Device address = 0
@ -82,40 +83,43 @@
const struct c1101_rfsettings_s cc1101_rfsettings_ISM2_905MHzGFSK250kbps =
{
.FSCTRL1 = 0x0C, /* FSCTRL1 Frequency Synthesizer Control */
.FSCTRL1 = 0x0c, /* FSCTRL1 Frequency Synthesizer Control */
.FSCTRL0 = 0x00, /* FSCTRL0 Frequency Synthesizer Control */
.FREQ2 = 0x22, /* FREQ2 Frequency Control Word, High Byte */
.FREQ1 = 0xB1, /* FREQ1 Frequency Control Word, Middle Byte */
.FREQ0 = 0x3B, /* FREQ0 Frequency Control Word, Low Byte */
.FREQ1 = 0xb1, /* FREQ1 Frequency Control Word, Middle Byte */
.FREQ0 = 0x3b, /* FREQ0 Frequency Control Word, Low Byte */
.MDMCFG4 = 0x2D, /* MDMCFG4 Modem Configuration */
.MDMCFG3 = 0x3B, /* MDMCFG3 Modem Configuration */
.MDMCFG4 = 0x2d, /* MDMCFG4 Modem Configuration */
.MDMCFG3 = 0x3b, /* MDMCFG3 Modem Configuration */
.MDMCFG2 = 0x13, /* MDMCFG2 Modem Configuration */
.MDMCFG1 = 0x22, /* MDMCFG1 Modem Configuration */
.MDMCFG0 = 0xF8, /* MDMCFG0 Modem Configuration */
.MDMCFG0 = 0xf8, /* MDMCFG0 Modem Configuration */
.DEVIATN = 0x62, /* DEVIATN Modem Deviation Setting */
.FOCCFG = 0x1D, /* FOCCFG Frequency Offset Compensation Configuration */
.FOCCFG = 0x1d, /* FOCCFG Frequency Offset Compensation Configuration */
.BSCFG = 0x1C, /* BSCFG Bit Synchronization Configuration */
.BSCFG = 0x1c, /* BSCFG Bit Synchronization Configuration */
.AGCCTRL2 = 0xC7, /* AGCCTRL2 AGC Control */
.AGCCTRL2 = 0xc7, /* AGCCTRL2 AGC Control */
.AGCCTRL1 = 0x00, /* AGCCTRL1 AGC Control */
.AGCCTRL0 = 0xB0, /* AGCCTRL0 AGC Control */
.AGCCTRL0 = 0xb0, /* AGCCTRL0 AGC Control */
.FREND1 = 0xB6, /* FREND1 Front End RX Configuration */
.FREND1 = 0xb6, /* FREND1 Front End RX Configuration */
.FREND0 = 0x10, /* FREND0 Front End TX Configuration */
.FSCAL3 = 0xEA, /* FSCAL3 Frequency Synthesizer Calibration */
.FSCAL2 = 0x2A, /* FSCAL2 Frequency Synthesizer Calibration */
.FSCAL3 = 0xea, /* FSCAL3 Frequency Synthesizer Calibration */
.FSCAL2 = 0x2a, /* FSCAL2 Frequency Synthesizer Calibration */
.FSCAL1 = 0x00, /* FSCAL1 Frequency Synthesizer Calibration */
.FSCAL0 = 0x1F, /* FSCAL0 Frequency Synthesizer Calibration */
.FSCAL0 = 0x1f, /* FSCAL0 Frequency Synthesizer Calibration */
.CHMIN = 0, /* VERIFY REGULATIONS! */
.CHMAX = 0xFF,
.CHMAX = 0xff,
.PAMAX = 8, /* 0 means power OFF, 8 represents PA[7] */
.PA = {0x03, 0x0E, 0x1E, 0x27, 0x39, 0x8E, 0xCD, 0xC0}
.PA =
{
0x03, 0x0e, 0x1e, 0x27, 0x39, 0x8e, 0xcd, 0xc0
}
};

3
drivers/wireless/bluetooth/bt_uart_bcm4343x.c
View file

@ -203,6 +203,7 @@ static int uartwriteconf(FAR const struct btuart_lowerhalf_s *lower,
ret = -ECOMM;
goto exit_uartwriteconf;
}
gotlen += ret;
}
@ -288,10 +289,12 @@ static int load_bcm4343x_firmware(FAR const struct btuart_lowerhalf_s *lower)
{
0x04, 0x0e, 0x04, 0x01, g_hcd_write_command, g_hcd_command_byte2, 0x00
};
const uint8_t launch_resp[] =
{
0x04, 0x0e, 0x04, 0x01, g_hcd_launch_command, g_hcd_command_byte2, 0x00
};
const uint8_t download_resp[] =
{
0x04, 0x0e, 0x04, 0x01, g_hcd_patchram_command, g_hcd_command_byte2, 0x00

62
drivers/wireless/cc1101.c
View file

@ -2,8 +2,7 @@
* drivers/wireless/cc1101.c
*
* Copyright (C) 2011 Uros Platise. All rights reserved.
*
* Authors: Uros Platise <uros.platise@isotel.eu>
* Author: Uros Platise <uros.platise@isotel.eu>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@ -122,7 +121,7 @@
#define CC1101_SPIFREQ_BURST 6500000 /* Hz, no delay */
#define CC1101_SPIFREQ_SINGLE 9000000 /* Hz, single access only - no delay */
#define CC1101_MCSM0_VALUE 0x1C
#define CC1101_MCSM0_VALUE 0x1c
/****************************************************************************
* Chipcon CC1101 Internal Registers
@ -140,12 +139,12 @@
#define CC1101_PKTCTRL1 0x07 /* Packet automation control */
#define CC1101_PKTCTRL0 0x08 /* Packet automation control */
#define CC1101_ADDR 0x09 /* Device address */
#define CC1101_CHANNR 0x0A /* Channel number */
#define CC1101_FSCTRL1 0x0B /* Frequency synthesizer control */
#define CC1101_FSCTRL0 0x0C /* Frequency synthesizer control */
#define CC1101_FREQ2 0x0D /* Frequency control word, high byte */
#define CC1101_FREQ1 0x0E /* Frequency control word, middle byte */
#define CC1101_FREQ0 0x0F /* Frequency control word, low byte */
#define CC1101_CHANNR 0x0a /* Channel number */
#define CC1101_FSCTRL1 0x0b /* Frequency synthesizer control */
#define CC1101_FSCTRL0 0x0c /* Frequency synthesizer control */
#define CC1101_FREQ2 0x0d /* Frequency control word, high byte */
#define CC1101_FREQ1 0x0e /* Frequency control word, middle byte */
#define CC1101_FREQ0 0x0f /* Frequency control word, low byte */
#define CC1101_MDMCFG4 0x10 /* Modem configuration */
#define CC1101_MDMCFG3 0x11 /* Modem configuration */
#define CC1101_MDMCFG2 0x12 /* Modem configuration */
@ -156,12 +155,12 @@
#define CC1101_MCSM1 0x17 /* Main Radio Cntrl State Machine config */
#define CC1101_MCSM0 0x18 /* Main Radio Cntrl State Machine config */
#define CC1101_FOCCFG 0x19 /* Frequency Offset Compensation config */
#define CC1101_BSCFG 0x1A /* Bit Synchronization configuration */
#define CC1101_AGCCTRL2 0x1B /* AGC control */
#define CC1101_AGCCTRL1 0x1C /* AGC control */
#define CC1101_AGCCTRL0 0x1D /* AGC control */
#define CC1101_WOREVT1 0x1E /* High byte Event 0 timeout */
#define CC1101_WOREVT0 0x1F /* Low byte Event 0 timeout */
#define CC1101_BSCFG 0x1a /* Bit Synchronization configuration */
#define CC1101_AGCCTRL2 0x1b /* AGC control */
#define CC1101_AGCCTRL1 0x1c /* AGC control */
#define CC1101_AGCCTRL0 0x1d /* AGC control */
#define CC1101_WOREVT1 0x1e /* High byte Event 0 timeout */
#define CC1101_WOREVT0 0x1f /* Low byte Event 0 timeout */
#define CC1101_WORCTRL 0x20 /* Wake On Radio control */
#define CC1101_FREND1 0x21 /* Front end RX configuration */
#define CC1101_FREND0 0x22 /* Front end TX configuration */
@ -172,11 +171,11 @@
#define CC1101_RCCTRL1 0x27 /* RC oscillator configuration */
#define CC1101_RCCTRL0 0x28 /* RC oscillator configuration */
#define CC1101_FSTEST 0x29 /* Frequency synthesizer cal control */
#define CC1101_PTEST 0x2A /* Production test */
#define CC1101_AGCTEST 0x2B /* AGC test */
#define CC1101_TEST2 0x2C /* Various test settings */
#define CC1101_TEST1 0x2D /* Various test settings */
#define CC1101_TEST0 0x2E /* Various test settings */
#define CC1101_PTEST 0x2a /* Production test */
#define CC1101_AGCTEST 0x2b /* AGC test */
#define CC1101_TEST2 0x2c /* Various test settings */
#define CC1101_TEST1 0x2d /* Various test settings */
#define CC1101_TEST0 0x2e /* Various test settings */
/* Status registers */
@ -230,6 +229,7 @@
#define CC1101_MCSM0_XOSC_FORCE_ON 0x01
/* Chip Status Byte */
/* Bit fields in the chip status byte */
#define CC1101_STATUS_CHIP_RDYn_BM 0x80
@ -260,12 +260,12 @@
#define CC1101_MARCSTATE_REGON 0x07
#define CC1101_MARCSTATE_STARTCAL 0x08
#define CC1101_MARCSTATE_BWBOOST 0x09
#define CC1101_MARCSTATE_FS_LOCK 0x0A
#define CC1101_MARCSTATE_IFADCON 0x0B
#define CC1101_MARCSTATE_ENDCAL 0x0C
#define CC1101_MARCSTATE_RX 0x0D
#define CC1101_MARCSTATE_RX_END 0x0E
#define CC1101_MARCSTATE_RX_RST 0x0F
#define CC1101_MARCSTATE_FS_LOCK 0x0a
#define CC1101_MARCSTATE_IFADCON 0x0b
#define CC1101_MARCSTATE_ENDCAL 0x0c
#define CC1101_MARCSTATE_RX 0x0d
#define CC1101_MARCSTATE_RX_END 0x0e
#define CC1101_MARCSTATE_RX_RST 0x0f
#define CC1101_MARCSTATE_TXRX_SWITCH 0x10
#define CC1101_MARCSTATE_RXFIFO_OVERFLOW 0x11
#define CC1101_MARCSTATE_FSTXON 0x12
@ -434,7 +434,9 @@ static int cc1101_file_close(FAR struct file *filep)
}
dev->ops.irq(dev, false);
// nrf24l01_changestate(dev, ST_POWER_DOWN);
#if 0
nrf24l01_changestate(dev, ST_POWER_DOWN);
#endif
dev->nopens--;
nxsem_post(&dev->devsem);
@ -970,13 +972,14 @@ void cc1101_setpacketctrl(struct cc1101_dev_s *dev)
values[0] = 0x07; /* No time-out */
values[1] = 0x03; /* Clear channel if RSSI < thr && !receiving;
* TX -> RX, RX -> RX: 0x3F */
* TX -> RX, RX -> RX: 0x3f */
values[2] =
CC1101_MCSM0_VALUE; /* Calibrate on IDLE -> RX/TX, OSC Timeout = ~500 us
* TODO: has XOSC_FORCE_ON */
cc1101_access(dev, CC1101_MCSM2, values, -3);
/* Wake-On Radio Control */
/* Not used yet. */
/* WOREVT1:WOREVT0 - 16-bit timeout register */
@ -1560,7 +1563,8 @@ void cc1101_isr_process(FAR void *arg)
case CC1101_RECV:
{
uint8_t buf[CC1101_FIFO_SIZE], len;
uint8_t buf[CC1101_FIFO_SIZE];
uint8_t len;
memset(buf, 0, sizeof(buf));
len = cc1101_read(dev, buf, sizeof(buf));

4
drivers/wireless/ieee80211/bcm43xxx/bcmf_chip_43362.c
View file

@ -62,10 +62,9 @@ extern const unsigned int bcm43362_firmware_image_len;
const struct bcmf_sdio_chip bcmf_43362_config_sdio =
{
/* General chip stats */
.ram_size = 0x3C000,
.ram_size = 0x3c000,
/* Backplane architecture */
@ -81,6 +80,7 @@ const struct bcmf_sdio_chip bcmf_43362_config_sdio =
},
/* Firmware images */
/* TODO find something smarter than using image_len references */
.nvram_image = (FAR uint8_t *)bcm43362_nvram_image,

1
drivers/wireless/ieee80211/bcm43xxx/bcmf_chip_43438.c
View file

@ -83,6 +83,7 @@ const struct bcmf_sdio_chip bcmf_43438_config_sdio =
},
/* Firmware images */
/* TODO find something smarter than using image_len references */
.nvram_image = (FAR uint8_t *)ap6212_nvram_image,

24
drivers/wireless/ieee80211/bcm43xxx/bcmf_sdio.c
View file

@ -66,15 +66,6 @@
#include "bcmf_sdio_core.h"
#include "bcmf_sdio_regs.h"
/* Supported chip configurations */
#ifdef CONFIG_IEEE80211_BROADCOM_BCM43362
extern const struct bcmf_sdio_chip bcmf_43362_config_sdio;
#endif
#ifdef CONFIG_IEEE80211_BROADCOM_BCM43438
extern const struct bcmf_sdio_chip bcmf_43438_config_sdio;
#endif
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
@ -88,16 +79,25 @@
#define BCMF_WAITDOG_TIMEOUT_TICK (5*CLOCKS_PER_SEC)
/* Chipcommon registers */
/* Chip-common registers */
#define CHIPCOMMON_GPIO_CONTROL ((uint32_t)(0x18000000 + 0x6C) )
#define CHIPCOMMON_GPIO_CONTROL ((uint32_t)(0x18000000 + 0x6c) )
#define CHIPCOMMON_SR_CONTROL0 ((uint32_t)(0x18000000 + 0x504) )
#define CHIPCOMMON_SR_CONTROL1 ((uint32_t)(0x18000000 + 0x508) )
/****************************************************************************
* Private Types
* Public Data
****************************************************************************/
/* Supported chip configurations */
#ifdef CONFIG_IEEE80211_BROADCOM_BCM43362
extern const struct bcmf_sdio_chip bcmf_43362_config_sdio;
#endif
#ifdef CONFIG_IEEE80211_BROADCOM_BCM43438
extern const struct bcmf_sdio_chip bcmf_43438_config_sdio;
#endif
/****************************************************************************
* Private Function Prototypes
****************************************************************************/

43
drivers/wireless/ieee802154/at86rf23x/at86rf23x.c
View file

@ -73,12 +73,12 @@
# error CONFIG_SPI_EXCHANGE required for this driver
#endif
#ifndef CONFIG_IEEE802154_at86rf23x_SPIMODE
# define CONFIG_IEEE802154_at86rf23x_SPIMODE SPIDEV_MODE0
#ifndef CONFIG_IEEE802154_AT86RF23X_SPIMODE
# define CONFIG_IEEE802154_AT86RF23X_SPIMODE SPIDEV_MODE0
#endif
#ifndef CONFIG_IEEE802154_at86rf23x_FREQUENCY
# define CONFIG_IEEE802154_at86rf23x_FREQUENCY 1000000
#ifndef CONFIG_IEEE802154_AT86RF23X_FREQUENCY
# define CONFIG_IEEE802154_AT86RF23X_FREQUENCY 1000000
#endif
/* Definitions for the device structure */
@ -136,9 +136,9 @@ static int at86rf23x_writeframe(FAR struct spi_dev_s *spi,
FAR uint8_t *frame, uint8_t len);
static uint8_t at86rf23x_readframe(FAR struct spi_dev_s *spi,
FAR uint8_t *frame_rx);
static int at86rf23x_setTRXstate(FAR struct at86rf23x_dev_s *dev,
static int at86rf23x_set_trxstate(FAR struct at86rf23x_dev_s *dev,
uint8_t state, uint8_t force);
static uint8_t at86rf23x_getTRXstate(FAR struct at86rf23x_dev_s *dev);
static uint8_t at86rf23x_get_trxstate(FAR struct at86rf23x_dev_s *dev);
static int at86rf23x_resetrf(FAR struct at86rf23x_dev_s *dev);
static int at86rf23x_initialize(FAR struct at86rf23x_dev_s *dev);
@ -224,8 +224,8 @@ static void at86rf23x_lock(FAR struct spi_dev_s *spi)
{
SPI_LOCK(spi, 1);
SPI_SETBITS(spi, 8);
SPI_SETMODE(spi, CONFIG_IEEE802154_at86rf23x_SPIMODE);
SPI_SETFREQUENCY(spi, CONFIG_IEEE802154_at86rf23x_FREQUENCY);
SPI_SETMODE(spi, CONFIG_IEEE802154_AT86RF23X_SPIMODE);
SPI_SETFREQUENCY(spi, CONFIG_IEEE802154_AT86RF23X_FREQUENCY);
}
/****************************************************************************
@ -399,20 +399,20 @@ static uint8_t at86rf23x_readframe(FAR struct spi_dev_s *spi,
}
/****************************************************************************
* Name: at86rf23x_getTRXstate
* Name: at86rf23x_get_trxstate
*
* Description:
* Return the current status of the TRX state machine.
*
****************************************************************************/
static uint8_t at86rf23x_getTRXstate(FAR struct at86rf23x_dev_s *dev)
static uint8_t at86rf23x_get_trxstate(FAR struct at86rf23x_dev_s *dev)
{
return at86rf23x_getregbits(dev->spi, RF23X_TRXSTATUS_STATUS);
}
/****************************************************************************
* Name: at86rf23x_setTRXstate
* Name: at86rf23x_set_trxstate
*
* Description:
* Set the TRX state machine to the desired state. If the state machine
@ -423,12 +423,12 @@ static uint8_t at86rf23x_getTRXstate(FAR struct at86rf23x_dev_s *dev)
*
****************************************************************************/
static int at86rf23x_setTRXstate(FAR struct at86rf23x_dev_s *dev,
static int at86rf23x_set_trxstate(FAR struct at86rf23x_dev_s *dev,
uint8_t state, uint8_t force)
{
/* Get the current state of the transceiver */
uint8_t status = at86rf23x_getTRXstate(dev);
uint8_t status = at86rf23x_get_trxstate(dev);
int ret = OK;
@ -559,7 +559,7 @@ static int at86rf23x_setTRXstate(FAR struct at86rf23x_dev_s *dev,
up_udelay(RF23X_TIME_TRANSITION_PLL_ACTIVE);
}
status = at86rf23x_getTRXstate(dev);
status = at86rf23x_get_trxstate(dev);
if ((status == TRX_STATUS_RXON) || (status == TRX_STATUS_PLLON))
{
at86rf23x_setregbits(dev->spi, RF23X_TRXCMD_STATE,
@ -670,7 +670,7 @@ static int at86rf23x_setchannel(FAR struct ieee802154_radio_s *ieee,
/* Validate we are in an acceptable mode to change the channel */
state = at86rf23x_getTRXstate(dev);
state = at86rf23x_get_trxstate(dev);
if ((TRX_STATUS_SLEEP == state) || (TRX_STATUS_PON == state))
{
@ -1007,7 +1007,6 @@ static int at86rf23x_gettxpower(FAR struct ieee802154_radio_s *ieee,
switch (reg)
{
case RF23X_TXPWR_POS_4:
*txpwr = 0;
break;
@ -1206,7 +1205,7 @@ static int at86rf23x_resetrf(FAR struct at86rf23x_dev_s *dev)
do
{
trx_status = at86rf23x_setTRXstate(dev, TRX_CMD_TRXOFF, true);
trx_status = at86rf23x_set_trxstate(dev, TRX_CMD_TRXOFF, true);
if (retry_cnt == RF23X_MAX_RETRY_RESET_TO_TRX_OFF)
{
@ -1237,7 +1236,7 @@ static int at86rf23x_rxenable(FAR struct ieee802154_radio_s *ieee, bool state,
/* Set the radio to the receive state */
return at86rf23x_setTRXstate(dev, TRX_CMD_RX_ON, false);
return at86rf23x_set_trxstate(dev, TRX_CMD_RX_ON, false);
/* Enable the RX IRQ */
@ -1310,7 +1309,7 @@ static int at86rf23x_regdump(FAR struct at86rf23x_dev_s *dev)
if ((i & 0x0f) == 0)
{
len = sprintf(buf, "%02x: ", i & 0xFF);
len = sprintf(buf, "%02x: ", i & 0xff);
}
/* Print the register value */
@ -1450,7 +1449,7 @@ static int at86rf23x_transmit(FAR struct ieee802154_radio_s *ieee,
* 3. Where do we control the retry process?
*/
if (at86rf23x_setTRXstate(dev, TRX_CMD_PLL_ON, false))
if (at86rf23x_set_trxstate(dev, TRX_CMD_PLL_ON, false))
{
at86rf23x_writeframe(dev->spi, packet->data, packet->len);
}
@ -1518,7 +1517,7 @@ FAR struct ieee802154_radio_s *
/* Turn the PLL to the on state */
at86rf23x_setTRXstate(dev, TRX_CMD_PLL_ON, false);
at86rf23x_set_trxstate(dev, TRX_CMD_PLL_ON, false);
/* SEED value of the CSMA backoff algorithm. */
@ -1574,7 +1573,7 @@ FAR struct ieee802154_radio_s *
#if 0
/* Put the Device to RX ON Mode */
at86rf23x_setTRXstate(dev, TRX_CMD_RX_ON, false);
at86rf23x_set_trxstate(dev, TRX_CMD_RX_ON, false);
#endif
/* Enable Radio IRQ */

2
drivers/wireless/ieee802154/mrf24j40/mrf24j40.c
View file

@ -355,7 +355,6 @@ void mrf24j40_beacon_trigger(FAR struct mrf24j40_radio_s *dev)
void mrf24j40_gts_setup(FAR struct mrf24j40_radio_s *dev, uint8_t fifo,
FAR struct iob_s *frame)
{
}
/****************************************************************************
@ -369,7 +368,6 @@ void mrf24j40_setup_fifo(FAR struct mrf24j40_radio_s *dev,
FAR const uint8_t *buf, uint8_t length,
uint32_t fifo_addr)
{
uint16_t frame_ctrl;
uint16_t addrmode;
int hlen = 3; /* Include frame control and seq number */

13
drivers/wireless/ieee802154/mrf24j40/mrf24j40_getset.c
View file

@ -216,7 +216,7 @@ int mrf24j40_setsaddr(FAR struct mrf24j40_radio_s *dev,
*
* Description:
* Define the device extended address. The following addresses are special:
* FFFFFFFFFFFFFFFFh : Unspecified
* ffffffffffffffffh : Unspecified
*
****************************************************************************/
@ -230,6 +230,7 @@ int mrf24j40_seteaddr(FAR struct mrf24j40_radio_s *dev,
mrf24j40_setreg(dev->spi, MRF24J40_EADR0 + i, eaddr[i]);
dev->addr.eaddr[i] = eaddr[i];
}
wlinfo("%02X:%02X:%02X:%02X:%02X:%02X:%02X:%02X\n", eaddr[0], eaddr[1],
eaddr[2], eaddr[3], eaddr[4], eaddr[5], eaddr[6], eaddr[7]);
@ -346,7 +347,7 @@ int mrf24j40_settxpower(FAR struct mrf24j40_radio_s *dev,
if (txpwr <= -3000 && txpwr > -3630)
{
reg = 0xC0;
reg = 0xc0;
txpwr += 3000;
}
else if (txpwr <= -2000)
@ -480,18 +481,18 @@ int mrf24j40_setpamode(FAR struct mrf24j40_radio_s *dev, int mode)
{
mrf24j40_setreg(dev->spi, MRF24J40_TRISGPIO, 0x08);
mrf24j40_setreg(dev->spi, MRF24J40_GPIO , 0x08);
mrf24j40_setreg(dev->spi, MRF24J40_TESTMODE, 0x0F);
mrf24j40_setreg(dev->spi, MRF24J40_TESTMODE, 0x0f);
}
else if (mode == MRF24J40_PA_ED)
{
mrf24j40_setreg(dev->spi, MRF24J40_TESTMODE, 0x08);
mrf24j40_setreg(dev->spi, MRF24J40_TRISGPIO, 0x0F);
mrf24j40_setreg(dev->spi, MRF24J40_GPIO , 0x0C);
mrf24j40_setreg(dev->spi, MRF24J40_TRISGPIO, 0x0f);
mrf24j40_setreg(dev->spi, MRF24J40_GPIO , 0x0c);
}
else if (mode == MRF24J40_PA_SLEEP)
{
mrf24j40_setreg(dev->spi, MRF24J40_TESTMODE, 0x08);
mrf24j40_setreg(dev->spi, MRF24J40_TRISGPIO, 0x0F);
mrf24j40_setreg(dev->spi, MRF24J40_TRISGPIO, 0x0f);
mrf24j40_setreg(dev->spi, MRF24J40_GPIO , 0x00);
}
else

9
drivers/wireless/ieee802154/mrf24j40/mrf24j40_interrupt.c
View file

@ -60,6 +60,10 @@ static void mrf24j40_irqwork_txnorm(FAR struct mrf24j40_radio_s *dev);
static void mrf24j40_irqwork_txgts(FAR struct mrf24j40_radio_s *dev,
uint8_t gts_num);
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Name: mrf24j40_irqwork_txnorm
*
@ -275,6 +279,7 @@ static void mrf24j40_irqwork_rx(FAR struct mrf24j40_radio_s *dev)
dev->radiocb->rxframe(dev->radiocb, ind);
done:
/* Enable reception of next packet by flushing the fifo.
* This is an MRF24J40 errata (no. 1).
*/
@ -295,6 +300,10 @@ done:
}
}
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: mrf24j40_irqworker
*

2
drivers/wireless/ieee802154/mrf24j40/mrf24j40_radif.c
View file

@ -646,6 +646,7 @@ int mrf24j40_setattr(FAR struct ieee802154_radio_s *radio,
ret = IEEE802154_STATUS_UNSUPPORTED_ATTRIBUTE;
break;
}
return ret;
}
@ -757,6 +758,7 @@ int mrf24j40_sfupdate(FAR struct ieee802154_radio_s *radio,
{
reg &= ~MRF24J40_TXMCR_SLOTTED;
}
mrf24j40_setreg(dev->spi, MRF24J40_TXMCR, reg);
mrf24j40_setorder(dev, sfspec->beaconorder, sfspec->sforder);

21
drivers/wireless/ieee802154/mrf24j40/mrf24j40_regops.c
View file

@ -49,7 +49,7 @@
#include "mrf24j40_regops.h"
/****************************************************************************
* Internal Driver Functions
* Public Functions
****************************************************************************/
/****************************************************************************
@ -67,7 +67,7 @@ void mrf24j40_setreg(FAR struct spi_dev_s *spi, uint32_t addr, uint8_t val)
if (!(addr & 0x80000000))
{
addr &= 0x3F; /* 6-bit address */
addr &= 0x3f; /* 6-bit address */
addr <<= 1;
addr |= 0x01; /* writing */
buf[0] = addr;
@ -75,11 +75,11 @@ void mrf24j40_setreg(FAR struct spi_dev_s *spi, uint32_t addr, uint8_t val)
}
else
{
addr &= 0x3FF; /* 10-bit address */
addr &= 0x3ff; /* 10-bit address */
addr <<= 5;
addr |= 0x8010; /* writing long */
buf[0] = (addr >> 8);
buf[1] = (addr & 0xFF);
buf[1] = (addr & 0xff);
len = 2;
}
@ -110,7 +110,7 @@ uint8_t mrf24j40_getreg(FAR struct spi_dev_s *spi, uint32_t addr)
{
/* 6-bit address */
addr &= 0x3F;
addr &= 0x3f;
addr <<= 1;
buf[0] = addr;
len = 1;
@ -119,15 +119,15 @@ uint8_t mrf24j40_getreg(FAR struct spi_dev_s *spi, uint32_t addr)
{
/* 10-bit address */
addr &= 0x3FF;
addr &= 0x3ff;
addr <<= 5;
addr |= 0x8000;
buf[0] = (addr >> 8);
buf[1] = (addr & 0xFF);
buf[1] = (addr & 0xff);
len = 2;
}
buf[len++] = 0xFF; /* dummy */
buf[len++] = 0xff; /* dummy */
mrf24j40_spi_lock(spi);
SPI_SELECT (spi, SPIDEV_IEEE802154(0), true);
@ -135,7 +135,6 @@ uint8_t mrf24j40_getreg(FAR struct spi_dev_s *spi, uint32_t addr)
SPI_SELECT (spi, SPIDEV_IEEE802154(0), false);
mrf24j40_spi_unlock(spi);
/* wlinfo("r[%04X]=%02X\n", addr, rx[len - 1]); */
return rx[len - 1];
}
@ -159,7 +158,7 @@ int mrf24j40_regdump(FAR struct mrf24j40_radio_s *dev)
{
if ((i & 15) == 0)
{
len=sprintf(buf, "%02x: ", i & 0xFF);
len = sprintf(buf, "%02x: ", i & 0xff);
}
len += sprintf(buf + len, "%02x ", mrf24j40_getreg(dev->spi, i));
@ -176,7 +175,7 @@ int mrf24j40_regdump(FAR struct mrf24j40_radio_s *dev)
{
if ((i & 15) == 0)
{
len=sprintf(buf, "%02x: ", i & 0xFF);
len = sprintf(buf, "%02x: ", i & 0xff);
}
len += sprintf(buf + len, "%02x ", mrf24j40_getreg(dev->spi, i));

73
drivers/wireless/ieee802154/xbee/xbee.c
View file

@ -19,8 +19,7 @@
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
*
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
@ -144,7 +143,8 @@ static int xbee_interrupt(int irq, FAR void *context, FAR void *arg)
if (work_available(&priv->attnwork))
{
return work_queue(HPWORK, &priv->attnwork, xbee_attnworker, (FAR void *)priv, 0);
return work_queue(HPWORK, &priv->attnwork, xbee_attnworker,
(FAR void *)priv, 0);
}
return OK;
@ -195,9 +195,9 @@ static void xbee_attnworker(FAR void *arg)
/* NOTE: There is a helpful side-effect to trying to get the SPI Lock here
* even when there is a write going on. That is, if the SPI write are on a
* thread with lower priority, trying to get the lock here should boost the
* priority of that thread, helping move along the low-level driver work
* that really should be happening in a high priority way anyway.
* thread with lower priority, trying to get the lock here should boost
* the priority of that thread, helping move along the low-level driver
* work that really should be happening in a high priority way anyway.
*/
SPI_LOCK(priv->spi, 1);
@ -283,7 +283,6 @@ static void xbee_attnworker(FAR void *arg)
if (iob != NULL)
{
iob->io_flink = NULL;
iob->io_len = 0;
iob->io_offset = 0;
@ -334,6 +333,7 @@ static void xbee_attnworker(FAR void *arg)
{
previob = previob->io_flink;
}
previob->io_flink = NULL;
}
@ -497,7 +497,7 @@ static bool xbee_verify_checksum(FAR const struct iob_s *iob)
checksum += iob->io_data[i];
}
if (checksum != 0xFF)
if (checksum != 0xff)
{
wlwarn("Invalid checksum\n");
return false;
@ -572,9 +572,11 @@ static void xbee_process_apiframes(FAR struct xbee_priv_s *priv,
}
}
#endif
wlinfo("Modem Status: %d\n", frame->io_data[frame->io_offset++]);
}
break;
case XBEE_APIFRAME_ATRESPONSE:
{
frame->io_offset++; /* Skip over frame index */
@ -633,9 +635,9 @@ static void xbee_process_apiframes(FAR struct xbee_priv_s *priv,
wlinfo("Association Indication: %d\n",
frame->io_data[frame->io_offset]);
/* 0xFF = No assocication status determined yet. */
/* 0xff = No assocication status determined yet. */
if (frame->io_data[frame->io_offset] != 0xFF &&
if (frame->io_data[frame->io_offset] != 0xff &&
frame->io_data[frame->io_offset] != 0x13)
{
wd_cancel(priv->assocwd);
@ -646,7 +648,8 @@ static void xbee_process_apiframes(FAR struct xbee_priv_s *priv,
if (frame->io_data[frame->io_offset] == 0)
{
primitive->u.assocconf.status = IEEE802154_STATUS_SUCCESS;
primitive->u.assocconf.status =
IEEE802154_STATUS_SUCCESS;
#ifdef CONFIG_XBEE_LOCKUP_WORKAROUND
/* Upon successful association, we know that the
* channel and PAN ID give us a valid connection.
@ -658,14 +661,15 @@ static void xbee_process_apiframes(FAR struct xbee_priv_s *priv,
if (work_available(&priv->backupwork))
{
work_queue(LPWORK, &priv->backupwork, xbee_backup_worker,
(FAR void *)priv, 0);
work_queue(LPWORK, &priv->backupwork,
xbee_backup_worker, (FAR void *)priv, 0);
}
#endif
}
else
{
primitive->u.assocconf.status = IEEE802154_STATUS_FAILURE;
primitive->u.assocconf.status =
IEEE802154_STATUS_FAILURE;
}
xbee_notify(priv, primitive);
@ -715,7 +719,8 @@ static void xbee_process_apiframes(FAR struct xbee_priv_s *priv,
}
else if (memcmp(command, "WR", 2) == 0)
{
wlinfo("Write Complete: %d\n", frame->io_data[frame->io_offset]);
wlinfo("Write Complete: %d\n",
frame->io_data[frame->io_offset]);
}
else
{
@ -734,12 +739,14 @@ static void xbee_process_apiframes(FAR struct xbee_priv_s *priv,
}
}
break;
case XBEE_APIFRAME_TXSTATUS:
{
xbee_process_txstatus(priv, frame->io_data[frame->io_offset],
frame->io_data[frame->io_offset + 1]);
}
break;
case XBEE_APIFRAME_RX_EADDR:
{
nextframe = frame->io_flink;
@ -748,11 +755,13 @@ static void xbee_process_apiframes(FAR struct xbee_priv_s *priv,
frame = nextframe;
/* xbee_process_rxframe takes care of freeing the IOB or passing
* it along to the next highest layer */
* it along to the next highest layer.
*/
continue;
}
break;
case XBEE_APIFRAME_RX_SADDR:
{
nextframe = frame->io_flink;
@ -761,11 +770,13 @@ static void xbee_process_apiframes(FAR struct xbee_priv_s *priv,
frame = nextframe;
/* xbee_process_rxframe takes care of freeing the IOB or passing
* it along to the next highest layer */
* it along to the next highest layer.
*/
continue;
}
break;
default:
{
/* This really should never happen since xbee_validateframe should
@ -1137,15 +1148,16 @@ static void xbee_lockupcheck_worker(FAR void *arg)
* Name: xbee_backup_worker
*
* Description:
* In the case that we need to reset the XBee to bring it out of a locked up
* state, we need to be able to restore it's previous state seemlessly to resume
* operation. In order to achieve this, we backup the parameters using the
* "WR" AT command. We do this at strategic points as we don't know what type
* of memory technology is being used and writing too often may reduce the lifetime
* of the device. The two key points chosen are upon association for endpoint nodes,
* and upon creating a new network for coordinator nodes. These conditions
* indicate that the node is actively communicating on the network and that
* the channel and pan ID are now set for the network.
* In the case that we need to reset the XBee to bring it out of a locked
* up state, we need to be able to restore it's previous state seamlessly
* to resume operation. In order to achieve this, we backup the
* parameters using the "WR" AT command. We do this at strategic points
* as we don't know what type of memory technology is being used and
* writing too often may reduce the lifetime of the device. The two key
* points chosen are upon association for endpoint nodes, and upon
* creating a new network for coordinator nodes. These conditions
* indicate that the node is actively communicating on the network and
* that the channel and pan ID are now set for the network.
*
****************************************************************************/
@ -1255,8 +1267,9 @@ XBEEHANDLE xbee_init(FAR struct spi_dev_s *spi,
priv->lower->enable(priv->lower, true);
/* Trigger a query to tell the XBee to operate in SPI mode. By default the XBee
* uses the UART interface. It switches automatically when a valid SPI frame is received.
/* Trigger a query to tell the XBee to operate in SPI mode. By default the
* XBee uses the UART interface. It switches automatically when a valid
* SPI frame is received.
*
* Use this opportunity to pull the extended address
*/
@ -1395,7 +1408,8 @@ void xbee_send_apiframe(FAR struct xbee_priv_s *priv,
* processing.
*/
iob->io_flink = iob_tryalloc(false, IOBUSER_WIRELESS_RAD802154);
iob->io_flink =
iob_tryalloc(false, IOBUSER_WIRELESS_RAD802154);
iob = iob->io_flink;
if (iob != NULL)
@ -1445,6 +1459,7 @@ void xbee_send_apiframe(FAR struct xbee_priv_s *priv,
{
previob = previob->io_flink;
}
previob->io_flink = NULL;
}

13
drivers/wireless/ieee802154/xbee/xbee_ioctl.c
View file

@ -19,8 +19,7 @@
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
*
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
@ -118,33 +117,39 @@ int xbee_ioctl(XBEEHANDLE xbee, int cmd, unsigned long arg)
&macarg->getreq.attrval);
}
break;
case MAC802154IOC_MLME_SET_REQUEST:
{
ret = xbee_req_set(xbee, macarg->setreq.attr,
&macarg->setreq.attrval);
}
break;
case MAC802154IOC_MLME_START_REQUEST:
{
ret = xbee_req_start(xbee, &macarg->startreq);
}
break;
case MAC802154IOC_MLME_ASSOC_REQUEST:
{
ret = xbee_req_associate(xbee, &macarg->assocreq);
}
break;
case MAC802154IOC_MLME_RESET_REQUEST:
{
ret = xbee_req_reset(xbee, macarg->resetreq.resetattr);
}
break;
#if 0
case MAC802154IOC_MLME_ASSOC_RESPONSE:
{
ret = xbee_resp_associate(xbee, &macarg->assocresp);
}
break;
case MAC802154IOC_MLME_DISASSOC_REQUEST:
{
ret = xbee_req_disassociate(xbee, &macarg->disassocreq);
@ -156,24 +161,26 @@ int xbee_ioctl(XBEEHANDLE xbee, int cmd, unsigned long arg)
ret = xbee_req_rxenable(xbee, &macarg->rxenabreq);
}
break;
case MAC802154IOC_MLME_SCAN_REQUEST:
{
ret = xbee_req_scan(xbee, &macarg->scanreq);
}
break;
case MAC802154IOC_MLME_POLL_REQUEST:
{
ret = xbee_req_poll(xbee, &macarg->pollreq);
}
break;
#endif
default:
wlerr("ERROR: Unrecognized cmd: %d\n", cmd);
ret = -ENOTTY;
break;
}
}
return ret;
}

27
drivers/wireless/ieee802154/xbee/xbee_mac.c
View file

@ -154,7 +154,8 @@ static void xbee_assocworker(FAR void *arg)
{
xbee_send_atquery(priv, "AI");
(void)wd_start(priv->assocwd, XBEE_ASSOC_POLLDELAY, xbee_assoctimer, 1, (wdparm_t)arg);
(void)wd_start(priv->assocwd, XBEE_ASSOC_POLLDELAY, xbee_assoctimer,
1, (wdparm_t)arg);
}
}
@ -341,8 +342,8 @@ int xbee_req_data(XBEEHANDLE xbee,
apiframelen = (frame->io_len - frame->io_offset - 3);
frame->io_data[index++] = XBEE_STARTBYTE;
frame->io_data[index++] = ((apiframelen >> 8) & 0xFF);
frame->io_data[index++] = (apiframelen & 0xFF);
frame->io_data[index++] = ((apiframelen >> 8) & 0xff);
frame->io_data[index++] = (apiframelen & 0xff);
frame->io_data[index++] = frametype;
frame->io_data[index++] = xbee_next_frameid(priv);
@ -466,13 +467,15 @@ int xbee_req_get(XBEEHANDLE xbee, enum ieee802154_attr_e attr,
case IEEE802154_ATTR_MAC_COORD_SADDR:
{
IEEE802154_SADDRCOPY(attrval->mac.coordsaddr, priv->pandesc.coordaddr.saddr);
IEEE802154_SADDRCOPY(attrval->mac.coordsaddr,
priv->pandesc.coordaddr.saddr);
}
break;
case IEEE802154_ATTR_MAC_COORD_EADDR:
{
IEEE802154_EADDRCOPY(attrval->mac.coordeaddr, priv->pandesc.coordaddr.eaddr);
IEEE802154_EADDRCOPY(attrval->mac.coordeaddr,
priv->pandesc.coordaddr.eaddr);
}
break;
@ -552,21 +555,25 @@ int xbee_req_set(XBEEHANDLE xbee, enum ieee802154_attr_e attr,
xbee_set_panid(priv, attrval->mac.panid);
}
break;
case IEEE802154_ATTR_MAC_EADDR:
{
ret = IEEE802154_STATUS_DENIED;
}
break;
case IEEE802154_ATTR_MAC_SADDR:
{
xbee_set_saddr(priv, attrval->mac.saddr);
}
break;
case IEEE802154_ATTR_PHY_CHAN:
{
xbee_set_chan(priv, attrval->phy.chan);
}
break;
case IEEE802154_ATTR_MAC_ASSOCIATION_PERMIT:
{
if (attrval->mac.assocpermit)
@ -579,6 +586,7 @@ int xbee_req_set(XBEEHANDLE xbee, enum ieee802154_attr_e attr,
}
}
break;
case IEEE802154_ATTR_PHY_TX_POWER:
{
/* TODO: Convert int32_t dbm input to closest PM/PL settings. Need to
@ -594,20 +602,26 @@ int xbee_req_set(XBEEHANDLE xbee, enum ieee802154_attr_e attr,
xbee_set_coordsaddr(priv, attrval->mac.coordsaddr);
}
break;
case IEEE802154_ATTR_MAC_COORD_EADDR:
{
xbee_set_coordeaddr(priv, attrval->mac.coordeaddr);
}
break;
case IEEE802154_ATTR_MAC_RESPONSE_WAIT_TIME:
{
priv->resp_waittime = attrval->mac.resp_waittime;
}
break;
case IEEE802154_ATTR_MAC_RX_ON_WHEN_IDLE:
{
xbee_setrxonidle(priv, attrval->mac.rxonidle);
}
break;
#endif
default:
{
wlwarn("Unsupported attribute\n");
@ -684,7 +698,8 @@ int xbee_req_associate(XBEEHANDLE xbee, FAR struct ieee802154_assoc_req_s *req)
* an update.
*/
return wd_start(priv->assocwd, XBEE_ASSOC_POLLDELAY, xbee_assoctimer, 1, (wdparm_t)priv);
return wd_start(priv->assocwd, XBEE_ASSOC_POLLDELAY, xbee_assoctimer,
1, (wdparm_t)priv);
}
/****************************************************************************

3
drivers/wireless/ieee802154/xbee/xbee_netdev.c
View file

@ -184,6 +184,7 @@ static int xbeenet_rxframe(FAR struct xbeenet_driver_s *maccb,
FAR struct ieee802154_data_ind_s *ind);
/* Network interface support ************************************************/
/* Common TX logic */
static int xbeenet_txpoll_callback(FAR struct net_driver_s *dev);
@ -518,7 +519,6 @@ static int xbeenet_rxframe(FAR struct xbeenet_driver_s *priv,
}
}
if (ret < 0)
#endif
{
@ -1122,7 +1122,6 @@ static int xbeenet_ioctl(FAR struct net_driver_s *dev, int cmd,
nxsem_post(&priv->xd_exclsem);
return ret;
}
#endif

29
drivers/wireless/lpwan/sx127x/sx127x.c
View file

@ -1016,8 +1016,9 @@ static int sx127x_ioctl(FAR struct file *filep, int cmd, unsigned long arg)
switch (cmd)
{
/* Set radio frequency. Arg: Pointer to
* uint32_t frequency value in Hz ! */
/* Set radio frequency. Arg: Pointer to uint32_t frequency value in
* Hz.
*/
case WLIOC_SETRADIOFREQ:
{
@ -1028,8 +1029,9 @@ static int sx127x_ioctl(FAR struct file *filep, int cmd, unsigned long arg)
break;
}
/* Get current radio frequency. arg: Pointer
* to uint32_t frequency value in Hz! */
/* Get current radio frequency. arg: Pointer to uint32_t frequency
* value in Hz.
*/
case WLIOC_GETRADIOFREQ:
{
@ -1364,7 +1366,6 @@ static int sx127x_lora_isr0_process(FAR struct sx127x_dev_s *dev)
wlinfo("Invalid LORA RX data!\n");
}
/* After receiving the data in RXSINGLE mode the chip goes into
* STANBY mode
*/
@ -1652,6 +1653,7 @@ static size_t sx127x_fskook_rxhandle(FAR struct sx127x_dev_s *dev)
sx127x_rxfifo_put(dev, (uint8_t *)&rxdata, len);
errout:
/* Return total length */
return len;
@ -1731,6 +1733,7 @@ static size_t sx127x_lora_rxhandle(FAR struct sx127x_dev_s *dev)
sx127x_rxfifo_put(dev, (uint8_t *)&rxdata, len);
errout:
/* Return total length */
return len;
@ -2545,11 +2548,15 @@ errout:
static void sx127x_fskook_init(FAR struct sx127x_dev_s *dev)
{
DEBUGASSERT(dev->modulation == SX127X_MODULATION_FSK ||
dev->modulation == SX127X_MODULATION_OOK);
uint8_t setbits = 0;
uint8_t clrbits = 0;
uint8_t syncword[] =
{
0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01
};
DEBUGASSERT(dev->modulation == SX127X_MODULATION_FSK ||
dev->modulation == SX127X_MODULATION_OOK);
/* Set FDEV */
@ -2567,10 +2574,9 @@ static void sx127x_fskook_init(FAR struct sx127x_dev_s *dev)
sx127x_fskook_seq_start(dev, false);
/* Configure Sync Word
* REVISIT: FSK communication doesnt work if syncword is disabled!
* REVISIT: FSK communication doesn't work if syncword is disabled!
*/
uint8_t syncword[] = {0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01};
sx127x_fskook_syncword_set(dev, syncword, 8);
/* Configure bandwidth */
@ -3598,6 +3604,7 @@ static void sx127x_ops_set(FAR struct sx127x_dev_s *dev, uint8_t modulation)
#endif
#endif /* CONFIG_LPWAN_SX127X_FSKOOK */
}
#ifdef CONFIG_LPWAN_SX127X_LORA
if (modulation == SX127X_MODULATION_LORA)
{
@ -4475,6 +4482,7 @@ static void sx127x_dumpregs(FAR struct sx127x_dev_s *dev)
break;
}
#endif
#ifdef CONFIG_LPWAN_SX127X_FSKOOK
case SX127X_MODULATION_FSK:
case SX127X_MODULATION_OOK:
@ -4483,6 +4491,7 @@ static void sx127x_dumpregs(FAR struct sx127x_dev_s *dev)
break;
}
#endif
default:
{
wlinfo("Unknown SX127X modulation\n");

6
drivers/wireless/nrf24l01.c
View file

@ -794,6 +794,7 @@ static void nrf24l01_tostate(FAR struct nrf24l01_dev_s *dev,
switch (state)
{
case ST_UNKNOWN:
/* Power down the module here... */
case ST_POWER_DOWN:
@ -1886,7 +1887,10 @@ int nrf24l01_settxpower(FAR struct nrf24l01_dev_s *dev, int outpower)
int nrf24l01_gettxpower(FAR struct nrf24l01_dev_s *dev)
{
uint8_t value;
int powers[] = { -18, -12, -6, 0};
int powers[] =
{
-18, -12, -6, 0
};
nrf24l01_lock(dev->spi);

2
drivers/wireless/spirit/drivers/spirit_netdev.c
View file

@ -1157,6 +1157,7 @@ static void spirit_interrupt_work(FAR void *arg)
wlinfo("Pending: %08lx\n", *(FAR unsigned long *)&irqstatus);
/* Process the Spirit1 interrupt */
/* First check for errors */
if (irqstatus.IRQ_RX_FIFO_ERROR != 0)
@ -2790,7 +2791,6 @@ int spirit_hw_initialize(FAR struct spirit_driver_s *priv,
*
****************************************************************************/
int spirit_netdev_initialize(FAR struct spi_dev_s *spi,
FAR const struct spirit_lower_s *lower)
{

9
drivers/wireless/spirit/lib/spirit_aes.c
View file

@ -246,10 +246,11 @@ int spirit_aes_write_key(FAR struct spirit_library_s *spirit,
*
* Input Parameters:
* spirit - Reference to a Spirit library state structure instance
* key pointer to the buffer of 4 words (16 bytes) containing the AES key.
* The first byte of the buffer shall be the most significant byte AES_KEY_0 of the AES key.
* The last byte of the buffer shall be the less significant byte AES_KEY_15 of the AES key.
* This parameter is an uint8_t*.
* key - Pointer to the buffer of 4 words (16 bytes) containing the AES
* key. The first byte of the buffer shall be the most
* significant byte AES_KEY_0 of the AES key.
* The last byte of the buffer shall be the less significant byte
* AES_KEY_15 of the AES key. This parameter is an uint8_t*.
*
* Returned Value:
* Zero (OK) on success; a negated errno value on any failure.

6
drivers/wireless/spirit/lib/spirit_calibration.c
View file

@ -226,7 +226,7 @@ int spirit_calibration_get_rcocal(FAR struct spirit_library_s *spirit,
/* Build the RFB value */
(*rfb) = (regval[0] & 0x0F) << 1 | (regval[1] >> 7);
(*rfb) = (regval[0] & 0x0f) << 1 | (regval[1] >> 7);
}
return ret;
@ -461,7 +461,8 @@ int spirit_calibration_set_vcowin(FAR struct spirit_library_s *spirit,
enum spirit_vcowin_e
spirit_calibration_get_vcowin(FAR struct spirit_library_s *spirit)
{
uint8_t regval1, regval2;
uint8_t regval1;
uint8_t regval2;
enum spirit_vcowin_e refword;
/* Reads the register containing the REFWORD value */
@ -525,7 +526,6 @@ enum spirit_vcowin_e
case 3:
refword = CALIB_TIME_58_67_US_24MHZ;
break;
}
}

2
drivers/wireless/spirit/lib/spirit_csma.c
View file

@ -183,7 +183,7 @@ int spirit_csma_getinfo(FAR struct spirit_library_s *spirit,
/* Reads the Cca length */
csmainit->ccalen = (enum spirit_csmalen_e) (regval[3] & 0xF0);
csmainit->ccalen = (enum spirit_csmalen_e) (regval[3] & 0xf0);
/* Reads the max number of back off */

5
drivers/wireless/spirit/lib/spirit_general.c
View file

@ -458,9 +458,10 @@ enum gm_conf_e spirit_general_get_xogm(FAR struct spirit_library_s *spirit)
(void)spirit_reg_read(spirit, ANA_FUNC_CONF1_BASE, &regval, 1);
/* Mask the GM_CONF field field and returns the settled transconductance of
* the XO at startup */
* the XO at startup.
*/
return ((enum gm_conf_e) ((regval & 0x1C) >> 2));
return ((enum gm_conf_e) ((regval & 0x1c) >> 2));
}
/******************************************************************************

9
drivers/wireless/spirit/lib/spirit_gpio.c
View file

@ -108,7 +108,8 @@ int spirit_gpio_enable_tempsensor(FAR struct spirit_library_s *spirit,
DEBUGASSERT(IS_SPIRIT_FUNCTIONAL_STATE(newstate));
/* Reads the ANA_FUNC_CONF0 register and mask the result to enable or disable
* the temperature sensor */
* the temperature sensor.
*/
ret = spirit_reg_read(spirit, ANA_FUNC_CONF0_BASE, &regval, 1);
if (ret >= 0)
@ -280,7 +281,8 @@ int spirit_gpio_enable_clockoutput(FAR struct spirit_library_s *spirit,
DEBUGASSERT(IS_SPIRIT_FUNCTIONAL_STATE(newstate));
/* Reads the MCU_CK_CONF register and mask the result to enable or disable
* the clock output */
* the clock output.
*/
ret = spirit_reg_read(spirit, MCU_CK_CONF_BASE, &regval, 1);
if (ret >= 0)
@ -335,7 +337,8 @@ int spirit_gpio_clockoutput_initialize(FAR struct spirit_library_s *spirit,
DEBUGASSERT(IS_SPIRIT_CLOCK_OUTPUT_EXTRA_CYCLES(clockoutput->xtracycles));
/* Calculates the register value to write according to the specified
* configuration */
* configuration.
*/
regval = ((uint8_t)(clockoutput->xoprescaler) |
(uint8_t)(clockoutput->rcoprescaler) |

5
drivers/wireless/spirit/lib/spirit_irq.c
View file

@ -64,7 +64,10 @@
int spirit_irq_disable_all(FAR struct spirit_library_s *spirit)
{
uint8_t regval[4] = { 0x00, 0x00, 0x00, 0x00 };
uint8_t regval[4] =
{
0x00, 0x00, 0x00, 0x00
};
/* Writes the IRQ_MASK registers */

4
drivers/wireless/spirit/lib/spirit_linearfifo.c
View file

@ -98,7 +98,7 @@ uint8_t spirit_fifo_get_txcount(FAR struct spirit_library_s *spirit)
/* Build and return value */
return (regval & 0x7F);
return (regval & 0x7f);
}
/******************************************************************************
@ -310,7 +310,7 @@ uint8_t spirit_fifo_get_txalmostfull(FAR struct spirit_library_s *spirit)
/* Build and returns value */
return (regval & 0x7F);
return (regval & 0x7f);
}
/******************************************************************************

3
drivers/wireless/spirit/lib/spirit_pktcommon.c
View file

@ -628,7 +628,8 @@ int spirit_pktcommon_set_syncword(FAR struct spirit_library_s *spirit,
uint8_t spirit_pktcommon_get_syncword(FAR struct spirit_library_s *spirit,
enum spirit_pktsyncword_e syncwordno)
{
uint8_t regaddr, regval;
uint8_t regaddr;
uint8_t regval;
/* Check the parameters */

4
drivers/wireless/spirit/lib/spirit_pktmbus.c
View file

@ -123,7 +123,7 @@ int spirit_pktmbus_get_setup(FAR struct spirit_library_s *spirit,
mbusinit->preamblen = regval[0];
mbusinit->postamblen = regval[1];
mbusinit->submode = (enum spirit_mbus_submode_e) (regval[2] & 0x0E);
mbusinit->submode = (enum spirit_mbus_submode_e) (regval[2] & 0x0e);
}
return ret;
@ -158,7 +158,7 @@ int spirit_pktmbus_set_format(FAR struct spirit_library_s *spirit)
/* Sets format bits. Also set to 0 the direct RX mode bits */
regval &= 0x0F;
regval &= 0x0f;
regval |= ((uint8_t) PCKTCTRL3_PCKT_FRMT_MBUS);
/* Writes value on the PCKTCTRL3 register */

3
drivers/wireless/spirit/lib/spirit_pktstack.c
View file

@ -130,7 +130,8 @@ int spirit_pktstack_initialize(FAR struct spirit_library_s *spirit,
}
/* Address and control length setting: source and destination address are
* always present so ADDRESS_LENGTH=2 */
* always present so ADDRESS_LENGTH=2.
*/
regval[0] = 0x10 | (uint8_t)pktstack->ctrllen;

53
drivers/wireless/spirit/lib/spirit_radio.c
View file

@ -309,7 +309,8 @@ int spirit_radio_initialize(FAR struct spirit_library_s *spirit,
/* Check the channel center frequency is in one of the possible range */
DEBUGASSERT(IS_FREQUENCY_BAND((radioinit->base_frequency +
((fcoffset * spirit->xtal_frequency) / FBASE_DIVIDER) +
((fcoffset * spirit->xtal_frequency) /
FBASE_DIVIDER) +
radioinit->chspace * radioinit->chnum)));
/* Calculates the datarate mantissa and exponent */
@ -1136,7 +1137,8 @@ int spirit_radio_set_foffset_ppm(FAR struct spirit_library_s *spirit,
FBASE_DIVIDER);
/* Calculate the offset respect to RF frequency and according to xtal_ppm
* parameter */
* parameter.
*/
offset = (int32_t)(((float)xtaloffset * fbase) / PPM_FACTOR);
@ -1502,7 +1504,8 @@ uint32_t spirit_radio_get_centerfreq(FAR struct spirit_library_s *spirit)
*
* Input Parameters:
* spirit - Reference to a Spirit library state structure instance
* datarate - datarate expressed in bps. This parameter ranging between 100 and 500000.
* datarate - datarate expressed in bps. This parameter ranging between
* 100 and 500000.
* pcm - pointer to the returned mantissa value.
* pce - pointer to the returned exponent value.
*
@ -1653,7 +1656,7 @@ int spirit_radio_convert_chbandwidth(FAR struct spirit_library_s *spirit,
}
}
delta = 0xFFFF;
delta = 0xffff;
for (j = 0; j < 3; j++)
{
@ -1698,7 +1701,7 @@ int spirit_radio_convert_freqdev(FAR struct spirit_library_s *spirit,
uint32_t bp;
uint32_t b = 0;
uint8_t i;
float xtalDivtmp = (float)spirit->xtal_frequency / (((uint32_t) 1) << 18);
float divtmp = (float)spirit->xtal_frequency / (((uint32_t) 1) << 18);
/* Check the parameters */
@ -1706,7 +1709,7 @@ int spirit_radio_convert_freqdev(FAR struct spirit_library_s *spirit,
for (i = 0; i < 10; i++)
{
a = (uint32_t)(xtalDivtmp * (uint32_t)(7.5 * (1 << i)));
a = (uint32_t)(divtmp * (uint32_t)(7.5 * (1 << i)));
if (fdev < a)
{
break;
@ -1718,7 +1721,7 @@ int spirit_radio_convert_freqdev(FAR struct spirit_library_s *spirit,
for (i = 0; i < 8; i++)
{
bp = b;
b = (uint32_t)(xtalDivtmp * (uint32_t)((8.0 + i) / 2 * (1 << (*pce))));
b = (uint32_t)(divtmp * (uint32_t)((8.0 + i) / 2 * (1 << (*pce))));
if (fdev < b)
{
break;
@ -1754,7 +1757,8 @@ int spirit_radio_convert_freqdev(FAR struct spirit_library_s *spirit,
int spirit_radio_set_datarate(FAR struct spirit_library_s *spirit,
uint32_t datarate)
{
uint8_t dre, regval[2];
uint8_t regval[2];
uint8_t dre;
int ret;
/* Check the parameters */
@ -1975,7 +1979,9 @@ int spirit_radio_set_chfilterbw(FAR struct spirit_library_s *spirit,
uint32_t spirit_radio_get_chfilterbw(FAR struct spirit_library_s *spirit)
{
uint8_t regval, bwm, bwe;
uint8_t regval;
uint8_t bwm;
uint8_t bwe;
/* Read the channel filter register for mantissa and exponent */
@ -2365,7 +2371,8 @@ int spirit_radio_config_patable_dbm(FAR struct spirit_library_s *spirit,
DEBUGASSERT(IS_PA_LOAD_CAP(load));
/* Check the PA level in dBm is in the range and calculate the PA_LEVEL value
* to write in the corresponding register using the linearization formula */
* to write in the corresponding register using the linearization formula.
*/
for (i = 0; i <= nlevels; i++)
{
@ -2401,7 +2408,7 @@ int spirit_radio_config_patable_dbm(FAR struct spirit_library_s *spirit,
* table - Pointer to an array of 8 elements containing the PA value in dbm.
* The first element will be the PA_LEVEL_0 and the last element
* will be PA_LEVEL_7. Any value higher than PA_UPPER_LIMIT implies
( no output power (output stage is in high impedance).
* no output power (output stage is in high impedance).
*
* Returned Value:
* Zero (OK) on success. A negated errno value is returned on any failure.
@ -3440,7 +3447,8 @@ uint8_t spirit_radio_get_afclowgain(FAR struct spirit_library_s *spirit)
uint8_t regval;
/* Read the AFC_0 register, mask the AFC Slow Gain field and return the
* value */
* value.
*/
(void)spirit_reg_read(spirit, AFC0_BASE, &regval, 1);
@ -3760,7 +3768,8 @@ int spirit_radio_enable_agcfreeze_maxatten(FAR struct spirit_library_s *spirit,
DEBUGASSERT(IS_SPIRIT_FUNCTIONAL_STATE(newstate));
/* Read the AGCCTRL_2 register and configure the AGC Start Max Attenuation
* field */
* field.
*/
ret = spirit_reg_read(spirit, AGCCTRL2_BASE, &regval, 1);
if (ret >= 0)
@ -3960,7 +3969,8 @@ uint8_t spirit_radio_get_agcmeasure(FAR struct spirit_library_s *spirit)
int spirit_radio_set_agcholdtime_us(FAR struct spirit_library_s *spirit,
uint8_t time)
{
uint8_t regval, hold;
uint8_t regval;
uint8_t hold;
/* Check the parameter */
@ -4149,7 +4159,8 @@ uint8_t spirit_radio_get_agchighthres(FAR struct spirit_library_s *spirit)
uint8_t regval;
/* Read the AGCCTRL_1 register, mask the THRESHOLD_HIGH field and return the
* value */
* value.
*/
(void)spirit_reg_read(spirit, AGCCTRL1_BASE, &regval, 1);
@ -4216,7 +4227,8 @@ uint8_t spirit_radio_get_agclowthres(FAR struct spirit_library_s *spirit)
uint8_t regval;
/* Read the AGCCTRL_1 register, mask the THRESHOLD_LOW field and return the
* value */
* value.
*/
(void)spirit_reg_read(spirit, AGCCTRL1_BASE, &regval, 1);
@ -4289,7 +4301,8 @@ enum spirit_clkrecmode_e
uint8_t regval;
/* Read the FDEV_0 register, mask the CLOCK_REC_ALGO_SEL field and return
* the value */
* the value.
*/
(void)spirit_reg_read(spirit, FDEV0_BASE, &regval, 1);
@ -4357,7 +4370,8 @@ uint8_t spirit_radio_get_clkrecgain(FAR struct spirit_library_s *spirit)
uint8_t regval;
/* Read the CLOCKREC register, mask the CLK_REC_P_GAIN field and return the
* value */
* value.
*/
(void)spirit_reg_read(spirit, CLOCKREC_BASE, &regval, 1);
@ -4498,7 +4512,8 @@ enum spirit_pstfltlen_e
uint8_t regval;
/* Read the CLOCKREC register, mask the PSTFLT_LEN field and return the
* value */
* value.
*/
(void)spirit_reg_read(spirit, CLOCKREC_BASE, &regval, 1);

2
drivers/wireless/spirit/lib/spirit_spi.c
View file

@ -1,5 +1,5 @@
/******************************************************************************
* drivers/wireless/spirit/lib//spirit_spi.c
* drivers/wireless/spirit/lib/spirit_spi.c
* NuttX SPIRIT SPI driver interface.
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.

54
drivers/wireless/spirit/lib/spirit_timer.c
View file

@ -196,7 +196,10 @@ enum spirit_functional_state_e
int spirit_timer_setup_rxtimeout(FAR struct spirit_library_s *spirit,
uint8_t counter, uint8_t prescaler)
{
uint8_t regval[2] = { prescaler, counter };
uint8_t regval[2] =
{
prescaler, counter
};
/* Writes the prescaler and counter value for RX timeout to the corresponding
* register.
@ -344,7 +347,10 @@ int spirit_timer_get_rxtimeout_setup(FAR struct spirit_library_s *spirit,
*
* Description:
* Sets the LDCR wake up timer initialization registers with the values of
* COUNTER and PRESCALER according to the formula: Twu=(PRESCALER +1)*(COUNTER+1)*Tck,
* COUNTER and PRESCALER according to the formula:
*
* Twu=(PRESCALER + 1) * (COUNTER +1 ) * Tck,
*
* where Tck = 28.818 us. The minimum vale of the wakeup timeout is 28.818us
* (PRESCALER and COUNTER equals to 0) and the maximum value is about 1.89 s
* (PRESCALER anc COUNTER equals to 255).
@ -362,10 +368,14 @@ int spirit_timer_get_rxtimeout_setup(FAR struct spirit_library_s *spirit,
int spirit_timer_setup_wakeuptimer(FAR struct spirit_library_s *spirit,
uint8_t counter, uint8_t prescaler)
{
uint8_t regval[2] = { prescaler, counter };
uint8_t regval[2] =
{
prescaler, counter
};
/* Writes the counter and prescaler value of wake-up timer in the
* corresponding register */
* corresponding register.
*/
return spirit_reg_write(spirit, TIMERS3_LDC_PRESCALER_BASE, regval, 2);
}
@ -399,7 +409,8 @@ int spirit_timer_set_wakeuptimer(FAR struct spirit_library_s *spirit,
spirit_timer_calc_wakeup_values(spirit, desired, &regval[1], &regval[0]);
/* Writes the counter and prescaler value of wake-up timer in the
* corresponding register */
* corresponding register.
*/
return spirit_reg_write(spirit, TIMERS3_LDC_PRESCALER_BASE, regval, 2);
}
@ -497,7 +508,8 @@ int spirit_timer_get_wakeuptimer_setup(FAR struct spirit_library_s *spirit,
*prescaler = regval[0];
*counter = regval[1];
*wakeupmsec = (float)((((*prescaler) + 1) * ((*counter) + 1) * (1000.0 / rco_freq)));
*wakeupmsec = (float)((((*prescaler) + 1) * ((*counter) + 1) *
(1000.0 / rco_freq)));
}
return ret;
@ -529,7 +541,10 @@ int spirit_timer_get_wakeuptimer_setup(FAR struct spirit_library_s *spirit,
int spirit_timer_setup_wakeuptimer_reload(FAR struct spirit_library_s *spirit,
uint8_t counter, uint8_t prescaler)
{
uint8_t regval[2] = { prescaler, counter };
uint8_t regval[2] =
{
prescaler, counter
};
/* Write the counter and prescaler value of reload wake-up timer in the
* corresponding register
@ -570,7 +585,8 @@ int spirit_timer_wakeuptimer_reload(FAR struct spirit_library_s *spirit,
spirit_timer_calc_wakeup_values(spirit, desired, &regval[1], &regval[0]);
/* Writes the counter and prescaler value of reload wake-up timer in the
* corresponding register */
* corresponding register.
*/
return spirit_reg_write(spirit, TIMERS1_LDC_RELOAD_PRESCALER_BASE, regval, 2);
}
@ -679,7 +695,8 @@ int spirit_timer_get_wakeuptimer_reload_setup(FAR struct spirit_library_s *spiri
*prescaler = regval[0];
*counter = regval[1];
*reload = (float)((((*prescaler) + 1) * ((*counter) + 1) * (1000.0 / rco_freq)));
*reload = (float)((((*prescaler) + 1) * ((*counter) + 1) *
(1000.0 / rco_freq)));
}
return ret;
@ -757,19 +774,22 @@ void spirit_timer_calc_wakeup_values(FAR struct spirit_library_s *spirit,
float desired, FAR uint8_t *counter,
FAR uint8_t *prescaler)
{
float rco_freq, err;
float rco_freq;
float err;
uint32_t n;
rco_freq = ((float)spirit_timer_get_rcofrequency(spirit)) / 1000;
/* N cycles in the time base of the timer: - clock of the timer is RCO
* frequency - divide times 1000 more because we have an input in ms
* (variable rco_freq is already this frequency divided by 1000) */
* (variable rco_freq is already this frequency divided by 1000).
*/
n = (uint32_t)(desired * rco_freq);
/* check if it is possible to reach that target with prescaler and counter of
* spirit1 */
* spirit1.
*/
if (n / 0xff > 0xfd)
{
@ -878,18 +898,21 @@ void spirit_timer_calc_rxtimeout_values(FAR struct spirit_library_s *spirit,
/* check if the error is minimum */
err = S_ABS((float)(*counter) * (*prescaler) * 1210000 / xtal_frequency - desired);
err = S_ABS((float)(*counter) * (*prescaler) * 1210000 /
xtal_frequency - desired);
if ((*counter) <= 254)
{
if (S_ABS((float)((*counter) + 1) * (*prescaler) * 1210000 / xtal_frequency - desired) < err)
if (S_ABS((float)((*counter) + 1) * (*prescaler) * 1210000 /
xtal_frequency - desired) < err)
{
(*counter)++;
}
}
/* decrement prescaler and counter according to the logic of this timer in
* spirit1 */
* spirit1.
*/
(*prescaler)--;
if ((*counter) > 1)
@ -968,4 +991,3 @@ int spirit_timer_cmd_reload(FAR struct spirit_library_s *spirit)
return spirit_command(spirit, COMMAND_LDC_RELOAD);
}

7
tools/nxstyle.c
View file

@ -798,6 +798,13 @@ int main(int argc, char **argv, char **envp)
(line[ident_index] != 'x' && line[ident_index] != 'X') ||
line[ident_index - 1] != '0')
{
/* REVISIT: Although pre-processor definitions are
* supposed to be all upper-case, there are exceptions
* such as using 'p' for a decimal point or 'MHz'.
* Those will be reported here, but probably should be
* considered false alarms.
*/
fprintf(stderr,
"Mixed case identifier found at line %d:%d\n",
lineno, ident_index);