forked from nuttx/nuttx-update
arch/arm/src/tiva/hardware: Add ADI 3 REFSYS header file.
This commit is contained in:
Gregory Nutt
parent
f4ae71be70
commit
68584aa6eb
9 changed files with 652 additions and 42 deletions
|
|
@ -51,6 +51,7 @@
|
|||
#include "hardware/tiva_vims.h"
|
||||
#include "hardware/tiva_ddi0_osc.h"
|
||||
#include "hardware/tiva_adi2_refsys.h"
|
||||
#include "hardware/tiva_adi3_refsys.h"
|
||||
|
||||
/******************************************************************************
|
||||
* Private Functions
|
||||
|
|
@ -116,15 +117,15 @@ static void trim_wakeup_fromshutdown(uint32_t fcfg1_revision)
|
|||
if ((getreg32(TIVA_CCFG_SIZE_AND_DIS_FLAGS) &
|
||||
CCFG_SIZE_AND_DIS_FLAGS_DIS_ALT_DCDC_SETTING) == 0)
|
||||
{
|
||||
/* ADI_3_REFSYS:DCDCCTL5[3] (=DITHER_EN) = CCFG_MODE_CONF_1[19]
|
||||
* (=ALT_DCDC_DITHER_EN) ADI_3_REFSYS:DCDCCTL5[2:0](=IPEAK ) =
|
||||
/* ADI3_REFSYS:DCDCCTL5[3] (=DITHER_EN) = CCFG_MODE_CONF_1[19]
|
||||
* (=ALT_DCDC_DITHER_EN) ADI3_REFSYS:DCDCCTL5[2:0](=IPEAK ) =
|
||||
* CCFG_MODE_CONF_1[18:16](=ALT_DCDC_IPEAK ) Using a single 4-bit masked
|
||||
* write since layout is equal for both source and destination
|
||||
*/
|
||||
|
||||
regval = getreg32(TIVA_CCFG_MODE_CONF_1);
|
||||
regval = (0xf0 | (regval >> CCFG_MODE_CONF_1_ALT_DCDC_IPEAK_SHIFT));
|
||||
putreg8((uint8_t)regval, TIVA_ADI3_MASK4B + (ADI_3_REFSYS_DCDCCTL5_OFFSET * 2));
|
||||
putreg8((uint8_t)regval, TIVA_ADI3_MASK4B + (ADI3_REFSYS_DCDCCTL5_OFFSET * 2));
|
||||
}
|
||||
|
||||
/* Enable for JTAG to be powered down(will still be powered on if debugger
|
||||
|
|
|
|||
|
|
@ -53,6 +53,7 @@
|
|||
#include "hardware/tiva_aon_pmctl.h"
|
||||
#include "hardware/tiva_aon_rtc.h"
|
||||
#include "hardware/tiva_adi2_refsys.h"
|
||||
#include "hardware/tiva_adi3_refsys.h"
|
||||
|
||||
/******************************************************************************
|
||||
* Pre-processor Definitions
|
||||
|
|
@ -145,7 +146,7 @@ static void Step_RCOSCHF_CTRIM(uint32_t toCode)
|
|||
|
||||
static void Step_VBG(int32_t target_signed)
|
||||
{
|
||||
/* VBG (ANA_TRIM[5:0]=TRIMTEMP --> ADI_3_REFSYS:REFSYSCTL3.TRIM_VBG) */
|
||||
/* VBG (ANA_TRIM[5:0]=TRIMTEMP --> ADI3_REFSYS:REFSYSCTL3.TRIM_VBG) */
|
||||
|
||||
int32_t current_signed;
|
||||
uint8_t ref_sysctl;
|
||||
|
|
@ -156,9 +157,9 @@ static void Step_VBG(int32_t target_signed)
|
|||
current_signed =
|
||||
(((int32_t)
|
||||
(ref_sysctl <<
|
||||
(32 - ADI_3_REFSYS_REFSYSCTL3_TRIM_VBG_W -
|
||||
ADI_3_REFSYS_REFSYSCTL3_TRIM_VBG_SHIFT))) >>
|
||||
(32 - ADI_3_REFSYS_REFSYSCTL3_TRIM_VBG_W));
|
||||
(32 - ADI3_REFSYS_REFSYSCTL3_TRIM_VBG_W -
|
||||
ADI3_REFSYS_REFSYSCTL3_TRIM_VBG_SHIFT))) >>
|
||||
(32 - ADI3_REFSYS_REFSYSCTL3_TRIM_VBG_W));
|
||||
|
||||
/* Wait for next edge on SCLK_LF (positive or negative) */
|
||||
|
||||
|
|
@ -175,14 +176,14 @@ static void Step_VBG(int32_t target_signed)
|
|||
current_signed--;
|
||||
}
|
||||
|
||||
ref_sysctl &= ~(ADI_3_REFSYS_REFSYSCTL3_BOD_BG_TRIM_EN |
|
||||
ADI_3_REFSYS_REFSYSCTL3_TRIM_VBG_MASK)) |
|
||||
ref_sysctl &= ~(ADI3_REFSYS_REFSYSCTL3_BOD_BG_TRIM_EN |
|
||||
ADI3_REFSYS_REFSYSCTL3_TRIM_VBG_MASK)) |
|
||||
((((uint32_t)current_signed) <<
|
||||
ADI_3_REFSYS_REFSYSCTL3_TRIM_VBG_SHIFT) &
|
||||
ADI_3_REFSYS_REFSYSCTL3_TRIM_VBG_MASK);
|
||||
ADI3_REFSYS_REFSYSCTL3_TRIM_VBG_SHIFT) &
|
||||
ADI3_REFSYS_REFSYSCTL3_TRIM_VBG_MASK);
|
||||
putreg8(ref_sysctl, TIVA_ADI3_REFSYS_REFSYSCTL3);
|
||||
|
||||
ref_sysctl |= ADI_3_REFSYS_REFSYSCTL3_BOD_BG_TRIM_EN;
|
||||
ref_sysctl |= ADI3_REFSYS_REFSYSCTL3_BOD_BG_TRIM_EN;
|
||||
putreg8(ref_sysctl, TIVA_ADI3_REFSYS_REFSYSCTL3);
|
||||
}
|
||||
}
|
||||
|
|
@ -213,8 +214,8 @@ static void trim_wakeup_fromshutdown(uint32_t fcfg1_revision)
|
|||
if ((getreg32(TIVA_CCFG_SIZE_AND_DIS_FLAGS) &
|
||||
CCFG_SIZE_AND_DIS_FLAGS_DIS_ALT_DCDC_SETTING) == 0)
|
||||
{
|
||||
/* ADI_3_REFSYS:DCDCCTL5[3] (=DITHER_EN) = CCFG_MODE_CONF_1[19]
|
||||
* (=ALT_DCDC_DITHER_EN) ADI_3_REFSYS:DCDCCTL5[2:0](=IPEAK ) =
|
||||
/* ADI3_REFSYS:DCDCCTL5[3] (=DITHER_EN) = CCFG_MODE_CONF_1[19]
|
||||
* (=ALT_DCDC_DITHER_EN) ADI3_REFSYS:DCDCCTL5[2:0](=IPEAK ) =
|
||||
* CCFG_MODE_CONF_1[18:16](=ALT_DCDC_IPEAK ) Using a single 4-bit masked
|
||||
* write since layout is equal for both source and destination
|
||||
*/
|
||||
|
|
@ -222,7 +223,7 @@ static void trim_wakeup_fromshutdown(uint32_t fcfg1_revision)
|
|||
regval = getreg32(TIVA_CCFG_MODE_CONF_1);
|
||||
regval = (0xf0 | (regval >> CCFG_MODE_CONF_1_ALT_DCDC_IPEAK_SHIFT));
|
||||
putreg8((uint8_t)regval,
|
||||
TIVA_ADI3_MASK4B + (ADI_3_REFSYS_DCDCCTL5_OFFSET * 2));
|
||||
TIVA_ADI3_MASK4B + (ADI3_REFSYS_DCDCCTL5_OFFSET * 2));
|
||||
}
|
||||
|
||||
/* TBD - Temporarily removed for CC13x2 / CC26x2 */
|
||||
|
|
@ -308,14 +309,14 @@ static void trim_wakeup_fromshutdown(uint32_t fcfg1_revision)
|
|||
putreg8(regval8, TIVA_ADI2_DIR + ADI2_REFSYS_REFSYSCTL0_OFFSET);
|
||||
|
||||
/* Write to register CTLSOCREFSYS2 (addr offset 4) bits[7:4] (TRIMMAG) in
|
||||
* ADI_3_REFSYS
|
||||
* ADI3_REFSYS
|
||||
*/
|
||||
|
||||
regval16 = (ADI_3_REFSYS_REFSYSCTL2_TRIM_VREF_MASK << 8) |
|
||||
regval16 = (ADI3_REFSYS_REFSYSCTL2_TRIM_VREF_MASK << 8) |
|
||||
(((fusedata & FCFG1_SHDW_OSC_BIAS_LDO_TRIM_TRIMMAG_MASK) >>
|
||||
FCFG1_SHDW_OSC_BIAS_LDO_TRIM_TRIMMAG_SHIFT) <<
|
||||
ADI_3_REFSYS_REFSYSCTL2_TRIM_VREF_SHIFT);
|
||||
putreg16(regval16, TIVA_ADI3_MASK8B + (ADI_3_REFSYS_REFSYSCTL2_OFFSET << 1));
|
||||
ADI3_REFSYS_REFSYSCTL2_TRIM_VREF_SHIFT);
|
||||
putreg16(regval16, TIVA_ADI3_MASK8B + (ADI3_REFSYS_REFSYSCTL2_OFFSET << 1));
|
||||
|
||||
/* Get TRIMBOD_EXTMODE or TRIMBOD_INTMODE from EFUSE shadow register in
|
||||
* FCFG1
|
||||
|
|
@ -348,37 +349,37 @@ static void trim_wakeup_fromshutdown(uint32_t fcfg1_revision)
|
|||
AON_PMCTL_PWRCTL_EXT_REG_MODE)
|
||||
{
|
||||
/* Apply VDDS BOD trim value Write to register CTLSOCREFSYS1 (addr
|
||||
* offset 3) bit[7:3] (TRIMBOD) in ADI_3_REFSYS
|
||||
* offset 3) bit[7:3] (TRIMBOD) in ADI3_REFSYS
|
||||
*/
|
||||
|
||||
regval16 = (ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_MASK << 8) |
|
||||
regval16 = (ADI3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_MASK << 8) |
|
||||
(((fusedata & FCFG1_SHDW_ANA_TRIM_TRIMBOD_EXTMODE_MASK) >>
|
||||
FCFG1_SHDW_ANA_TRIM_TRIMBOD_EXTMODE_SHIFT) <<
|
||||
ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_SHIFT);
|
||||
ADI3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_SHIFT);
|
||||
putreg16(regval16,
|
||||
TIVA_ADI3_MASK8B + (ADI_3_REFSYS_REFSYSCTL1_OFFSET << 1));
|
||||
TIVA_ADI3_MASK8B + (ADI3_REFSYS_REFSYSCTL1_OFFSET << 1));
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Apply VDDS BOD trim value Write to register CTLSOCREFSYS1 (addr
|
||||
* offset 3) bit[7:3] (TRIMBOD) in ADI_3_REFSYS
|
||||
* offset 3) bit[7:3] (TRIMBOD) in ADI3_REFSYS
|
||||
*/
|
||||
|
||||
regval16 = (ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_MASK << 8) |
|
||||
regval16 = (ADI3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_MASK << 8) |
|
||||
(((fusedata & FCFG1_SHDW_ANA_TRIM_TRIMBOD_INTMODE_MASK) >>
|
||||
FCFG1_SHDW_ANA_TRIM_TRIMBOD_INTMODE_SHIFT) <<
|
||||
ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_SHIFT);
|
||||
ADI3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_SHIFT);
|
||||
putreg16(regval16,
|
||||
TIVA_ADI3_MASK8B + (ADI_3_REFSYS_REFSYSCTL1_OFFSET << 1));
|
||||
TIVA_ADI3_MASK8B + (ADI3_REFSYS_REFSYSCTL1_OFFSET << 1));
|
||||
}
|
||||
|
||||
/* Load the new VDDS_BOD setting */
|
||||
|
||||
regval8 = getreg8(TIVA_ADI3_REFSYS_REFSYSCTL3);
|
||||
regval8 &= ~ADI_3_REFSYS_REFSYSCTL3_BOD_BG_TRIM_EN;
|
||||
regval8 &= ~ADI3_REFSYS_REFSYSCTL3_BOD_BG_TRIM_EN;
|
||||
putreg8(regval8, TIVA_ADI3_REFSYS_REFSYSCTL3);
|
||||
|
||||
regval8 |= ADI_3_REFSYS_REFSYSCTL3_BOD_BG_TRIM_EN;
|
||||
regval8 |= ADI3_REFSYS_REFSYSCTL3_BOD_BG_TRIM_EN;
|
||||
putreg8(regval8, TIVA_ADI3_REFSYS_REFSYSCTL3);
|
||||
|
||||
SetupStepVddrTrimTo((fusedata &
|
||||
|
|
@ -386,7 +387,7 @@ static void trim_wakeup_fromshutdown(uint32_t fcfg1_revision)
|
|||
FCFG1_SHDW_ANA_TRIM_VDDR_TRIM_SHIFT);
|
||||
}
|
||||
|
||||
/* VBG (ANA_TRIM[5:0]=TRIMTEMP --> ADI_3_REFSYS:REFSYSCTL3.TRIM_VBG) */
|
||||
/* VBG (ANA_TRIM[5:0]=TRIMTEMP --> ADI3_REFSYS:REFSYSCTL3.TRIM_VBG) */
|
||||
|
||||
Step_VBG(((int32_t)
|
||||
(fusedata <<
|
||||
|
|
@ -431,8 +432,8 @@ static void trim_wakeup_fromshutdown(uint32_t fcfg1_revision)
|
|||
* LPM_BIAS_WIDTH_TRIM = 3
|
||||
*/
|
||||
|
||||
putreg8(ADI_3_REFSYS_AUX_DEBUG_LPM_BIAS_BACKUP_EN,
|
||||
TIVA_ADI3_SET + ADI_3_REFSYS_AUX_DEBUG_OFFSET);
|
||||
putreg8(ADI3_REFSYS_AUX_DEBUG_LPM_BIAS_BACKUP_EN,
|
||||
TIVA_ADI3_SET + ADI3_REFSYS_AUX_DEBUG_OFFSET);
|
||||
|
||||
/* Set LPM_BIAS_WIDTH_TRIM = 3
|
||||
* Set mask (bits to be written) in [15:8]
|
||||
|
|
|
|||
|
|
@ -50,6 +50,7 @@
|
|||
#include "hardware/tiva_vims.h"
|
||||
#include "hardware/tiva_ddi0_osc.h"
|
||||
#include "hardware/tiva_aon_pmctl.h"
|
||||
#include "hardware/tiva_adi3_refsys.h"
|
||||
|
||||
/******************************************************************************
|
||||
* Pre-processor Definitions
|
||||
|
|
@ -108,8 +109,8 @@ static void trim_wakeup_fromshutdown(uint32_t fcfg1_revision)
|
|||
if ((getreg32(TIVA_CCFG_SIZE_AND_DIS_FLAGS) &
|
||||
CCFG_SIZE_AND_DIS_FLAGS_DIS_ALT_DCDC_SETTING) == 0)
|
||||
{
|
||||
/* ADI_3_REFSYS:DCDCCTL5[3] (=DITHER_EN) = CCFG_MODE_CONF_1[19]
|
||||
* (=ALT_DCDC_DITHER_EN) ADI_3_REFSYS:DCDCCTL5[2:0](=IPEAK ) =
|
||||
/* ADI3_REFSYS:DCDCCTL5[3] (=DITHER_EN) = CCFG_MODE_CONF_1[19]
|
||||
* (=ALT_DCDC_DITHER_EN) ADI3_REFSYS:DCDCCTL5[2:0](=IPEAK ) =
|
||||
* CCFG_MODE_CONF_1[18:16](=ALT_DCDC_IPEAK ) Using a single 4-bit masked
|
||||
* write since layout is equal for both source and destination
|
||||
*/
|
||||
|
|
@ -117,7 +118,7 @@ static void trim_wakeup_fromshutdown(uint32_t fcfg1_revision)
|
|||
regval = getreg32(TIVA_CCFG_MODE_CONF_1);
|
||||
regval = (0xf0 | regval >> CCFG_MODE_CONF_1_ALT_DCDC_IPEAK_SHIFT);
|
||||
putreg8((uint8_t)regval,
|
||||
TIVA_ADI3_MASK4B + (ADI_3_REFSYS_DCDCCTL5_OFFSET * 2));
|
||||
TIVA_ADI3_MASK4B + (ADI3_REFSYS_DCDCCTL5_OFFSET * 2));
|
||||
}
|
||||
|
||||
/* TBD - Temporarily removed for CC13x2 / CC26x2 */
|
||||
|
|
@ -177,13 +178,13 @@ static void trim_wakeup_fromshutdown(uint32_t fcfg1_revision)
|
|||
|
||||
if (trimreg & FCFG1_DAC_BIAS_CNF_LPM_BIAS_BACKUP_EN)
|
||||
{
|
||||
putreg8(ADI_3_REFSYS_AUX_DEBUG_LPM_BIAS_BACKUP_EN,
|
||||
TIVA_ADI3_SET + ADI_3_REFSYS_AUX_DEBUG_OFFSET);
|
||||
putreg8(ADI3_REFSYS_AUX_DEBUG_LPM_BIAS_BACKUP_EN,
|
||||
TIVA_ADI3_SET + ADI3_REFSYS_AUX_DEBUG_OFFSET);
|
||||
}
|
||||
else
|
||||
{
|
||||
putreg8(ADI_3_REFSYS_AUX_DEBUG_LPM_BIAS_BACKUP_EN,
|
||||
TIVA_ADI3_CLR + ADI_3_REFSYS_AUX_DEBUG_OFFSET);
|
||||
putreg8(ADI3_REFSYS_AUX_DEBUG_LPM_BIAS_BACKUP_EN,
|
||||
TIVA_ADI3_CLR + ADI3_REFSYS_AUX_DEBUG_OFFSET);
|
||||
}
|
||||
|
||||
/* Set LPM_BIAS_WIDTH_TRIM according to FCFG1 configuration */
|
||||
|
|
|
|||
241
arch/arm/src/tiva/hardware/cc13x0/cc13x0_adi3_refsys.h
Normal file
241
arch/arm/src/tiva/hardware/cc13x0/cc13x0_adi3_refsys.h
Normal file
|
|
@ -0,0 +1,241 @@
|
|||
/********************************************************************************************************************
|
||||
* arch/arm/src/tiva/hardware/cc13x0/cc13x0_adi3_refsys.h
|
||||
*
|
||||
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
|
||||
* Authors: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Technical content derives from a TI header file that has a compatible BSD license:
|
||||
*
|
||||
* Copyright (c) 2015-2017, Texas Instruments Incorporated
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
********************************************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X0_CC13X0_ADI3_REFSYS_H
|
||||
#define __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X0_CC13X0_ADI3_REFSYS_H
|
||||
|
||||
/********************************************************************************************************************
|
||||
* Included Files
|
||||
********************************************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
#include "hardware/tiva_memorymap.h"
|
||||
|
||||
/********************************************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
********************************************************************************************************************/
|
||||
|
||||
/* ADI3 REFSYS Register Offsets *************************************************************************************/
|
||||
|
||||
#define TIVA_ADI3_REFSYS_SPARE0_OFFSET 0x0001 /* Analog Test Control */
|
||||
#define TIVA_ADI3_REFSYS_REFSYSCTL0_OFFSET 0x0002
|
||||
#define TIVA_ADI3_REFSYS_REFSYSCTL1_OFFSET 0x0003
|
||||
#define TIVA_ADI3_REFSYS_REFSYSCTL2_OFFSET 0x0004
|
||||
#define TIVA_ADI3_REFSYS_REFSYSCTL3_OFFSET 0x0005
|
||||
#define TIVA_ADI3_REFSYS_DCDCCTL0_OFFSET 0x0006 /* DCDC Control 0 */
|
||||
#define TIVA_ADI3_REFSYS_DCDCCTL1_OFFSET 0x0007 /* DCDC Control 1 */
|
||||
#define TIVA_ADI3_REFSYS_DCDCCTL2_OFFSET 0x0008 /* DCDC Control 2 */
|
||||
#define TIVA_ADI3_REFSYS_DCDCCTL3_OFFSET 0x0009 /* DCDC Control 3 */
|
||||
#define TIVA_ADI3_REFSYS_DCDCCTL4_OFFSET 0x000a
|
||||
#define TIVA_ADI3_REFSYS_DCDCCTL5_OFFSET 0x000b
|
||||
|
||||
/* ADI3 REFSYS Register Addresses ***********************************************************************************/
|
||||
|
||||
#define TIVA_ADI3_REFSYS_SPARE0 (TIVA_ADI3_BASE + TIVA_ADI3_REFSYS_SPARE0_OFFSET)
|
||||
#define TIVA_ADI3_REFSYS_REFSYSCTL0 (TIVA_ADI3_BASE + TIVA_ADI3_REFSYS_REFSYSCTL0_OFFSET)
|
||||
#define TIVA_ADI3_REFSYS_REFSYSCTL1 (TIVA_ADI3_BASE + TIVA_ADI3_REFSYS_REFSYSCTL1_OFFSET)
|
||||
#define TIVA_ADI3_REFSYS_REFSYSCTL2 (TIVA_ADI3_BASE + TIVA_ADI3_REFSYS_REFSYSCTL2_OFFSET)
|
||||
#define TIVA_ADI3_REFSYS_REFSYSCTL3 (TIVA_ADI3_BASE + TIVA_ADI3_REFSYS_REFSYSCTL3_OFFSET)
|
||||
#define TIVA_ADI3_REFSYS_DCDCCTL0 (TIVA_ADI3_BASE + TIVA_ADI3_REFSYS_DCDCCTL0_OFFSET)
|
||||
#define TIVA_ADI3_REFSYS_DCDCCTL1 (TIVA_ADI3_BASE + TIVA_ADI3_REFSYS_DCDCCTL1_OFFSET)
|
||||
#define TIVA_ADI3_REFSYS_DCDCCTL2 (TIVA_ADI3_BASE + TIVA_ADI3_REFSYS_DCDCCTL2_OFFSET)
|
||||
#define TIVA_ADI3_REFSYS_DCDCCTL3 (TIVA_ADI3_BASE + TIVA_ADI3_REFSYS_DCDCCTL3_OFFSET)
|
||||
#define TIVA_ADI3_REFSYS_DCDCCTL4 (TIVA_ADI3_BASE + TIVA_ADI3_REFSYS_DCDCCTL4_OFFSET)
|
||||
#define TIVA_ADI3_REFSYS_DCDCCTL5 (TIVA_ADI3_BASE + TIVA_ADI3_REFSYS_DCDCCTL5_OFFSET)
|
||||
|
||||
/* ADI3 REFSYS Bitfield Definitions *********************************************************************************/
|
||||
|
||||
/* ADI3_REFSYS_SPARE0 */
|
||||
|
||||
#define ADI3_REFSYS_SPARE0_SPARE0_SHIFT (0) /* Bits 0-7: Do not change */
|
||||
#define ADI3_REFSYS_SPARE0_SPARE0_MASK (0xff << ADI3_REFSYS_SPARE0_SPARE0_SHIFT)
|
||||
# define ADI3_REFSYS_SPARE0_SPARE0(n) ((uint32_t)(n) << ADI3_REFSYS_SPARE0_SPARE0_SHIFT)
|
||||
|
||||
/* ADI3_REFSYS_REFSYSCTL0 */
|
||||
|
||||
#define ADI3_REFSYS_REFSYSCTL0_TESTCTL_SHIFT (0) /* Bits 0-7 */
|
||||
#define ADI3_REFSYS_REFSYSCTL0_TESTCTL_MASK (0xff << ADI3_REFSYS_REFSYSCTL0_TESTCTL_SHIFT)
|
||||
# define ADI3_REFSYS_REFSYSCTL0_TESTCTL(n) ((uint32_t)(n) << ADI3_REFSYS_REFSYSCTL0_TESTCTL_SHIFT)
|
||||
# define ADI3_REFSYS_REFSYSCTL0_TESTCTL_NC (0x00 << ADI3_REFSYS_REFSYSCTL0_TESTCTL_SHIFT)
|
||||
# define ADI3_REFSYS_REFSYSCTL0_TESTCTL_IPTAT2U (0x01 << ADI3_REFSYS_REFSYSCTL0_TESTCTL_SHIFT)
|
||||
# define ADI3_REFSYS_REFSYSCTL0_TESTCTL_IVREF4U (0x02 << ADI3_REFSYS_REFSYSCTL0_TESTCTL_SHIFT)
|
||||
# define ADI3_REFSYS_REFSYSCTL0_TESTCTL_IREF4U (0x04 << ADI3_REFSYS_REFSYSCTL0_TESTCTL_SHIFT)
|
||||
# define ADI3_REFSYS_REFSYSCTL0_TESTCTL_VBG (0x08 << ADI3_REFSYS_REFSYSCTL0_TESTCTL_SHIFT)
|
||||
# define ADI3_REFSYS_REFSYSCTL0_TESTCTL_VBGUNBUFF (0x10 << ADI3_REFSYS_REFSYSCTL0_TESTCTL_SHIFT)
|
||||
# define ADI3_REFSYS_REFSYSCTL0_TESTCTL_VREF0P8V (0x20 << ADI3_REFSYS_REFSYSCTL0_TESTCTL_SHIFT)
|
||||
# define ADI3_REFSYS_REFSYSCTL0_TESTCTL_VTEMP (0x40 << ADI3_REFSYS_REFSYSCTL0_TESTCTL_SHIFT)
|
||||
# define ADI3_REFSYS_REFSYSCTL0_TESTCTL_BMCOMPOUT (0x80 << ADI3_REFSYS_REFSYSCTL0_TESTCTL_SHIFT)
|
||||
|
||||
/* ADI3_REFSYS_REFSYSCTL1 */
|
||||
|
||||
#define ADI3_REFSYS_REFSYSCTL1_TESTCTL_SHIFT (0) /* Bits 0-1 */
|
||||
#define ADI3_REFSYS_REFSYSCTL1_TESTCTL_MASK (3 << ADI3_REFSYS_REFSYSCTL1_TESTCTL_SHIFT)
|
||||
# define ADI3_REFSYS_REFSYSCTL1_TESTCTL(n) ((uint32_t)(n) << ADI3_REFSYS_REFSYSCTL1_TESTCTL_SHIFT)
|
||||
# define ADI3_REFSYS_REFSYSCTL1_TESTCTL_NC (0 << ADI3_REFSYS_REFSYSCTL1_TESTCTL_SHIFT)
|
||||
# define ADI3_REFSYS_REFSYSCTL1_TESTCTL_BMCOMPIN (1 << ADI3_REFSYS_REFSYSCTL1_TESTCTL_SHIFT)
|
||||
# define ADI3_REFSYS_REFSYSCTL1_TESTCTL_IPTAT1U (2 << ADI3_REFSYS_REFSYSCTL1_TESTCTL_SHIFT)
|
||||
#define ADI3_REFSYS_REFSYSCTL1_BATMON_COMP_TEST_EN (1 << 2) /* Bit 2 */
|
||||
#define ADI3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_SHIFT (3) /* Bits 3-7 */
|
||||
#define ADI3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_MASK (31 << ADI3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_SHIFT)
|
||||
# define ADI3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD(n) ((uint32_t)(n) << ADI3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_SHIFT)
|
||||
# define ADI3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_4 (0 << ADI3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_SHIFT)
|
||||
# define ADI3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_5 (1 << ADI3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_SHIFT)
|
||||
# define ADI3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_6 (2 << ADI3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_SHIFT)
|
||||
# define ADI3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_7 (3 << ADI3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_SHIFT)
|
||||
# define ADI3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_0 (4 << ADI3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_SHIFT)
|
||||
# define ADI3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_1 (5 << ADI3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_SHIFT)
|
||||
# define ADI3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_2 (6 << ADI3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_SHIFT)
|
||||
# define ADI3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_3 (7 << ADI3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_SHIFT)
|
||||
# define ADI3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_12 (8 << ADI3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_SHIFT)
|
||||
# define ADI3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_13 (9 << ADI3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_SHIFT)
|
||||
# define ADI3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_14 (10 << ADI3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_SHIFT)
|
||||
# define ADI3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_15 (11 << ADI3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_SHIFT)
|
||||
# define ADI3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_8 (12 << ADI3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_SHIFT)
|
||||
# define ADI3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_9 (13 << ADI3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_SHIFT)
|
||||
# define ADI3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_10 (14 << ADI3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_SHIFT)
|
||||
# define ADI3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_11 (15 << ADI3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_SHIFT)
|
||||
# define ADI3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_20 (16 << ADI3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_SHIFT)
|
||||
# define ADI3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_21 (17 << ADI3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_SHIFT)
|
||||
# define ADI3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_22 (18 << ADI3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_SHIFT)
|
||||
# define ADI3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_23 (19 << ADI3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_SHIFT)
|
||||
# define ADI3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_16 (20 << ADI3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_SHIFT)
|
||||
# define ADI3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_17 (21 << ADI3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_SHIFT)
|
||||
# define ADI3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_18 (22 << ADI3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_SHIFT)
|
||||
# define ADI3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_19 (23 << ADI3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_SHIFT)
|
||||
# define ADI3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_28 (24 << ADI3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_SHIFT)
|
||||
# define ADI3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_29 (25 << ADI3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_SHIFT)
|
||||
# define ADI3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_30 (26 << ADI3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_SHIFT)
|
||||
# define ADI3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_31 (27 << ADI3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_SHIFT)
|
||||
# define ADI3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_24 (28 << ADI3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_SHIFT)
|
||||
# define ADI3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_25 (29 << ADI3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_SHIFT)
|
||||
# define ADI3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_26 (30 << ADI3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_SHIFT)
|
||||
# define ADI3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_27 (31 << ADI3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_SHIFT)
|
||||
|
||||
/* ADI3_REFSYS_REFSYSCTL2 */
|
||||
|
||||
#define ADI3_REFSYS_REFSYSCTL2_TRIM_TSENSE_SHIFT (0) /* Bits 0-1 */
|
||||
#define ADI3_REFSYS_REFSYSCTL2_TRIM_TSENSE_MASK (3 << ADI3_REFSYS_REFSYSCTL2_TRIM_TSENSE_SHIFT)
|
||||
# define ADI3_REFSYS_REFSYSCTL2_TRIM_TSENSE(n) ((uint32_t)(n) << ADI3_REFSYS_REFSYSCTL2_TRIM_TSENSE_SHIFT)
|
||||
|
||||
/* ADI3_REFSYS_REFSYSCTL3 */
|
||||
|
||||
#define ADI3_REFSYS_REFSYSCTL3_TRIM_VBG_SHIFT (0) /* Bits 0-5 */
|
||||
#define ADI3_REFSYS_REFSYSCTL3_TRIM_VBG_MASK (0x3f << ADI3_REFSYS_REFSYSCTL3_TRIM_VBG_SHIFT)
|
||||
# define ADI3_REFSYS_REFSYSCTL3_TRIM_VBG(n) ((uint32_t)(n) << ADI3_REFSYS_REFSYSCTL3_TRIM_VBG_SHIFT)
|
||||
#define ADI3_REFSYS_REFSYSCTL3_VTEMP_EN (1 << 6) /* Bit 6 */
|
||||
#define ADI3_REFSYS_REFSYSCTL3_BOD_BG_TRIM_EN (1 << 7) /* Bit 7 */
|
||||
|
||||
/* ADI3_REFSYS_DCDCCTL0 */
|
||||
|
||||
#define ADI3_REFSYS_DCDCCTL0_VDDR_TRIM_SHIFT (0) /* Bits 0-4: Set the VDDR voltage */
|
||||
/* Proprietary encoding */
|
||||
#define ADI3_REFSYS_DCDCCTL0_VDDR_TRIM_MASK (31 << ADI3_REFSYS_DCDCCTL0_VDDR_TRIM_SHIFT)
|
||||
# define ADI3_REFSYS_DCDCCTL0_VDDR_TRIM(n) ((uint32_t)(n) << ADI3_REFSYS_DCDCCTL0_VDDR_TRIM_SHIFT)
|
||||
# define ADI3_REFSYS_DCDCCTL0_VDDR_TRIM_DEFAULT (0 << ADI3_REFSYS_DCDCCTL0_VDDR_TRIM_SHIFT) /* Default, about 1.63V */
|
||||
# define ADI3_REFSYS_DCDCCTL0_VDDR_TRIM_TYPICAL (5 << ADI3_REFSYS_DCDCCTL0_VDDR_TRIM_SHIFT) /* Typical voltage after trim voltage 1.71V */
|
||||
# define ADI3_REFSYS_DCDCCTL0_VDDR_TRIM_MAX (21 << ADI3_REFSYS_DCDCCTL0_VDDR_TRIM_SHIFT) /* Max voltage 1.96V */
|
||||
# define ADI3_REFS */YS_DCDCCTL0_VDDR_TRIM_MIN (22 << ADI3_REFSYS_DCDCCTL0_VDDR_TRIM_SHIFT) /* Min voltage 1.47V
|
||||
#define ADI3_REFSYS_DCDCCTL0_GLDO_ISRC_SHIFT (5) /* Bits 5-7: Set charge and re-charge current level */
|
||||
/* 2's complement encoding */
|
||||
#define ADI3_REFSYS_DCDCCTL0_GLDO_ISRC_MASK (7 << ADI3_REFSYS_DCDCCTL0_GLDO_ISRC_SHIFT)
|
||||
# define ADI3_REFSYS_DCDCCTL0_GLDO_ISRC(n) ((uint32_t)(n) << ADI3_REFSYS_DCDCCTL0_GLDO_ISRC_SHIFT)
|
||||
# define ADI3_REFSYS_DCDCCTL0_GLDO_ISRC_DEFAULT (0 << ADI3_REFSYS_DCDCCTL0_GLDO_ISRC_SHIFT) /* Default 11mA */
|
||||
# define ADI3_REFSYS_DCDCCTL0_GLDO_ISRC_MAX (3 << ADI3_REFSYS_DCDCCTL0_GLDO_ISRC_SHIFT) /* Max 15mA */
|
||||
# define ADI3_REFSYS_DCDCCTL0_GLDO_ISRC_MIN (4 << ADI3_REFSYS_DCDCCTL0_GLDO_ISRC_SHIFT) /* Max 5mA */
|
||||
|
||||
/* ADI3_REFSYS_DCDCCTL1 */
|
||||
|
||||
#define ADI3_REFSYS_DCDCCTL1_VDDR_TRIM_SLEEP_SHIFT (0) /* Bits 0-4: Set the min VDDR voltage threshold during sleep mode */
|
||||
/* Proprietary encoding */
|
||||
#define ADI3_REFSYS_DCDCCTL1_VDDR_TRIM_SLEEP_MASK (31 << ADI3_REFSYS_DCDCCTL1_VDDR_TRIM_SLEEP_SHIFT)
|
||||
# define ADI3_REFSYS_DCDCCTL1_VDDR_TRIM_SLEEP(n) ((uint32_t)(n) << ADI3_REFSYS_DCDCCTL1_VDDR_TRIM_SLEEP_SHIFT)
|
||||
# define ADI3_REFSYS_DCDCCTL1_VDDR_TRIM_SLEEP_DEFAULT (nn << ADI3_REFSYS_DCDCCTL1_VDDR_TRIM_SLEEP_SHIFT) /* Default, about 1.63V */
|
||||
# define ADI3_REFSYS_DCDCCTL1_VDDR_TRIM_SLEEP_TYPICAL (nn << ADI3_REFSYS_DCDCCTL1_VDDR_TRIM_SLEEP_SHIFT) /* Typical voltage after trim voltage 1.52V */
|
||||
# define ADI3_REFSYS_DCDCCTL1_VDDR_TRIM_SLEEP_MAX (nn << ADI3_REFSYS_DCDCCTL1_VDDR_TRIM_SLEEP_SHIFT) /* Max voltage 1.96V */
|
||||
# define ADI3_REFSYS_DCDCCTL1_VDDR_TRIM_SLEEP_MIN (nn << ADI3_REFSYS_DCDCCTL1_VDDR_TRIM_SLEEP_SHIFT) /* Min voltage 1.47V */
|
||||
#define ADI3_REFSYS_DCDCCTL1_VDDR_OK_HYST (1 << 5) /* Bit 5: Increase the hysteresis for when VDDR is considered ok */
|
||||
/* 0: Hysteresis = 60mV; 1: Hysteresis = 70mV */
|
||||
#define ADI3_REFSYS_DCDCCTL1_IPTAT_TRIM_SHIFT (6) /* Bits 6-7: Trim GLDO bias current */
|
||||
/* Proprietary encoding */
|
||||
#define ADI3_REFSYS_DCDCCTL1_IPTAT_TRIM_MASK (3 << ADI3_REFSYS_DCDCCTL1_IPTAT_TRIM_SHIFT)
|
||||
# define ADI3_REFSYS_DCDCCTL1_IPTAT_TRIM(n) ((uint32_t)(n) << ADI3_REFSYS_DCDCCTL1_IPTAT_TRIM_SHIFT)
|
||||
# define ADI3_REFSYS_DCDCCTL1_IPTAT_TRIM_DEFAULT (0 << ADI3_REFSYS_DCDCCTL1_IPTAT_TRIM_SHIFT) /* Default */
|
||||
# define ADI3_REFSYS_DCDCCTL1_IPTAT_TRIM_INC1p3 (1 << ADI3_REFSYS_DCDCCTL1_IPTAT_TRIM_SHIFT) /* Increase GLDO bias by 1.3x */
|
||||
# define ADI3_REFSYS_DCDCCTL1_IPTAT_TRIM_INC1p6 (2 << ADI3_REFSYS_DCDCCTL1_IPTAT_TRIM_SHIFT) /* Increase GLDO bias by 1.6x */
|
||||
# define ADI3_REFSYS_DCDCCTL1_IPTAT_TRIM_DEC0p7 (3 << ADI3_REFSYS_DCDCCTL1_IPTAT_TRIM_SHIFT) /* Decrease GLDO bias by 0.7x */
|
||||
|
||||
/* ADI3_REFSYS_DCDCCTL2 */
|
||||
|
||||
#define ADI3_REFSYS_DCDCCTL2_TESTSEL_SHIFT (0) /* Bits 0-3: Select signal for test bus, one hot */
|
||||
#define ADI3_REFSYS_DCDCCTL2_TESTSEL_MASK (15 << ADI3_REFSYS_DCDCCTL2_TESTSEL_SHIFT)
|
||||
# define ADI3_REFSYS_DCDCCTL2_TESTSEL(n) ((uint32_t)(n) << ADI3_REFSYS_DCDCCTL2_TESTSEL_SHIFT)
|
||||
# define ADI3_REFSYS_DCDCCTL2_TESTSEL_NC (0 << ADI3_REFSYS_DCDCCTL2_TESTSEL_SHIFT) /* No signal connected to test bus */
|
||||
# define ADI3_REFSYS_DCDCCTL2_TESTSEL_ERRAMP_OUT (1 << ADI3_REFSYS_DCDCCTL2_TESTSEL_SHIFT) /* Error amp output voltage connected to test bus */
|
||||
# define ADI3_REFSYS_DCDCCTL2_TESTSEL_PASSGATE (2 << ADI3_REFSYS_DCDCCTL2_TESTSEL_SHIFT) /* Pass transistor gate voltage connected to test bus */
|
||||
# define ADI3_REFSYS_DCDCCTL2_TESTSEL_IB1U (4 << ADI3_REFSYS_DCDCCTL2_TESTSEL_SHIFT) /* 1uA bias current connected to test bus */
|
||||
# define ADI3_REFSYS_DCDCCTL2_TESTSEL_VDDROK (8 << ADI3_REFSYS_DCDCCTL2_TESTSEL_SHIFT) /* VDDR_OK connected to test bus */
|
||||
#define ADI3_REFSYS_DCDCCTL2_BIAS_DIS (1 << 4) /* Bit 4: Disable dummy bias current */
|
||||
#define ADI3_REFSYS_DCDCCTL2_TEST_VDDR (1 << 5) /* Bit 5: Connect VDDR to ATEST bus */
|
||||
#define ADI3_REFSYS_DCDCCTL2_TURNON_EA_SW (1 << 6) /* Bit 6: Turns on GLDO error amp switch */
|
||||
|
||||
/* ADI3_REFSYS_DCDCCTL3 */
|
||||
|
||||
/* ADI3_REFSYS_DCDCCTL4 */
|
||||
|
||||
#define ADI3_REFSYS_DCDCCTL4_HIGH_EN_SEL_SHIFT (0) /* Bits 0-2 */
|
||||
#define ADI3_REFSYS_DCDCCTL4_HIGH_EN_SEL_MASK (7 << ADI3_REFSYS_DCDCCTL4_HIGH_EN_SEL_SHIFT)
|
||||
# define ADI3_REFSYS_DCDCCTL4_HIGH_EN_SEL(n) ((uint32_t)(n) << ADI3_REFSYS_DCDCCTL4_HIGH_EN_SEL_SHIFT)
|
||||
#define ADI3_REFSYS_DCDCCTL4_LOW_EN_SEL_SHIFT (3) /* Bits 3-5 */
|
||||
#define ADI3_REFSYS_DCDCCTL4_LOW_EN_SEL_MASK (7 << ADI3_REFSYS_DCDCCTL4_LOW_EN_SEL_SHIFT)
|
||||
# define ADI3_REFSYS_DCDCCTL4_LOW_EN_SEL(n) ((uint32_t)(n) << ADI3_REFSYS_DCDCCTL4_LOW_EN_SEL_SHIFT)
|
||||
#define ADI3_REFSYS_DCDCCTL4_DEADTIME_TRIM_SHIFT (6) /* Bits 6-7 */
|
||||
#define ADI3_REFSYS_DCDCCTL4_DEADTIME_TRIM_MASK (3 << ADI3_REFSYS_DCDCCTL4_DEADTIME_TRIM_SHIFT)
|
||||
# define ADI3_REFSYS_DCDCCTL4_DEADTIME_TRIM(n) ((uint32_t)(n) << ADI3_REFSYS_DCDCCTL4_DEADTIME_TRIM_SHIFT)
|
||||
|
||||
/* ADI3_REFSYS_DCDCCTL5 */
|
||||
|
||||
#define ADI3_REFSYS_DCDCCTL5_IPEAK_SHIFT (0) /* Bits 0-2 */
|
||||
#define ADI3_REFSYS_DCDCCTL5_IPEAK_MASK (7 << ADI3_REFSYS_DCDCCTL5_IPEAK_SHIFT)
|
||||
# define ADI3_REFSYS_DCDCCTL5_IPEAK(n) ((uint32_t)(n) << ADI3_REFSYS_DCDCCTL5_IPEAK_SHIFT)
|
||||
#define ADI3_REFSYS_DCDCCTL5_DITHER_EN (1 << 3) /* Bit 3 */
|
||||
#define ADI3_REFSYS_DCDCCTL5_TESTP (1 << 4) /* Bit 4 */
|
||||
#define ADI3_REFSYS_DCDCCTL5_TESTN (1 << 5) /* Bit 5 */
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X0_CC13X0_ADI3_REFSYS_H */
|
||||
|
|
@ -993,7 +993,7 @@
|
|||
/* TIVA_FLASH_FSM_SECTOR1 (32-bit value) */
|
||||
/* TIVA_FLASH_FSM_SECTOR2 (32-bit value) */
|
||||
/* TIVA_FLASH_FSM_BSLE0 (32-bit value) */
|
||||
/* TIVA_FLASH_FSM_BSLE1 *(32-bit value) /
|
||||
/* TIVA_FLASH_FSM_BSLE1 (32-bit value) */
|
||||
/* TIVA_FLASH_FSM_BSLP0 (32-bit value) */
|
||||
/* TIVA_FLASH_FSM_BSLP1 (32-bit value) */
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,292 @@
|
|||
/********************************************************************************************************************
|
||||
* arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_adi3_refsys.h
|
||||
*
|
||||
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
|
||||
* Authors: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Technical content derives from a TI header file that has a compatible BSD license:
|
||||
*
|
||||
* Copyright (c) 2015-2017, Texas Instruments Incorporated
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
********************************************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X2_CC26X2_CC13X2_CC26X2_ADI3_REFSYS_H
|
||||
#define __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X2_CC26X2_CC13X2_CC26X2_ADI3_REFSYS_H
|
||||
|
||||
/********************************************************************************************************************
|
||||
* Included Files
|
||||
********************************************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
#include "hardware/tiva_memorymap.h"
|
||||
|
||||
/********************************************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
********************************************************************************************************************/
|
||||
|
||||
/* ADI3 REFSYS Register Offsets *************************************************************************************/
|
||||
|
||||
#define TIVA_ADI3_REFSYS_ATESTCTL1_OFFSET 0x0001
|
||||
#define TIVA_ADI3_REFSYS_REFSYSCTL0_OFFSET 0x0002
|
||||
#define TIVA_ADI3_REFSYS_REFSYSCTL1_OFFSET 0x0003
|
||||
#define TIVA_ADI3_REFSYS_REFSYSCTL2_OFFSET 0x0004
|
||||
#define TIVA_ADI3_REFSYS_REFSYSCTL3_OFFSET 0x0005
|
||||
#define TIVA_ADI3_REFSYS_DCDCCTL0_OFFSET 0x0006 /* DCDC Control 0 */
|
||||
#define TIVA_ADI3_REFSYS_DCDCCTL1_OFFSET 0x0007 /* DCDC Control 1 */
|
||||
#define TIVA_ADI3_REFSYS_DCDCCTL2_OFFSET 0x0008 /* DCDC Control 2 */
|
||||
#define TIVA_ADI3_REFSYS_DCDCCTL3_OFFSET 0x0009 /* DCDC Control 3 */
|
||||
#define TIVA_ADI3_REFSYS_DCDCCTL4_OFFSET 0x000a
|
||||
#define TIVA_ADI3_REFSYS_DCDCCTL5_OFFSET 0x000b
|
||||
#define TIVA_ADI3_REFSYS_AUX_DEBUG_OFFSET 0x000c /* RECHARGE_CONTROL_1 */
|
||||
#define TIVA_ADI3_REFSYS_CTL_RECHARGE_CMP0_OFFSET 0x000d /* Recharge Comparator Control Byte 0 */
|
||||
#define TIVA_ADI3_REFSYS_CTL_RECHARGE_CMP1_OFFSET 0x000e /* Recharge Comparator Control Byte 1 */
|
||||
|
||||
/* ADI3 REFSYS Register Addresses ***********************************************************************************/
|
||||
|
||||
#define TIVA_ADI3_REFSYS_ATESTCTL1 (TIVA_ADI3_BASE + TIVA_ADI3_REFSYS_ATESTCTL1_OFFSET)
|
||||
#define TIVA_ADI3_REFSYS_REFSYSCTL0 (TIVA_ADI3_BASE + TIVA_ADI3_REFSYS_REFSYSCTL0_OFFSET)
|
||||
#define TIVA_ADI3_REFSYS_REFSYSCTL1 (TIVA_ADI3_BASE + TIVA_ADI3_REFSYS_REFSYSCTL1_OFFSET)
|
||||
#define TIVA_ADI3_REFSYS_REFSYSCTL2 (TIVA_ADI3_BASE + TIVA_ADI3_REFSYS_REFSYSCTL2_OFFSET)
|
||||
#define TIVA_ADI3_REFSYS_REFSYSCTL3 (TIVA_ADI3_BASE + TIVA_ADI3_REFSYS_REFSYSCTL3_OFFSET)
|
||||
#define TIVA_ADI3_REFSYS_DCDCCTL0 (TIVA_ADI3_BASE + TIVA_ADI3_REFSYS_DCDCCTL0_OFFSET)
|
||||
#define TIVA_ADI3_REFSYS_DCDCCTL1 (TIVA_ADI3_BASE + TIVA_ADI3_REFSYS_DCDCCTL1_OFFSET)
|
||||
#define TIVA_ADI3_REFSYS_DCDCCTL2 (TIVA_ADI3_BASE + TIVA_ADI3_REFSYS_DCDCCTL2_OFFSET)
|
||||
#define TIVA_ADI3_REFSYS_DCDCCTL3 (TIVA_ADI3_BASE + TIVA_ADI3_REFSYS_DCDCCTL3_OFFSET)
|
||||
#define TIVA_ADI3_REFSYS_DCDCCTL4 (TIVA_ADI3_BASE + TIVA_ADI3_REFSYS_DCDCCTL4_OFFSET)
|
||||
#define TIVA_ADI3_REFSYS_DCDCCTL5 (TIVA_ADI3_BASE + TIVA_ADI3_REFSYS_DCDCCTL5_OFFSET)
|
||||
#define TIVA_ADI3_REFSYS_AUX_DEBUG (TIVA_ADI3_BASE + TIVA_ADI3_REFSYS_AUX_DEBUG_OFFSET)
|
||||
#define TIVA_ADI3_REFSYS_CTL_RECHARGE_CMP0 (TIVA_ADI3_BASE + TIVA_ADI3_REFSYS_CTL_RECHARGE_CMP0_OFFSET)
|
||||
#define TIVA_ADI3_REFSYS_CTL_RECHARGE_CMP1 (TIVA_ADI3_BASE + TIVA_ADI3_REFSYS_CTL_RECHARGE_CMP1_OFFSET)
|
||||
|
||||
/* ADI3 REFSYS Bitfield Definitions *********************************************************************************/
|
||||
|
||||
/* ADI3_REFSYS_ATESTCTL1 */
|
||||
|
||||
#define ADI3_REFSYS_ATESTCTL1_ATEST1_CTL_SHIFT (0) /* Bits 0-2 */
|
||||
#define ADI3_REFSYS_ATESTCTL1_ATEST1_CTL_MASK (7 << ADI3_REFSYS_ATESTCTL1_ATEST1_CTL_SHIFT)
|
||||
# define ADI3_REFSYS_ATESTCTL1_ATEST1_CTL(n) ((uint32_t)(n) << ADI3_REFSYS_ATESTCTL1_ATEST1_CTL_SHIFT)
|
||||
# define ADI3_REFSYS_ATESTCTL1_ATEST1_CTL_NC (0 << ADI3_REFSYS_ATESTCTL1_ATEST1_CTL_SHIFT)
|
||||
# define ADI3_REFSYS_ATESTCTL1_ATEST1_CTL_VREAD_DIV2_A1 (1 << ADI3_REFSYS_ATESTCTL1_ATEST1_CTL_SHIFT)
|
||||
# define ADI3_REFSYS_ATESTCTL1_ATEST1_CTL_VPP_DIV5_A1 (2 << ADI3_REFSYS_ATESTCTL1_ATEST1_CTL_SHIFT)
|
||||
# define ADI3_REFSYS_ATESTCTL1_ATEST1_CTL_VREFM_A1 (4 << ADI3_REFSYS_ATESTCTL1_ATEST1_CTL_SHIFT)
|
||||
#define ADI3_REFSYS_ATESTCTL1_ATEST0_CTL_SHIFT (3) /* Bits 3-4 */
|
||||
#define ADI3_REFSYS_ATESTCTL1_ATEST0_CTL_MASK (3 << ADI3_REFSYS_ATESTCTL1_ATEST0_CTL_SHIFT)
|
||||
# define ADI3_REFSYS_ATESTCTL1_ATEST0_CTL(n) ((uint32_t)(n) << ADI3_REFSYS_ATESTCTL1_ATEST0_CTL_SHIFT)
|
||||
# define ADI3_REFSYS_ATESTCTL1_ATEST0_CTL_NC (0 << ADI3_REFSYS_ATESTCTL1_ATEST0_CTL_SHIFT))
|
||||
# define ADI3_REFSYS_ATESTCTL1_ATEST0_CTL_IREF_A0 (1 << ADI3_REFSYS_ATESTCTL1_ATEST0_CTL_SHIFT))
|
||||
# define ADI3_REFSYS_ATESTCTL1_ATEST0_CTL_ICELL_A0 (2 << ADI3_REFSYS_ATESTCTL1_ATEST0_CTL_SHIFT))
|
||||
|
||||
/* ADI3_REFSYS_REFSYSCTL0 */
|
||||
|
||||
#define ADI3_REFSYS_REFSYSCTL0_TESTCTL_SHIFT (0) /* Bits 0-7 */
|
||||
#define ADI3_REFSYS_REFSYSCTL0_TESTCTL_MASK (0xff << ADI3_REFSYS_REFSYSCTL0_TESTCTL_SHIFT)
|
||||
# define ADI3_REFSYS_REFSYSCTL0_TESTCTL(n) ((uint32_t)(n) << ADI3_REFSYS_REFSYSCTL0_TESTCTL_SHIFT)
|
||||
# define ADI3_REFSYS_REFSYSCTL0_TESTCTL_NC (0x00 << ADI3_REFSYS_REFSYSCTL0_TESTCTL_SHIFT)
|
||||
# define ADI3_REFSYS_REFSYSCTL0_TESTCTL_IPTAT2U (0x01 << ADI3_REFSYS_REFSYSCTL0_TESTCTL_SHIFT)
|
||||
# define ADI3_REFSYS_REFSYSCTL0_TESTCTL_IVREF4U (0x02 << ADI3_REFSYS_REFSYSCTL0_TESTCTL_SHIFT)
|
||||
# define ADI3_REFSYS_REFSYSCTL0_TESTCTL_IREF4U (0x04 << ADI3_REFSYS_REFSYSCTL0_TESTCTL_SHIFT)
|
||||
# define ADI3_REFSYS_REFSYSCTL0_TESTCTL_VBG (0x08 << ADI3_REFSYS_REFSYSCTL0_TESTCTL_SHIFT)
|
||||
# define ADI3_REFSYS_REFSYSCTL0_TESTCTL_VBGUNBUFF (0x10 << ADI3_REFSYS_REFSYSCTL0_TESTCTL_SHIFT)
|
||||
# define ADI3_REFSYS_REFSYSCTL0_TESTCTL_VREF0P8V (0x20 << ADI3_REFSYS_REFSYSCTL0_TESTCTL_SHIFT)
|
||||
# define ADI3_REFSYS_REFSYSCTL0_TESTCTL_VTEMP (0x40 << ADI3_REFSYS_REFSYSCTL0_TESTCTL_SHIFT)
|
||||
# define ADI3_REFSYS_REFSYSCTL0_TESTCTL_BMCOMPOUT (0x80 << ADI3_REFSYS_REFSYSCTL0_TESTCTL_SHIFT)
|
||||
|
||||
/* ADI3_REFSYS_REFSYSCTL1 */
|
||||
|
||||
#define ADI3_REFSYS_REFSYSCTL1_TESTCTL_SHIFT (0) /* Bits 0-1 */
|
||||
#define ADI3_REFSYS_REFSYSCTL1_TESTCTL_MASK (3 << ADI3_REFSYS_REFSYSCTL1_TESTCTL_SHIFT)
|
||||
# define ADI3_REFSYS_REFSYSCTL1_TESTCTL(n) ((uint32_t)(n) << ADI3_REFSYS_REFSYSCTL1_TESTCTL_SHIFT)
|
||||
# define ADI3_REFSYS_REFSYSCTL1_TESTCTL_NC (0 << ADI3_REFSYS_REFSYSCTL1_TESTCTL_SHIFT)
|
||||
# define ADI3_REFSYS_REFSYSCTL1_TESTCTL_BMCOMPIN (1 << ADI3_REFSYS_REFSYSCTL1_TESTCTL_SHIFT)
|
||||
# define ADI3_REFSYS_REFSYSCTL1_TESTCTL_IPTAT1U (2 << ADI3_REFSYS_REFSYSCTL1_TESTCTL_SHIFT)
|
||||
#define ADI3_REFSYS_REFSYSCTL1_BATMON_COMP_TEST_EN (1 << 2) /* Bit 2 */
|
||||
#define ADI3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_SHIFT (3) /* Bits 3-7 */
|
||||
#define ADI3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_MASK (31 << ADI3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_SHIFT)
|
||||
# define ADI3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD(n) ((uint32_t)(n) << ADI3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_SHIFT)
|
||||
# define ADI3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_4 (0 << ADI3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_SHIFT)
|
||||
# define ADI3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_5 (1 << ADI3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_SHIFT)
|
||||
# define ADI3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_6 (2 << ADI3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_SHIFT)
|
||||
# define ADI3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_7 (3 << ADI3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_SHIFT)
|
||||
# define ADI3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_0 (4 << ADI3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_SHIFT)
|
||||
# define ADI3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_1 (5 << ADI3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_SHIFT)
|
||||
# define ADI3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_2 (6 << ADI3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_SHIFT)
|
||||
# define ADI3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_3 (7 << ADI3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_SHIFT)
|
||||
# define ADI3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_12 (8 << ADI3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_SHIFT)
|
||||
# define ADI3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_13 (9 << ADI3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_SHIFT)
|
||||
# define ADI3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_14 (10 << ADI3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_SHIFT)
|
||||
# define ADI3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_15 (11 << ADI3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_SHIFT)
|
||||
# define ADI3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_8 (12 << ADI3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_SHIFT)
|
||||
# define ADI3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_9 (13 << ADI3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_SHIFT)
|
||||
# define ADI3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_10 (14 << ADI3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_SHIFT)
|
||||
# define ADI3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_11 (15 << ADI3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_SHIFT)
|
||||
# define ADI3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_20 (16 << ADI3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_SHIFT)
|
||||
# define ADI3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_21 (17 << ADI3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_SHIFT)
|
||||
# define ADI3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_22 (18 << ADI3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_SHIFT)
|
||||
# define ADI3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_23 (19 << ADI3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_SHIFT)
|
||||
# define ADI3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_16 (20 << ADI3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_SHIFT)
|
||||
# define ADI3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_17 (21 << ADI3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_SHIFT)
|
||||
# define ADI3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_18 (22 << ADI3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_SHIFT)
|
||||
# define ADI3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_19 (23 << ADI3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_SHIFT)
|
||||
# define ADI3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_28 (24 << ADI3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_SHIFT)
|
||||
# define ADI3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_29 (25 << ADI3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_SHIFT)
|
||||
# define ADI3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_30 (26 << ADI3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_SHIFT)
|
||||
# define ADI3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_31 (27 << ADI3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_SHIFT)
|
||||
# define ADI3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_24 (28 << ADI3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_SHIFT)
|
||||
# define ADI3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_25 (29 << ADI3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_SHIFT)
|
||||
# define ADI3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_26 (30 << ADI3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_SHIFT)
|
||||
# define ADI3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_27 (31 << ADI3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_SHIFT)
|
||||
|
||||
/* ADI3_REFSYS_REFSYSCTL2 */
|
||||
|
||||
#define ADI3_REFSYS_REFSYSCTL2_TRIM_TSENSE_SHIFT (0) /* Bits 0-1 */
|
||||
#define ADI3_REFSYS_REFSYSCTL2_TRIM_TSENSE_MASK (3 << ADI3_REFSYS_REFSYSCTL2_TRIM_TSENSE_SHIFT)
|
||||
# define ADI3_REFSYS_REFSYSCTL2_TRIM_TSENSE(n) ((uint32_t)(n) << ADI3_REFSYS_REFSYSCTL2_TRIM_TSENSE_SHIFT)
|
||||
#define ADI3_REFSYS_REFSYSCTL2_BOD_EXTERNAL_REG_MODE (1 << 3) /* Bit 3 */
|
||||
#define ADI3_REFSYS_REFSYSCTL2_TRIM_VREF_SHIFT (4) /* Bits 4-7 */
|
||||
#define ADI3_REFSYS_REFSYSCTL2_TRIM_VREF_MASK (15 << ADI3_REFSYS_REFSYSCTL2_TRIM_VREF_SHIFT)
|
||||
# define ADI3_REFSYS_REFSYSCTL2_TRIM_VREF(n) ((uint32_t)(n) << ADI3_REFSYS_REFSYSCTL2_TRIM_VREF_SHIFT)
|
||||
|
||||
/* ADI3_REFSYS_REFSYSCTL3 */
|
||||
|
||||
#define ADI3_REFSYS_REFSYSCTL3_TRIM_VBG_SHIFT (0) /* Bits 0-5 */
|
||||
#define ADI3_REFSYS_REFSYSCTL3_TRIM_VBG_MASK (0x3f << ADI3_REFSYS_REFSYSCTL3_TRIM_VBG_SHIFT)
|
||||
# define ADI3_REFSYS_REFSYSCTL3_TRIM_VBG(n) ((uint32_t)(n) << ADI3_REFSYS_REFSYSCTL3_TRIM_VBG_SHIFT)
|
||||
#define ADI3_REFSYS_REFSYSCTL3_VTEMP_EN (1 << 6) /* Bit 6 */
|
||||
#define ADI3_REFSYS_REFSYSCTL3_BOD_BG_TRIM_EN (1 << 7) /* Bit 7 */
|
||||
|
||||
/* ADI3_REFSYS_DCDCCTL0 */
|
||||
|
||||
#define ADI3_REFSYS_DCDCCTL0_VDDR_TRIM_SHIFT (0) /* Bits 0-4: Set the VDDR voltage */
|
||||
/* Proprietary encoding */
|
||||
#define ADI3_REFSYS_DCDCCTL0_VDDR_TRIM_MASK (31 << ADI3_REFSYS_DCDCCTL0_VDDR_TRIM_SHIFT)
|
||||
# define ADI3_REFSYS_DCDCCTL0_VDDR_TRIM(n) ((uint32_t)(n) << ADI3_REFSYS_DCDCCTL0_VDDR_TRIM_SHIFT)
|
||||
# define ADI3_REFSYS_DCDCCTL0_VDDR_TRIM_DEFAULT (0 << ADI3_REFSYS_DCDCCTL0_VDDR_TRIM_SHIFT) /* Default, about 1.63V */
|
||||
# define ADI3_REFSYS_DCDCCTL0_VDDR_TRIM_TYPICAL (5 << ADI3_REFSYS_DCDCCTL0_VDDR_TRIM_SHIFT) /* Typical voltage after trim voltage 1.71V */
|
||||
# define ADI3_REFSYS_DCDCCTL0_VDDR_TRIM_MAX (21 << ADI3_REFSYS_DCDCCTL0_VDDR_TRIM_SHIFT) /* Max voltage 1.96V */
|
||||
# define ADI3_REFS */YS_DCDCCTL0_VDDR_TRIM_MIN (22 << ADI3_REFSYS_DCDCCTL0_VDDR_TRIM_SHIFT) /* Min voltage 1.47V
|
||||
#define ADI3_REFSYS_DCDCCTL0_GLDO_ISRC_SHIFT (5) /* Bits 5-7: Set charge and re-charge current level */
|
||||
/* 2's complement encoding */
|
||||
#define ADI3_REFSYS_DCDCCTL0_GLDO_ISRC_MASK (7 << ADI3_REFSYS_DCDCCTL0_GLDO_ISRC_SHIFT)
|
||||
# define ADI3_REFSYS_DCDCCTL0_GLDO_ISRC(n) ((uint32_t)(n) << ADI3_REFSYS_DCDCCTL0_GLDO_ISRC_SHIFT)
|
||||
# define ADI3_REFSYS_DCDCCTL0_GLDO_ISRC_DEFAULT (0 << ADI3_REFSYS_DCDCCTL0_GLDO_ISRC_SHIFT) /* Default 11mA */
|
||||
# define ADI3_REFSYS_DCDCCTL0_GLDO_ISRC_MAX (3 << ADI3_REFSYS_DCDCCTL0_GLDO_ISRC_SHIFT) /* Max 15mA */
|
||||
# define ADI3_REFSYS_DCDCCTL0_GLDO_ISRC_MIN (4 << ADI3_REFSYS_DCDCCTL0_GLDO_ISRC_SHIFT) /* Max 5mA */
|
||||
|
||||
/* ADI3_REFSYS_DCDCCTL1 */
|
||||
|
||||
#define ADI3_REFSYS_DCDCCTL1_VDDR_TRIM_SLEEP_SHIFT (0) /* Bits 0-4: Set the min VDDR voltage threshold during sleep mode */
|
||||
/* Proprietary encoding */
|
||||
#define ADI3_REFSYS_DCDCCTL1_VDDR_TRIM_SLEEP_MASK (31 << ADI3_REFSYS_DCDCCTL1_VDDR_TRIM_SLEEP_SHIFT)
|
||||
# define ADI3_REFSYS_DCDCCTL1_VDDR_TRIM_SLEEP(n) ((uint32_t)(n) << ADI3_REFSYS_DCDCCTL1_VDDR_TRIM_SLEEP_SHIFT)
|
||||
# define ADI3_REFSYS_DCDCCTL1_VDDR_TRIM_SLEEP_DEFAULT (nn << ADI3_REFSYS_DCDCCTL1_VDDR_TRIM_SLEEP_SHIFT) /* Default, about 1.63V */
|
||||
# define ADI3_REFSYS_DCDCCTL1_VDDR_TRIM_SLEEP_TYPICAL (nn << ADI3_REFSYS_DCDCCTL1_VDDR_TRIM_SLEEP_SHIFT) /* Typical voltage after trim voltage 1.52V */
|
||||
# define ADI3_REFSYS_DCDCCTL1_VDDR_TRIM_SLEEP_MAX (nn << ADI3_REFSYS_DCDCCTL1_VDDR_TRIM_SLEEP_SHIFT) /* Max voltage 1.96V */
|
||||
# define ADI3_REFSYS_DCDCCTL1_VDDR_TRIM_SLEEP_MIN (nn << ADI3_REFSYS_DCDCCTL1_VDDR_TRIM_SLEEP_SHIFT) /* Min voltage 1.47V */
|
||||
#define ADI3_REFSYS_DCDCCTL1_VDDR_OK_HYST (1 << 5) /* Bit 5: Increase the hysteresis for when VDDR is considered ok */
|
||||
/* 0: Hysteresis = 60mV; 1: Hysteresis = 70mV */
|
||||
#define ADI3_REFSYS_DCDCCTL1_IPTAT_TRIM_SHIFT (6) /* Bits 6-7: Trim GLDO bias current */
|
||||
/* Proprietary encoding */
|
||||
#define ADI3_REFSYS_DCDCCTL1_IPTAT_TRIM_MASK (3 << ADI3_REFSYS_DCDCCTL1_IPTAT_TRIM_SHIFT)
|
||||
# define ADI3_REFSYS_DCDCCTL1_IPTAT_TRIM(n) ((uint32_t)(n) << ADI3_REFSYS_DCDCCTL1_IPTAT_TRIM_SHIFT)
|
||||
# define ADI3_REFSYS_DCDCCTL1_IPTAT_TRIM_DEFAULT (0 << ADI3_REFSYS_DCDCCTL1_IPTAT_TRIM_SHIFT) /* Default */
|
||||
# define ADI3_REFSYS_DCDCCTL1_IPTAT_TRIM_INC1p3 (1 << ADI3_REFSYS_DCDCCTL1_IPTAT_TRIM_SHIFT) /* Increase GLDO bias by 1.3x */
|
||||
# define ADI3_REFSYS_DCDCCTL1_IPTAT_TRIM_INC1p6 (2 << ADI3_REFSYS_DCDCCTL1_IPTAT_TRIM_SHIFT) /* Increase GLDO bias by 1.6x */
|
||||
# define ADI3_REFSYS_DCDCCTL1_IPTAT_TRIM_DEC0p7 (3 << ADI3_REFSYS_DCDCCTL1_IPTAT_TRIM_SHIFT) /* Decrease GLDO bias by 0.7x */
|
||||
|
||||
/* ADI3_REFSYS_DCDCCTL2 */
|
||||
|
||||
#define ADI3_REFSYS_DCDCCTL2_TESTSEL_SHIFT (0) /* Bits 0-3: Select signal for test bus, one hot */
|
||||
#define ADI3_REFSYS_DCDCCTL2_TESTSEL_MASK (15 << ADI3_REFSYS_DCDCCTL2_TESTSEL_SHIFT)
|
||||
# define ADI3_REFSYS_DCDCCTL2_TESTSEL(n) ((uint32_t)(n) << ADI3_REFSYS_DCDCCTL2_TESTSEL_SHIFT)
|
||||
# define ADI3_REFSYS_DCDCCTL2_TESTSEL_NC (0 << ADI3_REFSYS_DCDCCTL2_TESTSEL_SHIFT) /* No signal connected to test bus */
|
||||
# define ADI3_REFSYS_DCDCCTL2_TESTSEL_ERRAMP_OUT (1 << ADI3_REFSYS_DCDCCTL2_TESTSEL_SHIFT) /* Error amp output voltage connected to test bus */
|
||||
# define ADI3_REFSYS_DCDCCTL2_TESTSEL_PASSGATE (2 << ADI3_REFSYS_DCDCCTL2_TESTSEL_SHIFT) /* Pass transistor gate voltage connected to test bus */
|
||||
# define ADI3_REFSYS_DCDCCTL2_TESTSEL_IB1U (4 << ADI3_REFSYS_DCDCCTL2_TESTSEL_SHIFT) /* 1uA bias current connected to test bus */
|
||||
# define ADI3_REFSYS_DCDCCTL2_TESTSEL_VDDROK (8 << ADI3_REFSYS_DCDCCTL2_TESTSEL_SHIFT) /* VDDR_OK connected to test bus */
|
||||
#define ADI3_REFSYS_DCDCCTL2_BIAS_DIS (1 << 4) /* Bit 4: Disable dummy bias current */
|
||||
#define ADI3_REFSYS_DCDCCTL2_TEST_VDDR (1 << 5) /* Bit 5: Connect VDDR to ATEST bus */
|
||||
#define ADI3_REFSYS_DCDCCTL2_TURNON_EA_SW (1 << 6) /* Bit 6: Turns on GLDO error amp switch */
|
||||
|
||||
/* ADI3_REFSYS_DCDCCTL3 */
|
||||
|
||||
/* ADI3_REFSYS_DCDCCTL4 */
|
||||
|
||||
#define ADI3_REFSYS_DCDCCTL4_HIGH_EN_SEL_SHIFT (0) /* Bits 0-2 */
|
||||
#define ADI3_REFSYS_DCDCCTL4_HIGH_EN_SEL_MASK (7 << ADI3_REFSYS_DCDCCTL4_HIGH_EN_SEL_SHIFT)
|
||||
# define ADI3_REFSYS_DCDCCTL4_HIGH_EN_SEL(n) ((uint32_t)(n) << ADI3_REFSYS_DCDCCTL4_HIGH_EN_SEL_SHIFT)
|
||||
#define ADI3_REFSYS_DCDCCTL4_LOW_EN_SEL_SHIFT (3) /* Bits 3-5 */
|
||||
#define ADI3_REFSYS_DCDCCTL4_LOW_EN_SEL_MASK (7 << ADI3_REFSYS_DCDCCTL4_LOW_EN_SEL_SHIFT)
|
||||
# define ADI3_REFSYS_DCDCCTL4_LOW_EN_SEL(n) ((uint32_t)(n) << ADI3_REFSYS_DCDCCTL4_LOW_EN_SEL_SHIFT)
|
||||
#define ADI3_REFSYS_DCDCCTL4_DEADTIME_TRIM_SHIFT (6) /* Bits 6-7 */
|
||||
#define ADI3_REFSYS_DCDCCTL4_DEADTIME_TRIM_MASK (3 << ADI3_REFSYS_DCDCCTL4_DEADTIME_TRIM_SHIFT)
|
||||
# define ADI3_REFSYS_DCDCCTL4_DEADTIME_TRIM(n) ((uint32_t)(n) << ADI3_REFSYS_DCDCCTL4_DEADTIME_TRIM_SHIFT)
|
||||
|
||||
/* ADI3_REFSYS_DCDCCTL5 */
|
||||
|
||||
#define ADI3_REFSYS_DCDCCTL5_IPEAK_SHIFT (0) /* Bits 0-2 */
|
||||
#define ADI3_REFSYS_DCDCCTL5_IPEAK_MASK (7 << ADI3_REFSYS_DCDCCTL5_IPEAK_SHIFT)
|
||||
# define ADI3_REFSYS_DCDCCTL5_IPEAK(n) ((uint32_t)(n) << ADI3_REFSYS_DCDCCTL5_IPEAK_SHIFT)
|
||||
#define ADI3_REFSYS_DCDCCTL5_DITHER_EN (1 << 3) /* Bit 3 */
|
||||
#define ADI3_REFSYS_DCDCCTL5_TESTP (1 << 4) /* Bit 4 */
|
||||
#define ADI3_REFSYS_DCDCCTL5_TESTN (1 << 5) /* Bit 5 */
|
||||
|
||||
/* ADI_3_REFSYS_AUX_DEBUG */
|
||||
|
||||
#define ADI3_REFSYS_AUX_DEBUG_DAC_DBG_EN (1 << 0) /* Bit 0: Enable Debug Mode */
|
||||
#define ADI3_REFSYS_AUX_DEBUG_DAC_DBG_SAMPLE (1 << 1) /* Bit 1: S-H Cap sample signal */
|
||||
#define ADI3_REFSYS_AUX_DEBUG_DAC_DBG_CAP_SAMPLE (1 << 2) /* Bit 2: Cap-array sample signal */
|
||||
#define ADI3_REFSYS_AUX_DEBUG_DAC_DBG_PRECHARGE (1 << 3) /* Bit 3: PRE-CHARGE signal */
|
||||
#define ADI3_REFSYS_AUX_DEBUG_DAC_DBG_HOLD (1 << 4) /* Bit 4: S-H Cap hold signal */
|
||||
#define ADI3_REFSYS_AUX_DEBUG_DAC_DBG_OFFSET_COMP (1 << 5) /* Bit 5: Offset compensation signal */
|
||||
#define ADI3_REFSYS_AUX_DEBUG_LPM_BIAS_BACKUP_EN (1 << 6) /* Bit 6: Activate the backup circuit */
|
||||
|
||||
/* ADI3_REFSYS_CTL_RECHARGE_CMP0 */
|
||||
|
||||
#define ADI3_REFSYS_CTL_RECHARGE_CMP0_TRIM_RECHARGE_COMP_REFLEVEL_SHIFT (0) /* Bits 0-3: Trim ref level of recharge */
|
||||
#define ADI3_REFSYS_CTL_RECHARGE_CMP0_TRIM_RECHARGE_COMP_REFLEVEL_MASK (15 << ADI3_REFSYS_CTL_RECHARGE_CMP0_TRIM_RECHARGE_COMP_REFLEVEL_SHIFT)
|
||||
# define ADI3_REFSYS_CTL_RECHARGE_CMP0_TRIM_RECHARGE_COMP_REFLEVEL(n) ((uint32_t)(n) << ADI3_REFSYS_CTL_RECHARGE_CMP0_TRIM_RECHARGE_COMP_REFLEVEL_SHIFT)
|
||||
# define ADI3_REFSYS_CTL_RECHARGE_CMP0_TRIM_RECHARGE_COMP_REFLEVEL_90PCT (15 << ADI3_REFSYS_CTL_RECHARGE_CMP0_TRIM_RECHARGE_COMP_REFLEVEL_SHIFT)
|
||||
# define ADI3_REFSYS_CTL_RECHARGE_CMP0_TRIM_RECHARGE_COMP_REFLEVEL_100PCT (0 << ADI3_REFSYS_CTL_RECHARGE_CMP0_TRIM_RECHARGE_COMP_REFLEVEL_SHIFT)
|
||||
#define ADI3_REFSYS_CTL_RECHARGE_CMP0_COMP_CLK_DISABLE (1 << 4) /* Bit 4: Enable 32 kHz SCLK_LF to recharge comparator */
|
||||
|
||||
/* ADI3_REFSYS_CTL_RECHARGE_CMP1 */
|
||||
|
||||
#define ADI3_REFSYS_CTL_RECHARGE_CMP1_TRIM_RECHARGE_COMP_OFFSET_SHIFT (0) /* Bis 0-4: Trim offset of Recharge comparator */
|
||||
#define ADI3_REFSYS_CTL_RECHARGE_CMP1_TRIM_RECHARGE_COMP_OFFSET_MASK (31 << ADI3_REFSYS_CTL_RECHARGE_CMP1_TRIM_RECHARGE_COMP_OFFSET_SHIFT)
|
||||
# define ADI3_REFSYS_CTL_RECHARGE_CMP1_TRIM_RECHARGE_COMP_OFFSET(n) ((uint32_t)(n) << ADI3_REFSYS_CTL_RECHARGE_CMP1_TRIM_RECHARGE_COMP_OFFSET_SHIFT)
|
||||
#define ADI3_REFSYS_CTL_RECHARGE_CMP1_TRIM_RECHARGE_COMP_OFFSET_MAXIN (0 << ADI3_REFSYS_CTL_RECHARGE_CMP1_TRIM_RECHARGE_COMP_OFFSET_SHIFT) /* Maximum degeneration on input side (VDDR side) */
|
||||
#define ADI3_REFSYS_CTL_RECHARGE_CMP1_TRIM_RECHARGE_COMP_OFFSET_MAXREF (31 << ADI3_REFSYS_CTL_RECHARGE_CMP1_TRIM_RECHARGE_COMP_OFFSET_SHIFT) /* Maximum degeneration on reference side from cap divider */
|
||||
#define ADI3_REFSYS_CTL_RECHARGE_CMP1_TRIM_RECHARGE_COMP_OFFSET_NOMINAL (16 << ADI3_REFSYS_CTL_RECHARGE_CMP1_TRIM_RECHARGE_COMP_OFFSET_SHIFT) /* Nominal code */
|
||||
#define ADI3_REFSYS_CTL_RECHARGE_CMP1_FORCE_SAMPLE_VDDR (1 << 5) /* Bit 5: Force Sample of VDDR on cap divider */
|
||||
#define ADI3_REFSYS_CTL_RECHARGE_CMP1_RECHARGE_BLOCK_ATEST_EN (1 << 6) /* Bit 6: Enable test inputs/outputs to recharge comparator */
|
||||
#define ADI3_REFSYS_CTL_RECHARGE_CMP1_RECHARGE_BLOCK_VTRIG_EN (1 << 7) /* Bit 7: Enable ATEST input to VDDR input of recharge comparator */
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X2_CC26X2_CC13X2_CC26X2_ADI3_REFSYS_H */
|
||||
|
|
@ -995,7 +995,7 @@
|
|||
/* TIVA_FLASH_FSM_SECTOR1 (32-bit value) */
|
||||
/* TIVA_FLASH_FSM_SECTOR2 (32-bit value) */
|
||||
/* TIVA_FLASH_FSM_BSLE0 (32-bit value) */
|
||||
/* TIVA_FLASH_FSM_BSLE1 *(32-bit value) /
|
||||
/* TIVA_FLASH_FSM_BSLE1 (32-bit value) */
|
||||
/* TIVA_FLASH_FSM_BSLP0 (32-bit value) */
|
||||
/* TIVA_FLASH_FSM_BSLP1 (32-bit value) */
|
||||
|
||||
|
|
|
|||
73
arch/arm/src/tiva/hardware/tiva_adi3_refsys.h
Normal file
73
arch/arm/src/tiva/hardware/tiva_adi3_refsys.h
Normal file
|
|
@ -0,0 +1,73 @@
|
|||
/************************************************************************************
|
||||
* arch/arm/src/tiva/hardware/tiva_adi3_refsys.h
|
||||
*
|
||||
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_TIVA_HARDWARE_TIVA_ADI3_REFSYS_H
|
||||
#define __ARCH_ARM_SRC_TIVA_HARDWARE_TIVA_ADI3_REFSYS_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
/* Include the pin mapping file for the specific Tiva/Stellaris/SimpleLink chip */
|
||||
|
||||
#if defined(CONFIG_ARCH_CHIP_LM) || defined(CONFIG_ARCH_CHIP_TM4C)
|
||||
/* These architectures do not support the ADI3 REFSYS block */
|
||||
#elif defined(CONFIG_ARCH_CHIP_CC13X0)
|
||||
# include "hardware/cc13x0/cc13x0_adi3_refsys.h"
|
||||
#elif defined(CONFIG_ARCH_CHIP_CC13X2)
|
||||
# include "hardware/cc13x2_cc26x2/cc13x2_cc26x2_adi3_refsys.h"
|
||||
#else
|
||||
# error "Unsupported Tiva/Stellaris/SimpleLink ADI3 REFSYS"
|
||||
#endif
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Types
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Data
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Function Prototypes
|
||||
************************************************************************************/
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_TIVA_HARDWARE_TIVA_ADI3_REFSYS_H */
|
||||
|
|
@ -708,7 +708,8 @@ static int sixlowpan_dispatch(FAR struct radio_driver_s *radio)
|
|||
* must apply to all of the frames in the list.
|
||||
*
|
||||
* Returned Value:
|
||||
* Ok is returned on success; Othewise a negated errno value is returned.
|
||||
* Zero (OK) is returned if the the frame was consumed; Othewise a negated
|
||||
* errno value is returned.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
|
|
|
|||
Loading…
Reference in a new issue