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Add ENCX24J600 Ethernet driver and support for the ENCX24J600 with the Olimex STM32 P107 board. From Max Holtberg

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This commit is contained in:
Gregory Nutt 2013-08-25 11:21:54 -06:00
parent bea6894bd7
commit 70be601ea2
11 changed files with 3509 additions and 8 deletions
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7
ChangeLog
View file

@ -5445,5 +5445,8 @@
From Max Holtzberg (2013-8-25).
* arch/arm/src/sama5/sam_ohci.c: SAMA5 OHCI is again functional by
itself after all of the changes to integrate with EHCI. (2013-8-25).
* drivers/net/encx24j600.c/.h and include/nuttx/net/encx24j600.h:
Support the Microchip ENCX24J600 Ethernet driver from Max Holtberg
(2013-8-25).
* configs/olimex-stm32-p107: Incorporate ENCX24J600 support for the
Olimex STM32 P107 board. From Max Holtzberg (2013-8-25).

8
configs/olimex-stm32-p107/src/Makefile
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@ -37,15 +37,19 @@
CFLAGS += -I$(TOPDIR)/sched
ASRCS =
ASRCS =
AOBJS = $(ASRCS:.S=$(OBJEXT))
CSRCS = up_boot.c
CSRCS = up_boot.c up_spi.c
ifeq ($(CONFIG_CAN),y)
CSRCS += up_can.c
endif
ifeq ($(CONFIG_ENCX24J600),y)
CSRCS += up_encx24j600.c
endif
COBJS = $(CSRCS:.c=$(OBJEXT))
SRCS = $(ASRCS) $(CSRCS)

88
configs/olimex-stm32-p107/src/p107-internal.h Normal file
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@ -0,0 +1,88 @@
/******************************************************************************
* configs/olimex-stm32-p107/src/p107-internal.h
*
* Copyright (C) 2013 Max Holtzberg. All rights reserved.
* Author: Max Holtzberg <mholtzberg@uvc-ingenieure.de>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************/
#ifndef __CONFIGS_OLIMEX_STM32_P107_SRC_INTERNAL_H
#define __CONFIGS_OLIMEX_STM32_P107_SRC_INTERNAL_H
/******************************************************************************
* Included Files
******************************************************************************/
#include <nuttx/config.h>
#include <nuttx/compiler.h>
#include <stdint.h>
/******************************************************************************
* Definitions
******************************************************************************/
/* ENCX24J600
*
* --- ------ -------------- ---------------------------------------------------
* PIN NAME SIGNAL NOTES
* --- ------ -------------- ---------------------------------------------------
*
* 54 PB15 PB15-CS_UEXT ENCX24J600 #CS
* 78 PC10 PC10-SPI3-SCK ENCX24J600 SCK
* 79 PC11 PC11-SPI3-MISO ENCX24J600 MISO
* 80 PC12 PC12-SPI3-MOSI ENCX24J600 MOSI
* 95 PB8 PB8 ENCX24J600 #Interrupt
*/
#ifdef CONFIG_ENCX24J600
# define GPIO_ENCX24J600_CS (GPIO_OUTPUT|GPIO_CNF_OUTPP|GPIO_MODE_50MHz| \
GPIO_OUTPUT_SET|GPIO_PORTB|GPIO_PIN15)
# define GPIO_ENCX24J600_INTR (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT| \
GPIO_EXTI|GPIO_PORTB|GPIO_PIN8)
#endif
#ifndef __ASSEMBLY__
/************************************************************************************
* Public Functions
************************************************************************************/
/************************************************************************************
* Name: stm32_spiinitialize
*
* Description:
* Called to configure SPI chip select GPIO pins for the M3 Wildfire board.
*
************************************************************************************/
void weak_function stm32_spiinitialize(void);
#endif /* __ASSEMBLY__ */
#endif /* __CONFIGS_OLIMEX_STM32_P107_SRC_INTERNAL_H */

14
configs/olimex-stm32-p107/src/up_boot.c
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@ -39,12 +39,11 @@
************************************************************************************/
#include <nuttx/config.h>
#include <debug.h>
#include <arch/board/board.h>
#include "up_arch.h"
#include "p107-internal.h"
/************************************************************************************
* Pre-processor Definitions
@ -70,4 +69,15 @@
void stm32_boardinitialize(void)
{
/* Configure SPI chip selects if 1) SPI is not disabled, and 2) the weak function
* stm32_spiinitialize() has been brought into the link.
*/
#if defined(CONFIG_STM32_SPI3)
if (stm32_spiinitialize)
{
stm32_spiinitialize();
}
#endif
}

196
configs/olimex-stm32-p107/src/up_encx24j600.c Normal file
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@ -0,0 +1,196 @@
/****************************************************************************
* configs/olimex-stm32-p107/src/up_encx24j600.c
*
* Copyright (C) 2012 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <stdio.h>
#include <debug.h>
#include <nuttx/spi/spi.h>
#include <nuttx/net/encx24j600.h>
#include <arch/board/board.h>
#include "chip.h"
#include "up_arch.h"
#include "up_internal.h"
#include "p107-internal.h"
#ifdef CONFIG_ENCX24J600
/****************************************************************************
* Definitions
****************************************************************************/
/* Configuration ************************************************************/
/* ENCX24J600
*
* --- ------ -------------- ------------------------------------------------
* PIN NAME SIGNAL NOTES
* --- ------ -------------- ------------------------------------------------
*
* 54 PB15 PB15-CS_UEXT ENCX24J600 #CS
* 78 PC10 PC10-SPI3-SCK ENCX24J600 SCK
* 79 PC11 PC11-SPI3-MISO ENCX24J600 MISO
* 80 PC12 PC12-SPI3-MOSI ENCX24J600 MOSI
* 95 PB8 PB8 ENCX24J600 #Interrupt
*/
/* ENCX24J600 is on SPI3 */
#ifndef CONFIG_STM32_SPI3
# error "Need CONFIG_STM32_SPI3 in the configuration"
#endif
/* SPI Assumptions **********************************************************/
#define ENCX24J600_SPI_PORTNO 3 /* On SPI1 */
#define ENCX24J600_DEVNO 0 /* Only one ENCX24J600 */
/****************************************************************************
* Private Types
****************************************************************************/
struct stm32_lower_s
{
const struct enc_lower_s lower; /* Low-level MCU interface */
xcpt_t handler; /* ENCX24J600 interrupt handler */
};
/****************************************************************************
* Private Function Prototypes
****************************************************************************/
static int up_attach(FAR const struct enc_lower_s *lower, xcpt_t handler);
static void up_enable(FAR const struct enc_lower_s *lower);
static void up_disable(FAR const struct enc_lower_s *lower);
/****************************************************************************
* Private Data
****************************************************************************/
/* The ENCX24J600 normal provides interrupts to the MCU via a GPIO pin. The
* following structure provides an MCU-independent mechanixm for controlling
* the ENCX24J600 GPIO interrupt.
*/
static struct stm32_lower_s g_enclower =
{
.lower =
{
.attach = up_attach,
.enable = up_enable,
.disable = up_disable
},
.handler = NULL,
};
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Name: struct enc_lower_s methods
****************************************************************************/
static int up_attach(FAR const struct enc_lower_s *lower, xcpt_t handler)
{
FAR struct stm32_lower_s *priv = (FAR struct stm32_lower_s *)lower;
/* Just save the handler for use when the interrupt is enabled */
priv->handler = handler;
return OK;
}
static void up_enable(FAR const struct enc_lower_s *lower)
{
FAR struct stm32_lower_s *priv = (FAR struct stm32_lower_s *)lower;
DEBUGASSERT(priv->handler);
(void)stm32_gpiosetevent(GPIO_ENCX24J600_INTR, false, true, true, priv->handler);
}
static void up_disable(FAR const struct enc_lower_s *lower)
{
(void)stm32_gpiosetevent(GPIO_ENCX24J600_INTR, false, true, true, NULL);
}
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: up_netinitialize
****************************************************************************/
void up_netinitialize(void)
{
FAR struct spi_dev_s *spi;
int ret;
/* Assumptions:
* 1) ENCX24J600 pins were configured in up_spi.c early in the boot-up phase.
* 2) Clocking for the SPI1 peripheral was also provided earlier in boot-up.
*/
spi = up_spiinitialize(ENCX24J600_SPI_PORTNO);
if (!spi)
{
nlldbg("Failed to initialize SPI port %d\n", ENCX24J600_SPI_PORTNO);
return;
}
/* Bind the SPI port to the ENCX24J600 driver */
ret = enc_initialize(spi, &g_enclower.lower, ENCX24J600_DEVNO);
if (ret < 0)
{
nlldbg("Failed to bind SPI port %d ENCX24J600 device %d: %d\n",
ENCX24J600_SPI_PORTNO, ENCX24J600_DEVNO, ret);
return;
}
nllvdbg("Bound SPI port %d to ENCX24J600 device %d\n",
ENCX24J600_SPI_PORTNO, ENCX24J600_DEVNO);
}
#endif /* CONFIG_ENCX24J600 */

154
configs/olimex-stm32-p107/src/up_spi.c Normal file
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@ -0,0 +1,154 @@
/************************************************************************************
* configs/olimex-stm32-p107/src/up_spi.c
*
* Copyright (C) 2013 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <stdbool.h>
#include <debug.h>
#include <nuttx/spi/spi.h>
#include <arch/board/board.h>
#include "up_arch.h"
#include "chip.h"
#include "stm32.h"
#include "p107-internal.h"
#if defined(CONFIG_STM32_SPI3)
/************************************************************************************
* Definitions
************************************************************************************/
/* Enables debug output from this file (needs CONFIG_DEBUG too) */
#undef SPI_DEBUG /* Define to enable debug */
#undef SPI_VERBOSE /* Define to enable verbose debug */
#ifdef SPI_DEBUG
# define spidbg lldbg
# ifdef SPI_VERBOSE
# define spivdbg lldbg
# else
# define spivdbg(x...)
# endif
#else
# undef SPI_VERBOSE
# define spidbg(x...)
# define spivdbg(x...)
#endif
/************************************************************************************
* Private Functions
************************************************************************************/
/************************************************************************************
* Public Functions
************************************************************************************/
/************************************************************************************
* Name: stm32_spiinitialize
*
* Description:
* Called to configure SPI chip select GPIO pins for the Olimex stm32-p107 board.
*
************************************************************************************/
void weak_function stm32_spiinitialize(void)
{
/* NOTE: Clocking for SPI3 was already provided in stm32_rcc.c.
* Configurations of SPI pins is performed in stm32_spi.c.
* Here, we only initialize chip select pins unique to the board
* architecture.
*/
/* Configure ENCX24J600 SPI1 CS (also RESET and interrupt pins) */
#if defined(CONFIG_ENCX24J600) && defined(CONFIG_STM32_SPI3)
stm32_configgpio(GPIO_ENCX24J600_CS);
stm32_configgpio(GPIO_ENCX24J600_INTR);
#endif
}
/****************************************************************************
* Name: stm32_spi1/2/3select and stm32_spi1/2/3status
*
* Description:
* The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status must be
* provided by board-specific logic. They are implementations of the select
* and status methods of the SPI interface defined by struct spi_ops_s (see
* include/nuttx/spi/spi.h). All other methods (including up_spiinitialize())
* are provided by common STM32 logic. To use this common SPI logic on your
* board:
*
* 1. Provide logic in stm32_boardinitialize() to configure SPI chip select
* pins.
* 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() functions in your
* board-specific logic. These functions will perform chip selection and
* status operations using GPIOs in the way your board is configured.
* 3. Add a calls to up_spiinitialize() in your low level application
* initialization logic
* 4. The handle returned by up_spiinitialize() may then be used to bind the
* SPI driver to higher level logic (e.g., calling
* mmcsd_spislotinitialize(), for example, will bind the SPI driver to
* the SPI MMC/SD driver).
*
****************************************************************************/
#ifdef CONFIG_STM32_SPI3
void stm32_spi3select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected)
{
spidbg("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert");
if (devid == SPIDEV_ETHERNET)
{
/* Set the GPIO low to select and high to de-select */
stm32_gpiowrite(GPIO_ENCX24J600_CS, !selected);
}
}
uint8_t stm32_spi3status(FAR struct spi_dev_s *dev, enum spi_dev_e devid)
{
return SPI_STATUS_PRESENT;
}
#endif
#endif /* CONFIG_STM32_SPI3 */

60
drivers/net/Kconfig
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@ -16,7 +16,7 @@ config NET_CS89x0
depends on EXPERIMENTAL
---help---
Under construction -- do not use
config ENC28J60
bool "Microchip ENC28J60 support"
default n
@ -79,6 +79,62 @@ config ENC28J60_REGDEBUG
endif
config ENCX24J600
bool "Microchip ENCX24J600 support"
default n
select SPI
---help---
References:
ENC424J600/624J600 Data Sheet Stand-Alone 10/100 Ethernet Controller
with SPI or Parallel Interface DS39935B, 2009 Microchip Technology Inc.
if ENCX24J600
config ENC28J60_NINTERFACES
int "Number of physical ENCX24J600"
default 1
range 1,1
---help---
Specifies the number of physical ENCX24J600
devices that will be supported.
config ENCX24J600_SPIMODE
int "SPI mode"
default 0
---help---
Controls the SPI mode. The ENCX24J600 spec says that it supports SPI
mode 0,0 only: "The implementation used on this device supports SPI
mode 0,0 only. In addition, the SPI port requires that SCK be at Idle
in a low state; selectable clock polarity is not supported."
However, sometimes you need to tinker with these things.
config ENCX24J600_FREQUENCY
int "SPI frequency"
default 14000000
---help---
Define to use a different bus frequency
config ENCX24J600_STATS
bool "Network statistics support"
default n
---help---
Collect network statistics
config ENCX24J600_DUMPPACKET
bool "Dump Packets"
default n
---help---
If selected, the ENCX24J600 driver will dump the contents of each
packet to the console.
config ENCX24J600_REGDEBUG
bool "Register-Level Debug"
default n
depends on DEBUG && DEBUG_NET
---help---
Enable very low-level register access debug. Depends on DEBUG and DEBUG_NET.
endif
config NET_E1000
bool "E1000 support"
default n
@ -86,7 +142,7 @@ config NET_E1000
config NET_SLIP
bool "SLIP (serial line) support"
default n
---help---
---help---
Reference: RFC 1055
config NET_VNET

4
drivers/net/Make.defs
View file

@ -51,6 +51,10 @@ ifeq ($(CONFIG_ENC28J60),y)
CSRCS += enc28j60.c
endif
ifeq ($(CONFIG_ENCX24J600),y)
CSRCS += encx24j600.c
endif
ifeq ($(CONFIG_NET_VNET),y)
CSRCS += vnet.c
endif

2382
drivers/net/encx24j600.c Normal file
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File diff suppressed because it is too large Load diff

423
drivers/net/encx24j600.h Normal file
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@ -0,0 +1,423 @@
/****************************************************************************
* drivers/net/encx24j600.h
*
* Copyright (C) 2013 UVC Ingenieure. All rights reserved.
* Author: Max Holtberg <mh@uvc.de>
*
* References:
* - ENC424J600/624J600 Data Sheet, Stand-Alone 10/100 Ethernet Controller
* with SPI or Parallel Interface, DS39935C, 2010 Microchip Technology Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
#ifndef __DRIVERS_NET_ENCX24J600_H
#define __DRIVERS_NET_ENCX24J600_H
/****************************************************************************
* Included Files
****************************************************************************/
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* ENCX24J600 Commands ********************************************************/
/* The SPI opcodes are divided into four families:
*
* Single Byte: Direct opcode instructions; designed for task-oriented SFR
* operations with no data returned
*
* Two-Byte: Direct opcode instruction; designed for SFR operation with byte
* data returned
*
* Three-Byte: Opcode with word length argument; includes read and write
* operations, designed for pointer manipulation with word length data returned
*
* N-Byte: Opcode with one or more bytes of argument; includes read and write
* operations designed for general memory space access with one or more bytes of
* data returned
*/
/* Single-Byte Instructions */
/* Because all single byte instructions are fixed length with no optional
* parameters, it is possible to execute any instruction immediately following
* the execution of any single byte instruction without deasserting the chip
* select line in between.
*/
#define ENC_B0SEL (0xc0) /* Selects SFR Bank 0 */
#define ENC_B1SEL (0xc2) /* Selects SFR Bank 1 */
#define ENC_B2SEL (0xc4) /* Selects SFR Bank 2 */
#define ENC_B3SEL (0xc6) /* Selects SFR Bank 3 */
#define ENC_SETETHRST (0xca) /* Issues System Reset by setting ETHRST (ECON2<4>) */
#define ENC_FCDISABLE (0xe0) /* Disables flow control (sets ECON1<7:6> = 00) */
#define ENC_FCSINGLE (0xe2) /* Transmits a single pause frame (sets ECON1<7:6> = 01) */
#define ENC_FCMULTIPLE (0xe4) /* Enables flow control with periodic pause frames (sets ECON1<7:6> = 10) */
#define ENC_FCCLEAR (0xe6) /* Terminates flow control with a final pause frame (sets ECON1<7:6> = 11) */
#define ENC_SETPKTDEC (0xcc) /* Decrements PKTCNT by setting PKTDEC (ECON1<8>) */
#define ENC_DMASTOP (0xd2) /* Stops current DMA operation by clearing DMAST (ECON1<5>) */
#define ENC_DMACKSUM (0xd8) /* Starts DMA and checksum operation (sets ECON1<5:2> = 1000) */
#define ENC_DMACKSUMS (0xda) /* Starts DMA checksum operation with seed (sets ECON1<5:2> = 1010) */
#define ENC_DMACOPY (0xdc) /* Starts DMA copy and checksum operation (sets ECON1<5:2> = 1100) */
#define ENC_DMACOPYS (0xde) /* Starts DMA copy and checksum operation with seed (sets ECON1<5:2> = 1110) */
#define ENC_SETTXRTS (0xd4) /* Sets TXRTS (ECON1<1>), sends an Ethernet packet */
#define ENC_ENABLERX (0xe8) /* Enables packet reception by setting RXEN (ECON1<0>) */
#define ENC_DISABLERX (0xea) /* Disables packet reception by clearing RXEN (ECON1<0>) */
#define ENC_SETEIE (0xec) /* Enable Ethernet Interrupts by setting INT (ESTAT<15>) */
#define ENC_CLREIE (0xee) /* Disable Ethernet Interrupts by clearing INT (ESTAT<15>) */
/* Two-Byte Instructions */
/* There is only one instruction in the ENCX24J600 command set which uses two
* SPI bytes. The Read Bank Select opcode, RBSEL, reads the internal SFR bank
* select state and returns the value to the host controller.
*/
#define ENC_RBSEL (0xc8)
/* Three-Byte Instructions */
#define ENC_WGPRDPT (0x60) /* Write General Purpose Buffer Read Pointer (EGPRDPT) */
#define ENC_RGPRDPT (0x62) /* Read General Purpose Buffer Read Pointer (EGPRDPT) */
#define ENC_WRXRDPT (0x64) /* Write Receive Buffer Read Pointer (ERXRDPT) */
#define ENC_RRXRDPT (0x66) /* Read Receive Buffer Read Pointer (ERXRDPT) */
#define ENC_WUDARDPT (0x68) /* Write User-Defined Area Read Pointer (EUDARDPT) */
#define ENC_RUDARDPT (0x6a) /* Read User-Defined Area Read Pointer (EUDARDPT) */
#define ENC_WGPWRPT (0x6c) /* Write General Purpose Buffer Write Pointer (EGPWRPT) */
#define ENC_RGPWRPT (0x6e) /* Read General Purpose Buffer Write Pointer (EGPWRPT) */
#define ENC_WRXWRPT (0x70) /* Write Receive Buffer Write Pointer (ERXWRPT) */
#define ENC_RRXWRPT (0x72) /* Read Receive Buffer Write Pointer (ERXWRPT) */
#define ENC_WUDAWRPT (0x78) /* Write User-Defined Area Write Pointer (EUDAWRPT) */
#define ENC_RUDAWRPT (0x76) /* Read User-Defined Area Write Pointer (EUDAWRPT) */
/* Banked N-Byte Instructions */
#define ENC_RCR (0x00) /* Read Control Register
000 | aaaaa | (Register value returned)) */
#define ENC_WCR (0x40) /* Write Control Register
010 | aaaaa | dddddddd */
#define ENC_BFS (0x80) /* Bit Field Set
100 | aaaaa | dddddddd */
#define ENC_BFC (0xa0) /* Bit Field Clear
101 | aaaaa | dddddddd */
/* Unbanked N-Byte Instructions */
#define ENC_RCRU (0x20) /* Read Control Register(s), Unbanked */
#define ENC_WCRU (0x22) /* Write Control Register(s), Unbanked */
#define ENC_BFSU (0x24) /* Bit Field(s) Set, Unbanked */
#define ENC_BFCU (0x26) /* Bit Field(s) Clear, Unbanked */
/* SRAM Access Instructions */
#define ENC_RGPDATA (0x28) /* Read Data from EGPDATA */
#define ENC_WGPDATA (0x2a) /* Write Data from EGPDATA */
#define ENC_RRXDATA (0x2c) /* Read Data from ERXDATA */
#define ENC_WRXDATA (0x2e) /* Write Data from ERXDATA */
#define ENC_RUDADATA (0x30) /* Read Data from EUDADATA */
#define ENC_WUDADATA (0x32) /* Write Data from EUDADATA */
/* Banked Control Registers *************************************************/
/* Registers are described by 16 bit values. The high byte describes the bank
* by the appropiate bank selection command.
* For registers which are available on all banks the comnmand is set to 0.
* Unbanked registers are identified by 0x01.
*/
#define ENC_ADDR_SHIFT (0)
#define ENC_ADDR_MASK (0xff << ENC_ADDR_SHIFT)
#define ENC_BANK_SHIFT (8)
#define ENC_BANK_MASK (0xff << ENC_BANK_SHIFT)
#define REGADDR(a,b) ((b) << ENC_BANK_SHIFT | (a) << ENC_ADDR_SHIFT)
#define GETADDR(a) (((a) & ENC_ADDR_MASK) >> ENC_ADDR_SHIFT)
#define GETBANK(a) (((a) & ENC_BANK_MASK) >> ENC_BANK_SHIFT)
/* Bank 0 Control Register Addresses */
#define ENC_ETXST REGADDR(0x00, ENC_B0SEL)
#define ENC_ETXLEN REGADDR(0x02, ENC_B0SEL)
#define ENC_ERXST REGADDR(0x04, ENC_B0SEL)
#define ENC_ERXTAIL REGADDR(0x06, ENC_B0SEL)
#define ENC_ERXHEAD REGADDR(0x08, ENC_B0SEL)
#define ENC_EDMAST REGADDR(0x0a, ENC_B0SEL)
#define ENC_EDMALEN REGADDR(0x0c, ENC_B0SEL)
#define ENC_EDMADST REGADDR(0x0e, ENC_B0SEL)
#define ENC_EDMACS REGADDR(0x10, ENC_B0SEL)
#define ENC_ETXSTAT REGADDR(0x12, ENC_B0SEL)
#define ENC_ETXWIRE REGADDR(0x14, ENC_B0SEL)
/* Bank 1 Contro Register Addresses */
#define ENC_EHT1 REGADDR(0x00, ENC_B1SEL)
#define ENC_EHT2 REGADDR(0x02, ENC_B1SEL)
#define ENC_EHT3 REGADDR(0x04, ENC_B1SEL)
#define ENC_EHT4 REGADDR(0x06, ENC_B1SEL)
#define ENC_EPMM1 REGADDR(0x08, ENC_B1SEL)
#define ENC_EPMM2 REGADDR(0x0a, ENC_B1SEL)
#define ENC_EPMM3 REGADDR(0x0c, ENC_B1SEL)
#define ENC_EPMM4 REGADDR(0x0e, ENC_B1SEL)
#define ENC_EPMCS REGADDR(0x10, ENC_B1SEL)
#define ENC_EPMO REGADDR(0x12, ENC_B1SEL)
#define ENC_ERXFCON REGADDR(0x14, ENC_B1SEL)
/* Bank 2 Control Register Addresses */
#define ENC_MACON1 REGADDR(0x00, ENC_B2SEL)
#define ENC_MACON2 REGADDR(0x02, ENC_B2SEL)
#define ENC_MABBIPG REGADDR(0x04, ENC_B2SEL)
#define ENC_MAIPG REGADDR(0x06, ENC_B2SEL)
#define ENC_MACLCON REGADDR(0x08, ENC_B2SEL)
#define ENC_MAMXFL REGADDR(0x0a, ENC_B2SEL)
/* 0x0c - 0x11 reserved */
#define ENC_MICMD REGADDR(0x12, ENC_B2SEL)
#define ENC_MIREGADR REGADDR(0x14, ENC_B2SEL)
/* MAC Control Register 1 Bit Definitions */
#define MACON1_PASSALL (1 << 1)
#define MACON1_RXPAUS (1 << 2)
#define MACON1_LOOPBK (1 << 4)
/* MAC Control Register 2 Bit Definitions */
#define MACON2_FULDPX (1 << 0) /* MAC Full-Duplex Enable bit */
#define MACON2_HFRMEN (1 << 2) /* Huge Frame Enable bit */
#define MACON2_PHDREN (1 << 3) /* Proprietary Header Enable bit */
#define MACON2_TXCRCEN (1 << 4) /* Transmit CRC Enable bit */
#define MACON2_PADCFG0 (1 << 5) /* Automatic Pad and CRC Configuration bits */
#define MACON2_PADCFG1 (1 << 6)
#define MACON2_PADCFG2 (1 << 7)
#define MACON2_NOBKOFF (1 << 12) /* No Backoff Enable bit (applies to half duplex only) */
#define MACON2_BPEN (1 << 13) /* No Backoff During Back Pressure Enable bit (applies to half duplex only) */
#define MACON2_DEFER (1 << 14) /* Defer Transmission Enable bit (applies to half duplex only) */
/* MII Management Command Register Bit Definitions */
#define MICMD_MIIRD (1 << 0) /* MII Read Enable bit */
#define MICMD_MIISCAN (1 << 1) /* MII Scan Enable bit */
/* MII Management Status Register Bit Definitions */
#define MISTAT_BUSY (1 << 0) /* MII Management Busy Status bit */
#define MISTAT_SCAN (1 << 1) /* MII Management Scan Status bit */
#define MISTAT_NVALID (1 << 2) /* MII Management Read Data Not Valid Status bit */
/* Bank 3 Control Register Addresses */
#define ENC_MAADR3 REGADDR(0x00, ENC_B3SEL)
#define ENC_MAADR2 REGADDR(0x02, ENC_B3SEL)
#define ENC_MAADR1 REGADDR(0x04, ENC_B3SEL)
#define ENC_MIWR REGADDR(0x06, ENC_B3SEL)
#define ENC_MIRD REGADDR(0x08, ENC_B3SEL)
#define ENC_MISTAT REGADDR(0x0a, ENC_B3SEL)
#define ENC_EPAUS REGADDR(0x0c, ENC_B3SEL)
#define ENC_ECON2 REGADDR(0x0e, ENC_B3SEL)
#define ENC_ERXWM REGADDR(0x10, ENC_B3SEL)
#define ENC_EIE REGADDR(0x12, ENC_B3SEL)
#define ENC_EIDLED REGADDR(0x14, ENC_B3SEL)
/* Ethernet Control Register Bit Definitions */
#define ECON2_AESLEN0 (1 << 0) /* AES Key Length Control bits */
#define ECON2_AESLEN1 (1 << 1) /* Modular Exponentiation Length Control bits */
#define ECON2_MODLEN0 (1 << 2)
#define ECON2_MODLEN1 (1 << 3)
#define ECON2_ETHRST (1 << 4) /* Master Ethernet Reset bit */
#define ECON2_RXRST (1 << 5) /* Receive Logic Reset bit */
#define ECON2_TXRST (1 << 6) /* Transmit Logic Reset bit */
#define ECON2_AUTOFC (1 << 7) /* Automatic Flow Control Enable bit */
#define ECON2_COCON_SHIFT (8) /* CLKOUT Frequency Control bits */
#define ECON2_COCON_MASK (0x0f << ECON2_COCON_SHIFT)
#define ECON2_SHA1MD5 (1 << 12) /* SHA-1/MD5 Hash Control bit */
#define ECON2_TXMAC (1 << 13) /* Automatically Transmit MAC Address Enable bit */
#define ECON2_STRCH (1 << 14) /* LED Stretching Enable bit */
#define ECON2_ETHEN (1 << 15) /* Ethernet Enable bit */
/* Ethernet Interrupt Enable Register Bit Definitions */
#define EIE_PCFULIE (1 << 0) /* Packet Counter Full Interrupt Enable bit */
#define EIE_RXABTIE (1 << 1) /* Receive Abort Interrupt Enable bit */
#define EIE_TXABTIE (1 << 2) /* Transmit Abort Interrupt Enable bit */
#define EIE_TXIE (1 << 3) /* Transmit Done Interrupt Enable bit */
#define EIE_DMAIE (1 << 5) /* DMA Interrupt Enable bit */
#define EIE_PKTIE (1 << 6) /* RX Packet Pending Interrupt Enable bit */
#define EIE_LINKIE (1 << 11) /* PHY Link Status Change Interrupt Enable bit */
#define EIE_AESIE (1 << 12) /* AES Encrypt/Decrypt Interrupt Enable bit */
#define EIE_HASHIE (1 << 13) /* MD5/SHA-1 Hash Interrupt Enable bit */
#define EIE_MODEXIE (1 << 14) /* Modular Exponentiation Interrupt Enable bit */
#define EIE_INTIE (1 << 15) /* INT Global Interrupt Enable bit */
/**
* The last 10 bytes (16h to 1Fh) of all SPI banks point to a common set of five
* registers: EUDAST, EUDAND, ESTAT, EIR and ECON1. These are key registers used
* in controlling and monitoring the operation of the device. Their common
* banked addresses allow easy access without switching the bank.
*/
/* Common Register Addresses */
#define ENC_EUDAST REGADDR(0x16, 0x00) /* User-Defined Area Start Pointer (EUDAST<7:0>) */
#define ENC_EUDAND REGADDR(0x18, 0x00) /* User-Defined Area End Pointer (EUDAND<7:0>) */
#define ENC_ESTAT REGADDR(0x1a, 0x00)
#define ENC_EIR REGADDR(0x1c, 0x00)
#define ENC_ECON1 REGADDR(0x1e, 0x00)
/* Ethernet Status Register Bit Definitions */
#define ESTAT_PKTCNT_SHIFT (0) /* Receive Packet Count bits */
#define ESTAT_PKTCNT_MASK (0xff)
#define ESTAT_PHYLNK (1 << 8) /* PHY Linked Status bit */
#define ESTAT_PHYDPX (1 << 10) /* PHY Full Duplex Status bit */
#define ESTAT_CLKRDY (1 << 12) /* Clock Ready Status bit */
#define ESTAT_RXBUSY (1 << 13) /* Receive Logic Active Status bit */
#define ESTAT_FCIDLE (1 << 14) /* Flow Control Idle Status bit */
#define ESTAT_INT (1 << 15) /* Interrupt Pending Status bit */
/* Ethernet Interrupt Flag Register Bit Definitions */
#define EIR_PCFULIF (1 << 0) /* Packet Counter Full Interrupt Flag bit */
#define EIR_RXABTIF (1 << 1) /* Receive Abort Interrupt Flag bit */
#define EIR_TXABTIF (1 << 2) /* Transmit Abort Interrupt Flag bit */
#define EIR_TXIF (1 << 3) /* Transmit Done Interrupt Flag bit */
#define EIR_DMAIF (1 << 5) /* DMA Interrupt Flag bit */
#define EIR_PKTIF (1 << 6) /* RX Packet Pending Interrupt Flag bit */
#define EIR_LINKIF (1 << 11) /* PHY Link Status Change Interrupt Flag bit */
#define EIR_AESIF (1 << 12) /* AES Encrypt/Decrypt Interrupt Flag bit */
#define EIR_HASHIF (1 << 13) /* MD5/SHA-1 Hash Interrupt Flag bit */
#define EIR_MODEXIF (1 << 14) /* Modular Exponentiation Interrupt Flag bit */
#define EIR_CRYPTEN (1 << 15) /* Modular Exponentiation and AES Cryptographic Modules Enable bit */
#define EIR_ALLINTS (0xf86f)
/* Ethernet Control Register 1 Bit Definitions */
#define ECON1_RXEN (1 << 0) /* Receive Enable bit */
#define ECON1_TXRTS (1 << 1) /* Transmit Request to Send Status/Control bit */
#define ECON1_DMANOCS (1 << 2) /* DMA No Checksum Control bit */
#define ECON1_DMACSSD (1 << 3) /* DMA Checksum Seed Control bit */
#define ECON1_DMACPY (1 << 4) /* DMA Copy Control bit */
#define ECON1_DMAST (1 << 5) /* DMA Start bit */
#define ECON1_FCOP0 (1 << 6) /* Flow Control Operation Control/Status bits */
#define ECON1_FCOP1 (1 << 7) /* Flow Control Operation Control/Status bits */
#define ECON1_PKTDEC (1 << 8) /* RX Packet Counter Decrement Control bit */
#define ECON1_AESOP0 (1 << 9) /* AES Operation Control bits */
#define ECON1_AESOP1 (1 << 10) /* AES Operation Control bits */
#define ECON1_AESST (1 << 11) /* AES Encrypt/Decrypt Start bit */
#define ECON1_HASHLST (1 << 12) /* MD5/SHA-1 Hash Last Block Control bit */
#define ECON1_HASHOP (1 << 13) /* MD5/SHA-1 Hash Operation Control bit */
#define ECON1_HASHEN (1 << 14) /* MD5/SHA-1 Hash Enable bit */
#define ECON1_MODEXST (1 << 15) /* Modular Exponentiation Start bit */
/* Unbanked Register Addresses */
#if 0
/* Disabled to prevent accidental use. All unbanked operations are implemented
* using the specific manipulation commands.
*/
#define ENC_EGPDATA 0x80
#define ENC_ERXDATA 0x82
#define ENC_EUDADATA 0x84
#define ENC_EGPRDPT 0x86
#define ENC_EGPWRPT 0x88
#define ENC_ERXRDPT 0x8a
#define ENC_ERXWRPT 0x8c
#define ENC_EUDARDPT 0x8e
#define ENC_EUDAWRPT 0x90
#endif
/* PHY Registers ************************************************************/
#define ENC_PHCON1 0x00
#define ENC_PHSTAT1 0x01
#define ENC_PHANA 0x04
#define ENC_PHANLPA 0x05
#define ENC_PHANE 0x06
#define ENC_PHCON2 0x11
#define ENC_PHSTAT2 0x1b
#define ENC_PHSTAT3 0x1f
/* PHY Control Register 1 Bit Definitions */
#define PHCON1_PFULDPX (1 << 8) /* PHY Duplex Select Control bit */
#define PHCON1_RENEG (1 << 9) /* Restart Auto-Negotiation Control bit */
#define PHCON1_PSLEEP (1 << 11) /* PHY Sleep Enable bit */
#define PHCON1_ANEN (1 << 12) /* PHY Auto-Negotiation Enable bit */
#define PHCON1_SPD100 (1 << 13) /* PHY Speed Select Control bit */
#define PHCON1_PLOOPBK (1 << 14) /* PHY Loopback Enable bit */
#define PHCON1_PRST (1 << 15) /* PHY Reset bit */
/* PHY Status Register 1 Bit Definitions */
#define PHSTAT1_EXTREGS (1 << 0) /* Extended Capabilities Registers Present Status bit */
#define PHSTAT1_LLSTAT (1 << 2) /* Latching Link Status bit */
#define PHSTAT1_ANABLE (1 << 3) /* Auto-Negotiation Ability Status bit */
#define PHSTAT1_LRFAULT (1 << 4) /* Latching Remote Fault Condition Status bit */
#define PHSTAT1_ANDONE (1 << 5) /* Auto-Negotiation Done Status bit */
#define PHSTAT1_HALF10 (1 << 11) /* 10Base-T Half-Duplex Ability Status bit */
#define PHSTAT1_FULL10 (1 << 12) /* 10Base-T Full-Duplex Ability Status bit */
#define PHSTAT1_HALF100 (1 << 13) /* 100Base-TX Half-Duplex Ability Status bit */
#define PHSTAT1_FULL100 (1 << 13) /* 100Base-TX Full-Duplex Ability Status bit */
/* PHY Auto-Negotiation Advertisement Register Bit Definitions */
#define PHANA_ADIEEE0 (1 << 0)
#define PHANA_ADIEEE1 (1 << 1)
#define PHANA_ADIEEE2 (1 << 2)
#define PHANA_ADIEEE3 (1 << 3)
#define PHANA_ADIEEE4 (1 << 4)
#define PHANA_AD10 (1 << 5) /* Advertise 10Base-T Half-Duplex Ability bit */
#define PHANA_AD10FD (1 << 6) /* Advertise 10Base-T Full-Duplex Ability bit */
#define PHANA_AD100 (1 << 7) /* Advertise 100Base-TX Half-Duplex Ability bit */
#define PHANA_AD100FD (1 << 8) /* Advertise 100Base-TX Full-Duplex Ability bit */
/* Advertise PAUSE Flow Control Ability bits */
/* 11 = Local device supports both symmetric PAUSE and asymmetric PAUSE toward local device */
/* 10 = Local device supports asymmetric PAUSE toward link partner only */
/* 01 = Local device supports symmetric PAUSE only (Normal Flow Control mode) */
/* 00 = Local device does not support PAUSE flow control */
#define PHANA_ADPAUS0 (1 << 10)
#define PHANA_ADPAUS1 (1 << 11)
#define PHANA_ADFAULT (1 << 13) /* Advertise Remote Fault Condition bit */
#define PHANA_ADNP (1 << 15) /* Advertise Next Page Ability bit */
/* Packet Memory ************************************************************/
/* 24-Kbyte Transmit/Receive Packet Dual Port SRAM */
#define PKTMEM_START 0x0000
#define PKTMEM_END 0x5fff
/* RX Status Bit Definitions ************************************************/
#define RXSTAT_OK (1 << 7)
#endif /* __DRIVERS_NET_ENCX24J600_H */

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/****************************************************************************
* include/nuttx/net/encx24j600.h
*
* Copyright (C) 2013 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
#ifndef __INCLUDE_NUTTX_NET_ENCX24J600_H
#define __INCLUDE_NUTTX_NET_ENCX24J600_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <stdint.h>
#include <stdbool.h>
#include <nuttx/irq.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* ENCX24J600 Configuration Settings:
*
* CONFIG_ENCX24J600 - Enabled ENCX24J600 support
* CONFIG_ENCX24J600_SPIMODE - Controls the SPI mode
* CONFIG_ENCX24J600_FREQUENCY - Define to use a different bus frequency
* CONFIG_ENCX24J600_NINTERFACES - Specifies the number of physical ENCX24J600
* devices that will be supported.
* CONFIG_ENCX24J600_STATS - Collect network statistics
* CONFIG_ENCX24J600_HALFDUPPLEX - Default is full duplex
*/
/****************************************************************************
* Public Types
****************************************************************************/
/* This structure returns driver statistics (if enabled) */
#ifdef CONFIG_ENCX24J600_STATS
struct enc_stats_s
{
uint8_t maxpktcnt; /* Max. number of buffered RX packets */
uint32_t txrequests; /* Number of TX packets queued */
uint32_t txifs; /* TXIF completion events */
uint32_t txabrts; /* TXIF completions with ESTAT.TXABRT */
uint32_t txerifs; /* TXERIF error events */
uint32_t txtimeouts; /* S/W detected TX timeouts */
uint32_t pktifs; /* PKTIF RX completion events */
uint32_t rxnotok; /* PKTIF without RXSTAT_OK */
uint32_t rxpktlen; /* PKTIF with bad pktlen */
uint32_t rxerifs; /* RXERIF error evernts */
};
#endif
/* The ENCX24J600 normal provides interrupts to the MCU via a GPIO pin. The
* following structure provides an MCU-independent mechanixm for controlling
* the ENCX24J600 GPIO interrupt.
*
* The ENC32J60 interrupt is an active low, *level* interrupt. "When an
* interrupt occurs, the interrupt flag is set. If the interrupt is enabled
* in the EIE register and the INTIE global interrupt enable bit is set, the
* INT pin will be driven low"
*
* "When an enabled interrupt occurs, the interrupt pin will remain low until
* all flags which are causing the interrupt are cleared or masked off
* (enable bit is cleared) by the host controller." However, the interrupt
* will behave like a falling edge interrupt because "After an interrupt
* occurs, the host controller [clears] the global enable bit for the
* interrupt pin before servicing the interrupt. Clearing the enable bit
* will cause the interrupt pin to return to the non-asserted state (high).
* Doing so will prevent the host controller from missing a falling edge
* should another interrupt occur while the immediate interrupt is being
* serviced."
*/
struct enc_lower_s
{
int (*attach)(FAR const struct enc_lower_s *lower, xcpt_t handler);
void (*enable)(FAR const struct enc_lower_s *lower);
void (*disable)(FAR const struct enc_lower_s *lower);
};
/****************************************************************************
* Public Data
****************************************************************************/
#ifdef __cplusplus
#define EXTERN extern "C"
extern "C" {
#else
#define EXTERN extern
#endif
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Function: enc_initialize
*
* Description:
* Initialize the Ethernet driver. The ENCX24J600 device is assumed to be
* in the post-reset state upon entry to this function.
*
* Parameters:
* spi - A reference to the platform's SPI driver for the ENCX24J600
* lower - The MCU-specific interrupt used to control low-level MCU
* functions (i.e., ENCX24J600 GPIO interrupts).
* devno - If more than one ENCX24J600 is supported, then this is the
* zero based number that identifies the ENCX24J600;
*
* Returned Value:
* OK on success; Negated errno on failure.
*
* Assumptions:
*
****************************************************************************/
struct spi_dev_s; /* see nuttx/spi/spi.h */
int enc_initialize(FAR struct spi_dev_s *spi,
FAR const struct enc_lower_s *lower, unsigned int devno);
/****************************************************************************
* Function: enc_stats
*
* Description:
* Return accumulated ENCX24J600 statistics. Statistics are cleared after
* being returned.
*
* Parameters:
* devno - If more than one ENCX24J600 is supported, then this is the
* zero based number that identifies the ENCX24J600;
* stats - The user-provided location to return the statistics.
*
* Returned Value:
* OK on success; Negated errno on failure.
*
* Assumptions:
*
****************************************************************************/
#ifdef CONFIG_ENCX24J600_STATS
int enc_stats(unsigned int devno, struct enc_stats_s *stats);
#endif
#undef EXTERN
#ifdef __cplusplus
}
#endif
#endif /* __INCLUDE_NUTTX_NET_ENCX24J600_H */