lupyuen/local-nuttx-update
1
0
Fork 0
forked from nuttx/nuttx-update
Code Pull requests Activity

Call up_irqinitialize from irq subsystem

Browse source 
Call up_irqinitialize from irq subsystem to make the irq ready for use as soon as possible
This commit is contained in:
Xiang Xiao 2020-02-07 14:41:58 +08:00 committed by Gregory Nutt
parent 48f1793a60
commit 76bbed07a4
55 changed files with 87 additions and 177 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

6
arch/arm/src/am335x/am335x_i2c.c
View file

@ -544,7 +544,7 @@ static inline int am335x_i2c_sem_waitdone(FAR struct am335x_i2c_priv_s *priv)
{
/* Get the current time */
(void)clock_gettime(CLOCK_REALTIME, &abstime);
clock_gettime(CLOCK_REALTIME, &abstime);
/* Calculate a time in the future */
@ -1294,8 +1294,8 @@ static int am335x_i2c_init(FAR struct am335x_i2c_priv_s *priv)
/* Configure pins */
(void)am335x_gpio_config(priv->config->scl_pin);
(void)am335x_gpio_config(priv->config->sda_pin);
am335x_gpio_config(priv->config->scl_pin);
am335x_gpio_config(priv->config->sda_pin);
/* Disable I2C module */

4
arch/arm/src/common/up_initialize.c
View file

@ -127,10 +127,6 @@ void up_initialize(void)
up_addregion();
/* Initialize the interrupt subsystem */
up_irqinitialize();
/* Initialize the system timer interrupt */
#if !defined(CONFIG_SUPPRESS_INTERRUPTS) && !defined(CONFIG_SUPPRESS_TIMER_INTS) && \

2
arch/arm/src/common/up_internal.h
View file

@ -337,8 +337,6 @@ void up_pminitialize(void);
/* Interrupt handling *******************************************************/
void up_irqinitialize(void);
/* Exception handling logic unique to the Cortex-M family */
#if defined(CONFIG_ARCH_CORTEXM0) || defined(CONFIG_ARCH_ARMV7M)

20
arch/arm/src/samd5e5/sam_gmac.c
View file

@ -752,8 +752,8 @@ static int sam_transmit(struct sam_gmac_s *priv)
/* Setup the TX timeout watchdog (perhaps restarting the timer) */
(void)wd_start(priv->txtimeout, SAM_TXTIMEOUT, sam_txtimeout_expiry, 1,
(uint32_t)priv);
wd_start(priv->txtimeout, SAM_TXTIMEOUT, sam_txtimeout_expiry, 1,
(uint32_t)priv);
/* Set d_len to zero meaning that the d_buf[] packet buffer is again
* available.
@ -895,7 +895,7 @@ static void sam_dopoll(struct sam_gmac_s *priv)
{
/* If we have the descriptor, then poll the network for new XMIT data. */
(void)devif_poll(dev, sam_txpoll);
devif_poll(dev, sam_txpoll);
}
}
@ -1764,12 +1764,12 @@ static void sam_poll_work(FAR void *arg)
{
/* Update TCP timing states and poll the network for new XMIT data. */
(void)devif_timer(dev, sam_txpoll);
devif_timer(dev, sam_txpoll);
}
/* Setup the watchdog poll timer again */
(void)wd_start(priv->txpoll, SAM_WDDELAY, sam_poll_expiry, 1, priv);
wd_start(priv->txpoll, SAM_WDDELAY, sam_poll_expiry, 1, priv);
net_unlock();
}
@ -1871,7 +1871,7 @@ static int sam_ifup(struct net_driver_s *dev)
/* Set and activate a timer process */
(void)wd_start(priv->txpoll, SAM_WDDELAY, sam_poll_expiry, 1, (uint32_t)priv);
wd_start(priv->txpoll, SAM_WDDELAY, sam_poll_expiry, 1, (uint32_t)priv);
/* Enable the GMAC interrupt */
@ -3576,7 +3576,7 @@ static void sam_ipv6multicast(struct sam_gmac_s *priv)
ninfo("IPv6 Multicast: %02x:%02x:%02x:%02x:%02x:%02x\n",
mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
(void)sam_addmac(dev, mac);
sam_addmac(dev, mac);
#ifdef CONFIG_NET_ICMPv6_AUTOCONF
/* Add the IPv6 all link-local nodes Ethernet address. This is the
@ -3584,7 +3584,7 @@ static void sam_ipv6multicast(struct sam_gmac_s *priv)
* packets.
*/
(void)sam_addmac(dev, g_ipv6_ethallnodes.ether_addr_octet);
sam_addmac(dev, g_ipv6_ethallnodes.ether_addr_octet);
#endif /* CONFIG_NET_ICMPv6_AUTOCONF */
#ifdef CONFIG_NET_ICMPv6_ROUTER
@ -3593,7 +3593,7 @@ static void sam_ipv6multicast(struct sam_gmac_s *priv)
* packets.
*/
(void)sam_addmac(dev, g_ipv6_ethallrouters.ether_addr_octet);
sam_addmac(dev, g_ipv6_ethallrouters.ether_addr_octet);
#endif /* CONFIG_NET_ICMPv6_ROUTER */
}
@ -3645,7 +3645,7 @@ static int sam_gmac_configure(struct sam_gmac_s *priv)
/* Clear any pending interrupts */
(void)sam_getreg(priv, SAM_GMAC_ISR);
sam_getreg(priv, SAM_GMAC_ISR);
/* Initial configuration:
*

4
arch/arm/src/stm32f7/stm32_sai.c
View file

@ -1041,7 +1041,7 @@ static void sai_worker(void *arg)
flags = enter_critical_section();
#ifdef CONFIG_STM32F7_SAI_DMA
(void)sai_dma_setup(priv);
sai_dma_setup(priv);
#endif
leave_critical_section(flags);
}
@ -1160,7 +1160,7 @@ static void sai_dma_callback(DMA_HANDLE handle, uint8_t isr, void *arg)
/* Cancel the watchdog timeout */
(void)wd_cancel(priv->dog);
wd_cancel(priv->dog);
/* Then schedule completion of the transfer to occur on the worker thread */

11
arch/arm/src/stm32h7/stm32_qspi.c
View file

@ -1380,7 +1380,7 @@ static void qspi_dma_callback(DMA_HANDLE handle, uint8_t isr, void *arg)
/* Cancel the watchdog timeout */
(void)wd_cancel(priv->dmadog);
wd_cancel(priv->dmadog);
/* Sample DMA registers at the time of the callback */
@ -1529,7 +1529,7 @@ static int qspi_memory_dma(struct stm32h7_qspidev_s *priv,
/* Cancel the watchdog timeout */
(void)wd_cancel(priv->dmadog);
wd_cancel(priv->dmadog);
/* Check if we were awakened by an error of some kind */
@ -1774,8 +1774,7 @@ static int qspi_lock(struct qspi_dev_s *dev, bool lock)
}
else
{
(void)nxsem_post(&priv->exclsem);
ret = OK;
ret = nxsem_post(&priv->exclsem);
}
return ret;
@ -2107,7 +2106,7 @@ static int qspi_command(struct qspi_dev_s *dev,
/* Wait for the interrupt routine to finish it's magic */
(void)nxsem_wait(&priv->op_sem);
nxsem_wait(&priv->op_sem);
MEMORY_SYNC();
/* Convey the result */
@ -2265,7 +2264,7 @@ static int qspi_memory(struct qspi_dev_s *dev,
/* Wait for the interrupt routine to finish it's magic */
(void)nxsem_wait(&priv->op_sem);
nxsem_wait(&priv->op_sem);
MEMORY_SYNC();
/* convey the result */

4
arch/avr/src/common/up_initialize.c
View file

@ -168,10 +168,6 @@ void up_initialize(void)
up_addregion();
/* Initialize the interrupt subsystem */
up_irqinitialize();
/* Initialize the system timer interrupt */
#if !defined(CONFIG_SUPPRESS_INTERRUPTS) && !defined(CONFIG_SUPPRESS_TIMER_INTS)

1
arch/avr/src/common/up_internal.h
View file

@ -123,7 +123,6 @@ extern uint32_t _ebss; /* End+1 of .bss */
/* Defined in files with the same name as the function */
void up_irqinitialize(void);
#ifdef CONFIG_ARCH_DMA
void weak_function up_dma_initialize(void);
#endif

4
arch/hc/src/common/up_initialize.c
View file

@ -90,10 +90,6 @@ void up_initialize(void)
up_addregion();
/* Initialize the interrupt subsystem */
up_irqinitialize();
/* Initialize the system timer interrupt */
#if !defined(CONFIG_SUPPRESS_INTERRUPTS) && !defined(CONFIG_SUPPRESS_TIMER_INTS)

1
arch/hc/src/common/up_internal.h
View file

@ -144,7 +144,6 @@ extern uint32_t g_intstackbase;
void up_copystate(uint8_t *dest, uint8_t *src);
void up_decodeirq(uint8_t *regs);
void up_irqinitialize(void);
int up_saveusercontext(uint8_t *saveregs);
void up_fullcontextrestore(uint8_t *restoreregs) noreturn_function;
void up_switchcontext(uint8_t *saveregs, uint8_t *restoreregs);

4
arch/mips/src/common/up_initialize.c
View file

@ -92,10 +92,6 @@ void up_initialize(void)
up_addregion();
/* Initialize the interrupt subsystem */
up_irqinitialize();
/* Initialize the system timer interrupt */
#if !defined(CONFIG_SUPPRESS_INTERRUPTS) && !defined(CONFIG_SUPPRESS_TIMER_INTS)

1
arch/mips/src/common/up_internal.h
View file

@ -235,7 +235,6 @@ void up_sigdeliver(void);
/* IRQs */
void up_irqinitialize(void);
bool up_pending_irq(int irq);
void up_clrpend_irq(int irq);

8
arch/mips/src/pic32mz/pic32mz-spi.c
View file

@ -753,7 +753,7 @@ static inline void spi_flush(FAR struct pic32mz_dev_s *priv)
while ((spi_getreg(priv, PIC32MZ_SPI_STAT_OFFSET) & SPI_STAT_SPIRBF) != 0)
{
(void)spi_getreg(priv, PIC32MZ_SPI_BUF_OFFSET);
spi_getreg(priv, PIC32MZ_SPI_BUF_OFFSET);
}
}
@ -889,7 +889,7 @@ static void spi_dmarxcallback(DMA_HANDLE handle, uint8_t status, void *arg)
/* Cancel the watchdog timeout */
(void)wd_cancel(priv->dmadog);
wd_cancel(priv->dmadog);
/* Sample DMA registers at the time of the callback */
@ -944,7 +944,7 @@ static void spi_dmatxcallback(DMA_HANDLE handle, uint8_t status, void *arg)
/* Cancel the watchdog timeout */
(void)wd_cancel(priv->dmadog);
wd_cancel(priv->dmadog);
/* Sample DMA registers at the time of the callback */
@ -1785,7 +1785,7 @@ static void spi_exchange(FAR struct spi_dev_s *dev, FAR const void *txbuffer,
/* Cancel the watchdog timeout */
(void)wd_cancel(priv->dmadog);
wd_cancel(priv->dmadog);
/* Check if we were awakened by an error of some kind. EINTR is not a
* failure. It simply means that the wait was awakened by a signal.

4
arch/misoc/src/lm32/lm32.h
View file

@ -128,10 +128,6 @@ void lm32_add_region(void);
void lm32_copystate(uint32_t *dest, uint32_t *src);
/* IRQ initialization *******************************************************/
void lm32_irq_initialize(void);
/* Interrupt decode *********************************************************/
uint32_t *lm32_decodeirq(uint32_t intstat, uint32_t *regs);

4
arch/misoc/src/lm32/lm32_initialize.c
View file

@ -67,10 +67,6 @@
void up_initialize(void)
{
/* Initialize the System Timer */
lm32_irq_initialize();
/* Initialize the serial driver */
misoc_serial_initialize();

4
arch/misoc/src/lm32/lm32_irq.c
View file

@ -60,10 +60,10 @@ volatile uint32_t *g_current_regs;
****************************************************************************/
/****************************************************************************
* Name: lm32_irq_initialize
* Name: up_irqinitialize
****************************************************************************/
void lm32_irq_initialize(void)
void up_irqinitialize(void)
{
/* currents_regs is non-NULL only while processing an interrupt */

4
arch/misoc/src/minerva/minerva.h
View file

@ -128,10 +128,6 @@ void minerva_add_region(void);
void minerva_copystate(uint32_t * dest, uint32_t * src);
/* IRQ initialization *******************************************************/
void minerva_irq_initialize(void);
/* Interrupt decode *********************************************************/
uint32_t *minerva_decodeirq(uint32_t intstat, uint32_t * regs);

4
arch/misoc/src/minerva/minerva_initialize.c
View file

@ -67,10 +67,6 @@
void up_initialize(void)
{
/* Initialize the System Timer */
minerva_irq_initialize();
/* Initialize the serial driver */
misoc_serial_initialize();

4
arch/misoc/src/minerva/minerva_irq.c
View file

@ -60,10 +60,10 @@ volatile uint32_t *g_current_regs;
****************************************************************************/
/****************************************************************************
* Name: minerva_irq_initialize
* Name: up_irqinitialize
****************************************************************************/
void minerva_irq_initialize(void)
void up_irqinitialize(void)
{
/* currents_regs is non-NULL only while processing an interrupt */

4
arch/or1k/src/common/up_initialize.c
View file

@ -185,10 +185,6 @@ void up_initialize(void)
up_addregion();
/* Initialize the interrupt subsystem */
up_irqinitialize();
/* Initialize the system timer interrupt */
#if !defined(CONFIG_SUPPRESS_INTERRUPTS) && !defined(CONFIG_SUPPRESS_TIMER_INTS) && \

2
arch/or1k/src/common/up_internal.h
View file

@ -263,8 +263,6 @@ void up_pminitialize(void);
/* Interrupt handling *******************************************************/
void up_irqinitialize(void);
/* Exception handling logic unique to the Cortex-M family */
/* Interrupt acknowledge and dispatch */

4
arch/renesas/src/common/up_initialize.c
View file

@ -86,10 +86,6 @@ void up_initialize(void)
g_current_regs = NULL;
/* Initialize the interrupt subsystem */
up_irqinitialize();
#if !defined(CONFIG_SUPPRESS_INTERRUPTS) && !defined(CONFIG_SUPPRESS_TIMER_INTS)
/* Initialize the system timer interrupt */

1
arch/renesas/src/common/up_internal.h
View file

@ -143,7 +143,6 @@ void up_dataabort(uint32_t *regs);
void up_decodeirq(uint32_t *regs);
uint32_t *up_doirq(int irq, uint32_t *regs);
void up_fullcontextrestore(uint32_t *regs) noreturn_function;
void up_irqinitialize(void);
void up_prefetchabort(uint32_t *regs);
int up_saveusercontext(uint32_t *regs);
void up_sigdeliver(void);

6
arch/risc-v/include/rv64gc/syscall.h
View file

@ -87,7 +87,7 @@
#define SYS_restore_context (1)
#define up_fullcontextrestore(restoreregs) \
(void)sys_call1(SYS_restore_context, (uintptr_t)restoreregs)
sys_call1(SYS_restore_context, (uintptr_t)restoreregs)
/* SYS call 2:
*
@ -96,7 +96,7 @@
#define SYS_switch_context (2)
#define up_switchcontext(saveregs, restoreregs) \
(void)sys_call2(SYS_switch_context, (uintptr_t)saveregs, (uintptr_t)restoreregs)
sys_call2(SYS_switch_context, (uintptr_t)saveregs, (uintptr_t)restoreregs)
#ifdef CONFIG_BUILD_KERNEL
/* SYS call 3:
@ -105,7 +105,7 @@
*/
#define SYS_syscall_return (3)
#define up_syscall_return() (void)sys_call0(SYS_syscall_return)
#define up_syscall_return() sys_call0(SYS_syscall_return)
#endif
#endif /* __ASSEMBLY__ */

4
arch/risc-v/src/common/up_initialize.c
View file

@ -114,10 +114,6 @@ void up_initialize(void)
up_addregion();
/* Initialize the interrupt subsystem */
up_irqinitialize();
/* Initialize the system timer interrupt */
#if !defined(CONFIG_SUPPRESS_INTERRUPTS) && !defined(CONFIG_SUPPRESS_TIMER_INTS) && \

1
arch/risc-v/src/common/up_internal.h
View file

@ -176,7 +176,6 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size);
/* IRQ initialization *******************************************************/
void up_irqinitialize(void);
void up_ack_irq(int irq);
#ifdef CONFIG_ARCH_RV64GC

4
arch/risc-v/src/fe310/fe310_irq.c
View file

@ -65,7 +65,7 @@ void up_irqinitialize(void)
{
/* Disable Machine interrupts */
(void)up_irq_save();
up_irq_save();
/* Disable all global interrupts */
@ -105,7 +105,7 @@ void up_irqinitialize(void)
/* And finally, enable interrupts */
(void)up_irq_enable();
up_irq_enable();
#endif
}

6
arch/risc-v/src/fe310/fe310_serial.c
View file

@ -646,14 +646,14 @@ void up_serialinit(void)
/* Register the console */
#ifdef HAVE_SERIAL_CONSOLE
(void)uart_register("/dev/console", &CONSOLE_DEV);
uart_register("/dev/console", &CONSOLE_DEV);
#endif
/* Register all UARTs */
(void)uart_register("/dev/ttyS0", &TTYS0_DEV);
uart_register("/dev/ttyS0", &TTYS0_DEV);
#ifdef TTYS1_DEV
(void)uart_register("/dev/ttyS1", &TTYS1_DEV);
uart_register("/dev/ttyS1", &TTYS1_DEV);
#endif
}

2
arch/risc-v/src/fe310/fe310_timerisr.c
View file

@ -132,7 +132,7 @@ void riscv_timer_initialize(void)
{
/* Attach timer interrupt handler */
(void)irq_attach(FE310_IRQ_MTIMER, fe310_timerisr, NULL);
irq_attach(FE310_IRQ_MTIMER, fe310_timerisr, NULL);
/* Reload CLINT mtimecmp */

2
arch/risc-v/src/k210/k210_cpuidlestack.c
View file

@ -98,7 +98,7 @@
int up_cpu_idlestack(int cpu, FAR struct tcb_s *tcb, size_t stack_size)
{
#if CONFIG_SMP_NCPUS > 1
(void)up_create_stack(tcb, stack_size, TCB_FLAG_TTYPE_KERNEL);
up_create_stack(tcb, stack_size, TCB_FLAG_TTYPE_KERNEL);
#endif
return OK;
}

4
arch/risc-v/src/k210/k210_cpustart.c
View file

@ -139,11 +139,11 @@ void k210_cpu_boot(int cpu)
sched_note_cpu_started(this_task());
#endif
(void)up_irq_enable();
up_irq_enable();
/* Then transfer control to the IDLE task */
(void)nx_idle_task(0, NULL);
nx_idle_task(0, NULL);
}
/****************************************************************************

4
arch/risc-v/src/k210/k210_irq.c
View file

@ -81,7 +81,7 @@ void up_irqinitialize(void)
{
/* Disable Machine interrupts */
(void)up_irq_save();
up_irq_save();
/* Disable all global interrupts */
@ -137,7 +137,7 @@ void up_irqinitialize(void)
/* And finally, enable interrupts */
(void)up_irq_enable();
up_irq_enable();
#endif
}

6
arch/risc-v/src/k210/k210_serial.c
View file

@ -646,14 +646,14 @@ void up_serialinit(void)
/* Register the console */
#ifdef HAVE_SERIAL_CONSOLE
(void)uart_register("/dev/console", &CONSOLE_DEV);
uart_register("/dev/console", &CONSOLE_DEV);
#endif
/* Register all UARTs */
(void)uart_register("/dev/ttyS0", &TTYS0_DEV);
uart_register("/dev/ttyS0", &TTYS0_DEV);
#ifdef TTYS1_DEV
(void)uart_register("/dev/ttyS1", &TTYS1_DEV);
uart_register("/dev/ttyS1", &TTYS1_DEV);
#endif
}

2
arch/risc-v/src/k210/k210_timerisr.c
View file

@ -135,7 +135,7 @@ void riscv_timer_initialize(void)
#if 1
/* Attach timer interrupt handler */
(void)irq_attach(K210_IRQ_MTIMER, k210_timerisr, NULL);
irq_attach(K210_IRQ_MTIMER, k210_timerisr, NULL);
/* Reload CLINT mtimecmp */

12
arch/risc-v/src/rv64gc/up_assert.c
View file

@ -307,19 +307,19 @@ static void _up_assert(int errorcode)
{
/* Flush any buffered SYSLOG data */
(void)syslog_flush();
syslog_flush();
/* Are we in an interrupt handler or the idle task? */
if (CURRENT_REGS || running_task()->flink == NULL)
{
(void)up_irq_save();
up_irq_save();
for (; ; )
{
#ifdef CONFIG_SMP
/* Try (again) to stop activity on other CPUs */
(void)spin_trylock(&g_cpu_irqlock);
spin_trylock(&g_cpu_irqlock);
#endif
#if CONFIG_BOARD_RESET_ON_ASSERT >= 1
@ -385,7 +385,7 @@ void up_assert(const uint8_t *filename, int lineno)
/* Flush any buffered SYSLOG data (from prior to the assertion) */
(void)syslog_flush();
syslog_flush();
#ifdef CONFIG_SMP
#if CONFIG_TASK_NAME_SIZE > 0
@ -420,12 +420,12 @@ void up_assert(const uint8_t *filename, int lineno)
#ifdef CONFIG_ARCH_USBDUMP
/* Dump USB trace data */
(void)usbtrace_enumerate(assert_tracecallback, NULL);
usbtrace_enumerate(assert_tracecallback, NULL);
#endif
/* Flush any buffered SYSLOG data (from the above) */
(void)syslog_flush();
syslog_flush();
#ifdef CONFIG_BOARD_CRASHDUMP
board_crashdump(up_getsp(), running_task(), filename, lineno);

2
arch/risc-v/src/rv64gc/up_fault.c
View file

@ -119,5 +119,5 @@ void up_fault(int irq, uint64_t *regs)
CURRENT_REGS[REG_TP], CURRENT_REGS[REG_RA]);
#endif
(void)up_irq_save();
up_irq_save();
}

4
arch/risc-v/src/rv64gc/up_sigdeliver.c
View file

@ -155,9 +155,9 @@ void up_sigdeliver(void)
*/
#ifdef CONFIG_SMP
(void)enter_critical_section();
enter_critical_section();
#else
(void)up_irq_save();
up_irq_save();
#endif
/* Restore the saved errno value */

11
arch/sim/include/irq.h
View file

@ -62,7 +62,7 @@
# define XCPTCONTEXT_REGS 6
#elif defined(CONFIG_HOST_ARM)
# define XCPTCONTEXT_REGS 16
# define XCPTCONTEXT_REGS 16
#endif
/****************************************************************************
@ -70,7 +70,6 @@
****************************************************************************/
#ifndef __ASSEMBLY__
/* Number of registers saved in context switch */
#if defined(CONFIG_HOST_X86_64) && !defined(CONFIG_SIM_M32)
typedef unsigned long xcpt_reg_t;
@ -94,6 +93,14 @@ struct xcptcontext
#ifndef __ASSEMBLY__
/****************************************************************************
* Name: up_irqinitialize
****************************************************************************/
static inline void up_irqinitialize(void)
{
}
/* Name: up_irq_save, up_irq_restore, and friends.
*
* NOTE: This function should never be called from application code and,

4
arch/x86/src/common/up_initialize.c
View file

@ -92,10 +92,6 @@ void up_initialize(void)
up_addregion();
/* Initialize the interrupt subsystem */
up_irqinitialize();
/* Initialize the system timer interrupt */
#if !defined(CONFIG_SUPPRESS_INTERRUPTS) && !defined(CONFIG_SUPPRESS_TIMER_INTS)

1
arch/x86/src/common/up_internal.h
View file

@ -177,7 +177,6 @@ void x86_boardinitialize(void);
void up_copystate(uint32_t *dest, uint32_t *src);
void up_savestate(uint32_t *regs);
void up_decodeirq(uint32_t *regs);
void up_irqinitialize(void);
#ifdef CONFIG_ARCH_DMA
void weak_function up_dma_initialize(void);
#endif

1
arch/xtensa/src/common/xtensa.h
View file

@ -308,7 +308,6 @@ void xtensa_sig_deliver(void);
/* Chip specific functions defined in arch/xtensa/src/<chip> */
/* IRQs */
void xtensa_irq_initialize(void);
bool xtensa_pending_irq(int irq);
void xtensa_clrpend_irq(int irq);

4
arch/xtensa/src/common/xtensa_initialize.c
View file

@ -100,10 +100,6 @@ void up_initialize(void)
xtensa_add_region();
/* Initialize the interrupt subsystem */
xtensa_irq_initialize();
#if !defined(CONFIG_SUPPRESS_INTERRUPTS) && !defined(CONFIG_SUPPRESS_TIMER_INTS)
/* Initialize the system timer interrupt */

4
arch/xtensa/src/esp32/esp32_irq.c
View file

@ -132,10 +132,10 @@ static inline void xtensa_attach_fromcpu1_interrupt(void)
****************************************************************************/
/****************************************************************************
* Name: xtensa_irq_initialize
* Name: up_irqinitialize
****************************************************************************/
void xtensa_irq_initialize(void)
void up_irqinitialize(void)
{
/* Initialize CPU interrupts */

4
arch/z16/src/common/up_initialize.c
View file

@ -105,10 +105,6 @@ void up_initialize(void)
up_addregion();
#endif
/* Initialize the interrupt subsystem */
up_irqinitialize();
#if !defined(CONFIG_SUPPRESS_INTERRUPTS) && !defined(CONFIG_SUPPRESS_TIMER_INTS)
/* Initialize the system timer interrupt */

1
arch/z16/src/common/up_internal.h
View file

@ -135,7 +135,6 @@ extern volatile FAR chipreg_t *g_current_regs;
void up_copystate(FAR chipreg_t *dest, FAR chipreg_t *src);
FAR chipreg_t *up_doirq(int irq, FAR chipreg_t *regs);
void up_restoreusercontext(FAR chipreg_t *regs);
void up_irqinitialize(void);
int up_saveusercontext(FAR chipreg_t *regs);
void up_sigdeliver(void);

10
arch/z80/src/common/up_initialize.c
View file

@ -96,16 +96,6 @@ void up_initialize(void)
up_addregion();
#endif
/* Initialize the interrupt subsystem */
z80_irq_initialize();
#ifdef CONFIG_RTC_ALARM
/* Enable RTC alarm interrupts */
z80_rtc_irqinitialize();
#endif
#if !defined(CONFIG_SUPPRESS_INTERRUPTS) && !defined(CONFIG_SUPPRESS_TIMER_INTS)
/* Initialize the system timer interrupt */

8
arch/z80/src/common/z80_internal.h
View file

@ -104,14 +104,6 @@ extern "C"
{
#endif
/* Supplied by chip- or board-specific logic */
void z80_irq_initialize(void);
#ifdef CONFIG_RTC_ALARM
void z80_rtc_irqinitialize(void);
#endif
#ifdef USE_LOWSERIALINIT
void z80_lowserial_initialize(void);
#endif

4
arch/z80/src/ez80/ez80_irq.c
View file

@ -60,10 +60,10 @@ volatile chipreg_t *g_current_regs;
****************************************************************************/
/****************************************************************************
* Name: z80_irq_initialize
* Name: up_irqinitialize
****************************************************************************/
void z80_irq_initialize(void)
void up_irqinitialize(void)
{
g_current_regs = NULL;

26
arch/z80/src/ez80/ez80_rtc.c
View file

@ -446,33 +446,15 @@ int up_rtc_initialize(void)
outp(EZ80_RTC_CTRL, regval);
#ifdef CONFIG_RTC_ALARM
irq_attach(EZ80_RTC_IRQ, ez80_alarm_interrupt, NULL);
#endif
rtc_dumpregs("After Initialization");
g_rtc_enabled = true;
return OK;
}
/****************************************************************************
* Name: z80_rtc_irqinitialize
*
* Description:
* Initialize IRQs for RTC, not possible during up_rtc_initialize because
* z80_irq_initialize is called later.
*
* Input Parameters:
* None
*
* Returned Value:
* Zero (OK) on success; a negated errno on failure
*
****************************************************************************/
#ifdef CONFIG_RTC_ALARM
int z80_rtc_irqinitialize(void)
{
return irq_attach(EZ80_RTC_IRQ, ez80_alarm_interrupt, NULL);
}
#endif
/****************************************************************************
* Name: up_rtc_getdatetime
*

4
arch/z80/src/z180/z180_irq.c
View file

@ -160,14 +160,14 @@ irqstate_t up_irq_enable(void) __naked
}
/****************************************************************************
* Name: z80_irq_initialize
* Name: up_irqinitialize
*
* Description:
* Initialize and enable interrupts
*
****************************************************************************/
void z80_irq_initialize(void)
void up_irqinitialize(void)
{
uint16_t vectaddr = (uint16_t)up_vectors;
uint8_t regval;

4
arch/z80/src/z8/z8_irq.c
View file

@ -60,10 +60,10 @@ struct z8_irqstate_s g_z8irqstate;
****************************************************************************/
/****************************************************************************
* Name: z80_irq_initialize
* Name: up_irqinitialize
****************************************************************************/
void z80_irq_initialize(void)
void up_irqinitialize(void)
{
/* Clear and disable all interrupts. Set all to priority 0. */

4
boards/z80/z80/z80sim/src/z80_irq.c
View file

@ -55,10 +55,10 @@ int z80sim_timerisr(int irq, FAR chipreg_t *regs);
****************************************************************************/
/****************************************************************************
* Name: z80_irq_initialize
* Name: up_irqinitialize
****************************************************************************/
void z80_irq_initialize(void)
void up_irqinitialize(void)
{
/* Attach the timer interrupt -- There is not special timer interrupt
* enable in the simulation so it must be enabled here before interrupts

2
boards/z80/z80/z80sim/src/z80_timerisr.c
View file

@ -78,7 +78,7 @@ int z80sim_timerisr(int irq, FAR chipreg_t *regs, void *arg)
void z80_timer_initialize(void)
{
/* The timer interrupt was attached in z80_irq_initialize -- see comments
/* The timer interrupt was attached in up_irqinitialize -- see comments
* there.
*/
}

6
include/nuttx/arch.h
View file

@ -1331,6 +1331,12 @@ int up_shmdt(uintptr_t vaddr, unsigned int npages);
/* See prototype in include/nuttx/elf.h */
/****************************************************************************
* Name: up_irqinitialize
****************************************************************************/
void up_irqinitialize(void);
/****************************************************************************
* Name: up_interrupt_context
*

2
sched/irq/irq_initialize.c
View file

@ -106,4 +106,6 @@ void irq_initialize(void)
irqchain_initialize();
#endif
up_irqinitialize();
}