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Sources and Docs: Fix typos and nxstyle issues

Browse source 
Documentation/contributing/coding_style.rst:

    * Fix repeated words: ("this this").
    * Remove trailing spaces.

boards/z80/z80/z80sim/README.txt:

    * Fix repeated words: ("this this") and rewrap lines.

graphics/Kconfig,
libs/libc/math/Kconfig:

    * Fix repeated words: ("this this").

arch/arm/src/armv7-a/arm_assert.c,
arch/arm/src/armv7-r/arm_assert.c,
arch/arm/src/imxrt/imxrt_enet.c,
arch/arm/src/kinetis/kinetis_enet.c,
arch/arm/src/kinetis/kinetis_flexcan.c,
arch/arm/src/s32k1xx/s32k1xx_enet.c,
arch/arm/src/s32k1xx/s32k1xx_flexcan.c,
arch/arm/src/stm32/stm32_pwm.c,
arch/arm/src/stm32h7/stm32_pwm.c,
arch/arm/src/stm32l4/stm32l4_pwm.c,
arch/renesas/src/rx65n/rx65n_usbdev.c,
binfmt/libnxflat/libnxflat_bind.c,
drivers/pipes/pipe_common.c,
net/igmp/igmp_input.c,
net/tcp/tcp_conn.c,
sched/sched/sched_roundrobin.c:

    * Fix typo in comment ("this this").

arch/arm/src/cxd56xx/cxd56_usbdev.c,
arch/arm/src/lc823450/lc823450_usbdev.c:

    * Fix typo in comment and rewrap lines.

arch/arm/src/imxrt/imxrt_usbdev.c,
arch/arm/src/stm32/stm32_dac.c,
arch/arm/src/stm32f0l0g0/stm32_pwm.c,
arch/arm/src/stm32f7/stm32_pwm.c,
arch/arm/src/tiva/lm/lm4f_gpio.h,
fs/nxffs/nxffs_write.c,
include/nuttx/analog/pga11x.h,
include/nuttx/usb/usbdev.h,
net/mld/mld_join.c:

    * Fix typo in comment ("this this").
    * Fix nxstyle issues.
This commit is contained in:
Nathan Hartman 2020-10-01 19:29:35 -04:00 committed by Alin Jerpelea
parent 3f461f59ba
commit 80ce7800a9
31 changed files with 413 additions and 335 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

4
Documentation/contributing/coding_style.rst
View file

@ -1209,8 +1209,8 @@ Structures
structure may be another structure that is defined only with the
scope of the containing structure. This practice is acceptable, but
discouraged.
- **No un-named structure fields**. Structure may contain other
structures as fields. This this case, the structure field must be
- **No un-named structure fields**. Structures may contain other
structures as fields. In this case, the structure field must be
named. C11 permits such un-named structure fields within a structure.
NuttX generally follows C89 and all code outside of architecture
specific directories must be compatible with C89.

2
arch/arm/src/armv7-a/arm_assert.c
View file

@ -247,7 +247,7 @@ static void up_dumpstate(void)
#endif
#ifdef CONFIG_ARCH_KERNEL_STACK
/* This this thread have a kernel stack allocated? */
/* Does this thread have a kernel stack allocated? */
if (rtcb->xcp.kstack)
{

2
arch/arm/src/armv7-r/arm_assert.c
View file

@ -240,7 +240,7 @@ static void up_dumpstate(void)
#endif
#ifdef CONFIG_ARCH_KERNEL_STACK
/* This this thread have a kernel stack allocated? */
/* Does this thread have a kernel stack allocated? */
if (rtcb->xcp.kstack)
{

6
arch/arm/src/cxd56xx/cxd56_usbdev.c
View file

@ -2203,9 +2203,9 @@ static void cxd56_usbdevreset(FAR struct cxd56_usbdev_s *priv)
* Input Parameters:
* ep - the struct usbdev_ep_s instance obtained from allocep()
* desc - A struct usb_epdesc_s instance describing the endpoint
* last - true if this this last endpoint to be configured. Some hardware
* needs to take special action when all of the endpoints have been
* configured.
* last - true if this is the last endpoint to be configured. Some
* hardware needs to take special action when all of the endpoints
* have been configured.
*
****************************************************************************/

2
arch/arm/src/imxrt/imxrt_enet.c
View file

@ -1090,7 +1090,7 @@ static void imxrt_enet_interrupt_work(FAR void *arg)
* Function: imxrt_enet_interrupt
*
* Description:
* Three interrupt sources will vector this this function:
* Three interrupt sources will vector to this function:
* 1. Ethernet MAC transmit interrupt handler
* 2. Ethernet MAC receive interrupt handler
* 3.

46
arch/arm/src/imxrt/imxrt_usbdev.c
View file

@ -257,7 +257,9 @@ struct imxrt_dtd_s
#define DTD_CONFIG_BUFFER_ERROR (1 << 5) /* Bit 6 : Status Buffer Error */
#define DTD_CONFIG_TRANSACTION_ERROR (1 << 3) /* Bit 3 : Status Transaction Error */
/* This represents a queue head - not these must be aligned to a 2048 byte boundary */
/* This represents a queue head - not these must be aligned to a 2048 byte
* boundary
*/
struct imxrt_dqh_s
{
@ -313,7 +315,9 @@ struct imxrt_dqh_s
#define IMXRT_INTRMAXPACKET (1024) /* Interrupt endpoint max packet (1 to 1024) */
#define IMXRT_ISOCMAXPACKET (512) /* Acutally 1..1023 */
/* Endpoint bit position in SETUPSTAT, PRIME, FLUSH, STAT, COMPLETE registers */
/* Endpoint bit position in SETUPSTAT, PRIME, FLUSH, STAT, COMPLETE
* registers
*/
#define IMXRT_ENDPTSHIFT(epphy) (IMXRT_EPPHYIN(epphy) ? (16 + ((epphy) >> 1)) : ((epphy) >> 1))
#define IMXRT_ENDPTMASK(epphy) (1 << IMXRT_ENDPTSHIFT(epphy))
@ -1180,7 +1184,9 @@ static void imxrt_usbreset(struct imxrt_usbdev_s *priv)
imxrt_putreg (imxrt_getreg(IMXRT_USBDEV_ENDPTCOMPLETE),
IMXRT_USBDEV_ENDPTCOMPLETE);
/* Wait for all prime operations to have completed and then flush all DTDs */
/* Wait for all prime operations to have completed and then flush all
* DTDs
*/
while (imxrt_getreg (IMXRT_USBDEV_ENDPTPRIME) != 0)
;
@ -1857,13 +1863,17 @@ bool imxrt_epcomplete(struct imxrt_usbdev_s *priv, uint8_t epphy)
bool complete = true;
if (IMXRT_EPPHYOUT(privep->epphy))
{
/* read(OUT) completes when request filled, or a short transfer is received */
/* read(OUT) completes when request filled, or a short transfer is
* received
*/
usbtrace(TRACE_INTDECODE(IMXRT_TRACEINTID_EPIN), complete);
}
else
{
/* write(IN) completes when request finished, unless we need to terminate with a ZLP */
/* write(IN) completes when request finished, unless we need to
* terminate with a ZLP
*/
bool need_zlp = (xfrd == privep->ep.maxpacket) &&
((privreq->req.flags & USBDEV_REQFLAGS_NULLPKT) != 0);
@ -1873,7 +1883,9 @@ bool imxrt_epcomplete(struct imxrt_usbdev_s *priv, uint8_t epphy)
usbtrace(TRACE_INTDECODE(IMXRT_TRACEINTID_EPOUT), complete);
}
/* If the transfer is complete, then dequeue and progress any further queued requests */
/* If the transfer is complete, then dequeue and progress any further
* queued requests
*/
if (complete)
{
@ -1885,7 +1897,9 @@ bool imxrt_epcomplete(struct imxrt_usbdev_s *priv, uint8_t epphy)
imxrt_progressep(privep);
}
/* Now it's safe to call the completion callback as it may well submit a new request */
/* Now it's safe to call the completion callback as it may well submit a
* new request
*/
if (complete)
{
@ -2049,7 +2063,9 @@ static int imxrt_usbinterrupt(int irq, FAR void *context, FAR void *arg)
uint32_t setupstat = imxrt_getreg(IMXRT_USBDEV_ENDPTSETUPSTAT);
if (setupstat)
{
/* Clear the endpoint complete CTRL OUT and IN when a Setup is received */
/* Clear the endpoint complete CTRL OUT and IN when a Setup is
* received
*/
imxrt_putreg(IMXRT_ENDPTMASK(IMXRT_EP0_IN) |
IMXRT_ENDPTMASK(IMXRT_EP0_OUT),
@ -2105,9 +2121,9 @@ static int imxrt_usbinterrupt(int irq, FAR void *context, FAR void *arg)
* Input Parameters:
* ep - the struct usbdev_ep_s instance obtained from allocep()
* desc - A struct usb_epdesc_s instance describing the endpoint
* last - true if this this last endpoint to be configured. Some hardware
* needs to take special action when all of the endpoints have been
* configured.
* last - true if this is the last endpoint to be configured. Some
* hardware needs to take special action when all of the endpoints
* have been configured.
*
****************************************************************************/
@ -2623,7 +2639,9 @@ static FAR struct usbdev_ep_s *imxrt_allocep(FAR struct usbdev_s *dev,
epset &= priv->epavail;
if (epset)
{
/* Select the lowest bit in the set of matching, available endpoints */
/* Select the lowest bit in the set of matching, available
* endpoints
*/
for (epndx = 2; epndx < IMXRT_NPHYSENDPOINTS; epndx++)
{
@ -2635,7 +2653,9 @@ static FAR struct usbdev_ep_s *imxrt_allocep(FAR struct usbdev_s *dev,
priv->epavail &= ~bit;
leave_critical_section(flags);
/* And return the pointer to the standard endpoint structure */
/* And return the pointer to the standard endpoint
* structure
*/
return &priv->eplist[epndx].ep;
}

2
arch/arm/src/kinetis/kinetis_enet.c
View file

@ -940,7 +940,7 @@ static void kinetis_interrupt_work(FAR void *arg)
* Function: kinetis_interrupt
*
* Description:
* Three interrupt sources will vector this this function:
* Three interrupt sources will vector to this function:
* 1. Ethernet MAC transmit interrupt handler
* 2. Ethernet MAC receive interrupt handler
* 3.

2
arch/arm/src/kinetis/kinetis_flexcan.c
View file

@ -1023,7 +1023,7 @@ static void kinetis_txdone(FAR void *arg)
* Function: kinetis_flexcan_interrupt
*
* Description:
* Three interrupt sources will vector this this function:
* Three interrupt sources will vector to this function:
* 1. CAN MB transmit interrupt handler
* 2. CAN MB receive interrupt handler
* 3.

6
arch/arm/src/lc823450/lc823450_usbdev.c
View file

@ -385,9 +385,9 @@ static void epcmd_write(int epnum, uint32_t val)
* Input Parameters:
* ep - the struct usbdev_ep_s instance obtained from allocep()
* desc - A struct usb_epdesc_s instance describing the endpoint
* last - true if this this last endpoint to be configured. Some hardware
* needs to take special action when all of the endpoints have been
* configured.
* last - true if this is the last endpoint to be configured. Some
* hardware needs to take special action when all of the endpoints
* have been configured.
*
****************************************************************************/

2
arch/arm/src/s32k1xx/s32k1xx_enet.c
View file

@ -1099,7 +1099,7 @@ static void s32k1xx_enet_interrupt_work(FAR void *arg)
* Function: s32k1xx_enet_interrupt
*
* Description:
* Three interrupt sources will vector this this function:
* Three interrupt sources will vector to this function:
* 1. Ethernet MAC transmit interrupt handler
* 2. Ethernet MAC receive interrupt handler
* 3.

2
arch/arm/src/s32k1xx/s32k1xx_flexcan.c
View file

@ -1024,7 +1024,7 @@ static void s32k1xx_txdone(FAR void *arg)
* Function: s32k1xx_flexcan_interrupt
*
* Description:
* Three interrupt sources will vector this this function:
* Three interrupt sources will vector to this function:
* 1. CAN MB transmit interrupt handler
* 2. CAN MB receive interrupt handler
* 3.

45
arch/arm/src/stm32/stm32_dac.c
View file

@ -1,4 +1,4 @@
/************************************************************************************
/****************************************************************************
* arch/arm/src/stm32/stm32_dac.c
*
* Copyright (C) 2011, 2013, 2016 Gregory Nutt. All rights reserved.
@ -32,7 +32,7 @@
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
****************************************************************************/
/****************************************************************************
* Included Files
@ -68,13 +68,16 @@
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Configuration ************************************************************/
/* Up to 2 DAC interfaces for up to 3 channels are supported
*
* NOTE: STM32_NDAC tells how many channels chip supports.
* ST is not consistent in the naming of DAC interfaces, so we introduce
* our own naming convention. We distinguish DAC1 and DAC2 only if the chip
* has two separate areas in memory map to support DAC channels.
* ST is not consistent in the naming of DAC interfaces, so we
* introduce our own naming convention. We distinguish DAC1 and DAC2
* only if the chip has two separate areas in memory map to support DAC
* channels.
*/
#if STM32_NDAC < 3
@ -205,7 +208,8 @@
# endif
#endif
/* DMA *********************************************************************/
/* DMA **********************************************************************/
/* DMA channels and interface values differ for the F1 and F4 families */
#undef HAVE_DMA
@ -485,8 +489,7 @@
# define DAC2CH1_TSEL_VALUE DAC_CR_TSEL_SW
#endif
/*
* We need index which describes when HRTIM is selected as trigger.
/* We need index which describes when HRTIM is selected as trigger.
* It will be used to skip timer configuration where needed.
*/
@ -534,7 +537,9 @@
* Private Types
****************************************************************************/
/* This structure represents the internal state of the single STM32 DAC block */
/* This structure represents the internal state of the single STM32 DAC
* block
*/
struct stm32_dac_s
{
@ -571,6 +576,7 @@ struct stm32_chan_s
/****************************************************************************
* Private Function Prototypes
****************************************************************************/
/* DAC Register access */
#ifdef HAVE_TIMER
@ -603,7 +609,7 @@ static int dac_ioctl(FAR struct dac_dev_s *dev, int cmd, unsigned long arg);
static int dac_timinit(FAR struct stm32_chan_s *chan);
# endif
static int dma_remap(FAR struct stm32_chan_s *chan);
static void dma_bufferinit(FAR struct stm32_chan_s *chan, uint16_t* buffer,
static void dma_bufferinit(FAR struct stm32_chan_s *chan, uint16_t *buffer,
uint16_t len);
#endif
static int dac_chaninit(FAR struct stm32_chan_s *chan);
@ -917,8 +923,8 @@ static void dac_reset(FAR struct dac_dev_s *dev)
* Description:
* Configure the DAC. This method is called the first time that the DAC
* device is opened. This will occur when the port is first opened.
* This setup includes configuring and attaching DAC interrupts. Interrupts
* are all disabled upon return.
* This setup includes configuring and attaching DAC interrupts.
* Interrupts are all disabled upon return.
*
* Input Parameters:
*
@ -1015,7 +1021,7 @@ static int dac_send(FAR struct dac_dev_s *dev, FAR struct dac_msg_s *msg)
if (chan->intf > 0)
{
stm32_dac_modify_cr(chan, 0, DAC_CR_EN|DAC_CR_BOFF);
stm32_dac_modify_cr(chan, 0, DAC_CR_EN | DAC_CR_BOFF);
}
else
#endif
@ -1070,6 +1076,7 @@ static int dac_send(FAR struct dac_dev_s *dev, FAR struct dac_msg_s *msg)
tim_modifyreg(chan, STM32_BTIM_EGR_OFFSET, 0, ATIM_EGR_UG);
}
#endif
return OK;
}
@ -1125,7 +1132,7 @@ static int dac_ioctl(FAR struct dac_dev_s *dev, int cmd, unsigned long arg)
* Name: dma_bufferinit
****************************************************************************/
static void dma_bufferinit(FAR struct stm32_chan_s *chan, uint16_t* buffer,
static void dma_bufferinit(FAR struct stm32_chan_s *chan, uint16_t *buffer,
uint16_t len)
{
memcpy(chan->dmabuffer, buffer, len);
@ -1289,8 +1296,8 @@ static int dac_timinit(FAR struct stm32_chan_s *chan)
modifyreg32(regaddr, 0, setbits);
/* Calculate optimal values for the timer prescaler and for the timer reload
* register. If 'frequency' is the desired frequency, then
/* Calculate optimal values for the timer prescaler and for the timer
* reload register. If 'frequency' is the desired frequency, then
*
* reload = timclk / frequency
* timclk = pclk / presc
@ -1299,8 +1306,8 @@ static int dac_timinit(FAR struct stm32_chan_s *chan)
*
* reload = pclk / presc / frequency
*
* There are many solutions to this this, but the best solution will be the
* one that has the largest reload value and the smallest prescaler value.
* There are many solutions to this, but the best solution will be the one
* that has the largest reload value and the smallest prescaler value.
* That is the solution that should give us the most accuracy in the timer
* control. Subject to:
*
@ -1439,7 +1446,7 @@ static int dac_chaninit(FAR struct stm32_chan_s *chan)
if (chan->hasdma)
{
/* Remap DMA request if necessary*/
/* Remap DMA request if necessary */
dma_remap(chan);

4
arch/arm/src/stm32/stm32_pwm.c
View file

@ -2369,8 +2369,8 @@ static int pwm_frequency_update(FAR struct pwm_lowerhalf_s *dev,
*
* reload = pclk / presc / frequency
*
* There are many solutions to this this, but the best solution will be the
* one that has the largest reload value and the smallest prescaler value.
* There are many solutions to this, but the best solution will be the one
* that has the largest reload value and the smallest prescaler value.
* That is the solution that should give us the most accuracy in the timer
* control. Subject to:
*

69
arch/arm/src/stm32f0l0g0/stm32_pwm.c
View file

@ -198,12 +198,14 @@ struct stm32_pwmtimer_s
static uint32_t stm32pwm_getreg(struct stm32_pwmtimer_s *priv, int offset);
static void stm32pwm_putreg(struct stm32_pwmtimer_s *priv, int offset,
uint32_t value);
static void stm32pwm_modifyreg(struct stm32_pwmtimer_s *priv, uint32_t offset,
uint32_t clearbits, uint32_t setbits);
uint32_t value);
static void stm32pwm_modifyreg(struct stm32_pwmtimer_s *priv,
uint32_t offset, uint32_t clearbits,
uint32_t setbits);
#ifdef CONFIG_DEBUG_PWM_INFO
static void stm32pwm_dumpregs(struct stm32_pwmtimer_s *priv, const char *msg);
static void stm32pwm_dumpregs(struct stm32_pwmtimer_s *priv,
const char *msg);
#else
# define stm32pwm_dumpregs(priv,msg)
#endif
@ -680,8 +682,9 @@ static void stm32pwm_putreg(struct stm32_pwmtimer_s *priv, int offset,
*
****************************************************************************/
static void stm32pwm_modifyreg(struct stm32_pwmtimer_s *priv, uint32_t offset,
uint32_t clearbits, uint32_t setbits)
static void stm32pwm_modifyreg(struct stm32_pwmtimer_s *priv,
uint32_t offset, uint32_t clearbits,
uint32_t setbits)
{
if (stm32pwm_reg_is_32bit(priv->timtype, offset) == true)
{
@ -790,7 +793,9 @@ static int stm32pwm_output_configure(FAR struct stm32_pwmtimer_s *priv,
cr2 = stm32pwm_getreg(priv, STM32_GTIM_CR2_OFFSET);
ccer = stm32pwm_getreg(priv, STM32_GTIM_CCER_OFFSET);
/* Reset the output polarity level of all channels (selects high polarity) */
/* Reset the output polarity level of all channels (selects high
* polarity)
*/
ccer &= ~(GTIM_CCER_CC1P << ((channel - 1) * 4));
@ -799,13 +804,14 @@ static int stm32pwm_output_configure(FAR struct stm32_pwmtimer_s *priv,
ccer |= (GTIM_CCER_CC1E << ((channel - 1) * 4));
#ifdef HAVE_ADVTIM
if (priv->timtype == TIMTYPE_ADVANCED || priv->timtype == TIMTYPE_COUNTUP16_N)
if (priv->timtype == TIMTYPE_ADVANCED ||
priv->timtype == TIMTYPE_COUNTUP16_N)
{
cr2 &= ~(ATIM_CR2_OIS1 << ((channel - 1) * 2));
}
#ifdef HAVE_PWM_COMPLEMENTARY
/* Verify if the current complementary channel is defined*/
/* Verify if the current complementary channel is defined */
if (priv->channels[channel - 1].npincfg != 0)
{
@ -889,7 +895,8 @@ static int stm32pwm_timer(FAR struct stm32_pwmtimer_s *priv,
info->duty, info->count);
#else
pwminfo("TIM%u channel: %u frequency: %u duty: %08x\n",
priv->timid, priv->channels[0].channel, info->frequency, info->duty);
priv->timid, priv->channels[0].channel, info->frequency,
info->duty);
#endif
DEBUGASSERT(info->frequency > 0);
@ -904,8 +911,8 @@ static int stm32pwm_timer(FAR struct stm32_pwmtimer_s *priv,
stm32pwm_putreg(priv, STM32_GTIM_SR_OFFSET, 0);
#endif
/* Calculate optimal values for the timer prescaler and for the timer reload
* register. If 'frequency' is the desired frequency, then
/* Calculate optimal values for the timer prescaler and for the timer
* reload register. If 'frequency' is the desired frequency, then
*
* reload = timclk / frequency
* timclk = pclk / presc
@ -914,7 +921,7 @@ static int stm32pwm_timer(FAR struct stm32_pwmtimer_s *priv,
*
* reload = pclk / presc / frequency
*
* There are many solutions to this this, but the best solution will be the
* There are many solutions to this, but the best solution will be the
* one that has the largest reload value and the smallest prescaler value.
* That is the solution that should give us the most accuracy in the timer
* control. Subject to:
@ -951,13 +958,14 @@ static int stm32pwm_timer(FAR struct stm32_pwmtimer_s *priv,
reload = timclk / info->frequency;
/* In center-aligned mode, the timer performs upcounting from zero to ARR value
* and then performs downcounting from ARR to zero and repeat. In other words,
* in one cycle the timer counts 2*ARR. For that reason, the reload (ARR) value
* is divided by 2.
/* In center-aligned mode, the timer performs upcounting from zero to ARR
* value and then performs downcounting from ARR to zero and repeat. In
* other words, in one cycle the timer counts 2*ARR. For that reason, the
* reload (ARR) value is divided by 2.
*/
if (priv->mode == STM32_TIMMODE_CENTER1 || priv->mode == STM32_TIMMODE_CENTER2 ||
if (priv->mode == STM32_TIMMODE_CENTER1 ||
priv->mode == STM32_TIMMODE_CENTER2 ||
priv->mode == STM32_TIMMODE_CENTER3)
{
reload /= 2;
@ -976,8 +984,10 @@ static int stm32pwm_timer(FAR struct stm32_pwmtimer_s *priv,
reload--;
}
pwminfo("TIM%u PCLK: %u frequency: %u TIMCLK: %u prescaler: %u reload: %u\n",
priv->timid, priv->pclk, info->frequency, timclk, prescaler, reload);
pwminfo("TIM%u PCLK: %u frequency: %u "
"TIMCLK: %u prescaler: %u reload: %u\n",
priv->timid, priv->pclk, info->frequency, timclk,
prescaler, reload);
/* Set up the timer CR1 register:
*
@ -1040,7 +1050,8 @@ static int stm32pwm_timer(FAR struct stm32_pwmtimer_s *priv,
break;
default:
pwmerr("ERROR: No such timer mode: %u\n", (unsigned int)priv->mode);
pwmerr("ERROR: No such timer mode: %u\n",
(unsigned int)priv->mode);
return -EINVAL;
}
}
@ -1224,7 +1235,8 @@ static int stm32pwm_timer(FAR struct stm32_pwmtimer_s *priv,
/* Set the CCMR1 mode values (leave CCMR2 zero) */
ocmode1 |= (ATIM_CCMR_CCS_CCOUT << ATIM_CCMR1_CC1S_SHIFT) |
(chanmode << ATIM_CCMR1_OC1M_SHIFT) | ATIM_CCMR1_OC1PE;
(chanmode << ATIM_CCMR1_OC1M_SHIFT) |
ATIM_CCMR1_OC1PE;
if (ocmbit)
{
@ -1252,7 +1264,8 @@ static int stm32pwm_timer(FAR struct stm32_pwmtimer_s *priv,
/* Set the CCMR1 mode values (leave CCMR2 zero) */
ocmode1 |= (ATIM_CCMR_CCS_CCOUT << ATIM_CCMR1_CC2S_SHIFT) |
(chanmode << ATIM_CCMR1_OC2M_SHIFT) | ATIM_CCMR1_OC2PE;
(chanmode << ATIM_CCMR1_OC2M_SHIFT) |
ATIM_CCMR1_OC2PE;
if (ocmbit)
{
@ -1348,7 +1361,8 @@ static int stm32pwm_timer(FAR struct stm32_pwmtimer_s *priv,
/* Special configuration for HAVE_ADVTIM */
#ifdef HAVE_ADVTIM
if (priv->timtype == TIMTYPE_ADVANCED || priv->timtype == TIMTYPE_COUNTUP16_N)
if (priv->timtype == TIMTYPE_ADVANCED ||
priv->timtype == TIMTYPE_COUNTUP16_N)
{
uint32_t bdtr;
@ -1577,7 +1591,9 @@ static int stm32pwm_interrupt(struct stm32_pwmtimer_s *priv)
stm32pwm_putreg(priv, STM32_ATIM_RCR_OFFSET, priv->curr - 1);
}
/* Now all of the time critical stuff is done so we can do some debug output */
/* Now all of the time critical stuff is done so we can do some debug
* output
*/
pwminfo("Update interrupt SR: %04x prev: %u curr: %u count: %u\n",
regval, priv->prev, priv->curr, priv->count);
@ -1936,7 +1952,8 @@ static int stm32pwm_start(FAR struct pwm_lowerhalf_s *dev,
}
}
#else
ret = stm32pwm_update_duty(priv, priv->channels[0].channel, info->duty);
ret = stm32pwm_update_duty(priv, priv->channels[0].channel,
info->duty);
#endif
}
else

51
arch/arm/src/stm32f7/stm32_pwm.c
View file

@ -231,10 +231,12 @@ struct stm32_pwmtimer_s
/****************************************************************************
* Static Function Prototypes
****************************************************************************/
/* Register access */
static uint16_t pwm_getreg(struct stm32_pwmtimer_s *priv, int offset);
static void pwm_putreg(struct stm32_pwmtimer_s *priv, int offset, uint16_t value);
static void pwm_putreg(struct stm32_pwmtimer_s *priv, int offset,
uint16_t value);
#ifdef CONFIG_DEBUG_PWM_INFO
static void pwm_dumpregs(struct stm32_pwmtimer_s *priv, FAR const char *msg);
@ -1032,7 +1034,7 @@ static void pwm_dumpregs(struct stm32_pwmtimer_s *priv, FAR const char *msg)
pwm_getreg(priv, STM32_GTIM_EGR_OFFSET),
pwm_getreg(priv, STM32_GTIM_CCMR1_OFFSET));
}
else
else
{
pwminfo(" SR: %04x EGR: %04x CCMR1: %04x CCMR2: %04x\n",
pwm_getreg(priv, STM32_GTIM_SR_OFFSET),
@ -1148,8 +1150,8 @@ static int pwm_timer(FAR struct stm32_pwmtimer_s *priv,
pwm_putreg(priv, STM32_GTIM_SR_OFFSET, 0);
#endif
/* Calculate optimal values for the timer prescaler and for the timer reload
* register. If 'frequency' is the desired frequency, then
/* Calculate optimal values for the timer prescaler and for the timer
* reload register. If 'frequency' is the desired frequency, then
*
* reload = timclk / frequency
* timclk = pclk / presc
@ -1158,8 +1160,8 @@ static int pwm_timer(FAR struct stm32_pwmtimer_s *priv,
*
* reload = pclk / presc / frequency
*
* There are many solutions to this this, but the best solution will be the
* one that has the largest reload value and the smallest prescaler value.
* There are many solutions to this, but the best solution will be the one
* that has the largest reload value and the smallest prescaler value.
* That is the solution that should give us the most accuracy in the timer
* control. Subject to:
*
@ -1207,8 +1209,10 @@ static int pwm_timer(FAR struct stm32_pwmtimer_s *priv,
reload--;
}
pwminfo("TIM%u PCLK: %u frequency: %u TIMCLK: %u prescaler: %u reload: %u\n",
priv->timid, priv->pclk, info->frequency, timclk, prescaler, reload);
pwminfo("TIM%u PCLK: %u frequency: %u "
"TIMCLK: %u prescaler: %u reload: %u\n",
priv->timid, priv->pclk, info->frequency,
timclk, prescaler, reload);
/* Set up the timer CR1 register:
*
@ -1440,7 +1444,9 @@ static int pwm_timer(FAR struct stm32_pwmtimer_s *priv,
(chanmode << ATIM_CCMR1_OC1M_SHIFT) |
ATIM_CCMR1_OC1PE;
/* Set the duty cycle by writing to the CCR register for this channel */
/* Set the duty cycle by writing to the CCR register for this
* channel
*/
pwm_putreg(priv, STM32_GTIM_CCR1_OFFSET, (uint16_t)ccr);
}
@ -1458,7 +1464,9 @@ static int pwm_timer(FAR struct stm32_pwmtimer_s *priv,
(chanmode << ATIM_CCMR1_OC2M_SHIFT) |
ATIM_CCMR1_OC2PE;
/* Set the duty cycle by writing to the CCR register for this channel */
/* Set the duty cycle by writing to the CCR register for this
* channel
*/
pwm_putreg(priv, STM32_GTIM_CCR2_OFFSET, (uint16_t)ccr);
}
@ -1476,7 +1484,9 @@ static int pwm_timer(FAR struct stm32_pwmtimer_s *priv,
(chanmode << ATIM_CCMR2_OC3M_SHIFT) |
ATIM_CCMR2_OC3PE;
/* Set the duty cycle by writing to the CCR register for this channel */
/* Set the duty cycle by writing to the CCR register for this
* channel
*/
pwm_putreg(priv, STM32_GTIM_CCR3_OFFSET, (uint16_t)ccr);
}
@ -1494,7 +1504,9 @@ static int pwm_timer(FAR struct stm32_pwmtimer_s *priv,
(chanmode << ATIM_CCMR2_OC4M_SHIFT) |
ATIM_CCMR2_OC4PE;
/* Set the duty cycle by writing to the CCR register for this channel */
/* Set the duty cycle by writing to the CCR register for this
* channel
*/
pwm_putreg(priv, STM32_GTIM_CCR4_OFFSET, (uint16_t)ccr);
}
@ -1518,7 +1530,9 @@ static int pwm_timer(FAR struct stm32_pwmtimer_s *priv,
ccmr1 = pwm_getreg(priv, STM32_GTIM_CCMR1_OFFSET);
ccmr2 = pwm_getreg(priv, STM32_GTIM_CCMR2_OFFSET);
/* Reset the Output Compare Mode Bits and set the select output compare mode */
/* Reset the Output Compare Mode Bits and set the select output compare
* mode
*/
ccmr1 &= ~(ATIM_CCMR1_CC1S_MASK | ATIM_CCMR1_OC1M_MASK | ATIM_CCMR1_OC1PE |
ATIM_CCMR1_CC2S_MASK | ATIM_CCMR1_OC2M_MASK | ATIM_CCMR1_OC2PE);
@ -1527,7 +1541,9 @@ static int pwm_timer(FAR struct stm32_pwmtimer_s *priv,
ccmr1 |= ocmode1;
ccmr2 |= ocmode2;
/* Reset the output polarity level of all channels (selects high polarity) */
/* Reset the output polarity level of all channels (selects high
* polarity)
*/
ccer &= ~(ATIM_CCER_CC1P | ATIM_CCER_CC2P | ATIM_CCER_CC3P |
ATIM_CCER_CC4P);
@ -1543,7 +1559,8 @@ static int pwm_timer(FAR struct stm32_pwmtimer_s *priv,
#if defined(CONFIG_STM32F7_TIM1_PWM) || defined(CONFIG_STM32F7_TIM8_PWM) || \
defined(CONFIG_STM32F7_TIM15_PWM) || defined(CONFIG_STM32F7_TIM16_PWM) || \
defined(CONFIG_STM32F7_TIM17_PWM)
if (priv->timtype == TIMTYPE_ADVANCED || priv->timtype == TIMTYPE_COUNTUP16)
if (priv->timtype == TIMTYPE_ADVANCED ||
priv->timtype == TIMTYPE_COUNTUP16)
{
uint16_t bdtr;
@ -1784,7 +1801,9 @@ static int pwm_interrupt(struct stm32_pwmtimer_s *priv)
pwm_putreg(priv, STM32_ATIM_RCR_OFFSET, (uint16_t)priv->curr - 1);
}
/* Now all of the time critical stuff is done so we can do some debug output */
/* Now all of the time critical stuff is done so we can do some debug
* output
*/
pwminfo("Update interrupt SR: %04x prev: %u curr: %u count: %u\n",
regval, priv->prev, priv->curr, priv->count);

4
arch/arm/src/stm32h7/stm32_pwm.c
View file

@ -2087,8 +2087,8 @@ static int pwm_frequency_update(FAR struct pwm_lowerhalf_s *dev,
*
* reload = pclk / presc / frequency
*
* There are many solutions to this this, but the best solution will be the
* one that has the largest reload value and the smallest prescaler value.
* There are many solutions to this, but the best solution will be the one
* that has the largest reload value and the smallest prescaler value.
* That is the solution that should give us the most accuracy in the timer
* control. Subject to:
*

4
arch/arm/src/stm32l4/stm32l4_pwm.c
View file

@ -1919,8 +1919,8 @@ static int pwm_frequency_update(FAR struct pwm_lowerhalf_s *dev,
*
* reload = pclk / presc / frequency
*
* There are many solutions to this this, but the best solution will be the
* one that has the largest reload value and the smallest prescaler value.
* There are many solutions to this, but the best solution will be the one
* that has the largest reload value and the smallest prescaler value.
* That is the solution that should give us the most accuracy in the timer
* control. Subject to:
*

8
arch/arm/src/tiva/lm/lm4f_gpio.h
View file

@ -129,8 +129,8 @@
*
* FFFS SPPP III. AAAA .... ...V PPPP PBBB
*
* TODO: The LM4F alsso support configuration of pins to trigger ADC and/or uDMA.
* That configuration is not addressed in this this encoding.
* TODO: The LM4F also supports configuration of pins to trigger ADC and/or
* uDMA. That configuration is not addressed in this encoding.
*/
/* These bits set the primary function of the pin:
@ -214,7 +214,9 @@
# define GPIO_ALT_14 (14 << GPIO_ALT_SHIFT)
# define GPIO_ALT_15 (15 << GPIO_ALT_SHIFT)
/* If the pin is an GPIO digital output, then this identifies the initial output value:
/* If the pin is an GPIO digital output, then this identifies the initial
* output value:
*
* .... .... .... .... .... ...V .... ....
*/

6
arch/renesas/src/rx65n/rx65n_usbdev.c
View file

@ -2867,9 +2867,9 @@ void usb_pstd_set_pipe_reg (uint16_t pipe_no, uint16_t pipe_cfgint,
* Input Parameters:
* ep - the struct usbdev_ep_s instance obtained from allocep()
* desc - A struct usb_epdesc_s instance describing the endpoint
* last - true if this this last endpoint to be configured. Some hardware
* needs to take special action when all of the endpoints have been
* configured.
* last - true if this is the last endpoint to be configured. Some
* hardware needs to take special action when all of the endpoints
* have been configured.
*
****************************************************************************/

2
binfmt/libnxflat/libnxflat_bind.c
View file

@ -454,7 +454,7 @@ static inline int nxflat_bindimports(FAR struct nxflat_loadinfo_s *loadinfo,
symname = (FAR char *)
(offset + loadinfo->ispace + sizeof(struct nxflat_hdr_s));
/* Find the exported symbol value for this this symbol name. */
/* Find the exported symbol value for this symbol name. */
#ifdef CONFIG_SYMTAB_ORDEREDBYNAME
symbol = symtab_findorderedbyname(exports, symname, nexports);

10
boards/z80/z80/z80sim/README.txt
View file

@ -116,11 +116,11 @@ tool. To change this configuration using that tool, you should:
Reconfiguring for Windows Native, Cygwin, or macOS
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
All of the z80 configurations in this this directory are set up to build
under Linux. That configuration can be converted to run natively in a
Windows CMD.exe shell. That configuration requires the MinGW host compiler
and several GNUWin32 tools (see discussion in the top-level NuttX/README.txt
file) and the following changes to the configuration file:
All of the z80 configurations in this directory are set up to build under
Linux. That configuration can be converted to run natively in a Windows
CMD.exe shell. That configuration requires the MinGW host compiler and
several GNUWin32 tools (see discussion in the top-level NuttX/README.txt file)
and the following changes to the configuration file:
-CONFIG_HOST_LINUX=y
+CONFIG_HOST_WINDOWS=y

5
drivers/pipes/pipe_common.c
View file

@ -213,9 +213,8 @@ int pipecommon_open(FAR struct file *filep)
{
dev->d_nwriters++;
/* If this this is the first writer, then the read semaphore indicates
* the number of readers waiting for the first writer. Wake them all
* up.
/* If this is the first writer, then the read semaphore indicates the
* number of readers waiting for the first writer. Wake them all up.
*/
if (dev->d_nwriters == 1)

23
fs/nxffs/nxffs_write.c
View file

@ -227,7 +227,9 @@ static inline int nxffs_wralloc(FAR struct nxffs_volume_s *volume,
ret = nxffs_hdrerased(volume, wrfile, mindata);
if (ret == OK)
{
/* Valid memory for the data block was found. Return success. */
/* Valid memory for the data block was found. Return
* success.
*/
return OK;
}
@ -519,7 +521,8 @@ static inline ssize_t nxffs_zappend(FAR struct nxffs_volume_s *volume,
*
****************************************************************************/
ssize_t nxffs_write(FAR struct file *filep, FAR const char *buffer, size_t buflen)
ssize_t nxffs_write(FAR struct file *filep, FAR const char *buffer,
size_t buflen)
{
FAR struct nxffs_volume_s *volume;
FAR struct nxffs_wrfile_s *wrfile;
@ -590,7 +593,9 @@ ssize_t nxffs_write(FAR struct file *filep, FAR const char *buffer, size_t bufle
nxffs_ioseek(volume, wrfile->doffset);
/* Verify that the FLASH data that was previously written is still intact */
/* Verify that the FLASH data that was previously written is still
* intact
*/
ret = nxffs_reverify(volume, wrfile);
if (ret < 0)
@ -606,7 +611,8 @@ ssize_t nxffs_write(FAR struct file *filep, FAR const char *buffer, size_t bufle
nwritten = nxffs_wrappend(volume, wrfile, &buffer[total], remaining);
if (nwritten < 0)
{
ferr("ERROR: Failed to append to FLASH to a data block: %d\n", -ret);
ferr("ERROR: Failed to append to FLASH to a data block: %d\n",
-ret);
goto errout_with_semaphore;
}
@ -684,7 +690,9 @@ int nxffs_wrextend(FAR struct nxffs_volume_s *volume,
nxffs_ioseek(volume, wrfile->doffset);
/* Verify that the FLASH data that was previously written is still intact */
/* Verify that the FLASH data that was previously written is still
* intact
*/
ret = nxffs_reverify(volume, wrfile);
if (ret < 0)
@ -898,7 +906,7 @@ int nxffs_wrverify(FAR struct nxffs_volume_s *volume, size_t size)
if (nerased >= size)
{
/* Yes.. this this is where we will put the object */
/* Yes.. this is where we will put the object */
off_t offset =
volume->ioblock * volume->geo.blocksize + iooffset;
@ -1005,7 +1013,8 @@ int nxffs_wrblkhdr(FAR struct nxffs_volume_s *volume,
* begin the search for the next inode header or data block.
*/
volume->froffset = (wrfile->doffset + wrfile->datlen + SIZEOF_NXFFS_DATA_HDR);
volume->froffset = (wrfile->doffset + wrfile->datlen +
SIZEOF_NXFFS_DATA_HDR);
/* wrfile->file.entry:
* datlen: Total file length accumulated so far. When the file is

12
graphics/Kconfig
View file

@ -20,7 +20,7 @@ config NX_LCDDRIVER
---help---
By default, the NX graphics system uses the frame buffer driver interface
defined in include/nuttx/video/fb.h. However, if LCD is support is enabled,
this this option is provide to select, instead, the LCD driver interface
this option is provided to select, instead, the LCD driver interface
defined in include/nuttx/lcd/lcd.h.
config NX_NDISPLAYS
@ -495,11 +495,11 @@ config NXSTART_EXTERNINIT
select LCD_EXTERNINIT if LCD && LCD_FRAMEBUFFER && NX_LCDDRIVER
---help---
Define to support external display initialization by platform-
specific code. This this option is defined, then nxmu_start()
will call board_graphics_setup(CONFIG_NXSTART_DEVNO) to initialize
the graphics device. This option is necessary if display is used
that cannot be initialized using the standard LCD or framebuffer
interfaces.
specific code. If this option is defined, then nxmu_start()
will call board_graphics_setup(CONFIG_NXSTART_DEVNO) to
initialize the graphics device. This option is necessary if
display is used that cannot be initialized using the standard
LCD or framebuffer interfaces.
config NXSTART_SERVERPRIO
int "NX Server priority"

36
include/nuttx/analog/pga11x.h
View file

@ -53,7 +53,9 @@
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Configuration ************************************************************/
/* Prerequisites:
* CONFIG_ADC=y is needed to enable support for analog input devices
*
@ -86,11 +88,12 @@
#endif
/* PGA11x Commands **********************************************************/
/* Write command Gain Selection Bits (PGA112/PGA113)
*
* the PGA112 and PGA116 provide binary gain selections (1, 2, 4, 8, 16, 32,
* 64, 128); the PGA113 and PGA117 provide scope gain selections (1, 2, 5, 10,
* 20, 50, 100, 200).
* 64, 128); the PGA113 and PGA117 provide scope gain selections (1, 2, 5,
* 10, 20, 50, 100, 200).
*/
#define PGA11X_GAIN_1 (0) /* Gain=1: Scope Gain=1 */
@ -114,17 +117,17 @@
* 10-channel input MUX.
*/
#define PGA11X_CHAN_VCAL (0) /* VCAL/CH0 */
#define PGA11X_CHAN_CH0 (0) /* VCAL/CH0 */
#define PGA11X_CHAN_CH1 (1) /* CH1 */
#define PGA11X_CHAN_CH2 (2) /* CH2 (PGA116/PGA117 only) */
#define PGA11X_CHAN_CH3 (3) /* CH3 (PGA116/PGA117 only) */
#define PGA11X_CHAN_CH4 (4) /* CH4 (PGA116/PGA117 only) */
#define PGA11X_CHAN_CH5 (5) /* CH5 (PGA116/PGA117 only) */
#define PGA11X_CHAN_CH6 (6) /* CH6 (PGA116/PGA117 only) */
#define PGA11X_CHAN_CH7 (7) /* CH7 (PGA116/PGA117 only) */
#define PGA11X_CHAN_CH8 (8) /* CH8 (PGA116/PGA117 only) */
#define PGA11X_CHAN_CH9 (9) /* CH9 (PGA116/PGA117 only) */
#define PGA11X_CHAN_VCAL (0) /* VCAL/CH0 */
#define PGA11X_CHAN_CH0 (0) /* VCAL/CH0 */
#define PGA11X_CHAN_CH1 (1) /* CH1 */
#define PGA11X_CHAN_CH2 (2) /* CH2 (PGA116/PGA117 only) */
#define PGA11X_CHAN_CH3 (3) /* CH3 (PGA116/PGA117 only) */
#define PGA11X_CHAN_CH4 (4) /* CH4 (PGA116/PGA117 only) */
#define PGA11X_CHAN_CH5 (5) /* CH5 (PGA116/PGA117 only) */
#define PGA11X_CHAN_CH6 (6) /* CH6 (PGA116/PGA117 only) */
#define PGA11X_CHAN_CH7 (7) /* CH7 (PGA116/PGA117 only) */
#define PGA11X_CHAN_CH8 (8) /* CH8 (PGA116/PGA117 only) */
#define PGA11X_CHAN_CH9 (9) /* CH9 (PGA116/PGA117 only) */
#define PGA11X_CHAN_CAL1 (12) /* CAL1: connects to GND */
#define PGA11X_CHAN_CAL2 (13) /* CAL2: connects to 0.9VCAL */
#define PGA11X_CHAN_CAL3 (14) /* CAL3: connects to 0.1VCAL */
@ -150,8 +153,8 @@ struct pga11x_usettings_s
/* These structures are used to encode gain and channel settings. This
* includes both devices in the case of a daisy-chained configuration.
* NOTE: This this logic is currently limited to only 2 devices in the
* daisy-chain.
* NOTE: This logic is currently limited to only 2 devices in the daisy-
* chain.
*/
struct pga11x_settings_s
@ -269,7 +272,8 @@ int pga11x_uselect(PGA11X_HANDLE handle, int pos,
*
****************************************************************************/
int pga11x_read(PGA11X_HANDLE handle, FAR struct pga11x_settings_s *settings);
int pga11x_read(PGA11X_HANDLE handle,
FAR struct pga11x_settings_s *settings);
/****************************************************************************
* Name: pga11x_uread

13
include/nuttx/usb/usbdev.h
View file

@ -68,7 +68,7 @@
*
* ep - the struct usbdev_ep_s instance obtained from allocep()
* desc - A struct usb_epdesc_s instance describing the endpoint
* last - true if this this last endpoint to be configured. Some hardware needs
* last - true if this is the last endpoint to be configured. Some hardware needs
* to take special action when all of the endpoints have been configured.
*/
@ -152,6 +152,7 @@
#define DEV_DISCONNECT(dev) (dev)->ops->pullup ? (dev)->ops->pullup(dev,false) : -EOPNOTSUPP
/* USB Class Driver Helpers *********************************************************/
/* All may be called from interrupt handling logic except bind() and unbind() */
/* Invoked when the driver is bound to a USB device driver. */
@ -328,8 +329,8 @@ struct usbdev_ops_s
/* Device-specific I/O command support */
CODE int (*ioctl)(FAR struct usbdev_s *dev, unsigned code,
unsigned long param);
CODE int (*ioctl)(FAR struct usbdev_s *dev, unsigned code,
unsigned long param);
};
struct usbdev_s
@ -380,7 +381,7 @@ extern "C"
#endif
/************************************************************************************
* Public Functions
* Public Function Prototypes
************************************************************************************/
/************************************************************************************
@ -406,7 +407,7 @@ int usbdev_register(FAR struct usbdevclass_driver_s *driver);
int usbdev_unregister(FAR struct usbdevclass_driver_s *driver);
/****************************************************************************
/************************************************************************************
* Name: usbdev_dma_alloc and usbdev_dma_free
*
* Description:
@ -430,7 +431,7 @@ int usbdev_unregister(FAR struct usbdevclass_driver_s *driver);
* does require the size of the allocation to be freed; that would need
* to be managed in the board-specific logic.
*
****************************************************************************/
************************************************************************************/
#if defined(CONFIG_USBDEV_DMA) && defined(CONFIG_USBDEV_DMAMEMORY)
FAR void *usbdev_dma_alloc(size_t size);

2
libs/libc/math/Kconfig
View file

@ -11,7 +11,7 @@ config LIBM
depends on !ARCH_MATH_H
select ARCH_FLOAT_H
---help---
By default, no math library will be provided by NuttX. In this this
By default, no math library will be provided by NuttX. In this
case, it is assumed that (1) no math library is required, or (2) you
will be using the math.h and float.h headers file and the libm
library provided by your toolchain.

2
net/igmp/igmp_input.c
View file

@ -178,7 +178,7 @@ void igmp_input(struct net_driver_s *dev)
if (net_ipv4addr_cmp(destipaddr, g_ipv4_allsystems))
{
/* Yes... Now check the if this this is a general or a group
/* Yes... Now check the if this is a general or a group
* specific query.
*
* RFC 2236, 2.1. Type

26
net/mld/mld_join.c
View file

@ -13,21 +13,21 @@
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of CITEL Technologies Ltd nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
* 3. Neither the name of CITEL Technologies Ltd nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY CITEL TECHNOLOGIES AND CONTRIBUTORS ``AS IS''
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL CITEL TECHNOLOGIES OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
* ARE DISCLAIMED. IN NO EVENT SHALL CITEL TECHNOLOGIES OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
@ -184,7 +184,7 @@ int mld_joingroup(FAR const struct ipv6_mreq *mrec)
return -ENOMEM;
}
/* Indicate one request to join the group from this this host */
/* Indicate one request to join the group from this host */
group->njoins = 1;
@ -241,7 +241,7 @@ int mld_joingroup(FAR const struct ipv6_mreq *mrec)
DEBUGASSERT(group->njoins > 0);
#endif
/* Indicate one more request to join the group from this this host */
/* Indicate one more request to join the group from this host */
DEBUGASSERT(group->njoins < UINT8_MAX);
group->njoins++;

6
net/tcp/tcp_conn.c
View file

@ -99,7 +99,7 @@ static dq_queue_t g_active_tcp_connections;
*
* Description:
* Given a local port number (in network byte order), find the TCP
* connection that listens on this this port.
* connection that listens on this port.
*
* Primary uses: (1) to determine if a port number is available, (2) to
* To identify the socket that will accept new connections on a local port.
@ -150,7 +150,7 @@ static inline FAR struct tcp_conn_s *tcp_ipv4_listener(in_addr_t ipaddr,
*
* Description:
* Given a local port number (in network byte order), find the TCP
* connection that listens on this this port.
* connection that listens on this port.
*
* Primary uses: (1) to determine if a port number is available, (2) to
* To identify the socket that will accept new connections on a local port.
@ -201,7 +201,7 @@ tcp_ipv6_listener(const net_ipv6addr_t ipaddr, uint16_t portno)
*
* Description:
* Given a local port number (in network byte order), find the TCP
* connection that listens on this this port.
* connection that listens on this port.
*
* Primary uses: (1) to determine if a port number is available, (2) to
* To identify the socket that will accept new connections on a local port.

2
sched/sched/sched_roundrobin.c
View file

@ -141,7 +141,7 @@ uint32_t nxsched_process_roundrobin(FAR struct tcb_s *tcb, uint32_t ticks,
tcb->flink->sched_priority >= tcb->sched_priority)
{
/* Just resetting the task priority to its current value.
* This this will cause the task to be rescheduled behind any
* This will cause the task to be rescheduled behind any
* other tasks at the same priority.
*/