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SAMA5D4: Add EMAC driver

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This commit is contained in:
Gregory Nutt 2014-06-11 12:23:31 -06:00
parent 9d0cfcc21d
commit 8b450d6d1b
9 changed files with 3939 additions and 202 deletions
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2
arch/arm/src/sam34/chip/sam_emac.h
View file

@ -379,7 +379,7 @@
#define EMAC_INT_TCOMP (1 << 7) /* Bit 7: Transmit Complete */
#define EMAC_INT_ROVR (1 << 10) /* Bit 10: Receive Overrun */
#define EMAC_INT_HRESP (1 << 11) /* Bit 11: Hresp not OK */
#define EMAC_INT_PFNX (1 << 12) /* Bit 12: Pause Frame with Non-zero Pause Quantum Received */
#define EMAC_INT_PFNZ (1 << 12) /* Bit 12: Pause Frame with Non-zero Pause Quantum Received */
#define EMAC_INT_PTZ (1 << 13) /* Bit 13: Pause Time Zero */
#define EMAC_INT_PTFR (1 << 14) /* Bit 14: Pause Frame Transmitted */
#define EMAC_INT_EXINT (1 << 15) /* Bit 15: External Interrupt (not (SR) */

4
arch/arm/src/sam34/sam_emac.c
View file

@ -1430,7 +1430,7 @@ static int sam_emac_interrupt(int irq, void *context)
* pause quantum. Cleared on a read.
*/
if ((pending & EMAC_INT_PFNX) != 0)
if ((pending & EMAC_INT_PFNZ) != 0)
{
nlldbg("Pause frame received\n");
}
@ -2805,7 +2805,7 @@ static int sam_emac_configure(struct sam_emac_s *priv)
regval = (EMAC_INT_RCOMP | EMAC_INT_RXUBR | EMAC_INT_TUR | EMAC_INT_RLEX |
EMAC_INT_TFC | EMAC_INT_TCOMP | EMAC_INT_ROVR | EMAC_INT_HRESP |
EMAC_INT_PFNX | EMAC_INT_PTZ);
EMAC_INT_PFNZ | EMAC_INT_PTZ);
sam_putreg(priv, SAM_EMAC_IER, regval);
return OK;
}

198
arch/arm/src/sama5/Kconfig
View file

@ -420,6 +420,7 @@ config SAMA5_GMAC
default n
depends on SAMA5_HAVE_GMAC
select NETDEVICES
select NETDEV_MULTINIC if SAMA5_EMAC
select ARCH_HAVE_PHY
config SAMA5_EMACA
@ -427,6 +428,7 @@ config SAMA5_EMACA
default n
depends on SAMA5_HAVE_EMACA
select NETDEVICES
select NETDEV_MULTINIC if SAMA5_GMAC
select ARCH_HAVE_PHY
config SAMA5_EMACB
@ -439,6 +441,7 @@ config SAMA5_EMAC0
depends on SAMA5_HAVE_EMACB
select SAMA5_EMACB
select NETDEVICES
select NETDEV_MULTINIC if SAMA5_EMAC1
select ARCH_HAVE_PHY
config SAMA5_EMAC1
@ -447,6 +450,7 @@ config SAMA5_EMAC1
depends on SAMA5_HAVE_EMACB && SAMA5_HAVE_EMAC1
select SAMA5_EMACB
select NETDEVICES
select NETDEV_MULTINIC if SAMA5_EMAC0
select ARCH_HAVE_PHY
config SAMA5_LCDC
@ -1255,69 +1259,69 @@ config SAMA5_EMAC_PHYSR_ALTCONFIG
where speed and mode information are combined. This might mean, for example,
separate bits for 10HD, 100HD, 10FD and 100FD.
config SAMA5_EMAC_PHYSR_SPEED
hex "PHY Speed Mask"
depends on SAMA5_EMAC_AUTONEG && !SAMA5_EMAC_PHYSR_ALTCONFIG
---help---
This must be provided if SAMA5_EMAC_AUTONEG is defined. This provides bit mask
for isolating the 10 or 100MBps speed indication.
config SAMA5_EMAC_PHYSR_100MBPS
hex "PHY 100Mbps Speed Value"
depends on SAMA5_EMAC_AUTONEG && !SAMA5_EMAC_PHYSR_ALTCONFIG
---help---
This must be provided if SAMA5_EMAC_AUTONEG is defined. This provides the value
of the speed bit(s) indicating 100MBps speed.
config SAMA5_EMAC_PHYSR_MODE
hex "PHY Mode Mask"
depends on SAMA5_EMAC_AUTONEG && !SAMA5_EMAC_PHYSR_ALTCONFIG
---help---
This must be provided if SAMA5_EMAC_AUTONEG is defined. This provide bit mask
for isolating the full or half duplex mode bits.
config SAMA5_EMAC_PHYSR_FULLDUPLEX
hex "PHY Full Duplex Mode Value"
depends on SAMA5_EMAC_AUTONEG && !SAMA5_EMAC_PHYSR_ALTCONFIG
---help---
This must be provided if SAMA5_EMAC_AUTONEG is defined. This provides the
value of the mode bits indicating full duplex mode.
if SAMA5_EMAC_AUTONEG
if SAMA5_EMAC_PHYSR_ALTCONFIG
config SAMA5_EMAC_PHYSR_ALTMODE
hex "PHY Mode Mask"
depends on SAMA5_EMAC_AUTONEG && SAMA5_EMAC_PHYSR_ALTCONFIG
---help---
This must be provided if SAMA5_EMAC_AUTONEG is defined. This provide bit mask
for isolating the speed and full/half duplex mode bits.
config SAMA5_EMAC_PHYSR_10HD
hex "10MBase-T Half Duplex Value"
depends on SAMA5_EMAC_AUTONEG && SAMA5_EMAC_PHYSR_ALTCONFIG
---help---
This must be provided if SAMA5_EMAC_AUTONEG is defined. This is the value
under the bit mask that represents the 10Mbps, half duplex setting.
config SAMA5_EMAC_PHYSR_100HD
hex "100Base-T Half Duplex Value"
depends on SAMA5_EMAC_AUTONEG && SAMA5_EMAC_PHYSR_ALTCONFIG
---help---
This must be provided if SAMA5_EMAC_AUTONEG is defined. This is the value
under the bit mask that represents the 100Mbps, half duplex setting.
config SAMA5_EMAC_PHYSR_10FD
hex "10Base-T Full Duplex Value"
depends on SAMA5_EMAC_AUTONEG && SAMA5_EMAC_PHYSR_ALTCONFIG
---help---
This must be provided if SAMA5_EMAC_AUTONEG is defined. This is the value
under the bit mask that represents the 10Mbps, full duplex setting.
config SAMA5_EMAC_PHYSR_100FD
hex "100Base-T Full Duplex Value"
depends on SAMA5_EMAC_AUTONEG && SAMA5_EMAC_PHYSR_ALTCONFIG
---help---
This must be provided if SAMA5_EMAC_AUTONEG is defined. This is the value
under the bit mask that represents the 100Mbps, full duplex setting.
endif # SAMA5_EMAC_PHYSR_ALTCONFIG
if !SAMA5_EMAC_PHYSR_ALTCONFIG
config SAMA5_EMAC_PHYSR_SPEED
hex "PHY Speed Mask"
---help---
This must be provided if SAMA5_EMAC_AUTONEG is defined. This provides bit mask
for isolating the 10 or 100MBps speed indication.
config SAMA5_EMAC_PHYSR_100MBPS
hex "PHY 100Mbps Speed Value"
---help---
This must be provided if SAMA5_EMAC_AUTONEG is defined. This provides the value
of the speed bit(s) indicating 100MBps speed.
config SAMA5_EMAC_PHYSR_MODE
hex "PHY Mode Mask"
---help---
This must be provided if SAMA5_EMAC_AUTONEG is defined. This provide bit mask
for isolating the full or half duplex mode bits.
config SAMA5_EMAC_PHYSR_FULLDUPLEX
hex "PHY Full Duplex Mode Value"
---help---
This must be provided if SAMA5_EMAC_AUTONEG is defined. This provides the
value of the mode bits indicating full duplex mode.
endif # !SAMA5_EMAC_PHYSR_ALTCONFIG
endif # SAMA5_EMAC_AUTONEG
config SAMA5_EMACA_PREALLOCATE
bool "Preallocate buffers"
default n
@ -1343,6 +1347,9 @@ endmenu # EMAC device driver options
endif # SAMA5_EMACA
if SAMA5_EMACB
menu "EMAC device driver options"
if SAMA5_EMAC0
menu "EMAC0 device driver options"
@ -1462,69 +1469,68 @@ config SAMA5_EMAC0_PHYSR_ALTCONFIG
where speed and mode information are combined. This might mean, for example,
separate bits for 10HD, 100HD, 10FD and 100FD.
config SAMA5_EMAC0_PHYSR_SPEED
hex "PHY Speed Mask"
depends on SAMA5_EMAC0_AUTONEG && !SAMA5_EMAC0_PHYSR_ALTCONFIG
---help---
This must be provided if SAMA5_EMAC0_AUTONEG is defined. This provides bit mask
for isolating the 10 or 100MBps speed indication.
config SAMA5_EMAC0_PHYSR_100MBPS
hex "PHY 100Mbps Speed Value"
depends on SAMA5_EMAC0_AUTONEG && !SAMA5_EMAC0_PHYSR_ALTCONFIG
---help---
This must be provided if SAMA5_EMAC0_AUTONEG is defined. This provides the value
of the speed bit(s) indicating 100MBps speed.
config SAMA5_EMAC0_PHYSR_MODE
hex "PHY Mode Mask"
depends on SAMA5_EMAC0_AUTONEG && !SAMA5_EMAC0_PHYSR_ALTCONFIG
---help---
This must be provided if SAMA5_EMAC0_AUTONEG is defined. This provide bit mask
for isolating the full or half duplex mode bits.
config SAMA5_EMAC0_PHYSR_FULLDUPLEX
hex "PHY Full Duplex Mode Value"
depends on SAMA5_EMAC0_AUTONEG && !SAMA5_EMAC0_PHYSR_ALTCONFIG
---help---
This must be provided if SAMA5_EMAC0_AUTONEG is defined. This provides the
value of the mode bits indicating full duplex mode.
if SAMA5_EMAC0_AUTONEG
if SAMA5_EMAC0_PHYSR_ALTCONFIG
config SAMA5_EMAC0_PHYSR_ALTMODE
hex "PHY Mode Mask"
depends on SAMA5_EMAC0_AUTONEG && SAMA5_EMAC0_PHYSR_ALTCONFIG
---help---
This must be provided if SAMA5_EMAC0_AUTONEG is defined. This provide bit mask
for isolating the speed and full/half duplex mode bits.
config SAMA5_EMAC0_PHYSR_10HD
hex "10MBase-T Half Duplex Value"
depends on SAMA5_EMAC0_AUTONEG && SAMA5_EMAC0_PHYSR_ALTCONFIG
---help---
This must be provided if SAMA5_EMAC0_AUTONEG is defined. This is the value
under the bit mask that represents the 10Mbps, half duplex setting.
config SAMA5_EMAC0_PHYSR_100HD
hex "100Base-T Half Duplex Value"
depends on SAMA5_EMAC0_AUTONEG && SAMA5_EMAC0_PHYSR_ALTCONFIG
---help---
This must be provided if SAMA5_EMAC0_AUTONEG is defined. This is the value
under the bit mask that represents the 100Mbps, half duplex setting.
config SAMA5_EMAC0_PHYSR_10FD
hex "10Base-T Full Duplex Value"
depends on SAMA5_EMAC0_AUTONEG && SAMA5_EMAC0_PHYSR_ALTCONFIG
---help---
This must be provided if SAMA5_EMAC0_AUTONEG is defined. This is the value
under the bit mask that represents the 10Mbps, full duplex setting.
config SAMA5_EMAC0_PHYSR_100FD
hex "100Base-T Full Duplex Value"
depends on SAMA5_EMAC0_AUTONEG && SAMA5_EMAC0_PHYSR_ALTCONFIG
---help---
This must be provided if SAMA5_EMAC0_AUTONEG is defined. This is the value
under the bit mask that represents the 100Mbps, full duplex setting.
endif # SAMA5_EMAC0_PHYSR_ALTCONFIG
if !SAMA5_EMAC0_PHYSR_ALTCONFIG
config SAMA5_EMAC0_PHYSR_SPEED
hex "PHY Speed Mask"
---help---
This must be provided if SAMA5_EMAC0_AUTONEG is defined. This provides bit mask
for isolating the 10 or 100MBps speed indication.
config SAMA5_EMAC0_PHYSR_100MBPS
hex "PHY 100Mbps Speed Value"
---help---
This must be provided if SAMA5_EMAC0_AUTONEG is defined. This provides the value
of the speed bit(s) indicating 100MBps speed.
config SAMA5_EMAC0_PHYSR_MODE
hex "PHY Mode Mask"
---help---
This must be provided if SAMA5_EMAC0_AUTONEG is defined. This provides the
bit mask for isolating the full or half duplex mode bits.
config SAMA5_EMAC0_PHYSR_FULLDUPLEX
hex "PHY Full Duplex Mode Value"
---help---
This must be provided if SAMA5_EMAC0_AUTONEG is defined. This provides the
value of the mode bits indicating full duplex mode.
endif # !SAMA5_EMAC0_PHYSR_ALTCONFIG
endif # SAMA5_EMAC0_AUTONEG
endmenu # EMAC0 device driver options
endif # SAMA5_EMAC0
@ -1647,69 +1653,68 @@ config SAMA5_EMAC1_PHYSR_ALTCONFIG
where speed and mode information are combined. This might mean, for example,
separate bits for 10HD, 100HD, 10FD and 100FD.
config SAMA5_EMAC1_PHYSR_SPEED
hex "PHY Speed Mask"
depends on SAMA5_EMAC1_AUTONEG && !SAMA5_EMAC1_PHYSR_ALTCONFIG
---help---
This must be provided if SAMA5_EMAC1_AUTONEG is defined. This provides bit mask
for isolating the 10 or 100MBps speed indication.
config SAMA5_EMAC1_PHYSR_100MBPS
hex "PHY 100Mbps Speed Value"
depends on SAMA5_EMAC1_AUTONEG && !SAMA5_EMAC1_PHYSR_ALTCONFIG
---help---
This must be provided if SAMA5_EMAC1_AUTONEG is defined. This provides the value
of the speed bit(s) indicating 100MBps speed.
config SAMA5_EMAC1_PHYSR_MODE
hex "PHY Mode Mask"
depends on SAMA5_EMAC1_AUTONEG && !SAMA5_EMAC1_PHYSR_ALTCONFIG
---help---
This must be provided if SAMA5_EMAC1_AUTONEG is defined. This provide bit mask
for isolating the full or half duplex mode bits.
config SAMA5_EMAC1_PHYSR_FULLDUPLEX
hex "PHY Full Duplex Mode Value"
depends on SAMA5_EMAC1_AUTONEG && !SAMA5_EMAC1_PHYSR_ALTCONFIG
---help---
This must be provided if SAMA5_EMAC1_AUTONEG is defined. This provides the
value of the mode bits indicating full duplex mode.
if SAMA5_EMAC1_AUTONEG
if SAMA5_EMAC1_PHYSR_ALTCONFIG
config SAMA5_EMAC1_PHYSR_ALTMODE
hex "PHY Mode Mask"
depends on SAMA5_EMAC1_AUTONEG && SAMA5_EMAC1_PHYSR_ALTCONFIG
---help---
This must be provided if SAMA5_EMAC1_AUTONEG is defined. This provide bit mask
for isolating the speed and full/half duplex mode bits.
config SAMA5_EMAC1_PHYSR_10HD
hex "10MBase-T Half Duplex Value"
depends on SAMA5_EMAC1_AUTONEG && SAMA5_EMAC1_PHYSR_ALTCONFIG
---help---
This must be provided if SAMA5_EMAC1_AUTONEG is defined. This is the value
under the bit mask that represents the 10Mbps, half duplex setting.
config SAMA5_EMAC1_PHYSR_100HD
hex "100Base-T Half Duplex Value"
depends on SAMA5_EMAC1_AUTONEG && SAMA5_EMAC1_PHYSR_ALTCONFIG
---help---
This must be provided if SAMA5_EMAC1_AUTONEG is defined. This is the value
under the bit mask that represents the 100Mbps, half duplex setting.
config SAMA5_EMAC1_PHYSR_10FD
hex "10Base-T Full Duplex Value"
depends on SAMA5_EMAC1_AUTONEG && SAMA5_EMAC1_PHYSR_ALTCONFIG
---help---
This must be provided if SAMA5_EMAC1_AUTONEG is defined. This is the value
under the bit mask that represents the 10Mbps, full duplex setting.
config SAMA5_EMAC1_PHYSR_100FD
hex "100Base-T Full Duplex Value"
depends on SAMA5_EMAC1_AUTONEG && SAMA5_EMAC1_PHYSR_ALTCONFIG
---help---
This must be provided if SAMA5_EMAC1_AUTONEG is defined. This is the value
under the bit mask that represents the 100Mbps, full duplex setting.
endif # SAMA5_EMAC1_PHYSR_ALTCONFIG
if !SAMA5_EMAC1_PHYSR_ALTCONFIG
config SAMA5_EMAC1_PHYSR_SPEED
hex "PHY Speed Mask"
---help---
This must be provided if SAMA5_EMAC1_AUTONEG is defined. This provides bit mask
for isolating the 10 or 100MBps speed indication.
config SAMA5_EMAC1_PHYSR_100MBPS
hex "PHY 100Mbps Speed Value"
---help---
This must be provided if SAMA5_EMAC1_AUTONEG is defined. This provides the value
of the speed bit(s) indicating 100MBps speed.
config SAMA5_EMAC1_PHYSR_MODE
hex "PHY Mode Mask"
---help---
This must be provided if SAMA5_EMAC1_AUTONEG is defined. This provide bit mask
for isolating the full or half duplex mode bits.
config SAMA5_EMAC1_PHYSR_FULLDUPLEX
hex "PHY Full Duplex Mode Value"
---help---
This must be provided if SAMA5_EMAC1_AUTONEG is defined. This provides the
value of the mode bits indicating full duplex mode.
endif # !SAMA5_EMAC1_PHYSR_ALTCONFIG
endif # SAMA5_EMAC1_AUTONEG
endmenu # EMAC1 device driver options
endif # SAMA5_EMAC1
@ -1736,6 +1741,7 @@ config SAMA5_EMACB_REGDEBUG
---help---
Enable very low-level register access debug. Depends on DEBUG.
endmenu # EMAC device driver options
endif # SAMA5_EMACB
if SAMA5_EMACA || SAMA5_EMAC0 || SAMA5_EMAC1 || SAMA5_GMAC

297
arch/arm/src/sama5/chip/sam_emacb.h
View file

@ -157,106 +157,215 @@
/* EMAC Register Addresses **********************************************************/
#define SAM_EMAC_NCR (SAM_EMAC_BASE+SAM_EMAC_NCR_OFFSET)
#define SAM_EMAC_NCFGR (SAM_EMAC_BASE+SAM_EMAC_NCFGR_OFFSET)
#define SAM_EMAC_NSR (SAM_EMAC_BASE+SAM_EMAC_NSR_OFFSET)
#define SAM_EMAC_TSR (SAM_EMAC_BASE+SAM_EMAC_TSR_OFFSET)
#define SAM_EMAC_UR (SAM_EMAC_BASE+SAM_EMAC_UR_OFFSET)
#define SAM_EMAC_DCFGR (SAM_EMAC_BASE+SAM_EMAC_DCFGR_OFFSET)
#define SAM_EMAC_RBQB (SAM_EMAC_BASE+SAM_EMAC_RBQB_OFFSET)
#define SAM_EMAC_TBQB (SAM_EMAC_BASE+SAM_EMAC_TBQB_OFFSET)
#define SAM_EMAC_RSR (SAM_EMAC_BASE+SAM_EMAC_RSR_OFFSET)
#define SAM_EMAC_ISR (SAM_EMAC_BASE+SAM_EMAC_ISR_OFFSET)
#define SAM_EMAC_IER (SAM_EMAC_BASE+SAM_EMAC_IER_OFFSET)
#define SAM_EMAC_IDR (SAM_EMAC_BASE+SAM_EMAC_IDR_OFFSET)
#define SAM_EMAC_IMR (SAM_EMAC_BASE+SAM_EMAC_IMR_OFFSET)
#define SAM_EMAC_MAN (SAM_EMAC_BASE+SAM_EMAC_MAN_OFFSET)
#define SAM_EMAC_RPQ (SAM_EMAC_BASE+SAM_EMAC_RPQ_OFFSET)
#define SAM_EMAC_TPQ (SAM_EMAC_BASE+SAM_EMAC_TPQ_OFFSET)
#define SAM_EMAC_HRB (SAM_EMAC_BASE+SAM_EMAC_HRB_OFFSET)
#define SAM_EMAC_HRT (SAM_EMAC_BASE+SAM_EMAC_HRT_OFFSET)
#define SAM_EMAC_SAB1 (SAM_EMAC_BASE+SAM_EMAC_SAB1_OFFSET)
#define SAM_EMAC_SAT1 (SAM_EMAC_BASE+SAM_EMAC_SAT1_OFFSET)
#define SAM_EMAC_SAB2 (SAM_EMAC_BASE+SAM_EMAC_SAB2_OFFSET)
#define SAM_EMAC_SAT2 (SAM_EMAC_BASE+SAM_EMAC_SAT2_OFFSET)
#define SAM_EMAC_SAB3 (SAM_EMAC_BASE+SAM_EMAC_SAB3_OFFSET)
#define SAM_EMAC_SAT3 (SAM_EMAC_BASE+SAM_EMAC_SAT3_OFFSET)
#define SAM_EMAC_SAB4 (SAM_EMAC_BASE+SAM_EMAC_SAB4_OFFSET)
#define SAM_EMAC_SAT4 (SAM_EMAC_BASE+SAM_EMAC_SAT4_OFFSET)
#define SAM_EMAC_TIDM1 (SAM_EMAC_BASE+SAM_EMAC_TIDM1_OFFSET)
#define SAM_EMAC_TIDM2 (SAM_EMAC_BASE+SAM_EMAC_TIDM2_OFFSET)
#define SAM_EMAC_TIDM3 (SAM_EMAC_BASE+SAM_EMAC_TIDM3_OFFSET)
#define SAM_EMAC_TIDM4 (SAM_EMAC_BASE+SAM_EMAC_TIDM4_OFFSET)
#define SAM_EMAC_IPGS (SAM_EMAC_BASE+SAM_EMAC_IPGS_OFFSET)
#define SAM_EMAC_SVLAN (SAM_EMAC_BASE+SAM_EMAC_SVLAN_OFFSET)
#define SAM_EMAC_TPFCP (SAM_EMAC_BASE+SAM_EMAC_TPFCP_OFFSET)
#define SAM_EMAC_SAMB1 (SAM_EMAC_BASE+SAM_EMAC_SAMB1_OFFSET)
#define SAM_EMAC_SAMT1 (SAM_EMAC_BASE+SAM_EMAC_SAMT1_OFFSET)
#ifdef CONFIG_SAMA5_EMAC0
/* EMAC0 base addresses */
# define SAM_EMAC0_NCR (SAM_EMAC0_BASE+SAM_EMAC_NCR_OFFSET)
# define SAM_EMAC0_NCFGR (SAM_EMAC0_BASE+SAM_EMAC_NCFGR_OFFSET)
# define SAM_EMAC0_NSR (SAM_EMAC0_BASE+SAM_EMAC_NSR_OFFSET)
# define SAM_EMAC0_TSR (SAM_EMAC0_BASE+SAM_EMAC_TSR_OFFSET)
# define SAM_EMAC0_UR (SAM_EMAC0_BASE+SAM_EMAC_UR_OFFSET)
# define SAM_EMAC0_DCFGR (SAM_EMAC0_BASE+SAM_EMAC_DCFGR_OFFSET)
# define SAM_EMAC0_RBQB (SAM_EMAC0_BASE+SAM_EMAC_RBQB_OFFSET)
# define SAM_EMAC0_TBQB (SAM_EMAC0_BASE+SAM_EMAC_TBQB_OFFSET)
# define SAM_EMAC0_RSR (SAM_EMAC0_BASE+SAM_EMAC_RSR_OFFSET)
# define SAM_EMAC0_ISR (SAM_EMAC0_BASE+SAM_EMAC_ISR_OFFSET)
# define SAM_EMAC0_IER (SAM_EMAC0_BASE+SAM_EMAC_IER_OFFSET)
# define SAM_EMAC0_IDR (SAM_EMAC0_BASE+SAM_EMAC_IDR_OFFSET)
# define SAM_EMAC0_IMR (SAM_EMAC0_BASE+SAM_EMAC_IMR_OFFSET)
# define SAM_EMAC0_MAN (SAM_EMAC0_BASE+SAM_EMAC_MAN_OFFSET)
# define SAM_EMAC0_RPQ (SAM_EMAC0_BASE+SAM_EMAC_RPQ_OFFSET)
# define SAM_EMAC0_TPQ (SAM_EMAC0_BASE+SAM_EMAC_TPQ_OFFSET)
# define SAM_EMAC0_HRB (SAM_EMAC0_BASE+SAM_EMAC_HRB_OFFSET)
# define SAM_EMAC0_HRT (SAM_EMAC0_BASE+SAM_EMAC_HRT_OFFSET)
# define SAM_EMAC0_SAB1 (SAM_EMAC0_BASE+SAM_EMAC_SAB1_OFFSET)
# define SAM_EMAC0_SAT1 (SAM_EMAC0_BASE+SAM_EMAC_SAT1_OFFSET)
# define SAM_EMAC0_SAB2 (SAM_EMAC0_BASE+SAM_EMAC_SAB2_OFFSET)
# define SAM_EMAC0_SAT2 (SAM_EMAC0_BASE+SAM_EMAC_SAT2_OFFSET)
# define SAM_EMAC0_SAB3 (SAM_EMAC0_BASE+SAM_EMAC_SAB3_OFFSET)
# define SAM_EMAC0_SAT3 (SAM_EMAC0_BASE+SAM_EMAC_SAT3_OFFSET)
# define SAM_EMAC0_SAB4 (SAM_EMAC0_BASE+SAM_EMAC_SAB4_OFFSET)
# define SAM_EMAC0_SAT4 (SAM_EMAC0_BASE+SAM_EMAC_SAT4_OFFSET)
# define SAM_EMAC0_TIDM1 (SAM_EMAC0_BASE+SAM_EMAC_TIDM1_OFFSET)
# define SAM_EMAC0_TIDM2 (SAM_EMAC0_BASE+SAM_EMAC_TIDM2_OFFSET)
# define SAM_EMAC0_TIDM3 (SAM_EMAC0_BASE+SAM_EMAC_TIDM3_OFFSET)
# define SAM_EMAC0_TIDM4 (SAM_EMAC0_BASE+SAM_EMAC_TIDM4_OFFSET)
# define SAM_EMAC0_IPGS (SAM_EMAC0_BASE+SAM_EMAC_IPGS_OFFSET)
# define SAM_EMAC0_SVLAN (SAM_EMAC0_BASE+SAM_EMAC_SVLAN_OFFSET)
# define SAM_EMAC0_TPFCP (SAM_EMAC0_BASE+SAM_EMAC_TPFCP_OFFSET)
# define SAM_EMAC0_SAMB1 (SAM_EMAC0_BASE+SAM_EMAC_SAMB1_OFFSET)
# define SAM_EMAC0_SAMT1 (SAM_EMAC0_BASE+SAM_EMAC_SAMT1_OFFSET)
/* Statistics registers */
#define SAM_EMAC_OTLO (SAM_EMAC_BASE+SAM_EMAC_OTLO_OFFSET)
#define SAM_EMAC_OTHI (SAM_EMAC_BASE+SAM_EMAC_OTHI_OFFSET)
#define SAM_EMAC_FT (SAM_EMAC_BASE+SAM_EMAC_FT_OFFSET)
#define SAM_EMAC_BCFT (SAM_EMAC_BASE+SAM_EMAC_BCFT_OFFSET)
#define SAM_EMAC_MFT (SAM_EMAC_BASE+SAM_EMAC_MFT_OFFSET)
#define SAM_EMAC_PFT (SAM_EMAC_BASE+SAM_EMAC_PFT_OFFSET)
#define SAM_EMAC_BFT64 (SAM_EMAC_BASE+SAM_EMAC_BFT64_OFFSET)
#define SAM_EMAC_TBFT127 (SAM_EMAC_BASE+SAM_EMAC_TBFT127_OFFSET)
#define SAM_EMAC_TBFT255 (SAM_EMAC_BASE+SAM_EMAC_TBFT255_OFFSET)
#define SAM_EMAC_TBFT511 (SAM_EMAC_BASE+SAM_EMAC_TBFT511_OFFSET)
#define SAM_EMAC_TBFT1023 (SAM_EMAC_BASE+SAM_EMAC_TBFT1023_OFFSET)
#define SAM_EMAC_TBFT1518 (SAM_EMAC_BASE+SAM_EMAC_TBFT1518_OFFSET)
#define SAM_EMAC_GTBFT1518 (SAM_EMAC_BASE+SAM_EMAC_GTBFT1518_OFFSET)
#define SAM_EMAC_TUR (SAM_EMAC_BASE+SAM_EMAC_TUR_OFFSET)
#define SAM_EMAC_SCF (SAM_EMAC_BASE+SAM_EMAC_SCF_OFFSET)
#define SAM_EMAC_MCF (SAM_EMAC_BASE+SAM_EMAC_MCF_OFFSET)
#define SAM_EMAC_EC (SAM_EMAC_BASE+SAM_EMAC_EC_OFFSET)
#define SAM_EMAC_LC (SAM_EMAC_BASE+SAM_EMAC_LC_OFFSET)
#define SAM_EMAC_DTF (SAM_EMAC_BASE+SAM_EMAC_DTF_OFFSET)
#define SAM_EMAC_CSE (SAM_EMAC_BASE+SAM_EMAC_CSE_OFFSET)
#define SAM_EMAC_ORLO (SAM_EMAC_BASE+SAM_EMAC_ORLO_OFFSET)
#define SAM_EMAC_ORHI (SAM_EMAC_BASE+SAM_EMAC_ORHI_OFFSET)
#define SAM_EMAC_FR (SAM_EMAC_BASE+SAM_EMAC_FR_OFFSET)
#define SAM_EMAC_BCFR (SAM_EMAC_BASE+SAM_EMAC_BCFR_OFFSET)
#define SAM_EMAC_MFR (SAM_EMAC_BASE+SAM_EMAC_MFR_OFFSET)
#define SAM_EMAC_PFR (SAM_EMAC_BASE+SAM_EMAC_PFR_OFFSET)
#define SAM_EMAC_BFR64 (SAM_EMAC_BASE+SAM_EMAC_BFR64_OFFSET)
#define SAM_EMAC_TBFR127 (SAM_EMAC_BASE+SAM_EMAC_TBFR127_OFFSET)
#define SAM_EMAC_TBFR255 (SAM_EMAC_BASE+SAM_EMAC_TBFR255_OFFSET)
#define SAM_EMAC_TBFR511 (SAM_EMAC_BASE+SAM_EMAC_TBFR511_OFFSET)
#define SAM_EMAC_TBFR1023 (SAM_EMAC_BASE+SAM_EMAC_TBFR1023_OFFSET)
#define SAM_EMAC_TBFR1518 (SAM_EMAC_BASE+SAM_EMAC_TBFR1518_OFFSET)
#define SAM_EMAC_TMXBFR (SAM_EMAC_BASE+SAM_EMAC_TMXBFR_OFFSET)
#define SAM_EMAC_UFR (SAM_EMAC_BASE+SAM_EMAC_UFR_OFFSET)
#define SAM_EMAC_OFR (SAM_EMAC_BASE+SAM_EMAC_OFR_OFFSET)
#define SAM_EMAC_JR (SAM_EMAC_BASE+SAM_EMAC_JR_OFFSET)
#define SAM_EMAC_FCSE (SAM_EMAC_BASE+SAM_EMAC_FCSE_OFFSET)
#define SAM_EMAC_LFFE (SAM_EMAC_BASE+SAM_EMAC_LFFE_OFFSET)
#define SAM_EMAC_RSE (SAM_EMAC_BASE+SAM_EMAC_RSE_OFFSET)
#define SAM_EMAC_AE (SAM_EMAC_BASE+SAM_EMAC_AE_OFFSET)
#define SAM_EMAC_RRE (SAM_EMAC_BASE+SAM_EMAC_RRE_OFFSET)
#define SAM_EMAC_ROE (SAM_EMAC_BASE+SAM_EMAC_ROE_OFFSET)
#define SAM_EMAC_IHCE (SAM_EMAC_BASE+SAM_EMAC_IHCE_OFFSET)
#define SAM_EMAC_TCE (SAM_EMAC_BASE+SAM_EMAC_TCE_OFFSET)
#define SAM_EMAC_UCE (SAM_EMAC_BASE+SAM_EMAC_UCE_OFFSET)
# define SAM_EMAC0_OTLO (SAM_EMAC0_BASE+SAM_EMAC_OTLO_OFFSET)
# define SAM_EMAC0_OTHI (SAM_EMAC0_BASE+SAM_EMAC_OTHI_OFFSET)
# define SAM_EMAC0_FT (SAM_EMAC0_BASE+SAM_EMAC_FT_OFFSET)
# define SAM_EMAC0_BCFT (SAM_EMAC0_BASE+SAM_EMAC_BCFT_OFFSET)
# define SAM_EMAC0_MFT (SAM_EMAC0_BASE+SAM_EMAC_MFT_OFFSET)
# define SAM_EMAC0_PFT (SAM_EMAC0_BASE+SAM_EMAC_PFT_OFFSET)
# define SAM_EMAC0_BFT64 (SAM_EMAC0_BASE+SAM_EMAC_BFT64_OFFSET)
# define SAM_EMAC0_TBFT127 (SAM_EMAC0_BASE+SAM_EMAC_TBFT127_OFFSET)
# define SAM_EMAC0_TBFT255 (SAM_EMAC0_BASE+SAM_EMAC_TBFT255_OFFSET)
# define SAM_EMAC0_TBFT511 (SAM_EMAC0_BASE+SAM_EMAC_TBFT511_OFFSET)
# define SAM_EMAC0_TBFT1023 (SAM_EMAC0_BASE+SAM_EMAC_TBFT1023_OFFSET)
# define SAM_EMAC0_TBFT1518 (SAM_EMAC0_BASE+SAM_EMAC_TBFT1518_OFFSET)
# define SAM_EMAC0_GTBFT1518 (SAM_EMAC0_BASE+SAM_EMAC_GTBFT1518_OFFSET)
# define SAM_EMAC0_TUR (SAM_EMAC0_BASE+SAM_EMAC_TUR_OFFSET)
# define SAM_EMAC0_SCF (SAM_EMAC0_BASE+SAM_EMAC_SCF_OFFSET)
# define SAM_EMAC0_MCF (SAM_EMAC0_BASE+SAM_EMAC_MCF_OFFSET)
# define SAM_EMAC0_EC (SAM_EMAC0_BASE+SAM_EMAC_EC_OFFSET)
# define SAM_EMAC0_LC (SAM_EMAC0_BASE+SAM_EMAC_LC_OFFSET)
# define SAM_EMAC0_DTF (SAM_EMAC0_BASE+SAM_EMAC_DTF_OFFSET)
# define SAM_EMAC0_CSE (SAM_EMAC0_BASE+SAM_EMAC_CSE_OFFSET)
# define SAM_EMAC0_ORLO (SAM_EMAC0_BASE+SAM_EMAC_ORLO_OFFSET)
# define SAM_EMAC0_ORHI (SAM_EMAC0_BASE+SAM_EMAC_ORHI_OFFSET)
# define SAM_EMAC0_FR (SAM_EMAC0_BASE+SAM_EMAC_FR_OFFSET)
# define SAM_EMAC0_BCFR (SAM_EMAC0_BASE+SAM_EMAC_BCFR_OFFSET)
# define SAM_EMAC0_MFR (SAM_EMAC0_BASE+SAM_EMAC_MFR_OFFSET)
# define SAM_EMAC0_PFR (SAM_EMAC0_BASE+SAM_EMAC_PFR_OFFSET)
# define SAM_EMAC0_BFR64 (SAM_EMAC0_BASE+SAM_EMAC_BFR64_OFFSET)
# define SAM_EMAC0_TBFR127 (SAM_EMAC0_BASE+SAM_EMAC_TBFR127_OFFSET)
# define SAM_EMAC0_TBFR255 (SAM_EMAC0_BASE+SAM_EMAC_TBFR255_OFFSET)
# define SAM_EMAC0_TBFR511 (SAM_EMAC0_BASE+SAM_EMAC_TBFR511_OFFSET)
# define SAM_EMAC0_TBFR1023 (SAM_EMAC0_BASE+SAM_EMAC_TBFR1023_OFFSET)
# define SAM_EMAC0_TBFR1518 (SAM_EMAC0_BASE+SAM_EMAC_TBFR1518_OFFSET)
# define SAM_EMAC0_TMXBFR (SAM_EMAC0_BASE+SAM_EMAC_TMXBFR_OFFSET)
# define SAM_EMAC0_UFR (SAM_EMAC0_BASE+SAM_EMAC_UFR_OFFSET)
# define SAM_EMAC0_OFR (SAM_EMAC0_BASE+SAM_EMAC_OFR_OFFSET)
# define SAM_EMAC0_JR (SAM_EMAC0_BASE+SAM_EMAC_JR_OFFSET)
# define SAM_EMAC0_FCSE (SAM_EMAC0_BASE+SAM_EMAC_FCSE_OFFSET)
# define SAM_EMAC0_LFFE (SAM_EMAC0_BASE+SAM_EMAC_LFFE_OFFSET)
# define SAM_EMAC0_RSE (SAM_EMAC0_BASE+SAM_EMAC_RSE_OFFSET)
# define SAM_EMAC0_AE (SAM_EMAC0_BASE+SAM_EMAC_AE_OFFSET)
# define SAM_EMAC0_RRE (SAM_EMAC0_BASE+SAM_EMAC_RRE_OFFSET)
# define SAM_EMAC0_ROE (SAM_EMAC0_BASE+SAM_EMAC_ROE_OFFSET)
# define SAM_EMAC0_IHCE (SAM_EMAC0_BASE+SAM_EMAC_IHCE_OFFSET)
# define SAM_EMAC0_TCE (SAM_EMAC0_BASE+SAM_EMAC_TCE_OFFSET)
# define SAM_EMAC0_UCE (SAM_EMAC0_BASE+SAM_EMAC_UCE_OFFSET)
/* PTP/1588 Timer Registers */
#define SAM_EMAC_TSSS (SAM_EMAC_BASE+SAM_EMAC_TSSS_OFFSET)
#define SAM_EMAC_TSSN (SAM_EMAC_BASE+SAM_EMAC_TSSN_OFFSET)
#define SAM_EMAC_TS (SAM_EMAC_BASE+SAM_EMAC_TS_OFFSET)
#define SAM_EMAC_TN (SAM_EMAC_BASE+SAM_EMAC_TN_OFFSET)
#define SAM_EMAC_TA (SAM_EMAC_BASE+SAM_EMAC_TA_OFFSET)
#define SAM_EMAC_TI (SAM_EMAC_BASE+SAM_EMAC_TI_OFFSET)
#define SAM_EMAC_EFTS (SAM_EMAC_BASE+SAM_EMAC_EFTS_OFFSET)
#define SAM_EMAC_EFTN (SAM_EMAC_BASE+SAM_EMAC_EFTN_OFFSET)
#define SAM_EMAC_EFRS (SAM_EMAC_BASE+SAM_EMAC_EFRS_OFFSET)
#define SAM_EMAC_EFRN (SAM_EMAC_BASE+SAM_EMAC_EFRN_OFFSET)
#define SAM_EMAC_PEFTS (SAM_EMAC_BASE+SAM_EMAC_PEFTS_OFFSET)
#define SAM_EMAC_PEFTN (SAM_EMAC_BASE+SAM_EMAC_PEFTN_OFFSET)
#define SAM_EMAC_PEFRS (SAM_EMAC_BASE+SAM_EMAC_PEFRS_OFFSET)
#define SAM_EMAC_PEFRN (SAM_EMAC_BASE+SAM_EMAC_PEFRN_OFFSET)
# define SAM_EMAC0_TSSS (SAM_EMAC0_BASE+SAM_EMAC_TSSS_OFFSET)
# define SAM_EMAC0_TSSN (SAM_EMAC0_BASE+SAM_EMAC_TSSN_OFFSET)
# define SAM_EMAC0_TS (SAM_EMAC0_BASE+SAM_EMAC_TS_OFFSET)
# define SAM_EMAC0_TN (SAM_EMAC0_BASE+SAM_EMAC_TN_OFFSET)
# define SAM_EMAC0_TA (SAM_EMAC0_BASE+SAM_EMAC_TA_OFFSET)
# define SAM_EMAC0_TI (SAM_EMAC0_BASE+SAM_EMAC_TI_OFFSET)
# define SAM_EMAC0_EFTS (SAM_EMAC0_BASE+SAM_EMAC_EFTS_OFFSET)
# define SAM_EMAC0_EFTN (SAM_EMAC0_BASE+SAM_EMAC_EFTN_OFFSET)
# define SAM_EMAC0_EFRS (SAM_EMAC0_BASE+SAM_EMAC_EFRS_OFFSET)
# define SAM_EMAC0_EFRN (SAM_EMAC0_BASE+SAM_EMAC_EFRN_OFFSET)
# define SAM_EMAC0_PEFTS (SAM_EMAC0_BASE+SAM_EMAC_PEFTS_OFFSET)
# define SAM_EMAC0_PEFTN (SAM_EMAC0_BASE+SAM_EMAC_PEFTN_OFFSET)
# define SAM_EMAC0_PEFRS (SAM_EMAC0_BASE+SAM_EMAC_PEFRS_OFFSET)
# define SAM_EMAC0_PEFRN (SAM_EMAC0_BASE+SAM_EMAC_PEFRN_OFFSET)
#endif
#ifdef CONFIG_SAMA5_EMAC1
/* EMAC1 base addresses */
# define SAM_EMAC1_NCR (SAM_EMAC1_BASE+SAM_EMAC_NCR_OFFSET)
# define SAM_EMAC1_NCFGR (SAM_EMAC1_BASE+SAM_EMAC_NCFGR_OFFSET)
# define SAM_EMAC1_NSR (SAM_EMAC1_BASE+SAM_EMAC_NSR_OFFSET)
# define SAM_EMAC1_TSR (SAM_EMAC1_BASE+SAM_EMAC_TSR_OFFSET)
# define SAM_EMAC1_UR (SAM_EMAC1_BASE+SAM_EMAC_UR_OFFSET)
# define SAM_EMAC1_DCFGR (SAM_EMAC1_BASE+SAM_EMAC_DCFGR_OFFSET)
# define SAM_EMAC1_RBQB (SAM_EMAC1_BASE+SAM_EMAC_RBQB_OFFSET)
# define SAM_EMAC1_TBQB (SAM_EMAC1_BASE+SAM_EMAC_TBQB_OFFSET)
# define SAM_EMAC1_RSR (SAM_EMAC1_BASE+SAM_EMAC_RSR_OFFSET)
# define SAM_EMAC1_ISR (SAM_EMAC1_BASE+SAM_EMAC_ISR_OFFSET)
# define SAM_EMAC1_IER (SAM_EMAC1_BASE+SAM_EMAC_IER_OFFSET)
# define SAM_EMAC1_IDR (SAM_EMAC1_BASE+SAM_EMAC_IDR_OFFSET)
# define SAM_EMAC1_IMR (SAM_EMAC1_BASE+SAM_EMAC_IMR_OFFSET)
# define SAM_EMAC1_MAN (SAM_EMAC1_BASE+SAM_EMAC_MAN_OFFSET)
# define SAM_EMAC1_RPQ (SAM_EMAC1_BASE+SAM_EMAC_RPQ_OFFSET)
# define SAM_EMAC1_TPQ (SAM_EMAC1_BASE+SAM_EMAC_TPQ_OFFSET)
# define SAM_EMAC1_HRB (SAM_EMAC1_BASE+SAM_EMAC_HRB_OFFSET)
# define SAM_EMAC1_HRT (SAM_EMAC1_BASE+SAM_EMAC_HRT_OFFSET)
# define SAM_EMAC1_SAB1 (SAM_EMAC1_BASE+SAM_EMAC_SAB1_OFFSET)
# define SAM_EMAC1_SAT1 (SAM_EMAC1_BASE+SAM_EMAC_SAT1_OFFSET)
# define SAM_EMAC1_SAB2 (SAM_EMAC1_BASE+SAM_EMAC_SAB2_OFFSET)
# define SAM_EMAC1_SAT2 (SAM_EMAC1_BASE+SAM_EMAC_SAT2_OFFSET)
# define SAM_EMAC1_SAB3 (SAM_EMAC1_BASE+SAM_EMAC_SAB3_OFFSET)
# define SAM_EMAC1_SAT3 (SAM_EMAC1_BASE+SAM_EMAC_SAT3_OFFSET)
# define SAM_EMAC1_SAB4 (SAM_EMAC1_BASE+SAM_EMAC_SAB4_OFFSET)
# define SAM_EMAC1_SAT4 (SAM_EMAC1_BASE+SAM_EMAC_SAT4_OFFSET)
# define SAM_EMAC1_TIDM1 (SAM_EMAC1_BASE+SAM_EMAC_TIDM1_OFFSET)
# define SAM_EMAC1_TIDM2 (SAM_EMAC1_BASE+SAM_EMAC_TIDM2_OFFSET)
# define SAM_EMAC1_TIDM3 (SAM_EMAC1_BASE+SAM_EMAC_TIDM3_OFFSET)
# define SAM_EMAC1_TIDM4 (SAM_EMAC1_BASE+SAM_EMAC_TIDM4_OFFSET)
# define SAM_EMAC1_IPGS (SAM_EMAC1_BASE+SAM_EMAC_IPGS_OFFSET)
# define SAM_EMAC1_SVLAN (SAM_EMAC1_BASE+SAM_EMAC_SVLAN_OFFSET)
# define SAM_EMAC1_TPFCP (SAM_EMAC1_BASE+SAM_EMAC_TPFCP_OFFSET)
# define SAM_EMAC1_SAMB1 (SAM_EMAC1_BASE+SAM_EMAC_SAMB1_OFFSET)
# define SAM_EMAC1_SAMT1 (SAM_EMAC1_BASE+SAM_EMAC_SAMT1_OFFSET)
/* Statistics registers */
# define SAM_EMAC1_OTLO (SAM_EMAC1_BASE+SAM_EMAC_OTLO_OFFSET)
# define SAM_EMAC1_OTHI (SAM_EMAC1_BASE+SAM_EMAC_OTHI_OFFSET)
# define SAM_EMAC1_FT (SAM_EMAC1_BASE+SAM_EMAC_FT_OFFSET)
# define SAM_EMAC1_BCFT (SAM_EMAC1_BASE+SAM_EMAC_BCFT_OFFSET)
# define SAM_EMAC1_MFT (SAM_EMAC1_BASE+SAM_EMAC_MFT_OFFSET)
# define SAM_EMAC1_PFT (SAM_EMAC1_BASE+SAM_EMAC_PFT_OFFSET)
# define SAM_EMAC1_BFT64 (SAM_EMAC1_BASE+SAM_EMAC_BFT64_OFFSET)
# define SAM_EMAC1_TBFT127 (SAM_EMAC1_BASE+SAM_EMAC_TBFT127_OFFSET)
# define SAM_EMAC1_TBFT255 (SAM_EMAC1_BASE+SAM_EMAC_TBFT255_OFFSET)
# define SAM_EMAC1_TBFT511 (SAM_EMAC1_BASE+SAM_EMAC_TBFT511_OFFSET)
# define SAM_EMAC1_TBFT1023 (SAM_EMAC1_BASE+SAM_EMAC_TBFT1023_OFFSET)
# define SAM_EMAC1_TBFT1518 (SAM_EMAC1_BASE+SAM_EMAC_TBFT1518_OFFSET)
# define SAM_EMAC1_GTBFT1518 (SAM_EMAC1_BASE+SAM_EMAC_GTBFT1518_OFFSET)
# define SAM_EMAC1_TUR (SAM_EMAC1_BASE+SAM_EMAC_TUR_OFFSET)
# define SAM_EMAC1_SCF (SAM_EMAC1_BASE+SAM_EMAC_SCF_OFFSET)
# define SAM_EMAC1_MCF (SAM_EMAC1_BASE+SAM_EMAC_MCF_OFFSET)
# define SAM_EMAC1_EC (SAM_EMAC1_BASE+SAM_EMAC_EC_OFFSET)
# define SAM_EMAC1_LC (SAM_EMAC1_BASE+SAM_EMAC_LC_OFFSET)
# define SAM_EMAC1_DTF (SAM_EMAC1_BASE+SAM_EMAC_DTF_OFFSET)
# define SAM_EMAC1_CSE (SAM_EMAC1_BASE+SAM_EMAC_CSE_OFFSET)
# define SAM_EMAC1_ORLO (SAM_EMAC1_BASE+SAM_EMAC_ORLO_OFFSET)
# define SAM_EMAC1_ORHI (SAM_EMAC1_BASE+SAM_EMAC_ORHI_OFFSET)
# define SAM_EMAC1_FR (SAM_EMAC1_BASE+SAM_EMAC_FR_OFFSET)
# define SAM_EMAC1_BCFR (SAM_EMAC1_BASE+SAM_EMAC_BCFR_OFFSET)
# define SAM_EMAC1_MFR (SAM_EMAC1_BASE+SAM_EMAC_MFR_OFFSET)
# define SAM_EMAC1_PFR (SAM_EMAC1_BASE+SAM_EMAC_PFR_OFFSET)
# define SAM_EMAC1_BFR64 (SAM_EMAC1_BASE+SAM_EMAC_BFR64_OFFSET)
# define SAM_EMAC1_TBFR127 (SAM_EMAC1_BASE+SAM_EMAC_TBFR127_OFFSET)
# define SAM_EMAC1_TBFR255 (SAM_EMAC1_BASE+SAM_EMAC_TBFR255_OFFSET)
# define SAM_EMAC1_TBFR511 (SAM_EMAC1_BASE+SAM_EMAC_TBFR511_OFFSET)
# define SAM_EMAC1_TBFR1023 (SAM_EMAC1_BASE+SAM_EMAC_TBFR1023_OFFSET)
# define SAM_EMAC1_TBFR1518 (SAM_EMAC1_BASE+SAM_EMAC_TBFR1518_OFFSET)
# define SAM_EMAC1_TMXBFR (SAM_EMAC1_BASE+SAM_EMAC_TMXBFR_OFFSET)
# define SAM_EMAC1_UFR (SAM_EMAC1_BASE+SAM_EMAC_UFR_OFFSET)
# define SAM_EMAC1_OFR (SAM_EMAC1_BASE+SAM_EMAC_OFR_OFFSET)
# define SAM_EMAC1_JR (SAM_EMAC1_BASE+SAM_EMAC_JR_OFFSET)
# define SAM_EMAC1_FCSE (SAM_EMAC1_BASE+SAM_EMAC_FCSE_OFFSET)
# define SAM_EMAC1_LFFE (SAM_EMAC1_BASE+SAM_EMAC_LFFE_OFFSET)
# define SAM_EMAC1_RSE (SAM_EMAC1_BASE+SAM_EMAC_RSE_OFFSET)
# define SAM_EMAC1_AE (SAM_EMAC1_BASE+SAM_EMAC_AE_OFFSET)
# define SAM_EMAC1_RRE (SAM_EMAC1_BASE+SAM_EMAC_RRE_OFFSET)
# define SAM_EMAC1_ROE (SAM_EMAC1_BASE+SAM_EMAC_ROE_OFFSET)
# define SAM_EMAC1_IHCE (SAM_EMAC1_BASE+SAM_EMAC_IHCE_OFFSET)
# define SAM_EMAC1_TCE (SAM_EMAC1_BASE+SAM_EMAC_TCE_OFFSET)
# define SAM_EMAC1_UCE (SAM_EMAC1_BASE+SAM_EMAC_UCE_OFFSET)
/* PTP/1588 Timer Registers */
# define SAM_EMAC1_TSSS (SAM_EMAC1_BASE+SAM_EMAC_TSSS_OFFSET)
# define SAM_EMAC1_TSSN (SAM_EMAC1_BASE+SAM_EMAC_TSSN_OFFSET)
# define SAM_EMAC1_TS (SAM_EMAC1_BASE+SAM_EMAC_TS_OFFSET)
# define SAM_EMAC1_TN (SAM_EMAC1_BASE+SAM_EMAC_TN_OFFSET)
# define SAM_EMAC1_TA (SAM_EMAC1_BASE+SAM_EMAC_TA_OFFSET)
# define SAM_EMAC1_TI (SAM_EMAC1_BASE+SAM_EMAC_TI_OFFSET)
# define SAM_EMAC1_EFTS (SAM_EMAC1_BASE+SAM_EMAC_EFTS_OFFSET)
# define SAM_EMAC1_EFTN (SAM_EMAC1_BASE+SAM_EMAC_EFTN_OFFSET)
# define SAM_EMAC1_EFRS (SAM_EMAC1_BASE+SAM_EMAC_EFRS_OFFSET)
# define SAM_EMAC1_EFRN (SAM_EMAC1_BASE+SAM_EMAC_EFRN_OFFSET)
# define SAM_EMAC1_PEFTS (SAM_EMAC1_BASE+SAM_EMAC_PEFTS_OFFSET)
# define SAM_EMAC1_PEFTN (SAM_EMAC1_BASE+SAM_EMAC_PEFTN_OFFSET)
# define SAM_EMAC1_PEFRS (SAM_EMAC1_BASE+SAM_EMAC_PEFRS_OFFSET)
# define SAM_EMAC1_PEFRN (SAM_EMAC1_BASE+SAM_EMAC_PEFRN_OFFSET)
#endif
/* EMAC Register Bit Definitions ****************************************************/

8
arch/arm/src/sama5/sam_emaca.c
View file

@ -88,13 +88,13 @@
****************************************************************************/
/* Configuration ************************************************************/
/* Number of buffer for RX */
/* Number of buffers for RX */
#ifndef CONFIG_SAMA5_EMAC_NRXBUFFERS
# define CONFIG_SAMA5_EMAC_NRXBUFFERS 16
#endif
/* Number of buffer for TX */
/* Number of buffers for TX */
#ifndef CONFIG_SAMA5_EMAC_NTXBUFFERS
# define CONFIG_SAMA5_EMAC_NTXBUFFERS 8
@ -267,7 +267,7 @@ struct sam_emac_s
uint8_t phyaddr; /* PHY address (pre-defined by pins on reset) */
uint16_t txhead; /* Circular buffer head index */
uint16_t txtail; /* Circualr buffer tail index */
uint16_t txtail; /* Circular buffer tail index */
uint16_t rxndx; /* RX index for current processing RX descriptor */
uint8_t *rxbuffer; /* Allocated RX buffers */
@ -2895,7 +2895,7 @@ int sam_emac_initialize(void)
#endif
priv->dev.d_private = (void*)&g_emac; /* Used to recover private state from dev */
/* Create a watchdog for timing polling for and timing of transmisstions */
/* Create a watchdog for timing polling for and timing of transmissions */
priv->txpoll = wd_create();
if (!priv->txpoll)

3589
arch/arm/src/sama5/sam_emacb.c Normal file
View file

File diff suppressed because it is too large Load diff

29
arch/arm/src/sama5/sam_ethernet.c
View file

@ -109,7 +109,7 @@ static inline void up_gmac_initialize(void)
*
****************************************************************************/
#if defined(CONFIG_SAMA5_EMACA) || defined(CONFIG_SAMA5_EMACB)
#if defined(CONFIG_SAMA5_EMACA)
static inline void up_emac_initialize(void)
{
int ret;
@ -119,9 +119,34 @@ static inline void up_emac_initialize(void)
ret = sam_emac_initialize();
if (ret < 0)
{
nlldbg("ERROR: sam_gmac_initialize failed: %d\n", ret);
nlldbg("ERROR: up_emac_initialize failed: %d\n", ret);
}
}
#elif defined(CONFIG_SAMA5_EMACB)
static inline void up_emac_initialize(void)
{
int ret;
#if defined(CONFIG_SAMA5_EMAC0)
/* Initialize the EMAC0 driver */
ret = sam_emac_initialize(EMAC0_INTF);
if (ret < 0)
{
nlldbg("ERROR: up_emac_initialize(EMAC0) failed: %d\n", ret);
}
#endif
#if defined(CONFIG_SAMA5_EMAC1)
/* Initialize the EMAC1 driver */
ret = sam_emac_initialize(EMAC1_INTF);
if (ret < 0)
{
nlldbg("ERROR: up_emac_initialize(EMAC1) failed: %d\n", ret);
}
#endif
}
#else
# define up_emac_initialize()
#endif

8
arch/arm/src/sama5/sam_ethernet.h
View file

@ -51,10 +51,10 @@
************************************************************************************/
/* Definitions for use with sam_phy_boardinitialize */
#if defined(SAMA5_HAVE_EMACA)
#if defined(CONFIG_SAMA5_HAVE_EMACA)
# define GMAC_INTF 0
# define EMAC_INTF 1
#elif defined(SAMA5_HAVE_EMACB)
#elif defined(CONFIG_SAMA5_HAVE_EMACB)
# define EMAC0_INTF 0
# define EMAC1_INTF 1
#endif
@ -239,8 +239,10 @@ int sam_gmac_initialize(void);
*
****************************************************************************/
#if defined(CONFIG_SAMA5_EMACA) || defined(CONFIG_SAMA5_EMACB)
#if defined(CONFIG_SAMA5_EMACA)
int sam_emac_initialize(void);
#elif defined(CONFIG_SAMA5_EMACB)
int sam_emac_initialize(int intf);
#endif
/************************************************************************************

6
drivers/net/Kconfig
View file

@ -292,6 +292,9 @@ config ETH0_PHY_KS8721
config ETH0_PHY_KSZ8051
bool "Micrel KSZ8051 PHY"
config ETH0_PHY_KSZ8081
bool "Micrel KSZ8081 PHY"
config ETH0_PHY_KSZ90x1
bool "Micrel KSZ9021/31 PHY"
@ -326,6 +329,9 @@ config ETH1_PHY_KS8721
config ETH1_PHY_KSZ8051
bool "Micrel KSZ8051 PHY"
config ETH1_PHY_KSZ8081
bool "Micrel KSZ8081 PHY"
config ETH1_PHY_KSZ90x1
bool "Micrel KSZ9021/31 PHY"