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Fix various typos and spelling errors.

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Nathan Hartman 2019-12-12 07:41:51 -06:00 committed by Gregory Nutt
parent 3737aa83fa
commit 9655730ef8
27 changed files with 58 additions and 58 deletions
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8
ChangeLog
View file

@ -3213,7 +3213,7 @@
strings by strerror().
* arch/arm/src/stm32/stm32_usbotghost.c: Finally... the USB OTG FS
appears to handle NAKing correctly.
* configs/stm32f4discovery/*: Added and verifed support for USB OTG FS
* configs/stm32f4discovery/*: Added and verified support for USB OTG FS
host on the STM32F4Discovery board.
* configs/*/defconfig: Remove configuration documentation from config
files. It is redundant, error-prone, and difficult to maintain.
@ -10053,7 +10053,7 @@
stm32_stdclockconfig() in stm32fxxxxx_rcc.c. Doing this I checked
the possible uses of the LSI and the LSE sources: the LSI can be used
for RTC and/or the IWDG, while the LSE only for the RTC (and to output
the MCO1 pin). This change is not verifed for any other platforms.
the MCO1 pin). This change is not verified for any other platforms.
From Leo Aloe3132
* Rename arch_nshinitialize() to board_app_initialize() (2015-03-30).
* ./*.mk, configs/.gitignore, Makefile, boardctl.c, include/nuttx/fs/ioctl,
@ -19507,7 +19507,7 @@
USART_CR3. This was not being done, so calls to TIOCSSINGLEWIRE were
silently failing.
This change checks the state of UE in USART_CR1, clears the UE bit
before writing HDSEL, then re-enables it if neccesary. From Kurt
before writing HDSEL, then re-enables it if necessary. From Kurt
Kiefer (2018-06-14).
* drivers/sensors: Add support for Telair T6713 carbon dioxide
sensor. From Juha Niskanen (2018-06-15).
@ -20035,7 +20035,7 @@
the STM32 RTC and use an external RTC you cannot because the external
RTC also depends on the global CONFIG_RTC. The solution is to add a
new CONFIG_STM32xx_RTC configuration option the permits to you select
or deselect the STM32 RTC but still be able to selecte the external
or deselect the STM32 RTC but still be able to select the external
RTC. From Gregory Nutt (2018-08-08).
* configs/stm32f4discovery/scripts/ld.script: Missing
EXTERN(_vectors) From Gregory Nutt (2018-08-08).

4
Documentation/NuttX.html
View file

@ -6421,11 +6421,11 @@ Mem: 29232 5920 23312 23312
<ul>
<p>
<b>STATUS:</b>
The basic port was code-complete in NuttX-5.19 and verifed in NuttX-6.0.
The basic port was code-complete in NuttX-5.19 and verified in NuttX-6.0.
The port was verified using the OS and NuttShell (NSH) examples under QEMU.
The port is reported to be functional on the <a href="http://bifferos.bizhat.com">Bifferboard</a> as well.
In NuttX 7.1, Lizhuoyi contributed additional keyboard and VGA drivers.
This is a great, stable starting point for anyone interest in fleshing out the x86 port!
This is a great, stable starting point for anyone interested in fleshing out the x86 port!
Refer to the NuttX <a href="https://bitbucket.org/nuttx/nuttx/src/master/boards/x86/qemu/qemu-i486/README.txt" target="_blank">README</a> file for further information.
</p>
</ul>

6
ReleaseNotes
View file

@ -8787,7 +8787,7 @@ detailed bugfix information):
stm32fxxxxx_rcc.c. Doing this I checked the possible uses of the
LSI and the LSE sources: the LSI can be used for RTC and/or the
IWDG, while the LSE only for the RTC (and to output the MCO1 pin).
This change is not verifed for any other platforms. From Leo
This change is not verified for any other platforms. From Leo
Aloe3132
* Tiva Drivers:
@ -19459,7 +19459,7 @@ detailed bugfix information):
use an external RTC you cannot because the external RTC also
depends on the global CONFIG_RTC. The solution is to add a new
CONFIG_STM32xx_RTC configuration option the permits to you select
or deselect the STM32 RTC but still be able to selecte the external
or deselect the STM32 RTC but still be able to select the external
RTC. From Gregory Nutt.
- STM32 F3 I2C: Fix compile error with I2C reset. From Juha
Niskanen.
@ -19467,7 +19467,7 @@ detailed bugfix information):
must be disabled in order to write HDSEL in USART_CR3. This was not
being done, so calls to TIOCSSINGLEWIRE were silently failing.
This change checks the state of UE in USART_CR1, clears the UE bit
before writing HDSEL, then re-enables it if neccesary. From Kurt
before writing HDSEL, then re-enables it if necessary. From Kurt
Kiefer.
- STM32 F7 DMA: DMA macros did not account for the increase from 8
to 16 DMA channels. From Gregory Nutt.

2
arch/arm/src/kinetis/kinetis_timerisr.c
View file

@ -122,7 +122,7 @@ void arm_timer_initialize(void)
regval |= (NVIC_SYSH_PRIORITY_DEFAULT << NVIC_SYSH_PRIORITY_PR15_SHIFT);
putreg32(regval, NVIC_SYSH12_15_PRIORITY);
/* Note that is should not be neccesary to set the SYSTICK clock source:
/* Note that it should not be necessary to set the SYSTICK clock source:
* "The CLKSOURCE bit in SysTick Control and Status register is always set
* to select the core clock."
*/

2
arch/arm/src/lpc17xx_40xx/lpc17_40_sdcard.c
View file

@ -1280,7 +1280,7 @@ static int lpc17_40_interrupt(int irq, void *context, FAR void *arg)
lpc17_40_endtransfer(priv, SDIOWAIT_TRANSFERDONE);
}
/* Otherwise, just disable futher transfer interrupts and
/* Otherwise, just disable further transfer interrupts and
* wait for the DMA complete event.
*/

4
arch/arm/src/sam34/sam4cm_oneshot.h
View file

@ -84,8 +84,8 @@ struct sam_oneshot_s
* the callback */
#ifdef CONFIG_SAM34_FREERUN
volatile uint32_t start_count; /* Stores the value of the freerun counter,
* at each start of the onshot timer. Is neccesary
* to find out if the onshot counter was updated
* at each start of the oneshot timer. Is necessary
* to find out if the oneshot counter was updated
* correctly at the time of the call to
* sam_oneshot_cancel or not. */
#endif

4
arch/arm/src/sama5/sam_oneshot.h
View file

@ -84,8 +84,8 @@ struct sam_oneshot_s
* the callback */
#ifdef CONFIG_SAMA5_FREERUN
volatile uint32_t start_count; /* Stores the value of the freerun counter,
* at each start of the onshot timer. Is neccesary
* to find out if the onshot counter was updated
* at each start of the oneshot timer. Is necessary
* to find out if the oneshot counter was updated
* correctly at the time of the call to
* sam_oneshot_cancel or not. */
#endif

4
arch/arm/src/samv7/sam_oneshot.h
View file

@ -84,8 +84,8 @@ struct sam_oneshot_s
* the callback */
#ifdef CONFIG_SAMV7_FREERUN
volatile uint32_t start_count; /* Stores the value of the freerun counter,
* at each start of the onshot timer. Is neccesary
* to find out if the onshot counter was updated
* at each start of the oneshot timer. Is necessary
* to find out if the oneshot counter was updated
* correctly at the time of the call to
* sam_oneshot_cancel or not. */
#endif

4
arch/arm/src/stm32/stm32_sdio.c
View file

@ -93,7 +93,7 @@
* CONFIG_STM32_SDIO_WIDTH_D1_ONLY - This may be selected to force the
* driver operate with only a single data line (the default is to use
* all 4 SD data lines).
* CONFIG_SDM_DMAPRIO - SDIO DMA priority. This can be selecte if
* CONFIG_SDM_DMAPRIO - SDIO DMA priority. This can be selected if
* CONFIG_STM32_SDIO_DMA is enabled.
* CONFIG_SDIO_XFRDEBUG - Enables some very low-level debug output
* This also requires CONFIG_DEBUG_FS and CONFIG_DEBUG_INFO
@ -1468,7 +1468,7 @@ static int stm32_interrupt(int irq, void *context, FAR void *arg)
stm32_endtransfer(priv, SDIOWAIT_TRANSFERDONE);
}
/* Otherwise, just disable futher transfer interrupts and
/* Otherwise, just disable further transfer interrupts and
* wait for the DMA complete event.
*/

4
arch/arm/src/stm32f7/stm32_sdmmc.c
View file

@ -95,7 +95,7 @@
* CONFIG_SDMMC1/2_WIDTH_D1_ONLY - This may be selected to force the driver
* operate with only a single data line (the default is to use all
* 4 SD data lines).
* CONFIG_SDMMMC_DMAPRIO - SDMMC DMA priority. This can be selecte if
* CONFIG_SDMMC_DMAPRIO - SDMMC DMA priority. This can be selected if
* CONFIG_STM32F7_SDMMC_DMA is enabled.
* CONFIG_CONFIG_STM32F7_SDMMC_XFRDEBUG - Enables some very low-level debug
* output. This also requires CONFIG_DEBUG_FS and CONFIG_DEBUG_INFO
@ -1723,7 +1723,7 @@ static int stm32_sdmmc_interrupt(int irq, void *context, void *arg)
stm32_endtransfer(priv, SDIOWAIT_TRANSFERDONE);
}
/* Otherwise, just disable futher transfer interrupts and
/* Otherwise, just disable further transfer interrupts and
* wait for the DMA complete event.
*/

4
arch/arm/src/stm32l4/stm32l4_sdmmc.c
View file

@ -94,7 +94,7 @@
* CONFIG_SDMMC1/2_WIDTH_D1_ONLY - This may be selected to force the driver
* operate with only a single data line (the default is to use all
* 4 SD data lines).
* CONFIG_SDMMMC_DMAPRIO - SDMMC DMA priority. This can be selecte if
* CONFIG_SDMMC_DMAPRIO - SDMMC DMA priority. This can be selected if
* CONFIG_STM32L4_SDMMC_DMA is enabled.
* CONFIG_CONFIG_STM32L4_SDMMC_XFRDEBUG - Enables some very low-level
* debug output. This also requires CONFIG_DEBUG_FS and
@ -1575,7 +1575,7 @@ static int stm32_sdmmc_interrupt(int irq, void *context, void *arg)
stm32_endtransfer(priv, SDIOWAIT_TRANSFERDONE);
}
/* Otherwise, just disable futher transfer interrupts and
/* Otherwise, just disable further transfer interrupts and
* wait for the DMA complete event.
*/

2
arch/arm/src/tms570/tms570_selftest.c
View file

@ -242,7 +242,7 @@ void tms570_memtest_selftest(void)
* Name: tms570_memtest_start
*
* Description:
* Start the memory test on the selecte set of RAMs. This test does not
* Start the memory test on the selected set of RAMs. This test does not
* return until the memory test is completed.
*
* Input Parameters:

2
arch/arm/src/xmc4/xmc4_timerisr.c
View file

@ -140,7 +140,7 @@ void arm_timer_initialize(void)
putreg32(regval, NVIC_SYSH12_15_PRIORITY);
#ifndef USE_STDBY_CLOCK
/* Note that is should not be neccesary to set the SYSTICK clock source:
/* Note that it should not be necessary to set the SYSTICK clock source:
* "The CLKSOURCE bit in SysTick Control and Status register is always set
* to select the core clock."
*

4
arch/mips/src/pic32mz/pic32mz-ethernet.c
View file

@ -179,8 +179,8 @@
/* Debug Configuration *****************************************************/
/* Register/Descriptor debug -- can only happen of CONFIG_DEBUG_FEATURES is
* selecte. This will probably generate much more output than you care to see.
/* Register/Descriptor debug -- can only happen if CONFIG_DEBUG_FEATURES is
* selected. This will probably generate much more output than you care to see.
*/
#ifndef CONFIG_DEBUG_FEATURES

4
boards/arm/imx6/sabre-6quad/README.txt
View file

@ -574,9 +574,9 @@ A: Yes with the following modifications to the procedure above.
gdb> mon go
That will restart U-Boot and you have to press ENTER in the terminal
window to stop U-Boot. Restarting U-Boot is a necesary part of the
window to stop U-Boot. Restarting U-Boot is a necessary part of the
restart process because you need to put the hardware back in its initial
state before running NuttX
state before running NuttX.
Then this will restart the debug session just as before:

16
boards/arm/samv7/samv71-xult/README.txt
View file

@ -144,9 +144,9 @@ to a particular configuration.
as of this writing. See discussion in include/nuttx/spi/slave.h and
in the section entitle "SPI Slave" below.
9. A QSPI FLASH driver was added and verifed on 2015-11-10. This driver
9. A QSPI FLASH driver was added and verified on 2015-11-10. This driver
operated in the memory mapped Serial Memory Mode (SMM). See the
"S25FL116K QuadSPI FLASH" section below for futher information.
"S25FL116K QuadSPI FLASH" section below for further information.
10. On-chip FLASH support as added and verified on 2015-11-13. See the
"Program FLASH Access" section below for further information.
@ -174,7 +174,7 @@ use either the VCOM or an external RS-232 driver. Here are some options.
------ ------ ------- ------- --------
In this configuration, an external RS232 driver can also be used
instead of the shield. Simply connext as follows:
instead of the shield. Simply connect as follows:
--------- -----------
Arduino RS-232
@ -489,7 +489,7 @@ The configuration data device will appear at /dev/config.
S25FL116K QuadSPI FLASH
====================
A QSPI FLASH driver was added and verifed on 2015-11-07. This driver
A QSPI FLASH driver was added and verified on 2015-11-07. This driver
operated in the memory mapped Serial Memory Mode (SMM). These
configuration options were enabled to test QSPI:
@ -575,7 +575,7 @@ wrapped as a character driver and available as /dev/mtd0.
Program FLASH Access
====================
An on-chip FLASH driver was added and verifed on 2015-11-13. These
An on-chip FLASH driver was added and verified on 2015-11-13. These
configuration options were enabled to test the on-chip FLASH support:
CONFIG_MTD_PROGMEM=y
@ -767,9 +767,9 @@ Cache-Related Issues
I- and D-Caches can be enabled but the D-Cache must be enabled in write-
through mode. This is to work around issues with the RX and TX descriptors
with are 8-bytes in size. But the D-Cache cache line size is 32-bytes.
which are 8-bytes in size. But the D-Cache cache line size is 32-bytes.
That means that you cannot reload, clean or invalidate a descriptor without
also effecting three neighboring descriptors. Setting write through mode
also affecting three neighboring descriptors. Setting write through mode
eliminates the need for cleaning the D-Cache. If only reloading and
invalidating are done, then there is no problem.
@ -1191,7 +1191,7 @@ the connectors worked. Let me share this so that, perhaps, I can save you
the same embarrassment:
- The maXTouch Xplained Pro has an Omron XF2M-5015-1A connector. There is a
black bar at back (toward the baord). Raise that bar and insert the cable
black bar at back (toward the board). Raise that bar and insert the cable
with the contacts away from the board. Lower that bar to lock the cable
in place.

2
boards/z80/ez80/ez80f910200zco/README.txt
View file

@ -62,7 +62,7 @@ Version 5.2.1
Version 5.3.0
I verifed compilation using 5.30 on June 2, 2019. To use this version,
I verified compilation using 5.30 on June 2, 2019. To use this version,
I had to make spurious modification to the implementation of gmtimer() to
work around an internal compiler error. I have still not verified that
are no errors in the compiled code.

2
drivers/input/ft5x06.c
View file

@ -9,7 +9,7 @@
* Dec. 18, 2012
*
* Some of this driver was developed with input from NXP sample code for
* the LPCXpresso-LPC54628 baord. That sample code as a compatible BSD
* the LPCXpresso-LPC54628 board. That sample code as a compatible BSD
* license:
*
* Copyright (c) 2016, Freescale Semiconductor, Inc.

2
drivers/input/ft5x06.h
View file

@ -9,7 +9,7 @@
* Dec. 18, 2012
*
* Some of this driver was developed with input from NXP sample code for
* the LPCXpresso-LPC54628 baord. That sample code as a compatible BSD
* the LPCXpresso-LPC54628 board. That sample code as a compatible BSD
* license:
*
* Copyright (c) 2016, Freescale Semiconductor, Inc.

2
drivers/net/telnet.c
View file

@ -628,7 +628,7 @@ static bool telnet_putchar(FAR struct telnet_dev_s *priv, uint8_t ch,
register int index;
bool ret = false;
/* Ignore carriage returns (we will put these in automatically as necesary) */
/* Ignore carriage returns (we will put these in automatically as necessary) */
if (ch != ISO_cr)
{

2
fs/nxffs/nxffs.h
View file

@ -955,7 +955,7 @@ int nxffs_wrreserve(FAR struct nxffs_volume_s *volume, size_t size);
*
* Input Parameters:
* volume - Describes the NXFFS volume
* size - The size of the object to be verifed.
* size - The size of the object to be verified.
*
* Returned Value:
* Zero is returned on success. Otherwise, a negated errno value is

2
fs/nxffs/nxffs_write.c
View file

@ -835,7 +835,7 @@ int nxffs_wrreserve(FAR struct nxffs_volume_s *volume, size_t size)
*
* Input Parameters:
* volume - Describes the NXFFS volume
* size - The size of the object to be verifed.
* size - The size of the object to be verified.
*
* Returned Value:
* Zero is returned on success. Otherwise, a negated errno value is

2
include/nuttx/sched_note.h
View file

@ -310,7 +310,7 @@ void sched_note_spinabort(FAR struct tcb_s *tcb, FAR volatile void *spinlock);
*
* Description:
* Remove the next note from the tail of the circular buffer. The note
* is also removed from the circular buffer to make room for futher notes.
* is also removed from the circular buffer to make room for further notes.
*
* Input Parameters:
* buffer - Location to return the next note

2
net/icmp/icmp_sendto.c
View file

@ -410,7 +410,7 @@ ssize_t icmp_sendto(FAR struct socket *psock, FAR const void *buf, size_t len,
* packets from the read-ahead buffer.
*
* REVISIT: How to we free up any lingering reponses if there are no
* futher pings?
* further pings?
*/
icmp = (FAR struct icmp_hdr_s *)buf;

2
net/icmpv6/icmpv6_sendto.c
View file

@ -401,7 +401,7 @@ ssize_t icmpv6_sendto(FAR struct socket *psock, FAR const void *buf, size_t len,
* packets from the read-ahead buffer.
*
* REVISIT: How to we free up any lingering reponses if there are no
* futher pings?
* further pings?
*/
icmpv6 = (FAR struct icmpv6_echo_request_s *)buf;

2
sched/sched/sched_note.c
View file

@ -594,7 +594,7 @@ void sched_note_spinabort(FAR struct tcb_s *tcb, FAR volatile void *spinlock)
*
* Description:
* Remove the next note from the tail of the circular buffer. The note
* is also removed from the circular buffer to make room for futher notes.
* is also removed from the circular buffer to make room for further notes.
*
* Input Parameters:
* buffer - Location to return the next note

2
tools/Makefile.host
View file

@ -182,7 +182,7 @@ nxstyle: nxstyle$(HOSTEXEEXT)
endif
# initialconfig - Create a barebones .config file sufficient only for
# instantiating the symbolic links necesary to do a real configuration
# instantiating the symbolic links necessary to do a real configuration
# from scratch.
initialconfig$(HOSTEXEEXT): initialconfig.c