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sched/: Make more naming consistent

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Rename various functions per the quidelines of https://cwiki.apache.org/confluence/display/NUTTX/Naming+of+OS+Internal+Functions

    nxsem_setprotocol -> nxsem_set_protocol
    nxsem_getprotocol -> nxsem_get_protocol
    nxsem_getvalue -> nxsem_get_value
This commit is contained in:
Gregory Nutt 2020-05-17 07:56:21 -06:00 committed by Alan Carvalho de Assis
parent d938b50969
commit a569006fd8
192 changed files with 288 additions and 288 deletions
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2
arch/arm/src/am335x/am335x_i2c.c
View file

@ -763,7 +763,7 @@ static inline void am335x_i2c_sem_init(FAR struct am335x_i2c_priv_s *priv)
*/
nxsem_init(&priv->sem_isr, 0, 0);
nxsem_setprotocol(&priv->sem_isr, SEM_PRIO_NONE);
nxsem_set_protocol(&priv->sem_isr, SEM_PRIO_NONE);
#endif
}

2
arch/arm/src/cxd56xx/cxd56_ge2d.c
View file

@ -248,7 +248,7 @@ int cxd56_ge2dinitialize(FAR const char *devname)
nxsem_init(&g_lock, 0, 1);
nxsem_init(&g_wait, 0, 0);
nxsem_setprotocol(&g_wait, SEM_PRIO_NONE);
nxsem_set_protocol(&g_wait, SEM_PRIO_NONE);
ret = register_driver(devname, &g_ge2dfops, 0666, NULL);
if (ret != 0)

2
arch/arm/src/cxd56xx/cxd56_i2c.c
View file

@ -619,7 +619,7 @@ static int cxd56_i2c_transfer(FAR struct i2c_master_s *dev,
* be performed normally.
*/
ret = nxsem_getvalue(&priv->wait, &semval);
ret = nxsem_get_value(&priv->wait, &semval);
DEBUGASSERT(ret == OK && semval == 0);
/* Disable clock gating (clock enable) */

2
arch/arm/src/cxd56xx/cxd56_sdhci.c
View file

@ -1423,7 +1423,7 @@ static void cxd56_sdio_sdhci_reset(FAR struct sdio_dev_s *dev)
* priority inheritance enabled.
*/
nxsem_setprotocol(&priv->waitsem, SEM_PRIO_NONE);
nxsem_set_protocol(&priv->waitsem, SEM_PRIO_NONE);
/* Create a watchdog timer */

2
arch/arm/src/efm32/efm32_i2c.c
View file

@ -702,7 +702,7 @@ static inline void efm32_i2c_sem_init(FAR struct efm32_i2c_priv_s *priv)
*/
nxsem_init(&priv->sem_isr, 0, 0);
nxsem_setprotocol(&priv->sem_isr, SEM_PRIO_NONE);
nxsem_set_protocol(&priv->sem_isr, SEM_PRIO_NONE);
#endif
}

4
arch/arm/src/efm32/efm32_spi.c
View file

@ -1638,8 +1638,8 @@ static int spi_portinitialize(struct efm32_spidev_s *priv)
* priority inheritance enabled.
*/
nxsem_setprotocol(&priv->rxdmasem, SEM_PRIO_NONE);
nxsem_setprotocol(&priv->txdmasem, SEM_PRIO_NONE);
nxsem_set_protocol(&priv->rxdmasem, SEM_PRIO_NONE);
nxsem_set_protocol(&priv->txdmasem, SEM_PRIO_NONE);
#endif
/* Enable SPI */

4
arch/arm/src/efm32/efm32_usbhost.c
View file

@ -5287,7 +5287,7 @@ static inline void efm32_sw_initialize(FAR struct efm32_usbhost_s *priv)
* priority inheritance enabled.
*/
nxsem_setprotocol(&priv->pscsem, SEM_PRIO_NONE);
nxsem_set_protocol(&priv->pscsem, SEM_PRIO_NONE);
/* Initialize the driver state data */
@ -5312,7 +5312,7 @@ static inline void efm32_sw_initialize(FAR struct efm32_usbhost_s *priv)
*/
nxsem_init(&chan->waitsem, 0, 0);
nxsem_setprotocol(&chan->waitsem, SEM_PRIO_NONE);
nxsem_set_protocol(&chan->waitsem, SEM_PRIO_NONE);
}
}

2
arch/arm/src/imx1/imx_spi.c
View file

@ -1114,7 +1114,7 @@ FAR struct spi_dev_s *imx_spibus_initialize(int port)
*/
nxsem_init(&priv->waitsem, 0, 0);
nxsem_setprotocol(&priv->waitsem, SEM_PRIO_NONE);
nxsem_set_protocol(&priv->waitsem, SEM_PRIO_NONE);
#endif
nxsem_init(&priv->exclsem, 0, 1);

2
arch/arm/src/imx6/imx_ecspi.c
View file

@ -1291,7 +1291,7 @@ FAR struct spi_dev_s *imx_spibus_initialize(int port)
*/
nxsem_init(&priv->waitsem, 0, 0);
nxsem_setprotocol(&priv->waitsem, SEM_PRIO_NONE);
nxsem_set_protocol(&priv->waitsem, SEM_PRIO_NONE);
#endif
nxsem_init(&priv->exclsem, 0, 1);

2
arch/arm/src/imxrt/imxrt_edma.c
View file

@ -773,7 +773,7 @@ void weak_function arm_dma_initialize(void)
* hence, should not have priority inheritance enabled.
*/
nxsem_setprotocol(&g_edma.dsem, SEM_PRIO_NONE);
nxsem_set_protocol(&g_edma.dsem, SEM_PRIO_NONE);
/* Initialize the list of free TCDs from the pool of pre-allocated TCDs. */

6
arch/arm/src/imxrt/imxrt_ehci.c
View file

@ -4036,7 +4036,7 @@ static int imxrt_epalloc(FAR struct usbhost_driver_s *drvr,
*/
nxsem_init(&epinfo->iocsem, 0, 0);
nxsem_setprotocol(&epinfo->iocsem, SEM_PRIO_NONE);
nxsem_set_protocol(&epinfo->iocsem, SEM_PRIO_NONE);
/* Success.. return an opaque reference to the endpoint information
* structure instance
@ -5058,7 +5058,7 @@ FAR struct usbhost_connection_s *imxrt_ehci_initialize(int controller)
* priority inheritance enabled.
*/
nxsem_setprotocol(&g_ehci.pscsem, SEM_PRIO_NONE);
nxsem_set_protocol(&g_ehci.pscsem, SEM_PRIO_NONE);
/* Initialize EP0 */
@ -5102,7 +5102,7 @@ FAR struct usbhost_connection_s *imxrt_ehci_initialize(int controller)
*/
nxsem_init(&rhport->ep0.iocsem, 0, 0);
nxsem_setprotocol(&rhport->ep0.iocsem, SEM_PRIO_NONE);
nxsem_set_protocol(&rhport->ep0.iocsem, SEM_PRIO_NONE);
/* Initialize the public port representation */

2
arch/arm/src/imxrt/imxrt_lpi2c.c
View file

@ -877,7 +877,7 @@ static inline void imxrt_lpi2c_sem_init(FAR struct imxrt_lpi2c_priv_s *priv)
*/
nxsem_init(&priv->sem_isr, 0, 0);
nxsem_setprotocol(&priv->sem_isr, SEM_PRIO_NONE);
nxsem_set_protocol(&priv->sem_isr, SEM_PRIO_NONE);
#endif
}

2
arch/arm/src/imxrt/imxrt_usdhc.c
View file

@ -3117,7 +3117,7 @@ FAR struct sdio_dev_s *imxrt_usdhc_initialize(int slotno)
* have priority inheritance enabled.
*/
nxsem_setprotocol(&priv->waitsem, SEM_PRIO_NONE);
nxsem_set_protocol(&priv->waitsem, SEM_PRIO_NONE);
/* Create a watchdog timer */

2
arch/arm/src/kinetis/kinetis_i2c.c
View file

@ -332,7 +332,7 @@ static inline void kinetis_i2c_sem_init(FAR struct kinetis_i2cdev_s *priv)
*/
nxsem_init(&priv->wait, 0, 0);
nxsem_setprotocol(&priv->wait, SEM_PRIO_NONE);
nxsem_set_protocol(&priv->wait, SEM_PRIO_NONE);
}
/****************************************************************************

2
arch/arm/src/kinetis/kinetis_sdhc.c
View file

@ -2877,7 +2877,7 @@ FAR struct sdio_dev_s *sdhc_initialize(int slotno)
* priority inheritance enabled.
*/
nxsem_setprotocol(&priv->waitsem, SEM_PRIO_NONE);
nxsem_set_protocol(&priv->waitsem, SEM_PRIO_NONE);
/* Create a watchdog timer */

2
arch/arm/src/lc823450/lc823450_sdc.c
View file

@ -699,7 +699,7 @@ int lc823450_sdc_locked(void)
for (i = 0; i < 2; i++)
{
nxsem_getvalue(&_sdc_sem[i], &val);
nxsem_get_value(&_sdc_sem[i], &val);
if (1 != val)
{
ret = 1;

2
arch/arm/src/lpc17xx_40xx/lpc17_40_i2c.c
View file

@ -627,7 +627,7 @@ struct i2c_master_s *lpc17_40_i2cbus_initialize(int port)
* priority inheritance enabled.
*/
nxsem_setprotocol(&priv->wait, SEM_PRIO_NONE);
nxsem_set_protocol(&priv->wait, SEM_PRIO_NONE);
/* Allocate a watchdog timer */

2
arch/arm/src/lpc17xx_40xx/lpc17_40_sdcard.c
View file

@ -2792,7 +2792,7 @@ FAR struct sdio_dev_s *sdio_initialize(int slotno)
* priority inheritance enabled.
*/
nxsem_setprotocol(&priv->waitsem, SEM_PRIO_NONE);
nxsem_set_protocol(&priv->waitsem, SEM_PRIO_NONE);
/* Create a watchdog timer */

6
arch/arm/src/lpc17xx_40xx/lpc17_40_usbhost.c
View file

@ -2360,7 +2360,7 @@ static int lpc17_40_epalloc(struct usbhost_driver_s *drvr,
*/
nxsem_init(&ed->wdhsem, 0, 0);
nxsem_setprotocol(&ed->wdhsem, SEM_PRIO_NONE);
nxsem_set_protocol(&ed->wdhsem, SEM_PRIO_NONE);
/* Link the common tail TD to the ED's TD list */
@ -3804,7 +3804,7 @@ struct usbhost_connection_s *lpc17_40_usbhost_initialize(int controller)
* have priority inheritance enabled.
*/
nxsem_setprotocol(&priv->pscsem, SEM_PRIO_NONE);
nxsem_set_protocol(&priv->pscsem, SEM_PRIO_NONE);
#ifndef CONFIG_USBHOST_INT_DISABLE
priv->ininterval = MAX_PERINTERVAL;
@ -3902,7 +3902,7 @@ struct usbhost_connection_s *lpc17_40_usbhost_initialize(int controller)
*/
nxsem_init(&EDCTRL->wdhsem, 0, 0);
nxsem_setprotocol(&EDCTRL->wdhsem, SEM_PRIO_NONE);
nxsem_set_protocol(&EDCTRL->wdhsem, SEM_PRIO_NONE);
/* Initialize user-configurable EDs */

2
arch/arm/src/lpc2378/lpc23xx_i2c.c
View file

@ -588,7 +588,7 @@ struct i2c_master_s *lpc2378_i2cbus_initialize(int port)
* priority inheritance enabled.
*/
nxsem_setprotocol(&priv->wait, SEM_PRIO_NONE);
nxsem_set_protocol(&priv->wait, SEM_PRIO_NONE);
/* Allocate a watchdog timer */

6
arch/arm/src/lpc31xx/lpc31_ehci.c
View file

@ -4043,7 +4043,7 @@ static int lpc31_epalloc(FAR struct usbhost_driver_s *drvr,
*/
nxsem_init(&epinfo->iocsem, 0, 0);
nxsem_setprotocol(&epinfo->iocsem, SEM_PRIO_NONE);
nxsem_set_protocol(&epinfo->iocsem, SEM_PRIO_NONE);
/* Success.. return an opaque reference to the endpoint information
* structure instance
@ -5064,7 +5064,7 @@ FAR struct usbhost_connection_s *lpc31_ehci_initialize(int controller)
* priority inheritance enabled.
*/
nxsem_setprotocol(&g_ehci.pscsem, SEM_PRIO_NONE);
nxsem_set_protocol(&g_ehci.pscsem, SEM_PRIO_NONE);
/* Initialize EP0 */
@ -5108,7 +5108,7 @@ FAR struct usbhost_connection_s *lpc31_ehci_initialize(int controller)
*/
nxsem_init(&rhport->ep0.iocsem, 0, 0);
nxsem_setprotocol(&rhport->iocsem, SEM_PRIO_NONE);
nxsem_set_protocol(&rhport->iocsem, SEM_PRIO_NONE);
/* Initialize the public port representation */

2
arch/arm/src/lpc31xx/lpc31_i2c.c
View file

@ -558,7 +558,7 @@ struct i2c_master_s *lpc31_i2cbus_initialize(int port)
* priority inheritance enabled.
*/
nxsem_setprotocol(&priv->wait, SEM_PRIO_NONE);
nxsem_set_protocol(&priv->wait, SEM_PRIO_NONE);
/* Enable I2C system clocks */

6
arch/arm/src/lpc43xx/lpc43_ehci.c
View file

@ -3881,7 +3881,7 @@ static int lpc43_epalloc(FAR struct usbhost_driver_s *drvr,
*/
nxsem_init(&epinfo->iocsem, 0, 0);
nxsem_setprotocol(&epinfo->iocsem, SEM_PRIO_NONE);
nxsem_set_protocol(&epinfo->iocsem, SEM_PRIO_NONE);
/* Success.. return an opaque reference to the endpoint information
* structure instance
@ -4896,7 +4896,7 @@ FAR struct usbhost_connection_s *lpc43_ehci_initialize(int controller)
* priority inheritance enabled.
*/
nxsem_setprotocol(&g_ehci.pscsem, SEM_PRIO_NONE);
nxsem_set_protocol(&g_ehci.pscsem, SEM_PRIO_NONE);
/* Initialize EP0 */
@ -4940,7 +4940,7 @@ FAR struct usbhost_connection_s *lpc43_ehci_initialize(int controller)
*/
nxsem_init(&rhport->ep0.iocsem, 0, 0);
nxsem_setprotocol(&rhport->ep0.iocsem, SEM_PRIO_NONE);
nxsem_set_protocol(&rhport->ep0.iocsem, SEM_PRIO_NONE);
/* Initialize the public port representation */

2
arch/arm/src/lpc43xx/lpc43_i2c.c
View file

@ -533,7 +533,7 @@ struct i2c_master_s *lpc43_i2cbus_initialize(int port)
* priority inheritance enabled.
*/
nxsem_setprotocol(&priv->wait, SEM_PRIO_NONE);
nxsem_set_protocol(&priv->wait, SEM_PRIO_NONE);
/* Allocate a watchdog timer */

2
arch/arm/src/lpc43xx/lpc43_sdmmc.c
View file

@ -2881,7 +2881,7 @@ FAR struct sdio_dev_s *lpc43_sdmmc_initialize(int slotno)
* priority inheritance enabled.
*/
nxsem_setprotocol(&priv->waitsem, SEM_PRIO_NONE);
nxsem_set_protocol(&priv->waitsem, SEM_PRIO_NONE);
/* Create a watchdog timer */

2
arch/arm/src/lpc54xx/lpc54_i2c_master.c
View file

@ -1213,7 +1213,7 @@ struct i2c_master_s *lpc54_i2cbus_initialize(int port)
* priority inheritance enabled.
*/
nxsem_setprotocol(&priv->waitsem, SEM_PRIO_NONE);
nxsem_set_protocol(&priv->waitsem, SEM_PRIO_NONE);
#endif
/* Allocate a watchdog timer */

2
arch/arm/src/lpc54xx/lpc54_sdmmc.c
View file

@ -2888,7 +2888,7 @@ FAR struct sdio_dev_s *lpc54_sdmmc_initialize(int slotno)
* priority inheritance enabled.
*/
nxsem_setprotocol(&priv->waitsem, SEM_PRIO_NONE);
nxsem_set_protocol(&priv->waitsem, SEM_PRIO_NONE);
/* Create a watchdog timer */

6
arch/arm/src/lpc54xx/lpc54_usb0_ohci.c
View file

@ -2445,7 +2445,7 @@ static int lpc54_epalloc(struct usbhost_driver_s *drvr,
*/
nxsem_init(&ed->wdhsem, 0, 0);
nxsem_setprotocol(&ed->wdhsem, SEM_PRIO_NONE);
nxsem_set_protocol(&ed->wdhsem, SEM_PRIO_NONE);
/* Link the common tail TD to the ED's TD list */
@ -3880,7 +3880,7 @@ struct usbhost_connection_s *lpc54_usbhost_initialize(int controller)
* priority inheritance enabled.
*/
nxsem_setprotocol(&priv->pscsem, SEM_PRIO_NONE);
nxsem_set_protocol(&priv->pscsem, SEM_PRIO_NONE);
#ifndef CONFIG_OHCI_INT_DISABLE
priv->ininterval = MAX_PERINTERVAL;
@ -3970,7 +3970,7 @@ struct usbhost_connection_s *lpc54_usbhost_initialize(int controller)
*/
nxsem_init(&EDCTRL->wdhsem, 0, 0);
nxsem_setprotocol(&EDCTRL->wdhsem, SEM_PRIO_NONE);
nxsem_set_protocol(&EDCTRL->wdhsem, SEM_PRIO_NONE);
/* Initialize user-configurable EDs */

2
arch/arm/src/nrf52/nrf52_i2c.c
View file

@ -597,7 +597,7 @@ static int nrf52_i2c_sem_init(FAR struct nrf52_i2c_priv_s *priv)
*/
nxsem_init(&priv->sem_isr, 0, 0);
nxsem_setprotocol(&priv->sem_isr, SEM_PRIO_NONE);
nxsem_set_protocol(&priv->sem_isr, SEM_PRIO_NONE);
#endif
return OK;

2
arch/arm/src/nrf52/nrf52_radio.c
View file

@ -1171,7 +1171,7 @@ nrf52_radio_initialize(int intf, FAR struct nrf52_radio_board_s *board)
*/
nxsem_init(&dev->sem_isr, 0, 0);
nxsem_setprotocol(&dev->sem_isr, SEM_PRIO_NONE);
nxsem_set_protocol(&dev->sem_isr, SEM_PRIO_NONE);
/* Connect board-specific data */

4
arch/arm/src/nrf52/nrf52_rng.c
View file

@ -144,10 +144,10 @@ static int nrf52_rng_initialize(void)
memset(&g_rngdev, 0, sizeof(struct rng_dev_s));
nxsem_init(&g_rngdev.rd_sem, 0, 0);
nxsem_setprotocol(&g_rngdev.rd_sem, SEM_PRIO_NONE);
nxsem_set_protocol(&g_rngdev.rd_sem, SEM_PRIO_NONE);
nxsem_init(&g_rngdev.excl_sem, 0, 1);
nxsem_setprotocol(&g_rngdev.excl_sem, SEM_PRIO_NONE);
nxsem_set_protocol(&g_rngdev.excl_sem, SEM_PRIO_NONE);
_info("Ready to stop\n");
nrf52_rng_stop();

2
arch/arm/src/nrf52/nrf52_spi.c
View file

@ -994,7 +994,7 @@ FAR struct spi_dev_s *nrf52_spibus_initialize(int port)
*/
nxsem_init(&priv->sem_isr, 0, 0);
nxsem_setprotocol(&priv->sem_isr, SEM_PRIO_NONE);
nxsem_set_protocol(&priv->sem_isr, SEM_PRIO_NONE);
/* Attach SPI interrupt */

2
arch/arm/src/s32k1xx/s32k1xx_edma.c
View file

@ -743,7 +743,7 @@ void weak_function arm_dma_initialize(void)
* hence, should not have priority inheritance enabled.
*/
nxsem_setprotocol(&g_edma.dsem, SEM_PRIO_NONE);
nxsem_set_protocol(&g_edma.dsem, SEM_PRIO_NONE);
/* Initialize the list of free TCDs from the pool of pre-allocated TCDs. */

2
arch/arm/src/s32k1xx/s32k1xx_lpi2c.c
View file

@ -789,7 +789,7 @@ static inline void
*/
nxsem_init(&priv->sem_isr, 0, 0);
nxsem_setprotocol(&priv->sem_isr, SEM_PRIO_NONE);
nxsem_set_protocol(&priv->sem_isr, SEM_PRIO_NONE);
#endif
}

2
arch/arm/src/sam34/sam_hsmci.c
View file

@ -2719,7 +2719,7 @@ FAR struct sdio_dev_s *sdio_initialize(int slotno)
* priority inheritance enabled.
*/
nxsem_setprotocol(&priv->waitsem, SEM_PRIO_NONE);
nxsem_set_protocol(&priv->waitsem, SEM_PRIO_NONE);
/* Create a watchdog timer */

2
arch/arm/src/sam34/sam_spi.c
View file

@ -1888,7 +1888,7 @@ struct spi_dev_s *sam_spibus_initialize(int port)
*/
nxsem_init(&spics->dmawait, 0, 0);
nxsem_setprotocol(&spics->dmawait, SEM_PRIO_NONE);
nxsem_set_protocol(&spics->dmawait, SEM_PRIO_NONE);
/* Create a watchdog time to catch DMA timeouts */

2
arch/arm/src/sam34/sam_twi.c
View file

@ -981,7 +981,7 @@ struct i2c_master_s *sam_i2cbus_initialize(int bus)
* priority inheritance enabled.
*/
nxsem_setprotocol(&priv->waitsem, SEM_PRIO_NONE);
nxsem_set_protocol(&priv->waitsem, SEM_PRIO_NONE);
/* Allocate a watchdog timer */

6
arch/arm/src/sama5/sam_ehci.c
View file

@ -3800,7 +3800,7 @@ static int sam_epalloc(FAR struct usbhost_driver_s *drvr,
*/
nxsem_init(&epinfo->iocsem, 0, 0);
nxsem_setprotocol(&epinfo->iocsem, SEM_PRIO_NONE);
nxsem_set_protocol(&epinfo->iocsem, SEM_PRIO_NONE);
/* Success.. return an opaque reference to the endpoint information
* structure instance
@ -4874,7 +4874,7 @@ FAR struct usbhost_connection_s *sam_ehci_initialize(int controller)
* priority inheritance enabled.
*/
nxsem_setprotocol(&g_ehci.pscsem, SEM_PRIO_NONE);
nxsem_set_protocol(&g_ehci.pscsem, SEM_PRIO_NONE);
/* Initialize EP0 */
@ -4918,7 +4918,7 @@ FAR struct usbhost_connection_s *sam_ehci_initialize(int controller)
*/
nxsem_init(&rhport->ep0.iocsem, 0, 0);
nxsem_setprotocol(&rhport->ep0.iocsem, SEM_PRIO_NONE);
nxsem_set_protocol(&rhport->ep0.iocsem, SEM_PRIO_NONE);
/* Initialize the public port representation */

2
arch/arm/src/sama5/sam_hsmci.c
View file

@ -3344,7 +3344,7 @@ FAR struct sdio_dev_s *sdio_initialize(int slotno)
* priority inheritance enabled.
*/
nxsem_setprotocol(&priv->waitsem, SEM_PRIO_NONE);
nxsem_set_protocol(&priv->waitsem, SEM_PRIO_NONE);
/* Create a watchdog timer */

4
arch/arm/src/sama5/sam_nand.c
View file

@ -2976,7 +2976,7 @@ struct mtd_dev_s *sam_nand_initialize(int cs)
*/
nxsem_init(&priv->waitsem, 0, 0);
nxsem_setprotocol(&priv->waitsem, SEM_PRIO_NONE);
nxsem_set_protocol(&priv->waitsem, SEM_PRIO_NONE);
#endif
/* Perform one-time, global NFC/PMECC initialization */
@ -2995,7 +2995,7 @@ struct mtd_dev_s *sam_nand_initialize(int cs)
*/
nxsem_init(&g_nand.waitsem, 0, 0);
nxsem_setprotocol(&g_nand.waitsem, SEM_PRIO_NONE);
nxsem_set_protocol(&g_nand.waitsem, SEM_PRIO_NONE);
#endif
/* Enable the NAND FLASH Controller (The NFC is always used) */

4
arch/arm/src/sama5/sam_ohci.c
View file

@ -2718,7 +2718,7 @@ static int sam_epalloc(struct usbhost_driver_s *drvr,
* priority inheritance enabled.
*/
nxsem_setprotocol(&eplist->wdhsem, SEM_PRIO_NONE);
nxsem_set_protocol(&eplist->wdhsem, SEM_PRIO_NONE);
/* We must have exclusive access to the ED pool, the bulk list, the
* periodic list, and the interrupt table.
@ -4020,7 +4020,7 @@ struct usbhost_connection_s *sam_ohci_initialize(int controller)
* priority inheritance enabled.
*/
nxsem_setprotocol(&g_ohci.pscsem, SEM_PRIO_NONE);
nxsem_set_protocol(&g_ohci.pscsem, SEM_PRIO_NONE);
#ifndef CONFIG_USBHOST_INT_DISABLE
g_ohci.ininterval = MAX_PERINTERVAL;

2
arch/arm/src/sama5/sam_spi.c
View file

@ -1817,7 +1817,7 @@ struct spi_dev_s *sam_spibus_initialize(int port)
*/
nxsem_init(&spics->dmawait, 0, 0);
nxsem_setprotocol(&spics->dmawait, SEM_PRIO_NONE);
nxsem_set_protocol(&spics->dmawait, SEM_PRIO_NONE);
/* Create a watchdog time to catch DMA timeouts */

2
arch/arm/src/sama5/sam_trng.c
View file

@ -360,7 +360,7 @@ static int sam_rng_initialize(void)
* priority inheritance enabled.
*/
nxsem_setprotocol(&g_trngdev.waitsem, SEM_PRIO_NONE);
nxsem_set_protocol(&g_trngdev.waitsem, SEM_PRIO_NONE);
/* Enable clocking to the TRNG */

2
arch/arm/src/sama5/sam_tsd.c
View file

@ -1664,7 +1664,7 @@ int sam_tsd_register(struct sam_adc_s *adc, int minor)
*/
nxsem_init(&priv->waitsem, 0, 0);
nxsem_setprotocol(&priv->waitsem, SEM_PRIO_NONE);
nxsem_set_protocol(&priv->waitsem, SEM_PRIO_NONE);
/* Register the device as an input device */

2
arch/arm/src/sama5/sam_twi.c
View file

@ -1288,7 +1288,7 @@ struct i2c_master_s *sam_i2cbus_initialize(int bus)
* priority inheritance enabled.
*/
nxsem_setprotocol(&priv->waitsem, SEM_PRIO_NONE);
nxsem_set_protocol(&priv->waitsem, SEM_PRIO_NONE);
/* Perform repeatable TWI hardware initialization */

2
arch/arm/src/samd2l2/sam_spi.c
View file

@ -1431,7 +1431,7 @@ static void spi_dma_setup(struct sam_spidev_s *priv)
/* Initialize the semaphore used to notify when DMA is complete */
nxsem_init(&priv->dmasem, 0, 0);
nxsem_setprotocol(&priv->dmasem, SEM_PRIO_NONE);
nxsem_set_protocol(&priv->dmasem, SEM_PRIO_NONE);
}
#endif

2
arch/arm/src/samd5e5/sam_spi.c
View file

@ -1520,7 +1520,7 @@ static void spi_dma_setup(struct sam_spidev_s *priv)
/* Initialize the semaphore used to notify when DMA is complete */
nxsem_init(&priv->dmasem, 0, 0);
nxsem_setprotocol(&priv->dmasem, SEM_PRIO_NONE);
nxsem_set_protocol(&priv->dmasem, SEM_PRIO_NONE);
}
#endif

2
arch/arm/src/samv7/sam_hsmci.c
View file

@ -3378,7 +3378,7 @@ FAR struct sdio_dev_s *sdio_initialize(int slotno)
* priority inheritance enabled.
*/
nxsem_setprotocol(&priv->waitsem, SEM_PRIO_NONE);
nxsem_set_protocol(&priv->waitsem, SEM_PRIO_NONE);
/* Create a watchdog timer */

8
arch/arm/src/samv7/sam_mcan.c
View file

@ -1466,7 +1466,7 @@ static void mcan_buffer_reserve(FAR struct sam_mcan_s *priv)
flags = enter_critical_section();
txfqs1 = mcan_getreg(priv, SAM_MCAN_TXFQS_OFFSET);
nxsem_getvalue(&priv->txfsem, &sval);
nxsem_get_value(&priv->txfsem, &sval);
txfqs2 = mcan_getreg(priv, SAM_MCAN_TXFQS_OFFSET);
/* If the semaphore count and the TXFQS samples are in
@ -1611,7 +1611,7 @@ static void mcan_buffer_release(FAR struct sam_mcan_s *priv)
* many times.
*/
nxsem_getvalue(&priv->txfsem, &sval);
nxsem_get_value(&priv->txfsem, &sval);
if (sval < priv->config->ntxfifoq)
{
nxsem_post(&priv->txfsem);
@ -3111,7 +3111,7 @@ static bool mcan_txready(FAR struct can_dev_s *dev)
* the TX FIFO/queue. Make sure that they are consistent.
*/
nxsem_getvalue(&priv->txfsem, &sval);
nxsem_get_value(&priv->txfsem, &sval);
DEBUGASSERT(((notfull && sval > 0) || (!notfull && sval <= 0)) &&
(sval <= priv->config->ntxfifoq));
#endif
@ -3182,7 +3182,7 @@ static bool mcan_txempty(FAR struct can_dev_s *dev)
* elements, then there is no transfer in progress.
*/
nxsem_getvalue(&priv->txfsem, &sval);
nxsem_get_value(&priv->txfsem, &sval);
DEBUGASSERT(sval > 0 && sval <= priv->config->ntxfifoq);
empty = (sval == priv->config->ntxfifoq);

2
arch/arm/src/samv7/sam_qspi.c
View file

@ -1797,7 +1797,7 @@ struct qspi_dev_s *sam_qspi_initialize(int intf)
*/
nxsem_init(&priv->dmawait, 0, 0);
nxsem_setprotocol(&priv->dmawait, SEM_PRIO_NONE);
nxsem_set_protocol(&priv->dmawait, SEM_PRIO_NONE);
/* Create a watchdog time to catch DMA timeouts */

2
arch/arm/src/samv7/sam_spi.c
View file

@ -2173,7 +2173,7 @@ FAR struct spi_dev_s *sam_spibus_initialize(int port)
*/
nxsem_init(&spics->dmawait, 0, 0);
nxsem_setprotocol(&spics->dmawait, SEM_PRIO_NONE);
nxsem_set_protocol(&spics->dmawait, SEM_PRIO_NONE);
/* Create a watchdog time to catch DMA timeouts */

2
arch/arm/src/samv7/sam_trng.c
View file

@ -363,7 +363,7 @@ static int sam_rng_initialize(void)
* priority inheritance enabled.
*/
nxsem_setprotocol(&g_trngdev.waitsem, SEM_PRIO_NONE);
nxsem_set_protocol(&g_trngdev.waitsem, SEM_PRIO_NONE);
/* Enable clocking to the TRNG */

2
arch/arm/src/samv7/sam_twihs.c
View file

@ -1456,7 +1456,7 @@ struct i2c_master_s *sam_i2cbus_initialize(int bus)
* have priority inheritance enabled.
*/
nxsem_setprotocol(&priv->waitsem, SEM_PRIO_NONE);
nxsem_set_protocol(&priv->waitsem, SEM_PRIO_NONE);
/* Perform repeatable TWIHS hardware initialization */

2
arch/arm/src/samv7/sam_xdmac.c
View file

@ -1593,7 +1593,7 @@ void sam_dmainitialize(struct sam_xdmac_s *xdmac)
* hence, should not have priority inheritance enabled.
*/
nxsem_setprotocol(&xdmac->dsem, SEM_PRIO_NONE);
nxsem_set_protocol(&xdmac->dsem, SEM_PRIO_NONE);
}
/****************************************************************************

2
arch/arm/src/stm32/stm32_1wire.c
View file

@ -735,7 +735,7 @@ static inline void stm32_1wire_sem_init(FAR struct stm32_1wire_priv_s *priv)
* priority inheritance enabled.
*/
nxsem_setprotocol(&priv->sem_isr, SEM_PRIO_NONE);
nxsem_set_protocol(&priv->sem_isr, SEM_PRIO_NONE);
}
/****************************************************************************

2
arch/arm/src/stm32/stm32_dma2d.c
View file

@ -1110,7 +1110,7 @@ int stm32_dma2dinitialize(void)
*/
nxsem_init(g_interrupt.sem, 0, 0);
nxsem_setprotocol(g_interrupt.sem, SEM_PRIO_NONE);
nxsem_set_protocol(g_interrupt.sem, SEM_PRIO_NONE);
#ifdef CONFIG_STM32_FB_CMAP
/* Enable dma2d transfer and clut loading interrupts only */

4
arch/arm/src/stm32/stm32_hciuart.c
View file

@ -2592,10 +2592,10 @@ void hciuart_initialize(void)
/* Initialize signalling semaphores */
nxsem_init(&state->rxwait, 0, 0);
nxsem_setprotocol(&state->rxwait, SEM_PRIO_NONE);
nxsem_set_protocol(&state->rxwait, SEM_PRIO_NONE);
nxsem_init(&state->txwait, 0, 0);
nxsem_setprotocol(&state->txwait, SEM_PRIO_NONE);
nxsem_set_protocol(&state->txwait, SEM_PRIO_NONE);
/* Attach and enable the HCI UART IRQ */

2
arch/arm/src/stm32/stm32_i2c.c
View file

@ -771,7 +771,7 @@ static inline void stm32_i2c_sem_init(FAR struct stm32_i2c_priv_s *priv)
*/
nxsem_init(&priv->sem_isr, 0, 0);
nxsem_setprotocol(&priv->sem_isr, SEM_PRIO_NONE);
nxsem_set_protocol(&priv->sem_isr, SEM_PRIO_NONE);
#endif
}

2
arch/arm/src/stm32/stm32_i2c_alt.c
View file

@ -780,7 +780,7 @@ static inline void stm32_i2c_sem_init(FAR struct stm32_i2c_priv_s *priv)
*/
nxsem_init(&priv->sem_isr, 0, 0);
nxsem_setprotocol(&priv->sem_isr, SEM_PRIO_NONE);
nxsem_set_protocol(&priv->sem_isr, SEM_PRIO_NONE);
#endif
}

4
arch/arm/src/stm32/stm32_i2c_v2.c
View file

@ -1064,7 +1064,7 @@ static inline void stm32_i2c_sem_init(FAR struct i2c_master_s *dev)
*/
nxsem_init(&((struct stm32_i2c_inst_s *)dev)->priv->sem_isr, 0, 0);
nxsem_setprotocol(&((struct stm32_i2c_inst_s *)dev)->priv->sem_isr, SEM_PRIO_NONE);
nxsem_set_protocol(&((struct stm32_i2c_inst_s *)dev)->priv->sem_isr, SEM_PRIO_NONE);
#endif
}
@ -2688,7 +2688,7 @@ static int stm32_i2c_pm_prepare(FAR struct pm_callback_s *cb, int domain,
/* Check if exclusive lock for I2C bus is held. */
if (nxsem_getvalue(&priv->sem_excl, &sval) < 0)
if (nxsem_get_value(&priv->sem_excl, &sval) < 0)
{
DEBUGASSERT(false);
return -EINVAL;

2
arch/arm/src/stm32/stm32_ltdc.c
View file

@ -1632,7 +1632,7 @@ static void stm32_ltdc_irqconfig(void)
*/
nxsem_init(g_interrupt.sem, 0, 0);
nxsem_setprotocol(g_interrupt.sem, SEM_PRIO_NONE);
nxsem_set_protocol(g_interrupt.sem, SEM_PRIO_NONE);
/* Attach LTDC interrupt vector */

4
arch/arm/src/stm32/stm32_otgfshost.c
View file

@ -5309,7 +5309,7 @@ static inline void stm32_sw_initialize(FAR struct stm32_usbhost_s *priv)
* priority inheritance enabled.
*/
nxsem_setprotocol(&priv->pscsem, SEM_PRIO_NONE);
nxsem_set_protocol(&priv->pscsem, SEM_PRIO_NONE);
/* Initialize the driver state data */
@ -5334,7 +5334,7 @@ static inline void stm32_sw_initialize(FAR struct stm32_usbhost_s *priv)
*/
nxsem_init(&chan->waitsem, 0, 0);
nxsem_setprotocol(&chan->waitsem, SEM_PRIO_NONE);
nxsem_set_protocol(&chan->waitsem, SEM_PRIO_NONE);
}
}

4
arch/arm/src/stm32/stm32_otghshost.c
View file

@ -5307,7 +5307,7 @@ static inline void stm32_sw_initialize(FAR struct stm32_usbhost_s *priv)
* priority inheritance enabled.
*/
nxsem_setprotocol(&priv->pscsem, SEM_PRIO_NONE);
nxsem_set_protocol(&priv->pscsem, SEM_PRIO_NONE);
/* Initialize the driver state data */
@ -5332,7 +5332,7 @@ static inline void stm32_sw_initialize(FAR struct stm32_usbhost_s *priv)
*/
nxsem_init(&chan->waitsem, 0, 0);
nxsem_setprotocol(&chan->waitsem, SEM_PRIO_NONE);
nxsem_set_protocol(&chan->waitsem, SEM_PRIO_NONE);
}
}

2
arch/arm/src/stm32/stm32_rng.c
View file

@ -261,7 +261,7 @@ static ssize_t stm32_rng_read(struct file *filep, char *buffer, size_t buflen)
*/
nxsem_init(&g_rngdev.rd_readsem, 0, 0);
nxsem_setprotocol(&g_rngdev.rd_readsem, SEM_PRIO_NONE);
nxsem_set_protocol(&g_rngdev.rd_readsem, SEM_PRIO_NONE);
g_rngdev.rd_buflen = buflen;
g_rngdev.rd_buf = buffer;

2
arch/arm/src/stm32/stm32_sdio.c
View file

@ -3040,7 +3040,7 @@ FAR struct sdio_dev_s *sdio_initialize(int slotno)
* priority inheritance enabled.
*/
nxsem_setprotocol(&priv->waitsem, SEM_PRIO_NONE);
nxsem_set_protocol(&priv->waitsem, SEM_PRIO_NONE);
/* Create a watchdog timer */

4
arch/arm/src/stm32/stm32_spi.c
View file

@ -2062,8 +2062,8 @@ static void spi_bus_initialize(FAR struct stm32_spidev_s *priv)
nxsem_init(&priv->rxsem, 0, 0);
nxsem_init(&priv->txsem, 0, 0);
nxsem_setprotocol(&priv->rxsem, SEM_PRIO_NONE);
nxsem_setprotocol(&priv->txsem, SEM_PRIO_NONE);
nxsem_set_protocol(&priv->rxsem, SEM_PRIO_NONE);
nxsem_set_protocol(&priv->txsem, SEM_PRIO_NONE);
/* Get DMA channels. NOTE: stm32_dmachannel() will always assign the DMA
* channel. If the channel is not available, then stm32_dmachannel() will

2
arch/arm/src/stm32/stm32f40xxx_i2c.c
View file

@ -826,7 +826,7 @@ static inline void stm32_i2c_sem_init(FAR struct stm32_i2c_priv_s *priv)
*/
nxsem_init(&priv->sem_isr, 0, 0);
nxsem_setprotocol(&priv->sem_isr, SEM_PRIO_NONE);
nxsem_set_protocol(&priv->sem_isr, SEM_PRIO_NONE);
#endif
}

4
arch/arm/src/stm32f0l0g0/stm32_i2c.c
View file

@ -1078,7 +1078,7 @@ static inline void stm32_i2c_sem_init(FAR struct i2c_master_s *dev)
*/
nxsem_init(&((struct stm32_i2c_inst_s *)dev)->priv->sem_isr, 0, 0);
nxsem_setprotocol(&((struct stm32_i2c_inst_s *)dev)->priv->sem_isr, SEM_PRIO_NONE);
nxsem_set_protocol(&((struct stm32_i2c_inst_s *)dev)->priv->sem_isr, SEM_PRIO_NONE);
#endif
}
@ -2698,7 +2698,7 @@ static int stm32_i2c_pm_prepare(FAR struct pm_callback_s *cb, int domain,
/* Check if exclusive lock for I2C bus is held. */
if (nxsem_getvalue(&priv->sem_excl, &sval) < 0)
if (nxsem_get_value(&priv->sem_excl, &sval) < 0)
{
DEBUGASSERT(false);
return -EINVAL;

2
arch/arm/src/stm32f0l0g0/stm32_rng.c
View file

@ -261,7 +261,7 @@ static ssize_t stm32_rng_read(struct file *filep, char *buffer, size_t buflen)
*/
nxsem_init(&g_rngdev.rd_readsem, 0, 0);
nxsem_setprotocol(&g_rngdev.rd_readsem, SEM_PRIO_NONE);
nxsem_set_protocol(&g_rngdev.rd_readsem, SEM_PRIO_NONE);
g_rngdev.rd_buflen = buflen;
g_rngdev.rd_buf = buffer;

6
arch/arm/src/stm32f0l0g0/stm32_spi.c
View file

@ -1611,7 +1611,7 @@ static int spi_pm_prepare(FAR struct pm_callback_s *cb, int domain,
/* Check if exclusive lock for SPI bus is held. */
if (nxsem_getvalue(&priv->exclsem, &sval) < 0)
if (nxsem_get_value(&priv->exclsem, &sval) < 0)
{
DEBUGASSERT(false);
return -EINVAL;
@ -1725,8 +1725,8 @@ static void spi_bus_initialize(FAR struct stm32_spidev_s *priv)
* priority inheritance enabled.
*/
nxsem_setprotocol(&priv->rxsem, SEM_PRIO_NONE);
nxsem_setprotocol(&priv->txsem, SEM_PRIO_NONE);
nxsem_set_protocol(&priv->rxsem, SEM_PRIO_NONE);
nxsem_set_protocol(&priv->txsem, SEM_PRIO_NONE);
/* Get DMA channels. NOTE: stm32_dmachannel() will always assign the DMA
* channel. If the channel is not available, then stm32_dmachannel() will

2
arch/arm/src/stm32f7/stm32_dma2d.c
View file

@ -1111,7 +1111,7 @@ int stm32_dma2dinitialize(void)
*/
nxsem_init(g_interrupt.sem, 0, 0);
nxsem_setprotocol(g_interrupt.sem, SEM_PRIO_NONE);
nxsem_set_protocol(g_interrupt.sem, SEM_PRIO_NONE);
#ifdef CONFIG_STM32F7_FB_CMAP
/* Enable dma2d transfer and clut loading interrupts only */

4
arch/arm/src/stm32f7/stm32_i2c.c
View file

@ -1102,7 +1102,7 @@ static inline void stm32_i2c_sem_init(FAR struct i2c_master_s *dev)
*/
nxsem_init(&((struct stm32_i2c_inst_s *)dev)->priv->sem_isr, 0, 0);
nxsem_setprotocol(&((struct stm32_i2c_inst_s *)dev)->priv->sem_isr, SEM_PRIO_NONE);
nxsem_set_protocol(&((struct stm32_i2c_inst_s *)dev)->priv->sem_isr, SEM_PRIO_NONE);
#endif
}
@ -2726,7 +2726,7 @@ static int stm32_i2c_pm_prepare(FAR struct pm_callback_s *cb, int domain,
/* Check if exclusive lock for I2C bus is held. */
if (nxsem_getvalue(&priv->sem_excl, &sval) < 0)
if (nxsem_get_value(&priv->sem_excl, &sval) < 0)
{
DEBUGASSERT(false);
return -EINVAL;

2
arch/arm/src/stm32f7/stm32_ltdc.c
View file

@ -1634,7 +1634,7 @@ static void stm32_ltdc_irqconfig(void)
*/
nxsem_init(g_interrupt.sem, 0, 0);
nxsem_setprotocol(g_interrupt.sem, SEM_PRIO_NONE);
nxsem_set_protocol(g_interrupt.sem, SEM_PRIO_NONE);
/* Attach LTDC interrupt vector */

4
arch/arm/src/stm32f7/stm32_otghost.c
View file

@ -5296,7 +5296,7 @@ static inline void stm32_sw_initialize(FAR struct stm32_usbhost_s *priv)
* priority inheritance enabled.
*/
nxsem_setprotocol(&priv->pscsem, SEM_PRIO_NONE);
nxsem_set_protocol(&priv->pscsem, SEM_PRIO_NONE);
/* Initialize the driver state data */
@ -5321,7 +5321,7 @@ static inline void stm32_sw_initialize(FAR struct stm32_usbhost_s *priv)
*/
nxsem_init(&chan->waitsem, 0, 0);
nxsem_setprotocol(&chan->waitsem, SEM_PRIO_NONE);
nxsem_set_protocol(&chan->waitsem, SEM_PRIO_NONE);
}
}

4
arch/arm/src/stm32f7/stm32_qspi.c
View file

@ -2600,7 +2600,7 @@ struct qspi_dev_s *stm32f7_qspi_initialize(int intf)
*/
nxsem_init(&priv->dmawait, 0, 0);
nxsem_setprotocol(&priv->dmawait, SEM_PRIO_NONE);
nxsem_set_protocol(&priv->dmawait, SEM_PRIO_NONE);
/* Create a watchdog time to catch DMA timeouts */
@ -2628,7 +2628,7 @@ struct qspi_dev_s *stm32f7_qspi_initialize(int intf)
*/
nxsem_init(&priv->op_sem, 0, 0);
nxsem_setprotocol(&priv->op_sem, SEM_PRIO_NONE);
nxsem_set_protocol(&priv->op_sem, SEM_PRIO_NONE);
#endif
/* Perform hardware initialization. Puts the QSPI into an active

2
arch/arm/src/stm32f7/stm32_rng.c
View file

@ -282,7 +282,7 @@ static ssize_t stm32_rngread(struct file *filep, char *buffer, size_t buflen)
*/
nxsem_init(&g_rngdev.rd_readsem, 0, 0);
nxsem_setprotocol(&g_rngdev.rd_readsem, SEM_PRIO_NONE);
nxsem_set_protocol(&g_rngdev.rd_readsem, SEM_PRIO_NONE);
g_rngdev.rd_buflen = buflen;
g_rngdev.rd_buf = buffer;

2
arch/arm/src/stm32f7/stm32_sdmmc.c
View file

@ -3473,7 +3473,7 @@ FAR struct sdio_dev_s *sdio_initialize(int slotno)
* priority inheritance enabled.
*/
nxsem_setprotocol(&priv->waitsem, SEM_PRIO_NONE);
nxsem_set_protocol(&priv->waitsem, SEM_PRIO_NONE);
/* Create a watchdog timer */

6
arch/arm/src/stm32f7/stm32_spi.c
View file

@ -2072,7 +2072,7 @@ static int spi_pm_prepare(FAR struct pm_callback_s *cb, int domain,
/* Check if exclusive lock for SPI bus is held. */
if (nxsem_getvalue(&priv->exclsem, &sval) < 0)
if (nxsem_get_value(&priv->exclsem, &sval) < 0)
{
DEBUGASSERT(false);
return -EINVAL;
@ -2169,8 +2169,8 @@ static void spi_bus_initialize(struct stm32_spidev_s *priv)
nxsem_init(&priv->rxsem, 0, 0);
nxsem_init(&priv->txsem, 0, 0);
nxsem_setprotocol(&priv->rxsem, SEM_PRIO_NONE);
nxsem_setprotocol(&priv->txsem, SEM_PRIO_NONE);
nxsem_set_protocol(&priv->rxsem, SEM_PRIO_NONE);
nxsem_set_protocol(&priv->txsem, SEM_PRIO_NONE);
/* Get DMA channels. NOTE: stm32_dmachannel() will always assign the
* DMA channel. If the channel is not available, then

4
arch/arm/src/stm32h7/stm32_i2c.c
View file

@ -1055,7 +1055,7 @@ static inline void stm32_i2c_sem_init(FAR struct i2c_master_s *dev)
*/
nxsem_init(&((struct stm32_i2c_inst_s *)dev)->priv->sem_isr, 0, 0);
nxsem_setprotocol(&((struct stm32_i2c_inst_s *)dev)->priv->sem_isr, SEM_PRIO_NONE);
nxsem_set_protocol(&((struct stm32_i2c_inst_s *)dev)->priv->sem_isr, SEM_PRIO_NONE);
#endif
}
@ -2671,7 +2671,7 @@ static int stm32_i2c_pm_prepare(FAR struct pm_callback_s *cb, int domain,
/* Check if exclusive lock for I2C bus is held. */
if (nxsem_getvalue(&priv->sem_excl, &sval) < 0)
if (nxsem_get_value(&priv->sem_excl, &sval) < 0)
{
DEBUGASSERT(false);
return -EINVAL;

4
arch/arm/src/stm32h7/stm32_otghost.c
View file

@ -5303,7 +5303,7 @@ static inline void stm32_sw_initialize(FAR struct stm32_usbhost_s *priv)
* priority inheritance enabled.
*/
nxsem_setprotocol(&priv->pscsem, SEM_PRIO_NONE);
nxsem_set_protocol(&priv->pscsem, SEM_PRIO_NONE);
/* Initialize the driver state data */
@ -5328,7 +5328,7 @@ static inline void stm32_sw_initialize(FAR struct stm32_usbhost_s *priv)
*/
nxsem_init(&chan->waitsem, 0, 0);
nxsem_setprotocol(&chan->waitsem, SEM_PRIO_NONE);
nxsem_set_protocol(&chan->waitsem, SEM_PRIO_NONE);
}
}

4
arch/arm/src/stm32h7/stm32_qspi.c
View file

@ -2667,7 +2667,7 @@ struct qspi_dev_s *stm32h7_qspi_initialize(int intf)
*/
nxsem_init(&priv->dmawait, 0, 0);
nxsem_setprotocol(&priv->dmawait, SEM_PRIO_NONE);
nxsem_set_protocol(&priv->dmawait, SEM_PRIO_NONE);
/* Create a watchdog time to catch DMA timeouts */
@ -2695,7 +2695,7 @@ struct qspi_dev_s *stm32h7_qspi_initialize(int intf)
*/
nxsem_init(&priv->op_sem, 0, 0);
nxsem_setprotocol(&priv->op_sem, SEM_PRIO_NONE);
nxsem_set_protocol(&priv->op_sem, SEM_PRIO_NONE);
#endif
/* Perform hardware initialization. Puts the QSPI into an active

2
arch/arm/src/stm32h7/stm32_sdmmc.c
View file

@ -3528,7 +3528,7 @@ FAR struct sdio_dev_s *sdio_initialize(int slotno)
* priority inheritance enabled.
*/
nxsem_setprotocol(&priv->waitsem, SEM_PRIO_NONE);
nxsem_set_protocol(&priv->waitsem, SEM_PRIO_NONE);
/* Create a watchdog timer */

6
arch/arm/src/stm32h7/stm32_spi.c
View file

@ -2247,7 +2247,7 @@ static int spi_pm_prepare(FAR struct pm_callback_s *cb, int domain,
/* Check if exclusive lock for SPI bus is held. */
if (nxsem_getvalue(&priv->exclsem, &sval) < 0)
if (nxsem_get_value(&priv->exclsem, &sval) < 0)
{
DEBUGASSERT(false);
return -EINVAL;
@ -2371,8 +2371,8 @@ static void spi_bus_initialize(struct stm32_spidev_s *priv)
nxsem_init(&priv->rxsem, 0, 0);
nxsem_init(&priv->txsem, 0, 0);
nxsem_setprotocol(&priv->rxsem, SEM_PRIO_NONE);
nxsem_setprotocol(&priv->txsem, SEM_PRIO_NONE);
nxsem_set_protocol(&priv->rxsem, SEM_PRIO_NONE);
nxsem_set_protocol(&priv->txsem, SEM_PRIO_NONE);
/* Get DMA channels. NOTE: stm32_dmachannel() will always assign the DMA
* channel. If the channel is not available, then stm32_dmachannel() will

4
arch/arm/src/stm32l4/stm32l4_1wire.c
View file

@ -655,7 +655,7 @@ static inline void stm32_1wire_sem_init(FAR struct stm32_1wire_priv_s *priv)
* priority inheritance enabled.
*/
nxsem_setprotocol(&priv->sem_isr, SEM_PRIO_NONE);
nxsem_set_protocol(&priv->sem_isr, SEM_PRIO_NONE);
}
/****************************************************************************
@ -1175,7 +1175,7 @@ static int stm32_1wire_pm_prepare(FAR struct pm_callback_s *cb, int domain,
/* Check if exclusive lock for 1-Wire bus is held. */
if (nxsem_getvalue(&priv->sem_excl, &sval) < 0)
if (nxsem_get_value(&priv->sem_excl, &sval) < 0)
{
DEBUGASSERT(false);
return -EINVAL;

4
arch/arm/src/stm32l4/stm32l4_i2c.c
View file

@ -1096,7 +1096,7 @@ static inline void stm32l4_i2c_sem_init(FAR struct i2c_master_s *dev)
*/
nxsem_init(&((struct stm32l4_i2c_inst_s *)dev)->priv->sem_isr, 0, 0);
nxsem_setprotocol(&((struct stm32l4_i2c_inst_s *)dev)->priv->sem_isr,
nxsem_set_protocol(&((struct stm32l4_i2c_inst_s *)dev)->priv->sem_isr,
SEM_PRIO_NONE);
#endif
}
@ -2850,7 +2850,7 @@ static int stm32l4_i2c_pm_prepare(FAR struct pm_callback_s *cb, int domain,
/* Check if exclusive lock for I2C bus is held. */
if (nxsem_getvalue(&priv->sem_excl, &sval) < 0)
if (nxsem_get_value(&priv->sem_excl, &sval) < 0)
{
DEBUGASSERT(false);
return -EINVAL;

4
arch/arm/src/stm32l4/stm32l4_otgfshost.c
View file

@ -5342,7 +5342,7 @@ static inline void stm32l4_sw_initialize(FAR struct stm32l4_usbhost_s *priv)
* priority inheritance enabled.
*/
nxsem_setprotocol(&priv->pscsem, SEM_PRIO_NONE);
nxsem_set_protocol(&priv->pscsem, SEM_PRIO_NONE);
/* Initialize the driver state data */
@ -5368,7 +5368,7 @@ static inline void stm32l4_sw_initialize(FAR struct stm32l4_usbhost_s *priv)
*/
nxsem_init(&chan->waitsem, 0, 0);
nxsem_setprotocol(&chan->waitsem, SEM_PRIO_NONE);
nxsem_set_protocol(&chan->waitsem, SEM_PRIO_NONE);
}
}

4
arch/arm/src/stm32l4/stm32l4_qspi.c
View file

@ -2540,7 +2540,7 @@ struct qspi_dev_s *stm32l4_qspi_initialize(int intf)
*/
nxsem_init(&priv->dmawait, 0, 0);
nxsem_setprotocol(&priv->dmawait, SEM_PRIO_NONE);
nxsem_set_protocol(&priv->dmawait, SEM_PRIO_NONE);
/* Create a watchdog time to catch DMA timeouts */
@ -2568,7 +2568,7 @@ struct qspi_dev_s *stm32l4_qspi_initialize(int intf)
*/
nxsem_init(&priv->op_sem, 0, 0);
nxsem_setprotocol(&priv->op_sem, SEM_PRIO_NONE);
nxsem_set_protocol(&priv->op_sem, SEM_PRIO_NONE);
#endif
/* Perform hardware initialization. Puts the QSPI into an active

2
arch/arm/src/stm32l4/stm32l4_rng.c
View file

@ -267,7 +267,7 @@ static ssize_t stm32l4_rngread(struct file *filep, char *buffer, size_t buflen)
*/
nxsem_init(&g_rngdev.rd_readsem, 0, 0);
nxsem_setprotocol(&g_rngdev.rd_readsem, SEM_PRIO_NONE);
nxsem_set_protocol(&g_rngdev.rd_readsem, SEM_PRIO_NONE);
g_rngdev.rd_buflen = buflen;
g_rngdev.rd_buf = buffer;

2
arch/arm/src/stm32l4/stm32l4_sdmmc.c
View file

@ -3176,7 +3176,7 @@ FAR struct sdio_dev_s *sdio_initialize(int slotno)
* priority inheritance enabled.
*/
nxsem_setprotocol(&priv->waitsem, SEM_PRIO_NONE);
nxsem_set_protocol(&priv->waitsem, SEM_PRIO_NONE);
/* Create a watchdog timer */

6
arch/arm/src/stm32l4/stm32l4_spi.c
View file

@ -1667,7 +1667,7 @@ static int spi_pm_prepare(FAR struct pm_callback_s *cb, int domain,
/* Check if exclusive lock for SPI bus is held. */
if (nxsem_getvalue(&priv->exclsem, &sval) < 0)
if (nxsem_get_value(&priv->exclsem, &sval) < 0)
{
DEBUGASSERT(false);
return -EINVAL;
@ -1765,8 +1765,8 @@ static void spi_bus_initialize(FAR struct stm32l4_spidev_s *priv)
* priority inheritance enabled.
*/
nxsem_setprotocol(&priv->rxsem, SEM_PRIO_NONE);
nxsem_setprotocol(&priv->txsem, SEM_PRIO_NONE);
nxsem_set_protocol(&priv->rxsem, SEM_PRIO_NONE);
nxsem_set_protocol(&priv->txsem, SEM_PRIO_NONE);
/* Get DMA channels. NOTE: stm32l4_dmachannel() will always assign the DMA
* channel. If the channel is not available, then stm32l4_dmachannel()

4
arch/arm/src/tiva/common/tiva_hciuart.c
View file

@ -1848,10 +1848,10 @@ void hciuart_initialize(void)
/* Initialize signalling semaphores */
nxsem_init(&state->rxwait, 0, 0);
nxsem_setprotocol(&state->rxwait, SEM_PRIO_NONE);
nxsem_set_protocol(&state->rxwait, SEM_PRIO_NONE);
nxsem_init(&state->txwait, 0, 0);
nxsem_setprotocol(&state->txwait, SEM_PRIO_NONE);
nxsem_set_protocol(&state->txwait, SEM_PRIO_NONE);
/* Attach and enable the HCI UART IRQ */

2
arch/arm/src/tiva/common/tiva_i2c.c
View file

@ -849,7 +849,7 @@ static inline void tiva_i2c_sem_init(struct tiva_i2c_priv_s *priv)
*/
nxsem_init(&priv->waitsem, 0, 0);
nxsem_setprotocol(&priv->waitsem, SEM_PRIO_NONE);
nxsem_set_protocol(&priv->waitsem, SEM_PRIO_NONE);
#endif
}

2
arch/arm/src/tiva/common/tiva_ssi.c
View file

@ -1623,7 +1623,7 @@ FAR struct spi_dev_s *tiva_ssibus_initialize(int port)
*/
nxsem_init(&priv->xfrsem, 0, 0);
nxsem_setprotocol(&priv->xfrsem, SEM_PRIO_NONE);
nxsem_set_protocol(&priv->xfrsem, SEM_PRIO_NONE);
#endif
nxsem_init(&priv->exclsem, 0, 1);

2
arch/arm/src/xmc4/xmc4_spi.c
View file

@ -2090,7 +2090,7 @@ struct spi_dev_s *xmc4_spibus_initialize(int channel)
*/
nxsem_init(&spics->dmawait, 0, 0);
nxsem_setprotocol(&spics->dmawait, SEM_PRIO_NONE);
nxsem_set_protocol(&spics->dmawait, SEM_PRIO_NONE);
/* Create a watchdog time to catch DMA timeouts */

2
arch/mips/src/pic32mz/pic32mz_i2c.c
View file

@ -877,7 +877,7 @@ static inline void pic32mz_i2c_sem_init(FAR struct pic32mz_i2c_priv_s *priv)
*/
nxsem_init(&priv->sem_isr, 0, 0);
nxsem_setprotocol(&priv->sem_isr, SEM_PRIO_NONE);
nxsem_set_protocol(&priv->sem_isr, SEM_PRIO_NONE);
#endif
}

2
arch/mips/src/pic32mz/pic32mz_spi.c
View file

@ -2038,7 +2038,7 @@ FAR struct spi_dev_s *pic32mz_spibus_initialize(int port)
*/
nxsem_init(&priv->dmawait, 0, 0);
nxsem_setprotocol(&priv->dmawait, SEM_PRIO_NONE);
nxsem_set_protocol(&priv->dmawait, SEM_PRIO_NONE);
/* Create a watchdog timer to catch DMA timeouts */

2
arch/sim/src/sim/up_touchscreen.c
View file

@ -637,7 +637,7 @@ int sim_tsc_initialize(int minor)
* priority inheritance enabled.
*/
nxsem_setprotocol(&priv->waitsem, SEM_PRIO_NONE);
nxsem_set_protocol(&priv->waitsem, SEM_PRIO_NONE);
priv->minor = minor;

2
boards/arm/cxd56xx/common/src/cxd56_imageproc.c
View file

@ -388,7 +388,7 @@ void imageproc_initialize(void)
nxsem_init(&g_rotexc, 0, 1);
nxsem_init(&g_rotwait, 0, 0);
nxsem_init(&g_geexc, 0, 1);
nxsem_setprotocol(&g_rotwait, SEM_PRIO_NONE);
nxsem_set_protocol(&g_rotwait, SEM_PRIO_NONE);
cxd56_ge2dinitialize(GEDEVNAME);

2
drivers/1wire/1wire.c
View file

@ -193,7 +193,7 @@ static int onewire_pm_prepare(FAR struct pm_callback_s *cb, int domain,
/* Check if exclusive lock for the bus master is held. */
if (nxsem_getvalue(&master->devsem.sem, &sval) < 0)
if (nxsem_get_value(&master->devsem.sem, &sval) < 0)
{
DEBUGASSERT(false);
return -EINVAL;

2
drivers/analog/adc.c
View file

@ -613,7 +613,7 @@ int adc_register(FAR const char *path, FAR struct adc_dev_s *dev)
* priority inheritance enabled.
*/
nxsem_setprotocol(&dev->ad_recv.af_sem, SEM_PRIO_NONE);
nxsem_set_protocol(&dev->ad_recv.af_sem, SEM_PRIO_NONE);
/* Reset the ADC hardware */

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