forked from nuttx/nuttx-update
SAMA5 PWM: Driver now in build and configuration system
This commit is contained in:
Gregory Nutt
parent
e73d77c73f
commit
b5791ac7a6
7 changed files with 399 additions and 132 deletions
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@ -5974,4 +5974,7 @@
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* arch/arm/src/sama5/sam_pwm.c and .h: Add PWM driver for SAMA5
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untested on initial checkout (not even incorporated in to build
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system) (2013-11-6).
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* arch/arm/src/sama5/Make.defs and Kconfig: SAMA5 PWM driver now
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incorporated into build and configuration system. Builds with
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no errors (2013-11-6).
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@ -196,6 +196,7 @@ config SAMA5_TC1
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config SAMA5_PWM
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bool "Pulse Width Modulation Controller (PWM)"
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default n
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select PWM
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config SAMA5_ADC
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bool "Touch Screen ADC Controller (ADC)"
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@ -2368,6 +2369,239 @@ endif # SAMA5_TSD
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endmenu # Touchscreen Configuration
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endif # SAMA5_ADC
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if SAMA5_PWM
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menu "PWM configuration"
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config SAMA5_PWM_CLKA
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bool "Enable PWM CLKA"
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default n
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---help---
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Enable the PWM CLKA source.
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config SAMA5_PWM_CLKA_FREQUENCY
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int "CLKA frequency"
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default 100
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depends on SAMA5_PWM_CLKA
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---help---
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If the CLKA source is enabled, then you must also provide the
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frequency of the CLKA. This frequency will be derived from from MCK
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using a prescaler and divider. Therefore, a wide range of
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frequencies are possible.
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config SAMA5_PWM_CLKB
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bool "Enable PWM CLKB"
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default n
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---help---
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Enable the PWM CLKB source.
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config SAMA5_PWM_CLKB_FREQUENCY
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int "CLKB frequency"
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default 100
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depends on SAMA5_PWM_CLKB
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---help---
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If the CLKB source is enabled, then you must also provide the
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frequency of the CLKB. This frequency will be derived from from MCK
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using a prescaler and divider. Therefore, a wide range of
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frequencies are possible.
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config SAMA5_PWM_CHAN0
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bool "Enable PWM channel 0"
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default n
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if SAMA5_PWM_CHAN0
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choice
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prompt "PWM channel 0 clock source"
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default SAMA5_PWM_CHAN0_MCK
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config SAMA5_PWM_CHAN0_MCK
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bool "MCK (divided)"
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config SAMA5_PWM_CHAN0_CLKA
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bool "CLKA"
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depends on SAMA5_PWM_CLKA
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config SAMA5_PWM_CHAN0_CLKB
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bool "CLKB"
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depends on SAMA5_PWM_CLKB
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endchoice # PWM channel 0 clock source
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config SAMA5_PWM_CHAN0_MCKDIV
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int "MCK divider"
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default 1
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depends on SAMA5_PWM_CHAN0_MCK
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---help---
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If source clock for the PWM channel is the MCK, then you must also
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specify the MCK divider to use with the MCK. The only valid options
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are 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, and 1024. Other
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selections will cause compile time errors.
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config SAMA5_PWM_CHAN0_OUTPUTH
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bool "Configure OUTPUT H pin"
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default n
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config SAMA5_PWM_CHAN0_OUTPUTL
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bool "Configure OUTPUT L pin"
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default n
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config SAMA5_PWM_CHAN0_FAULTINPUT
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bool "Configure Fault Input pin"
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default n
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endif # SAMA5_PWM_CHAN0
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config SAMA5_PWM_CHAN1
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bool "Enable PWM channel 1"
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default n
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if SAMA5_PWM_CHAN1
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choice
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prompt "PWM channel 1 clock source"
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default SAMA5_PWM_CHAN1_MCK
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config SAMA5_PWM_CHAN1_MCK
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bool "MCK (divided)"
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config SAMA5_PWM_CHAN1_CLKA
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bool "CLKA"
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depends on SAMA5_PWM_CLKA
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config SAMA5_PWM_CHAN1_CLKB
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bool "CLKB"
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depends on SAMA5_PWM_CLKB
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endchoice # PWM channel 1 clock source
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config SAMA5_PWM_CHAN1_MCKDIV
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int "MCK divider"
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default 1
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depends on SAMA5_PWM_CHAN1_MCK
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---help---
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If source clock for the PWM channel is the MCK, then you must also
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specify the MCK divider to use with the MCK. The only valid options
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are 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, and 1024. Other
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selections will cause compile time errors.
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config SAMA5_PWM_CHAN1_OUTPUTH
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bool "Configure OUTPUT H pin"
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default n
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config SAMA5_PWM_CHAN1_OUTPUTL
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bool "Configure OUTPUT L pin"
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default n
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config SAMA5_PWM_CHAN1_FAULTINPUT
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bool "Configure Fault Input pin"
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default n
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endif # SAMA5_PWM_CHAN1
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config SAMA5_PWM_CHAN2
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bool "Enable PWM channel 2"
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default n
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if SAMA5_PWM_CHAN2
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choice
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prompt "PWM channel 2 clock source"
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default SAMA5_PWM_CHAN2_MCK
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config SAMA5_PWM_CHAN2_MCK
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bool "MCK (divided)"
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config SAMA5_PWM_CHAN2_CLKA
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bool "CLKA"
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depends on SAMA5_PWM_CLKA
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config SAMA5_PWM_CHAN2_CLKB
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bool "CLKB"
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depends on SAMA5_PWM_CLKB
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endchoice # PWM channel 2 clock source
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config SAMA5_PWM_CHAN2_MCKDIV
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int "MCK divider"
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default 1
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depends on SAMA5_PWM_CHAN2_MCK
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---help---
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If source clock for the PWM channel is the MCK, then you must also
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specify the MCK divider to use with the MCK. The only valid options
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are 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, and 1024. Other
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selections will cause compile time errors.
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config SAMA5_PWM_CHAN2_OUTPUTH
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bool "Configure OUTPUT H pin"
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default n
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config SAMA5_PWM_CHAN2_OUTPUTL
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bool "Configure OUTPUT L pin"
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default n
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config SAMA5_PWM_CHAN2_FAULTINPUT
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bool "Configure Fault Input pin"
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default n
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endif # SAMA5_PWM_CHAN2
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config SAMA5_PWM_CHAN3
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bool "Enable PWM channel 3"
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default n
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if SAMA5_PWM_CHAN3
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choice
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prompt "PWM channel 3 clock source"
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default SAMA5_PWM_CHAN3_MCK
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config SAMA5_PWM_CHAN3_MCK
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bool "MCK (divided)"
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config SAMA5_PWM_CHAN3_CLKA
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bool "CLKA"
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depends on SAMA5_PWM_CLKA
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config SAMA5_PWM_CHAN3_CLKB
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bool "CLKB"
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depends on SAMA5_PWM_CLKB
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endchoice # PWM channel 3 clock source
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config SAMA5_PWM_CHAN3_MCKDIV
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int "MCK divider"
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default 1
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depends on SAMA5_PWM_CHAN3_MCK
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---help---
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If source clock for the PWM channel is the MCK, then you must also
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specify the MCK divider to use with the MCK. The only valid options
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are 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, and 1024. Other
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selections will cause compile time errors.
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config SAMA5_PWM_CHAN3_OUTPUTH
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bool "Configure OUTPUT H pin"
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default n
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config SAMA5_PWM_CHAN3_OUTPUTL
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bool "Configure OUTPUT L pin"
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default n
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config SAMA5_PWM_CHAN3_FAULTINPUT
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bool "Configure Fault Input pin"
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default n
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endif # SAMA5_PWM_CHAN3
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config SAMA5_PWM_REGDEBUG
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bool "Enable register-level PWM debug"
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default n
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depends on DEBUG
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---help---
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Enable very low register-level debug output.
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endmenu # PWM configuration
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endif # SAMA5_PWM
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if SAMA5_WDT
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menu "Watchdog Configuration"
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@ -205,6 +205,10 @@ CHIP_CSRCS += sam_tsd.c
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endif
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endif
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ifeq ($(CONFIG_SAMA5_PWM),y)
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CHIP_CSRCS += sam_pwm.c
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endif
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ifeq ($(CONFIG_SAMA5_TC0),y)
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CHIP_CSRCS += sam_tc.c
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else
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@ -48,6 +48,8 @@
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#include <nuttx/arch.h>
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#include <nuttx/pwm.h>
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#include "chip/sam_pinmap.h"
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#include <arch/board/board.h>
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#include "up_internal.h"
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@ -105,48 +107,48 @@
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# error CONFIG_SAMA5_PWM_CLKA_FREQUENCY is not defined
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# elif (BOARD_MCK_FREQUENCY / CONFIG_SAMA5_PWM_CLKA_FREQUENCY) < 256
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# define PWM_CLK_PREA PWM_CLK_PREA_DIV1
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# define CLKA_PRE 1
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# define CLKA_PRE_BITS PWM_CLK_PREA_DIV1
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# define CLKA_PRE 1
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# elif (BOARD_MCK_FREQUENCY / 2 / CONFIG_SAMA5_PWM_CLKA_FREQUENCY) < 256
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# define PWM_CLK_PREA PWM_CLK_PREA_DIV2
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# define CLKA_PRE 2
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# define CLKA_PRE_BITS PWM_CLK_PREA_DIV2
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# define CLKA_PRE 2
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# elif (BOARD_MCK_FREQUENCY / 4 / CONFIG_SAMA5_PWM_CLKA_FREQUENCY) < 256
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# define PWM_CLK_PREA PWM_CLK_PREA_DIV4
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# define CLKA_PRE 4
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# define CLKA_PRE_BITS PWM_CLK_PREA_DIV4
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# define CLKA_PRE 4
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# elif (BOARD_MCK_FREQUENCY / 8 / CONFIG_SAMA5_PWM_CLKA_FREQUENCY) < 256
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# define PWM_CLK_PREA PWM_CLK_PREA_DIV8
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# define CLKA_PRE 8
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# define CLKA_PRE_BITS PWM_CLK_PREA_DIV8
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# define CLKA_PRE 8
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# elif (BOARD_MCK_FREQUENCY / 16 / CONFIG_SAMA5_PWM_CLKA_FREQUENCY) < 256
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# define PWM_CLK_PREA PWM_CLK_PREA_DIV16
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# define CLKA_PRE 16
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# define CLKA_PRE_BITS PWM_CLK_PREA_DIV16
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# define CLKA_PRE 16
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# elif (BOARD_MCK_FREQUENCY / 32 / CONFIG_SAMA5_PWM_CLKA_FREQUENCY) < 256
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# define PWM_CLK_PREA PWM_CLK_PREA_DIV32
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# define CLKA_PRE 32
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# define CLKA_PRE_BITS PWM_CLK_PREA_DIV32
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# define CLKA_PRE 32
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# elif (BOARD_MCK_FREQUENCY / 64 / CONFIG_SAMA5_PWM_CLKA_FREQUENCY) < 256
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# define PWM_CLK_PREA PWM_CLK_PREA_DIV64
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# define CLKA_PRE 64
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# define CLKA_PRE_BITS PWM_CLK_PREA_DIV64
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# define CLKA_PRE 64
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# elif (BOARD_MCK_FREQUENCY / 128 / CONFIG_SAMA5_PWM_CLKA_FREQUENCY) < 256
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# define PWM_CLK_PREA PWM_CLK_PREA_DIV128
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# define CLKA_PRE 128
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# define CLKA_PRE_BITS PWM_CLK_PREA_DIV128
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# define CLKA_PRE 128
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# elif (BOARD_MCK_FREQUENCY / 256 / CONFIG_SAMA5_PWM_CLKA_FREQUENCY) < 256
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# define PWM_CLK_PREA PWM_CLK_PREA_DIV256
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# define CLKA_PRE 256
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# define CLKA_PRE_BITS PWM_CLK_PREA_DIV256
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# define CLKA_PRE 256
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# elif (BOARD_MCK_FREQUENCY / 512 / CONFIG_SAMA5_PWM_CLKA_FREQUENCY) < 256
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# define PWM_CLK_PREA PWM_CLK_PREA_DIV512
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# define CLKA_PRE 512
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# define CLKA_PRE_BITS PWM_CLK_PREA_DIV512
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# define CLKA_PRE 512
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# elif (BOARD_MCK_FREQUENCY / 1024 / CONFIG_SAMA5_PWM_CLKA_FREQUENCY) < 256
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# define PWM_CLK_PREA PWM_CLK_PREA_DIV1024
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# define CLKA_PRE 1024
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# define CLKA_PRE_BITS PWM_CLK_PREA_DIV1024
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# define CLKA_PRE 1024
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# else
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# error Cannot realize CONFIG_SAMA5_PWM_CLKA_FREQUENCY
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@ -154,12 +156,12 @@
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# define CLKA_DIV (BOARD_MCK_FREQUENCY / CLKA_PRE / CONFIG_SAMA5_PWM_CLKA_FREQUENCY)
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# define CLKA_FREQUENCY (BOARD_MCK_FREQUENCY / CLKA_PRE / CLKA_DIV)
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# define PWM_CLK_DIVA PWM_CLK_DIVA(CLKA_DIV)
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# define CLKA_DIV_BITS PWM_CLK_DIVA(CLKA_DIV)
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#else
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# undef CONFIG_SAMA5_PWM_CLKA_FREQUENCY
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# define PWM_CLK_PREA PWM_CLK_PREA_DIV1
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# define PWM_CLK_DIVA PWM_CLK_DIVA_OFF
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# undef CONFIG_SAMA5_PWM_CLKA_FREQUENCY
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# define CLKA_PRE_BITS PWM_CLK_PREA_DIV1
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# define CLKA_DIV_BITS PWM_CLK_DIVA_OFF
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#endif
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#ifdef CONFIG_SAMA5_PWM_CLKB
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@ -168,61 +170,61 @@
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# error CONFIG_SAMA5_PWM_CLKB_FREQUENCY is not defined
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# elif (BOARD_MCK_FREQUENCY / CONFIG_SAMA5_PWM_CLKB_FREQUENCY) < 256
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# define PWM_CLK_PREB PWM_CLK_PREB_DIV1
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# define CLKB_PRE 1
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# define CLKB_PRE_BITS PWM_CLK_PREB_DIV1
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# define CLKB_PRE 1
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# elif (BOARD_MCK_FREQUENCY / 2 / CONFIG_SAMA5_PWM_CLKB_FREQUENCY) < 256
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# define PWM_CLK_PREB PWM_CLK_PREB_DIV2
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# define CLKB_PRE 2
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# define CLKB_PRE_BITS PWM_CLK_PREB_DIV2
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# define CLKB_PRE 2
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# elif (BOARD_MCK_FREQUENCY / 4 / CONFIG_SAMA5_PWM_CLKB_FREQUENCY) < 256
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# define PWM_CLK_PREB PWM_CLK_PREB_DIV4
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# define CLKB_PRE 4
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# define CLKB_PRE_BITS PWM_CLK_PREB_DIV4
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# define CLKB_PRE 4
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# elif (BOARD_MCK_FREQUENCY / 8 / CONFIG_SAMA5_PWM_CLKB_FREQUENCY) < 256
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# define PWM_CLK_PREB PWM_CLK_PREB_DIV8
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# define CLKB_PRE 8
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# define CLKB_PRE_BITS PWM_CLK_PREB_DIV8
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# define CLKB_PRE 8
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# elif (BOARD_MCK_FREQUENCY / 16 / CONFIG_SAMA5_PWM_CLKB_FREQUENCY) < 256
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# define PWM_CLK_PREB PWM_CLK_PREB_DIV16
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# define CLKB_PRE 16
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# define CLKB_PRE_BITS PWM_CLK_PREB_DIV16
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# define CLKB_PRE 16
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# elif (BOARD_MCK_FREQUENCY / 32 / CONFIG_SAMA5_PWM_CLKB_FREQUENCY) < 256
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# define PWM_CLK_PREB PWM_CLK_PREB_DIV32
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# define CLKB_PRE 32
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# define CLKB_PRE_BITS PWM_CLK_PREB_DIV32
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# define CLKB_PRE 32
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# elif (BOARD_MCK_FREQUENCY / 64 / CONFIG_SAMA5_PWM_CLKB_FREQUENCY) < 256
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# define PWM_CLK_PREB PWM_CLK_PREB_DIV64
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# define CLKB_PRE 64
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# define CLKB_PRE_BITS PWM_CLK_PREB_DIV64
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# define CLKB_PRE 64
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# elif (BOARD_MCK_FREQUENCY / 128 / CONFIG_SAMA5_PWM_CLKB_FREQUENCY) < 256
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# define PWM_CLK_PREB PWM_CLK_PREB_DIV128
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# define CLKB_PRE 128
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# define CLKB_PRE_BITS PWM_CLK_PREB_DIV128
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# define CLKB_PRE 128
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# elif (BOARD_MCK_FREQUENCY / 256 / CONFIG_SAMA5_PWM_CLKB_FREQUENCY) < 256
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# define PWM_CLK_PREB PWM_CLK_PREB_DIV256
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# define CLKB_PRE 256
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# define CLKB_PRE_BITS PWM_CLK_PREB_DIV256
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# define CLKB_PRE 256
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# elif (BOARD_MCK_FREQUENCY / 512 / CONFIG_SAMA5_PWM_CLKB_FREQUENCY) < 256
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# define PWM_CLK_PREB PWM_CLK_PREB_DIV512
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# define CLKB_PRE 512
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# define CLKB_PRE_BITS PWM_CLK_PREB_DIV512
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# define CLKB_PRE 512
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# elif (BOARD_MCK_FREQUENCY / 1024 / CONFIG_SAMA5_PWM_CLKB_FREQUENCY) < 256
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# define PWM_CLK_PREB PWM_CLK_PREB_DIV1024
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# define CLKB_PRE 1024
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# define CLKB_PRE_BITS PWM_CLK_PREB_DIV1024
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# define CLKB_PRE 1024
|
||||
|
||||
# else
|
||||
# error Cannot realize CONFIG_SAMA5_PWM_CLKB_FREQUENCY
|
||||
# endif
|
||||
|
||||
# define CLKB_DIV (BOARD_MCK_FREQUENCY / CLKB_PRE / CONFIG_SAMA5_PWM_CLKB_FREQUENCY / )
|
||||
# define CLKB_DIV (BOARD_MCK_FREQUENCY / CLKB_PRE / CONFIG_SAMA5_PWM_CLKB_FREQUENCY)
|
||||
# define CLKB_FREQUENCY (BOARD_MCK_FREQUENCY / CLKB_PRE / CLKB_DIV)
|
||||
# define PWM_CLK_DIVB PWM_CLK_DIVB(CLKB_DIV)
|
||||
# define CLKB_DIV_BITS PWM_CLK_DIVB(CLKB_DIV)
|
||||
|
||||
#else
|
||||
# undef CONFIG_SAMA5_PWM_CLKB_FREQUENCY
|
||||
# define PWM_CLK_PREB PWM_CLK_PREB_DIV1
|
||||
# define PWM_CLK_DIVB PWM_CLK_DIVB_OFF
|
||||
# undef CONFIG_SAMA5_PWM_CLKB_FREQUENCY
|
||||
# define CLKB_PRE_BITS PWM_CLK_PREB_DIV1
|
||||
# define CLKB_DIV_BITS PWM_CLK_DIVB_OFF
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SAMA5_PWM_CHAN0
|
||||
|
|
@ -230,27 +232,27 @@
|
|||
# undef CONFIG_SAMA5_PWM_CHAN0_CLKA
|
||||
# undef CONFIG_SAMA5_PWM_CHAN0_CLKB
|
||||
# if CONFIG_SAMA5_PWM_CHAN0_MCKDIV == 1
|
||||
# SAMA5_PWM_CHAN0_MCKDIV_LOG2 = 0
|
||||
# define SAMA5_PWM_CHAN0_MCKDIV_LOG2 = 0
|
||||
# elif CONFIG_SAMA5_PWM_CHAN0_MCKDIV == 2
|
||||
# SAMA5_PWM_CHAN0_MCKDIV_LOG2 = 1
|
||||
# define SAMA5_PWM_CHAN0_MCKDIV_LOG2 = 1
|
||||
# elif CONFIG_SAMA5_PWM_CHAN0_MCKDIV == 4
|
||||
# SAMA5_PWM_CHAN0_MCKDIV_LOG2 = 2
|
||||
# define SAMA5_PWM_CHAN0_MCKDIV_LOG2 = 2
|
||||
# elif CONFIG_SAMA5_PWM_CHAN0_MCKDIV == 8
|
||||
# SAMA5_PWM_CHAN0_MCKDIV_LOG2 = 3
|
||||
# define SAMA5_PWM_CHAN0_MCKDIV_LOG2 = 3
|
||||
# elif CONFIG_SAMA5_PWM_CHAN0_MCKDIV == 16
|
||||
# SAMA5_PWM_CHAN0_MCKDIV_LOG2 = 4
|
||||
# define SAMA5_PWM_CHAN0_MCKDIV_LOG2 = 4
|
||||
# elif CONFIG_SAMA5_PWM_CHAN0_MCKDIV == 32
|
||||
# SAMA5_PWM_CHAN0_MCKDIV_LOG2 = 5
|
||||
# define SAMA5_PWM_CHAN0_MCKDIV_LOG2 = 5
|
||||
# elif CONFIG_SAMA5_PWM_CHAN0_MCKDIV == 64
|
||||
# SAMA5_PWM_CHAN0_MCKDIV_LOG2 = 6
|
||||
# define SAMA5_PWM_CHAN0_MCKDIV_LOG2 = 6
|
||||
# elif CONFIG_SAMA5_PWM_CHAN0_MCKDIV == 128
|
||||
# SAMA5_PWM_CHAN0_MCKDIV_LOG2 = 7
|
||||
# define SAMA5_PWM_CHAN0_MCKDIV_LOG2 = 7
|
||||
# elif CONFIG_SAMA5_PWM_CHAN0_MCKDIV == 256
|
||||
# SAMA5_PWM_CHAN0_MCKDIV_LOG2 = 8
|
||||
# define SAMA5_PWM_CHAN0_MCKDIV_LOG2 = 8
|
||||
# elif CONFIG_SAMA5_PWM_CHAN0_MCKDIV == 512
|
||||
# SAMA5_PWM_CHAN0_MCKDIV_LOG2 = 9
|
||||
# define SAMA5_PWM_CHAN0_MCKDIV_LOG2 = 9
|
||||
# elif CONFIG_SAMA5_PWM_CHAN0_MCKDIV == 1024
|
||||
# SAMA5_PWM_CHAN0_MCKDIV_LOG2 = 10
|
||||
# define SAMA5_PWM_CHAN0_MCKDIV_LOG2 = 10
|
||||
# else
|
||||
# error Unsupported MCK divider value
|
||||
# endif
|
||||
|
|
@ -269,27 +271,27 @@
|
|||
# undef CONFIG_SAMA5_PWM_CHAN1_CLKA
|
||||
# undef CONFIG_SAMA5_PWM_CHAN1_CLKB
|
||||
# if CONFIG_SAMA5_PWM_CHAN1_MCKDIV == 1
|
||||
# SAMA5_PWM_CHAN1_MCKDIV_LOG2 = 0
|
||||
# define SAMA5_PWM_CHAN1_MCKDIV_LOG2 0
|
||||
# elif CONFIG_SAMA5_PWM_CHAN1_MCKDIV == 2
|
||||
# SAMA5_PWM_CHAN1_MCKDIV_LOG2 = 1
|
||||
# define SAMA5_PWM_CHAN1_MCKDIV_LOG2 1
|
||||
# elif CONFIG_SAMA5_PWM_CHAN1_MCKDIV == 4
|
||||
# SAMA5_PWM_CHAN1_MCKDIV_LOG2 = 2
|
||||
# define SAMA5_PWM_CHAN1_MCKDIV_LOG2 2
|
||||
# elif CONFIG_SAMA5_PWM_CHAN1_MCKDIV == 8
|
||||
# SAMA5_PWM_CHAN1_MCKDIV_LOG2 = 3
|
||||
# define SAMA5_PWM_CHAN1_MCKDIV_LOG2 3
|
||||
# elif CONFIG_SAMA5_PWM_CHAN1_MCKDIV == 16
|
||||
# SAMA5_PWM_CHAN1_MCKDIV_LOG2 = 4
|
||||
# define SAMA5_PWM_CHAN1_MCKDIV_LOG2 4
|
||||
# elif CONFIG_SAMA5_PWM_CHAN1_MCKDIV == 32
|
||||
# SAMA5_PWM_CHAN1_MCKDIV_LOG2 = 5
|
||||
# define SAMA5_PWM_CHAN1_MCKDIV_LOG2 5
|
||||
# elif CONFIG_SAMA5_PWM_CHAN1_MCKDIV == 64
|
||||
# SAMA5_PWM_CHAN1_MCKDIV_LOG2 = 6
|
||||
# define SAMA5_PWM_CHAN1_MCKDIV_LOG2 6
|
||||
# elif CONFIG_SAMA5_PWM_CHAN1_MCKDIV == 128
|
||||
# SAMA5_PWM_CHAN1_MCKDIV_LOG2 = 7
|
||||
# define SAMA5_PWM_CHAN1_MCKDIV_LOG2 7
|
||||
# elif CONFIG_SAMA5_PWM_CHAN1_MCKDIV == 256
|
||||
# SAMA5_PWM_CHAN1_MCKDIV_LOG2 = 8
|
||||
# define SAMA5_PWM_CHAN1_MCKDIV_LOG2 8
|
||||
# elif CONFIG_SAMA5_PWM_CHAN1_MCKDIV == 512
|
||||
# SAMA5_PWM_CHAN1_MCKDIV_LOG2 = 9
|
||||
# define SAMA5_PWM_CHAN1_MCKDIV_LOG2 9
|
||||
# elif CONFIG_SAMA5_PWM_CHAN1_MCKDIV == 1024
|
||||
# SAMA5_PWM_CHAN1_MCKDIV_LOG2 = 10
|
||||
# define SAMA5_PWM_CHAN1_MCKDIV_LOG2 10
|
||||
# else
|
||||
# error Unsupported MCK divider value
|
||||
# endif
|
||||
|
|
@ -308,27 +310,27 @@
|
|||
# undef CONFIG_SAMA5_PWM_CHAN2_CLKA
|
||||
# undef CONFIG_SAMA5_PWM_CHAN2_CLKB
|
||||
# if CONFIG_SAMA5_PWM_CHAN2_MCKDIV == 1
|
||||
# SAMA5_PWM_CHAN2_MCKDIV_LOG2 = 0
|
||||
# define SAMA5_PWM_CHAN2_MCKDIV_LOG2 0
|
||||
# elif CONFIG_SAMA5_PWM_CHAN2_MCKDIV == 2
|
||||
# SAMA5_PWM_CHAN2_MCKDIV_LOG2 = 1
|
||||
# define SAMA5_PWM_CHAN2_MCKDIV_LOG2 1
|
||||
# elif CONFIG_SAMA5_PWM_CHAN2_MCKDIV == 4
|
||||
# SAMA5_PWM_CHAN2_MCKDIV_LOG2 = 2
|
||||
# define SAMA5_PWM_CHAN2_MCKDIV_LOG2 2
|
||||
# elif CONFIG_SAMA5_PWM_CHAN2_MCKDIV == 8
|
||||
# SAMA5_PWM_CHAN2_MCKDIV_LOG2 = 3
|
||||
# define SAMA5_PWM_CHAN2_MCKDIV_LOG2 3
|
||||
# elif CONFIG_SAMA5_PWM_CHAN2_MCKDIV == 16
|
||||
# SAMA5_PWM_CHAN2_MCKDIV_LOG2 = 4
|
||||
# define SAMA5_PWM_CHAN2_MCKDIV_LOG2 4
|
||||
# elif CONFIG_SAMA5_PWM_CHAN2_MCKDIV == 32
|
||||
# SAMA5_PWM_CHAN2_MCKDIV_LOG2 = 5
|
||||
# define SAMA5_PWM_CHAN2_MCKDIV_LOG2 5
|
||||
# elif CONFIG_SAMA5_PWM_CHAN2_MCKDIV == 64
|
||||
# SAMA5_PWM_CHAN2_MCKDIV_LOG2 = 6
|
||||
# define SAMA5_PWM_CHAN2_MCKDIV_LOG2 6
|
||||
# elif CONFIG_SAMA5_PWM_CHAN2_MCKDIV == 128
|
||||
# SAMA5_PWM_CHAN2_MCKDIV_LOG2 = 7
|
||||
# define SAMA5_PWM_CHAN2_MCKDIV_LOG2 7
|
||||
# elif CONFIG_SAMA5_PWM_CHAN2_MCKDIV == 256
|
||||
# SAMA5_PWM_CHAN2_MCKDIV_LOG2 = 8
|
||||
# define SAMA5_PWM_CHAN2_MCKDIV_LOG2 8
|
||||
# elif CONFIG_SAMA5_PWM_CHAN2_MCKDIV == 512
|
||||
# SAMA5_PWM_CHAN2_MCKDIV_LOG2 = 9
|
||||
# define SAMA5_PWM_CHAN2_MCKDIV_LOG2 9
|
||||
# elif CONFIG_SAMA5_PWM_CHAN2_MCKDIV == 1024
|
||||
# SAMA5_PWM_CHAN2_MCKDIV_LOG2 = 10
|
||||
# define SAMA5_PWM_CHAN2_MCKDIV_LOG2 10
|
||||
# else
|
||||
# error Unsupported MCK divider value
|
||||
# endif
|
||||
|
|
@ -347,27 +349,27 @@
|
|||
# undef CONFIG_SAMA5_PWM_CHAN3_CLKA
|
||||
# undef CONFIG_SAMA5_PWM_CHAN3_CLKB
|
||||
# if CONFIG_SAMA5_PWM_CHAN3_MCKDIV == 1
|
||||
# SAMA5_PWM_CHAN3_MCKDIV_LOG2 = 0
|
||||
# define SAMA5_PWM_CHAN3_MCKDIV_LOG2 0
|
||||
# elif CONFIG_SAMA5_PWM_CHAN3_MCKDIV == 2
|
||||
# SAMA5_PWM_CHAN3_MCKDIV_LOG2 = 1
|
||||
# define SAMA5_PWM_CHAN3_MCKDIV_LOG2 1
|
||||
# elif CONFIG_SAMA5_PWM_CHAN3_MCKDIV == 4
|
||||
# SAMA5_PWM_CHAN3_MCKDIV_LOG2 = 2
|
||||
# define SAMA5_PWM_CHAN3_MCKDIV_LOG2 2
|
||||
# elif CONFIG_SAMA5_PWM_CHAN3_MCKDIV == 8
|
||||
# SAMA5_PWM_CHAN3_MCKDIV_LOG2 = 3
|
||||
# define SAMA5_PWM_CHAN3_MCKDIV_LOG2 3
|
||||
# elif CONFIG_SAMA5_PWM_CHAN3_MCKDIV == 16
|
||||
# SAMA5_PWM_CHAN3_MCKDIV_LOG2 = 4
|
||||
# define SAMA5_PWM_CHAN3_MCKDIV_LOG2 4
|
||||
# elif CONFIG_SAMA5_PWM_CHAN3_MCKDIV == 32
|
||||
# SAMA5_PWM_CHAN3_MCKDIV_LOG2 = 5
|
||||
# define SAMA5_PWM_CHAN3_MCKDIV_LOG2 5
|
||||
# elif CONFIG_SAMA5_PWM_CHAN3_MCKDIV == 64
|
||||
# SAMA5_PWM_CHAN3_MCKDIV_LOG2 = 6
|
||||
# define SAMA5_PWM_CHAN3_MCKDIV_LOG2 6
|
||||
# elif CONFIG_SAMA5_PWM_CHAN3_MCKDIV == 128
|
||||
# SAMA5_PWM_CHAN3_MCKDIV_LOG2 = 7
|
||||
# define SAMA5_PWM_CHAN3_MCKDIV_LOG2 7
|
||||
# elif CONFIG_SAMA5_PWM_CHAN3_MCKDIV == 256
|
||||
# SAMA5_PWM_CHAN3_MCKDIV_LOG2 = 8
|
||||
# define SAMA5_PWM_CHAN3_MCKDIV_LOG2 8
|
||||
# elif CONFIG_SAMA5_PWM_CHAN3_MCKDIV == 512
|
||||
# SAMA5_PWM_CHAN3_MCKDIV_LOG2 = 9
|
||||
# define SAMA5_PWM_CHAN3_MCKDIV_LOG2 9
|
||||
# elif CONFIG_SAMA5_PWM_CHAN3_MCKDIV == 1024
|
||||
# SAMA5_PWM_CHAN3_MCKDIV_LOG2 = 10
|
||||
# define SAMA5_PWM_CHAN3_MCKDIV_LOG2 10
|
||||
# else
|
||||
# error Unsupported MCK divider value
|
||||
# endif
|
||||
|
|
@ -413,7 +415,6 @@
|
|||
# define pwmlldbg(x...)
|
||||
# define pwmvdbg(x...)
|
||||
# define pwmllvdbg(x...)
|
||||
# define pwm_dumpgpio(p,m)
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
|
|
@ -523,7 +524,7 @@ static const struct pwm_ops_s g_pwmops =
|
|||
|
||||
/* This is the overall state of the PWM peripheral */
|
||||
|
||||
static sam_pwm_s g_pwm =
|
||||
static struct sam_pwm_s g_pwm =
|
||||
{
|
||||
.initialized = false,
|
||||
#ifndef PWM_SINGLE
|
||||
|
|
@ -537,7 +538,9 @@ static sam_pwm_s g_pwm =
|
|||
static struct sam_pwm_chan_s g_pwm_chan0 =
|
||||
{
|
||||
.ops = &g_pwmops,
|
||||
#ifndef PWM_SINGLE
|
||||
.pwm = &g_pwm,
|
||||
#endif
|
||||
.channel = 0,
|
||||
.base = SAM_PWM_CHAN_BASE(0),
|
||||
|
||||
|
|
@ -570,7 +573,9 @@ static struct sam_pwm_chan_s g_pwm_chan0 =
|
|||
static struct sam_pwm_chan_s g_pwm_chan1 =
|
||||
{
|
||||
.ops = &g_pwmops,
|
||||
#ifndef PWM_SINGLE
|
||||
.pwm = &g_pwm,
|
||||
#endif
|
||||
.channel = 1,
|
||||
.base = SAM_PWM_CHAN_BASE(1),
|
||||
|
||||
|
|
@ -585,13 +590,13 @@ static struct sam_pwm_chan_s g_pwm_chan1 =
|
|||
# error No clock source for channel 0
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SAMA5_PWM_CHAN0_OUTPUTH
|
||||
#ifdef CONFIG_SAMA5_PWM_CHAN1_OUTPUTH
|
||||
.ohpincfg = PIO_PWM1_H,
|
||||
#endif
|
||||
#ifdef CONFIG_SAMA5_PWM_CHAN0_OUTPUTL
|
||||
#ifdef CONFIG_SAMA5_PWM_CHAN1_OUTPUTL
|
||||
.olpincfg = PIO_PWM1_L,
|
||||
#endif
|
||||
#ifdef CONFIG_SAMA5_PWM_CHAN0_FAULTINPUT
|
||||
#ifdef CONFIG_SAMA5_PWM_CHAN1_FAULTINPUT
|
||||
.fipincfg = PIO_PWM1_FI,
|
||||
#endif
|
||||
};
|
||||
|
|
@ -603,7 +608,9 @@ static struct sam_pwm_chan_s g_pwm_chan1 =
|
|||
static struct sam_pwm_chan_s g_pwm_chan2 =
|
||||
{
|
||||
.ops = &g_pwmops,
|
||||
#ifndef PWM_SINGLE
|
||||
.pwm = &g_pwm,
|
||||
#endif
|
||||
.channel = 2,
|
||||
.base = SAM_PWM_CHAN_BASE(2),
|
||||
|
||||
|
|
@ -618,13 +625,13 @@ static struct sam_pwm_chan_s g_pwm_chan2 =
|
|||
# error No clock source for channel 0
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SAMA5_PWM_CHAN0_OUTPUTH
|
||||
#ifdef CONFIG_SAMA5_PWM_CHAN2_OUTPUTH
|
||||
.ohpincfg = PIO_PWM2_H,
|
||||
#endif
|
||||
#ifdef CONFIG_SAMA5_PWM_CHAN0_OUTPUTL
|
||||
#ifdef CONFIG_SAMA5_PWM_CHAN2_OUTPUTL
|
||||
.olpincfg = PIO_PWM2_L,
|
||||
#endif
|
||||
#ifdef CONFIG_SAMA5_PWM_CHAN0_FAULTINPUT
|
||||
#ifdef CONFIG_SAMA5_PWM_CHAN2_FAULTINPUT
|
||||
.fipincfg = PIO_PWM2_FI,
|
||||
#endif
|
||||
};
|
||||
|
|
@ -636,8 +643,11 @@ static struct sam_pwm_chan_s g_pwm_chan2 =
|
|||
static struct sam_pwm_chan_s g_pwm_chan3 =
|
||||
{
|
||||
.ops = &g_pwmops,
|
||||
#ifndef PWM_SINGLE
|
||||
.pwm = &g_pwm,
|
||||
#endif
|
||||
.channel = 3,
|
||||
.base = SAM_PWM_CHAN_BASE(3),
|
||||
|
||||
#if defined(CONFIG_SAMA5_PWM_CHAN3_MCK)
|
||||
.clksrc = PWM_CLKSRC_MCK,
|
||||
|
|
@ -650,13 +660,13 @@ static struct sam_pwm_chan_s g_pwm_chan3 =
|
|||
# error No clock source for channel 0
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SAMA5_PWM_CHAN0_OUTPUTH
|
||||
#ifdef CONFIG_SAMA5_PWM_CHAN3_OUTPUTH
|
||||
.ohpincfg = PIO_PWM3_H,
|
||||
#endif
|
||||
#ifdef CONFIG_SAMA5_PWM_CHAN0_OUTPUTL
|
||||
#ifdef CONFIG_SAMA5_PWM_CHAN3_OUTPUTL
|
||||
.olpincfg = PIO_PWM3_L,
|
||||
#endif
|
||||
#ifdef CONFIG_SAMA5_PWM_CHAN0_FAULTINPUT
|
||||
#ifdef CONFIG_SAMA5_PWM_CHAN3_FAULTINPUT
|
||||
.fipincfg = PIO_PWM3_FI,
|
||||
#endif
|
||||
};
|
||||
|
|
@ -741,7 +751,7 @@ static uint32_t pwm_getreg(struct sam_pwm_chan_s *chan, int offset)
|
|||
uint32_t regval;
|
||||
|
||||
#ifdef PWM_SINGLE
|
||||
regaddr = SAM_PWMC_VBASE + offset
|
||||
regaddr = SAM_PWMC_VBASE + offset;
|
||||
#else
|
||||
struct sam_pwm_chan_s *pwm = chan->pwm;
|
||||
regaddr = pwm->base + offset;
|
||||
|
|
@ -812,7 +822,7 @@ static void pwm_putreg(struct sam_pwm_chan_s *chan, int offset, uint32_t regval)
|
|||
uintptr_t regaddr;
|
||||
|
||||
#ifdef PWM_SINGLE
|
||||
regaddr = SAM_PWMC_VBASE + offset
|
||||
regaddr = SAM_PWMC_VBASE + offset;
|
||||
#else
|
||||
struct sam_pwm_chan_s *pwm = chan->pwm;
|
||||
regaddr = pwm->base + offset;
|
||||
|
|
@ -995,7 +1005,6 @@ static int pwm_setup(FAR struct pwm_lowerhalf_s *dev)
|
|||
(void)sam_configpio(chan->fipincfg);
|
||||
}
|
||||
|
||||
pwm_dumpgpio(chan->pincfg, "PWM setup");
|
||||
return OK;
|
||||
}
|
||||
|
||||
|
|
@ -1018,9 +1027,8 @@ static int pwm_setup(FAR struct pwm_lowerhalf_s *dev)
|
|||
static int pwm_shutdown(FAR struct pwm_lowerhalf_s *dev)
|
||||
{
|
||||
FAR struct sam_pwm_chan_s *chan = (FAR struct sam_pwm_chan_s *)dev;
|
||||
uint32_t pincfg;
|
||||
|
||||
pwmvdbg("Channel %d pincfg: %08x\n", chan->channel, chan->pincfg);
|
||||
pwmvdbg("Channel %d\n", chan->channel);
|
||||
|
||||
/* Make sure that the output has been stopped */
|
||||
|
||||
|
|
@ -1053,19 +1061,19 @@ static int pwm_start(FAR struct pwm_lowerhalf_s *dev,
|
|||
FAR struct sam_pwm_chan_s *chan = (FAR struct sam_pwm_chan_s *)dev;
|
||||
uint32_t regval;
|
||||
uint32_t cprd;
|
||||
uint32_t srcfreq;
|
||||
uint32_t fsrc;
|
||||
|
||||
/* Disable the channel (should already be disabled) */
|
||||
|
||||
sam_putreg(priv, SAM_PWM_DIS_OFFSET, PWM_CHID(chan->channel));
|
||||
pwm_putreg(chan, SAM_PWM_DIS_OFFSET, PWM_CHID(chan->channel));
|
||||
|
||||
/* Determine the clock source */
|
||||
|
||||
switch (chan->clksrc)
|
||||
{
|
||||
case PWM_CLKSRC_MCK:
|
||||
regval = PWM_CMR_CPRE_MCKDIV(SAMA5_PWM_CHAN0_MCKDIV_LOG2);
|
||||
fsrc = BOARD_MCK_FREQUENCY >> SAMA5_PWM_CHAN0_MCKDIV_LOG2;
|
||||
regval = PWM_CMR_CPRE_MCKDIV(chan->divlog2);
|
||||
fsrc = BOARD_MCK_FREQUENCY >> chan->divlog2;
|
||||
break;
|
||||
|
||||
case PWM_CLKSRC_CLKA:
|
||||
|
|
@ -1085,7 +1093,7 @@ static int pwm_start(FAR struct pwm_lowerhalf_s *dev,
|
|||
|
||||
/* Configure the channel */
|
||||
|
||||
sam_chan_putreg(priv, SAM_PWM_CMR_OFFSET, PWM_CMR_CPRE_CLKA);
|
||||
pwm_chan_putreg(chan, SAM_PWM_CMR_OFFSET, PWM_CMR_CPRE_CLKA);
|
||||
|
||||
/* Set the PWM period.
|
||||
*
|
||||
|
|
@ -1107,7 +1115,7 @@ static int pwm_start(FAR struct pwm_lowerhalf_s *dev,
|
|||
*/
|
||||
|
||||
cprd = (info->frequency + (fsrc >> 1)) / fsrc;
|
||||
sam_chan_putreg(priv, SAM_PWM_CPRD_OFFSET, cprd);
|
||||
pwm_chan_putreg(chan, SAM_PWM_CPRD_OFFSET, cprd);
|
||||
|
||||
/* Set the PWM duty. Since the PWM is disabled, we can write directly
|
||||
* to the CTDY (vs. the CTDYUPD) register.
|
||||
|
|
@ -1121,11 +1129,11 @@ static int pwm_start(FAR struct pwm_lowerhalf_s *dev,
|
|||
regval = cprd;
|
||||
}
|
||||
|
||||
sam_chan_putreg(priv, SAM_PWM_CDTY_OFFSET, regval);
|
||||
pwm_chan_putreg(chan, SAM_PWM_CDTY_OFFSET, regval);
|
||||
|
||||
/* Enable the channel */
|
||||
|
||||
sam_putreg(priv, SAM_PWM_ENA_OFFSET, PWM_CHID(chan->channel));
|
||||
pwm_putreg(chan, SAM_PWM_ENA_OFFSET, PWM_CHID(chan->channel));
|
||||
return OK;
|
||||
}
|
||||
|
||||
|
|
@ -1156,12 +1164,12 @@ static int pwm_stop(FAR struct pwm_lowerhalf_s *dev)
|
|||
|
||||
/* Disable further PWM interrupts from this channel */
|
||||
|
||||
sam_putreg(chan, SAM_PWM_IDR1_OFFSET,
|
||||
pwm_putreg(chan, SAM_PWM_IDR1_OFFSET,
|
||||
PWM_INT1_CHID(chan->channel) | PWM_INT1_FCHID(chan->channel));
|
||||
|
||||
/* Disable the channel */
|
||||
|
||||
sam_putreg(priv, SAM_PWM_DIS_OFFSET, PWM_CHID(chan->channel));
|
||||
pwm_putreg(chan, SAM_PWM_DIS_OFFSET, PWM_CHID(chan->channel));
|
||||
pwm_dumpregs(chan, "After stop");
|
||||
return OK;
|
||||
}
|
||||
|
|
@ -1236,7 +1244,7 @@ static void pwm_resetpins(FAR struct sam_pwm_chan_s *chan)
|
|||
* Name: sam_pwminitialize
|
||||
*
|
||||
* Description:
|
||||
* Initialize one timer for use with the upper_level PWM driver.
|
||||
* Initialize one PWM channel for use with the upper_level PWM driver.
|
||||
*
|
||||
* Input Parameters:
|
||||
* channel - A number identifying the PWM channel use.
|
||||
|
|
@ -1254,7 +1262,7 @@ FAR struct pwm_lowerhalf_s *sam_pwminitialize(int channel)
|
|||
|
||||
pwmvdbg("Channel %d\n", channel);
|
||||
|
||||
switch (timer)
|
||||
switch (channel)
|
||||
{
|
||||
#ifdef CONFIG_SAMA5_PWM_CHAN0
|
||||
case 0:
|
||||
|
|
@ -1301,17 +1309,17 @@ FAR struct pwm_lowerhalf_s *sam_pwminitialize(int channel)
|
|||
{
|
||||
/* Enable the PWM peripheral clock */
|
||||
|
||||
sam_pwm_enableclks();
|
||||
sam_pwm_enableclk();
|
||||
|
||||
/* Set clock A and clock B */
|
||||
|
||||
regval = PWM_CLK_PREA | PWM_CLK_DIVA | PWM_CLK_PREB | PWM_CLK_DIVB;
|
||||
sam_putreg(chan, SAM_PWM_CLK_OFFSET, regval);
|
||||
regval = (CLKA_PRE_BITS | CLKA_DIV_BITS | CLKB_PRE_BITS | CLKB_DIV_BITS);
|
||||
pwm_putreg(chan, SAM_PWM_CLK_OFFSET, regval);
|
||||
|
||||
/* Disable all PWM interrupts at the PWM peripheral */
|
||||
|
||||
sam_putreg(chan, SAM_PWM_IDR1_OFFSET, PWM_INT1_ALL);
|
||||
sam_putreg(chan, SAM_PWM_IDR2_OFFSET, PWM_INT2_ALL);
|
||||
pwm_putreg(chan, SAM_PWM_IDR1_OFFSET, PWM_INT1_ALL);
|
||||
pwm_putreg(chan, SAM_PWM_IDR2_OFFSET, PWM_INT2_ALL);
|
||||
|
||||
/* Attach the PWM interrupt handler */
|
||||
|
||||
|
|
@ -1327,8 +1335,8 @@ FAR struct pwm_lowerhalf_s *sam_pwminitialize(int channel)
|
|||
|
||||
/* Clear any pending PWM interrupts */
|
||||
|
||||
(void)sam_getreg(chan, SAM_PWM_ISR1_OFFSET);
|
||||
(void)sam_getreg(chan, SAM_PWM_ISR2_OFFSET);
|
||||
(void)pwm_getreg(chan, SAM_PWM_ISR1_OFFSET);
|
||||
(void)pwm_getreg(chan, SAM_PWM_ISR2_OFFSET);
|
||||
|
||||
/* Enable PWM interrupts at the AIC */
|
||||
|
||||
|
|
|
|||
|
|
@ -43,6 +43,7 @@
|
|||
#include <nuttx/config.h>
|
||||
|
||||
#include "chip.h"
|
||||
#include "chip/sam_pwm.h"
|
||||
|
||||
#ifdef CONFIG_SAMA5_PWM
|
||||
|
||||
|
|
|
|||
|
|
@ -1215,6 +1215,7 @@ config STM32_TIM1_PWM
|
|||
bool "TIM1 PWM"
|
||||
default n
|
||||
depends on STM32_TIM1
|
||||
select ARCH_HAVE_PWM_PULSECOUNT
|
||||
---help---
|
||||
Reserve timer 1 for use by PWM
|
||||
|
||||
|
|
@ -1236,6 +1237,7 @@ config STM32_TIM2_PWM
|
|||
bool "TIM2 PWM"
|
||||
default n
|
||||
depends on STM32_TIM2
|
||||
select ARCH_HAVE_PWM_PULSECOUNT
|
||||
---help---
|
||||
Reserve timer 2 for use by PWM
|
||||
|
||||
|
|
@ -1257,6 +1259,7 @@ config STM32_TIM3_PWM
|
|||
bool "TIM3 PWM"
|
||||
default n
|
||||
depends on STM32_TIM3
|
||||
select ARCH_HAVE_PWM_PULSECOUNT
|
||||
---help---
|
||||
Reserve timer 3 for use by PWM
|
||||
|
||||
|
|
@ -1278,6 +1281,7 @@ config STM32_TIM4_PWM
|
|||
bool "TIM4 PWM"
|
||||
default n
|
||||
depends on STM32_TIM4
|
||||
select ARCH_HAVE_PWM_PULSECOUNT
|
||||
---help---
|
||||
Reserve timer 4 for use by PWM
|
||||
|
||||
|
|
@ -1299,6 +1303,7 @@ config STM32_TIM5_PWM
|
|||
bool "TIM5 PWM"
|
||||
default n
|
||||
depends on STM32_TIM5
|
||||
select ARCH_HAVE_PWM_PULSECOUNT
|
||||
---help---
|
||||
Reserve timer 5 for use by PWM
|
||||
|
||||
|
|
@ -1320,6 +1325,7 @@ config STM32_TIM8_PWM
|
|||
bool "TIM8 PWM"
|
||||
default n
|
||||
depends on STM32_TIM8
|
||||
select ARCH_HAVE_PWM_PULSECOUNT
|
||||
---help---
|
||||
Reserve timer 8 for use by PWM
|
||||
|
||||
|
|
@ -1341,6 +1347,7 @@ config STM32_TIM9_PWM
|
|||
bool "TIM9 PWM"
|
||||
default n
|
||||
depends on STM32_TIM9
|
||||
select ARCH_HAVE_PWM_PULSECOUNT
|
||||
---help---
|
||||
Reserve timer 9 for use by PWM
|
||||
|
||||
|
|
@ -1362,6 +1369,7 @@ config STM32_TIM10_PWM
|
|||
bool "TIM10 PWM"
|
||||
default n
|
||||
depends on STM32_TIM10
|
||||
select ARCH_HAVE_PWM_PULSECOUNT
|
||||
---help---
|
||||
Reserve timer 10 for use by PWM
|
||||
|
||||
|
|
@ -1383,6 +1391,7 @@ config STM32_TIM11_PWM
|
|||
bool "TIM11 PWM"
|
||||
default n
|
||||
depends on STM32_TIM11
|
||||
select ARCH_HAVE_PWM_PULSECOUNT
|
||||
---help---
|
||||
Reserve timer 11 for use by PWM
|
||||
|
||||
|
|
@ -1404,6 +1413,7 @@ config STM32_TIM12_PWM
|
|||
bool "TIM12 PWM"
|
||||
default n
|
||||
depends on STM32_TIM12
|
||||
select ARCH_HAVE_PWM_PULSECOUNT
|
||||
---help---
|
||||
Reserve timer 12 for use by PWM
|
||||
|
||||
|
|
@ -1425,6 +1435,7 @@ config STM32_TIM13_PWM
|
|||
bool "TIM13 PWM"
|
||||
default n
|
||||
depends on STM32_TIM13
|
||||
select ARCH_HAVE_PWM_PULSECOUNT
|
||||
---help---
|
||||
Reserve timer 13 for use by PWM
|
||||
|
||||
|
|
@ -1446,6 +1457,7 @@ config STM32_TIM14_PWM
|
|||
bool "TIM14 PWM"
|
||||
default n
|
||||
depends on STM32_TIM14
|
||||
select ARCH_HAVE_PWM_PULSECOUNT
|
||||
---help---
|
||||
Reserve timer 14 for use by PWM
|
||||
|
||||
|
|
|
|||
|
|
@ -80,6 +80,10 @@ config CAN_LOOPBACK
|
|||
|
||||
endif
|
||||
|
||||
config ARCH_HAVE_PWM_PULSECOUNT
|
||||
bool
|
||||
default n
|
||||
|
||||
menuconfig PWM
|
||||
bool "PWM Driver Support"
|
||||
default n
|
||||
|
|
@ -91,6 +95,7 @@ if PWM
|
|||
config PWM_PULSECOUNT
|
||||
bool "PWM Pulse Count Support"
|
||||
default n
|
||||
depends on ARCH_HAVE_PWM_PULSECOUNT
|
||||
---help---
|
||||
Some hardware will support generation of a fixed number of pulses.
|
||||
This might be used, for example to support a stepper motor. If the
|
||||
|
|
|
|||
Loading…
Reference in a new issue