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Fix nxstyle issue

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Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
This commit is contained in:
Xiang Xiao 2020-05-05 01:34:04 +08:00 committed by patacongo
parent de33f86ae3
commit b7d922960f
35 changed files with 622 additions and 584 deletions
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10
arch/arm/src/am335x/am335x_i2c.c
View file

@ -825,7 +825,7 @@ static void am335x_i2c_tracenew(FAR struct am335x_i2c_priv_s *priv,
if (trace->count != 0)
{
/* Yes.. bump up the trace index (unless we are out of trace entries) */
/* Yes.. bump up the trace index (unless out of trace entries) */
if (priv->tndx >= (CONFIG_I2C_NTRACE - 1))
{
@ -941,7 +941,9 @@ static void am335x_i2c_setclock(FAR struct am335x_i2c_priv_s *priv,
I2C_CON_EN, 0);
}
/* I2C bus clock is Source Clock (Hz) / ((psc + 1) * (scll + 7 + sclh + 5)) */
/* I2C bus clock is:
* Source Clock (Hz) / ((psc + 1) * (scll + 7 + sclh + 5))
*/
for (scl = 14; scl < 522; scl += 2)
{
@ -1479,7 +1481,7 @@ static int am335x_i2c_transfer(FAR struct i2c_master_s *dev,
else if ((priv->status & I2C_IRQ_ERRORMASK) != 0)
{
/* I2C_IRQ_ERRORMASK is the 'OR' of the following individual bits: */
/* I2C_IRQ_ERRORMASK is the OR of the following individual bits: */
if (priv->status & I2C_IRQ_AL)
{
@ -1531,7 +1533,7 @@ static int am335x_i2c_transfer(FAR struct i2c_master_s *dev,
am335x_i2c_tracedump(priv);
/* Ensure that any ISR happening after we finish can't overwrite any user data */
/* Ensure ISR happening after we finish can't overwrite any user data */
priv->dcnt = 0;
priv->ptr = NULL;

2
arch/arm/src/efm32/efm32_i2c.c
View file

@ -767,7 +767,7 @@ static void efm32_i2c_tracenew(FAR struct efm32_i2c_priv_s *priv)
if (trace->count != 0)
{
/* Yes.. bump up the trace index (unless we are out of trace entries) */
/* Yes.. bump up the trace index (unless out of trace entries) */
if (priv->tndx >= (CONFIG_I2C_NTRACE - 1))
{

48
arch/arm/src/efm32/efm32_usbhost.c
View file

@ -1654,7 +1654,9 @@ static void efm32_transfer_start(FAR struct efm32_usbhost_s *priv, int chidx)
if (minsize <= avail)
{
/* Yes.. Get the size of the biggest thing that we can put in the Tx FIFO now */
/* Yes.. Get the size of the biggest thing that we can put
* in the Tx FIFO now
*/
wrsize = chan->buflen;
if (wrsize > avail)
@ -1973,7 +1975,7 @@ static ssize_t efm32_in_transfer(FAR struct efm32_usbhost_s *priv, int chidx,
return (ssize_t)ret;
}
/* Set up for the transfer based on the direction and the endpoint type */
/* Set up for the transfer based on the direction and the endpoint */
ret = efm32_in_setup(priv, chidx);
if (ret < 0)
@ -2039,7 +2041,7 @@ static void efm32_in_next(FAR struct efm32_usbhost_s *priv,
int result;
int ret;
/* Is the full transfer complete? Did the last chunk transfer complete OK? */
/* Is the full transfer complete? Did the last chunk transfer OK? */
result = -(int)chan->result;
if (chan->xfrd < chan->buflen && result == OK)
@ -2102,7 +2104,7 @@ static int efm32_in_asynch(FAR struct efm32_usbhost_s *priv, int chidx,
FAR struct efm32_chan_s *chan;
int ret;
/* Set up for the transfer data and callback BEFORE starting the first transfer */
/* Set up for the transfer BEFORE starting the first transfer */
chan = &priv->chan[chidx];
chan->buffer = buffer;
@ -2247,7 +2249,7 @@ static ssize_t efm32_out_transfer(FAR struct efm32_usbhost_s *priv,
return (ssize_t)ret;
}
/* Set up for the transfer based on the direction and the endpoint type */
/* Set up for the transfer based on the direction and the endpoint */
ret = efm32_out_setup(priv, chidx);
if (ret < 0)
@ -2298,7 +2300,7 @@ static ssize_t efm32_out_transfer(FAR struct efm32_usbhost_s *priv,
}
else
{
/* Successfully transferred. Update the buffer pointer and length */
/* Successfully transferred. Update the buffer pointer/length */
buffer += xfrlen;
buflen -= xfrlen;
@ -2331,7 +2333,7 @@ static void efm32_out_next(FAR struct efm32_usbhost_s *priv,
int result;
int ret;
/* Is the full transfer complete? Did the last chunk transfer complete OK? */
/* Is the full transfer complete? Did the last chunk transfer OK? */
result = -(int)chan->result;
if (chan->xfrd < chan->buflen && result == OK)
@ -2394,7 +2396,7 @@ static int efm32_out_asynch(FAR struct efm32_usbhost_s *priv, int chidx,
FAR struct efm32_chan_s *chan;
int ret;
/* Set up for the transfer data and callback BEFORE starting the first transfer */
/* Set up for the transfer BEFORE starting the first transfer */
chan = &priv->chan[chidx];
chan->buffer = buffer;
@ -2500,11 +2502,11 @@ static inline void efm32_gint_hcinisr(FAR struct efm32_usbhost_s *priv,
pending &= regval;
uinfo("HCINTMSK%d: %08x pending: %08x\n", chidx, regval, pending);
/* Check for a pending ACK response received/transmitted (ACK) interrupt */
/* Check for a pending ACK response received/transmitted interrupt */
if ((pending & USB_HC_INT_ACK) != 0)
{
/* Clear the pending the ACK response received/transmitted (ACK) interrupt */
/* Clear the pending the ACK response received/transmitted interrupt */
efm32_putreg(EFM32_USB_HC_INT(chidx), USB_HC_INT_ACK);
}
@ -2568,7 +2570,7 @@ static inline void efm32_gint_hcinisr(FAR struct efm32_usbhost_s *priv,
efm32_putreg(EFM32_USB_HC_INT(chidx), USB_HC_INT_XFERCOMPL);
/* Then handle the transfer completion event based on the endpoint type */
/* Then handle the transfer completion event based on the endpoint */
if (chan->eptype == EFM32_USB_EPTYPE_CTRL ||
chan->eptype == EFM32_USB_EPTYPE_BULK)
@ -2711,7 +2713,7 @@ static inline void efm32_gint_hcinisr(FAR struct efm32_usbhost_s *priv,
efm32_putreg(EFM32_USB_HC_CHAR(chidx), regval);
}
#else
/* Halt all transfers on the NAK -- the CHH interrupt is expected next */
/* Halt all transfers on the NAK -- CHH interrupt is expected next */
efm32_chan_halt(priv, chidx, CHREASON_NAK);
#endif
@ -2764,11 +2766,11 @@ static inline void efm32_gint_hcoutisr(FAR struct efm32_usbhost_s *priv,
pending &= regval;
uinfo("HCINTMSK%d: %08x pending: %08x\n", chidx, regval, pending);
/* Check for a pending ACK response received/transmitted (ACK) interrupt */
/* Check for a pending ACK response received/transmitted interrupt */
if ((pending & USB_HC_INT_ACK) != 0)
{
/* Clear the pending the ACK response received/transmitted (ACK) interrupt */
/* Clear the pending the ACK response received/transmitted interrupt */
efm32_putreg(EFM32_USB_HC_INT(chidx), USB_HC_INT_ACK);
}
@ -3074,7 +3076,7 @@ static inline void efm32_gint_rxflvlisr(FAR struct efm32_usbhost_s *priv)
chidx = (grxsts & _USB_GRXSTSP_CHEPNUM_MASK) >> _USB_GRXSTSP_CHEPNUM_SHIFT;
/* Get the host channel characteristics register (HCCHAR) for this channel */
/* Get the host channel characteristics register (HCCHAR) */
hcchar = efm32_getreg(EFM32_USB_HC_CHAR(chidx));
@ -3725,7 +3727,7 @@ static inline void efm32_hostinit_enable(void)
efm32_putreg(EFM32_USB_GINTSTS, 0xffffffff);
/* Clear any pending USB OTG Interrupts (should be done elsewhere if OTG is supported) */
/* Clear any pending USB OTG Interrupts */
efm32_putreg(EFM32_USB_GOTGINT, 0xffffffff);
@ -3976,7 +3978,7 @@ static int efm32_rh_enumerate(FAR struct efm32_usbhost_s *priv,
DEBUGASSERT(priv->smstate == SMSTATE_ATTACHED);
/* USB 2.0 spec says at least 50ms delay before port reset. We wait 100ms. */
/* USB 2.0 spec says at least 50ms delay before port reset. wait 100ms. */
nxsig_usleep(100 * 1000);
@ -4217,7 +4219,7 @@ static int efm32_epfree(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep)
DEBUGASSERT(priv);
/* We must have exclusive access to the USB host hardware and state structures */
/* We must have exclusive access to the USB host hardware and structures */
ret = efm32_takesem(&priv->exclsem);
if (ret < 0)
@ -4546,7 +4548,7 @@ static int efm32_ctrlin(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep0,
while (elapsed < EFM32_DATANAK_DELAY);
}
/* All failures exit here after all retries and timeouts have been exhausted */
/* All failures exit here after all retries and timeouts are exhausted */
efm32_givesem(&priv->exclsem);
return -ETIMEDOUT;
@ -4574,7 +4576,7 @@ static int efm32_ctrlout(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep0,
buflen = efm32_getle16(req->len);
/* We must have exclusive access to the USB host hardware and state structures */
/* We must have exclusive access to the USB host hardware and structures */
ret = efm32_takesem(&priv->exclsem);
if (ret < 0)
@ -4638,7 +4640,7 @@ static int efm32_ctrlout(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep0,
while (elapsed < EFM32_DATANAK_DELAY);
}
/* All failures exit here after all retries and timeouts have been exhausted */
/* All failures exit here after all retries and timeouts are exhausted */
efm32_givesem(&priv->exclsem);
return -ETIMEDOUT;
@ -4695,7 +4697,7 @@ static ssize_t efm32_transfer(FAR struct usbhost_driver_s *drvr,
DEBUGASSERT(priv && buffer && chidx < EFM32_MAX_TX_FIFOS && buflen > 0);
/* We must have exclusive access to the USB host hardware and state structures */
/* We must have exclusive access to the USB host hardware and structures */
ret = efm32_takesem(&priv->exclsem);
if (ret < 0)
@ -4767,7 +4769,7 @@ static int efm32_asynch(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep,
DEBUGASSERT(priv && buffer && chidx < EFM32_MAX_TX_FIFOS && buflen > 0);
/* We must have exclusive access to the USB host hardware and state structures */
/* We must have exclusive access to the USB host hardware and structures */
ret = efm32_takesem(&priv->exclsem);
if (ret < 0)

2
arch/arm/src/imxrt/imxrt_lpi2c.c
View file

@ -940,7 +940,7 @@ static void imxrt_lpi2c_tracenew(FAR struct imxrt_lpi2c_priv_s *priv,
if (trace->count != 0)
{
/* Yes.. bump up the trace index (unless we are out of trace entries) */
/* Yes.. bump up the trace index (unless out of trace entries) */
if (priv->tndx >= (CONFIG_I2C_NTRACE - 1))
{

4
arch/arm/src/imxrt/imxrt_ocotp.c
View file

@ -51,7 +51,7 @@
#include "imxrt_periphclks.h"
#include "imxrt_ocotp.h"
/*****************************************************************************
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
@ -175,7 +175,7 @@ static void imxrt_ocotp_initialize(void)
OCOTP_TIMING2_RELAX_READ(relax_read) |
OCOTP_TIMING2_RELAX_PROG(relax_prog));
}
}
}
static int imxrt_ocotp_wait_for_completion(uint32_t timeout_ms)
{

66
arch/arm/src/max326xx/max32660/max32660_wdt.c
View file

@ -104,7 +104,8 @@ struct max326_wdt_lowerhalf_s
* Private Function Prototypes
****************************************************************************/
static inline void max326_wdog_reset(FAR struct max326_wdt_lowerhalf_s *priv);
static inline void
max326_wdog_reset(FAR struct max326_wdt_lowerhalf_s *priv);
static void max326_int_enable(FAR struct max326_wdt_lowerhalf_s *priv);
static uint32_t max326_time_left(FAR struct max326_wdt_lowerhalf_s *priv);
static uint64_t max326_exp2msec(uint32_t pclk, uint8_t exp);
@ -248,24 +249,24 @@ static uint32_t max326_time_left(FAR struct max326_wdt_lowerhalf_s *priv)
* matter, the interrupt time period is the right answer in either case.
*/
ctrl = getreg32(MAX326_WDT0_CTRL);
exp = (ctrl & WDT0_CTRL_INTPERIOD_MASK) >> WDT0_CTRL_INTPERIOD_SHIFT;
ctrl = getreg32(MAX326_WDT0_CTRL);
exp = (ctrl & WDT0_CTRL_INTPERIOD_MASK) >> WDT0_CTRL_INTPERIOD_SHIFT;
timeout = max326_exp2msec(max326_pclk_frequency(), exp);
elapsed = TICK2MSEC(clock_systimer() - priv->lastping);
timeout = max326_exp2msec(max326_pclk_frequency(), exp);
elapsed = TICK2MSEC(clock_systimer() - priv->lastping);
if (elapsed > timeout)
{
timeleft = 0;
}
else
{
timeleft = timeout - elapsed;
if (timeleft > UINT32_MAX)
{
timeleft = UINT32_MAX;
}
}
if (elapsed > timeout)
{
timeleft = 0;
}
else
{
timeleft = timeout - elapsed;
if (timeleft > UINT32_MAX)
{
timeleft = UINT32_MAX;
}
}
return (uint32_t)timeleft;
}
@ -351,8 +352,8 @@ static uint8_t max326_msec2exp(uint32_t msec)
* Start the watchdog timer, resetting the time to the current timeout.
*
* Input Parameters:
* lower - A pointer the publicly visible representation of the "lower-half"
* driver state structure.
* lower - A pointer the publicly visible representation of the
* "lower-half" driver state structure.
*
* Returned Values:
* Zero on success; a negated errno value on failure.
@ -398,8 +399,8 @@ static int max326_start(FAR struct watchdog_lowerhalf_s *lower)
* Stop the watchdog timer
*
* Input Parameters:
* lower - A pointer the publicly visible representation of the "lower-half"
* driver state structure.
* lower - A pointer the publicly visible representation of the
* "lower-half" driver state structure.
*
* Returned Values:
* Zero on success; a negated errno value on failure.
@ -439,8 +440,8 @@ static int max326_stop(FAR struct watchdog_lowerhalf_s *lower)
* the watchdog timer or "petting the dog".
*
* Input Parameters:
* lower - A pointer the publicly visible representation of the "lower-half"
* driver state structure.
* lower - A pointer the publicly visible representation of the
* "lower-half" driver state structure.
*
* Returned Values:
* Zero on success; a negated errno value on failure.
@ -471,8 +472,8 @@ static int max326_keepalive(FAR struct watchdog_lowerhalf_s *lower)
* Get the current watchdog timer status
*
* Input Parameters:
* lower - A pointer the publicly visible representation of the "lower-half"
* driver state structure.
* lower - A pointer the publicly visible representation of the
* "lower-half" driver state structure.
* status - The location to return the watchdog status information.
*
* Returned Values:
@ -528,8 +529,8 @@ static int max326_getstatus(FAR struct watchdog_lowerhalf_s *lower,
* Set a new timeout value (and reset the watchdog timer)
*
* Input Parameters:
* lower - A pointer the publicly visible representation of the "lower-half"
* driver state structure.
* lower - A pointer the publicly visible representation of the
* "lower-half" driver state structure.
* timeout - The new timeout value in milliseconds.
*
* Returned Values:
@ -584,8 +585,8 @@ static int max326_settimeout(FAR struct watchdog_lowerhalf_s *lower,
* Attach the user WDT interrupt handler and enable the interrupt.
*
* Input Parameters:
* lower - A pointer the publicly visible representation of the "lower-half"
* driver state structure.
* lower - A pointer the publicly visible representation of the
* "lower-half" driver state structure.
* handler - The new WDT interrupt handler.
*
* Returned Values:
@ -638,8 +639,8 @@ static xcpt_t max326_capture(FAR struct watchdog_lowerhalf_s *lower,
* Handle IOCTL commands forwarded from the upper half driver
*
* Input Parameters:
* lower - A pointer the publicly visible representation of the "lower-half"
* driver state structure.
* lower - A pointer the publicly visible representation of the
* "lower-half" driver state structure.
* cmd - IOCTL command
* arg - Argument associated with the IOCTL command.
*
@ -690,7 +691,8 @@ int max326_wdt_initialize(FAR const char *devpath)
/* Register the watchdog driver as /dev/watchdog0 */
handle = watchdog_register(devpath, (FAR struct watchdog_lowerhalf_s *)priv);
handle = watchdog_register(devpath,
(FAR struct watchdog_lowerhalf_s *)priv);
return (handle != NULL) ? OK : -ENODEV;
}

12
arch/arm/src/nrf52/nrf52_wdt.c
View file

@ -110,12 +110,12 @@
struct nrf52_wdt_lowerhalf_s
{
FAR const struct watchdog_ops_s *ops; /* Lower half operations */
uint32_t timeout; /* The (actual) timeout */
uint32_t lastreset; /* The last reset time */
bool started; /* true: The watchdog timer has been started */
uint16_t reload; /* Timer reload value */
uint16_t mode; /* watchdog mode under sleep and halt of CPU */
FAR const struct watchdog_ops_s *ops; /* Lower half operations */
uint32_t timeout; /* The (actual) timeout */
uint32_t lastreset; /* The last reset time */
bool started; /* true: The watchdog timer has been started */
uint16_t reload; /* Timer reload value */
uint16_t mode; /* watchdog mode under sleep and halt of CPU */
};
/****************************************************************************

2
arch/arm/src/s32k1xx/s32k1xx_lpi2c.c
View file

@ -852,7 +852,7 @@ static void s32k1xx_lpi2c_tracenew(FAR struct s32k1xx_lpi2c_priv_s *priv,
if (trace->count != 0)
{
/* Yes.. bump up the trace index (unless we are out of trace entries) */
/* Yes.. bump up the trace index (unless out of trace entries) */
if (priv->tndx >= (CONFIG_I2C_NTRACE - 1))
{

66
arch/arm/src/stm32/stm32_iwdg.c
View file

@ -59,7 +59,9 @@
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Clocking *****************************************************************/
/* The minimum frequency of the IWDG clock is:
*
* Fmin = Flsi / 256
@ -112,6 +114,7 @@
/****************************************************************************
* Private Types
****************************************************************************/
/* This structure provides the private representation of the "lower-half"
* driver state structure. This structure must be cast-compatible with the
* well-known watchdog_lowerhalf_s structure.
@ -119,18 +122,19 @@
struct stm32_lowerhalf_s
{
FAR const struct watchdog_ops_s *ops; /* Lower half operations */
uint32_t lsifreq; /* The calibrated frequency of the LSI oscillator */
uint32_t timeout; /* The (actual) selected timeout */
uint32_t lastreset; /* The last reset time */
bool started; /* true: The watchdog timer has been started */
uint8_t prescaler; /* Clock prescaler value */
uint16_t reload; /* Timer reload value */
FAR const struct watchdog_ops_s *ops; /* Lower half operations */
uint32_t lsifreq; /* The calibrated frequency of the LSI oscillator */
uint32_t timeout; /* The (actual) selected timeout */
uint32_t lastreset; /* The last reset time */
bool started; /* true: The watchdog timer has been started */
uint8_t prescaler; /* Clock prescaler value */
uint16_t reload; /* Timer reload value */
};
/****************************************************************************
* Private Function Prototypes
****************************************************************************/
/* Register operations ******************************************************/
#ifdef CONFIG_STM32_IWDG_REGDEBUG
@ -156,6 +160,7 @@ static int stm32_settimeout(FAR struct watchdog_lowerhalf_s *lower,
/****************************************************************************
* Private Data
****************************************************************************/
/* "Lower half" driver methods */
static const struct watchdog_ops_s g_wdgops =
@ -196,8 +201,8 @@ static uint16_t stm32_getreg(uint32_t addr)
uint16_t val = getreg16(addr);
/* Is this the same value that we read from the same register last time? Are
* we polling the register? If so, suppress some of the output.
/* Is this the same value that we read from the same register last time?
* Are we polling the register? If so, suppress some of the output.
*/
if (addr == prevaddr && val == preval)
@ -223,7 +228,7 @@ static uint16_t stm32_getreg(uint32_t addr)
{
/* Yes.. then show how many times the value repeated */
wdinfo("[repeats %d more times]\n", count-3);
wdinfo("[repeats %d more times]\n", count - 3);
}
/* Save the new address, value, and count */
@ -312,8 +317,8 @@ static inline void stm32_setprescaler(FAR struct stm32_lowerhalf_s *priv)
* Start the watchdog timer, resetting the time to the current timeout,
*
* Input Parameters:
* lower - A pointer the publicly visible representation of the "lower-half"
* driver state structure.
* lower - A pointer the publicly visible representation of the
* "lower-half" driver state structure.
*
* Returned Value:
* Zero on success; a negated errno value on failure.
@ -332,9 +337,9 @@ static int stm32_start(FAR struct watchdog_lowerhalf_s *lower)
if (!priv->started)
{
/* REVISIT: It appears that you can only setup the prescaler and reload
* registers once. After that, the SR register's PVU and RVU bits never go
* to zero. So we defer setting up these registers until the watchdog
/* REVISIT: It appears that you can only setup the prescaler and reload
* registers once. After that, the SR register's PVU and RVU bits never
* go to 0. So we defer setting up these registers until the watchdog
* is started, then refuse any further attempts to change timeout.
*/
@ -347,8 +352,8 @@ static int stm32_start(FAR struct watchdog_lowerhalf_s *lower)
#endif
/* Enable IWDG (the LSI oscillator will be enabled by hardware). NOTE:
* If the "Hardware watchdog" feature is enabled through the device option
* bits, the watchdog is automatically enabled at power-on.
* If the "Hardware watchdog" feature is enabled through the device
* option bits, the watchdog is automatically enabled at power-on.
*/
flags = enter_critical_section();
@ -368,8 +373,8 @@ static int stm32_start(FAR struct watchdog_lowerhalf_s *lower)
* Stop the watchdog timer
*
* Input Parameters:
* lower - A pointer the publicly visible representation of the "lower-half"
* driver state structure.
* lower - A pointer the publicly visible representation of the
* "lower-half" driver state structure.
*
* Returned Value:
* Zero on success; a negated errno value on failure.
@ -393,8 +398,8 @@ static int stm32_stop(FAR struct watchdog_lowerhalf_s *lower)
* the watchdog timer or "petting the dog".
*
* Input Parameters:
* lower - A pointer the publicly visible representation of the "lower-half"
* driver state structure.
* lower - A pointer the publicly visible representation of the
* "lower-half" driver state structure.
*
* Returned Value:
* Zero on success; a negated errno value on failure.
@ -425,8 +430,8 @@ static int stm32_keepalive(FAR struct watchdog_lowerhalf_s *lower)
* Get the current watchdog timer status
*
* Input Parameters:
* lower - A pointer the publicly visible representation of the "lower-half"
* driver state structure.
* lower - A pointer the publicly visible representation of the
* "lower-half" driver state structure.
* status - The location to return the watchdog status information.
*
* Returned Value:
@ -484,8 +489,8 @@ static int stm32_getstatus(FAR struct watchdog_lowerhalf_s *lower,
* Set a new timeout value (and reset the watchdog timer)
*
* Input Parameters:
* lower - A pointer the publicly visible representation of the "lower-half"
* driver state structure.
* lower - A pointer the publicly visible representation of the
* "lower-half" driver state structure.
* timeout - The new timeout value in milliseconds.
*
* Returned Value:
@ -605,8 +610,8 @@ static int stm32_settimeout(FAR struct watchdog_lowerhalf_s *lower,
*/
#ifndef CONFIG_STM32_IWDG_ONETIMESETUP
/* If CONFIG_STM32_IWDG_DEFERREDSETUP is selected, then perform the register
* configuration only if the timer has been started.
/* If CONFIG_STM32_IWDG_DEFERREDSETUP is selected, then perform the
* register configuration only if the timer has been started.
*/
#ifdef CONFIG_STM32_IWDG_DEFERREDSETUP
@ -630,8 +635,8 @@ static int stm32_settimeout(FAR struct watchdog_lowerhalf_s *lower,
* Name: stm32_iwdginitialize
*
* Description:
* Initialize the IWDG watchdog timer. The watchdog timer is initialized and
* registers as 'devpath'. The initial state of the watchdog timer is
* Initialize the IWDG watchdog timer. The watchdog timer is initialized
* and registers as 'devpath'. The initial state of the watchdog timer is
* disabled.
*
* Input Parameters:
@ -675,7 +680,8 @@ void stm32_iwdginitialize(FAR const char *devpath, uint32_t lsifreq)
* device option bits, the watchdog is automatically enabled at power-on.
*/
stm32_settimeout((FAR struct watchdog_lowerhalf_s *)priv, CONFIG_STM32_IWDG_DEFTIMOUT);
stm32_settimeout((FAR struct watchdog_lowerhalf_s *)priv,
CONFIG_STM32_IWDG_DEFTIMOUT);
/* Register the watchdog driver as /dev/watchdog0 */

56
arch/arm/src/stm32/stm32_otgfshost.c
View file

@ -1575,7 +1575,9 @@ static void stm32_transfer_start(FAR struct stm32_usbhost_s *priv, int chidx)
if (minsize <= avail)
{
/* Yes.. Get the size of the biggest thing that we can put in the Tx FIFO now */
/* Yes.. Get the size of the biggest thing that we can put
* in the Tx FIFO now
*/
wrsize = chan->buflen;
if (wrsize > avail)
@ -1895,7 +1897,7 @@ static ssize_t stm32_in_transfer(FAR struct stm32_usbhost_s *priv, int chidx,
return (ssize_t)ret;
}
/* Set up for the transfer based on the direction and the endpoint type */
/* Set up for the transfer based on the direction and the endpoint */
ret = stm32_in_setup(priv, chidx);
if (ret < 0)
@ -2061,7 +2063,7 @@ static void stm32_in_next(FAR struct stm32_usbhost_s *priv,
int result;
int ret;
/* Is the full transfer complete? Did the last chunk transfer complete OK? */
/* Is the full transfer complete? Did the last chunk transfer OK? */
result = -(int)chan->result;
if (chan->xfrd < chan->buflen && result == OK)
@ -2124,7 +2126,7 @@ static int stm32_in_asynch(FAR struct stm32_usbhost_s *priv, int chidx,
FAR struct stm32_chan_s *chan;
int ret;
/* Set up for the transfer data and callback BEFORE starting the first transfer */
/* Set up for the transfer BEFORE starting the first transfer */
chan = &priv->chan[chidx];
chan->buffer = buffer;
@ -2267,7 +2269,7 @@ static ssize_t stm32_out_transfer(FAR struct stm32_usbhost_s *priv,
return (ssize_t)ret;
}
/* Set up for the transfer based on the direction and the endpoint type */
/* Set up for the transfer based on the direction and the endpoint */
ret = stm32_out_setup(priv, chidx);
if (ret < 0)
@ -2318,7 +2320,7 @@ static ssize_t stm32_out_transfer(FAR struct stm32_usbhost_s *priv,
}
else
{
/* Successfully transferred. Update the buffer pointer and length */
/* Successfully transferred. Update the buffer pointer/length */
buffer += xfrlen;
buflen -= xfrlen;
@ -2351,7 +2353,7 @@ static void stm32_out_next(FAR struct stm32_usbhost_s *priv,
int result;
int ret;
/* Is the full transfer complete? Did the last chunk transfer complete OK? */
/* Is the full transfer complete? Did the last chunk transfer OK? */
result = -(int)chan->result;
if (chan->xfrd < chan->buflen && result == OK)
@ -2414,7 +2416,7 @@ static int stm32_out_asynch(FAR struct stm32_usbhost_s *priv, int chidx,
FAR struct stm32_chan_s *chan;
int ret;
/* Set up for the transfer data and callback BEFORE starting the first transfer */
/* Set up for the transfer BEFORE starting the first transfer */
chan = &priv->chan[chidx];
chan->buffer = buffer;
@ -2520,11 +2522,11 @@ static inline void stm32_gint_hcinisr(FAR struct stm32_usbhost_s *priv,
pending &= regval;
uinfo("HCINTMSK%d: %08x pending: %08x\n", chidx, regval, pending);
/* Check for a pending ACK response received/transmitted (ACK) interrupt */
/* Check for a pending ACK response received/transmitted interrupt */
if ((pending & OTGFS_HCINT_ACK) != 0)
{
/* Clear the pending the ACK response received/transmitted (ACK) interrupt */
/* Clear the pending the ACK response received/transmitted interrupt */
stm32_putreg(STM32_OTGFS_HCINT(chidx), OTGFS_HCINT_ACK);
}
@ -2588,7 +2590,7 @@ static inline void stm32_gint_hcinisr(FAR struct stm32_usbhost_s *priv,
stm32_putreg(STM32_OTGFS_HCINT(chidx), OTGFS_HCINT_XFRC);
/* Then handle the transfer completion event based on the endpoint type */
/* Then handle the transfer completion event based on the endpoint */
if (chan->eptype == OTGFS_EPTYPE_CTRL ||
chan->eptype == OTGFS_EPTYPE_BULK)
@ -2724,7 +2726,7 @@ static inline void stm32_gint_hcinisr(FAR struct stm32_usbhost_s *priv,
}
#else
/* Halt all transfers on the NAK -- the CHH interrupt is expected next */
/* Halt all transfers on the NAK -- CHH interrupt is expected next */
stm32_chan_halt(priv, chidx, CHREASON_NAK);
#endif
@ -2777,11 +2779,11 @@ static inline void stm32_gint_hcoutisr(FAR struct stm32_usbhost_s *priv,
pending &= regval;
uinfo("HCINTMSK%d: %08x pending: %08x\n", chidx, regval, pending);
/* Check for a pending ACK response received/transmitted (ACK) interrupt */
/* Check for a pending ACK response received/transmitted interrupt */
if ((pending & OTGFS_HCINT_ACK) != 0)
{
/* Clear the pending the ACK response received/transmitted (ACK) interrupt */
/* Clear the pending the ACK response received/transmitted interrupt */
stm32_putreg(STM32_OTGFS_HCINT(chidx), OTGFS_HCINT_ACK);
}
@ -3103,7 +3105,7 @@ static inline void stm32_gint_rxflvlisr(FAR struct stm32_usbhost_s *priv)
chidx = (grxsts & OTGFS_GRXSTSH_CHNUM_MASK) >> OTGFS_GRXSTSH_CHNUM_SHIFT;
/* Get the host channel characteristics register (HCCHAR) for this channel */
/* Get the host channel characteristics register (HCCHAR) */
hcchar = stm32_getreg(STM32_OTGFS_HCCHAR(chidx));
@ -3755,7 +3757,7 @@ static inline void stm32_hostinit_enable(void)
stm32_putreg(STM32_OTGFS_GINTSTS, 0xffffffff);
/* Clear any pending USB OTG Interrupts (should be done elsewhere if OTG is supported) */
/* Clear any pending USB OTG Interrupts */
stm32_putreg(STM32_OTGFS_GOTGINT, 0xffffffff);
@ -4123,7 +4125,7 @@ static int stm32_ep0configure(FAR struct usbhost_driver_s *drvr,
DEBUGASSERT(drvr != NULL && ep0info != NULL && funcaddr < 128 &&
maxpacketsize <= 64);
/* We must have exclusive access to the USB host hardware and state structures */
/* We must have exclusive access to the USB host hardware and structures */
ret = stm32_takesem(&priv->exclsem);
if (ret < 0)
@ -4188,7 +4190,7 @@ static int stm32_epalloc(FAR struct usbhost_driver_s *drvr,
DEBUGASSERT(drvr != 0 && epdesc != NULL && ep != NULL);
/* We must have exclusive access to the USB host hardware and state structures */
/* We must have exclusive access to the USB host hardware and structures */
ret = stm32_takesem(&priv->exclsem);
if (ret < 0)
@ -4242,7 +4244,7 @@ static int stm32_epfree(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep)
DEBUGASSERT(priv);
/* We must have exclusive access to the USB host hardware and state structures */
/* We must have exclusive access to the USB host hardware and structures */
ret = stm32_takesem_noncancelable(&priv->exclsem);
@ -4506,7 +4508,7 @@ static int stm32_ctrlin(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep0,
buflen = stm32_getle16(req->len);
/* We must have exclusive access to the USB host hardware and state structures */
/* We must have exclusive access to the USB host hardware and structures */
ret = stm32_takesem(&priv->exclsem);
if (ret < 0)
@ -4565,7 +4567,7 @@ static int stm32_ctrlin(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep0,
while (elapsed < STM32_DATANAK_DELAY);
}
/* All failures exit here after all retries and timeouts have been exhausted */
/* All failures exit here after all retries and timeouts are exhausted */
stm32_givesem(&priv->exclsem);
return -ETIMEDOUT;
@ -4593,7 +4595,7 @@ static int stm32_ctrlout(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep0,
buflen = stm32_getle16(req->len);
/* We must have exclusive access to the USB host hardware and state structures */
/* We must have exclusive access to the USB host hardware and structures */
ret = stm32_takesem(&priv->exclsem);
if (ret < 0)
@ -4657,7 +4659,7 @@ static int stm32_ctrlout(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep0,
while (elapsed < STM32_DATANAK_DELAY);
}
/* All failures exit here after all retries and timeouts have been exhausted */
/* All failures exit here after all retries and timeouts are exhausted */
stm32_givesem(&priv->exclsem);
return -ETIMEDOUT;
@ -4715,7 +4717,7 @@ static ssize_t stm32_transfer(FAR struct usbhost_driver_s *drvr,
DEBUGASSERT(priv && buffer && chidx < STM32_MAX_TX_FIFOS && buflen > 0);
/* We must have exclusive access to the USB host hardware and state structures */
/* We must have exclusive access to the USB host hardware and structures */
ret = stm32_takesem(&priv->exclsem);
if (ret < 0)
@ -4787,7 +4789,7 @@ static int stm32_asynch(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep,
DEBUGASSERT(priv && buffer && chidx < STM32_MAX_TX_FIFOS && buflen > 0);
/* We must have exclusive access to the USB host hardware and state structures */
/* We must have exclusive access to the USB host hardware and structures */
ret = stm32_takesem(&priv->exclsem);
if (ret < 0)
@ -5190,7 +5192,9 @@ static void stm32_host_initialize(FAR struct stm32_usbhost_s *priv)
regval &= ~OTGFS_HCFG_FSLSS;
stm32_putreg(STM32_OTGFS_HCFG, regval);
/* Carve up FIFO memory for the Rx FIFO and the periodic and non-periodic Tx FIFOs */
/* Carve up FIFO memory for the Rx FIFO and the periodic
* and non-periodic Tx FIFOs
*/
/* Configure Rx FIFO size (GRXFSIZ) */

52
arch/arm/src/stm32/stm32_otghshost.c
View file

@ -1576,7 +1576,9 @@ static void stm32_transfer_start(FAR struct stm32_usbhost_s *priv, int chidx)
if (minsize <= avail)
{
/* Yes.. Get the size of the biggest thing that we can put in the Tx FIFO now */
/* Yes.. Get the size of the biggest thing that we can put
* in the Tx FIFO now
*/
wrsize = chan->buflen;
if (wrsize > avail)
@ -1896,7 +1898,7 @@ static ssize_t stm32_in_transfer(FAR struct stm32_usbhost_s *priv, int chidx,
return (ssize_t)ret;
}
/* Set up for the transfer based on the direction and the endpoint type */
/* Set up for the transfer based on the direction and the endpoint */
ret = stm32_in_setup(priv, chidx);
if (ret < 0)
@ -2062,7 +2064,7 @@ static void stm32_in_next(FAR struct stm32_usbhost_s *priv,
int result;
int ret;
/* Is the full transfer complete? Did the last chunk transfer complete OK? */
/* Is the full transfer complete? Did the last chunk transfer OK? */
result = -(int)chan->result;
if (chan->xfrd < chan->buflen && result == OK)
@ -2125,7 +2127,7 @@ static int stm32_in_asynch(FAR struct stm32_usbhost_s *priv, int chidx,
FAR struct stm32_chan_s *chan;
int ret;
/* Set up for the transfer data and callback BEFORE starting the first transfer */
/* Set up for the transfer BEFORE starting the first transfer */
chan = &priv->chan[chidx];
chan->buffer = buffer;
@ -2268,7 +2270,7 @@ static ssize_t stm32_out_transfer(FAR struct stm32_usbhost_s *priv,
return (ssize_t)ret;
}
/* Set up for the transfer based on the direction and the endpoint type */
/* Set up for the transfer based on the direction and the endpoint */
ret = stm32_out_setup(priv, chidx);
if (ret < 0)
@ -2319,7 +2321,7 @@ static ssize_t stm32_out_transfer(FAR struct stm32_usbhost_s *priv,
}
else
{
/* Successfully transferred. Update the buffer pointer and length */
/* Successfully transferred. Update the buffer pointer/length */
buffer += xfrlen;
buflen -= xfrlen;
@ -2352,7 +2354,7 @@ static void stm32_out_next(FAR struct stm32_usbhost_s *priv,
int result;
int ret;
/* Is the full transfer complete? Did the last chunk transfer complete OK? */
/* Is the full transfer complete? Did the last chunk transfer OK? */
result = -(int)chan->result;
if (chan->xfrd < chan->buflen && result == OK)
@ -2415,7 +2417,7 @@ static int stm32_out_asynch(FAR struct stm32_usbhost_s *priv, int chidx,
FAR struct stm32_chan_s *chan;
int ret;
/* Set up for the transfer data and callback BEFORE starting the first transfer */
/* Set up for the transfer BEFORE starting the first transfer */
chan = &priv->chan[chidx];
chan->buffer = buffer;
@ -2521,11 +2523,11 @@ static inline void stm32_gint_hcinisr(FAR struct stm32_usbhost_s *priv,
pending &= regval;
uinfo("HCINTMSK%d: %08x pending: %08x\n", chidx, regval, pending);
/* Check for a pending ACK response received/transmitted (ACK) interrupt */
/* Check for a pending ACK response received/transmitted interrupt */
if ((pending & OTGHS_HCINT_ACK) != 0)
{
/* Clear the pending the ACK response received/transmitted (ACK) interrupt */
/* Clear the pending the ACK response received/transmitted interrupt */
stm32_putreg(STM32_OTGHS_HCINT(chidx), OTGHS_HCINT_ACK);
}
@ -2589,7 +2591,7 @@ static inline void stm32_gint_hcinisr(FAR struct stm32_usbhost_s *priv,
stm32_putreg(STM32_OTGHS_HCINT(chidx), OTGHS_HCINT_XFRC);
/* Then handle the transfer completion event based on the endpoint type */
/* Then handle the transfer completion event based on the endpoint */
if (chan->eptype == OTGHS_EPTYPE_CTRL ||
chan->eptype == OTGHS_EPTYPE_BULK)
@ -2725,7 +2727,7 @@ static inline void stm32_gint_hcinisr(FAR struct stm32_usbhost_s *priv,
}
#else
/* Halt all transfers on the NAK -- the CHH interrupt is expected next */
/* Halt all transfers on the NAK -- CHH interrupt is expected next */
stm32_chan_halt(priv, chidx, CHREASON_NAK);
#endif
@ -2778,11 +2780,11 @@ static inline void stm32_gint_hcoutisr(FAR struct stm32_usbhost_s *priv,
pending &= regval;
uinfo("HCINTMSK%d: %08x pending: %08x\n", chidx, regval, pending);
/* Check for a pending ACK response received/transmitted (ACK) interrupt */
/* Check for a pending ACK response received/transmitted interrupt */
if ((pending & OTGHS_HCINT_ACK) != 0)
{
/* Clear the pending the ACK response received/transmitted (ACK) interrupt */
/* Clear the pending the ACK response received/transmitted interrupt */
stm32_putreg(STM32_OTGHS_HCINT(chidx), OTGHS_HCINT_ACK);
}
@ -3104,7 +3106,7 @@ static inline void stm32_gint_rxflvlisr(FAR struct stm32_usbhost_s *priv)
chidx = (grxsts & OTGHS_GRXSTSH_CHNUM_MASK) >> OTGHS_GRXSTSH_CHNUM_SHIFT;
/* Get the host channel characteristics register (HCCHAR) for this channel */
/* Get the host channel characteristics register (HCCHAR) */
hcchar = stm32_getreg(STM32_OTGHS_HCCHAR(chidx));
@ -3755,7 +3757,7 @@ static inline void stm32_hostinit_enable(void)
stm32_putreg(STM32_OTGHS_GINTSTS, 0xffffffff);
/* Clear any pending USB OTG Interrupts (should be done elsewhere if OTG is supported) */
/* Clear any pending USB OTG Interrupts */
stm32_putreg(STM32_OTGHS_GOTGINT, 0xffffffff);
@ -4123,7 +4125,7 @@ static int stm32_ep0configure(FAR struct usbhost_driver_s *drvr,
DEBUGASSERT(drvr != NULL && ep0info != NULL && funcaddr < 128 &&
maxpacketsize <= 64);
/* We must have exclusive access to the USB host hardware and state structures */
/* We must have exclusive access to the USB host hardware and structures */
ret = stm32_takesem(&priv->exclsem);
if (ret < 0)
@ -4188,7 +4190,7 @@ static int stm32_epalloc(FAR struct usbhost_driver_s *drvr,
DEBUGASSERT(drvr != 0 && epdesc != NULL && ep != NULL);
/* We must have exclusive access to the USB host hardware and state structures */
/* We must have exclusive access to the USB host hardware and structures */
ret = stm32_takesem(&priv->exclsem);
if (ret < 0)
@ -4242,7 +4244,7 @@ static int stm32_epfree(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep)
DEBUGASSERT(priv);
/* We must have exclusive access to the USB host hardware and state structures */
/* We must have exclusive access to the USB host hardware and structures */
ret = stm32_takesem_noncancelable(&priv->exclsem);
@ -4506,7 +4508,7 @@ static int stm32_ctrlin(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep0,
buflen = stm32_getle16(req->len);
/* We must have exclusive access to the USB host hardware and state structures */
/* We must have exclusive access to the USB host hardware and structures */
ret = stm32_takesem(&priv->exclsem);
if (ret < 0)
@ -4565,7 +4567,7 @@ static int stm32_ctrlin(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep0,
while (elapsed < STM32_DATANAK_DELAY);
}
/* All failures exit here after all retries and timeouts have been exhausted */
/* All failures exit here after all retries and timeouts are exhausted */
stm32_givesem(&priv->exclsem);
return -ETIMEDOUT;
@ -4593,7 +4595,7 @@ static int stm32_ctrlout(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep0,
buflen = stm32_getle16(req->len);
/* We must have exclusive access to the USB host hardware and state structures */
/* We must have exclusive access to the USB host hardware and structures */
ret = stm32_takesem(&priv->exclsem);
if (ret < 0)
@ -4657,7 +4659,7 @@ static int stm32_ctrlout(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep0,
while (elapsed < STM32_DATANAK_DELAY);
}
/* All failures exit here after all retries and timeouts have been exhausted */
/* All failures exit here after all retries and timeouts are exhausted */
stm32_givesem(&priv->exclsem);
return -ETIMEDOUT;
@ -4715,7 +4717,7 @@ static ssize_t stm32_transfer(FAR struct usbhost_driver_s *drvr,
DEBUGASSERT(priv && buffer && chidx < STM32_MAX_TX_FIFOS && buflen > 0);
/* We must have exclusive access to the USB host hardware and state structures */
/* We must have exclusive access to the USB host hardware and structures */
ret = stm32_takesem(&priv->exclsem);
if (ret < 0)
@ -4787,7 +4789,7 @@ static int stm32_asynch(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep,
DEBUGASSERT(priv && buffer && chidx < STM32_MAX_TX_FIFOS && buflen > 0);
/* We must have exclusive access to the USB host hardware and state structures */
/* We must have exclusive access to the USB host hardware and structures */
ret = stm32_takesem(&priv->exclsem);
if (ret < 0)

52
arch/arm/src/stm32f7/stm32_otghost.c
View file

@ -1578,7 +1578,9 @@ static void stm32_transfer_start(FAR struct stm32_usbhost_s *priv, int chidx)
if (minsize <= avail)
{
/* Yes.. Get the size of the biggest thing that we can put in the Tx FIFO now */
/* Yes.. Get the size of the biggest thing that we can put
* in the Tx FIFO now
*/
wrsize = chan->buflen;
if (wrsize > avail)
@ -1897,7 +1899,7 @@ static ssize_t stm32_in_transfer(FAR struct stm32_usbhost_s *priv, int chidx,
return (ssize_t)ret;
}
/* Set up for the transfer based on the direction and the endpoint type */
/* Set up for the transfer based on the direction and the endpoint */
ret = stm32_in_setup(priv, chidx);
if (ret < 0)
@ -2063,7 +2065,7 @@ static void stm32_in_next(FAR struct stm32_usbhost_s *priv,
int result;
int ret;
/* Is the full transfer complete? Did the last chunk transfer complete OK? */
/* Is the full transfer complete? Did the last chunk transfer OK? */
result = -(int)chan->result;
if (chan->xfrd < chan->buflen && result == OK)
@ -2126,7 +2128,7 @@ static int stm32_in_asynch(FAR struct stm32_usbhost_s *priv, int chidx,
FAR struct stm32_chan_s *chan;
int ret;
/* Set up for the transfer data and callback BEFORE starting the first transfer */
/* Set up for the transfer BEFORE starting the first transfer */
chan = &priv->chan[chidx];
chan->buffer = buffer;
@ -2269,7 +2271,7 @@ static ssize_t stm32_out_transfer(FAR struct stm32_usbhost_s *priv,
return (ssize_t)ret;
}
/* Set up for the transfer based on the direction and the endpoint type */
/* Set up for the transfer based on the direction and the endpoint */
ret = stm32_out_setup(priv, chidx);
if (ret < 0)
@ -2320,7 +2322,7 @@ static ssize_t stm32_out_transfer(FAR struct stm32_usbhost_s *priv,
}
else
{
/* Successfully transferred. Update the buffer pointer and length */
/* Successfully transferred. Update the buffer pointer/length */
buffer += xfrlen;
buflen -= xfrlen;
@ -2353,7 +2355,7 @@ static void stm32_out_next(FAR struct stm32_usbhost_s *priv,
int result;
int ret;
/* Is the full transfer complete? Did the last chunk transfer complete OK? */
/* Is the full transfer complete? Did the last chunk transfer OK? */
result = -(int)chan->result;
if (chan->xfrd < chan->buflen && result == OK)
@ -2416,7 +2418,7 @@ static int stm32_out_asynch(FAR struct stm32_usbhost_s *priv, int chidx,
FAR struct stm32_chan_s *chan;
int ret;
/* Set up for the transfer data and callback BEFORE starting the first transfer */
/* Set up for the transfer BEFORE starting the first transfer */
chan = &priv->chan[chidx];
chan->buffer = buffer;
@ -2522,11 +2524,11 @@ static inline void stm32_gint_hcinisr(FAR struct stm32_usbhost_s *priv,
pending &= regval;
uinfo("HCINTMSK%d: %08x pending: %08x\n", chidx, regval, pending);
/* Check for a pending ACK response received/transmitted (ACK) interrupt */
/* Check for a pending ACK response received/transmitted interrupt */
if ((pending & OTG_HCINT_ACK) != 0)
{
/* Clear the pending the ACK response received/transmitted (ACK) interrupt */
/* Clear the pending the ACK response received/transmitted interrupt */
stm32_putreg(STM32_OTG_HCINT(chidx), OTG_HCINT_ACK);
}
@ -2588,7 +2590,7 @@ static inline void stm32_gint_hcinisr(FAR struct stm32_usbhost_s *priv,
stm32_putreg(STM32_OTG_HCINT(chidx), OTG_HCINT_XFRC);
/* Then handle the transfer completion event based on the endpoint type */
/* Then handle the transfer completion event based on the endpoint */
if (chan->eptype == OTG_EPTYPE_CTRL || chan->eptype == OTG_EPTYPE_BULK)
{
@ -2723,7 +2725,7 @@ static inline void stm32_gint_hcinisr(FAR struct stm32_usbhost_s *priv,
}
#else
/* Halt all transfers on the NAK -- the CHH interrupt is expected next */
/* Halt all transfers on the NAK -- CHH interrupt is expected next */
stm32_chan_halt(priv, chidx, CHREASON_NAK);
#endif
@ -2776,11 +2778,11 @@ static inline void stm32_gint_hcoutisr(FAR struct stm32_usbhost_s *priv,
pending &= regval;
uinfo("HCINTMSK%d: %08x pending: %08x\n", chidx, regval, pending);
/* Check for a pending ACK response received/transmitted (ACK) interrupt */
/* Check for a pending ACK response received/transmitted interrupt */
if ((pending & OTG_HCINT_ACK) != 0)
{
/* Clear the pending the ACK response received/transmitted (ACK) interrupt */
/* Clear the pending the ACK response received/transmitted interrupt */
stm32_putreg(STM32_OTG_HCINT(chidx), OTG_HCINT_ACK);
}
@ -3100,7 +3102,7 @@ static inline void stm32_gint_rxflvlisr(FAR struct stm32_usbhost_s *priv)
chidx = (grxsts & OTG_GRXSTSH_CHNUM_MASK) >> OTG_GRXSTSH_CHNUM_SHIFT;
/* Get the host channel characteristics register (HCCHAR) for this channel */
/* Get the host channel characteristics register (HCCHAR) */
hcchar = stm32_getreg(STM32_OTG_HCCHAR(chidx));
@ -3749,7 +3751,7 @@ static inline void stm32_hostinit_enable(void)
stm32_putreg(STM32_OTG_GINTSTS, 0xffffffff);
/* Clear any pending USB OTG Interrupts (should be done elsewhere if OTG is supported) */
/* Clear any pending USB OTG Interrupts */
stm32_putreg(STM32_OTG_GOTGINT, 0xffffffff);
@ -4113,7 +4115,7 @@ static int stm32_ep0configure(FAR struct usbhost_driver_s *drvr,
DEBUGASSERT(drvr != NULL && ep0info != NULL && funcaddr < 128 &&
maxpacketsize <= 64);
/* We must have exclusive access to the USB host hardware and state structures */
/* We must have exclusive access to the USB host hardware and structures */
ret = stm32_takesem(&priv->exclsem);
if (ret < 0)
@ -4178,7 +4180,7 @@ static int stm32_epalloc(FAR struct usbhost_driver_s *drvr,
DEBUGASSERT(drvr != 0 && epdesc != NULL && ep != NULL);
/* We must have exclusive access to the USB host hardware and state structures */
/* We must have exclusive access to the USB host hardware and structures */
ret = stm32_takesem(&priv->exclsem);
if (ret < 0)
@ -4232,7 +4234,7 @@ static int stm32_epfree(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep)
DEBUGASSERT(priv);
/* We must have exclusive access to the USB host hardware and state structures */
/* We must have exclusive access to the USB host hardware and structures */
ret = stm32_takesem_noncancelable(&priv->exclsem);
@ -4496,7 +4498,7 @@ static int stm32_ctrlin(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep0,
buflen = stm32_getle16(req->len);
/* We must have exclusive access to the USB host hardware and state structures */
/* We must have exclusive access to the USB host hardware and structures */
ret = stm32_takesem(&priv->exclsem);
if (ret < 0)
@ -4555,7 +4557,7 @@ static int stm32_ctrlin(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep0,
while (elapsed < STM32_DATANAK_DELAY);
}
/* All failures exit here after all retries and timeouts have been exhausted */
/* All failures exit here after all retries and timeouts are exhausted */
stm32_givesem(&priv->exclsem);
return -ETIMEDOUT;
@ -4583,7 +4585,7 @@ static int stm32_ctrlout(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep0,
buflen = stm32_getle16(req->len);
/* We must have exclusive access to the USB host hardware and state structures */
/* We must have exclusive access to the USB host hardware and structures */
ret = stm32_takesem(&priv->exclsem);
if (ret < 0)
@ -4647,7 +4649,7 @@ static int stm32_ctrlout(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep0,
while (elapsed < STM32_DATANAK_DELAY);
}
/* All failures exit here after all retries and timeouts have been exhausted */
/* All failures exit here after all retries and timeouts are exhausted */
stm32_givesem(&priv->exclsem);
return -ETIMEDOUT;
@ -4704,7 +4706,7 @@ static ssize_t stm32_transfer(FAR struct usbhost_driver_s *drvr,
DEBUGASSERT(priv && buffer && chidx < STM32_MAX_TX_FIFOS && buflen > 0);
/* We must have exclusive access to the USB host hardware and state structures */
/* We must have exclusive access to the USB host hardware and structures */
ret = stm32_takesem(&priv->exclsem);
if (ret < 0)
@ -4776,7 +4778,7 @@ static int stm32_asynch(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep,
DEBUGASSERT(priv && buffer && chidx < STM32_MAX_TX_FIFOS && buflen > 0);
/* We must have exclusive access to the USB host hardware and state structures */
/* We must have exclusive access to the USB host hardware and structures */
ret = stm32_takesem(&priv->exclsem);
if (ret < 0)

14
arch/arm/src/stm32h7/stm32_iwdg.c
View file

@ -121,13 +121,13 @@
struct stm32_lowerhalf_s
{
FAR const struct watchdog_ops_s *ops; /* Lower half operations */
uint32_t lsifreq; /* The calibrated frequency of the LSI oscillator */
uint32_t timeout; /* The (actual) selected timeout */
uint32_t lastreset; /* The last reset time */
bool started; /* true: The watchdog timer has been started */
uint8_t prescaler; /* Clock prescaler value */
uint16_t reload; /* Timer reload value */
FAR const struct watchdog_ops_s *ops; /* Lower half operations */
uint32_t lsifreq; /* The calibrated frequency of the LSI oscillator */
uint32_t timeout; /* The (actual) selected timeout */
uint32_t lastreset; /* The last reset time */
bool started; /* true: The watchdog timer has been started */
uint8_t prescaler; /* Clock prescaler value */
uint16_t reload; /* Timer reload value */
};
/****************************************************************************

50
arch/arm/src/stm32h7/stm32_otghost.c
View file

@ -1583,7 +1583,9 @@ static void stm32_transfer_start(FAR struct stm32_usbhost_s *priv, int chidx)
if (minsize <= avail)
{
/* Yes.. Get the size of the biggest thing that we can put in the Tx FIFO now */
/* Yes.. Get the size of the biggest thing that we can put
* in the Tx FIFO now
*/
wrsize = chan->buflen;
if (wrsize > avail)
@ -1902,7 +1904,7 @@ static ssize_t stm32_in_transfer(FAR struct stm32_usbhost_s *priv, int chidx,
return (ssize_t)ret;
}
/* Set up for the transfer based on the direction and the endpoint type */
/* Set up for the transfer based on the direction and the endpoint */
ret = stm32_in_setup(priv, chidx);
if (ret < 0)
@ -2068,7 +2070,7 @@ static void stm32_in_next(FAR struct stm32_usbhost_s *priv,
int result;
int ret;
/* Is the full transfer complete? Did the last chunk transfer complete OK? */
/* Is the full transfer complete? Did the last chunk transfer OK? */
result = -(int)chan->result;
if (chan->xfrd < chan->buflen && result == OK)
@ -2131,7 +2133,7 @@ static int stm32_in_asynch(FAR struct stm32_usbhost_s *priv, int chidx,
FAR struct stm32_chan_s *chan;
int ret;
/* Set up for the transfer data and callback BEFORE starting the first transfer */
/* Set up for the transfer BEFORE starting the first transfer */
chan = &priv->chan[chidx];
chan->buffer = buffer;
@ -2274,7 +2276,7 @@ static ssize_t stm32_out_transfer(FAR struct stm32_usbhost_s *priv,
return (ssize_t)ret;
}
/* Set up for the transfer based on the direction and the endpoint type */
/* Set up for the transfer based on the direction and the endpoint */
ret = stm32_out_setup(priv, chidx);
if (ret < 0)
@ -2325,7 +2327,7 @@ static ssize_t stm32_out_transfer(FAR struct stm32_usbhost_s *priv,
}
else
{
/* Successfully transferred. Update the buffer pointer and length */
/* Successfully transferred. Update the buffer pointe/length */
buffer += xfrlen;
buflen -= xfrlen;
@ -2358,7 +2360,7 @@ static void stm32_out_next(FAR struct stm32_usbhost_s *priv,
int result;
int ret;
/* Is the full transfer complete? Did the last chunk transfer complete OK? */
/* Is the full transfer complete? Did the last chunk transfer OK? */
result = -(int)chan->result;
if (chan->xfrd < chan->buflen && result == OK)
@ -2421,7 +2423,7 @@ static int stm32_out_asynch(FAR struct stm32_usbhost_s *priv, int chidx,
FAR struct stm32_chan_s *chan;
int ret;
/* Set up for the transfer data and callback BEFORE starting the first transfer */
/* Set up for the transfer BEFORE starting the first transfer */
chan = &priv->chan[chidx];
chan->buffer = buffer;
@ -2527,11 +2529,11 @@ static inline void stm32_gint_hcinisr(FAR struct stm32_usbhost_s *priv,
pending &= regval;
uinfo("HCINTMSK%d: %08x pending: %08x\n", chidx, regval, pending);
/* Check for a pending ACK response received/transmitted (ACK) interrupt */
/* Check for a pending ACK response received/transmitted interrupt */
if ((pending & OTG_HCINT_ACK) != 0)
{
/* Clear the pending the ACK response received/transmitted (ACK) interrupt */
/* Clear the pending the ACK response received/transmitted interrupt */
stm32_putreg(STM32_OTG_HCINT(chidx), OTG_HCINT_ACK);
}
@ -2593,7 +2595,7 @@ static inline void stm32_gint_hcinisr(FAR struct stm32_usbhost_s *priv,
stm32_putreg(STM32_OTG_HCINT(chidx), OTG_HCINT_XFRC);
/* Then handle the transfer completion event based on the endpoint type */
/* Then handle the transfer completion event based on the endpoint */
if (chan->eptype == OTG_EPTYPE_CTRL || chan->eptype == OTG_EPTYPE_BULK)
{
@ -2727,7 +2729,7 @@ static inline void stm32_gint_hcinisr(FAR struct stm32_usbhost_s *priv,
}
#else
/* Halt all transfers on the NAK -- the CHH interrupt is expected next */
/* Halt all transfers on the NAK -- CHH interrupt is expected next */
stm32_chan_halt(priv, chidx, CHREASON_NAK);
#endif
@ -2780,11 +2782,11 @@ static inline void stm32_gint_hcoutisr(FAR struct stm32_usbhost_s *priv,
pending &= regval;
uinfo("HCINTMSK%d: %08x pending: %08x\n", chidx, regval, pending);
/* Check for a pending ACK response received/transmitted (ACK) interrupt */
/* Check for a pending ACK response received/transmitted interrupt */
if ((pending & OTG_HCINT_ACK) != 0)
{
/* Clear the pending the ACK response received/transmitted (ACK) interrupt */
/* Clear the pending the ACK response received/transmitted interrupt */
stm32_putreg(STM32_OTG_HCINT(chidx), OTG_HCINT_ACK);
}
@ -3104,7 +3106,7 @@ static inline void stm32_gint_rxflvlisr(FAR struct stm32_usbhost_s *priv)
chidx = (grxsts & OTG_GRXSTSH_CHNUM_MASK) >> OTG_GRXSTSH_CHNUM_SHIFT;
/* Get the host channel characteristics register (HCCHAR) for this channel */
/* Get the host channel characteristics register (HCCHAR) */
hcchar = stm32_getreg(STM32_OTG_HCCHAR(chidx));
@ -3753,7 +3755,7 @@ static inline void stm32_hostinit_enable(void)
stm32_putreg(STM32_OTG_GINTSTS, 0xffffffff);
/* Clear any pending USB OTG Interrupts (should be done elsewhere if OTG is supported) */
/* Clear any pending USB OTG Interrupts */
stm32_putreg(STM32_OTG_GOTGINT, 0xffffffff);
@ -4118,7 +4120,7 @@ static int stm32_ep0configure(FAR struct usbhost_driver_s *drvr,
DEBUGASSERT(drvr != NULL && ep0info != NULL && funcaddr < 128 &&
maxpacketsize <= 64);
/* We must have exclusive access to the USB host hardware and state structures */
/* We must have exclusive access to the USB host hardware and structures */
ret = stm32_takesem(&priv->exclsem);
if (ret < 0)
@ -4238,7 +4240,7 @@ static int stm32_epfree(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep)
DEBUGASSERT(priv);
/* We must have exclusive access to the USB host hardware and state structures */
/* We must have exclusive access to the USB host hardware and structures */
ret = stm32_takesem_noncancelable(&priv->exclsem);
@ -4502,7 +4504,7 @@ static int stm32_ctrlin(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep0,
buflen = stm32_getle16(req->len);
/* We must have exclusive access to the USB host hardware and state structures */
/* We must have exclusive access to the USB host hardware and structures */
ret = stm32_takesem(&priv->exclsem);
if (ret < 0)
@ -4561,7 +4563,7 @@ static int stm32_ctrlin(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep0,
while (elapsed < STM32_DATANAK_DELAY);
}
/* All failures exit here after all retries and timeouts have been exhausted */
/* All failures exit here after all retries and timeouts are exhausted */
stm32_givesem(&priv->exclsem);
return -ETIMEDOUT;
@ -4589,7 +4591,7 @@ static int stm32_ctrlout(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep0,
buflen = stm32_getle16(req->len);
/* We must have exclusive access to the USB host hardware and state structures */
/* We must have exclusive access to the USB host hardware and structures */
ret = stm32_takesem(&priv->exclsem);
if (ret < 0)
@ -4653,7 +4655,7 @@ static int stm32_ctrlout(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep0,
while (elapsed < STM32_DATANAK_DELAY);
}
/* All failures exit here after all retries and timeouts have been exhausted */
/* All failures exit here after all retries and timeouts are exhausted */
stm32_givesem(&priv->exclsem);
return -ETIMEDOUT;
@ -4711,7 +4713,7 @@ static ssize_t stm32_transfer(FAR struct usbhost_driver_s *drvr,
DEBUGASSERT(priv && buffer && chidx < STM32_MAX_TX_FIFOS && buflen > 0);
/* We must have exclusive access to the USB host hardware and state structures */
/* We must have exclusive access to the USB host hardware and structures */
ret = stm32_takesem(&priv->exclsem);
if (ret < 0)
@ -4783,7 +4785,7 @@ static int stm32_asynch(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep,
DEBUGASSERT(priv && buffer && chidx < STM32_MAX_TX_FIFOS && buflen > 0);
/* We must have exclusive access to the USB host hardware and state structures */
/* We must have exclusive access to the USB host hardware and structures */
ret = stm32_takesem(&priv->exclsem);
if (ret < 0)

79
arch/arm/src/stm32l4/stm32l4_iwdg.c
View file

@ -102,13 +102,13 @@
struct stm32l4_lowerhalf_s
{
FAR const struct watchdog_ops_s *ops; /* Lower half operations */
uint32_t lsifreq; /* The calibrated frequency of the LSI oscillator */
uint32_t timeout; /* The (actual) selected timeout */
uint32_t lastreset; /* The last reset time */
bool started; /* true: The watchdog timer has been started */
uint8_t prescaler; /* Clock prescaler value */
uint16_t reload; /* Timer reload value */
FAR const struct watchdog_ops_s *ops; /* Lower half operations */
uint32_t lsifreq; /* The calibrated frequency of the LSI oscillator */
uint32_t timeout; /* The (actual) selected timeout */
uint32_t lastreset; /* The last reset time */
bool started; /* true: The watchdog timer has been started */
uint8_t prescaler; /* Clock prescaler value */
uint16_t reload; /* Timer reload value */
};
/****************************************************************************
@ -125,7 +125,8 @@ static void stm32l4_putreg(uint16_t val, uint32_t addr);
# define stm32l4_putreg(val,addr) putreg16(val,addr)
#endif
static inline void stm32l4_setprescaler(FAR struct stm32l4_lowerhalf_s *priv);
static inline void
stm32l4_setprescaler(FAR struct stm32l4_lowerhalf_s *priv);
/* "Lower half" driver methods **********************************************/
@ -181,8 +182,8 @@ static uint16_t stm32l4_getreg(uint32_t addr)
uint16_t val = getreg16(addr);
/* Is this the same value that we read from the same register last time? Are
* we polling the register? If so, suppress some of the output.
/* Is this the same value that we read from the same register last time?
* Are we polling the register? If so, suppress some of the output.
*/
if (addr == prevaddr && val == preval)
@ -273,11 +274,11 @@ static inline void stm32l4_setprescaler(FAR struct stm32l4_lowerhalf_s *priv)
* yet be cleared.
*/
while ((stm32l4_getreg(STM32L4_IWDG_SR) & (IWDG_SR_PVU | IWDG_SR_RVU)) != 0);
while (stm32l4_getreg(STM32L4_IWDG_SR) & (IWDG_SR_PVU | IWDG_SR_RVU));
/* Set the prescaler */
stm32l4_putreg((uint16_t)priv->prescaler << IWDG_PR_SHIFT, STM32L4_IWDG_PR);
stm32l4_putreg(priv->prescaler << IWDG_PR_SHIFT, STM32L4_IWDG_PR);
/* Set the reload value */
@ -301,7 +302,7 @@ static inline void stm32l4_setprescaler(FAR struct stm32l4_lowerhalf_s *priv)
if (priv->started)
{
while ((stm32l4_getreg(STM32L4_IWDG_SR) & (IWDG_SR_PVU | IWDG_SR_RVU)) != 0);
while (stm32l4_getreg(STM32L4_IWDG_SR) & (IWDG_SR_PVU | IWDG_SR_RVU));
}
leave_critical_section(flags);
@ -314,8 +315,8 @@ static inline void stm32l4_setprescaler(FAR struct stm32l4_lowerhalf_s *priv)
* Start the watchdog timer, resetting the time to the current timeout,
*
* Input Parameters:
* lower - A pointer the publicly visible representation of the "lower-half"
* driver state structure.
* lower - A pointer the publicly visible representation of the
* "lower-half" driver state structure.
*
* Returned Value:
* Zero on success; a negated errno value on failure.
@ -324,7 +325,8 @@ static inline void stm32l4_setprescaler(FAR struct stm32l4_lowerhalf_s *priv)
static int stm32l4_start(FAR struct watchdog_lowerhalf_s *lower)
{
FAR struct stm32l4_lowerhalf_s *priv = (FAR struct stm32l4_lowerhalf_s *)lower;
FAR struct stm32l4_lowerhalf_s *priv =
(FAR struct stm32l4_lowerhalf_s *)lower;
irqstate_t flags;
wdinfo("Entry: started=%d\n");
@ -341,8 +343,8 @@ static int stm32l4_start(FAR struct watchdog_lowerhalf_s *lower)
stm32l4_setprescaler(priv);
/* Enable IWDG (the LSI oscillator will be enabled by hardware). NOTE:
* If the "Hardware watchdog" feature is enabled through the device option
* bits, the watchdog is automatically enabled at power-on.
* If the "Hardware watchdog" feature is enabled through the device
* option bits, the watchdog is automatically enabled at power-on.
*/
flags = enter_critical_section();
@ -362,8 +364,8 @@ static int stm32l4_start(FAR struct watchdog_lowerhalf_s *lower)
* Stop the watchdog timer
*
* Input Parameters:
* lower - A pointer the publicly visible representation of the "lower-half"
* driver state structure.
* lower - A pointer the publicly visible representation of the
* "lower-half" driver state structure.
*
* Returned Value:
* Zero on success; a negated errno value on failure.
@ -387,8 +389,8 @@ static int stm32l4_stop(FAR struct watchdog_lowerhalf_s *lower)
* the watchdog timer or "petting the dog".
*
* Input Parameters:
* lower - A pointer the publicly visible representation of the "lower-half"
* driver state structure.
* lower - A pointer the publicly visible representation of the
* "lower-half" driver state structure.
*
* Returned Value:
* Zero on success; a negated errno value on failure.
@ -397,7 +399,8 @@ static int stm32l4_stop(FAR struct watchdog_lowerhalf_s *lower)
static int stm32l4_keepalive(FAR struct watchdog_lowerhalf_s *lower)
{
FAR struct stm32l4_lowerhalf_s *priv = (FAR struct stm32l4_lowerhalf_s *)lower;
FAR struct stm32l4_lowerhalf_s *priv =
(FAR struct stm32l4_lowerhalf_s *)lower;
irqstate_t flags;
wdinfo("Entry\n");
@ -419,8 +422,8 @@ static int stm32l4_keepalive(FAR struct watchdog_lowerhalf_s *lower)
* Get the current watchdog timer status
*
* Input Parameters:
* lower - A pointer the publicly visible representation of the "lower-half"
* driver state structure.
* lower - A pointer the publicly visible representation of the
* "lower-half" driver state structure.
* status - The location to return the watchdog status information.
*
* Returned Value:
@ -431,7 +434,8 @@ static int stm32l4_keepalive(FAR struct watchdog_lowerhalf_s *lower)
static int stm32l4_getstatus(FAR struct watchdog_lowerhalf_s *lower,
FAR struct watchdog_status_s *status)
{
FAR struct stm32l4_lowerhalf_s *priv = (FAR struct stm32l4_lowerhalf_s *)lower;
FAR struct stm32l4_lowerhalf_s *priv =
(FAR struct stm32l4_lowerhalf_s *)lower;
uint32_t ticks;
uint32_t elapsed;
@ -478,8 +482,8 @@ static int stm32l4_getstatus(FAR struct watchdog_lowerhalf_s *lower,
* Set a new timeout value (and reset the watchdog timer)
*
* Input Parameters:
* lower - A pointer the publicly visible representation of the "lower-half"
* driver state structure.
* lower - A pointer the publicly visible representation of the
* "lower-half" driver state structure.
* timeout - The new timeout value in milliseconds.
*
* Returned Value:
@ -490,7 +494,8 @@ static int stm32l4_getstatus(FAR struct watchdog_lowerhalf_s *lower,
static int stm32l4_settimeout(FAR struct watchdog_lowerhalf_s *lower,
uint32_t timeout)
{
FAR struct stm32l4_lowerhalf_s *priv = (FAR struct stm32l4_lowerhalf_s *)lower;
FAR struct stm32l4_lowerhalf_s *priv =
(FAR struct stm32l4_lowerhalf_s *)lower;
uint32_t fiwdg;
uint64_t reload;
int prescaler;
@ -598,8 +603,8 @@ static int stm32l4_settimeout(FAR struct watchdog_lowerhalf_s *lower,
* Name: stm32l4_iwdginitialize
*
* Description:
* Initialize the IWDG watchdog timer. The watchdog timer is initialized and
* registers as 'devpath'. The initial state of the watchdog timer is
* Initialize the IWDG watchdog timer. The watchdog timer is initialized
* and registers as 'devpath'. The initial state of the watchdog timer is
* disabled.
*
* Input Parameters:
@ -658,13 +663,13 @@ void stm32l4_iwdginitialize(FAR const char *devpath, uint32_t lsifreq)
#if defined(CONFIG_STM32L4_JTAG_FULL_ENABLE) || \
defined(CONFIG_STM32L4_JTAG_NOJNTRST_ENABLE) || \
defined(CONFIG_STM32L4_JTAG_SW_ENABLE)
{
uint32_t cr;
{
uint32_t cr;
cr = getreg32(STM32_DBGMCU_APB1_FZ);
cr |= DBGMCU_APB1_IWDGSTOP;
putreg32(cr, STM32_DBGMCU_APB1_FZ);
}
cr = getreg32(STM32_DBGMCU_APB1_FZ);
cr |= DBGMCU_APB1_IWDGSTOP;
putreg32(cr, STM32_DBGMCU_APB1_FZ);
}
#endif
}

52
arch/arm/src/stm32l4/stm32l4_otgfshost.c
View file

@ -1595,7 +1595,9 @@ static void stm32l4_transfer_start(FAR struct stm32l4_usbhost_s *priv,
if (minsize <= avail)
{
/* Yes.. Get the size of the biggest thing that we can put in the Tx FIFO now */
/* Yes.. Get the size of the biggest thing that we can put in
* the Tx FIFO now
*/
wrsize = chan->buflen;
if (wrsize > avail)
@ -1916,7 +1918,7 @@ static ssize_t stm32l4_in_transfer(FAR struct stm32l4_usbhost_s *priv,
return (ssize_t)ret;
}
/* Set up for the transfer based on the direction and the endpoint type */
/* Set up for the transfer based on the direction and the endpoint */
ret = stm32l4_in_setup(priv, chidx);
if (ret < 0)
@ -2082,7 +2084,7 @@ static void stm32l4_in_next(FAR struct stm32l4_usbhost_s *priv,
int result;
int ret;
/* Is the full transfer complete? Did the last chunk transfer complete OK? */
/* Is the full transfer complete? Did the last chunk transfer OK? */
result = -(int)chan->result;
if (chan->xfrd < chan->buflen && result == OK)
@ -2145,7 +2147,7 @@ static int stm32l4_in_asynch(FAR struct stm32l4_usbhost_s *priv, int chidx,
FAR struct stm32l4_chan_s *chan;
int ret;
/* Set up for the transfer data and callback BEFORE starting the first transfer */
/* Set up for the transfer BEFORE starting the first transfer */
chan = &priv->chan[chidx];
chan->buffer = buffer;
@ -2288,7 +2290,7 @@ static ssize_t stm32l4_out_transfer(FAR struct stm32l4_usbhost_s *priv,
return (ssize_t)ret;
}
/* Set up for the transfer based on the direction and the endpoint type */
/* Set up for the transfer based on the direction and the endpoint */
ret = stm32l4_out_setup(priv, chidx);
if (ret < 0)
@ -2340,7 +2342,7 @@ static ssize_t stm32l4_out_transfer(FAR struct stm32l4_usbhost_s *priv,
}
else
{
/* Successfully transferred. Update the buffer pointer and length */
/* Successfully transferred. Update the buffer pointer/length */
buffer += xfrlen;
buflen -= xfrlen;
@ -2373,7 +2375,7 @@ static void stm32l4_out_next(FAR struct stm32l4_usbhost_s *priv,
int result;
int ret;
/* Is the full transfer complete? Did the last chunk transfer complete OK? */
/* Is the full transfer complete? Did the last chunk transfer OK? */
result = -(int)chan->result;
if (chan->xfrd < chan->buflen && result == OK)
@ -2436,7 +2438,7 @@ static int stm32l4_out_asynch(FAR struct stm32l4_usbhost_s *priv, int chidx,
FAR struct stm32l4_chan_s *chan;
int ret;
/* Set up for the transfer data and callback BEFORE starting the first transfer */
/* Set up for the transfer BEFORE starting the first transfer */
chan = &priv->chan[chidx];
chan->buffer = buffer;
@ -2542,11 +2544,11 @@ static inline void stm32l4_gint_hcinisr(FAR struct stm32l4_usbhost_s *priv,
pending &= regval;
uinfo("HCINTMSK%d: %08x pending: %08x\n", chidx, regval, pending);
/* Check for a pending ACK response received/transmitted (ACK) interrupt */
/* Check for a pending ACK response received/transmitted interrupt */
if ((pending & OTGFS_HCINT_ACK) != 0)
{
/* Clear the pending the ACK response received/transmitted (ACK) interrupt */
/* Clear the pending the ACK response received/transmitted interrupt */
stm32l4_putreg(STM32L4_OTGFS_HCINT(chidx), OTGFS_HCINT_ACK);
}
@ -2610,7 +2612,7 @@ static inline void stm32l4_gint_hcinisr(FAR struct stm32l4_usbhost_s *priv,
stm32l4_putreg(STM32L4_OTGFS_HCINT(chidx), OTGFS_HCINT_XFRC);
/* Then handle the transfer completion event based on the endpoint type */
/* Then handle the transfer completion event based on the endpoint */
if (chan->eptype == OTGFS_EPTYPE_CTRL ||
chan->eptype == OTGFS_EPTYPE_BULK)
@ -2746,7 +2748,7 @@ static inline void stm32l4_gint_hcinisr(FAR struct stm32l4_usbhost_s *priv,
}
#else
/* Halt all transfers on the NAK -- the CHH interrupt is expected next */
/* Halt all transfers on the NAK -- CHH interrupt is expected next */
stm32l4_chan_halt(priv, chidx, CHREASON_NAK);
#endif
@ -2799,11 +2801,11 @@ static inline void stm32l4_gint_hcoutisr(FAR struct stm32l4_usbhost_s *priv,
pending &= regval;
uinfo("HCINTMSK%d: %08x pending: %08x\n", chidx, regval, pending);
/* Check for a pending ACK response received/transmitted (ACK) interrupt */
/* Check for a pending ACK response received/transmitted interrupt */
if ((pending & OTGFS_HCINT_ACK) != 0)
{
/* Clear the pending the ACK response received/transmitted (ACK) interrupt */
/* Clear the pending the ACK response received/transmitted interrupt */
stm32l4_putreg(STM32L4_OTGFS_HCINT(chidx), OTGFS_HCINT_ACK);
}
@ -3125,7 +3127,7 @@ static inline void stm32l4_gint_rxflvlisr(FAR struct stm32l4_usbhost_s *priv)
chidx = (grxsts & OTGFS_GRXSTSH_CHNUM_MASK) >> OTGFS_GRXSTSH_CHNUM_SHIFT;
/* Get the host channel characteristics register (HCCHAR) for this channel */
/* Get the host channel characteristics register (HCCHAR) */
hcchar = stm32l4_getreg(STM32L4_OTGFS_HCCHAR(chidx));
@ -3777,7 +3779,7 @@ static inline void stm32l4_hostinit_enable(void)
stm32l4_putreg(STM32L4_OTGFS_GINTSTS, 0xffffffff);
/* Clear any pending USB OTG Interrupts (should be done elsewhere if OTG is supported) */
/* Clear any pending USB OTG Interrupts */
stm32l4_putreg(STM32L4_OTGFS_GOTGINT, 0xffffffff);
@ -4147,7 +4149,7 @@ static int stm32l4_ep0configure(FAR struct usbhost_driver_s *drvr,
DEBUGASSERT(drvr != NULL && ep0info != NULL && funcaddr < 128 &&
maxpacketsize <= 64);
/* We must have exclusive access to the USB host hardware and state structures */
/* We must have exclusive access to the USB host hardware and structures */
ret = stm32l4_takesem(&priv->exclsem);
if (ret < 0)
@ -4212,7 +4214,7 @@ static int stm32l4_epalloc(FAR struct usbhost_driver_s *drvr,
DEBUGASSERT(drvr != 0 && epdesc != NULL && ep != NULL);
/* We must have exclusive access to the USB host hardware and state structures */
/* We must have exclusive access to the USB host hardware and structures */
ret = stm32l4_takesem(&priv->exclsem);
if (ret < 0)
@ -4266,7 +4268,7 @@ static int stm32l4_epfree(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep)
DEBUGASSERT(priv);
/* We must have exclusive access to the USB host hardware and state structures */
/* We must have exclusive access to the USB host hardware and structures */
ret = stm32l4_takesem_noncancelable(&priv->exclsem);
@ -4536,7 +4538,7 @@ static int stm32l4_ctrlin(FAR struct usbhost_driver_s *drvr,
buflen = stm32l4_getle16(req->len);
/* We must have exclusive access to the USB host hardware and state structures */
/* We must have exclusive access to the USB host hardware and structures */
ret = stm32l4_takesem(&priv->exclsem);
if (ret < 0)
@ -4595,7 +4597,7 @@ static int stm32l4_ctrlin(FAR struct usbhost_driver_s *drvr,
while (elapsed < STM32L4_DATANAK_DELAY);
}
/* All failures exit here after all retries and timeouts have been exhausted */
/* All failures exit here after all retries and timeouts are exhausted */
stm32l4_givesem(&priv->exclsem);
return -ETIMEDOUT;
@ -4625,7 +4627,7 @@ static int stm32l4_ctrlout(FAR struct usbhost_driver_s *drvr,
buflen = stm32l4_getle16(req->len);
/* We must have exclusive access to the USB host hardware and state structures */
/* We must have exclusive access to the USB host hardware and structures */
ret = stm32l4_takesem(&priv->exclsem);
if (ret < 0)
@ -4688,7 +4690,7 @@ static int stm32l4_ctrlout(FAR struct usbhost_driver_s *drvr,
while (elapsed < STM32L4_DATANAK_DELAY);
}
/* All failures exit here after all retries and timeouts have been exhausted */
/* All failures exit here after all retries and timeouts are exhausted */
stm32l4_givesem(&priv->exclsem);
return -ETIMEDOUT;
@ -4746,7 +4748,7 @@ static ssize_t stm32l4_transfer(FAR struct usbhost_driver_s *drvr,
DEBUGASSERT(priv && buffer && chidx < STM32L4_MAX_TX_FIFOS && buflen > 0);
/* We must have exclusive access to the USB host hardware and state structures */
/* We must have exclusive access to the USB host hardware and structures */
ret = stm32l4_takesem(&priv->exclsem);
if (ret < 0)
@ -4818,7 +4820,7 @@ static int stm32l4_asynch(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep,
DEBUGASSERT(priv && buffer && chidx < STM32L4_MAX_TX_FIFOS && buflen > 0);
/* We must have exclusive access to the USB host hardware and state structures */
/* We must have exclusive access to the USB host hardware and structures */
ret = stm32l4_takesem(&priv->exclsem);
if (ret < 0)

4
arch/mips/src/pic32mz/pic32mz_i2c.c
View file

@ -514,7 +514,7 @@ static void pic32mz_i2c_tracenew(FAR struct pic32mz_i2c_priv_s *priv,
if (trace->count != 0)
{
/* Yes.. bump up the trace index (unless we are out of trace entries) */
/* Yes.. bump up the trace index (unless out of trace entries) */
if (priv->tndx >= (CONFIG_I2C_NTRACE - 1))
{
@ -1693,7 +1693,7 @@ static int pic32mz_i2c_transfer(FAR struct i2c_master_s *dev,
pic32mz_i2c_tracedump(priv);
/* Ensure that any ISR happening after we finish can't overwrite any user data */
/* Ensure ISR happening after we finish can't overwrite any user data */
priv->dcnt = 0;
priv->ptr = NULL;

4
drivers/lcd/ft80x.c
View file

@ -417,7 +417,7 @@ static int ft80x_interrupt(int irq, FAR void *context, FAR void *arg)
DEBUGASSERT(priv != NULL);
/* Schedule to perform the interrupt work on the high priority work queue. */
/* Perform the interrupt work on the high priority work queue. */
work_queue(HPWORK, &priv->intwork, ft80x_interrupt_work, priv, 0);
@ -1455,7 +1455,7 @@ static int ft80x_initialize(FAR struct ft80x_dev_s *priv)
/* 7. Enable back light control for display */
#warning Missing logic
/* 8. Write FT80X_REG_PCLK, video output begins with the first display list */
/* 8. Write FT80X_REG_PCLK, video output with the first display list */
#if defined(CONFIG_LCD_FT80X_WQVGA)
ft80x_write_byte(priv, FT80X_REG_PCLK, 5);

8
drivers/mmcsd/mmcsd_sdio.c
View file

@ -1786,7 +1786,7 @@ static ssize_t mmcsd_writesingle(FAR struct mmcsd_state_s *priv,
if ((priv->caps & SDIO_CAPS_DMABEFOREWRITE) == 0)
{
/* Send CMD24, WRITE_BLOCK, and verify that good R1 status is returned */
/* Send CMD24, WRITE_BLOCK, and verify good R1 status is returned */
mmcsd_sendcmdpoll(priv, MMCSD_CMD24, offset);
ret = mmsd_recv_r1(priv, MMCSD_CMD24);
@ -1823,7 +1823,7 @@ static ssize_t mmcsd_writesingle(FAR struct mmcsd_state_s *priv,
if ((priv->caps & SDIO_CAPS_DMABEFOREWRITE) != 0)
{
/* Send CMD24, WRITE_BLOCK, and verify that good R1 status is returned */
/* Send CMD24, WRITE_BLOCK, and verify good R1 status is returned */
mmcsd_sendcmdpoll(priv, MMCSD_CMD24, offset);
ret = mmsd_recv_r1(priv, MMCSD_CMD24);
@ -3276,7 +3276,7 @@ static int mmcsd_cardidentify(FAR struct mmcsd_state_s *priv)
priv->type |= MMCSD_CARDTYPE_BLOCK;
}
/* And break out of the loop with an SD card identified */
/* And break out of the loop with an card identified */
break;
}
@ -3432,7 +3432,7 @@ static int mmcsd_probe(FAR struct mmcsd_state_s *priv)
}
else
{
/* Then initialize the driver according to the identified card type */
/* Then initialize the driver according to the card type */
switch (priv->type)
{

173
drivers/mtd/sst39vf.c
View file

@ -91,17 +91,8 @@
struct sst39vf_chip_s
{
#if 0 /* Not used */
bool top; /* Top protect SST39VF1602/3202 */
#endif
uint16_t chipid; /* ID of the chip */
#if 0 /* Not used */
uint16_t nblocks; /* Number of erase blocks */
#endif
uint16_t nsectors; /* Number of erase-ablesectors */
#if 0 /* Not used */
uint32_t blocksize; /* Size of one erase block */
#endif
uint32_t sectorsize; /* Size of one sector */
};
@ -130,7 +121,8 @@ struct sst39vf_dev_s
/* Low Level Helpers */
static inline void sst39vf_flashwrite(FAR const struct sst39vf_wrinfo_s *wrinfo);
static inline void
sst39vf_flashwrite(FAR const struct sst39vf_wrinfo_s *wrinfo);
static inline uint16_t sst39vf_flashread(uintptr_t address);
static void sst39vf_writeseq(FAR const struct sst39vf_wrinfo_s *wrinfo,
int nseq);
@ -159,41 +151,29 @@ static int sst39vf_ioctl(FAR struct mtd_dev_s *dev, int cmd,
static const struct sst39vf_chip_s g_sst39vf1601 =
{
/* false, top - Bottom hardware block protection */
0x234b, /* chipid */
/* 32, nblocks */
512, /* nsectors */
/* 64 * 1024, blocksize */
4 * 1024 /* sectorsize */
};
static const struct sst39vf_chip_s g_sst39vf1602 =
{
/* true, top - Top hardware block protection */
0x234a, /* chipid */
/* 32, nblocks */
512, /* nsectors */
/* 64 * 1024, blocksize */
4 * 1024 /* sectorsize */
};
static const struct sst39vf_chip_s g_sst39vf3201 =
{
/* false, top - Bottom hardware block protection */
0x235b, /* chipid */
/* 64, nblocks */
1024, /* nsectors */
/* 64 * 1024, blocksize */
4 * 1024 /* sectorsize */
};
static const struct sst39vf_chip_s g_sst39vf3202 =
{
/* true, top - Top hardware block protection */
0x235a, /* chipid */
/* 64, nblocks */
1024, /* nsectors */
/* 64 * 1024, blocksize */
4 * 1024 /* sectorsize */
};
@ -219,80 +199,84 @@ static struct sst39vf_dev_s g_sst39vf =
static const struct sst39vf_wrinfo_s g_wordprogram[3] =
{
{0x5555, 0x00aa}, {0x2aaa, 0x0055}, {0x5555, 0x00a0} /* , {address, data} */
{
0x5555, 0x00aa
},
{
0x2aaa, 0x0055
},
{
0x5555, 0x00a0
}
};
static const struct sst39vf_wrinfo_s g_sectorerase[5] =
{
{0x5555, 0x00aa}, {0x2aaa, 0x0055}, {0x5555, 0x0080},
{0x5555, 0x00aa}, {0x2aaa, 0x0055} /* , {sector, 0x0030} */
{
0x5555, 0x00aa
},
{
0x2aaa, 0x0055
},
{
0x5555, 0x0080
},
{
0x5555, 0x00aa
},
{
0x2aaa, 0x0055
}
};
#if 0 /* Not used */
static const struct sst39vf_wrinfo_s g_blockerase[5] =
{
{0x5555, 0x00aa}, {0x2aaa, 0x0055}, {0x5555, 0x80},
{0x5555, 0x00aa}, {0x2aaa, 0x0055} /* , {block, 0x0050} */
};
#endif
static const struct sst39vf_wrinfo_s g_chiperase[6] =
{
{0x5555, 0x00aa}, {0x2aaa, 0x0055}, {0x5555, 0x0080},
{0x5555, 0x00aa}, {0x2aaa, 0x0055}, {0x5555, 0x0010}
{
0x5555, 0x00aa
},
{
0x2aaa, 0x0055
},
{
0x5555, 0x0080
},
{
0x5555, 0x00aa
},
{
0x2aaa, 0x0055
},
{
0x5555, 0x0010
}
};
#if 0 /* Not used */
static const struct sst39vf_wrinfo_s g_erasesuspend[1] =
{
{0x5555, 0x00aa}
};
static const struct sst39vf_wrinfo_s g_eraseresume[1] =
{
{0x5555, 0x00aa}
};
static const struct sst39vf_wrinfo_s g_querysecid[3] =
{
{0x5555, 0x00aa}, {0x2aaa, 0x0055}, {0x5555, 0x0088}
};
static const struct sst39vf_wrinfo_s g_securityid_wordprogram[3] =
{
{0x5555, 0x00aa}, {0x2aaa, 0x0055}, {0x5555, 0x00a5}, /* {address, data} */
};
static const struct sst39vf_wrinfo_s g_securityid_lockout[3] =
{
{0x5555, 0x00aa}, {0x2aaa, 0x0055}, {0x5555, 0x0085} /* {0xXX, 0x0000} */
};
#endif
static const struct sst39vf_wrinfo_s g_swid_entry[3] =
{
{0x5555, 0x00aa}, {0x2aaa, 0x0055}, {0x5555, 0x0090}
{
0x5555, 0x00aa
},
{
0x2aaa, 0x0055
},
{
0x5555, 0x0090
}
};
#if 0 /* Not used */
static const struct sst39vf_wrinfo_s g_cfiquery[3] =
{
{0x5555, 0x00aa}, {0x2aaa, 0x0055}, {0x5555, 0x0080},
};
#endif
static const struct sst39vf_wrinfo_s g_swid_exit[3] =
{
{0x5555, 0x00aa}, {0x2aaa, 0x0055}, {0x5555, 0x00f0}
{
0x5555, 0x00aa
},
{
0x2aaa, 0x0055
},
{
0x5555, 0x00f0
}
};
#if 0 /* Not used */
static const struct sst39vf_wrinfo_s g_swid_exit2[1] =
{
{0x0000, 0x00f0},
};
#endif
/****************************************************************************
* Private Functions
****************************************************************************/
@ -305,7 +289,8 @@ static const struct sst39vf_wrinfo_s g_swid_exit2[1] =
*
****************************************************************************/
static inline void sst39vf_flashwrite(FAR const struct sst39vf_wrinfo_s *wrinfo)
static inline void
sst39vf_flashwrite(FAR const struct sst39vf_wrinfo_s *wrinfo)
{
volatile uint16_t *addr = SST39VF_ADDR(wrinfo->address);
*addr = wrinfo->data;
@ -332,7 +317,8 @@ static inline uint16_t sst39vf_flashread(uintptr_t address)
*
****************************************************************************/
static void sst39vf_writeseq(FAR const struct sst39vf_wrinfo_s *wrinfo, int nseq)
static void sst39vf_writeseq(FAR const struct sst39vf_wrinfo_s *wrinfo,
int nseq)
{
while (nseq--)
{
@ -361,8 +347,8 @@ static void sst39vf_writeseq(FAR const struct sst39vf_wrinfo_s *wrinfo, int nseq
* "An additional Toggle Bit is available on DQ2, which can be used in
* conjunction with DQ6 to check whether a particular sector is being
* actively erased or erase-suspended. ... The Toggle Bit (DQ2) is valid
* after the rising edge of the last WE# (or CE#) pulse of Write operation.
* ..."
* after the rising edge of the last WE# (or CE#) pulse of Write
* operation."
*
****************************************************************************/
@ -406,12 +392,12 @@ static int sst39vf_waittoggle(FAR const struct sst39vf_wrinfo_s *wrinfo,
* Erase the entire chip
*
* "The SST39VF160x/320x provide a Chip-Erase operation, which allows the
* user to erase the entire memory array to the “1” state. This is useful
* when the entire device must be quickly erased. The Chip-Erase operation
* is initiated by executing a six-byte command sequence with Chip-Erase
* command (10H) at address 5555H in the last byte sequence. The Erase
* operation begins with the rising edge of the sixth WE# or CE#,
* whichever occurs first. During the Erase operation, the only valid
* user to erase the entire memory array to the “1” state. This is
* useful when the entire device must be quickly erased. The Chip-Erase
* operation is initiated by executing a six-byte command sequence with
* Chip-Erase command (10H) at address 5555H in the last byte sequence.
* The Erase operation begins with the rising edge of the sixth WE# or
* CE#, whichever occurs first. During the Erase operation, the only valid
* read is Toggle Bit or Data# Polling... Any commands issued during the
* Chip-Erase operation are ignored. When WP# is low, any attempt to
* Chip-Erase will be ignored. During the command sequence, WP# should
@ -557,8 +543,8 @@ static int sst39vf_sectorerase(FAR struct sst39vf_dev_s *priv,
* programming, the sector where the word exists must be fully erased. The
* rogram operation is accomplished in three steps. The first step is the
* three-byte load sequence for Software Data Protection. The second step
* is to load word address and word data. During the Word-Program operation,
* the addresses are latched on the falling edge of either CE# or WE#,
* is to load word address and word data. During the Word-Program operation
* , the addresses are latched on the falling edge of either CE# or WE#,
* whichever occurs last. The data is latched on the rising edge of either
* CE# or WE#, whichever occurs first. The third step is the internal
* Program operation which is initiated after the rising edge of the
@ -725,7 +711,8 @@ static ssize_t sst39vf_read(FAR struct mtd_dev_s *dev, off_t offset,
* Name: sst39vf_ioctl
****************************************************************************/
static int sst39vf_ioctl(FAR struct mtd_dev_s *dev, int cmd, unsigned long arg)
static int sst39vf_ioctl(FAR struct mtd_dev_s *dev,
int cmd, unsigned long arg)
{
FAR struct sst39vf_dev_s *priv = (FAR struct sst39vf_dev_s *)dev;
int ret = -ENOTTY;
@ -739,8 +726,8 @@ static int sst39vf_ioctl(FAR struct mtd_dev_s *dev, int cmd, unsigned long arg)
FAR struct mtd_geometry_s *geo = (FAR struct mtd_geometry_s *)arg;
if (geo)
{
/* Populate the geometry structure with information need to know
* the capacity and how to access the device.
/* Populate the geometry structure with information need to
* know the capacity and how to access the device.
*/
geo->blocksize = priv->chip->sectorsize;

73
drivers/net/enc28j60.c
View file

@ -130,7 +130,7 @@
#define ENCWORK LPWORK
/* CONFIG_ENC28J60_DUMPPACKET will dump the contents of each packet to the console. */
/* CONFIG_ENC28J60_DUMPPACKET will dump the contents of each packet. */
#ifdef CONFIG_ENC28J60_DUMPPACKET
# define enc_dumppacket(m,a,n) lib_dumpbuffer(m,a,n)
@ -146,7 +146,7 @@
/* Timing *******************************************************************/
/* TX poll deley = 1 seconds. CLK_TCK is the number of clock ticks per second */
/* TX poll deley = 1 seconds. CLK_TCK is the number of ticks per second */
#define ENC_WDDELAY (1*CLK_TCK)
@ -192,7 +192,7 @@
#define enc_bfsgreg(priv,ctrlreg,setbits) \
enc_wrgreg2(priv, ENC_BFS | GETADDR(ctrlreg), setbits)
/* This is a helper pointer for accessing the contents of the Ethernet header */
/* This is a helper pointer for accessing the contents of Ethernet header */
#define BUF ((struct eth_hdr_s *)priv->dev.d_buf)
@ -404,8 +404,8 @@ static inline void enc_configspi(FAR struct spi_dev_s *spi)
static void enc_lock(FAR struct enc_driver_s *priv)
{
/* Lock the SPI bus in case there are multiple devices competing for the SPI
* bus.
/* Lock the SPI bus in case there are multiple devices competing for the
* SPI bus.
*/
SPI_LOCK(priv->spi, true);
@ -475,7 +475,7 @@ static uint8_t enc_rdgreg2(FAR struct enc_driver_s *priv, uint8_t cmd)
* 16-clocks: 8 to clock out the cmd + 8 to clock in the data.
*/
SPI_SEND(priv->spi, cmd); /* Clock out the command */
SPI_SEND(priv->spi, cmd); /* Clock out the command */
rddata = SPI_SEND(priv->spi, 0); /* Clock in the data */
/* De-select ENC28J60 chip */
@ -988,7 +988,7 @@ static uint16_t enc_rdphy(FAR struct enc_driver_s *priv, uint8_t phyaddr)
/* "To read from a PHY register:
*
* 1. Write the address of the PHY register to read from into the MIREGADR
* 1. Write the address of the PHY register to read from into MIREGADR
* register.
*/
@ -1059,8 +1059,8 @@ static void enc_wrphy(FAR struct enc_driver_s *priv, uint8_t phyaddr,
enc_wrbreg(priv, ENC_MIWRL, phydata);
/* 3. Write the upper 8 bits of data to write into the MIWRH register.
* Writing to this register automatically begins the MIIM transaction,
/* 3. Write the upper 8 bits of data to write into MIWRH register.
* Writing to this register automatically begins MIIM transaction,
* so it must be written to after MIWRL. The MISTAT.BUSY bit becomes
* set.
*/
@ -1068,7 +1068,7 @@ static void enc_wrphy(FAR struct enc_driver_s *priv, uint8_t phyaddr,
enc_wrbreg(priv, ENC_MIWRH, phydata >> 8);
/* The PHY register will be written after the MIIM operation completes,
* which takes 10.24 µs. When the write operation has completed, the BUSY
* which takes 10.24 µs. When the write operation has completed, BUSY
* bit will clear itself.
*
* The host controller should not start any MIISCAN or MIIRD operations
@ -1232,8 +1232,8 @@ static int enc_txpoll(struct net_driver_s *dev)
}
}
/* If zero is returned, the polling will continue until all connections have
* been examined.
/* If zero is returned, the polling will continue until all connections
* have been examined.
*/
return OK;
@ -1306,7 +1306,7 @@ static void enc_txif(FAR struct enc_driver_s *priv)
* Name: enc_txerif
*
* Description:
* An TXERIF interrupt was received indicating that a TX abort has occurred.
* An TXERIF interrupt was received indicating that TX abort has occurred.
*
* Input Parameters:
* priv - Reference to the driver state structure
@ -1349,8 +1349,8 @@ static void enc_txerif(FAR struct enc_driver_s *priv)
* Name: enc_rxerif
*
* Description:
* An RXERIF interrupt was received indicating that the last TX packet(s) is
* done
* An RXERIF interrupt was received indicating that the last TX packet(s)
* is done
*
* Input Parameters:
* priv - Reference to the driver state structure
@ -1637,11 +1637,11 @@ static void enc_irqworker(FAR void *arg)
/* Disable further interrupts by clearing the global interrupt enable bit.
* "After an interrupt occurs, the host controller should clear the global
* enable bit for the interrupt pin before servicing the interrupt. Clearing
* the enable bit will cause the interrupt pin to return to the non-asserted
* state (high). Doing so will prevent the host controller from missing a
* falling edge should another interrupt occur while the immediate interrupt
* is being serviced."
* enable bit for the interrupt pin before servicing the interrupt.
* Clearing the enable bit will cause the interrupt pin to return to the
* non-asserted state (high). Doing so will prevent the host controller
* from missing a falling edge should another interrupt occur while the
* immediate interrupt is being serviced."
*/
enc_bfcgreg(priv, ENC_EIE, EIE_INTIE);
@ -1660,10 +1660,10 @@ static void enc_irqworker(FAR void *arg)
ninfo("EIR: %02x\n", eir);
/* DMAIF: The DMA interrupt indicates that the DMA module has completed
* its memory copy or checksum calculation. Additionally, this interrupt
* will be caused if the host controller cancels a DMA operation by
* manually clearing the DMAST bit. Once set, DMAIF can only be cleared
* by the host controller or by a Reset condition.
* its memory copy or checksum calculation. Additionally, this
* interrupt will be caused if the host controller cancels a DMA
* operation by manually clearing the DMAST bit. Once set, DMAIF can
* only be cleared by the host controller or by a Reset condition.
*/
if ((eir & EIR_DMAIF) != 0) /* DMA interrupt */
@ -1745,9 +1745,9 @@ static void enc_irqworker(FAR void *arg)
* In Full-Duplex mode, condition 5 is the only one that should cause
* this interrupt. Collisions and other problems related to sharing
* the network are not possible on full-duplex networks. The conditions
* which cause the transmit error interrupt meet the requirements of the
* transmit interrupt. As a result, when this interrupt occurs, TXIF
* will also be simultaneously set.
* which cause the transmit error interrupt meet the requirements of
* the transmit interrupt. As a result, when this interrupt occurs,
* TXIF will also be simultaneously set.
*/
if ((eir & EIR_TXERIF) != 0) /* Transmit Error Interrupts */
@ -1761,12 +1761,13 @@ static void enc_irqworker(FAR void *arg)
* buffer and to provide a notification means for the arrival of new
* packets. When the receive buffer has at least one packet in it,
* EIR.PKTIF will be set. In other words, this interrupt flag will be
* set anytime the Ethernet Packet Count register (EPKTCNT) is non-zero.
* set anytime the Ethernet Packet Count register (EPKTCNT) is
* non-zero.
*
* The PKTIF bit can only be cleared by the host controller or by a
* Reset condition. In order to clear PKTIF, the EPKTCNT register must
* be decremented to 0. If the last data packet in the receive buffer is
* processed, EPKTCNT will become zero and the PKTIF bit will
* be decremented to 0. If the last data packet in the receive buffer
* is processed, EPKTCNT will become zero and the PKTIF bit will
* automatically be cleared.
*/
@ -1959,7 +1960,7 @@ static void enc_txtimeout(int argc, uint32_t arg, ...)
* can occur until we restart the Tx timeout watchdog.
*/
ret = work_queue(ENCWORK, &priv->towork, enc_toworker, (FAR void *)priv, 0);
ret = work_queue(ENCWORK, &priv->towork, enc_toworker, priv, 0);
DEBUGASSERT(ret == OK);
UNUSED(ret);
}
@ -2220,14 +2221,16 @@ static int enc_txavail(struct net_driver_s *dev)
if (priv->ifstate == ENCSTATE_UP)
{
/* Check if the hardware is ready to send another packet. The driver
* starts a transmission process by setting ECON1.TXRTS. When the packet
* is finished transmitting or is aborted due to an error/cancellation,
* the ECON1.TXRTS bit will be cleared.
* starts a transmission process by setting ECON1.TXRTS. When the
* packet is finished transmitting or is aborted due to an error/
* cancellation, the ECON1.TXRTS bit will be cleared.
*/
if ((enc_rdgreg(priv, ENC_ECON1) & ECON1_TXRTS) == 0)
{
/* The interface is up and TX is idle; poll the network for new XMIT data */
/* The interface is up and TX is idle;
* poll the network for new XMIT data
*/
devif_poll(&priv->dev, enc_txpoll);
}

90
drivers/net/encx24j600.c
View file

@ -90,8 +90,8 @@
* CONFIG_ENCX24J600 - Enabled ENCX24J600 support
* CONFIG_ENCX24J600_SPIMODE - Controls the SPI mode
* CONFIG_ENCX24J600_FREQUENCY - Define to use a different bus frequency
* CONFIG_ENCX24J600_NINTERFACES - Specifies the number of physical ENCX24J600
* devices that will be supported.
* CONFIG_ENCX24J600_NINTERFACES - Specifies the number of physica
* l ENCX24J600 devices that will be supported.
*/
/* The ENCX24J600 spec says that it supports SPI mode 0,0 only: "The
@ -136,7 +136,7 @@
#define ENCWORK LPWORK
/* CONFIG_ENCX24J600_DUMPPACKET will dump the contents of each packet to the console. */
/* CONFIG_ENCX24J600_DUMPPACKET will dump the contents of each packet. */
#ifdef CONFIG_ENCX24J600_DUMPPACKET
# define enc_dumppacket(m,a,n) lib_dumpbuffer(m,a,n)
@ -152,7 +152,7 @@
/* Timing *******************************************************************/
/* TX poll delay = 1 seconds. CLK_TCK is the number of clock ticks per second */
/* TX poll delay = 1 seconds. CLK_TCK is the number of ticks per second */
#define ENC_WDDELAY (1*CLK_TCK)
@ -181,7 +181,7 @@
#define ENC_NTXDESCR ((PKTMEM_RX_START - PKTMEM_START) / PKTMEM_ALIGNED_BUFSIZE)
/* This is a helper pointer for accessing the contents of the Ethernet header */
/* This is a helper pointer for accessing the contents of Ethernet header */
#define BUF ((struct eth_hdr_s *)priv->dev.d_buf)
@ -305,7 +305,8 @@ static void enc_bfs(FAR struct enc_driver_s *priv, uint16_t ctrlreg,
uint16_t bits);
static void enc_bfc(FAR struct enc_driver_s *priv, uint16_t ctrlreg,
uint16_t bits);
static void enc_cmd(FAR struct enc_driver_s *priv, uint8_t cmd, uint16_t arg);
static void enc_cmd(FAR struct enc_driver_s *priv,
uint8_t cmd, uint16_t arg);
#if 0 /* Sometimes useful */
static void enc_rxdump(FAR struct enc_driver_s *priv);
@ -395,8 +396,8 @@ static int enc_reset(FAR struct enc_driver_s *priv);
static void enc_lock(FAR struct enc_driver_s *priv)
{
/* Lock the SPI bus in case there are multiple devices competing for the SPI
* bus.
/* Lock the SPI bus in case there are multiple devices competing for the
* SPI bus.
*/
SPI_LOCK(priv->spi, true);
@ -921,7 +922,7 @@ static uint16_t enc_rdphy(FAR struct enc_driver_s *priv, uint8_t phyaddr)
uint16_t data = 0;
/* "To read from a PHY register:
* 1. Write the address of the PHY register to read from into the MIREGADR
* 1. Write the address of the PHY register to read from into MIREGADR
* register (Register 3-1). Make sure to also set reserved bit 8 of
* this register.
*/
@ -937,7 +938,7 @@ static uint16_t enc_rdphy(FAR struct enc_driver_s *priv, uint8_t phyaddr)
/* 3. Wait 25.6 μs. Poll the BUSY (MISTAT<0>) bit to be certain that the
* operation is complete. While busy, the host controller should not
* start any MIISCAN operations or write to the MIWR register. When the
* start any MIISCAN operations or write to the MIWR register. When
* MAC has obtained the register contents, the BUSY bit will clear
* itself.
*/
@ -982,14 +983,14 @@ static void enc_wrphy(FAR struct enc_driver_s *priv, uint8_t phyaddr,
{
/* "To write to a PHY register:
*
* 1. Write the address of the PHY register to write to into the MIREGADR
* 1. Write the address of the PHY register to write to into MIREGADR
* register. Make sure to also set reserved bit 8 of this register.
*/
enc_wrreg(priv, ENC_MIREGADR, 0x0100 | phyaddr);
/* 2. Write the 16 bits of data into the MIWR register. The low byte must
* be written first, followed by the high byte.
/* 2. Write the 16 bits of data into the MIWR register. The low byte
* must be written first, followed by the high byte.
*/
enc_wrreg(priv, ENC_MIWR, phydata);
@ -1206,8 +1207,8 @@ static int enc_txpoll(struct net_driver_s *dev)
}
}
/* If zero is returned, the polling will continue until all connections have
* been examined.
/* If zero is returned, the polling will continue until all connections
* have been examined.
*/
return ret;
@ -1385,8 +1386,8 @@ static struct enc_descr_s *enc_rxgetdescr(FAR struct enc_driver_s *priv)
* Name: enc_rxrmpkt
*
* Description:
* Remove packet from the RX queue and free the block of memory in the enc's
* SRAM.
* Remove packet from the RX queue and free the block of memory in the
* enc's SRAM.
*
* Input Parameters:
* priv - Reference to the driver state structure
@ -1482,7 +1483,7 @@ static void enc_rxdispatch(FAR struct enc_driver_s *priv)
enc_rxldpkt(priv, descr);
#ifdef CONFIG_NET_PKT
/* When packet sockets are enabled, feed the frame into the packet tap */
/* When packet sockets are enabled, feed the frame to the packet tap */
pkt_input(&priv->dev);
#endif
@ -1656,7 +1657,7 @@ static void enc_pktif(FAR struct enc_driver_s *priv)
{
curpkt = priv->nextpkt;
/* Set the rx data pointer to the start of the received packet (ERXRDPT) */
/* Set the rx data pointer to the start of received packet (ERXRDPT) */
enc_cmd(priv, ENC_WRXRDPT, curpkt);
@ -1835,11 +1836,12 @@ static void enc_irqworker(FAR void *arg)
/* A good practice is for the host controller to clear the Global Interrupt
* Enable bit, INTIE (EIE<15>), immediately after an interrupt event. This
* causes the interrupt pin to return to the non-asserted (high) state. Once
* the interrupt has been serviced, the INTIE bit is set again to re-enable
* interrupts. If a new interrupt occurs while servicing another, the act of
* resetting the global enable bit will cause a new falling edge to occur on
* the interrupt pin and ensure that the host does not miss any events
* causes the interrupt pin to return to the non-asserted (high) state.
* Once the interrupt has been serviced, the INTIE bit is set again to
* re-enable interrupts. If a new interrupt occurs while servicing another,
* the act of resetting the global enable bit will cause a new falling edge
* to occur on the interrupt pin and ensure that the host does not miss any
* events
*/
enc_bfc(priv, ENC_EIE, EIE_INTIE);
@ -1893,13 +1895,13 @@ static void enc_irqworker(FAR void *arg)
}
/* The receive abort interrupt occurs when the reception of a frame has
* been aborted. A frame being received is aborted when the Head Pointer
* attempts to overrun the Tail Pointer, or when the packet counter has
* reached FFh. In either case, the receive buffer is full and cannot
* fit the incoming frame, so the packet has been dropped. This
* interrupt does not occur when packets are dropped due to the receive
* filters rejecting a packet. The interrupt should be cleared by
* software once it has been serviced.
* been aborted. A frame being received is aborted when the Head
* Pointer attempts to overrun the Tail Pointer, or when the packet
* counter has reached FFh. In either case, the receive buffer is full
* and cannot fit the incoming frame, so the packet has been dropped.
* This interrupt does not occur when packets are dropped due to the
* receive filters rejecting a packet. The interrupt should be cleared
* by software once it has been serviced.
*
* To enable the receive abort interrupt, set RXABTIE (EIE<1>).
* The corresponding interrupt flag is RXABTIF (EIR<1>).
@ -1929,8 +1931,9 @@ static void enc_irqworker(FAR void *arg)
{
enc_pktif(priv); /* Handle packet receipt */
/* No clearing necessary, after PKTCNT == 0 the bit is automatically
* cleared. This means we will loop until all packets are processed.
/* No clearing necessary, after PKTCNT == 0 the bit is cleared
* automatically. This means we will loop until all packets are
* processed.
*/
}
@ -2111,7 +2114,7 @@ static void enc_txtimeout(int argc, uint32_t arg, ...)
* can occur until we restart the Tx timeout watchdog.
*/
ret = work_queue(ENCWORK, &priv->towork, enc_toworker, (FAR void *)priv, 0);
ret = work_queue(ENCWORK, &priv->towork, enc_toworker, priv, 0);
UNUSED(ret);
DEBUGASSERT(ret == OK);
}
@ -2383,7 +2386,9 @@ static int enc_txavail(struct net_driver_s *dev)
if ((enc_rdreg(priv, ENC_ECON1) & ECON1_TXRTS) == 0)
{
/* The interface is up and TX is idle; poll the network for new XMIT data */
/* The interface is up and TX is idle;
* poll the network for new XMIT data
*/
devif_poll(&priv->dev, enc_txpoll);
}
@ -2654,7 +2659,7 @@ static void enc_resetbuffers(FAR struct enc_driver_s *priv)
priv->nextpkt = PKTMEM_RX_START;
enc_wrreg(priv, ENC_ERXST, PKTMEM_RX_START);
/* Program the Tail Pointer, ERXTAIL, to the last even address of the buffer */
/* Program the Tail Pointer, ERXTAIL, to the last even address of buffer */
enc_wrreg(priv, ENC_ERXTAIL, PKTMEM_RX_END - 2);
@ -2663,7 +2668,7 @@ static void enc_resetbuffers(FAR struct enc_driver_s *priv)
sq_init(&priv->txqueue);
sq_init(&priv->rxqueue);
/* For transmission we preinitialize the descriptors to aligned NET_BUFFSIZE */
/* For transmission we preinitialize the descriptors */
for (i = 0; i < ENC_NTXDESCR; i++)
{
@ -2736,8 +2741,8 @@ static int enc_reset(FAR struct enc_driver_s *priv)
return -ENODEV;
}
/* Wait at least 256 μs for the PHY registers and PHY status bits to become
* available.
/* Wait at least 256 μs for the PHY registers and PHY status bits to
* become available.
*/
up_udelay(256);
@ -2747,9 +2752,10 @@ static int enc_reset(FAR struct enc_driver_s *priv)
enc_resetbuffers(priv);
#if 0
/* When restarting auto-negotiation, the ESTAT_PHYLINK gets set but the link
* seems not to be ready. Because auto-negotiation is enabled by default
* (but with different PHANA_* settings) I did not investigate that further.
/* When restarting auto-negotiation, the ESTAT_PHYLINK gets set but the
* link seems not to be ready. Because auto-negotiation is enabled by
* default (but with different PHANA_* settings) I did not investigate
* that further.
*/
/* "Typically, when using auto-negotiation, users should write 0x05e1 to

39
drivers/power/activity_governor.c
View file

@ -77,8 +77,8 @@ struct pm_domain_state_s
{
/* recommended - The recommended state based on the governor policy
* mndex - The index to the next slot in the memory[] array to use.
* mcnt - A tiny counter used only at start up. The actual
* algorithm cannot be applied until CONFIG_PM_GOVERNOR_MEMORY
* mcnt - A tiny counter used only at start up. The actual algorithm
* cannot be applied until CONFIG_PM_GOVERNOR_MEMORY
* samples have been collected.
*/
@ -245,18 +245,18 @@ static void governor_activity(int domain, int count)
DEBUGASSERT(domain >= 0 && domain < CONFIG_PM_NDOMAINS);
pdomstate = &g_pm_activity_governor.domain_states[domain];
/* Just increment the activity count in the current time slice. The priority
* is simply the number of counts that are added.
/* Just increment the activity count in the current time slice. The
* priority is simply the number of counts that are added.
*/
if (count > 0)
{
/* Add the activity count to the accumulated counts in a critical section. */
/* Add the activity count to the accumulated counts. */
flags = enter_critical_section();
accum = (uint32_t)pdomstate->accum + count;
/* Make sure that we do not overflow the underlying uint16_t representation */
/* Make sure that we do not overflow the underlying representation */
if (accum > INT16_MAX)
{
@ -270,9 +270,9 @@ static void governor_activity(int domain, int count)
/* Check the elapsed time. In periods of low activity, time slicing is
* controlled by IDLE loop polling; in periods of higher activity, time
* slicing is controlled by driver activity. In either case, the
* duration of the time slice is only approximate; during times of heavy
* activity, time slices may be become longer and the activity level may
* be over-estimated.
* duration of the time slice is only approximate; during times of
* heavy activity, time slices may be become longer and the activity
* level may be over-estimated.
*/
now = clock_systimer();
@ -327,7 +327,7 @@ static void governor_update(int domain, int16_t accum)
int index;
#if CONFIG_PM_GOVERNOR_MEMORY > 1
int32_t denom;
int i;
int i = 0;
int j;
#endif
@ -349,9 +349,9 @@ static void governor_update(int domain, int16_t accum)
return;
}
/* The averaging algorithm is simply: Y = (An*X + SUM(Ai*Yi))/SUM(Aj), where
* i = 1..n-1 and j= 1..n, n is the length of the "memory", Ai is the
* weight applied to each value, and X is the current activity.
/* The averaging algorithm is simply: Y = (An*X + SUM(Ai*Yi))/SUM(Aj),
* where i = 1..n-1 and j= 1..n, n is the length of the "memory", Ai is
* the weight applied to each value, and X is the current activity.
*
* CONFIG_PM_GOVERNOR_MEMORY:
* provides the memory for the algorithm. Default: 2
@ -365,11 +365,11 @@ static void governor_update(int domain, int16_t accum)
denom = CONFIG_PM_GOVERNOR_COEFN;
/* Then calculate Y += SUM(Ai*Yi), i = 1..n-1. The oldest sample will
* reside at the domain's mndx (and this is the value that we will overwrite
* with the new value).
* reside at the domain's mndx (and this is the value that we will
* overwrite with the new value).
*/
for (i = 0, j = pdomstate->mndx; i < CONFIG_PM_GOVERNOR_MEMORY - 1; i++, j++)
for (j = pdomstate->mndx; i < CONFIG_PM_GOVERNOR_MEMORY - 1; i++, j++)
{
if (j >= CONFIG_PM_GOVERNOR_MEMORY - 1)
{
@ -435,8 +435,8 @@ static void governor_update(int domain, int16_t accum)
{
unsigned int nextstate;
/* Get the next state and the table index for the next state (which will
* be the current state)
/* Get the next state and the table index for the next state (which
* will be the current state)
*/
index = state;
@ -605,7 +605,8 @@ static void governor_timer(int domain)
delay = 1;
}
if (!WDOG_ISACTIVE(pdomstate->wdog) || abs(delay - left) > PM_TIMER_GAP)
if (!WDOG_ISACTIVE(pdomstate->wdog) ||
abs(delay - left) > PM_TIMER_GAP)
{
wd_start(pdomstate->wdog, delay, governor_timer_cb, 0);
}

2
drivers/serial/serial.c
View file

@ -1359,7 +1359,7 @@ static int uart_ioctl(FAR struct file *filep, int cmd, unsigned long arg)
#endif
#if defined(CONFIG_TTY_SIGINT) || defined(CONFIG_TTY_SIGSTP)
/* Make the given terminal the controlling terminal of the calling process */
/* Make the controlling terminal of the calling process */
case TIOCSCTTY:
{

38
drivers/usbhost/usbhost_max3421e.c
View file

@ -1873,7 +1873,7 @@ static ssize_t max3421e_out_transfer(FAR struct max3421e_usbhost_s *priv,
return (ssize_t)ret;
}
/* Set up for the transfer based on the direction and the endpoint type */
/* Set up for the transfer based on the direction and the endpoint */
max3421e_lock(priv);
ret = max3421e_out_setup(priv, chan);
@ -1921,7 +1921,7 @@ static ssize_t max3421e_out_transfer(FAR struct max3421e_usbhost_s *priv,
}
else
{
/* Successfully transferred. Update the buffer pointer and length */
/* Successfully transferred. Update the buffer pointer/length */
buffer += xfrlen;
buflen -= xfrlen;
@ -1953,7 +1953,7 @@ static void max3421e_out_next(FAR struct max3421e_usbhost_s *priv,
int result;
int ret;
/* Is the full transfer complete? Did the last chunk transfer complete OK? */
/* Is the full transfer complete? Did the last chunk transfer OK? */
result = -(int)priv->result;
if (priv->xfrd < priv->buflen && result == OK)
@ -2018,7 +2018,7 @@ static int max3421e_out_asynch(FAR struct max3421e_usbhost_s *priv,
{
int ret;
/* Set up for the transfer data and callback BEFORE starting the first transfer */
/* Set up for the transfer BEFORE starting the first transfer */
priv->buffer = buffer;
priv->buflen = buflen;
@ -2699,7 +2699,7 @@ static ssize_t max3421e_in_transfer(FAR struct max3421e_usbhost_s *priv,
return (ssize_t)ret;
}
/* Set up for the transfer based on the direction and the endpoint type */
/* Set up for the transfer based on the direction and the endpoint */
max3421e_lock(priv);
ret = max3421e_in_setup(priv, chan);
@ -2867,7 +2867,7 @@ static void max3421e_in_next(FAR struct max3421e_usbhost_s *priv,
int result;
int ret;
/* Is the full transfer complete? Did the last chunk transfer complete OK? */
/* Is the full transfer complete? Did the last chunk transfer OK? */
result = -(int)priv->result;
if (priv->xfrd < priv->buflen && result == OK)
@ -2933,7 +2933,7 @@ static int max3421e_in_asynch(FAR struct max3421e_usbhost_s *priv,
{
int ret;
/* Set up for the transfer data and callback BEFORE starting the first transfer */
/* Set up for the transfer BEFORE starting the first transfer */
priv->buffer = buffer;
priv->buflen = buflen;
@ -3134,7 +3134,7 @@ static void max3421e_irqwork(FAR void *arg)
pending = max3421e_int_status(priv);
priv->lower->acknowledge(lower);
/* Break out of the loop when there are no further pending interrupts. */
/* Break out of the loop when there are no pending interrupts. */
if (pending == 0)
{
@ -3398,7 +3398,7 @@ static int max3421e_wait(FAR struct usbhost_connection_s *conn,
for (; ; )
{
/* We must have exclusive access to the USB host hardware and state structures */
/* We must have exclusive access to USB host hardware and structures */
ret = max3421e_take_exclsem(priv);
if (ret < 0)
@ -3577,7 +3577,7 @@ static int max3421e_enumerate(FAR struct usbhost_connection_s *conn,
DEBUGASSERT(maxconn != NULL && maxconn->priv != NULL);
priv = maxconn->priv;
/* We must have exclusive access to the USB host hardware and state structures */
/* We must have exclusive access to the USB host hardware and structures */
ret = max3421e_take_exclsem(priv);
if (ret < 0)
@ -3685,7 +3685,7 @@ static int max3421e_ep0configure(FAR struct usbhost_driver_s *drvr,
DEBUGASSERT(drvr != NULL && funcaddr < 128 && maxpacketsize <= 64);
/* We must have exclusive access to the USB host hardware and state structures */
/* We must have exclusive access to the USB host hardware and structures */
ret = max3421e_take_exclsem(priv);
if (ret < 0)
@ -3746,7 +3746,7 @@ static int max3421e_epalloc(FAR struct usbhost_driver_s *drvr,
hport = epdesc->hport;
DEBUGASSERT(hport != NULL);
/* We must have exclusive access to the USB host hardware and state structures */
/* We must have exclusive access to the USB host hardware and structures */
ret = max3421e_take_exclsem(priv);
if (ret < 0)
@ -3816,7 +3816,7 @@ static int max3421e_epfree(FAR struct usbhost_driver_s *drvr,
DEBUGASSERT(priv);
/* We must have exclusive access to the USB host hardware and state structures */
/* We must have exclusive access to the USB host hardware and structures */
ret = max3421e_take_exclsem(priv);
if (ret >= 0)
@ -4067,7 +4067,7 @@ static int max3421e_ctrlin(FAR struct usbhost_driver_s *drvr,
buflen = max3421e_getle16(req->len);
/* We must have exclusive access to the USB host hardware and state structures */
/* We must have exclusive access to the USB host hardware and structures */
ret = max3421e_take_exclsem(priv);
if (ret < 0)
@ -4132,7 +4132,7 @@ static int max3421e_ctrlin(FAR struct usbhost_driver_s *drvr,
while (elapsed < MAX3421E_DATANAK_DELAY);
}
/* All failures exit here after all retries and timeouts have been exhausted */
/* All failures exit here after all retries and timeouts are exhausted */
max3421e_give_exclsem(priv);
return -ETIMEDOUT;
@ -4167,7 +4167,7 @@ static int max3421e_ctrlout(FAR struct usbhost_driver_s *drvr,
buflen = max3421e_getle16(req->len);
/* We must have exclusive access to the USB host hardware and state structures */
/* We must have exclusive access to the USB host hardware and structures */
ret = max3421e_take_exclsem(priv);
if (ret < 0)
@ -4234,7 +4234,7 @@ static int max3421e_ctrlout(FAR struct usbhost_driver_s *drvr,
while (elapsed < MAX3421E_DATANAK_DELAY);
}
/* All failures exit here after all retries and timeouts have been exhausted */
/* All failures exit here after all retries and timeouts are exhausted */
max3421e_give_exclsem(priv);
return -ETIMEDOUT;
@ -4295,7 +4295,7 @@ static ssize_t max3421e_transfer(FAR struct usbhost_driver_s *drvr,
usbhost_vtrace2(MAX3421E_VTRACE2_TRANSFER, (unsigned int)ep, buflen);
/* We must have exclusive access to the USB host hardware and state structures */
/* We must have exclusive access to the USB host hardware and structures */
ret = max3421e_take_exclsem(priv);
if (ret < 0)
@ -4371,7 +4371,7 @@ static int max3421e_asynch(FAR struct usbhost_driver_s *drvr,
usbhost_vtrace2(MAX3421E_VTRACE2_ASYNCH, (unsigned int)ep, buflen);
/* We must have exclusive access to the USB host hardware and state structures */
/* We must have exclusive access to the USB host hardware and structures */
ret = max3421e_take_exclsem(priv);
if (ret < 0)

4
drivers/wireless/spirit/lib/spirit_spi.c
View file

@ -617,7 +617,7 @@ int spirit_update_status(FAR struct spirit_library_s *spirit)
return spirit_reg_read(spirit, MC_STATE1_BASE, &regval, 1);
}
/****************************************************************************
/******************************************************************************
* Name: spirit_waitstatus
*
* Description:
@ -635,7 +635,7 @@ int spirit_update_status(FAR struct spirit_library_s *spirit)
* Assumptions:
* We have exclusive access to the driver state and to the spirit library.
*
****************************************************************************/
******************************************************************************/
int spirit_waitstatus(FAR struct spirit_library_s *spirit,
enum spirit_state_e state, unsigned int msec)

14
fs/procfs/fs_procfsuptime.c
View file

@ -116,7 +116,7 @@ const struct procfs_operations uptime_operations =
uptime_open, /* open */
uptime_close, /* close */
uptime_read, /* read */
NULL, /* write */
NULL, /* write */
uptime_dup, /* dup */
@ -165,7 +165,7 @@ static int uptime_open(FAR struct file *filep, FAR const char *relpath,
/* Allocate a container to hold the file attributes */
attr = (FAR struct uptime_file_s *)kmm_zalloc(sizeof(struct uptime_file_s));
attr = kmm_zalloc(sizeof(struct uptime_file_s));
if (!attr)
{
ferr("ERROR: Failed to allocate file attributes\n");
@ -244,7 +244,7 @@ static ssize_t uptime_read(FAR struct file *filep, FAR char *buffer,
ticktime = clock_systimer() - INITIAL_SYSTEM_TIMER_TICKS;
#if defined(CONFIG_HAVE_DOUBLE) && defined(CONFIG_LIBC_FLOATINGPOINT)
/* Convert the system up time to a seconds + hundredths of seconds string */
/* Convert the up time to a seconds + hundredths of seconds string */
now = (double)ticktime / (double)CLOCKS_PER_SEC;
linesize = snprintf(attr->line, UPTIME_LINELEN, "%10.2f\n", now);
@ -256,7 +256,9 @@ static ssize_t uptime_read(FAR struct file *filep, FAR char *buffer,
remainder = (unsigned int)(ticktime % CLOCKS_PER_SEC);
csec = (100 * remainder + (CLOCKS_PER_SEC / 2)) / CLOCKS_PER_SEC;
/* Make sure that rounding did not force the hundredths of a second above 99 */
/* Make sure that rounding did not force the hundredths of
* a second above 99
*/
if (csec > 99)
{
@ -283,7 +285,7 @@ static ssize_t uptime_read(FAR struct file *filep, FAR char *buffer,
/* Transfer the system up time to user receive buffer */
offset = filep->f_pos;
ret = procfs_memcpy(attr->line, attr->linesize, buffer, buflen, &offset);
ret = procfs_memcpy(attr->line, attr->linesize, buffer, buflen, &offset);
/* Update the file offset */
@ -317,7 +319,7 @@ static int uptime_dup(FAR const struct file *oldp, FAR struct file *newp)
/* Allocate a new container to hold the task and attribute selection */
newattr = (FAR struct uptime_file_s *)kmm_malloc(sizeof(struct uptime_file_s));
newattr = kmm_malloc(sizeof(struct uptime_file_s));
if (!newattr)
{
ferr("ERROR: Failed to allocate file attributes\n");

3
net/socket/net_timeo.c
View file

@ -1,7 +1,8 @@
/****************************************************************************
* net/socket/net_timeo.c
*
* Copyright (C) 2007-2009, 2011-2012, 2014 Gregory Nutt. All rights reserved.
* Copyright (C) 2007-2009, 2011-2012, 2014 Gregory Nutt.
* All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without

22
net/tcp/tcp_conn.c
View file

@ -263,10 +263,10 @@ static int tcp_selectport(uint8_t domain, FAR const union ip_addr_u *ipaddr,
{
if (portno == 0)
{
/* No local port assigned. Loop until we find a valid listen port number
* that is not being used by any other connection. NOTE the following
* loop is assumed to terminate but could not if all 32000-4096+1 ports
* are in used (unlikely).
/* No local port assigned. Loop until we find a valid listen port
* number that is not being used by any other connection. NOTE the
* following loop is assumed to terminate but could not if all
* 32000-4096+1 ports are in used (unlikely).
*/
do
@ -476,7 +476,7 @@ static inline int tcp_ipv4_bind(FAR struct tcp_conn_s *conn,
return port;
}
/* Save the local address in the connection structure (network byte order). */
/* Save the local address in the connection structure (network order). */
conn->lport = htons(port);
net_ipv4addr_copy(conn->u.ipv4.laddr, addr->sin_addr.s_addr);
@ -535,15 +535,15 @@ static inline int tcp_ipv6_bind(FAR struct tcp_conn_s *conn,
/* The port number must be unique for this address binding */
port = tcp_selectport(PF_INET6,
(FAR const union ip_addr_u *)addr->sin6_addr.in6_u.u6_addr16,
ntohs(addr->sin6_port));
(FAR const union ip_addr_u *)addr->sin6_addr.in6_u.u6_addr16,
ntohs(addr->sin6_port));
if (port < 0)
{
nerr("ERROR: tcp_selectport failed: %d\n", port);
return port;
}
/* Save the local address in the connection structure (network byte order). */
/* Save the local address in the connection structure (network order). */
conn->lport = htons(port);
net_ipv6addr_copy(conn->u.ipv6.laddr, addr->sin6_addr.in6_u.u6_addr16);
@ -637,8 +637,8 @@ FAR struct tcp_conn_s *tcp_alloc(uint8_t domain)
if (!conn)
{
/* As a fall-back, check for connection structures which can be stalled.
*
/* As a fall-back, check for connection structures which can be
* stalled.
* Search the active connection list for the oldest connection
* that is about to be closed anyway.
*/
@ -1116,7 +1116,7 @@ int tcp_connect(FAR struct tcp_conn_s *conn, FAR const struct sockaddr *addr)
}
/* If the TCP port has not already been bound to a local port, then select
* one now. We assume that the IP address has been bound to a local device,
* one now. We assume that the IP address has been bound to a local device,
* but the port may still be INPORT_ANY.
*/

26
net/tcp/tcp_input.c
View file

@ -127,7 +127,7 @@ static void tcp_input(FAR struct net_driver_s *dev, uint8_t domain,
tcpiplen = iplen + TCP_HDRLEN;
/* Get the size of the link layer header, the IP header, and the TCP header */
/* Get the size of the link layer header, the IP and TCP header */
hdrlen = tcpiplen + NET_LL_HDRLEN(dev);
@ -192,8 +192,8 @@ static void tcp_input(FAR struct net_driver_s *dev, uint8_t domain,
* response.
*/
/* First allocate a new connection structure and see if there is any
* user application to accept it.
/* First allocate a new connection structure and see if there is
* any user application to accept it.
*/
conn = tcp_alloc_accept(dev, tcp);
@ -508,9 +508,9 @@ found:
if ((conn->tcpstateflags & TCP_STATE_MASK) == TCP_ESTABLISHED)
{
nwarn("WARNING: ackseq > unackseq\n");
nwarn(" sndseq=%u tx_unacked=%u unackseq=%u ackseq=%u\n",
tcp_getsequence(conn->sndseq), conn->tx_unacked, unackseq,
ackseq);
nwarn("sndseq=%u tx_unacked=%u unackseq=%u ackseq=%u\n",
tcp_getsequence(conn->sndseq), conn->tx_unacked,
unackseq, ackseq);
conn->tx_unacked = 0;
}
@ -522,7 +522,7 @@ found:
*/
ninfo("sndseq: %08x->%08x unackseq: %08x new tx_unacked: %d\n",
tcp_getsequence(conn->sndseq), ackseq, unackseq, conn->tx_unacked);
tcp_getsequence(conn->sndseq), ackseq, unackseq, conn->tx_unacked);
tcp_setsequence(conn->sndseq, ackseq);
/* Do RTT estimation, unless we have done retransmissions. */
@ -748,8 +748,8 @@ found:
*
* If the incoming packet is a FIN, we should close the connection on
* this side as well, and we send out a FIN and enter the LAST_ACK
* state. We require that there is no outstanding data; otherwise the
* sequence numbers will be screwed up.
* state. We require that there is no outstanding data; otherwise
* the sequence numbers will be screwed up.
*/
if ((tcp->flags & TCP_FIN) != 0 &&
@ -757,8 +757,8 @@ found:
{
/* Needs to be investigated further.
* Windows often sends FIN packets together with the last ACK for
* the received data. So the socket layer has to get this ACK even
* if the connection is going to be closed.
* the received data. So the socket layer has to get this ACK
* even if the connection is going to be closed.
*/
#if 0
@ -768,8 +768,8 @@ found:
}
#endif
/* Update the sequence number and indicate that the connection has
* been closed.
/* Update the sequence number and indicate that the connection
* has been closed.
*/
net_incr32(conn->rcvseq, dev->d_len + 1);

7
net/tcp/tcp_timer.c
View file

@ -423,8 +423,7 @@ void tcp_timer(FAR struct net_driver_s *dev, FAR struct tcp_conn_s *conn,
unsigned int tcpiplen;
/* No.. we need to send another probe.
*
* Get the size of the IP header and the TCP header.
* Get the size of the IP and TCP header.
*/
#ifdef CONFIG_NET_IPv4
@ -465,8 +464,8 @@ void tcp_timer(FAR struct net_driver_s *dev, FAR struct tcp_conn_s *conn,
tcp_setsequence(conn->sndseq, saveseq);
/* Increment the number of un-ACKed bytes due to the
* dummy byte that we just sent.
/* Increment the number of un-ACKed bytes due to
* the dummy byte that we just sent.
*/
conn->tx_unacked++;

3
sched/clock/clock.c
View file

@ -56,7 +56,8 @@
* implementation-defined era related only to the process invocation.
*
* To determine the time in seconds, the value returned by clock() should
* be divided by the value of the macro CLOCKS_PER_SEC as defined in <time.h>.
* be divided by the value of the macro CLOCKS_PER_SEC as defined in
* <time.h>.
*
* NOTE: The current implementation does NOT return the processor time
* used by the process. NuttX currently does not keep any record of

4
sched/clock/clock_systimer.c
View file

@ -101,7 +101,7 @@ clock_t clock_systimer(void)
/* Convert to a 64-bit value in microseconds, then in clock tick units */
return USEC2TICK(1000000 * (uint64_t)ts.tv_sec + (uint64_t)ts.tv_nsec / 1000);
return USEC2TICK(1000000 * (uint64_t)ts.tv_sec + ts.tv_nsec / 1000);
# else /* CONFIG_SYSTEM_TIME64 */
@ -114,7 +114,7 @@ clock_t clock_systimer(void)
/* Convert to a 64- then a 32-bit value */
tmp = USEC2TICK(1000000 * (uint64_t)ts.tv_sec + (uint64_t)ts.tv_nsec / 1000);
tmp = USEC2TICK(1000000 * (uint64_t)ts.tv_sec + ts.tv_nsec / 1000);
return (clock_t)(tmp & TIMER_MASK32);
# endif /* CONFIG_SYSTEM_TIME64 */

4
sched/irq/irq_attach.c
View file

@ -94,9 +94,9 @@ int irq_attach(int irq, xcpt_t isr, FAR void *arg)
/* Disable the interrupt if we can before detaching it. We might
* not be able to do this if: (1) the device does not have a
* centralized interrupt controller (so up_disable_irq() is not
* supported). Or (2) if the device has different number for vector
* supported). Or (2) if the device has different number for vector
* numbers and IRQ numbers (in that case, we don't know the correct
* IRQ number to use to disable the interrupt). In those cases, the
* IRQ number to use to disable the interrupt). In those cases, the
* code will just need to be careful that it disables all interrupt
* sources before detaching from the interrupt vector.
*/

121
wireless/ieee802154/mac802154.c
View file

@ -75,9 +75,9 @@ static void mac802154_resetqueues(FAR struct ieee802154_privmac_s *priv);
/* IEEE 802.15.4 PHY Interface OPs */
static int mac802154_radiopoll(FAR const struct ieee802154_radiocb_s *radiocb,
bool gts,
FAR struct ieee802154_txdesc_s **tx_desc);
static int
mac802154_radiopoll(FAR const struct ieee802154_radiocb_s *radiocb,
bool gts, FAR struct ieee802154_txdesc_s **tx_desc);
static void mac802154_txdone(FAR const struct ieee802154_radiocb_s *radiocb,
FAR struct ieee802154_txdesc_s *tx_desc);
@ -87,8 +87,9 @@ static void mac802154_rxframe(FAR const struct ieee802154_radiocb_s *radiocb,
FAR struct ieee802154_data_ind_s *ind);
static void mac802154_rxframe_worker(FAR void *arg);
static void mac802154_edresult(FAR const struct ieee802154_radiocb_s *radiocb,
uint8_t edval);
static void
mac802154_edresult(FAR const struct ieee802154_radiocb_s *radiocb,
uint8_t edval);
static void mac802154_sfevent(FAR const struct ieee802154_radiocb_s *radiocb,
enum ieee802154_sfevent_e sfevent);
@ -144,9 +145,9 @@ static void mac802154_resetqueues(FAR struct ieee802154_privmac_s *priv)
* Name: mac802154_txdesc_pool
*
* Description:
* This function allocates a tx descriptor and the dependent primitive (data
* confirmation) from the free list. The primitive and tx descriptor must be
* freed separately.
* This function allocates a tx descriptor and the dependent primitive
* (data confirmation) from the free list. The primitive and tx descriptor
* must be freed separately.
*
* Assumptions:
* priv MAC struct is locked when calling.
@ -166,9 +167,9 @@ int mac802154_txdesc_alloc(FAR struct ieee802154_privmac_s *priv,
FAR struct ieee802154_primitive_s *primitive;
/* Try and take a count from the semaphore. If this succeeds, we have
* "reserved" the structure, but still need to unlink it from the free list.
* The MAC is already locked, so there shouldn't be any other conflicting
* calls.
* "reserved" the structure, but still need to unlink it from the free
* list. The MAC is already locked, so there shouldn't be any other
* conflicting calls.
*/
ret = nxsem_trywait(&priv->txdesc_sem);
@ -211,7 +212,7 @@ int mac802154_txdesc_alloc(FAR struct ieee802154_privmac_s *priv,
return ret;
}
/* We can now safely unlink the next free structure from the free list */
/* We can now safely unlink the next structure from the free list */
*txdesc =
(FAR struct ieee802154_txdesc_s *)sq_remfirst(&priv->txdesc_queue);
@ -237,8 +238,8 @@ int mac802154_txdesc_alloc(FAR struct ieee802154_privmac_s *priv,
*
* Description:
* Internal function used by various parts of the MAC layer. This function
* allocates an IOB, populates the frame according to input args, and links
* the IOB into the provided tx descriptor.
* allocates an IOB, populates the frame according to input args, and
* links the IOB into the provided tx descriptor.
*
* Assumptions:
* Called with the MAC locked
@ -489,11 +490,11 @@ static void mac802154_notify_worker(FAR void *arg)
* that effect the beacon are updated.
*
* Internal function used by various parts of the MAC layer. This function
* uses the various MAC attributes to update the beacon frame. It loads the
* inactive beacon frame structure and then notifies the radio layer of the
* uses the various MAC attributes to update the beacon frame. It loads
* the inactive beacon frame structure and then notifies the radio layer
* new frame. the provided tx descriptor in the indirect list and manages
* the scheduling for purging the transaction if it does not get extracted
* in time.
* of the the scheduling for purging the transaction if it does not get
* extracted in time.
*
* Assumptions:
* Called with the MAC locked
@ -632,8 +633,8 @@ void mac802154_updatebeacon(FAR struct ieee802154_privmac_s *priv)
sq_next((FAR sq_entry_t *)txdesc);
}
/* At this point, we know how many of each transaction we have, we can setup
* the Pending Address Specification field
/* At this point, we know how many of each transaction we have, we can
* setup the Pending Address Specification field
*/
beacon->bf_data[pendaddrspec_ind] =
@ -675,10 +676,10 @@ void mac802154_setupindirect(FAR struct ieee802154_privmac_s *priv,
/* Update the timestamp for purging the transaction */
/* The maximum time (in unit periods) that a transaction is stored by a
* coordinator and indicated in its beacon. The unit period is governed by
* macBeaconOrder, BO, as follows: For 0 ≤ BO ≤ 14, the unit period will
* be aBaseSuperframeDuration × 2 BO . For BO = 15, the unit period will
* be aBaseSuperframeDuration. [1] pg. 129
* coordinator and indicated in its beacon. The unit period is governed
* by macBeaconOrder, BO, as follows: For 0 ≤ BO ≤ 14, the unit period
* will be aBaseSuperframeDuration × 2 BO . For BO = 15, the unit period
* will be aBaseSuperframeDuration. [1] pg. 129
*/
if (priv->sfspec.beaconorder < 15)
@ -689,7 +690,8 @@ void mac802154_setupindirect(FAR struct ieee802154_privmac_s *priv,
}
else
{
symbols = priv->trans_persisttime * IEEE802154_BASE_SUPERFRAME_DURATION;
symbols = priv->trans_persisttime *
IEEE802154_BASE_SUPERFRAME_DURATION;
}
ticks = mac802154_symtoticks(priv, symbols);
@ -703,9 +705,10 @@ void mac802154_setupindirect(FAR struct ieee802154_privmac_s *priv,
priv->beaconupdate = true;
}
/* Check to see if the purge indirect timer is scheduled. If it is, when the
* timer fires, it will schedule the next purge timer event. Inherently, the
* queue will be in order of which transaction needs to be purged next.
/* Check to see if the purge indirect timer is scheduled. If it is, when
* the timer fires, it will schedule the next purge timer event.
* Inherently, the queue will be in order of which transaction needs to
* be purged next.
*
* If the purge indirect timer has not been scheduled, schedule it for when
* this transaction should expire.
@ -812,7 +815,7 @@ static int
DEBUGASSERT(cb != NULL && cb->priv != NULL);
priv = cb->priv;
/* Get exclusive access to the driver structure. Ignore any EINTR signals */
/* Get exclusive access to the driver structure. Ignore EINTR signals */
mac802154_lock(priv, false);
@ -889,7 +892,7 @@ static void mac802154_txdone(FAR const struct ieee802154_radiocb_s *radiocb,
*
* Description:
* Worker function scheduled from mac802154_txdone. This function pops any
* TX descriptors off of the list and calls the next highest layers callback
* TX descriptors off of the list and calls the next highest layer callback
* to inform the layer of the completed transaction and the status of it.
*
****************************************************************************/
@ -953,11 +956,11 @@ static void mac802154_txdone_worker(FAR void *arg)
/* Data requests can be sent for 3 different reasons.
*
* 1. On a beacon-enabled PAN, this command shall be sent
* by a device when macAutoRequest is equal to TRUE and
* a beacon frame indicating that data are pending for
* that device is received from its coordinator.
* 2. when instructed to do so by the next higher layer on
* reception of the MLME-POLL.request primitive.
* by a device when macAutoRequest is equal to TRUE
* and a beacon frame indicating that data are pending
* for that device is received from its coordinator.
* 2. when instructed to do so by the next higher layer
* on reception of the MLME-POLL.request primitive.
* 3. a device may send this command to the coordinator
* macResponseWaitTime after the acknowledgment to an
* association request command.
@ -1101,7 +1104,7 @@ static void mac802154_rxframe_worker(FAR void *arg)
ind = (FAR struct ieee802154_data_ind_s *)
sq_remfirst(&priv->dataind_queue);
/* Once we pop off the indication, we don't need to keep the mac locked */
/* Once we pop off the indication, we needn't to keep the mac locked */
mac802154_unlock(priv)
@ -1440,7 +1443,8 @@ static void mac802154_rxdataframe(FAR struct ieee802154_privmac_s *priv,
}
else
{
ieee802154_primitive_free((FAR struct ieee802154_primitive_s *)ind);
ieee802154_primitive_free(
(FAR struct ieee802154_primitive_s *)ind);
}
}
else
@ -1489,7 +1493,8 @@ static void mac802154_rxdatareq(FAR struct ieee802154_privmac_s *priv,
{
if (txdesc->destaddr.mode == IEEE802154_ADDRMODE_SHORT)
{
if (IEEE802154_SADDRCMP(txdesc->destaddr.saddr, ind->src.saddr))
if (IEEE802154_SADDRCMP(txdesc->destaddr.saddr,
ind->src.saddr))
{
/* Remove the transaction from the queue */
@ -1514,7 +1519,8 @@ static void mac802154_rxdatareq(FAR struct ieee802154_privmac_s *priv,
}
else if (txdesc->destaddr.mode == IEEE802154_ADDRMODE_EXTENDED)
{
if (IEEE802154_EADDRCMP(txdesc->destaddr.eaddr, ind->src.eaddr))
if (IEEE802154_EADDRCMP(txdesc->destaddr.eaddr,
ind->src.eaddr))
{
/* Remove the transaction from the queue */
@ -1599,7 +1605,7 @@ static void mac802154_rxdatareq(FAR struct ieee802154_privmac_s *priv,
*frame_ctrl |= (ind->src.mode << IEEE802154_FRAMECTRL_SHIFT_DADDR);
/* Check if the source PAN ID of the incoming request is the same as ours. */
/* Check the source PAN ID of the incoming request is the same as ours. */
if (IEEE802154_PANIDCMP(ind->src.panid, priv->addr.panid))
{
@ -1644,15 +1650,16 @@ static void mac802154_rxdatareq(FAR struct ieee802154_privmac_s *priv,
* Name: mac802154_edresult
*
* Description:
* Called from the radio driver through the callback struct. This
* function is called when the radio has finished an energy detect operation.
* This is triggered by a SCAN.request primitive with ScanType set to Energy
* Called from the radio driver through the callback struct. This function
* is called when the radio has finished an energy detect operation. This
* is triggered by a SCAN.request primitive with ScanType set to Energy
* Detect (ED)
*
****************************************************************************/
static void mac802154_edresult(FAR const struct ieee802154_radiocb_s *radiocb,
uint8_t edval)
static void
mac802154_edresult(FAR const struct ieee802154_radiocb_s *radiocb,
uint8_t edval)
{
FAR struct mac802154_radiocb_s *cb =
(FAR struct mac802154_radiocb_s *)radiocb;
@ -1667,7 +1674,7 @@ static void mac802154_edresult(FAR const struct ieee802154_radiocb_s *radiocb,
mac802154_lock(priv, false);
/* If we are actively performing a scan operation, notify the scan handler */
/* If we are actively performing a scan operation, notify the handler */
if (priv->curr_op == MAC802154_OP_SCAN)
{
@ -1746,8 +1753,8 @@ static void mac802154_rxbeaconframe(FAR struct ieee802154_privmac_s *priv,
bool pending_eaddr = false;
int i;
/* Even though we may not use the primitive, we allocate one to hold all the
* parsed beacon information. Freeing the primitive is quick, so it's worth
/* Even though we may not use the primitive, we allocate one to hold all
* the parsed beacon information. Freeing the primitive is quick, so it's
* worth saving a copy (If you were to parse all the info in locally, you
* would have to copy the data over in the case that you actually need to
* notify the next highest layer)
@ -1809,7 +1816,7 @@ static void mac802154_rxbeaconframe(FAR struct ieee802154_privmac_s *priv,
IEEE802154_GETGTSPERMIT(iob->io_data, iob->io_offset);
iob->io_offset++;
/* If there are any GTS descriptors, handle the GTS Dir and GTS List fields */
/* If there are any GTS descriptors, handle the GTS Dir and List fields */
if (ngtsdesc > 0)
{
@ -1876,6 +1883,7 @@ static void mac802154_rxbeaconframe(FAR struct ieee802154_privmac_s *priv,
/* Wait to actually decide how to handle this until we parse
* the rest of the frame
*/
wlinfo("Data pending for us in coord\n");
pending_saddr = true;
}
@ -1897,12 +1905,13 @@ static void mac802154_rxbeaconframe(FAR struct ieee802154_privmac_s *priv,
/* Wait to actually decide how to handle this until we parse
* the rest of the frame
*/
wlinfo("Data pending for us in coord\n");
pending_eaddr = true;
}
}
/* If there is anything left in the frame, process it as the beacon payload */
/* If there is anything left, process it as the beacon payload */
beacon->payloadlength = iob->io_len - iob->io_offset;
@ -1912,7 +1921,7 @@ static void mac802154_rxbeaconframe(FAR struct ieee802154_privmac_s *priv,
beacon->payloadlength);
}
/* At this point, we have extracted all relevant info from the incoming frame */
/* At this point, all relevant info is extracted from the incoming frame */
mac802154_lock(priv, false);
@ -1968,7 +1977,7 @@ static void mac802154_rxbeaconframe(FAR struct ieee802154_privmac_s *priv,
else
{
/* Check the superframe structure and update the appropriate attributes. */
/* Check superframe structure and update the appropriate attributes. */
if (memcmp(&priv->sfspec, &beacon->pandesc.sfspec,
sizeof(struct ieee802154_superframespec_s)) != 0)
@ -1985,8 +1994,8 @@ static void mac802154_rxbeaconframe(FAR struct ieee802154_privmac_s *priv,
/* If we are performing an association and there is data pending for us
* we ignore the autoRequest logic and just extract it. We also don't
* send a BEACON-NOTFIY.indication in this case, not sure if that
* is the right thing to do, can't find anything definitive in standard.
* send a BEACON-NOTFIY.indication in this case, not sure if that is
* the right thing to do, can't find anything definitive in standard.
*/
if (priv->curr_op == MAC802154_OP_ASSOC && pending_eaddr)
@ -2010,8 +2019,8 @@ static void mac802154_rxbeaconframe(FAR struct ieee802154_privmac_s *priv,
{
/* If a beacon frame is received and macAutoRequest is set to
* TRUE, the MLME shall first issue the MLME-
* BEACON-NOTIFY.indication primitive if the beacon contains any
* payload.
* BEACON-NOTIFY.indication primitive if the beacon contains
* any payload.
*/
if (beacon->payloadlength > 0)