forked from nuttx/nuttx-update
Squashed commit of the following:
A few bugfixes in initial testing on the i.MX6. Behavior seems a little more stable, but there are still memory corruption issues. Also print CPU number on assertion.
Add a file missed in the last big commit.
arch/arm/src/armv7a and imx6: Add support for per-CPU IRQ and FIQ interrupt stacks (bugfix). Add support so that up_assert will print the correct interrupt stack on an assertion (FIQ stack is still not printed).
arch/arm/src/lc823450: Combine the content of smp_macros.h into chip.h. Add support so that up_assert will print the correct interrupt stack on an assertion.
This commit is contained in:
Gregory Nutt
parent
bee8ed3289
commit
bb88f8d0bb
15 changed files with 598 additions and 123 deletions
11
TODO
11
TODO
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@ -1,4 +1,4 @@
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NuttX TODO List (Last updated June 20, 2018)
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NuttX TODO List (Last updated June 21, 2018)
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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This file summarizes known NuttX bugs, limitations, inconsistencies with
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@ -10,7 +10,7 @@ issues related to each board port.
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nuttx/:
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(15) Task/Scheduler (sched/)
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(4) SMP
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(3) SMP
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(1) Memory Management (mm/)
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(0) Power Management (drivers/pm)
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(3) Signals (sched/signal, arch/)
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@ -482,13 +482,6 @@ o SMP
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simplification in the design and permit commonality with
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other, non-GIC imoplementations.
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Title: BAD INTERRUPTSTACK LOGIC FOR ARMv7-A IN SMP CONFIGURATION
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Description: The handler at arch/arm/src/armv7-a/arm_vectors.S supports
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only a single interrupt stack. In SMP mode, that same
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interrupt stack is used for all CPUs. That cannot work.
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Status: Open
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Priority: High
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o Memory Management (mm/)
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^^^^^^^^^^^^^^^^^^^^^^^
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@ -36,28 +36,28 @@
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#ifndef __ARCH_ARM_SRC_A1X_CHIP_H
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#define __ARCH_ARM_SRC_A1X_CHIP_H
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/************************************************************************************
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/*****************************************************************************
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* Included Files
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************************************************************************************/
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****************************************************************************/
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#include <nuttx/config.h>
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#include "chip/a1x_memorymap.h"
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/************************************************************************************
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/****************************************************************************
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* Pre-processor Definitions
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************************************************************************************/
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****************************************************************************/
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/************************************************************************************
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/****************************************************************************
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* Public Types
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************************************************************************************/
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****************************************************************************/
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/************************************************************************************
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/****************************************************************************
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* Public Data
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************************************************************************************/
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****************************************************************************/
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/************************************************************************************
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/****************************************************************************
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* Public Functions
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************************************************************************************/
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****************************************************************************/
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#endif /* __ARCH_ARM_SRC_A1X_CHIP_H */
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@ -52,14 +52,17 @@
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#include <arch/board/board.h>
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#include "up_arch.h"
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#include "sched/sched.h"
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#include "irq/irq.h"
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#include "up_arch.h"
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#include "up_internal.h"
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#include "chip.h"
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* USB trace dumping */
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#ifndef CONFIG_USBDEV_TRACE
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@ -210,7 +213,7 @@ static void up_dumpstate(void)
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uint32_t sp = up_getsp();
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uint32_t ustackbase;
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uint32_t ustacksize;
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#if CONFIG_ARCH_INTERRUPTSTACK > 3
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#if CONFIG_ARCH_INTERRUPTSTACK > 7
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uint32_t istackbase;
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uint32_t istacksize;
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#endif
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@ -233,11 +236,15 @@ static void up_dumpstate(void)
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_alert("Current sp: %08x\n", sp);
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#if CONFIG_ARCH_INTERRUPTSTACK > 3
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#if CONFIG_ARCH_INTERRUPTSTACK > 7
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/* Get the limits on the interrupt stack memory */
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#ifdef CONFIG_SMP
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istackbase = (uint32_t)up_intstack_base();
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#else
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istackbase = (uint32_t)&g_intstackbase;
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istacksize = (CONFIG_ARCH_INTERRUPTSTACK & ~3);
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#endif
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istacksize = (CONFIG_ARCH_INTERRUPTSTACK & ~7);
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/* Show interrupt stack info */
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@ -271,11 +278,13 @@ static void up_dumpstate(void)
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}
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#endif
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#if CONFIG_ARCH_INTERRUPTSTACK > 3
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#if CONFIG_ARCH_INTERRUPTSTACK > 7
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/* Does the current stack pointer lie within the interrupt stack? */
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if (sp > istackbase - istacksize && sp < istackbase)
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{
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uint32_t *stackbase;
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/* Yes.. dump the interrupt stack */
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_alert("Interrupt Stack\n", sp);
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@ -285,7 +294,12 @@ static void up_dumpstate(void)
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* at the base of the interrupt stack.
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*/
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sp = g_intstackbase;
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#ifdef CONFIG_SMP
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stackbase = (uint32_t *)up_intstack_base();
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#else
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stackbase = (uint32_t *)&g_intstackbase;
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#endif
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sp = *stackbase;
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_alert("User sp: %08x\n", sp);
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}
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#endif
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@ -399,12 +413,22 @@ void up_assert(const uint8_t *filename, int lineno)
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(void)syslog_flush();
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#ifdef CONFIG_SMP
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#if CONFIG_TASK_NAME_SIZE > 0
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_alert("Assertion failed CPU%d at file:%s line: %d task: %s\n",
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up_cpu_index(), filename, lineno, rtcb->name);
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#else
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_alert("Assertion failed CPU%d at file:%s line: %d\n",
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up_cpu_index(), filename, lineno);
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#endif
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#else
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#if CONFIG_TASK_NAME_SIZE > 0
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_alert("Assertion failed at file:%s line: %d task: %s\n",
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filename, lineno, rtcb->name);
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#else
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_alert("Assertion failed at file:%s line: %d\n",
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filename, lineno);
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#endif
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#endif
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up_dumpstate();
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@ -1,7 +1,7 @@
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/************************************************************************************
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* arch/arm/src/armv7-a/arm_vectors.S
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*
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* Copyright (C) 2013-2014 Gregory Nutt. All rights reserved.
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* Copyright (C) 2013-2014, 2018 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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@ -42,6 +42,7 @@
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#include "arm.h"
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#include "cp15.h"
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#include "chip.h"
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.file "arm_vectors.S"
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@ -53,22 +54,83 @@
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g_irqtmp:
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.word 0 /* Saved lr */
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.word 0 /* Saved spsr */
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g_undeftmp:
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.word 0 /* Saved lr */
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.word 0 /* Saved spsr */
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g_aborttmp:
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.word 0 /* Saved lr */
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.word 0 /* Saved spsr */
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#ifdef CONFIG_ARMV7A_DECODEFIQ
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g_fiqtmp:
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.word 0 /* Saved lr */
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.word 0 /* Saved spsr */
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#endif
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#if CONFIG_ARCH_INTERRUPTSTACK > 3 && defined(CONFIG_ARMV7A_HAVE_GICv2)
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#if CONFIG_ARCH_INTERRUPTSTACK > 7 && defined(CONFIG_ARMV7A_HAVE_GICv2)
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g_nestlevel:
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#ifdef CONFIG_SMP
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.rept CONFIG_SMP_NCPUS
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.word 0 /* CPUn Interrupt nesting level */
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.endr
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#else
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.word 0 /* Interrupt nesting level */
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#endif
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#endif /* CONFIG_ARCH_INTERRUPTSTACK > 7 && CONFIG_ARMV7A_HAVE_GICv2 */
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/************************************************************************************
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* Macro Definitions
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************************************************************************************/
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/************************************************************************************
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* Name: cpuindex
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*
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* Description:
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* Return an index idenifying the current CPU. Single CPU case. Must be
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* provided by MCU-specific logic in chip.h for the SMP case.
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*
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************************************************************************************/
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#if !defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 7
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.macro cpuindex, index
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.mov \index, #0
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.endm
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#endif
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/************************************************************************************
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* Name: setirqstack
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*
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* Description:
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* Set the current stack pointer to the "top" of the IRQ interrupt stack. Single
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* CPU case. Must be provided by MCU-specific logic in chip.h for the SMP case.
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*
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************************************************************************************/
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#if !defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 7
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.macro setirqstack, tmp1, tmp2
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ldr sp, .Lirqstackbase /* SP = IRQ stack top */
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.endm
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#endif
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/************************************************************************************
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* Name: setfiqstack
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*
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* Description:
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* Set the current stack pointer to the "top" of the FIQ interrupt stack. Single
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* CPU case. Must be provided by MCU-specific logic in chip.h for the SMP case.
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*
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************************************************************************************/
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#if !defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 7
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.macro setfiqstack, tmp1, tmp2
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ldr sp, .Lfiqstackbase /* SP = FIQ stack top */
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.endm
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#endif
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/************************************************************************************
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* Private Functions
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************************************************************************************/
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@ -175,14 +237,19 @@ arm_vectorirq:
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mov fp, #0 /* Init frame pointer */
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mov r0, sp /* Get r0=xcp */
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#if CONFIG_ARCH_INTERRUPTSTACK > 3
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#if CONFIG_ARCH_INTERRUPTSTACK > 7
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#ifdef CONFIG_ARMV7A_HAVE_GICv2
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/* We will switch to the interrupt stack, UNLESS we are processing a
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* nested interrupt in which case we are already using the interrupt
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* stack. SGI interrupts may be nested because they are non-maskable.
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*/
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ldr r5, .Lirqnestlevel /* r1=Points to interrupt nesting level */
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ldr r5, .Lirqnestlevel /* r5=Points to interrupt nesting level */
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#ifdef CONFIG_SMP
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cpuindex r1 /* r1=cpu index */
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lsls r1, r1, #2 /* r1=array byte offset */
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add r5, r5, r1 /* Indexed interrupt nesting level */
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#endif
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ldr r1, [r5] /* Get r1= nesting level */
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add r1, r1, #1 /* Increment nesting level */
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str r1, [r5] /* Save r1= nesting level */
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/* Call arm_decodeirq() on the interrupt stack */
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ldr sp, .Lirqstackbase /* SP = interrupt stack base */
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setirqstack r1, r5 /* SP = IRQ stack top */
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str r0, [sp] /* Save the user stack pointer */
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mov r4, sp /* Save the SP in a preserved register */
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bic sp, sp, #7 /* Force 8-byte alignment */
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@ -268,14 +335,19 @@ arm_vectorirq:
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.Lirqtmp:
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.word g_irqtmp
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#if CONFIG_ARCH_INTERRUPTSTACK > 3
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#if CONFIG_ARCH_INTERRUPTSTACK > 7
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#ifndef CONFIG_SMP
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.Lirqstackbase:
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.word g_intstackbase
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#endif
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#ifdef CONFIG_ARMV7A_HAVE_GICv2
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.Lirqnestlevel:
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.word g_nestlevel
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#endif
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#endif
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#endif /* CONFIG_ARCH_INTERRUPTSTACK > 7 */
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.size arm_vectorirq, . - arm_vectorirq
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.align 5
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@ -930,8 +1002,8 @@ arm_vectorfiq:
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mov fp, #0 /* Init frame pointer */
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mov r0, sp /* Get r0=xcp */
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#if CONFIG_ARCH_INTERRUPTSTACK > 3
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ldr sp, .Lfiqstackbase /* SP = interrupt stack base */
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#if CONFIG_ARCH_INTERRUPTSTACK > 7
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setfiqstack r1, r4 /* SP = FIQ stack top */
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str r0, [sp] /* Save the user stack pointer */
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mov r4, sp /* Save the SP in a preserved register */
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bic sp, sp, #7 /* Force 8-byte alignment */
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@ -983,7 +1055,8 @@ arm_vectorfiq:
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.Lfiqtmp:
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.word g_fiqtmp
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#if CONFIG_ARCH_INTERRUPTSTACK > 3
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#if !defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 7
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.Lfiqstackbase:
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.word g_fiqstackbase
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#endif
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@ -997,7 +1070,7 @@ arm_vectorfiq:
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* Name: g_intstackalloc/g_intstackbase
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************************************************************************************/
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#if CONFIG_ARCH_INTERRUPTSTACK > 3
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#if !defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 7
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.bss
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.align 4
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@ -1007,27 +1080,27 @@ arm_vectorfiq:
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.type g_intstackbase, object
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g_intstackalloc:
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.skip ((CONFIG_ARCH_INTERRUPTSTACK & ~3) - 4)
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.skip ((CONFIG_ARCH_INTERRUPTSTACK & ~7) - 4)
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g_intstackbase:
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.skip 4
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.size g_intstackbase, 4
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.size g_intstackalloc, (CONFIG_ARCH_INTERRUPTSTACK & ~3)
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.size g_intstackalloc, (CONFIG_ARCH_INTERRUPTSTACK & ~7)
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/************************************************************************************
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* Name: g_fiqstackalloc/g_fiqstackbase
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************************************************************************************/
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.globl g_fiqstackalloc
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.type g_fiqstackalloc, object
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.globl g_fiqstackbase
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.type g_fiqstackbase, object
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/************************************************************************************
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* Name: g_fiqstackalloc/g_fiqstackbase
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************************************************************************************/
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g_fiqstackalloc:
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.skip ((CONFIG_ARCH_INTERRUPTSTACK & ~3) - 4)
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.skip ((CONFIG_ARCH_INTERRUPTSTACK & ~7) - 4)
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g_fiqstackbase:
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.skip 4
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.size g_fiqstackbase, 4
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.size g_fiqstackalloc, (CONFIG_ARCH_INTERRUPTSTACK & ~3)
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.size g_fiqstackalloc, (CONFIG_ARCH_INTERRUPTSTACK & ~7)
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#endif /* CONFIG_ARCH_INTERRUPTSTACK > 3 */
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#endif /* !CONFIG_SMP && CONFIG_ARCH_INTERRUPTSTACK > 7 */
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.end
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@ -44,9 +44,6 @@
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#include "exc_return.h"
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#include "chip.h"
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#ifdef CONFIG_SMP
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# include "smp_macros.h"
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#endif
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/************************************************************************************
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* Pre-processor Definitions
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||||
|
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@ -96,8 +93,17 @@
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* Macro Definitions
|
||||
************************************************************************************/
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/************************************************************************************
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* Name: setintstack
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*
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* Description:
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* Set the current stack pointer to the "top" the interrupt stack. Single CPU
|
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* case. Must be provided by MCU-specific logic in the SMP case.
|
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*
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************************************************************************************/
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#if !defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 7
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.macro setintstack, tmp
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.macro setintstack, tmp1, tmp2
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ldr sp, =g_intstackbase
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.endm
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#endif
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@ -206,7 +212,7 @@ exception_common:
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* here prohibits nested interrupts without some additional logic!
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*/
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setintstack r2
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setintstack r2, r3
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#else
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/* Otherwise, we will re-use the interrupted thread's stack. That may
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|
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@ -43,13 +43,11 @@
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#include "exc_return.h"
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#include "chip.h"
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#ifdef CONFIG_SMP
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# include "smp_macros.h"
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#endif
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/************************************************************************************************
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||||
* Pre-processor Definitions
|
||||
************************************************************************************************/
|
||||
|
||||
/* Configuration ********************************************************************************/
|
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|
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#ifdef CONFIG_ARCH_HIPRI_INTERRUPT
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|
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@ -93,8 +91,17 @@
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* Macro Definitions
|
||||
************************************************************************************************/
|
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|
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/************************************************************************************************
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* Name: setintstack
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*
|
||||
* Description:
|
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* Set the current stack pointer to the "top" the interrupt stack. Single CPU case. Must be
|
||||
* provided by MCU-specific logic in chip.h for the SMP case.
|
||||
*
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||||
************************************************************************************************/
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#if !defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 7
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.macro setintstack, tmp
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.macro setintstack, tmp1, tmp2
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ldr sp, =g_intstackbase
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.endm
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#endif
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@ -214,7 +221,7 @@ exception_common:
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* here prohibits nested interrupts without some additional logic!
|
||||
*/
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setintstack r2
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setintstack r2, r3
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|
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#else
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/* Otherwise, we will re-use the interrupted thread's stack. That may
|
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|
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|
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|
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@ -53,10 +53,12 @@
|
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|
||||
#include <arch/board/board.h>
|
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|
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#include "up_arch.h"
|
||||
#include "sched/sched.h"
|
||||
#include "irq/irq.h"
|
||||
|
||||
#include "up_arch.h"
|
||||
#include "up_internal.h"
|
||||
#include "chip.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
|
|
@ -224,7 +226,7 @@ static void up_dumpstate(void)
|
|||
uint32_t sp = up_getsp();
|
||||
uint32_t ustackbase;
|
||||
uint32_t ustacksize;
|
||||
#if CONFIG_ARCH_INTERRUPTSTACK > 3
|
||||
#if CONFIG_ARCH_INTERRUPTSTACK > 7
|
||||
uint32_t istackbase;
|
||||
uint32_t istacksize;
|
||||
#endif
|
||||
|
|
@ -242,11 +244,15 @@ static void up_dumpstate(void)
|
|||
ustacksize = (uint32_t)rtcb->adj_stack_size;
|
||||
}
|
||||
|
||||
#if CONFIG_ARCH_INTERRUPTSTACK > 3
|
||||
#if CONFIG_ARCH_INTERRUPTSTACK > 7
|
||||
/* Get the limits on the interrupt stack memory */
|
||||
|
||||
#ifdef CONFIG_SMP
|
||||
istackbase = (uint32_t)up_intstack_base();
|
||||
#else
|
||||
istackbase = (uint32_t)&g_intstackbase;
|
||||
istacksize = (CONFIG_ARCH_INTERRUPTSTACK & ~3);
|
||||
#endif
|
||||
istacksize = (CONFIG_ARCH_INTERRUPTSTACK & ~7);
|
||||
|
||||
/* Show interrupt stack info */
|
||||
|
||||
|
|
@ -404,12 +410,22 @@ void up_assert(const uint8_t *filename, int lineno)
|
|||
|
||||
(void)syslog_flush();
|
||||
|
||||
#ifdef CONFIG_SMP
|
||||
#if CONFIG_TASK_NAME_SIZE > 0
|
||||
_alert("Assertion failed CPU%d at file:%s line: %d task: %s\n",
|
||||
up_cpu_index(), filename, lineno, rtcb->name);
|
||||
#else
|
||||
_alert("Assertion failed CPU%d at file:%s line: %d\n",
|
||||
up_cpu_index(), filename, lineno);
|
||||
#endif
|
||||
#else
|
||||
#if CONFIG_TASK_NAME_SIZE > 0
|
||||
_alert("Assertion failed at file:%s line: %d task: %s\n",
|
||||
filename, lineno, rtcb->name);
|
||||
#else
|
||||
_alert("Assertion failed at file:%s line: %d\n",
|
||||
filename, lineno);
|
||||
#endif
|
||||
#endif
|
||||
|
||||
up_dumpstate();
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
/****************************************************************************
|
||||
* arch/arm/src/imx6/chip.h
|
||||
*
|
||||
* Copyright (C) 2016 Gregory Nutt. All rights reserved.
|
||||
* Copyright (C) 2016, 2018 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
|
|
@ -41,7 +41,13 @@
|
|||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
# include <nuttx/arch.h>
|
||||
#endif
|
||||
|
||||
#include "chip/imx_memorymap.h"
|
||||
#include "imx_irq.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
|
|
@ -63,6 +69,125 @@
|
|||
* Public Data
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef __ASSEMBLY__
|
||||
|
||||
#if defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 7
|
||||
.globl g_irqstack_top
|
||||
.globl g_fiqstack_top
|
||||
#endif /* CONFIG_SMP && CONFIG_ARCH_INTERRUPTSTACK > 7 */
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
|
||||
/****************************************************************************
|
||||
* Macro Definitions
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef __ASSEMBLY__
|
||||
|
||||
/***************************************************************************
|
||||
* Name: cpuindex
|
||||
*
|
||||
* Description:
|
||||
* Return an index idenifying the current CPU.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#if defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 7
|
||||
.macro cpuindex, index
|
||||
mrc p15, 0, \index, c0, c0, 5 /* Read the MPIDR */
|
||||
and \index, \index, #3 /* Bits 0-1=CPU ID */
|
||||
.endm
|
||||
#endif
|
||||
|
||||
/***************************************************************************
|
||||
* Name: setirqstack
|
||||
*
|
||||
* Description:
|
||||
* Set the current stack pointer to the -"top" of the IRQ interrupt
|
||||
* stack for the current CPU.
|
||||
*
|
||||
***************************************************************************/
|
||||
|
||||
#if defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 7
|
||||
.macro setirqstack, tmp1, tmp2
|
||||
mrc p15, 0, \tmp1, c0, c0, 5 /* tmp1=MPIDR */
|
||||
and \tmp1, \tmp1, #3 /* Bits 0-1=CPU ID */
|
||||
ldr \tmp2, =g_irqstack_top /* tmp2=Array of IRQ stack pointers */
|
||||
lsls \tmp1, \tmp1, #2 /* tmp1=Array byte offset */
|
||||
add \tmp2, \tmp2, \tmp1 /* tmp2=Offset address into array */
|
||||
ldr sp, [\tmp2, #0] /* sp=Address in stack allocation */
|
||||
.endm
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Name: setfiqstack
|
||||
*
|
||||
* Description:
|
||||
* Set the current stack pointer to the -"top" of the FIQ interrupt
|
||||
* stack for the current CPU.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#if defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 7
|
||||
.macro setfiqstack, tmp1, tmp2
|
||||
mrc p15, 0, \tmp1, c0, c0, 5 /* tmp1=MPIDR */
|
||||
and \tmp1, \tmp1, #3 /* Bits 0-1=CPU ID */
|
||||
ldr \tmp2, =g_fiqstack_top /* tmp2=Array of FIQ stack pointers */
|
||||
lsls \tmp1, \tmp1, #2 /* tmp1=Array byte offset */
|
||||
add \tmp2, \tmp2, \tmp1 /* tmp2=Offset address into array */
|
||||
ldr sp, [\tmp2, #0] /* sp=Address in stack allocation */
|
||||
.endm
|
||||
#endif
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
|
||||
/****************************************************************************
|
||||
* Inline Functions
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
/****************************************************************************
|
||||
* Name: up_intstack_base
|
||||
*
|
||||
* Description:
|
||||
* Return a pointer to the "base" the correct interrupt stack for the
|
||||
* current CPU.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#if defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 7
|
||||
static inline uintptr_t up_intstack_base(void)
|
||||
{
|
||||
uintptr_t base = (uintptr_t)g_irqstack_alloc;
|
||||
#if CONFIG_SMP_NCPUS > 1
|
||||
uint32_t cpu = up_cpu_index();
|
||||
|
||||
base += cpu * INTSTACK_SIZE;
|
||||
#endif
|
||||
|
||||
return base;
|
||||
}
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Name: up_intstack_top
|
||||
*
|
||||
* Description:
|
||||
* Return a pointer to the "top" the correct interrupt stack for the
|
||||
* current CPU.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#if defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 7
|
||||
static inline uintptr_t up_intstack_top(void)
|
||||
{
|
||||
return up_intstack_base() + INTSTACK_SIZE;
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* !__ASSEMBLY__ */
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
/****************************************************************************
|
||||
* arch/arm/src/imx6/imx_irq.c
|
||||
*
|
||||
* Copyright (C) 2016 Gregory Nutt. All rights reserved.
|
||||
* Copyright (C) 2016, 2018 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
|
|
@ -46,6 +46,15 @@
|
|||
#include "up_internal.h"
|
||||
#include "sctlr.h"
|
||||
#include "gic.h"
|
||||
#include "imx_irq.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/* Size of the interrupt stack allocation */
|
||||
|
||||
#define INTSTACK_ALLOC (CONFIG_SMP_NCPUS * INTSTACK_SIZE)
|
||||
|
||||
/****************************************************************************
|
||||
* Public Data
|
||||
|
|
@ -67,6 +76,46 @@ volatile uint32_t *g_current_regs[CONFIG_SMP_NCPUS];
|
|||
volatile uint32_t *g_current_regs[1];
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 7
|
||||
/* In the SMP configuration, we will need custom IRQ and FIQ stacks.
|
||||
* These definitions provide the aligned stack allocations.
|
||||
*/
|
||||
|
||||
uint64_t g_irqstack_alloc[INTSTACK_ALLOC >> 3];
|
||||
uint64_t g_fiqstack_alloc[INTSTACK_ALLOC >> 3];
|
||||
|
||||
/* These are arrays that point to the top of each interrupt stack */
|
||||
|
||||
uintptr_t g_irqstack_top[CONFIG_SMP_NCPUS] =
|
||||
{
|
||||
(uintptr_t)g_irqstack_alloc + INTSTACK_SIZE,
|
||||
#if CONFIG_SMP_NCPUS > 1
|
||||
(uintptr_t)g_irqstack_alloc + 2 * INTSTACK_SIZE,
|
||||
#endif
|
||||
#if CONFIG_SMP_NCPUS > 2
|
||||
(uintptr_t)g_irqstack_alloc + 3 * INTSTACK_SIZE,
|
||||
#endif
|
||||
#if CONFIG_SMP_NCPUS > 3
|
||||
(uintptr_t)g_irqstack_alloc + 4 * INTSTACK_SIZE
|
||||
#endif
|
||||
};
|
||||
|
||||
uintptr_t g_fiqstack_top[CONFIG_SMP_NCPUS] =
|
||||
{
|
||||
(uintptr_t)g_fiqstack_alloc + INTSTACK_SIZE,
|
||||
#if CONFIG_SMP_NCPUS > 1
|
||||
(uintptr_t)g_fiqstack_alloc + 2 * INTSTACK_SIZE,
|
||||
#endif
|
||||
#if CONFIG_SMP_NCPUS > 2
|
||||
(uintptr_t)g_fiqstack_alloc + 3 * INTSTACK_SIZE,
|
||||
#endif
|
||||
#if CONFIG_SMP_NCPUS > 3
|
||||
(uintptr_t)g_fiqstack_alloc + 4 * INTSTACK_SIZE
|
||||
#endif
|
||||
};
|
||||
|
||||
#endif
|
||||
|
||||
/* Symbols defined via the linker script */
|
||||
|
||||
extern uint32_t _vector_start; /* Beginning of vector block */
|
||||
|
|
|
|||
95
arch/arm/src/imx6/imx_irq.h
Normal file
95
arch/arm/src/imx6/imx_irq.h
Normal file
|
|
@ -0,0 +1,95 @@
|
|||
/****************************************************************************
|
||||
* arch/arm/src/imx6/imx_irq.h
|
||||
*
|
||||
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_IMX6_IMX_IRQ_H
|
||||
#define __ARCH_ARM_SRC_IMX6_IMX_IRQ_H
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/* The size of one interrupt stack. This is the configured value aligned
|
||||
* the 8-bytes as required by the ARM EABI.
|
||||
*/
|
||||
|
||||
#define INTSTACK_SIZE (CONFIG_ARCH_INTERRUPTSTACK & ~7)
|
||||
|
||||
/****************************************************************************
|
||||
* Public Data
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
#define EXTERN extern "C"
|
||||
extern "C"
|
||||
{
|
||||
#else
|
||||
#define EXTERN extern
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 7
|
||||
/* In the SMP configuration, we will need custom IRQ and FIQ stacks.
|
||||
* These definitions provide the aligned stack allocations.
|
||||
*/
|
||||
|
||||
EXTERN uint64_t g_irqstack_alloc[];
|
||||
EXTERN uint64_t g_fiqstack_alloc[];
|
||||
|
||||
/* These are arrays that point to the top of each interrupt stack */
|
||||
|
||||
EXTERN uintptr_t g_irqstack_top[CONFIG_SMP_NCPUS];
|
||||
EXTERN uintptr_t g_irqstack_top[CONFIG_SMP_NCPUS];
|
||||
|
||||
#endif /* CONFIG_SMP && CONFIG_ARCH_INTERRUPTSTACK > 7 */
|
||||
|
||||
/****************************************************************************
|
||||
* Public Function Prototypes
|
||||
****************************************************************************/
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* __ARCH_ARM_SRC_IMX6_IMX_IRQ_H */
|
||||
|
|
@ -41,9 +41,12 @@
|
|||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <sys/types.h>
|
||||
#include <arch/lc823450/chip.h>
|
||||
#include <arch/lc823450/irq.h>
|
||||
#ifndef __ASSEMBLY__
|
||||
# include <sys/types.h>
|
||||
# include <arch/lc823450/chip.h>
|
||||
# include <arch/lc823450/irq.h>
|
||||
# include "lc823450_irq.h"
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
|
|
@ -56,16 +59,70 @@
|
|||
|
||||
#define ARMV7M_PERIPHERAL_INTERRUPTS LC823450_IRQ_NEXTINT
|
||||
|
||||
/* Access to COREID register */
|
||||
|
||||
#define LC823450_CORE_BASE 0xe00fe000
|
||||
#define CORE_COREID (LC823450_CORE_BASE + 0)
|
||||
#define CORE_COREID_ID (1 << 0)
|
||||
|
||||
/****************************************************************************
|
||||
* Public Types
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
/****************************************************************************
|
||||
* Public Data
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef __ASSEMBLY__
|
||||
|
||||
#if defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 7
|
||||
.globl g_instack_alloc
|
||||
#endif /* CONFIG_SMP && CONFIG_ARCH_INTERRUPTSTACK > 7 */
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
|
||||
/****************************************************************************
|
||||
* Macro Definitions
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef __ASSEMBLY__
|
||||
|
||||
/****************************************************************************
|
||||
* Name: setintstack
|
||||
*
|
||||
* Description:
|
||||
* Set the current stack pointer to the "top" the correct interrupt stack
|
||||
* for the current CPU.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#if defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 7
|
||||
.macro setintstack, tmp1, tmp2
|
||||
#if CONFIG_SMP_NCPUS > 1
|
||||
ldr \tmp1, =CORE_COREID
|
||||
ldr \tmp1, [\tmp1, 0] /* \tmp = getreg32(coreid_reg) */
|
||||
and \tmp1, \tmp1, 1 /* \tmp = COREID */
|
||||
cmp \tmp1, #0
|
||||
bne 1f
|
||||
ldr sp, =g_cpu0_instack_base
|
||||
b 2f
|
||||
1:
|
||||
ldr sp, =g_cpu1_instack_base
|
||||
2:
|
||||
#else
|
||||
ldr sp, =g_cpu0_instack_base
|
||||
#endif
|
||||
.endm
|
||||
#endif /* CONFIG_SMP && CONFIG_ARCH_INTERRUPTSTACK > 7 */
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
|
||||
/****************************************************************************
|
||||
* Inline Functions
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
#ifdef __cplusplus
|
||||
#define EXTERN extern "C"
|
||||
extern "C"
|
||||
|
|
@ -75,19 +132,40 @@ extern "C"
|
|||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Inline Functions
|
||||
* Name: up_intstack_base
|
||||
*
|
||||
* Description:
|
||||
* Set the current stack pointer to the "top" the correct interrupt stack
|
||||
* for the current CPU.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#if defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 7
|
||||
static inline uintptr_t up_intstack_base(void)
|
||||
{
|
||||
uintptr_t base = (uintptr_t)g_instack_alloc;
|
||||
#if CONFIG_SMP_NCPUS > 1
|
||||
uint32_t coreid = getreg32(CORE_COREID);
|
||||
|
||||
if ((coreid & CORE_COREID_ID) != 0)
|
||||
{
|
||||
base += INTSTACK_SIZE;
|
||||
}
|
||||
#endif
|
||||
|
||||
return base;
|
||||
}
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Public Function Prototypes
|
||||
****************************************************************************/
|
||||
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
#undef EXTERN
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* !__ASSEMBLY__ */
|
||||
|
||||
#endif /* _ARCH_ARM_SRC_LC823450_CHIP_H */
|
||||
|
|
|
|||
|
|
@ -80,20 +80,9 @@
|
|||
#define NVIC_ENA_OFFSET (0)
|
||||
#define NVIC_CLRENA_OFFSET (NVIC_IRQ0_31_CLEAR - NVIC_IRQ0_31_ENABLE)
|
||||
|
||||
/****************************************************************************
|
||||
* Private Data
|
||||
****************************************************************************/
|
||||
/* Size of the interrupt stack allocation */
|
||||
|
||||
#if defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 7
|
||||
/* In the SMP configuration, we will need two custom interrupt stacks.
|
||||
* These definitions provide the aligned stack allocations.
|
||||
*/
|
||||
|
||||
static uint64_t g_cpu0_instack_alloc[CONFIG_ARCH_INTERRUPTSTACK >> 3];
|
||||
#if CONFIG_SMP_NCPUS > 1
|
||||
static uint64_t g_cpu1_instack_alloc[CONFIG_ARCH_INTERRUPTSTACK >> 3];
|
||||
#endif
|
||||
#endif
|
||||
#define INTSTACK_ALLOC (CONFIG_SMP_NCPUS * INTSTACK_SIZE)
|
||||
|
||||
/****************************************************************************
|
||||
* Public Data
|
||||
|
|
@ -111,14 +100,19 @@ volatile uint32_t *g_current_regs[1];
|
|||
|
||||
#if defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 7
|
||||
/* In the SMP configuration, we will need two custom interrupt stacks.
|
||||
* These defintions provide the "top" of the push-down stacks.
|
||||
* These definitions provide the aligned stack allocations.
|
||||
*/
|
||||
|
||||
const uint32_t g_cpu0_instack_base = (uint32_t)g_cpu0_instack_alloc +
|
||||
sizeof(g_cpu0_instack_alloc);
|
||||
uint64_t g_instack_alloc[INTSTACK_ALLOC >> 3];
|
||||
|
||||
/* These definitions provide the "top" of the push-down stacks. */
|
||||
|
||||
const uint32_t g_cpu0_instack_base =
|
||||
(uint32_t)g_instack_alloc + INTSTACK_SIZE)
|
||||
|
||||
#if CONFIG_SMP_NCPUS > 1
|
||||
const uint32_t g_cpu1_instack_base = (uint32_t)g_cpu1_instack_alloc +
|
||||
sizeof(g_cpu1_instack_alloc);
|
||||
const uint32_t g_cpu1_instack_base =
|
||||
(uint32_t)g_instack_alloc + 2 * INTSTACK_SIZE)
|
||||
#endif
|
||||
#endif
|
||||
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/****************************************************************************
|
||||
* arch/arm/src/lc823450/smp_macros.h
|
||||
* arch/arm/src/lc823450/lc823450_irq.h
|
||||
*
|
||||
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
|
|
@ -33,8 +33,8 @@
|
|||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_LC823450_SMP_MACROS_H
|
||||
#define __ARCH_ARM_SRC_LC823450_SMP_MACROS_H
|
||||
#ifndef __ARCH_ARM_SRC_LC823450_LC823450_IRQ_H
|
||||
#define __ARCH_ARM_SRC_LC823450_LC823450_IRQ_H
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
|
|
@ -42,45 +42,55 @@
|
|||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#if defined(__ASSEMBLY__) && defined(CONFIG_SMP)
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
#define COREID_REG 0xe00fe000
|
||||
/* The size of one interrupt stack. This is the configured value aligned
|
||||
* the 8-bytes as required by the ARM EABI.
|
||||
*/
|
||||
|
||||
#define INTSTACK_SIZE (CONFIG_ARCH_INTERRUPTSTACK & ~7)
|
||||
|
||||
/****************************************************************************
|
||||
* Imported Public Data
|
||||
* Public Data
|
||||
****************************************************************************/
|
||||
|
||||
#if CONFIG_ARCH_INTERRUPTSTACK > 7
|
||||
.globl g_cpu0_instack_base
|
||||
.globl g_cpu1_instack_base
|
||||
#endif
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
/****************************************************************************
|
||||
* Macro Definitions
|
||||
****************************************************************************/
|
||||
|
||||
#if CONFIG_ARCH_INTERRUPTSTACK > 7
|
||||
.macro setintstack, tmp
|
||||
#if CONFIG_SMP_NCPUS > 1
|
||||
ldr \tmp, =COREID_REG
|
||||
ldr \tmp, [\tmp, 0] /* \tmp = getreg32(coreid_reg) */
|
||||
and \tmp, \tmp, 1 /* \tmp = COREID */
|
||||
cmp \tmp, #0
|
||||
bne 1f
|
||||
ldr sp, =g_cpu0_instack_base
|
||||
b 2f
|
||||
1:
|
||||
ldr sp, =g_cpu1_instack_base
|
||||
2:
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
#define EXTERN extern "C"
|
||||
extern "C"
|
||||
{
|
||||
#else
|
||||
ldr sp, =g_cpu0_instack_base
|
||||
#endif
|
||||
.endm
|
||||
#define EXTERN extern
|
||||
#endif
|
||||
|
||||
#endif /* __ASSEMBLY__ && CONFIG_SMP */
|
||||
#endif /* __ARCH_ARM_SRC_LC823450_SMP_MACROS_H */
|
||||
#if defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 7
|
||||
/* In the SMP configuration, we will need two custom interrupt stacks.
|
||||
* These definitions provide the aligned stack allocations.
|
||||
*/
|
||||
|
||||
EXTERN uint64_t g_instack_alloc[];
|
||||
|
||||
/* These definitions provide the "top" of the push-down stacks. */
|
||||
|
||||
EXTERN const uint32_t g_cpu0_instack_base;
|
||||
#if CONFIG_SMP_NCPUS > 1
|
||||
EXTERN const uint32_t g_cpu1_instack_base;
|
||||
#endif
|
||||
|
||||
#endif /* CONFIG_SMP && CONFIG_ARCH_INTERRUPTSTACK > 7 */
|
||||
|
||||
/****************************************************************************
|
||||
* Public Function Prototypes
|
||||
****************************************************************************/
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* __ARCH_ARM_SRC_LC823450_LC823450_IRQ_H */
|
||||
|
|
@ -1,7 +1,7 @@
|
|||
/************************************************************************************
|
||||
* arch/arm/src/sama5/chip.h
|
||||
*
|
||||
* Copyright (C) 2013-2014 Gregory Nutt. All rights reserved.
|
||||
* Copyright (C) 2013-2014, 2018 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
|
|
@ -41,7 +41,10 @@
|
|||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
#include <arch/sama5/chip.h>
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
# include <arch/sama5/chip.h>
|
||||
#endif
|
||||
|
||||
#include "chip/sam_memorymap.h"
|
||||
|
||||
|
|
|
|||
|
|
@ -165,7 +165,9 @@ Status
|
|||
|
||||
2018-06-20: There is a problem with the Interrupt Stack for SMP in
|
||||
arch/arm/src/armv7-a/arm_vectors.S: There is only one interrupt stack for
|
||||
all CPUs!
|
||||
all CPUs! A fix for this was put in place on 2018-06-21. Big Improvement!
|
||||
Bit this does not completely eliminate instabilities which seem to be
|
||||
related to memory corruption -- mm_mallinfo() asserts.
|
||||
|
||||
Platform Features
|
||||
=================
|
||||
|
|
|
|||
Loading…
Reference in a new issue