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arch/tricore: synchronize instruction/data following MTCR/MFCR

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Some barrier are necessary to avoid compiler optimizations

Signed-off-by: chao an <anchao@lixiang.com>
This commit is contained in:
chao an 2024-07-16 14:59:57 +08:00 committed by Xiang Xiao
parent 8f243d3eb7
commit bc7791e079
2 changed files with 15 additions and 1 deletions
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8
arch/tricore/src/common/tricore_csa.c
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@ -50,10 +50,18 @@ uintptr_t *tricore_alloc_csa(uintptr_t pc, uintptr_t sp,
plcsa = (uintptr_t *)tricore_csa2addr(__mfcr(CPU_FCX));
/* DSYNC instruction should be executed immediately prior to the MTCR */
__dsync();
pucsa = (uintptr_t *)tricore_csa2addr(plcsa[REG_UPCXI]);
__mtcr(CPU_FCX, pucsa[REG_UPCXI]);
/* ISYNC instruction executed immediately following MTCR */
__isync();
memset(pucsa, 0, XCPTCONTEXT_SIZE);
memset(plcsa, 0, XCPTCONTEXT_SIZE);

8
arch/tricore/src/common/tricore_svcall.c
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@ -57,7 +57,13 @@ void tricore_svcall(volatile void *trap)
uintptr_t *regs;
uint32_t cmd;
regs = tricore_csa2addr(__mfcr(CPU_PCXI));
regs = (uintptr_t *)__mfcr(CPU_PCXI);
/* DSYNC instruction should be executed immediately prior to the MTCR */
__dsync();
regs = tricore_csa2addr((uintptr_t)regs);
CURRENT_REGS = regs;