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and fix the wrong correction
This commit is contained in:
Xiang Xiao 2020-02-23 02:31:14 +08:00 committed by Gregory Nutt
parent a07ad7a115
commit bd4e8e19d3
526 changed files with 883 additions and 883 deletions
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4
.asf.yaml
View file

@ -2,9 +2,9 @@ github:
description: "Apache NuttX is a mature, real-time embedded operating system (RTOS)"
homepage: https://nuttx.apache.org/
features:
# Enable issues managment
# Enable issues management
issues: true
# Enable project for project managment boards
# Enable project for project management boards
projects: true
labels:
- nuttx

76
ChangeLog
View file

@ -475,7 +475,7 @@
* Add support for Intel Hex format output using objcopy
* Completed the basic port of the NXP LPC2148 on the mcu123.com board.
The basic port includes successful booting, timer interrupts, serial console,
succesfully passing the examples/ostest, and a NuttShell (NSH) configuration.
successfully passing the examples/ostest, and a NuttShell (NSH) configuration.
* ARM architectures now support drivers/lowconsole.c
0.3.16 2008-10-10 Gregory Nutt <gnutt@nuttx.org>
@ -2525,7 +2525,7 @@
* net/setsockopt.c, net/getsockopt.c, net/bind.c, net/socket.c: Add more
low level, thread-independent socket interfaces for use within the OS.
Some of these are currently used by the FTP controlling terminal. More will
be used to support the NFS file system currenly underwork.
be used to support the NFS file system currently underwork.
* include/nuttx/net/: Major re-organization of networking headerf files.
Moved all non-standard, NuttX-specific header files from include/net and
include/nuttx into include/nuttx/net.
@ -3197,7 +3197,7 @@
need to be used at path segments (Richard Cochran).
* arch/arm/src/stm32/stm32_usbotghost.c: The STM32 USB host driver only
works with debug turned on. The problem appears to be that with debug
OFF, there are more NAKs occuring in more places than before and this
OFF, there are more NAKs occurring in more places than before and this
reveals a variety of errors. This check in improves NAK robustness
for control transfers but does not resolve all of the issues.
* configs/stm3220g-eval/*/defconfig: Calibrated delay loop. It had
@ -3382,7 +3382,7 @@
* lib/stdio/lib_sscanf.c: Add %n pseudo-format (from Kate).
* lib/stdio/lib_sscanf.c: There is an issue of handling input
when (1) no fieldwidth is provided and (2) there is no space
seperating the input values. No solutions is in place for this
separating the input values. No solutions is in place for this
case now (either space or a fieldwidth must be provided). But
at least some of the bad logic that attempted to handle this
case has been removed (noted by Kate).
@ -4130,7 +4130,7 @@
for pthreads. By dividing the TCB structure into these variants,
pthreads do not have to be burdened by task-specific data structures
(and vice versa).
* sched/task_exithook.c adn group_create.c: Fix an error, the
* sched/task_exithook.c and group_create.c: Fix an error, the
task within the task group may exit early leaving a pthread to
exit the task group last. In this case, we need to remember the
the PID of the main task in the task group and use that PID for
@ -4878,7 +4878,7 @@
* arch/include/sam34/chip.h: Add chip definitions for the SAM4L
family (2013-6-3).
* configs/sam4l-xplained: A partial configuration that will (eventually)
support the SAM4L Xplained Pro developement board (2013-6-3).
support the SAM4L Xplained Pro development board (2013-6-3).
* arch/arm/src/sam34/chip/sam4l_pinmap.h: Initial cut as SAM4L
pin mapping (2013-6-3).
* arch/arm/src/stm32/stm32*_dma.*: Add a new interface function,
@ -5046,7 +5046,7 @@
* drivers/lcd/ug-2864ambag01.c and ug-9664hswag01.c: Add/updated
support for reverse portrait mode from lessons learned with the
UG-2832HSWEG04. Untested changes! (2013-6-24).
* arch/arm/src/stm32/stm32_ccm.c and .h: Add support for a seperate CCM
* arch/arm/src/stm32/stm32_ccm.c and .h: Add support for a separate CCM
heap. This may be useful for segregating allocations for CCM (which
cannot be used for DMA) from other allocations (that may be used used
for DMA) (2013-6-25).
@ -8815,7 +8815,7 @@
definition. From Lazlo (2014-10-9).
* include/syscall.h, syscall/, and libc/: Remove syslog interfaces
from the set of system calls (2014-10-9).
* libc/syslog: Move syslog back out of the kernel into the C libary
* libc/syslog: Move syslog back out of the kernel into the C library
(2014-10-9).
* arch/mips/src/pic32mx/pic32mx-devcfg.h: For PIC32MX7, DEVCFG0 bit
2 must be set. Writing bit 2 as zero can brick the CPU on some
@ -9104,7 +9104,7 @@
destruction of waitsem, irqsem and readysem to
cc3000_open/cc3000_close.
* include/cxx/cctype: Undefine macros defined ctype.h so that builtin
C++ implementations will be used intead. From Lorenz Meier
C++ implementations will be used instead. From Lorenz Meier
(2014-11-28).
* configs/stm3210e-eval/src/stm32_djoystick.c: Add a discrete Joystick
supportfor the STM3210E-EVAL (2014-11-28).
@ -10074,7 +10074,7 @@
include/nuttx/input/touchscreen.h: arch_tcinitialize() and
arch_tcunitinitialize() renamed to board_tsc_setup() and
board_tsc_teardown(). These are not long called directly by
applications but only indirectly throught the crappy boardctl() OS
applications but only indirectly through the crappy boardctl() OS
interface (2015-03-31).
* configs/Kconfig, boardctl.c, include/nuttx/board.h, include/sys/boardctl.h,
and several ADC files in configs/<board>/src/: Rename adc_devinit() to
@ -10987,7 +10987,7 @@
machines follow the Microsoft ABI for parameter passing. The older,
Linux System 5 ABI will not work on X86_64-based Cygwin machines. Also,
the newer Cygwin tool chains do nor pre-pend symbol names with the
underscore character. With these changes the simulator agains works
underscore character. With these changes the simulator against works
with the newer Cygwin64 platform (2015-09-24).
* arch/arm/src/lpc43xx: Extensive I2C and clocking updates from Lok Tep
(2015-09-29).
@ -12333,7 +12333,7 @@
many data as possible via a CDC/ACM device and verified the received
data on the PC. From Stefan Kolb (2016-07-13).
* STM32: Fix bug in oneshot timer. From Max Neklyudov (2016-07-13).
* STM32L4: Port foward bugfix from stm32 of oneshot timer. From
* STM32L4: Port forward bugfix from stm32 of oneshot timer. From
ziggurat29 (2016-07-13).
* STM32 and EFM32: I'm using syslog through ITM. In this case
syslog_channel function is call before RAM initialization in
@ -13042,7 +13042,7 @@
CONFIG_SDIO_DMA which is only defined in stm32/Kconfig. Changed to
CONFIG_STM32F7_SDMMC_DMA and defined in stm32f7/Kconfig (2016-11-07).
* arch/arm/src/stm32: Add PWM driver support for STMF37xx. The
changes have been tested successfuly for TIM4 and TIM17 (different
changes have been tested successfully for TIM4 and TIM17 (different
IPs). From Marc Rechté (2016-11-07).
* sched/semaphore: sem_trywait() no longer modifies the errno value
UNLESS an error occurs. This allows these functions to be used
@ -13057,7 +13057,7 @@
* drivers/sensors and configs/stm32f103-minimum: Add Vishay VEML6070
driver and support for STM32F103-Minimum board. From From Alan
Carvalho de Assis(2016-11-13).
* Misoc LM32: Corrects a bug that never occured in qemu on simulation or
* Misoc LM32: Corrects a bug that never occurred in qemu on simulation or
real fpga. The error was that the r1 register was being modified out of
context switching and not restoring it. From Ramtin Amin (2016-11-14)
* arch/arm/src/samv71: A problem occurred with the SAMV7 USBDEVHS driver
@ -13321,7 +13321,7 @@
fixes. From David Sidrane (2016-12-05).
* Expanded otgfs support to stm32F469 and stm32f446. Added missing bits
definitions, Used stm32F469 and stm32f446 bit definitions, Removed
unsed header file. From David Sidrane (2016-12-05).
unused header file. From David Sidrane (2016-12-05).
* Remove BOARDIOC_CAN_INITIALIZE. CAN initialization is now done in the
board initialization logic just like every other device driver
(2016-12-06).
@ -13355,7 +13355,7 @@
(2016-12-10).
* task_delete() now obeys all cancellation point semantics (2016-12-10).
* Add task_setcancelstate(), task_setcanceltype(), and task_testcancel().
These are non-standard interfaces analogous to the correponding pthread_
These are non-standard interfaces analogous to the corresponding pthread_
interfaces that provide cancellation controls for tasks (2016-12-10).
* i.MX6 interrupt handling: Additional logic needed to handle nested
interrupts when an interrupt stack is used (2016-12-13).
@ -13404,8 +13404,8 @@
* Xtensa EPS32: Make sure that all C callable assembly functions includes
ENTRY prologue and RET epilogue (2016-12-15).
* Xtensa ESP32: Fix windowspill register handling + Use r6, not r2 when
passing paramters with call4 (2016-12-16).
* Xtensa ESP32: Use r6, not r2 when passing paramters with call4
passing parameters with call4 (2016-12-16).
* Xtensa ESP32: Use r6, not r2 when passing parameters with call4
(2016-12-16).
* Xtensa ESP32: Correct a logic problem the prevented dumping the IDLE
thread's stack on an assertion (2016-12-16).
@ -14103,7 +14103,7 @@
C++ std namespace. From Alan Carvalho de Assis (2017-03-08).
* Kinetis: Fixed GPIO _PIN_OUTPUT_LOWDRIVE swapped with
_PIN_OUTPUT_OPENDRAIN. From David Sidrane (2017-03-08).
* Ensure interrupts are back on BEFORE running code dependant on
* Ensure interrupts are back on BEFORE running code dependent on
clock_systimer. From David Sidrane (2017-03-08).
* Enable compilation of libc++ same way as uClibc++. From Alan
Carvalho de Assis (2017-03-08).
@ -14190,7 +14190,7 @@
(2017-03-10).
* STM32, STM32 F7, and STM32 L4: Clone Freddie Chopin's I2C change to
similar STM32 I2C drivers. From David Sidrane (2017-03-10).
* Priority Inversion fixes: Initalization. From David Sidrane
* Priority Inversion fixes: Initialization. From David Sidrane
(2017-03-10).
* configs: Add Particle Photon board support. From Simon Piriou
(2017-03-10).
@ -14362,7 +14362,7 @@
(2017-03-22).
* STM32: Fix erase sector number for microcontrolers with more than 11
sectors. Erase a sector from the second bank cause the bit 4 of SNB
being set but never unsed, so trying to erase a sector from the first
being set but never unused, so trying to erase a sector from the first
bank was acually eraseing a sector from the second bank. From José
Roberto de Souza (2017-03-22).
* STM32: Make up_progmem thread safe. Writing to a flash sector while
@ -15228,7 +15228,7 @@
Piriou (2017-05-14).
* configs/photon/wlan: disable network logs and add nsh over telnet.
From Simon Piriou (2017-05-14).
* TCP: Send RST if applicaiton 'unlistens()' before we complete the
* TCP: Send RST if application 'unlistens()' before we complete the
connection sequence (2017-05-14).
* drivers: fix some bad NULL checks. From Juha Niskanen (2017-05-15).
* drivers: rename newly introduced up_i2creset to I2C_RESET. From
@ -15527,7 +15527,7 @@
current interrupt parameter passing (2017-06-12).
* gethostbyname_r: Fix check for space in buffer (2017-06-12).
* MTD M2PX: If we READ while a write/erase is pending, the command is
ignored and the write/erase continues. If we dont catch this
ignored and the write/erase continues. If we don't catch this
situation we will return garbage to the user because the flash will
not execute the command. So READ MUST wait for write completion, and
before that, the bus must be locked since it's a precondition to
@ -15540,7 +15540,7 @@
from the timer output of a STM32 clocked at 140 MHz (which works fine
in baremetal C), I stumbled on what I believe to be an error in
arch/arm/src/stm32/stm32_pwm.c. Line 1304 we are told that: reload =
timclk / info->frequency; which I belive to be incorrect, it should
timclk / info->frequency; which I believe to be incorrect, it should
be: reload = timclk / info->frequency - 1; since starting to count
from 0, if I want to output half of the TIM clock, I must count to 1
and not to 2. Surely enough, the original code did output 140/3=47
@ -16059,7 +16059,7 @@
proof of concept. More to come. Currently there are only tables for
the INET/INET6 family, the Unix LOCAL family, and the raw PACKET
family. Hopefully there will be AF_IEEE802154 and AF_BLUETOOTH
comming down the pike. Add recvfrom() method to interface
coming down the pike. Add recvfrom() method to interface
(2017-07-12).
* ieee802154: Fixes setting devmode logic. From Anthony Merlino
(2017-07-13).
@ -16475,7 +16475,7 @@
* STM32L476VG Discovery: Add a knsh configuration that may be used to
test the PROTECTED build mode (2017-08-17).
* stm32f7:DMA correct comments and document stm32_dmacapable. Updated
comment to proper refernce manual for STM32F7 not STM32F4. Added
comment to proper reference manual for STM32F7 not STM32F4. Added
stm32_dmacapable input paramaters documentation. From David Sidrane
(2017-08-17).
* STM32 F7: DMA add dcache alignment check in stm32_dmacapable. In the
@ -17584,7 +17584,7 @@
interrupts example. From Mateusz Szafoni (2017-10-22).
* Misc STM32 chagnes
- STM32 HRTIM: Fix warnings related with RCC
- STM32F33xxx ADC: Add some publicly visable interfaces and some
- STM32F33xxx ADC: Add some publicly visible interfaces and some
code to support injected channels
- STM32F33xxx DMA: Add public interface to handle with DMA interrupts
From Mateusz Szafoni (2017-10-22).
@ -18131,7 +18131,7 @@
generic one. Add a workaround in up_txready() to avoid data
corruption. From Masayuki Ishikawa (2017-11-27).
* arch/arm/src/lpc43xx: lpc43_adc.c was being selected by the build
system wehn DAC was selected (2017-11-27).
system when DAC was selected (2017-11-27).
* configs/lc823450-xgevk: Add RNDIS configuration. From Masayuki
Ishikawa (2017-11-28).
* drivers/input/nunchuck.c: Add Nintendo Wii Nunchuck driver. From
@ -19430,7 +19430,7 @@
Kinetis UART must be placed in 9 bit mode (M=1) with when 8 bit data with
parity is required. If left in 8 bit mode (M=0) with parity then D7 of the
TX/RX register becomes parity bit. Hence what is called 9-bit or 8-bit
Mode Select is a misnomer. 8 bit mode when parity is enabled is realy 7
Mode Select is a misnomer. 8 bit mode when parity is enabled is really 7
bit with parity. From David Sidrane (2018-05-30).
* arch/sim: Various fixes necessary to build the simulator under MSYS2.
From Gregory Nutt (2018-05-31).
@ -20048,7 +20048,7 @@
* arch/arm/src/stm32l4/chip: Merged stm32l4x2xx and stm32l4x3xx pinmap
files. Removed references to stm32l4x2xx_pinmap.h From Daniel P.
Carvalho (2018-08-09).
* arch/arm/src/kinetis: PIT add Liftime and Chaining
* arch/arm/src/kinetis: PIT add Lifetime and Chaining
arch/arm/src/kinetis: flexcan fix duplicate line and ordering
arch/arm/src/kinetis: kinetis_lowput.c LPUART data format with
parity fix. The 9-bit data mode is typically used with parity to
@ -22437,7 +22437,7 @@
battery_charger_dev_s' should be a pointer to operations structure.
From Alan Carvalho de Assis (2019-01-05).
* drivers/net/telnet.c: Add NAWS and poll interface to telnet for screen
size negotation used with termcurses. From Ken Pettit (2019-01-05).
size negotiation used with termcurses. From Ken Pettit (2019-01-05).
* arch/arm/src/samv7/sam_serial.c: Fix case where TTYS0 is not defined.
From Ken Pettit (2019-01-05).
* arch/arm/src/armv7-a/arm_mmu.c: Fix end address calculation for
@ -23417,7 +23417,7 @@
- configs/teensy-3.x/usbnsh/defconfig: update config according to
change in USBDEV_TRACE_INITIALIDSET
From Mateusz Szafoni (2019-03-10).
* arch/arm/src/imxrt/imxrt_clockconfig.c: If SDRAM is actived it was
* arch/arm/src/imxrt/imxrt_clockconfig.c: If SDRAM is activated it was
only running at 40MHz. This was becaus imxrt_clockconfig.c changed the
SEMC clock divider after the DCD was configured. This commit corrects
that. From Johannes (2019-03-10).
@ -23430,7 +23430,7 @@
display number as an argument. This makes it possible to have multiple
instances of the NX server running on boards that support multiple
displays. Also includes updates to boardctl() to accept display number
paramters. From Gregory Nutt (2019-03-10).
parameters. From Gregory Nutt (2019-03-10).
* Add three patches about STM32 intherupts and network loopback files
- Add the missing macro STM32_IRQ_NIRQS used by
./arch/arm/src/stm32f7/stm32_irq.c
@ -23459,7 +23459,7 @@
the reference count before freeing the dspace memory region. From
Gregory Nutt (2019-03-12).
* tools/nxstyle.c: Don't complain about certain lowercase characters in
otherwise uppercase pre-processor identifers: IPv6, IPv4, ICMPv6,
otherwise uppercase pre-processor identifiers: IPv6, IPv4, ICMPv6,
IGMPv2, p as a decimal point, d signifying a divisor. It was a bad
idea to let the door open a crack for there. While they improve
readability, the inconsistently also causes other problems. From
@ -24075,7 +24075,7 @@
* In many files: Remove references to CONFIG_DISABLE_SIGNALS. Signals can
no longer be disabled. From Gregory Nutt (2019-04-29).
* net/socket/getsockname.c: Fix addrlen check in socket debug features.
Getsockname checked erroneously a pointer agains 0, where the intention
Getsockname checked erroneously a pointer against 0, where the intention
was to dereference the pointer and to check the length. This causes also
a compilation failure if the code is compiled with CONFIG_DEBUG_FEATURES
and with -Werror flag set. From Jukka Laitinen (2019-04-30).
@ -25775,7 +25775,7 @@
drain From Beat Küng (2019-08-15).
* boards/arm/s32k1xx/s32k118evb/src/s32k118_clockconfig.c: Add clock
configuration data for the S32K118EVB. From Gregory Nutt (2019-08-15).
* arch/arm/src/tiva/common/tiva_irq.c: Add handling for IRQs 128 thru
* arch/arm/src/tiva/common/tiva_irq.c: Add handling for IRQs 128 through
159. Handling was missing for these IRQs, resulting in compiler
warning(s) for 'Missing logic' and/or 'Missing output.' From Nathan
Hartman (2019-08-15).
@ -27203,7 +27203,7 @@
in this directory. From Gregory Nutt (2019-10-29).
* NXP k66 Ethernet
- Kinetis:Add TJA1100 Phy
- Kinetis:enet.c formated with nxstyle
- Kinetis:enet.c formatted with nxstyle
- net:mii Cleanup TJA1100 Support. Formating and adding mask and
shifts.
- net:Kconfig Cleanup formatting.
@ -27274,7 +27274,7 @@
selected. Since SPI is mandatory it should be auto selected. From
Alin Jerpelea (2019-11-04).
* net/netlink: The NETLINK_ROUTE logic needs to return the first queued
response and not attempt to match up reponses with requests. That is
response and not attempt to match up responses with requests. That is
the Linux compatible way. Also, use queue.h functions for list
management and fix an error in arp_snapshot(). From Gregory Nutt
(2019-11-04).

6
Documentation/NuttX.html
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@ -3847,7 +3847,7 @@ nsh>
Some initial files for the LPC17xx family were released in NuttX 5.6, but
</li>
<li>
The first functional release for the NXP LPC1768/Nucleus2G occured with NuttX 5.7 with
The first functional release for the NXP LPC1768/Nucleus2G occurred with NuttX 5.7 with
Some additional enhancements through NuttX-5.9.
Refer to the NuttX board <a href="https://bitbucket.org/patacongo/obsoleted/src/master/configs/nucleus2g/README.txt" target="_blank">README</a> file for further information.
</li>
@ -3866,7 +3866,7 @@ nsh>
<p><b>Obsoleted</b>.
Support for the Nucleus2G board was terminated on 2016-04-12.
There has not been any activity with the commercial board in a few years and it no longer appears to be available from the 2g-eng.com website.
Since the board is commercial and no longer publically available, it no longer qualifies for inclusion in the open source repositories.
Since the board is commercial and no longer publicly available, it no longer qualifies for inclusion in the open source repositories.
A snapshot of the code is still available in the <a href="https://bitbucket.org/patacongo/obsoleted/src/master/boards/nucleus2g">Obsoleted repository</a> and can easily be <i>reconstitued</i> if needed.
</p>
</li>
@ -4078,7 +4078,7 @@ nsh>
<td>
<p>
<a name="xmd45xx"><b>Infineon XMC45xx</b>.</a>
An initial but still incomplete port to the XMC4500 Relax board was released with NuttX-7.21 (although it wass not really ready for prime time). Basic NSH functionality was a serial console was added by Alan Carvahlo de Assis in NuttX-7.23. Alan also added an SPI driver in NuttX-7.25.
An initial but still incomplete port to the XMC4500 Relax board was released with NuttX-7.21 (although it was not really ready for prime time). Basic NSH functionality was a serial console was added by Alan Carvahlo de Assis in NuttX-7.23. Alan also added an SPI driver in NuttX-7.25.
</p>
<p>
This initial porting effort uses the Infineon XMC4500 Relax v1 board as described on the manufacturer's <a href="http://www.infineon.com/cms/en/product/evaluation-boards/KIT_XMC45_RELAX_V1/productType.html?productType=db3a304437849205013813b23ac17763">website</a>.

2
Documentation/NuttXBinfmt.html
View file

@ -469,7 +469,7 @@ void envpath_release(ENVPATH_HANDLE handle);
struct symtab_s
{
FAR const char *sym_name; /* A pointer to the symbol name string */
FAR const void *sym_value; /* The value associated witht the string */
FAR const void *sym_value; /* The value associated with the string */
};
</pre></ul>

18
Documentation/NuttXCCodingStandard.html
View file

@ -417,7 +417,7 @@
</li>
<li>
Text following '.' or ':' begins with an upper-case character;
text folowing ',' or ';' begins with a lower-case character.
text following ',' or ';' begins with a lower-case character.
</li>
</ul>
<p>
@ -608,7 +608,7 @@
<p>
<b>Comments to the Right of Data Definitions</b>.
Comments to the right of a declaration with an enumeration or structure, on the other hand, are encouraged, provided that the comments are short and do not exceed the maximum line width (usually 78 characters).
Columnar alignment of comments is very desireable (but often cannot be achieved without violating the line width).
Columnar alignment of comments is very desirable (but often cannot be achieved without violating the line width).
</p>
<center><table width="60%" border=1>
<tr><td bgcolor="white">
@ -696,7 +696,7 @@ struct animals_s
<p>
<b>C Style Comments</b>.
C99/C11/C++ style comments (beginning wih <code>//</code>) should not be used with NuttX.
C99/C11/C++ style comments (beginning with <code>//</code>) should not be used with NuttX.
NuttX generally follows C89 and all code outside of architecture specific directories must be compatible with C89.
</p>
<center><table width="60%" border=1>
@ -803,7 +803,7 @@ void some_function(void)
</li>
<li>
<b>Compound Statements</b>.
Within this document, an opening left brace followed by a sequence of statments, and ending with a closing right brace is refered to as a <i>compound statement</i>.
Within this document, an opening left brace followed by a sequence of statments, and ending with a closing right brace is referred to as a <i>compound statement</i>.
</li>
<li>
<b>Nested Compound Statements</b>.
@ -1047,7 +1047,7 @@ int animals(int animal)
C pre-processor statements should always be indented in this way in the <code>Pre-processor Definitions</code> <a href="#cfilestructure">section</a> of each file.
C pre-processor statements may be indented in the <code>Public/Private Data</code> and <code>Public/Private Functions</code> sections of the file.
However, often the indentation of C pre-processor statements conflicts with the indentation of the C code and makes the code more difficult to read.
In such cases, indentation of C pre-processor statements should be ommitted in those sections (only).
In such cases, indentation of C pre-processor statements should be omitted in those sections (only).
</p>
<center><table width="60%" border=1>
@ -1133,7 +1133,7 @@ int animals(int animal)
Otherwise, there should be no space before the left parentheses
</li>
<li>
<b>No space betwen function name and argument list</b>.
<b>No space between function name and argument list</b>.
There should be no space between a function name and an argument list.
</li>
<li>
@ -1455,7 +1455,7 @@ typedef int myinteger_t;
First for structures that are defined within another union or structure (discouraged). In those cases, the structure name should always be omitted.
</li>
<li>
Second for structures as the type of a local variable. In this case, again, the structure name should always be ommitted.
Second for structures as the type of a local variable. In this case, again, the structure name should always be omitted.
</li>
</ol>
</li>
@ -2570,7 +2570,7 @@ x++;
</li>
<li>
<b>Followed by a single blank line</b>.
The final right brace that closes the <code>while &lt;condition&gt;</code> statment must be followed by a single blank line.
The final right brace that closes the <code>while &lt;condition&gt;</code> statement must be followed by a single blank line.
</li>
<li>
<b>Exception</b>.
@ -2692,7 +2692,7 @@ x++;
<li>
<b>Error Exit Labels</b>.
The error exit label is normally called <code>errout</code>.
Multiple error labels are often to required to <i>unwind</i> to recover resources committe in logic prior to the error to otherwise <i>undo</i> preceding operations.
Multiple error labels are often to required to <i>unwind</i> to recover resources committed in logic prior to the error to otherwise <i>undo</i> preceding operations.
Naming for these other labels would be some like <code>errout_with_allocation</code>, <code>errout_with_openfile</code>, etc.
</li>
<li>

4
Documentation/NuttxPortingGuide.html
View file

@ -2296,7 +2296,7 @@ The specific environmental definitions are unique for each board but should incl
There are many interfaces exported from board- to architecture-specific logic.
But there are only a few exported from board-specific logic to common NuttX logic.
Those few of those related to initialization will be discussed in this paragraph.
There are others, like those used by <a href="#boardctl"><code>boardctl()</code></a> that will be dicussed in other paragraphs.
There are others, like those used by <a href="#boardctl"><code>boardctl()</code></a> that will be discussed in other paragraphs.
</p>
<p>
All of the board-specific interfaces used by the NuttX OS logic are for controlled board initialization.
@ -2339,7 +2339,7 @@ The specific environmental definitions are unique for each board but should incl
This additional initialization phase may be used, for example, to initialize more complex, board-specific device drivers.
</p>
<p>
Waiting for events, use of I2C, SPI, etc are permissable in the context of board_late_initialize().
Waiting for events, use of I2C, SPI, etc are permissible in the context of board_late_initialize().
That is because <code>board_late_initialize()</code> will run on a temporary, internal kernel thread.
</p>

2
Documentation/NuttxUserGuide.html
View file

@ -860,7 +860,7 @@ int exec(FAR const char *filename, FAR char * const *argv,
<p>
This non-standard interface is included as a official NuttX API only because it is needed in certain build modes: <code>exec()</code> is probably the only want to load programs in the PROTECTED mode. Other file execution APIs rely on a symbol table provided by the OS. In the PROTECTED build mode, the OS cannot provide any meaningful symbolic information for execution of code in the user-space blob so that is the <code>exec()</code> function is really needed in that build case
</p>
The interface is available in the FLAT build mode although it is not really necessary in that case. It is currently used by some example code under the <code>apps/</code> that that generate their own symbol tables for linking test programs. So althought it is not necessary, it can still be useful.
The interface is available in the FLAT build mode although it is not really necessary in that case. It is currently used by some example code under the <code>apps/</code> that that generate their own symbol tables for linking test programs. So although it is not necessary, it can still be useful.
</p>
<p>
The interface would be completely useless and will not be supported in the KERNEL build mode where the contrary is true: An application process cannot provide any meaning symbolic information for use in linking a different process.

60
ReleaseNotes
View file

@ -2476,7 +2476,7 @@ New features in this release include:
the OS test and the NuttShell (NSH) both exist.
* Tests: New re-usable tests (in apps/examples) for PWM, ADC, and
CAN loopback. Several existing tests can now be built as NSH built-in
applicaitons (dhcpd, nettest, and all of the new tests).
applications (dhcpd, nettest, and all of the new tests).
Bugfixes, order roughly on decreasing criticality include:
@ -3295,7 +3295,7 @@ Additional new features and extended functionality:
- Tasking logic is extended to support the notion of address
environments. An address environment is the key notion underlying
"process" vs. tasks. If tasks are created with address environments
(by binfmt), the OS will propogate that environment to child threads
(by binfmt), the OS will propagate that environment to child threads
and will destroy the address environment when the "process" exists.
- If support for the PATH variable is enabled, the OS start up logic
will create an initial environment containing the default PATH
@ -4351,7 +4351,7 @@ Additional new features and extended functionality:
- Added support for the Atmel SAM4L Xplained Pro development board.
This board features the ATSAM4LC4C MCU (Cortex-M4 with 256KB FLASH +
32KB SRAM).
- Added support for the Atmel SAM4S Xplained developement board. This
- Added support for the Atmel SAM4S Xplained development board. This
board features the ATSAM4S16C MCU (Cortex-M4 with 1MB FLASH + 128KB
SRAM).
@ -4968,7 +4968,7 @@ Additional new features and extended functionality:
- Add GMII/GRMII PHY definitions for the Micrel KSZ9021/31 PHY.
- New network-optimized, higher-performance sendfile() implementation
from Max Holtzberg.
- Added a simple routing table. This table is currenly only used (1)
- Added a simple routing table. This table is currently only used (1)
when we need to look-up an Ethernet device based on an IP address,
and (2) in the ARP logic when we need to request the MAC address of
the router, vs the MAC address of the peer.
@ -9947,7 +9947,7 @@ Additional new features and extended functionality:
- VFS: The VFS was extended to support standard file operations on
block drivers (open, close, read, write, etc.). The open() interface
accomplishes this by creating a temporary characer driver to mediate
the character oriented accesses to tje block driver.
the character oriented accesses to the block driver.
- HOSTFS: Added a HOSTFS file system for use with the simulator. The
HOSTFS file system mounts in the simulated Nuttx context by provides
proxied access to the file system on the host PC. This is useful for
@ -10497,7 +10497,7 @@ Additional new features and extended functionality:
- procfs: Add /proc/kmm entry that shows that state of the kernel
heap. Only useful in PROTECTED and KERNEL build modes where there
is a kernel heap.
- procfs: Add support for showing CPU in the tast status if SMP is
- procfs: Add support for showing CPU in the taste status if SMP is
enabled.
* Networking:
@ -12338,7 +12338,7 @@ Additional new features and extended functionality:
- task_delete() now obeys all cancellation point semantics.
- Add task_setcancelstate(), task_setcanceltype(), and
task_testcancel(). These are non-standard interfaces analogous to the
correponding pthread_ interfaces that provide cancellation controls
corresponding pthread_ interfaces that provide cancellation controls
for tasks.
* Graphics/Display Drivers:
@ -12484,7 +12484,7 @@ Additional new features and extended functionality:
mode and does not support external TIMER triggers. This is a work in
progress. From Marc Rechté.
- STM32 F3: Add PWM driver support for STMF37xx. The changes have been
tested successfuly for TIM4 and TIM17 (different IPs). From Marc
tested successfully for TIM4 and TIM17 (different IPs). From Marc
Rechté.
- STM32 F4: Support oversampling by 8 for the STM32 F4. From David
Sidrane.
@ -12493,7 +12493,7 @@ Additional new features and extended functionality:
From David Sidrane.
- STM32 F4: Expanded OTGFS support to stm32F469 and stm32f446. Added
missing bit definitions, Used stm32F469 and stm32f446 bit
definitions, Removed unsed header file. From David Sidrane.
definitions, Removed unused header file. From David Sidrane.
- STM32 F4: Allow dma in 1 bit mode in STM32F4xxx. From David Sidrane.
- STM32 F7: Allow the config to override the clock edge setting. From
David Sidrane.
@ -12691,7 +12691,7 @@ detailed bugfix information):
enter/leave_critical_section logic to deal with the case where
interrupts are disabled only on the local CPU. In this case, some
rather complex spinlocks must be used to maintain the critical section
accross all CPUs.
across all CPUs.
- SMP Critical Sections: Fixes for the SMP case: (1) Change order for
SMP case in enter_critical_section: (1) Disable local interrupts
BEFORE taking spinlock and (2) If SMP is enabled, if any interrupt
@ -12881,7 +12881,7 @@ detailed bugfix information):
* Misoc LM32:
- Misoc LM32: Corrects a bug that never occured in qemu on simulation or
- Misoc LM32: Corrects a bug that never occurred in qemu on simulation or
real fpga. The error was that the r1 register was being modified out
of context switching and not restoring it. From Ramtin Amin
@ -13915,7 +13915,7 @@ Additional new features and extended functionality:
- Added support for set [{+|-}{e|x|xe|ex}] [<name> <value>]. Set the
'exit on error control' and/or 'print a trace' of commands when
parsing scripts in NSH. The settinngs are in effect from the point
of exection, until they are changed again, or in the case of the init
of execution, until they are changed again, or in the case of the init
script, the settings are returned to the default settings when it
exits. Included child scripts will run with the parents settings and
changes made in the child script will effect the parent on return.
@ -14164,7 +14164,7 @@ detailed bugfix information):
Kivilinna.
- TCP: Wait for 3-Way Handshare before accept() returns. From Simon
Piriou.
- TCP: Send RST if applicaiton 'unlistens()' before we complete the
- TCP: Send RST if application 'unlistens()' before we complete the
connection sequence.
- TCP: An RST received during the 3-way handshake requires a little
more clean-up.
@ -14254,7 +14254,7 @@ detailed bugfix information):
- Kinetis: Fixed GPIO _PIN_OUTPUT_LOWDRIVE swapped with
_PIN_OUTPUT_OPENDRAIN. From David Sidrane.
- Ensure interrupts are back on BEFORE running code dependant on
- Ensure interrupts are back on BEFORE running code dependent on
clock_systimer. From David Sidrane.
- Kinetis k66, k64, k60, k40, k20: Pin mux configure all I2C signals as
Open Drain. The output structure of the GPIO for I2C needs to be
@ -14319,7 +14319,7 @@ detailed bugfix information):
polling interval for the case of isochronous and interrupt endpoints.
- STM32: Fix erase sector number for microcontrolers with more than 11
sectors. Erase a sector from the second bank cause the bit 4 of SNB
being set but never unsed, so trying to erase a sector from the first
being set but never unused, so trying to erase a sector from the first
bank was acually eraseing a sector from the second bank. From José
Roberto de Souza.
- STM32: Make up_progmem thread safe. Writing to a flash sector while
@ -14945,7 +14945,7 @@ Additional new features and extended functionality:
* Tools:
- testbuild.sh: Added -x to fail build on errors for continous
- testbuild.sh: Added -x to fail build on errors for continuous
integration (CI). On CI we want to know ASAP of a failure. From
David Sidrane.
- Improve configure.sh behavior: (1) enable to call from top directory.
@ -15117,7 +15117,7 @@ detailed bugfix information):
cloned error: It was not locking the bus while performing byte write
operations.
- MTD M2PX: If we READ while a write/erase is pending, the command is
ignored and the write/erase continues. If we dont catch this situation
ignored and the write/erase continues. If we don't catch this situation
we will return garbage to the user because the flash will not execute
the command. So READ MUST wait for write completion, and before that,
the bus must be locked since it's a precondition to calling
@ -16453,7 +16453,7 @@ detailed bugfix information):
* NXP/Freescale LPC43xx:
- lpc43xx: lpc43_adc.c was being selected by the build system wehn
- lpc43xx: lpc43_adc.c was being selected by the build system when
DAC was selected.
* NXP/Freescale LPC43xx Drivers:
@ -16520,7 +16520,7 @@ detailed bugfix information):
the RTC_TR register instead of being locked."
- STM32 Serial: Do not stop processing input in SW flow-control
mode. From Juha Niskanen.
- STM32F33xxx ADC: Add some publicly visable interfaces and some
- STM32F33xxx ADC: Add some publicly visible interfaces and some
code to support injected channels. From Mateusz Szafoni.
- STM32F33xxx DMA: Add public interface to handle with DMA
interrupts. From Mateusz Szafoni.
@ -17911,7 +17911,7 @@ Additional new features and extended functionality:
existing code. The previously existing tftpget/tftpput functions
are now wrappers on the new ones, with callbacks that read/write
from files, so my modifications are backwards compatible with
existing applications, eg the associated nsh commands dont need to
existing applications, eg the associated nsh commands don't need to
be changed. From Sebastien Lorquet.
* Wireless Utilities: apps/wireless:
@ -18108,7 +18108,7 @@ detailed bugfix information):
with parity is required. If left in 8 bit mode (M=0) with parity
then D7 of the TX/RX register becomes parity bit. Hence what is
called 9-bit or 8-bit Mode Select is a misnomer. 8 bit mode when
parity is enabled is realy 7 bit with parity. From David Sidrane.
parity is enabled is really 7 bit with parity. From David Sidrane.
* NXP/Freescale Kinetis Boards:
@ -19409,7 +19409,7 @@ detailed bugfix information):
complete. The second problem is that Software Reset For DAT Line
SDHC_SYSCTL[RSTD] clears the bits 24-0 in SDHC_PROTO this looses
the wide bus setting DTW From David Sidrane.
- Kinetis: (1) PIT add Liftime and Chaining, (2) flexcan fix
- Kinetis: (1) PIT add Lifetime and Chaining, (2) flexcan fix
duplicate line and ordering, (3) kinetis_lowput.c LPUART data
format with parity fix. The 9-bit data mode is typically used with
parity to allow eight bits of data plus the parity, (4) lowputc
@ -21717,7 +21717,7 @@ detailed bugfix information):
3. Paste buffer from 'dd' was being free'd after the 'p'aste operation,
preventing multiple paste opportunity. Fixed.
4. The cursor was not being bound to the line end and was allowed to
'hover' over the '\n' EOL character. This caused wierd (relative to
'hover' over the '\n' EOL character. This caused weird (relative to
standard vi) insertion locations and cursor movement with 'a'ppend
and 'i'nsert. Fixed.
5. The 'vi_shrinkpos' position didn't take the end of file pointer into
@ -21725,7 +21725,7 @@ detailed bugfix information):
wierdness when deleting things near the end of the file. Fixed.
6. The 'yy'ank command was improperly deleting the text from the
document instead of simply yanking to the paste buffer. Fixed.
7. The 'dd'elete line funciton was not copying the deleted line to the
7. The 'dd'elete line function was not copying the deleted line to the
paste buffer as part of the delete operation. Fixed.
8. The bottom line of the screen was sometimes being used for document
text and other times for command / find entry. Fixed by reserving
@ -21761,7 +21761,7 @@ detailed bugfix information):
17. In command mode, backspace was deleting characters which is
different from standard vi. Backspace in command mode normally
simply moves the cursor left / to the previous line. Fixed.
18. Added code to handle boundry conditions when the file is new and
18. Added code to handle boundary conditions when the file is new and
commands are applied to an empty file.
19. Fixed vi_shrinktext so it doesn't allocate a zero-length buffer when
the last character in the file is deleted.
@ -21930,7 +21930,7 @@ Additional new features and extended functionality:
expense of increased memory usage. Redraw requests in other cases
are also suppressed: Changes to window position, size, etc. As a
consequence, some manual updates will be required when certain
events occurr (like removing a toolbar from a window). NOTE: A
events occur (like removing a toolbar from a window). NOTE: A
significant amount of RAM, usually external SDRAM, may be required
to use per-window framebuffers.
@ -22175,7 +22175,7 @@ Additional new features and extended functionality:
- tools/nxstyle.c: Add logic to detect a blank line following a left
brace or a blank line preceding a right brace. From Gregory Nutt.
- tools/nxstyle.c: Don't complain about certain lowercase characters
in otherwise uppercase pre-processor identifers: IPv6, IPv4,
in otherwise uppercase pre-processor identifiers: IPv6, IPv4,
ICMPv6, IGMPv2, p as a decimal point, d signifying a divisor. It
was a bad idea to let the door open a crack for there. While they
improve readability, the inconsistently also causes other
@ -22626,7 +22626,7 @@ detailed bugfix information):
* NXP i.MXRT:
- i.MXRT Clock Configuration: If SDRAM is actived it was only
- i.MXRT Clock Configuration: If SDRAM is activated it was only
running at 40MHz. This was becaus imxrt_clockconfig.c changed the
SEMC clock divider after the DCD was configured. This commit
corrects that. From Johannes.
@ -23280,7 +23280,7 @@ detailed bugfix information):
* Networking/Network Drivers:
- getsockname(): Fix addrlen check in socket debug features.
Getsockname() checked erroneously a pointer agains 0, where the
Getsockname() checked erroneously a pointer against 0, where the
intention was to dereference the pointer and to check the length.
This causes also a compilation failure if the code is compiled
with CONFIG_DEBUG_FEATURES and with -Werror flag set. From Jukka
@ -24919,7 +24919,7 @@ Additional new features and extended functionality:
- Tiva Configuration: Modify preprocessor logic to support
configurations with no UART. Now similar to logic for other
architectures. From Nathan Hartman.
- Tiva Interrupts: Add handling for IRQs 128 thru 159. From Nathan
- Tiva Interrupts: Add handling for IRQs 128 through 159. From Nathan
Hartman.
* TI Tiva Drivers:

4
TODO
View file

@ -632,7 +632,7 @@ o SMP
the g_csection_wait[] needs to be moved back to
g_readytorun[].
- This may result in a context switch. The tasks should be
moved back to g_readytorun[] higest priority first. If a
moved back to g_readytorun[] highest priority first. If a
context switch occurs and the critical section to re-taken
by the re-started task, the lower priority tasks in
g_csection_wait[] must stay in that list.
@ -1124,7 +1124,7 @@ o Kernel/Protected Build
via a system call at high rates.
Title: SIGNAL ACTION VULNERABILITY
Description: When a signal action is peformed, the user stack is used.
Description: When a signal action is performed, the user stack is used.
Unlike Linux, applications do not have separate user and
supervisor stacks; everything is done on the user stack.

2
arch/README.txt
View file

@ -115,7 +115,7 @@ include/irq.h
NOTE: These interfaces are not available to application code but can
only be used within the operating system code. And, in general,
these functions should *never* be called directly, not unless you
know absolutely well what you are doing. Rather you shoudl typically
know absolutely well what you are doing. Rather you should typically
use the wrapper functions enter_critical_section() and leave_critical_section()
as prototyped in include/nuttx/irq.h.

2
arch/arm/include/cxd56xx/backuplog.h
View file

@ -63,7 +63,7 @@ extern "C"
*
* Description:
* Initialize the log header where the address and size of each log area
* are decribed. If the log header has been already configured as a wakeup
* are described. If the log header has been already configured as a wakeup
* from sleeping or reboot case, then do nothing and return OK.
*
* Returned Value:

2
arch/arm/include/cxd56xx/gnss.h
View file

@ -665,7 +665,7 @@ struct cxd56_gnss_ope_mode_param_s
uint32_t cycle;
};
/* Sattelite almanac, ephemeris data */
/* Satellite almanac, ephemeris data */
struct cxd56_gnss_orbital_param_s
{

2
arch/arm/include/cxd56xx/gnss_type.h
View file

@ -96,7 +96,7 @@ extern "C"
#define CXD56_GNSS_PVT_VELFIX_1D 5 /* 1D fix */
#define CXD56_GNSS_PVT_VELFIX_PRED 6 /* Prediction */
/* GNSS oribital infomation data type, almanac & ephemeris */
/* GNSS oribital information data type, almanac & ephemeris */
#define CXD56_GNSS_DATA_GPS 0 /* GPS data type */
#define CXD56_GNSS_DATA_GLONASS 1 /* Glonass data type */

4
arch/arm/include/cxd56xx/scu.h
View file

@ -503,7 +503,7 @@ void seq_setaddress(FAR struct seq_s *seq, uint32_t slave_addr);
*
* This function use 'oneshot' feature on SCU. So user unnecessary to specify
* any opened sequencer.
* This function usefull for accessing register directly.
* This function useful for accessing register directly.
*
* param [in] slavesel : Slave select
* param [in] inst : Sequencer instruction
@ -523,7 +523,7 @@ int scu_spitransfer(int slavesel, uint16_t *inst, uint32_t nr_insts,
*
* This function use 'oneshot' feature on SCU. So user unnecessary to
* specify any opened sequencer.
* This function usefull for accessing register directly.
* This function useful for accessing register directly.
*
* param [in] port : I2C port (0 or 1)
* param [in] slave : Slave address

2
arch/arm/include/lpc17xx_40xx/irq.h
View file

@ -77,7 +77,7 @@
#define LPC17_40_IRQ_EXTINT (16) /* Vector number of the first external interrupt */
/* Family Specfic Interrupts */
/* Family Specific Interrupts */
#if defined(LPC176x) /* LPC175/6 family */
# include <arch/lpc17xx_40xx/lpc176x_irq.h>

2
arch/arm/include/stm32l4/chip.h
View file

@ -199,7 +199,7 @@
#else
# define STM32L4_NPORTS 8 /* 8 GPIO ports, GPIOA-H */
#endif
# define STM32L4_NADC 3 /* 12-bit ADC1-3, upto 24 channels */
# define STM32L4_NADC 3 /* 12-bit ADC1-3, up to 24 channels */
# define STM32L4_NDAC 2 /* 12-bit DAC1-2 */
# define STM32L4_NCRC 1 /* CRC */
# define STM32L4_NCOMP 2 /* Comparators */

2
arch/arm/include/tiva/cc13x0_irq.h
View file

@ -78,7 +78,7 @@
#define TIVA_IRQ_GPT2B (36) /* GPT2B interrupt event */
#define TIVA_IRQ_GPT3A (37) /* GPT3A interrupt event */
#define TIVA_IRQ_GPT3B (38) /* GPT3B interrupt event */
#define TIVA_IRQ_CRYPTO_RESULT_AVAIL (39) /* CRYPTO result available interupt
#define TIVA_IRQ_CRYPTO_RESULT_AVAIL (39) /* CRYPTO result available interrupt
* event */
#define TIVA_IRQ_DMA_DONE (40) /* Combined DMA done */
#define TIVA_IRQ_DMA_ERR (41) /* DMA bus error */

4
arch/arm/src/a1x/Kconfig
View file

@ -356,7 +356,7 @@ config A1X_DDR_MAPOFFSET
closely to other settings:
RAM_START and RAM_VSTART give this physical and virtual addresses
of the start of usable memory (begining with .text). NOTE that
of the start of usable memory (beginning with .text). NOTE that
this may not necessarily be the actual start of the mapped SDRAM
region. It will be larger if NuttX begins at an offset from
beginning of mapped SDRAM (which is the normal case).
@ -379,7 +379,7 @@ config A1X_DDR_MAPSIZE
closely to other settings:
RAM_START and RAM_VSTART give this physical and virtual addresses
of the start of usable memory (begining with .text). NOTE that
of the start of usable memory (beginning with .text). NOTE that
this may not necessarily be the actual start of the mapped SDRAM
region. It will be larger if NuttX begins at an offset from
beginning of mapped SDRAM (which is the normal case).

4
arch/arm/src/am335x/Kconfig
View file

@ -219,7 +219,7 @@ config AM335X_DDR_MAPOFFSET
closely to other settings:
RAM_START and RAM_VSTART give this physical and virtual addresses
of the start of usable memory (begining with .text). NOTE that
of the start of usable memory (beginning with .text). NOTE that
this may not necessarily be the actual start of the mapped SDRAM
region. It will be larger if NuttX begins at an offset from
beginning of mapped SDRAM (which is the normal case).
@ -242,7 +242,7 @@ config AM335X_DDR_MAPSIZE
closely to other settings:
RAM_START and RAM_VSTART give this physical and virtual addresses
of the start of usable memory (begining with .text). NOTE that
of the start of usable memory (beginning with .text). NOTE that
this may not necessarily be the actual start of the mapped SDRAM
region. It will be larger if NuttX begins at an offset from
beginning of mapped SDRAM (which is the normal case).

2
arch/arm/src/arm/pg_macros.h
View file

@ -294,7 +294,7 @@
/* Page Management **********************************************************/
/* For page managment purposes, the following summarize the "heap" of
/* For page management purposes, the following summarize the "heap" of
* free pages, operations on free pages and the L2 page table.
*
* PG_POOL_VA2L1OFFSET(va) - Given a virtual address, return the L1 table

2
arch/arm/src/arm/up_head.S
View file

@ -535,7 +535,7 @@ __start:
*
* R4 = Virtual address of the page table
* R3 = Physical address of the NuttX execution space (aligned to a
* one megabyte addres boundary
* one megabyte address boundary
*/
#ifdef CONFIG_IDENTITY_TEXTMAP

2
arch/arm/src/arm/up_saveusercontext.S
View file

@ -82,7 +82,7 @@ up_saveusercontext:
/* Make sure that the return value will be non-zero (the
* value of the other volatile registers don't matter --
* r1-r3, ip). This function is called throught the
* r1-r3, ip). This function is called through the
* noraml C calling conventions and the values of these
* registers cannot be assumed at the point of setjmp
* return.

2
arch/arm/src/armv7-a/arm_fullcontextrestore.S
View file

@ -118,7 +118,7 @@ up_fullcontextrestore:
#else
/* For a flat build, we can do all of this here... Just think of this as
* a longjmp() all on steriods.
* a longjmp() all on steroids.
*/
/* Recover all registers except for r0, r1, r2, R15, and CPSR */

2
arch/arm/src/armv7-a/arm_head.S
View file

@ -309,7 +309,7 @@ __start:
adr r0, .LCraminfo /* Address of primary RAM info */
ldmia r0, {r1, r2, r3, r4} /* Load the primary RAM description */
add r2, r5, r2, lsr #18 /* R2=Offset page table addres */
add r2, r5, r2, lsr #18 /* R2=Offset page table address */
/* Loop until each page table entry has been written for the primary RAM
* region.

2
arch/arm/src/armv7-r/arm_fullcontextrestore.S
View file

@ -130,7 +130,7 @@ up_fullcontextrestore:
#else
/* For a flat build, we can do all of this here... Just think of this as
* a longjmp() all on steriods.
* a longjmp() all on steroids.
*/
/* Recover all registers except for r0, r1, R15, and CPSR */

32
arch/arm/src/armv7-r/gic.h
View file

@ -513,22 +513,22 @@
* task management.
*/
#define GIC_IRQ_SGI0 0 /* Sofware Generated Interrupt (SGI) 0 */
#define GIC_IRQ_SGI1 1 /* Sofware Generated Interrupt (SGI) 1 */
#define GIC_IRQ_SGI2 2 /* Sofware Generated Interrupt (SGI) 2 */
#define GIC_IRQ_SGI3 3 /* Sofware Generated Interrupt (SGI) 3 */
#define GIC_IRQ_SGI4 4 /* Sofware Generated Interrupt (SGI) 4 */
#define GIC_IRQ_SGI5 5 /* Sofware Generated Interrupt (SGI) 5 */
#define GIC_IRQ_SGI6 6 /* Sofware Generated Interrupt (SGI) 6 */
#define GIC_IRQ_SGI7 7 /* Sofware Generated Interrupt (SGI) 7 */
#define GIC_IRQ_SGI8 8 /* Sofware Generated Interrupt (SGI) 8 */
#define GIC_IRQ_SGI9 9 /* Sofware Generated Interrupt (SGI) 9 */
#define GIC_IRQ_SGI10 10 /* Sofware Generated Interrupt (SGI) 10 */
#define GIC_IRQ_SGI11 11 /* Sofware Generated Interrupt (SGI) 11 */
#define GIC_IRQ_SGI12 12 /* Sofware Generated Interrupt (SGI) 12 */
#define GIC_IRQ_SGI13 13 /* Sofware Generated Interrupt (SGI) 13 */
#define GIC_IRQ_SGI14 14 /* Sofware Generated Interrupt (SGI) 14 */
#define GIC_IRQ_SGI15 15 /* Sofware Generated Interrupt (SGI) 15 */
#define GIC_IRQ_SGI0 0 /* Software Generated Interrupt (SGI) 0 */
#define GIC_IRQ_SGI1 1 /* Software Generated Interrupt (SGI) 1 */
#define GIC_IRQ_SGI2 2 /* Software Generated Interrupt (SGI) 2 */
#define GIC_IRQ_SGI3 3 /* Software Generated Interrupt (SGI) 3 */
#define GIC_IRQ_SGI4 4 /* Software Generated Interrupt (SGI) 4 */
#define GIC_IRQ_SGI5 5 /* Software Generated Interrupt (SGI) 5 */
#define GIC_IRQ_SGI6 6 /* Software Generated Interrupt (SGI) 6 */
#define GIC_IRQ_SGI7 7 /* Software Generated Interrupt (SGI) 7 */
#define GIC_IRQ_SGI8 8 /* Software Generated Interrupt (SGI) 8 */
#define GIC_IRQ_SGI9 9 /* Software Generated Interrupt (SGI) 9 */
#define GIC_IRQ_SGI10 10 /* Software Generated Interrupt (SGI) 10 */
#define GIC_IRQ_SGI11 11 /* Software Generated Interrupt (SGI) 11 */
#define GIC_IRQ_SGI12 12 /* Software Generated Interrupt (SGI) 12 */
#define GIC_IRQ_SGI13 13 /* Software Generated Interrupt (SGI) 13 */
#define GIC_IRQ_SGI14 14 /* Software Generated Interrupt (SGI) 14 */
#define GIC_IRQ_SGI15 15 /* Software Generated Interrupt (SGI) 15 */
#define GIC_IRQ_GTM 27 /* Global Timer (GTM) PPI(0) */
#define GIC_IRQ_FIQ 28 /* Fast Interrupt Request (nFIQ) PPI(1) */

6
arch/arm/src/c5471/c5471_ethernet.c
View file

@ -259,7 +259,7 @@
/* Bits 16-31: reserved */
#define ENET_MODO_FIFO_EN 0x00008000 /* Bit 15: Fifo enable */
/* Bits 8-14: reserved */
#define ENET_MODE_RJCT_SFE 0x00000080 /* Bit 7: Reject short frames durig receive */
#define ENET_MODE_RJCT_SFE 0x00000080 /* Bit 7: Reject short frames during receive */
#define ENET_MODE_DPNET 0x00000040 /* Bit 6: Demand priority networkd vs CSMA/CD */
#define ENET_MODE_MWIDTH 0x00000020 /* Bit 5: Select nibble mode MII port */
#define ENET_MODE_WRAP 0x00000010 /* Bit 4: Internal MAC loopback */
@ -725,7 +725,7 @@ static int c5471_mdread (int adr, int reg)
* end offers either the 10baseT or 100baseT electrical interface connecting
* to an RJ45 onboard network connector. The PHY transeiver has several
* internal registers allowing host configuration and status access. These
* internal registers are accessable by clocking serial data in/out of the
* internal registers are accessible by clocking serial data in/out of the
* MDIO pin of the LU3X31T-T64 chip. For c547X, the MDC and the MDIO pins
* are connected to the C547x GPIO15 and GPIO14 pins respectivley. Host
* software twiddles the GPIO pins appropriately to get data serially into
@ -1842,7 +1842,7 @@ static int c5471_ifup(struct net_driver_s *dev)
dev->d_ipaddr & 0xff, (dev->d_ipaddr >> 8) & 0xff,
(dev->d_ipaddr >> 16) & 0xff, dev->d_ipaddr >> 24);
/* Initilize Ethernet interface */
/* Initialize Ethernet interface */
c5471_reset(priv);

2
arch/arm/src/cxd56xx/Kconfig
View file

@ -46,7 +46,7 @@ config CXD56_RESET_ON_CRASH
default n
---help---
If selected the board_crashdump should reset the machine after
saveing the state of the machine
saving the state of the machine
comment "Basic Options"

2
arch/arm/src/cxd56xx/cxd56_backuplog.c
View file

@ -183,7 +183,7 @@ static int allocate_memory(size_t size)
*
* Description:
* Initialize the log header where the address and size of each log area
* are decribed. If the log header has been already configured in a wakeup
* are described. If the log header has been already configured in a wakeup
* from sleeping or reboot case, then do nothing and return OK.
*
* Returned Value:

4
arch/arm/src/cxd56xx/cxd56_cisif.c
View file

@ -331,7 +331,7 @@ static void cisif_ycc_axi_trdn_int(uint8_t code)
if (g_errint_receive)
{
/* In error occured case in the same frame, ignore */
/* In error occurred case in the same frame, ignore */
cisif_reg_write(CISIF_YCC_DREAD_CONT, 0);
return;
@ -380,7 +380,7 @@ static void cisif_jpg_axi_trdn_int(uint8_t code)
if (g_errint_receive)
{
/* In error occured case in the same frame, ignore */
/* In error occurred case in the same frame, ignore */
cisif_reg_write(CISIF_JPG_DREAD_CONT, 0);
return;

2
arch/arm/src/cxd56xx/cxd56_clock.c
View file

@ -177,7 +177,7 @@ static sem_t g_clockexc = SEM_INITIALIZER(1);
* swreset : SWRESET_SCU
* crgintmask : CRG_INT_CLR0, CRG_INT_STAT_RAW0
*
* Each member values are indicated the number of bit in apropriate registers.
* Each member values are indicated the number of bit in appropriate registers.
*/
#if defined(CONFIG_CXD56_SPI3)

2
arch/arm/src/cxd56xx/cxd56_cpupause.c
View file

@ -441,7 +441,7 @@ void up_send_irqreq(int idx, int irq, int cpu)
putreg32(1, CXD56_CPU_P2_INT + (4 * cpu));
/* Wait for the handler is excecuted on cpu */
/* Wait for the handler is executed on cpu */
spin_lock(&g_cpu_paused[cpu]);
spin_unlock(&g_cpu_paused[cpu]);

2
arch/arm/src/cxd56xx/cxd56_dmac.c
View file

@ -693,7 +693,7 @@ void weak_function up_dma_initialize(void)
*
* Input parameters:
* ch - DMA channel to use
* maxsize - Max size to be transfered in bytes
* maxsize - Max size to be transferred in bytes
*
* Returned Value:
* This function ALWAYS returns a non-NULL, void* DMA channel handle.

2
arch/arm/src/cxd56xx/cxd56_dmac.h
View file

@ -96,7 +96,7 @@ extern "C"
*
* Input parameters:
* ch - DMA channel to use
* maxsize - Max size to be transfered in bytes
* maxsize - Max size to be transferred in bytes
*
* Returned Value:
* This function ALWAYS returns a non-NULL, void* DMA channel handle.

2
arch/arm/src/cxd56xx/cxd56_gnss.c
View file

@ -379,7 +379,7 @@ static int (*g_cmdlist[CXD56_GNSS_IOCTL_MAX])(FAR struct file *filep,
* Description:
* Process CXD56_GNSS_IOCTL_START command.
* Start a positioning
* begining to search the satellites and measure the receiver position
* beginning to search the satellites and measure the receiver position
*
* Input Parameters:
* filep - File structure pointer

4
arch/arm/src/cxd56xx/cxd56_gnss_api.h
View file

@ -61,7 +61,7 @@
#define CXD56_GNSS_OPMOD_1PSS 5
/* Start a positioning
* begining to search the satellites and measure the receiver position
* beginning to search the satellites and measure the receiver position
*/
int GD_Start(uint8_t startMode);
@ -226,7 +226,7 @@ int GD_SetAcquist(FAR uint8_t *pAcquistData, uint16_t acquistSize);
int GD_SetTimeGps(FAR struct cxd56_gnss_date_s *date,
FAR struct cxd56_gnss_time_s *time);
/* Clear Receiver Infomation */
/* Clear Receiver Information */
int GD_ClearReceiverInfo(uint32_t type);

2
arch/arm/src/cxd56xx/cxd56_pmic.c
View file

@ -865,7 +865,7 @@ int cxd56_pmic_getchargevol(FAR int *voltage)
* Set charge voltage
*
* Input Parameter:
* voltage - Avalable values are every 50 between 4000 to 4400 (mv)
* voltage - Available values are every 50 between 4000 to 4400 (mv)
*
* Returned Value:
* Return 0 on success. Otherwise, return a negated errno.

2
arch/arm/src/cxd56xx/cxd56_pmic.h
View file

@ -530,7 +530,7 @@ int cxd56_pmic_getchargevol(FAR int *voltage);
* Set charge voltage
*
* Input Parameter:
* voltage - Avalable values are every 50 between 4000 to 4400 (mV)
* voltage - Available values are every 50 between 4000 to 4400 (mV)
*
* Returned Value:
* Return 0 on success. Otherwise, return a negated errno.

2
arch/arm/src/cxd56xx/cxd56_sdhci.c
View file

@ -2294,7 +2294,7 @@ static int cxd56_sdio_waitresponse(FAR struct sdio_dev_s *dev, uint32_t cmd)
*
* Returned Value:
* Number of bytes sent on success; a negated errno on failure. Here a
* failure means only a faiure to obtain the requested reponse (due to
* failure means only a faiure to obtain the requested response (due to
* transport problem -- timeout, CRC, etc.). The implementation only
* assures that the response is returned intacta and does not check errors
* within the response itself.

2
arch/arm/src/cxd56xx/cxd56_usbdev.c
View file

@ -379,7 +379,7 @@ struct cxd56_usbdev_s
* the SETUP command can be processed.
*
* ep0datlen
* Lenght of OUT DATA received in ep0data[]
* Length of OUT DATA received in ep0data[]
*/
struct usb_ctrlreq_s ctrl; /* Last EP0 request */

2
arch/arm/src/dm320/dm320_ahb.h
View file

@ -48,7 +48,7 @@
#define DM320_AHB_SDRAMSA (DM320_AHB_VADDR+0x0f00) /* SDRAM start address */
#define DM320_AHB_SDRAMEA (DM320_AHB_VADDR+0x0f04) /* SDRAM end address */
#define DM320_AHB_BUSCONTROL (DM320_AHB_VADDR+0x0f08) /* Bus endianess control */
#define DM320_AHB_BUSCONTROL (DM320_AHB_VADDR+0x0f08) /* Bus endianness control */
#define DM320_AHB_RSV1 (DM320_AHB_VADDR+0x0f0c) /* Reserved */
#define DM320_AHB_USBCTL (DM320_AHB_VADDR+0x0f10) /* USB control register (ES1.1) */

2
arch/arm/src/efm32/efm32_spi.c
View file

@ -825,7 +825,7 @@ static uint32_t spi_setfrequency(struct spi_dev_s *dev, uint32_t frequency)
*
* One can possibly factorize 128 and br. However, since the last
* 6 bits of CLKDIV are don't care, we can base our integer arithmetic
* on the below formula without loosing any extra precision:
* on the below formula without losing any extra precision:
*
* CLKDIV / 64 = (2 * fHFPERCLK)/br - 4
*

8
arch/arm/src/efm32/efm32_usbdev.c
View file

@ -454,12 +454,12 @@ struct efm32_usbdev_s
* the accompanying EP0 IN data in ep0data[] before the SETUP command is
* processed.
*
* For IN SETUP requests, the DATA phase will occurr AFTER the SETUP
* For IN SETUP requests, the DATA phase will occur AFTER the SETUP
* control request is processed. In that case, ep0data[] may be used as
* the response buffer.
*
* ep0datlen
* Lenght of OUT DATA received in ep0data[] (Not used with OUT data)
* Length of OUT DATA received in ep0data[] (Not used with OUT data)
*/
struct usb_ctrlreq_s ctrlreq;
@ -5206,7 +5206,7 @@ static void efm32_hwinitialize(FAR struct efm32_usbdev_s *priv)
*/
/* I never saw this in original EFM32 lib
* and in refrence manual I found:
* and in reference manual I found:
* "Non-periodic TxFIFO Empty Level (can be enabled only when the core is
* operating in Slave mode as a host.)"
*/
@ -5531,7 +5531,7 @@ void up_usbuninitialize(void)
usbtrace(TRACE_DEVUNINIT, 0);
/* To be sure that usb ref are writen, turn on USB clocking */
/* To be sure that usb ref are written, turn on USB clocking */
modifyreg32(EFM32_CMU_HFCORECLKEN0, 0,
CMU_HFCORECLKEN0_USB | CMU_HFCORECLKEN0_USBC);

4
arch/arm/src/efm32/efm32_usbhost.c
View file

@ -3204,7 +3204,7 @@ static inline void efm32_gint_ptxfeisr(FAR struct efm32_usbhost_s *priv)
chan->xfrd += chan->inflight;
chan->inflight = 0;
/* If we have now transfered the entire buffer, then this transfer is
/* If we have now transferred the entire buffer, then this transfer is
* complete (this case really should never happen because we disable
* the PTXFE interrupt on the final packet).
*/
@ -3742,7 +3742,7 @@ static void efm32_txfe_enable(FAR struct efm32_usbhost_s *priv, int chidx)
uint32_t regval;
/* Disable all interrupts so that we have exclusive access to the GINTMSK
* (it would be sufficent just to disable the GINT interrupt).
* (it would be sufficient just to disable the GINT interrupt).
*/
flags = enter_critical_section();

2
arch/arm/src/efm32/hardware/efm32_pcnt.h
View file

@ -90,7 +90,7 @@
#define EFM32_PCNT_ROUTE_OFFSET 0x0028 /* I/O Routing Register */
#define EFM32_PCNT_FREEZE_OFFSET 0x002c /* Freeze Register */
#define EFM32_PCNT_SYNCBUSY_OFFSET 0x0030 /* Synchronization Busy Register */
#define EFM32_PCNT_AUXCNT_OFFSET 0x0038 /* Auxillary Counter Value Register */
#define EFM32_PCNT_AUXCNT_OFFSET 0x0038 /* Auxiliary Counter Value Register */
#define EFM32_PCNT_INPUT_OFFSET 0x003c /* PCNT Input Register */
/* PCNT Register Addresses *****************************************************************************************************/

2
arch/arm/src/imx1/imx_serial.c
View file

@ -514,7 +514,7 @@ static int up_setup(struct uart_dev_s *dev)
ucr2 &= ~UART_UCR2_IRTS;
/* CTS controled by Rx FIFO */
/* CTS controlled by Rx FIFO */
ucr2 |= UART_UCR2_CTSC;

2
arch/arm/src/imx1/imx_spi.c
View file

@ -115,7 +115,7 @@ struct imx_spidev_s
/* These are functions pointers that are configured to perform the
* appropriate transfer for the particular kind of exchange that is
* occurring. Differnt functions may be selected depending on (1)
* occurring. Different functions may be selected depending on (1)
* if the tx or txbuffer is NULL and depending on the number of bits
* per word.
*/

2
arch/arm/src/imx6/imx_ecspi.c
View file

@ -164,7 +164,7 @@ struct imx_spidev_s
/* These are functions pointers that are configured to perform the
* appropriate transfer for the particular kind of exchange that is
* occurring. Differnt functions may be selected depending on (1)
* occurring. Different functions may be selected depending on (1)
* if the tx or txbuffer is NULL and depending on the number of bits
* per word.
*/

2
arch/arm/src/imx6/imx_lowputc.c
View file

@ -367,7 +367,7 @@ int imx_uart_configure(uint32_t base, FAR const struct uart_config_s *config)
#if 0
if (config->hwfc)
{
/* CTS controled by Rx FIFO */
/* CTS controlled by Rx FIFO */
ucr2 |= UART_UCR2_CTSC;

2
arch/arm/src/imxrt/hardware/imxrt_usdhc.h
View file

@ -468,7 +468,7 @@
#define USDHC_DL_CTRL_SLV_UPDINT_SHIFT (20) /* Bits 20-27: DLL Control SLV Update Interval */
#define USDHC_DL_CTRL_SLV_UPDINT_MASK (0xff << USDHC_DL_CTRL_SLV_UPDINT_SHIFT)
# define USDHC_DL_CTRL_SLV_UPDINT(n) ((n) << USDHC_DL_CTRL_SLV_UPDINT_SHIFT)
#define USDHC_DL_CTRL_REF_UPDINT_SHIFT (28) /* Bits 28-31: DLL Control Refernce Update Interval */
#define USDHC_DL_CTRL_REF_UPDINT_SHIFT (28) /* Bits 28-31: DLL Control Reference Update Interval */
#define USDHC_DL_CTRL_REF_UPDINT_MASK (0xf << USDHC_DL_CTRL_REF_UPDINT_SHIFT)
# define USDHC_DL_CTRL_REF_UPDINT(n) ((n)<< USDHC_DL_CTRL_REF_UPDINT_SHIFT)

2
arch/arm/src/imxrt/imxrt_ehci.c
View file

@ -3577,7 +3577,7 @@ static int imxrt_rh_enumerate(FAR struct usbhost_connection_s *conn,
* 01b K-state Low-speed device, release ownership of port
*
* NOTE: Low-speed devices could be detected by examining the PORTSC PSPD
* field after resetting the device. The more convential way here, however,
* field after resetting the device. The more conventional way here, however,
* also appears to work.
*/

2
arch/arm/src/kinetis/hardware/kinetis_rtc.h
View file

@ -52,7 +52,7 @@
/* Register Offsets *****************************************************************/
/* NXP/Freescale has familes and technology generations (sometimes seen as processor
/* NXP/Freescale has families and technology generations (sometimes seen as processor
* speed). These are organized into feature families, and faster speeds sometimes
* have extended features. Families are K02 K10 K20 K22 K24 K30 K40 K50 K60 K64 K65
* K66 K70 K80

4
arch/arm/src/kinetis/hardware/kinetis_usbhs.h
View file

@ -511,9 +511,9 @@
/* Master Interface Data Burst Size Register */
/* Bits 16-31: Reserved */
#define USBHS_BURSTSIZE_TXPBURST_SHIFT (8) /* Bits 8-15: Programable TX Burst length */
#define USBHS_BURSTSIZE_TXPBURST_SHIFT (8) /* Bits 8-15: Programmable TX Burst length */
#define USBHS_BURSTSIZE_TXPBURST_MASK (0xff << USBHS_BURSTSIZE_TXPBURST_SHIFT)
#define USBHS_BURSTSIZE_RXPBURST_SHIFT (0) /* Bits 0-7: Programable RX Burst length */
#define USBHS_BURSTSIZE_RXPBURST_SHIFT (0) /* Bits 0-7: Programmable RX Burst length */
#define USBHS_BURSTSIZE_RXPBURST_MASK (0xff << USBHS_BURSTSIZE_RXPBURST_SHIFT)
/* Transmit FIFO Tuning Control Register */

2
arch/arm/src/kinetis/kinetis_enet.c
View file

@ -999,7 +999,7 @@ static void kinetis_txtimeout_work(FAR void *arg)
net_lock();
NETDEV_TXTIMEOUTS(&priv->dev);
/* Take the interface down and bring it back up. The is the most agressive
/* Take the interface down and bring it back up. The is the most aggressive
* hardware reset.
*/

4
arch/arm/src/kinetis/kinetis_sdhc.c
View file

@ -1412,7 +1412,7 @@ static void kinetis_frequency(FAR struct sdio_dev_s *dev, uint32_t frequency)
*
* SDCLK frequency = (base clock) / (prescaler * divisor)
*
* The prescaler is avalable only for the values: 2, 4, 8, 16, 32, 64, 128,
* The prescaler is available only for the values: 2, 4, 8, 16, 32, 64, 128,
* and 256. Pick the smallest value of SDCLKFS that would result in an
* in-range frequency.
*
@ -2135,7 +2135,7 @@ static int kinetis_waitresponse(FAR struct sdio_dev_s *dev, uint32_t cmd)
*
* Returned Value:
* Number of bytes sent on success; a negated errno on failure. Here a
* failure means only a faiure to obtain the requested reponse (due to
* failure means only a faiure to obtain the requested response (due to
* transport problem -- timeout, CRC, etc.). The implementation only
* assures that the response is returned intacta and does not check errors
* within the response itself.

2
arch/arm/src/kinetis/kinetis_usbdev.c
View file

@ -3653,7 +3653,7 @@ static int khci_epbdtstall(struct usbdev_ep_s *ep, bool resume, bool epin)
/* Check for the EP0 OUT endpoint. This is a special case because we
* need to set it up to receive the next setup packet (Hmmm... what
* if there are queued outgoing reponses. We need to revisit this.)
* if there are queued outgoing responses. We need to revisit this.)
*/
if (epno == 0 && !epin)

2
arch/arm/src/lc823450/lc823450_dvfs2.c
View file

@ -488,7 +488,7 @@ uint32_t lc823450_get_apb(void)
/****************************************************************************
* Name: lc823450_dvfs_tick_callback
* This callback is called in the timer interupt on CPU0
* This callback is called in the timer interrupt on CPU0
****************************************************************************/
void lc823450_dvfs_tick_callback(void)

2
arch/arm/src/lc823450/lc823450_ipl2.c
View file

@ -332,7 +332,7 @@ static int check_diskformat(void)
return 0;
}
/* If part2 has MBR signature, this eMMC was formated by PC.
/* If part2 has MBR signature, this eMMC was formatted by PC.
* This means the set is just after writing IPL2.
*/

2
arch/arm/src/lc823450/lc823450_spi.c
View file

@ -347,7 +347,7 @@ static uint16_t spi_send(FAR struct spi_dev_s *dev, uint16_t wd)
modifyreg32(LC823450_SPI_SMD, 0, SPI_SMD_SSTR);
/* Wait for Tranfer done */
/* Wait for Transfer done */
while ((getreg32(LC823450_SPI_ISR) & SPI_ISR_SPIF) == 0)
;

2
arch/arm/src/lc823450/lc823450_usbdev.c
View file

@ -511,7 +511,7 @@ static int lc823450_epclearreq(struct usbdev_ep_s *ep)
q_ent = sq_remlast(&privep->req_q);
req = &container_of(q_ent, struct lc823450_req_s, q_ent)->req;
/* return reqbuf to funciton driver */
/* return reqbuf to function driver */
req->result = -ESHUTDOWN;
req->callback(ep, req);

4
arch/arm/src/lpc17xx_40xx/hardware/lpc178x_40xx_syscon.h
View file

@ -338,7 +338,7 @@
#define SYSCON_PBOOST_BOOST_SHIFT (0) /* Bits 0-1: Boost control bits */
#define SYSCON_PBOOST_BOOST_MASK (3 << SYSCON_PBOOST_BOOST_SHIFT)
#define SYSCON_PBOOST_BOOST_OFF (0) /* Boost OFF, operation must be below 100MHz */
#define SYSCON_PBOOST_BOOST_ON (3) /* Boost ON, operation upto 120MHz allowed */
#define SYSCON_PBOOST_BOOST_ON (3) /* Boost ON, operation up to 120MHz allowed */
/* Bits 2-31: Reserved */
/* SPIFI Clock Selection Register */
@ -613,7 +613,7 @@
#define SYSCON_EMCCAL_START_SHIFT (14) /* Bit 14: Start control bit for EMC calibration counter */
#define SYSCON_EMCCAL_START_MASK (1 << SYSCON_EMCCAL_START_SHIFT)
# define SYSCON_EMCCAL_START (1) /* Automatically cleared when measurement is done */
#define SYSCON_EMCCAL_DONE_SHIFT (15) /* Bit 15: Measurement completetion flag bit */
#define SYSCON_EMCCAL_DONE_SHIFT (15) /* Bit 15: Measurement completion flag bit */
#define SYSCON_EMCCAL_DONE_MASK (1 << SYSCON_EMCCAL_DONE_SHIFT)
/* Automatically cleared when START bit is set */
/* Bits 16-31: Reserved */

6
arch/arm/src/lpc17xx_40xx/hardware/lpc17_40_usb.h
View file

@ -298,7 +298,7 @@
#define USBOTG_STCTRL_PORTFUNC_SHIFT (0) /* Bits 0-1: Controls port function */
#define USBOTG_STCTRL_PORTFUNC_MASK (3 << USBOTG_STCTRL_PORTFUNC_SHIFT)
# define USBOTG_STCTRL_PORTFUNC_HNPOK (1 << USBOTG_STCTRL_PORTFUNC_SHIFT) /* HNP suceeded */
# define USBOTG_STCTRL_PORTFUNC_HNPOK (1 << USBOTG_STCTRL_PORTFUNC_SHIFT) /* HNP succeeded */
#define USBOTG_STCTRL_TMRSCALE_SHIFT (2) /* Bits 2-3: Timer scale selection */
#define USBOTG_STCTRL_TMRSCALE_MASK (3 << USBOTG_STCTRL_TMR_SCALE_SHIFT)
# define USBOTG_STCTRL_TMRSCALE_10US (0 << USBOTG_STCTRL_TMR_SCALE_SHIFT) /* 10uS (100 KHz) */
@ -643,7 +643,7 @@
#define CMD_USBDEV_SETMODE (0x00f3)
#define CMD_USBDEV_READFRAMENO (0x00f5)
#define CMD_USBDEV_READTESTREG (0x00fd)
#define CMD_USBDEV_SETSTATUS (0x01fe) /* Bit 8 set to distingish get from set */
#define CMD_USBDEV_SETSTATUS (0x01fe) /* Bit 8 set to distinguish get from set */
#define CMD_USBDEV_GETSTATUS (0x00fe)
#define CMD_USBDEV_GETERRORCODE (0x00ff)
#define CMD_USBDEV_READERRORSTATUS (0x00fb)
@ -652,7 +652,7 @@
#define CMD_USBDEV_EPSELECT (0x0000)
#define CMD_USBDEV_EPSELECTCLEAR (0x0040)
#define CMD_USBDEV_EPSETSTATUS (0x0140) /* Bit 8 set to distingish get from selectclear */
#define CMD_USBDEV_EPSETSTATUS (0x0140) /* Bit 8 set to distinguish get from selectclear */
#define CMD_USBDEV_EPCLRBUFFER (0x00f2)
#define CMD_USBDEV_EPVALIDATEBUFFER (0x00fa)

2
arch/arm/src/lpc17xx_40xx/lpc17_40_adc.c
View file

@ -475,7 +475,7 @@ static int adc_interrupt(int irq, void *context, FAR void *arg)
FAR struct up_dev_s *priv = (FAR struct up_dev_s *)g_adcdev.ad_priv;
volatile uint32_t regVal, regVal2, regVal3;
/* Verify that an interrupt has actually occured */
/* Verify that an interrupt has actually occurred */
regVal2 = getreg32(LPC17_40_ADC_STAT); /* Read ADSTAT will clear the interrupt flag */
if ((regVal2) & (1 << 16))

2
arch/arm/src/lpc17xx_40xx/lpc17_40_lcd.c
View file

@ -366,7 +366,7 @@ static int lpc17_40_putcmap(FAR struct fb_vtable_s *vtable,
(uint32_t)cmap->blue[i+1] << LCD_PAL_B1_SHIFT);
}
/* Save the new pallete value */
/* Save the new palette value */
*pal++ = (rgb0 | rgb1);
}

4
arch/arm/src/lpc17xx_40xx/lpc17_40_sdcard.c
View file

@ -1970,7 +1970,7 @@ static int lpc17_40_waitresponse(FAR struct sdio_dev_s *dev, uint32_t cmd)
*
* Returned Value:
* Number of bytes sent on success; a negated errno on failure. Here a
* failure means only a faiure to obtain the requested reponse (due to
* failure means only a faiure to obtain the requested response (due to
* transport problem -- timeout, CRC, etc.). The implementation only
* assures that the response is returned intacta and does not check errors
* within the response itself.
@ -2387,7 +2387,7 @@ static void lpc17_40_callbackenable(FAR struct sdio_dev_s *dev,
*
* Input Parameters:
* dev - Device-specific state data
* callback - The funtion to call on the media change
* callback - The function to call on the media change
* arg - A caller provided value to return with the callback
*
* Returned Value:

2
arch/arm/src/lpc17xx_40xx/lpc17_40_spi.h
View file

@ -150,7 +150,7 @@ void spi_flush(FAR struct spi_dev_s *dev);
*
* Input Parameters:
* dev - Device-specific state data
* callback - The funtion to call on the media change
* callback - The function to call on the media change
* arg - A caller provided value to return with the callback
*
* Returned Value:

2
arch/arm/src/lpc17xx_40xx/lpc17_40_ssp.h
View file

@ -156,7 +156,7 @@ void ssp_flush(FAR struct spi_dev_s *dev);
*
* Input Parameters:
* dev - Device-specific state data
* callback - The funtion to call on the media change
* callback - The function to call on the media change
* arg - A caller provided value to return with the callback
*
* Returned Value:

4
arch/arm/src/lpc17xx_40xx/lpc17_40_usbdev.c
View file

@ -2235,7 +2235,7 @@ static int lpc17_40_usbinterrupt(int irq, FAR void *context, FAR void *arg)
{
/* On the first time through the loop, pending will be
* the bitset of high priority pending interrupts; on the
* second time throught it will be the bitset of low
* second time through it will be the bitset of low
* priority interrupts.
*/
@ -2380,7 +2380,7 @@ static int lpc17_40_usbinterrupt(int irq, FAR void *context, FAR void *arg)
{
/* On the first time through the loop, pending will be
* the bitset of high priority pending interrupts; on the
* second time throught it will be the bitset of low
* second time through it will be the bitset of low
* priority interrupts. Note that EP0 IN and OUT are
* omitted.
*/

4
arch/arm/src/lpc214x/lpc214x_usbdev.c
View file

@ -2198,7 +2198,7 @@ static int lpc214x_usbinterrupt(int irq, FAR void *context, FAR void *arg)
{
/* On the first time through the loop, pending will be
* the bitset of high priority pending interrupts; on the
* second time throught it will be the bitset of low
* second time through it will be the bitset of low
* priority interrupts.
*/
@ -2342,7 +2342,7 @@ static int lpc214x_usbinterrupt(int irq, FAR void *context, FAR void *arg)
{
/* On the first time through the loop, pending will be
* the bitset of high priority pending interrupts; on the
* second time throught it will be the bitset of low
* second time through it will be the bitset of low
* priority interrupts. Note that EP0 IN and OUT are
* omitted.
*/

26
arch/arm/src/lpc31xx/lpc31_cgu.h
View file

@ -1241,7 +1241,7 @@
#define CGU_FDC17_RUN (1 << 0) /* Bit 0: Enable fractional divider */
#define CGU_FDC_FIELDWIDTH 8 /* MSUB and MADD fields are 8-bits in width */
#define CGU_FDC17_FIELDWIDTH 13 /* Exept for FDC17 which is 13-bits in width */
#define CGU_FDC17_FIELDWIDTH 13 /* Except for FDC17 which is 13-bits in width */
/* Dynamic Fractional Divider registers DYNFDC0 to DYNFDC6, addresses 0x13004578 to 0x13004590 */
@ -1566,44 +1566,44 @@ Nandflash Controller */
#define CGU_HPREQ_N (1 << 1) /* Bit 1: Pre-divider ratio change request */
#define CGU_HPREQ_M (1 << 0) /* Bit 0: Feedback divider ratio change request */
/* HP0 Bandwith Selection register HP0_INSELR, address 0x13004d10,
* HP1 bandwith Selection register HP1_INSELR, address 0x13004d48
/* HP0 Bandwidth Selection register HP0_INSELR, address 0x13004d10,
* HP1 bandwidth Selection register HP1_INSELR, address 0x13004d48
*/
#define CGU_HPINSELR_SHIFT (0) /* Bits 0-3: Pins to select the bandwidth */
#define CGU_HPINSELR_MASK (15 << CGU_HPINSELR_SHIFT)
/* HP0 Bandwith Selection register HP0_INSELI, address 0x13004d14,
* HP1 bandwith Selection register HP1_INSELI, address 0x13004d4c
/* HP0 Bandwidth Selection register HP0_INSELI, address 0x13004d14,
* HP1 bandwidth Selection register HP1_INSELI, address 0x13004d4c
*/
#define CGU_HPINSELI_SHIFT (0) /* Bits 0-5: Bandwidth selection register of HP0/1 PLL */
#define CGU_HPINSELI_MASK (63 << CGU_HPINSELI_SHIFT)
/* HP0 Bandwith Selection register HP0_INSELP, address 0x13004d18,
* HP1 bandwith Selection register HP1_INSELP, address 0x13004d50
/* HP0 Bandwidth Selection register HP0_INSELP, address 0x13004d18,
* HP1 bandwidth Selection register HP1_INSELP, address 0x13004d50
*/
#define CGU_HPINSELP_SHIFT (0) /* Bits 0-4: Bandwidth selection register of HP0/1 PLL */
#define CGU_HPINSELP_MASK (31 << CGU_HPINSELP_SHIFT)
/* HP0 Bandwith Selection register HP0_SELR, address 0x13004d1c,
* HP1 bandwith Selection register HP1_SELR, address 0x13004d54
/* HP0 Bandwidth Selection register HP0_SELR, address 0x13004d1c,
* HP1 bandwidth Selection register HP1_SELR, address 0x13004d54
*/
#define CGU_HPSELR_SHIFT (0) /* Bits 0-3: Bandwidth selection register of HP0/1 PLL */
#define CGU_HPSELR_MASK (15 << CGU_HPSELR_SHIFT)
/* HP0 Bandwith Selection register HP0_SELI, address 0x13004d20
* HP1 bandwith Selection register HP1_SELI, address 0x13004d58
/* HP0 Bandwidth Selection register HP0_SELI, address 0x13004d20
* HP1 bandwidth Selection register HP1_SELI, address 0x13004d58
*/
#define CGU_HPSELI_SHIFT (0) /* Bits 0-5: Bandwidth selection register of HP0/1 PLL */
#define CGU_HPSELI_MASK (63 << CGU_HPSELI_SHIFT)
/* HP0 Bandwith Selection register HP0_SELP, address 0x13004d24,
* HP1 bandwith Selection register HP1_SELP, address 0x13004d5c
/* HP0 Bandwidth Selection register HP0_SELP, address 0x13004d24,
* HP1 bandwidth Selection register HP1_SELP, address 0x13004d5c
*/
#define CGU_HPSELP_SHIFT (0) /* Bits 0-4: Bandwidth selection register of HP0/1 PLL */

2
arch/arm/src/lpc31xx/lpc31_ehci.c
View file

@ -3565,7 +3565,7 @@ static int lpc31_rh_enumerate(FAR struct usbhost_connection_s *conn,
* 01b K-state Low-speed device, release ownership of port
*
* NOTE: Low-speed devices could be detected by examining the PORTSC PSPD
* field after resetting the device. The more convential way here, however,
* field after resetting the device. The more conventional way here, however,
* also appears to work.
*/

2
arch/arm/src/lpc31xx/lpc31_i2c.h
View file

@ -158,7 +158,7 @@
#define I2C_CLKLO_MASK (0x3ff << I2C_CLKLO_SHIFT)
/* I2Cn Slave Addres I2C0_ADDR, address 0x1300a014, I2C1_ADDR, address 0x1300a414 */
/* I2Cn Slave Address I2C0_ADDR, address 0x1300a014, I2C1_ADDR, address 0x1300a414 */
#define I2C_ADR_SHIFT (0) /* Bits 0-9: I2C bus slave address */
#define I2C_ADR_MASK (0x3ff << I2C_ADR_SHIFT)

2
arch/arm/src/lpc31xx/lpc31_nand.h
View file

@ -236,7 +236,7 @@
# define NAND_CONFIG_LC_0WAITSTATES (0 << NAND_CONFIG_LC_SHIFT)
# define NAND_CONFIG_LC_1WAITSTATES (1 << NAND_CONFIG_LC_SHIFT)
# define NAND_CONFIG_LC_2WAITSTATES (2 << NAND_CONFIG_LC_SHIFT)
#define NAND_CONFIG_ES (1 << 4) /* Bit 4: Endianess setting */
#define NAND_CONFIG_ES (1 << 4) /* Bit 4: Endianness setting */
#define NAND_CONFIG_DE (1 << 3) /* Bit 3: DMA external enable */
#define NAND_CONFIG_AO (1 << 2) /* Bit 2: AES on (LPC3154 only) */
#define NAND_CONFIG_WD (1 << 1) /* Bit 1: Wide device */

2
arch/arm/src/lpc31xx/lpc31_pllconfig.c
View file

@ -69,7 +69,7 @@
* Name: lpc31_switchdomains
*
* Description:
* Temporarily switch the referemce clock of all domains whose selected
* Temporarily switch the reference clock of all domains whose selected
* input is the PLL-to-be configured .
*
****************************************************************************/

2
arch/arm/src/lpc31xx/lpc31_spi.c
View file

@ -685,7 +685,7 @@ static void spi_setbits(FAR struct spi_dev_s *dev, int nbits)
static uint8_t spi_status(FAR struct spi_dev_s *dev, uint32_t devid)
{
/* FIXME: is there anyway to determine this
* it should probably be board dependant anyway */
* it should probably be board dependent anyway */
return SPI_STATUS_PRESENT;
}

2
arch/arm/src/lpc43xx/lpc43_ehci.c
View file

@ -3409,7 +3409,7 @@ static int lpc43_rh_enumerate(FAR struct usbhost_connection_s *conn,
* 01b K-state Low-speed device, release ownership of port
*
* NOTE: Low-speed devices could be detected by examining the PORTSC PSPD
* field after resetting the device. The more convential way here, however,
* field after resetting the device. The more conventional way here, however,
* also appears to work.
*/

4
arch/arm/src/lpc43xx/lpc43_sdmmc.c
View file

@ -1952,7 +1952,7 @@ static int lpc43_waitresponse(FAR struct sdio_dev_s *dev, uint32_t cmd)
*
* Returned Value:
* Number of bytes sent on success; a negated errno on failure. Here a
* failure means only a faiure to obtain the requested reponse (due to
* failure means only a faiure to obtain the requested response (due to
* transport problem -- timeout, CRC, etc.). The implementation only
* assures that the response is returned intacta and does not check errors
* within the response itself.
@ -2373,7 +2373,7 @@ static void lpc43_callbackenable(FAR struct sdio_dev_s *dev,
*
* Input Parameters:
* dev - Device-specific state data
* callback - The funtion to call on the media change
* callback - The function to call on the media change
* arg - A caller provided value to return with the callback
*
* Returned Value:

2
arch/arm/src/lpc43xx/lpc43_start.c
View file

@ -102,7 +102,7 @@
*
* Description:
* Set the shadow register to 0x1040:0000 and the VTOR to 0x0000:0000 so
* that any exceptions (particulary things like hard faults) that occur
* that any exceptions (particularly things like hard faults) that occur
* before we are initialized are caught by the BOOT ROM.
*
****************************************************************************/

2
arch/arm/src/lpc43xx/spifi/changelog.txt
View file

@ -91,7 +91,7 @@ Change Log:
module.
2. Added support for S25FL129P (256kB sectors).
3. Verified S25FL129P 64kB sectors variant.
4. Renamed familes to indicate functionality in place of root device.
4. Renamed families to indicate functionality in place of root device.
(This was done to avoid confusion over where devices reside).
5. Family cleanup to aid in comparison.
6. Removed Chip.h dependency.

2
arch/arm/src/lpc43xx/spifi/inc/private/spifilib_chiphw.h
View file

@ -75,7 +75,7 @@ typedef struct LPC_SPIFI_CHIPHW {
volatile uint32_t STAT; /**< SPIFI status register */
} LPC_SPIFI_CHIPHW_T;
/** @defgroup LPCSPIFILIB_HW_PRIM LPCSPIFILIB primative API functions
/** @defgroup LPCSPIFILIB_HW_PRIM LPCSPIFILIB primitive API functions
* @{
*/

2
arch/arm/src/lpc43xx/spifi/src/spifilib_dev_common.c
View file

@ -637,7 +637,7 @@ SPIFI_ERR_T spifiDevSetOpts(SPIFI_HANDLE_T *pHandle, uint32_t options, uint8_t s
/* default to not supported */
SPIFI_ERR_T retValue = SPIFI_ERR_NOTSUPPORTED;
/* If changing any of the high speed modes process seperately */
/* If changing any of the high speed modes process separately */
if (options & (SPIFI_CAP_DUAL_READ | SPIFI_CAP_DUAL_WRITE | SPIFI_CAP_QUAD_READ | SPIFI_CAP_QUAD_WRITE)) {
uint32_t hsOptions;
uint8_t memMode;

2
arch/arm/src/lpc54xx/lpc54_i2c_master.c
View file

@ -393,7 +393,7 @@ static void lpc54_i2c_xfrsetup(struct lpc54_i2cdev_s *priv)
if ((msg->flags & I2C_M_NOSTART) != 0)
{
/* Start condition will be ommited. Begin the tranfer in the data
/* Start condition will be omitted. Begin the transfer in the data
* phase.
*/

2
arch/arm/src/lpc54xx/lpc54_lcd.c
View file

@ -349,7 +349,7 @@ static int lpc54_putcmap(FAR struct fb_vtable_s *vtable,
(uint32_t)cmap->blue[i+1] << LCD_PAL_B1_SHIFT);
}
/* Save the new pallete value */
/* Save the new palette value */
*pal++ = (rgb0 | rgb1);
}

4
arch/arm/src/lpc54xx/lpc54_sdmmc.c
View file

@ -1952,7 +1952,7 @@ static int lpc54_waitresponse(FAR struct sdio_dev_s *dev, uint32_t cmd)
*
* Returned Value:
* Number of bytes sent on success; a negated errno on failure. Here a
* failure means only a faiure to obtain the requested reponse (due to
* failure means only a faiure to obtain the requested response (due to
* transport problem -- timeout, CRC, etc.). The implementation only
* assures that the response is returned intacta and does not check errors
* within the response itself.
@ -2373,7 +2373,7 @@ static void lpc54_callbackenable(FAR struct sdio_dev_s *dev,
*
* Input Parameters:
* dev - Device-specific state data
* callback - The funtion to call on the media change
* callback - The function to call on the media change
* arg - A caller provided value to return with the callback
*
* Returned Value:

2
arch/arm/src/max326xx/max32660/max32660_rtc.c
View file

@ -562,7 +562,7 @@ int max326_rtc_setalarm(FAR struct timespec *ts, alm_callback_t cb, FAR void *ar
goto errout_with_lock;
}
/* Get the ALARM delay betwen now and the alarm time */
/* Get the ALARM delay between now and the alarm time */
b32delay = b32alarm - b32now;

2
arch/arm/src/nrf52/hardware/nrf52_radio.h
View file

@ -481,7 +481,7 @@
/* RXADDRESSES Register */
#define RADIO_RXADDRESSES_ADDR(i) (1 << (i)) /* Bits 0-7: Enable or disable reception on logical addres i */
#define RADIO_RXADDRESSES_ADDR(i) (1 << (i)) /* Bits 0-7: Enable or disable reception on logical address i */
/* CRCCNF Register */

2
arch/arm/src/nrf52/hardware/nrf52_saadc.h
View file

@ -72,7 +72,7 @@
#define NRF52_SAADC_CHLIMIT_OFFSET(x) (0x51c + (x + 0x10)) /* High/low limits for event monitoring of a CH[x] */
#define NRF52_SAADC_RESOLUTION_OFFSET 0x05f0 /* Resolution configuration */
#define NRF52_SAADC_OVERSAMPLE_OFFSET 0x05f4 /* Oversampling configuration */
#define NRF52_SAADC_SAMPLERATE_OFFSET 0x05f8 /* Controls normal or continous sample rate */
#define NRF52_SAADC_SAMPLERATE_OFFSET 0x05f8 /* Controls normal or continuous sample rate */
#define NRF52_SAADC_PTR_OFFSET 0x062c /* Data pointer */
#define NRF52_SAADC_MAXCNT_OFFSET 0x0630 /* Maximum number of 16-bit samples */
#define NRF52_SAADC_AMOUNT_OFFSET 0x0634 /* Number of 16-bit samples written to buffer */

2
arch/arm/src/nrf52/nrf52_spi.c
View file

@ -850,7 +850,7 @@ static void nrf52_spi_exchange(FAR struct spi_dev_s *dev,
nrf52_spi_putreg(priv, NRF52_SPIM_EVENTS_STOPPED_OFFSET, 0);
/* Clear RX/TX DMA after tranfer */
/* Clear RX/TX DMA after transfer */
nrf52_spi_putreg(priv, NRF52_SPIM_RXDPTR_OFFSET, 0);
nrf52_spi_putreg(priv, NRF52_SPIM_RXDMAXCNT_OFFSET, 0);

2
arch/arm/src/sam34/hardware/sam_acc.h
View file

@ -94,7 +94,7 @@
# define ACC_MR_SELMINUS_AD3 (7 << ACC_MR_SELMINUS_SHIFT) /* Select AD3 */
#define ACC_MR_SELPLUS_SHIFT (4) /* Bits 4-6: Selection for plus comparator input */
#define ACC_MR_SELPLUS_MASK (7 << ACC_MR_SELPLUS_SHIFT)
# define ACC_MR_SELPLUS_AD(n) ((uint32_t)(n) << ACC_MR_SELPLUS_SHIFT) /* Select ADn, n=0-7 */
# define ACC_MR_SELPLUS_AD(n) ((uint32_t)(n) << ACC_MR_SELPLUS_SHIFT) /* Select and, n=0-7 */
# define ACC_MR_SELPLUS_AD0 (0 << ACC_MR_SELPLUS_SHIFT) /* Select AD0 */
# define ACC_MR_SELPLUS_AD1 (1 << ACC_MR_SELPLUS_SHIFT) /* Select AD1 */
# define ACC_MR_SELPLUS_AD2 (2 << ACC_MR_SELPLUS_SHIFT) /* Select AD2 */

2
arch/arm/src/sam34/sam3u_gpio.h
View file

@ -108,7 +108,7 @@
* .... .... V... ....
*/
#define GPIO_OUTPUT_SET (1 << 7) /* Bit 7: Inital value of output */
#define GPIO_OUTPUT_SET (1 << 7) /* Bit 7: Initial value of output */
#define GPIO_OUTPUT_CLEAR (0)
/* This identifies the GPIO port:

2
arch/arm/src/sam34/sam3x_gpio.h
View file

@ -108,7 +108,7 @@
* .... .... ...V .... ....
*/
#define GPIO_OUTPUT_SET (1 << 8) /* Bit 8: Inital value of output */
#define GPIO_OUTPUT_SET (1 << 8) /* Bit 8: Initial value of output */
#define GPIO_OUTPUT_CLEAR (0)
/* This identifies the GPIO port:

2
arch/arm/src/sam34/sam4l_gpio.h
View file

@ -205,7 +205,7 @@
* Peripheral: .... .... .... .... .... ....
*/
#define GPIO_OUTPUT_SET (1 << 12) /* Bit 12: Inital value of output */
#define GPIO_OUTPUT_SET (1 << 12) /* Bit 12: Initial value of output */
#define GPIO_OUTPUT_CLEAR (0)
/* Selections for an interrupting input and peripheral events:

4
arch/arm/src/sam34/sam_hsmci.c
View file

@ -1999,7 +1999,7 @@ static int sam_waitresponse(FAR struct sdio_dev_s *dev, uint32_t cmd)
*
* Returned Value:
* Number of bytes sent on success; a negated errno on failure. Here a
* failure means only a failure to obtain the requested reponse (due to
* failure means only a failure to obtain the requested response (due to
* transport problem -- timeout, CRC, etc.). The implementation only
* assures that the response is returned intact and does not check errors
* within the response itself.
@ -2381,7 +2381,7 @@ static void sam_callbackenable(FAR struct sdio_dev_s *dev,
*
* Input Parameters:
* dev - Device-specific state data
* callback - The funtion to call on the media change
* callback - The function to call on the media change
* arg - A caller provided value to return with the callback
*
* Returned Value:

2
arch/arm/src/sam34/sam_twi.c
View file

@ -761,7 +761,7 @@ static void twi_setfrequency(struct twi_dev_s *priv, uint32_t frequency)
for (ckdiv = 0; ckdiv < 8; ckdiv++)
{
/* Calulate the CLDIV value using the current CKDIV guess */
/* Calculate the CLDIV value using the current CKDIV guess */
cldiv = ((priv->clkin / (frequency << 1)) - 4) / (1 << ckdiv);

2
arch/arm/src/sama5/Kconfig
View file

@ -3571,7 +3571,7 @@ choice
config SAMA5_ADC_SWTRIG
bool "Software trigger"
---help---
A-to-D Conversion is initiated only by sofware via an ioctl()
A-to-D Conversion is initiated only by software via an ioctl()
config SAMA5_ADC_ADTRG
bool "External trigger via the ADTRG pin"

2
arch/arm/src/sama5/sam_can.c
View file

@ -1529,7 +1529,7 @@ static void can_interrupt(int irq, void *context, FAR void *arg)
* 1. Synchronization segment (SYNC_SEG): a bit change is expected to occur
* within this time segment. It has a fixed length of one time quantum
* (1 x tCAN).
* 2. Propogation segment (PROP_SEG): This part of the bit time is used
* 2. Propagation segment (PROP_SEG): This part of the bit time is used
* to compensate for the physical delay times within the network. It is
* twice the sum of the signal’s propagation time on the bus line, the
* input comparator delay, and the output driver delay. It is

2
arch/arm/src/sama5/sam_dmac.c
View file

@ -1782,7 +1782,7 @@ static int sam_dmac_interrupt(int irq, void *context, FAR void *arg)
regval = sam_getdmac(dmac, SAM_DMAC_EBCISR_OFFSET) &
sam_getdmac(dmac, SAM_DMAC_EBCIMR_OFFSET);
/* Check if the any transfer has completed or any errors have ocurred. */
/* Check if the any transfer has completed or any errors have occurred. */
if (regval & DMAC_EBC_ALLCHANINTS)
{

4
arch/arm/src/sama5/sam_hsmci.c
View file

@ -2428,7 +2428,7 @@ static int sam_waitresponse(FAR struct sdio_dev_s *dev, uint32_t cmd)
*
* Returned Value:
* Number of bytes sent on success; a negated errno on failure. Here a
* failure means only a failure to obtain the requested reponse (due to
* failure means only a failure to obtain the requested response (due to
* transport problem -- timeout, CRC, etc.). The implementation only
* assures that the response is returned intact and does not check errors
* within the response itself.
@ -2819,7 +2819,7 @@ static void sam_callbackenable(FAR struct sdio_dev_s *dev,
*
* Input Parameters:
* dev - Device-specific state data
* callback - The funtion to call on the media change
* callback - The function to call on the media change
* arg - A caller provided value to return with the callback
*
* Returned Value:

2
arch/arm/src/sama5/sam_isi.c
View file

@ -77,7 +77,7 @@
struct sam_isi_s
{
uint32_t actual; /* Acutal ISI_MCK frequency */
uint32_t actual; /* Actual ISI_MCK frequency */
};
/****************************************************************************

8
arch/arm/src/sama5/sam_nand.c
View file

@ -1373,7 +1373,7 @@ static int nand_dma_write(struct sam_nandcs_s *priv,
/* Setup the Memory-to-Memory DMA. The semantics of the DMA module are
* awkward here. We will treat the NAND (dest) as the peripheral destination
* and memory as the source. Internally, the DMA module will realize taht
* and memory as the source. Internally, the DMA module will realize that
* this is a memory to memory transfer and should do the right thing.
*/
@ -1509,7 +1509,7 @@ static int nand_read(struct sam_nandcs_s *priv, uint8_t *buffer,
#ifdef CONFIG_SAMA5_NAND_DMA
/* Then perform the transfer via memory-to-memory DMA or not, depending
* on if we have a DMA channel assigned and if the transfer is
* sufficiently large. Small DMAs (e.g., for spare data) are not peformed
* sufficiently large. Small DMAs (e.g., for spare data) are not performed
* because the DMA context switch can take more time that the DMA itself.
*/
@ -1745,7 +1745,7 @@ static int nand_nfcsram_write(struct sam_nandcs_s *priv, uint8_t *buffer,
#ifdef CONFIG_SAMA5_NAND_DMA
/* Then perform the transfer via memory-to-memory DMA or not, depending
* on if we have a DMA channel assigned and if the transfer is
* sufficiently large. Small DMAs (e.g., for spare data) are not peformed
* sufficiently large. Small DMAs (e.g., for spare data) are not performed
* because the DMA context switch can take more time that the DMA itself.
*/
@ -1813,7 +1813,7 @@ static int nand_write(struct sam_nandcs_s *priv, uint8_t *buffer,
#ifdef CONFIG_SAMA5_NAND_DMA
/* Then perform the transfer via memory-to-memory DMA or not, depending
* on if we have a DMA channel assigned and if the transfer is
* sufficiently large. Small DMAs (e.g., for spare data) are not peformed
* sufficiently large. Small DMAs (e.g., for spare data) are not performed
* because the DMA context switch can take more time that the DMA itself.
*/

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