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esp32s3: add simple boot support

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The Simple Boot feature for Espressif chips is a method of booting
that doesn't depend on a 2nd stage bootloader. Its not the
intention to replace a 2nd stage bootloader such as MCUboot and
ESP-IDF bootloader, but to have a minimal and straight-forward way
of booting, and also simplify the building.

This commit also removes deprecated code and makes this bootloader
configuration as default for esp32s3 targets and removes the need
for running 'make bootloader' command for it.

Other related fix, but not directly to Simple Boot:
- Instrumentation is required to run from IRAM to support it during
initialization. `is_eco0` function also needs to run from IRAM.
- `rtc.data` section placement was fixed.
- Provide arch-defined interfaces for efuses, in order to decouple
board config level from arch-defined values.

Signed-off-by: Almir Okato <almir.okato@espressif.com>
This commit is contained in:
Almir Okato 2024-02-09 16:15:33 -03:00 committed by Xiang Xiao
parent 9009cd6f2d
commit d098c1dc87
49 changed files with 1211 additions and 7600 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
arch/xtensa/Kconfig
View file

@ -78,7 +78,7 @@ config ARCH_CHIP_ESP32S3
bool "Espressif ESP32-S3"
select ARCH_FAMILY_LX7
select XTENSA_HAVE_INTERRUPTS
select ARCH_HAVE_BOOTLOADER
select ARCH_HAVE_BOOTLOADER if !ESPRESSIF_SIMPLE_BOOT
select ARCH_HAVE_FPU
select ARCH_HAVE_MPU
select ARCH_HAVE_MULTICPU

6
arch/xtensa/include/esp32s3/.gitignore vendored Normal file
View file

@ -0,0 +1,6 @@
/soc.h
/reg_base.h
/esp_attr.h
/esp_assert.h
/esp_bit_defs.h
/sdkconfig.h

24
arch/xtensa/src/esp32s3/Bootloader.mk
View file

@ -20,7 +20,7 @@
.PHONY: bootloader clean_bootloader
ifeq ($(CONFIG_ESP32S3_BOOTLOADER_BUILD_FROM_SOURCE),y)
ifeq ($(CONFIG_ESPRESSIF_SIMPLE_BOOT),)
TOOLSDIR = $(TOPDIR)/tools/espressif
CHIPDIR = $(TOPDIR)/arch/xtensa/src/chip
@ -83,8 +83,13 @@ else ifeq ($(CONFIG_ESP32S3_APP_FORMAT_LEGACY),y)
$(call cfg_val,CONFIG_PARTITION_TABLE_OFFSET,$(CONFIG_ESP32S3_PARTITION_TABLE_OFFSET)) \
} >> $(BOOTLOADER_CONFIG)
endif
endif
ifeq ($(CONFIG_ESP32S3_APP_FORMAT_MCUBOOT),y)
ifeq ($(CONFIG_ESPRESSIF_SIMPLE_BOOT),y)
bootloader:
$(Q) echo "Using direct bootloader to boot NuttX."
else ifeq ($(CONFIG_ESP32S3_APP_FORMAT_MCUBOOT),y)
BOOTLOADER_BIN = $(TOPDIR)/mcuboot-esp32s3.bin
@ -126,18 +131,3 @@ clean_bootloader:
$(call DELFILE,$(TOPDIR)/partition-table-esp32s3.bin)
endif
else ifeq ($(CONFIG_ESP32S3_BOOTLOADER_DOWNLOAD_PREBUILT),y)
BOOTLOADER_VERSION = latest
BOOTLOADER_URL = https://github.com/espressif/esp-nuttx-bootloader/releases/download/$(BOOTLOADER_VERSION)
bootloader:
$(call DOWNLOAD,$(BOOTLOADER_URL),bootloader-esp32s3.bin,$(TOPDIR)/bootloader-esp32s3.bin)
$(call DOWNLOAD,$(BOOTLOADER_URL),partition-table-esp32s3.bin,$(TOPDIR)/partition-table-esp32s3.bin)
clean_bootloader:
$(call DELFILE,$(TOPDIR)/bootloader-esp32s3.bin)
$(call DELFILE,$(TOPDIR)/partition-table-esp32s3.bin)
endif

42
arch/xtensa/src/esp32s3/Kconfig
View file

@ -39,6 +39,10 @@ config ESPRESSIF_CHIP_SERIES
string
default "esp32s3"
config ESPRESSIF_NUM_CPUS
int
default 2
choice ESP32S3_DEFAULT_CPU_FREQ
prompt "CPU frequency"
default ESP32S3_DEFAULT_CPU_FREQ_240
@ -530,6 +534,7 @@ config ESP32S3_WDT
config ESP32S3_EFUSE
bool "EFUSE support"
select EFUSE
default n
---help---
Enable ESP32-S3 efuse support.
@ -1887,15 +1892,13 @@ config ESP32S3_SPI_FLASH_SUPPORT_PSRAM_STACK
3. Once operation in step 2 triggers, CPU will trigger exception.
So related SPI flash functions should be sent and run in tasks which use SRAM as task stack.
if ESP32S3_APP_FORMAT_LEGACY
comment "Partition Table configuration"
config ESP32S3_PARTITION_TABLE
bool "Create MTD partitions from Partition Table"
default n
depends on ESP32S3_MTD && ESP32S3_APP_FORMAT_LEGACY
select ESP32S3_BOOTLOADER_BUILD_FROM_SOURCE
depends on ESP32S3_MTD
select ESP32S3_APP_FORMAT_LEGACY
---help---
Decode partition table and initialize partitions as MTD.
@ -1904,8 +1907,6 @@ config ESP32S3_PARTITION_MOUNTPT
default "/dev/esp/partition/"
depends on ESP32S3_PARTITION_TABLE
endif # ESP32S3_APP_FORMAT_LEGACY
endif # ESP32S3_SPIFLASH
endmenu # SPI Flash configuration
@ -2173,38 +2174,26 @@ endmenu
menu "Bootloader and Image Configuration"
config ESP32S3_APP_FORMAT_LEGACY
config ESPRESSIF_SIMPLE_BOOT
bool
default y if !ESP32S3_APP_FORMAT_MCUBOOT
depends on !ESP32S3_APP_FORMAT_MCUBOOT
---help---
This is the legacy application image format, as supported by the ESP-IDF
2nd stage bootloader.
depends on !ESP32S3_APP_FORMAT_LEGACY
default y
config ESP32S3_APP_FORMAT_MCUBOOT
bool "Enable MCUboot-bootable format"
depends on !MCUBOOT_BOOTLOADER
default n
select ESP32S3_HAVE_OTA_PARTITION
select ESP32S3_BOOTLOADER_BUILD_FROM_SOURCE
---help---
Enables the Espressif port of MCUboot to be used as 2nd stage bootloader.
config ESP32S3_BOOTLOADER_DOWNLOAD_PREBUILT
config ESP32S3_APP_FORMAT_LEGACY
bool
default y if !ESP32S3_BOOTLOADER_BUILD_FROM_SOURCE
depends on !ESP32S3_BOOTLOADER_BUILD_FROM_SOURCE
default y if BUILD_PROTECTED
---help---
The build system will download the prebuilt binaries from
https://github.com/espressif/esp-nuttx-bootloader according to the chosen
Application Image Format (ESP32S3_APP_FORMAT_LEGACY or ESP32S3_APP_FORMAT_MCUBOOT)
config ESP32S3_BOOTLOADER_BUILD_FROM_SOURCE
bool "Build binaries from source"
---help---
The build system will build all the required binaries from source. It will clone
the https://github.com/espressif/esp-nuttx-bootloader repository and build a
custom bootloader according to the chosen Application Image Format
(ESP32S3_APP_FORMAT_LEGACY or ESP32S3_APP_FORMAT_MCUBOOT) and partition information.
This is the legacy application image format, as supported by the ESP-IDF
2nd stage bootloader.
choice
prompt "Target slot for image flashing"
@ -2250,7 +2239,6 @@ config ESP32S3_CUSTOM_PARTITION_TABLE_OFFSET
bool "Customize partition table offset"
default n
depends on ESP32S3_APP_FORMAT_LEGACY
select ESP32S3_BOOTLOADER_BUILD_FROM_SOURCE
---help---
Enable to select the offset of the partition table in the flash.

7
arch/xtensa/src/esp32s3/Make.defs
View file

@ -194,7 +194,7 @@ endif
ESP_HAL_3RDPARTY_REPO = esp-hal-3rdparty
ifndef ESP_HAL_3RDPARTY_VERSION
ESP_HAL_3RDPARTY_VERSION = c6a4edccfce95e32ef5e34d9f1119d9c581c5c1c
ESP_HAL_3RDPARTY_VERSION = 7c4fae7ebc5342b19cab03511bfa277176bba377
endif
ifndef ESP_HAL_3RDPARTY_URL
@ -212,6 +212,8 @@ chip/$(ESP_HAL_3RDPARTY_REPO):
CFLAGS += -Wno-undef -Wno-unused-variable
CFLAGS += ${DEFINE_PREFIX}_RETARGETABLE_LOCKING
AFLAGS += $(CFLAGS)
# Files that require the HAL recipe
include chip/Bootloader.mk
@ -231,9 +233,6 @@ ifeq ($(CONFIG_ESP32S3_WIRELESS),y)
$(Q) cd chip/$(ESP_HAL_3RDPARTY_REPO)/components/mbedtls/mbedtls && git apply ../../../nuttx/patches/components/mbedtls/mbedtls/*.patch
endif
distclean::
$(call DELDIR, chip/$(ESP_HAL_3RDPARTY_REPO))
ifeq ($(CONFIG_ESP32S3_WIRELESS),y)
include chip/Wireless.mk
endif

2
arch/xtensa/src/esp32s3/esp32s3_ble_adapter.c
View file

@ -53,7 +53,7 @@
#include "hardware/wdev_reg.h"
#include "rom/esp32s3_spiflash.h"
#include "xtensa.h"
#include "xtensa_attr.h"
#include "esp_attr.h"
#include "esp32s3_irq.h"
#include "esp32s3_rt_timer.h"
#include "esp32s3_rtc.h"

2
arch/xtensa/src/esp32s3/esp32s3_clockconfig.c
View file

@ -28,7 +28,7 @@
#include <sys/param.h>
#include "xtensa.h"
#include "xtensa_attr.h"
#include "esp_attr.h"
#include "hardware/esp32s3_soc.h"
#include "hardware/esp32s3_uart.h"
#include "hardware/esp32s3_system.h"

142
arch/xtensa/src/esp32s3/esp32s3_efuse.c
View file

@ -440,51 +440,6 @@ static int esp32s3_efuse_process(const efuse_desc_t *field[], void *ptr,
return err;
}
/****************************************************************************
* Name: esp32s3_efuse_write_reg
*
* Description:
* Write value to efuse register.
*
* Input Parameters:
* blk - Block number of eFuse
* num_reg - The register number in the block
* value - Value to write
*
* Returned Value:
* None.
*
****************************************************************************/
static void esp32s3_efuse_write_reg(uint32_t blk, uint32_t num_reg,
uint32_t value)
{
uint32_t addr_wr_reg;
uint32_t reg_to_write;
uint32_t blk_start = g_start_efuse_wrreg[blk];
DEBUGASSERT(blk >= 0 && blk < EFUSE_BLK_MAX);
DEBUGASSERT(num_reg <= 7);
/* The block 0 and register 7 doesn't exist */
if (blk == 0 && num_reg == 7)
{
merr("Block 0 Register 7 doesn't exist!\n");
return;
}
addr_wr_reg = blk_start + num_reg * 4;
reg_to_write = getreg32(addr_wr_reg) | value;
/* The register can be written in parts so we combine the new value
* with the one already available.
*/
putreg32(reg_to_write, addr_wr_reg);
}
/****************************************************************************
* Name: esp32s3_efuse_write_blob
*
@ -518,33 +473,6 @@ static int esp32s3_efuse_write_blob(uint32_t num_reg, int bit_offset,
return OK;
}
/****************************************************************************
* Name: esp32s3_efuse_read_reg
*
* Description:
* Read efuse register.
*
* Input Parameters:
* blk - Block number of eFuse
* num_reg - The register number in the block
*
* Returned Value:
* Return the value in the efuse register.
*
****************************************************************************/
static uint32_t esp32s3_efuse_read_reg(uint32_t blk, uint32_t num_reg)
{
DEBUGASSERT(blk >= 0 && blk < EFUSE_BLK_MAX);
uint32_t value;
uint32_t blk_start = g_start_efuse_rdreg[blk];
DEBUGASSERT(num_reg <= 7);
value = getreg32(blk_start + num_reg * 4);
return value;
}
/****************************************************************************
* Name: esp32s3_efuse_fill_buff
*
@ -709,3 +637,73 @@ void esp32s3_efuse_burn_efuses(void)
};
}
/****************************************************************************
* Name: esp32s3_efuse_read_reg
*
* Description:
* Read efuse register.
*
* Input Parameters:
* blk - Block number of eFuse
* num_reg - The register number in the block
*
* Returned Value:
* Return the value in the efuse register.
*
****************************************************************************/
uint32_t esp32s3_efuse_read_reg(uint32_t blk, uint32_t num_reg)
{
DEBUGASSERT(blk >= 0 && blk < EFUSE_BLK_MAX);
uint32_t value;
uint32_t blk_start = g_start_efuse_rdreg[blk];
DEBUGASSERT(num_reg <= 7);
value = getreg32(blk_start + num_reg * 4);
return value;
}
/****************************************************************************
* Name: esp32s3_efuse_write_reg
*
* Description:
* Write value to efuse register.
*
* Input Parameters:
* blk - Block number of eFuse
* num_reg - The register number in the block
* value - Value to write
*
* Returned Value:
* None.
*
****************************************************************************/
void esp32s3_efuse_write_reg(uint32_t blk, uint32_t num_reg, uint32_t value)
{
uint32_t addr_wr_reg;
uint32_t reg_to_write;
uint32_t blk_start = g_start_efuse_wrreg[blk];
DEBUGASSERT(blk >= 0 && blk < EFUSE_BLK_MAX);
DEBUGASSERT(num_reg <= 7);
/* The block 0 and register 7 doesn't exist */
if (blk == 0 && num_reg == 7)
{
merr("Block 0 Register 7 doesn't exist!\n");
return;
}
addr_wr_reg = blk_start + num_reg * 4;
reg_to_write = getreg32(addr_wr_reg) | value;
/* The register can be written in parts so we combine the new value
* with the one already available.
*/
putreg32(reg_to_write, addr_wr_reg);
}

35
arch/xtensa/src/esp32s3/esp32s3_efuse.h
View file

@ -162,6 +162,41 @@ int esp32s3_efuse_write_field(const efuse_desc_t *field[],
void esp32s3_efuse_burn_efuses(void);
/****************************************************************************
* Name: esp32s3_efuse_read_reg
*
* Description:
* Read efuse register.
*
* Input Parameters:
* blk - Block number of eFuse
* num_reg - The register number in the block
*
* Returned Value:
* Return the value in the efuse register.
*
****************************************************************************/
uint32_t esp32s3_efuse_read_reg(uint32_t blk, uint32_t num_reg);
/****************************************************************************
* Name: esp32s3_efuse_write_reg
*
* Description:
* Write value to efuse register.
*
* Input Parameters:
* blk - Block number of eFuse
* num_reg - The register number in the block
* value - Value to write
*
* Returned Value:
* None.
*
****************************************************************************/
void esp32s3_efuse_write_reg(uint32_t blk, uint32_t num_reg, uint32_t value);
/****************************************************************************
* Name: esp32s3_efuse_initialize
*

3
arch/xtensa/src/esp32s3/esp32s3_himem.c
View file

@ -35,7 +35,8 @@
#include "esp32s3_spiflash_mtd.h"
#include "hardware/esp32s3_soc.h"
#include "hardware/esp32s3_cache_memory.h"
#include "hardware/esp32s3_extmem.h"
#include "soc/extmem_reg.h"
/****************************************************************************
* Pre-processor Definitions

3
arch/xtensa/src/esp32s3/esp32s3_otg.h
View file

@ -29,9 +29,6 @@
#include <stdint.h>
#include "chip.h"
#include "hardware/esp32s3_otg.h"
#if defined(CONFIG_ESP32S3_OTG)
/****************************************************************************

5
arch/xtensa/src/esp32s3/esp32s3_psram_octal.c
View file

@ -33,13 +33,12 @@
#include "esp32s3_psram.h"
#include "esp32s3_spi_timing.h"
#include "hardware/esp32s3_spi_mem_reg.h"
#include "hardware/esp32s3_iomux.h"
#include "hardware/esp32s3_gpio.h"
#include "hardware/esp32s3_gpio_sigmap.h"
#include "hardware/esp32s3_syscon.h"
#include "rom/esp32s3_spiflash.h"
#include "rom/esp32s3_opi_flash.h"
#include "rom/opi_flash.h"
/****************************************************************************
* Pre-processor Definitions
@ -600,7 +599,7 @@ static void IRAM_ATTR config_psram_spi_phases(void)
*
****************************************************************************/
static inline void spi_flash_set_rom_required_regs(void)
void IRAM_ATTR spi_flash_set_rom_required_regs(void)
{
#ifdef CONFIG_ESP32S3_FLASH_MODE_OCT

15
arch/xtensa/src/esp32s3/esp32s3_psram_quad.c
View file

@ -31,11 +31,10 @@
#include "esp32s3_psram.h"
#include "esp32s3_spi_timing.h"
#include "rom/esp32s3_spiflash.h"
#include "rom/esp32s3_opi_flash.h"
#include "hardware/esp32s3_spi_mem_reg.h"
#include "hardware/esp32s3_iomux.h"
#include "hardware/esp32s3_gpio_sigmap.h"
#include "rom/esp32s3_spiflash.h"
#include "rom/opi_flash.h"
/* EFUSE */
@ -148,6 +147,16 @@ static void psram_set_op_mode(int spi_num, int mode)
}
}
/* Redefine external struct members name */
#define addr_bit_len addrBitLen
#define cmd_bit_len cmdBitLen
#define dummy_bit_len dummyBitLen
#define tx_data txData
#define tx_data_bit_len txDataBitLen
#define rx_data rxData
#define rx_data_bit_len rxDataBitLen
static void _psram_exec_cmd(int spi_num,
uint32_t cmd, int cmd_bit_len,
uint32_t addr, int addr_bit_len,

2
arch/xtensa/src/esp32s3/esp32s3_rng.c
View file

@ -41,7 +41,7 @@
#include <arch/xtensa/core_macros.h>
#include "xtensa.h"
#include "xtensa_attr.h"
#include "esp_attr.h"
#include "hardware/wdev_reg.h"
#include "esp32s3_clockconfig.h"

2
arch/xtensa/src/esp32s3/esp32s3_rt_timer.c
View file

@ -41,7 +41,7 @@
#include <nuttx/spinlock.h>
#include "xtensa.h"
#include "xtensa_attr.h"
#include "esp_attr.h"
#include "esp32s3_irq.h"
#include "esp32s3_rt_timer.h"
#include "hardware/esp32s3_soc.h"

6
arch/xtensa/src/esp32s3/esp32s3_rtc.c
View file

@ -44,14 +44,14 @@
#include "hardware/esp32s3_apb_ctrl.h"
#include "hardware/regi2c_dig_reg.h"
#include "hardware/regi2c_ctrl.h"
#include "hardware/esp32s3_spi_mem_reg.h"
#include "hardware/esp32s3_extmem.h"
#include "hardware/esp32s3_syscon.h"
#include "hardware/regi2c_bbpll.h"
#include "hardware/regi2c_lp_bias.h"
#include "xtensa.h"
#include "xtensa_attr.h"
#include "esp_attr.h"
#include "soc/extmem_reg.h"
#include "soc/spi_mem_reg.h"
#include "esp32s3_rtc.h"

7
arch/xtensa/src/esp32s3/esp32s3_spi_timing.c
View file

@ -30,12 +30,13 @@
#include "esp32s3_gpio.h"
#include "esp32s3_psram.h"
#include "esp32s3_spi_timing.h"
#include "hardware/esp32s3_spi_mem_reg.h"
#include "hardware/esp32s3_iomux.h"
#include "hardware/esp32s3_gpio.h"
#include "hardware/esp32s3_gpio_sigmap.h"
#include "rom/esp32s3_spiflash.h"
#include "rom/esp32s3_opi_flash.h"
#include "rom/opi_flash.h"
#include "soc/spi_mem_reg.h"
/****************************************************************************
* Pre-processor Definitions
@ -54,7 +55,7 @@
#endif
#if defined(CONFIG_ESP32S3_FLASH_SAMPLE_MODE_DTR)
# if defined(CONFIG_ESP32S3_FLASH_FREQ_80M)
# if defined(CONFIG_ESP32S3_FLASH_FREQ_80M)
# define ESP32S3_SPI_TIMING_FLASH_CORE_CLK 160
# elif defined(CONFIG_ESP32S3_FLASH_FREQ_120M)
# define ESP32S3_SPI_TIMING_FLASH_CORE_CLK 240

15
arch/xtensa/src/esp32s3/esp32s3_spiflash.c
View file

@ -41,16 +41,17 @@
#include "sched/sched.h"
#include "xtensa.h"
#include "xtensa_attr.h"
#include "esp_attr.h"
#include "hardware/esp32s3_efuse.h"
#include "hardware/esp32s3_extmem.h"
#include "hardware/esp32s3_spi_mem_reg.h"
#include "hardware/esp32s3_cache_memory.h"
#include "rom/esp32s3_spiflash.h"
#include "rom/esp32s3_opi_flash.h"
#include "esp32s3_irq.h"
#include "esp32s3_spiflash.h"
#include "soc/extmem_reg.h"
#include "soc/spi_mem_reg.h"
#include "rom/opi_flash.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
@ -208,14 +209,10 @@ extern void cache_invalidate_icache_all(void);
* Private Data
****************************************************************************/
static struct spiflash_guard_funcs g_spi_flash_guard_funcs =
static spi_flash_guard_funcs_t g_spi_flash_guard_funcs =
{
.start = spiflash_start,
.end = spiflash_end,
.op_lock = NULL,
.op_unlock = NULL,
.address_is_safe = NULL,
.yield = NULL,
};
static uint32_t s_flash_op_cache_state[CONFIG_SMP_NCPUS];

10
arch/xtensa/src/esp32s3/esp32s3_spiflash_mtd.c
View file

@ -41,7 +41,7 @@
#include "hardware/esp32s3_soc.h"
#include "hardware/esp32s3_cache_memory.h"
#include "xtensa_attr.h"
#include "esp_attr.h"
#include "esp32s3_spiflash.h"
#include "esp32s3_spiram.h"
@ -90,7 +90,7 @@ struct esp32s3_mtd_dev_s
/* SPI Flash data */
const struct spiflash_legacy_data_s **data;
esp_rom_spiflash_legacy_data_t **data;
};
#ifdef CONFIG_ESP32S3_SPI_FLASH_SUPPORT_PSRAM_STACK
@ -177,7 +177,7 @@ static const struct esp32s3_mtd_dev_s g_esp32s3_spiflash =
#endif
.name = "esp32s3_spiflash"
},
.data = (const struct spiflash_legacy_data_s **)
.data = (esp_rom_spiflash_legacy_data_t **)
(&rom_spiflash_legacy_data),
};
@ -195,7 +195,7 @@ static const struct esp32s3_mtd_dev_s g_esp32s3_spiflash_encrypt =
#endif
.name = "esp32s3_spiflash_encrypt"
},
.data = (const struct spiflash_legacy_data_s **)
.data = (esp_rom_spiflash_legacy_data_t **)
(&rom_spiflash_legacy_data),
};
@ -1087,7 +1087,7 @@ struct mtd_dev_s *esp32s3_spiflash_alloc_mtdpart(uint32_t mtd_offset,
bool encrypted)
{
const struct esp32s3_mtd_dev_s *priv;
const esp32s3_spiflash_chip_t *chip;
const esp_rom_spiflash_chip_t *chip;
struct mtd_dev_s *mtd_part;
uint32_t blocks;
uint32_t startblock;

7
arch/xtensa/src/esp32s3/esp32s3_spiram.c
View file

@ -37,14 +37,15 @@
#include <assert.h>
#include "xtensa.h"
#include "xtensa_attr.h"
#include "esp_attr.h"
#include "esp32s3_psram.h"
#include "esp32s3_spiram.h"
#include "hardware/esp32s3_soc.h"
#include "hardware/esp32s3_cache_memory.h"
#include "hardware/esp32s3_extmem.h"
#include "hardware/esp32s3_iomux.h"
#include "soc/extmem_reg.h"
#define PSRAM_MODE PSRAM_VADDR_MODE_NORMAL
#if defined(CONFIG_ESP32S3_SPIRAM)
@ -551,7 +552,7 @@ int IRAM_ATTR instruction_flash2spiram_offset(void)
}
#endif
#if defined(CONFIG_ESP32_SPIRAM_RODATA)
#if defined(CONFIG_ESP32S3_SPIRAM_RODATA)
void rodata_flash_page_info_init(void)
{
uint32_t rodata_page_cnt = ((uint32_t)_rodata_reserved_end -

351
arch/xtensa/src/esp32s3/esp32s3_start.c
View file

@ -31,7 +31,7 @@
#include <nuttx/irq.h>
#include "xtensa.h"
#include "xtensa_attr.h"
#include "esp_attr.h"
#include "esp32s3_start.h"
#include "esp32s3_lowputc.h"
@ -46,10 +46,26 @@
#include "esp32s3_spi_timing.h"
#include "hardware/esp32s3_cache_memory.h"
#include "hardware/esp32s3_system.h"
#include "hardware/esp32s3_extmem.h"
#include "rom/esp32s3_libc_stubs.h"
#include "rom/opi_flash.h"
#include "rom/esp32s3_spiflash.h"
#include "rom/esp32s3_opi_flash.h"
#include "hal/mmu_hal.h"
#include "hal/mmu_types.h"
#include "hal/cache_types.h"
#include "hal/cache_ll.h"
#include "hal/cache_hal.h"
#include "soc/extmem_reg.h"
#include "rom/cache.h"
#include "spi_flash_mmap.h"
#ifdef CONFIG_ESPRESSIF_SIMPLE_BOOT
# include "bootloader_init.h"
# include "bootloader_flash_priv.h"
# include "esp_rom_uart.h"
# include "esp_rom_sys.h"
# include "esp_app_format.h"
#endif
#include "esp_clk_internal.h"
#include "periph_ctrl.h"
@ -64,15 +80,55 @@
# define showprogress(c)
#endif
#ifdef CONFIG_ESP32S3_APP_FORMAT_MCUBOOT
#if defined(CONFIG_ESP32S3_APP_FORMAT_MCUBOOT) || \
defined (CONFIG_ESPRESSIF_SIMPLE_BOOT)
# ifdef CONFIG_ESP32S3_APP_FORMAT_MCUBOOT
# define PRIMARY_SLOT_OFFSET CONFIG_ESP32S3_OTA_PRIMARY_SLOT_OFFSET
/* Cache MMU address mask (MMU tables ignore bits which are zero) */
#define PRIMARY_SLOT_OFFSET CONFIG_ESP32S3_OTA_PRIMARY_SLOT_OFFSET
# define MMU_FLASH_MASK (~(MMU_PAGE_SIZE - 1))
# else
/* Force offset to the beginning of the whole image */
#define HDR_ATTR locate_code(".entry_addr") used_code
# define PRIMARY_SLOT_OFFSET 0
# endif
# define HDR_ATTR __attribute__((section(".entry_addr"))) \
__attribute__((used))
# define MMU_BLOCK_SIZE 0x00010000 /* 64 KB */
# define CACHE_REG EXTMEM_ICACHE_CTRL1_REG
# define CACHE_MASK (EXTMEM_ICACHE_SHUT_IBUS_M | \
EXTMEM_ICACHE_SHUT_DBUS_M)
/* Cache MMU address mask (MMU tables ignore bits which are zero) */
# define CHECKSUM_ALIGN 16
# define IS_PADD(addr) (addr == 0)
# define IS_DRAM(addr) (addr >= SOC_DRAM_LOW && addr < SOC_DRAM_HIGH)
# define IS_IRAM(addr) (addr >= SOC_IRAM_LOW && addr < SOC_IRAM_HIGH)
# define IS_IROM(addr) (addr >= SOC_IROM_LOW && addr < SOC_IROM_HIGH)
# define IS_DROM(addr) (addr >= SOC_DROM_LOW && addr < SOC_DROM_HIGH)
# define IS_SRAM(addr) (IS_IRAM(addr) || IS_DRAM(addr))
# define IS_MMAP(addr) (IS_IROM(addr) || IS_DROM(addr))
# ifdef SOC_RTC_FAST_MEM_SUPPORTED
# define IS_RTC_FAST_IRAM(addr) \
(addr >= SOC_RTC_IRAM_LOW && addr < SOC_RTC_IRAM_HIGH)
# define IS_RTC_FAST_DRAM(addr) \
(addr >= SOC_RTC_DRAM_LOW && addr < SOC_RTC_DRAM_HIGH)
# else
# define IS_RTC_FAST_IRAM(addr) 0
# define IS_RTC_FAST_DRAM(addr) 0
# endif
# ifdef SOC_RTC_SLOW_MEM_SUPPORTED
# define IS_RTC_SLOW_DRAM(addr) \
(addr >= SOC_RTC_DATA_LOW && addr < SOC_RTC_DATA_HIGH)
# else
# define IS_RTC_SLOW_DRAM(addr) 0
# endif
#define MMU_FLASH_MASK (~(MMU_PAGE_SIZE - 1))
# define IS_NONE(addr) (!IS_IROM(addr) && !IS_DROM(addr) \
&& !IS_IRAM(addr) && !IS_DRAM(addr) \
&& !IS_RTC_FAST_IRAM(addr) && !IS_RTC_FAST_DRAM(addr) \
&& !IS_RTC_SLOW_DRAM(addr) && !IS_PADD(addr))
# define IS_MAPPING(addr) IS_IROM(addr) || IS_DROM(addr)
#endif
@ -80,7 +136,8 @@
* Private Types
****************************************************************************/
#ifdef CONFIG_ESP32S3_APP_FORMAT_MCUBOOT
#if defined(CONFIG_ESP32S3_APP_FORMAT_MCUBOOT) || \
defined (CONFIG_ESPRESSIF_SIMPLE_BOOT)
extern uint8_t _image_irom_vma[];
extern uint8_t _image_irom_lma[];
extern uint8_t _image_irom_size[];
@ -94,14 +151,9 @@ extern uint8_t _image_drom_size[];
* ROM Function Prototypes
****************************************************************************/
#ifdef CONFIG_ESP32S3_APP_FORMAT_MCUBOOT
#if defined(CONFIG_ESP32S3_APP_FORMAT_MCUBOOT) || \
defined (CONFIG_ESPRESSIF_SIMPLE_BOOT)
extern int ets_printf(const char *fmt, ...) printf_like(1, 2);
extern int cache_dbus_mmu_set(uint32_t ext_ram, uint32_t vaddr,
uint32_t paddr, uint32_t psize, uint32_t num,
uint32_t fixed);
extern int cache_ibus_mmu_set(uint32_t ext_ram, uint32_t vaddr,
uint32_t paddr, uint32_t psize, uint32_t num,
uint32_t fixed);
#endif
extern void rom_config_instruction_cache_mode(uint32_t cfg_cache_size,
@ -122,7 +174,6 @@ extern void cache_set_idrom_mmu_info(uint32_t instr_page_num,
int i_off,
int ro_off);
#ifdef CONFIG_ESP32S3_DATA_CACHE_16KB
extern void cache_invalidate_dcache_all(void);
extern int cache_occupy_addr(uint32_t addr, uint32_t size);
#endif
@ -130,15 +181,17 @@ extern int cache_occupy_addr(uint32_t addr, uint32_t size);
* Private Function Prototypes
****************************************************************************/
#ifdef CONFIG_ESP32S3_APP_FORMAT_MCUBOOT
noreturn_function void __start(void);
#if defined(CONFIG_ESP32S3_APP_FORMAT_MCUBOOT) || \
defined (CONFIG_ESPRESSIF_SIMPLE_BOOT)
IRAM_ATTR noreturn_function void __start(void);
#endif
/****************************************************************************
* Private Data
****************************************************************************/
#ifdef CONFIG_ESP32S3_APP_FORMAT_MCUBOOT
#if defined(CONFIG_ESP32S3_APP_FORMAT_MCUBOOT) || \
defined (CONFIG_ESPRESSIF_SIMPLE_BOOT)
HDR_ATTR static void (*_entry_point)(void) = __start;
#endif
@ -146,6 +199,8 @@ HDR_ATTR static void (*_entry_point)(void) = __start;
* Public Data
****************************************************************************/
extern uint8_t _instruction_reserved_start[];
extern uint8_t _instruction_reserved_end[];
extern uint8_t _rodata_reserved_start[];
extern uint8_t _rodata_reserved_end[];
@ -176,6 +231,17 @@ noinstrument_function static void IRAM_ATTR configure_cpu_caches(void)
{
int s_instr_flash2spiram_off = 0;
int s_rodata_flash2spiram_off = 0;
uint32_t _instruction_size = (uint32_t)&_instruction_reserved_end -
(uint32_t)&_instruction_reserved_start;
uint32_t cache_mmu_irom_size =
((_instruction_size + SPI_FLASH_MMU_PAGE_SIZE - 1) /
SPI_FLASH_MMU_PAGE_SIZE) * sizeof(uint32_t);
uint32_t _rodata_size = (uint32_t)&_rodata_reserved_end -
(uint32_t)&_rodata_reserved_start;
uint32_t cache_mmu_drom_size =
((_rodata_size + SPI_FLASH_MMU_PAGE_SIZE - 1) /
SPI_FLASH_MMU_PAGE_SIZE) * sizeof(uint32_t);
/* Configure the mode of instruction cache: cache size, cache line size. */
@ -195,20 +261,16 @@ noinstrument_function static void IRAM_ATTR configure_cpu_caches(void)
/* Configure the Cache MMU size for instruction and rodata in flash. */
uint32_t rodata_reserved_start_align =
(uint32_t)_rodata_reserved_start & ~(MMU_PAGE_SIZE - 1);
uint32_t cache_mmu_irom_size =
((rodata_reserved_start_align - SOC_DROM_LOW) / MMU_PAGE_SIZE) *
sizeof(uint32_t);
uint32_t cache_mmu_drom_size =
(((uint32_t)_rodata_reserved_end - rodata_reserved_start_align +
MMU_PAGE_SIZE - 1) /
MMU_PAGE_SIZE) * sizeof(uint32_t);
cache_set_idrom_mmu_size(cache_mmu_irom_size,
CACHE_DROM_MMU_MAX_END - cache_mmu_irom_size);
#if CONFIG_SPIRAM_FETCH_INSTRUCTIONS
s_instr_flash2spiram_off = instruction_flash2spiram_offset();
#endif
#if CONFIG_SPIRAM_RODATA
s_rodata_flash2spiram_off = rodata_flash2spiram_offset();
#endif
cache_set_idrom_mmu_info(cache_mmu_irom_size / sizeof(uint32_t),
cache_mmu_drom_size / sizeof(uint32_t),
(uint32_t)_rodata_reserved_start,
@ -299,6 +361,7 @@ noinstrument_function void noreturn_function IRAM_ATTR __esp32s3_start(void)
esp32s3_region_protection();
#ifndef CONFIG_ESPRESSIF_SIMPLE_BOOT
/* Move CPU0 exception vectors to IRAM */
__asm__ __volatile__ ("wsr %0, vecbase\n"::"r" (_init_start));
@ -311,6 +374,7 @@ noinstrument_function void noreturn_function IRAM_ATTR __esp32s3_start(void)
{
*dest++ = 0;
}
#endif
#ifndef CONFIG_SMP
/* Make sure that the APP_CPU is disabled for now */
@ -410,29 +474,6 @@ noinstrument_function void noreturn_function IRAM_ATTR __esp32s3_start(void)
for (; ; ); /* Should not return */
}
/****************************************************************************
* Name: calc_mmu_pages
*
* Description:
* Calculate the number of cache pages to map.
*
* Input Parameters:
* size - Size of data to map
* vaddr - Virtual address where data will be mapped
*
* Returned Value:
* Number of cache MMU pages required to do the mapping.
*
****************************************************************************/
#ifdef CONFIG_ESP32S3_APP_FORMAT_MCUBOOT
static inline uint32_t calc_mmu_pages(uint32_t size, uint32_t vaddr)
{
return (size + (vaddr - (vaddr & MMU_FLASH_MASK)) + MMU_PAGE_SIZE - 1) /
MMU_PAGE_SIZE;
}
#endif
/****************************************************************************
* Name: map_rom_segments
*
@ -447,55 +488,155 @@ static inline uint32_t calc_mmu_pages(uint32_t size, uint32_t vaddr)
*
****************************************************************************/
#ifdef CONFIG_ESP32S3_APP_FORMAT_MCUBOOT
static int map_rom_segments(void)
#if defined(CONFIG_ESP32S3_APP_FORMAT_MCUBOOT) || \
defined(CONFIG_ESPRESSIF_SIMPLE_BOOT)
static int map_rom_segments(uint32_t app_drom_start, uint32_t app_drom_vaddr,
uint32_t app_drom_size, uint32_t app_irom_start,
uint32_t app_irom_vaddr, uint32_t app_irom_size)
{
uint32_t rc = 0;
uint32_t regval;
uint32_t drom_lma_aligned;
uint32_t drom_vma_aligned;
uint32_t drom_page_count;
uint32_t irom_lma_aligned;
uint32_t irom_vma_aligned;
uint32_t irom_page_count;
uint32_t actual_mapped_len = 0;
uint32_t app_irom_start_aligned = app_irom_start & MMU_FLASH_MASK;
uint32_t app_irom_vaddr_aligned = app_irom_vaddr & MMU_FLASH_MASK;
uint32_t app_drom_start_aligned = app_drom_start & MMU_FLASH_MASK;
uint32_t app_drom_vaddr_aligned = app_drom_vaddr & MMU_FLASH_MASK;
size_t partition_offset = PRIMARY_SLOT_OFFSET;
uint32_t app_irom_lma = partition_offset + (uint32_t)_image_irom_lma;
uint32_t app_irom_size = (uint32_t)_image_irom_size;
uint32_t app_irom_vma = (uint32_t)_image_irom_vma;
uint32_t app_drom_lma = partition_offset + (uint32_t)_image_drom_lma;
uint32_t app_drom_size = (uint32_t)_image_drom_size;
uint32_t app_drom_vma = (uint32_t)_image_drom_vma;
#ifdef CONFIG_ESPRESSIF_SIMPLE_BOOT
esp_image_header_t image_header; /* Header for entire image */
esp_image_segment_header_t WORD_ALIGNED_ATTR segment_hdr;
bool padding_checksum = false;
unsigned int segments = 0;
unsigned int ram_segments = 0;
unsigned int rom_segments = 0;
size_t offset = CONFIG_BOOTLOADER_OFFSET_IN_FLASH;
uint32_t autoload = cache_suspend_dcache();
cache_invalidate_dcache_all();
/* Read image header */
/* Clear the MMU entries that are already set up, so the new app only has
* the mappings it creates.
*/
for (size_t i = 0; i < FLASH_MMU_TABLE_SIZE; i++)
if (bootloader_flash_read(offset, &image_header,
sizeof(esp_image_header_t),
true) != ESP_OK)
{
FLASH_MMU_TABLE[i] = MMU_TABLE_INVALID_VAL;
ets_printf("Failed to load image header!\n");
abort();
}
drom_lma_aligned = app_drom_lma & MMU_FLASH_MASK;
drom_vma_aligned = app_drom_vma & MMU_FLASH_MASK;
drom_page_count = calc_mmu_pages(app_drom_size, app_drom_vma);
rc = cache_dbus_mmu_set(MMU_ACCESS_FLASH, drom_vma_aligned,
drom_lma_aligned, 64, drom_page_count, 0);
offset += sizeof(esp_image_header_t);
irom_lma_aligned = app_irom_lma & MMU_FLASH_MASK;
irom_vma_aligned = app_irom_vma & MMU_FLASH_MASK;
irom_page_count = calc_mmu_pages(app_irom_size, app_irom_vma);
rc = cache_ibus_mmu_set(MMU_ACCESS_FLASH, irom_vma_aligned,
irom_lma_aligned, 64, irom_page_count, 0);
/* Iterate for segment information parsing */
regval = getreg32(EXTMEM_DCACHE_CTRL1_REG);
regval &= EXTMEM_DCACHE_SHUT_CORE0_BUS;
putreg32(regval, EXTMEM_DCACHE_CTRL1_REG);
while (segments++ < 16 && rom_segments < 2)
{
/* Read segment header */
cache_resume_dcache(autoload);
if (bootloader_flash_read(offset, &segment_hdr,
sizeof(esp_image_segment_header_t),
true) != ESP_OK)
{
ets_printf("failed to read segment header at %x\n", offset);
abort();
}
if (IS_NONE(segment_hdr.load_addr))
{
break;
}
if (IS_RTC_FAST_IRAM(segment_hdr.load_addr) ||
IS_RTC_FAST_DRAM(segment_hdr.load_addr) ||
IS_RTC_SLOW_DRAM(segment_hdr.load_addr))
{
/* RTC segment is loaded by ROM bootloader */
ram_segments++;
}
ets_printf("%s: lma 0x%08x vma 0x%08x len 0x%-6x (%u)\n",
IS_NONE(segment_hdr.load_addr) ? "???" :
IS_RTC_FAST_IRAM(segment_hdr.load_addr) ||
IS_RTC_FAST_DRAM(segment_hdr.load_addr) ||
IS_RTC_SLOW_DRAM(segment_hdr.load_addr) ? "rtc" :
IS_MMAP(segment_hdr.load_addr) ?
IS_IROM(segment_hdr.load_addr) ? "imap" : "dmap" :
IS_PADD(segment_hdr.load_addr) ? "padd" :
IS_DRAM(segment_hdr.load_addr) ? "dram" : "iram",
offset + sizeof(esp_image_segment_header_t),
segment_hdr.load_addr, segment_hdr.data_len,
segment_hdr.data_len);
/* Fix drom and irom produced be the linker, as this
* is later invalidated by the elf2image command.
*/
if (IS_DROM(segment_hdr.load_addr) &&
segment_hdr.load_addr == (uint32_t)_image_drom_vma)
{
app_drom_start = offset + sizeof(esp_image_segment_header_t);
app_drom_start_aligned = app_drom_start & MMU_FLASH_MASK;
rom_segments++;
}
if (IS_IROM(segment_hdr.load_addr) &&
segment_hdr.load_addr == (uint32_t)_image_irom_vma)
{
app_irom_start = offset + sizeof(esp_image_segment_header_t);
app_irom_start_aligned = app_irom_start & MMU_FLASH_MASK;
rom_segments++;
}
if (IS_SRAM(segment_hdr.load_addr))
{
ram_segments++;
}
offset += sizeof(esp_image_segment_header_t) + segment_hdr.data_len;
if (ram_segments == image_header.segment_count && !padding_checksum)
{
offset += (CHECKSUM_ALIGN - 1) - (offset % CHECKSUM_ALIGN) + 1;
padding_checksum = true;
}
}
if (segments == 0 || segments == 16)
{
ets_printf("Error parsing segments\n");
}
ets_printf("total segments stored %d\n", segments - 1);
#endif
cache_hal_disable(CACHE_TYPE_ALL);
/* Clear the MMU entries that are already set up,
* so the new app only has the mappings it creates.
*/
mmu_hal_unmap_all();
mmu_hal_map_region(0, MMU_TARGET_FLASH0,
app_drom_vaddr_aligned, app_drom_start_aligned,
app_drom_size, &actual_mapped_len);
mmu_hal_map_region(0, MMU_TARGET_FLASH0,
app_irom_vaddr_aligned, app_irom_start_aligned,
app_irom_size, &actual_mapped_len);
/* ------------------Enable corresponding buses--------------------- */
cache_bus_mask_t bus_mask = cache_ll_l1_get_bus(0, app_drom_vaddr_aligned,
app_drom_size);
cache_ll_l1_enable_bus(0, bus_mask);
bus_mask = cache_ll_l1_get_bus(0, app_irom_vaddr_aligned, app_irom_size);
cache_ll_l1_enable_bus(0, bus_mask);
#if CONFIG_ESPRESSIF_NUM_CPUS > 1
bus_mask = cache_ll_l1_get_bus(1, app_drom_vaddr_aligned, app_drom_size);
cache_ll_l1_enable_bus(1, bus_mask);
bus_mask = cache_ll_l1_get_bus(1, app_irom_vaddr_aligned, app_irom_size);
cache_ll_l1_enable_bus(1, bus_mask);
#endif
/* ------------------Enable Cache----------------------------------- */
cache_hal_enable(CACHE_TYPE_ALL);
return (int)rc;
}
@ -520,14 +661,34 @@ static int map_rom_segments(void)
noinstrument_function void IRAM_ATTR __start(void)
{
#ifdef CONFIG_ESP32S3_APP_FORMAT_MCUBOOT
if (map_rom_segments() != 0)
#if defined(CONFIG_ESP32S3_APP_FORMAT_MCUBOOT) || \
defined(CONFIG_ESPRESSIF_SIMPLE_BOOT)
size_t partition_offset = PRIMARY_SLOT_OFFSET;
uint32_t app_irom_start = partition_offset + (uint32_t)_image_irom_lma;
uint32_t app_irom_size = (uint32_t)_image_irom_size;
uint32_t app_irom_vaddr = (uint32_t)_image_irom_vma;
uint32_t app_drom_start = partition_offset + (uint32_t)_image_drom_lma;
uint32_t app_drom_size = (uint32_t)_image_drom_size;
uint32_t app_drom_vaddr = (uint32_t)_image_drom_vma;
# ifdef CONFIG_ESPRESSIF_SIMPLE_BOOT
__asm__ __volatile__ ("wsr %0, vecbase\n"::"r" (_init_start));
if (bootloader_init() != 0)
{
ets_printf("Hardware init failed, aborting\n");
while (true);
}
# endif
if (map_rom_segments(app_drom_start, app_drom_vaddr, app_drom_size,
app_irom_start, app_irom_vaddr, app_irom_size) != 0)
{
ets_printf("Failed to setup XIP, aborting\n");
while (true);
}
#endif
configure_cpu_caches();
__esp32s3_start();

1
arch/xtensa/src/esp32s3/esp32s3_twai.c
View file

@ -48,6 +48,7 @@
#include "periph_ctrl.h"
#include "hardware/esp32s3_system.h"
#include "hardware/esp32s3_twai.h"
#include "hardware/esp32s3_gpio_sigmap.h"
#if defined(CONFIG_ESP32S3_TWAI)

1
arch/xtensa/src/esp32s3/esp32s3_twai.h
View file

@ -27,7 +27,6 @@
#include <nuttx/config.h>
#include <nuttx/can/can.h>
#include "hardware/esp32s3_twai.h"
/****************************************************************************
* Pre-processor Definitions

8
arch/xtensa/src/esp32s3/esp32s3_userspace.c
View file

@ -35,17 +35,18 @@
#include "chip.h"
#include "xtensa.h"
#include "xtensa_attr.h"
#include "esp_attr.h"
#include "esp32s3_irq.h"
#include "esp32s3_userspace.h"
#include "hardware/esp32s3_apb_ctrl.h"
#include "hardware/esp32s3_cache_memory.h"
#include "hardware/esp32s3_extmem.h"
#include "hardware/esp32s3_rom_layout.h"
#include "hardware/esp32s3_sensitive.h"
#include "hardware/esp32s3_soc.h"
#include "hardware/esp32s3_wcl_core.h"
#include "soc/extmem_reg.h"
#ifdef CONFIG_BUILD_PROTECTED
/****************************************************************************
@ -80,9 +81,6 @@
#define WCL_SEQ_LAST_VAL 6
#define I_D_SRAM_OFFSET (SOC_DIRAM_IRAM_LOW - SOC_DIRAM_DRAM_LOW)
#define MAP_IRAM_TO_DRAM(addr) ((addr) - I_D_SRAM_OFFSET)
/* Categories bits for split line configuration */
#define PMS_SRAM_CATEGORY_BELOW 0x0

2
arch/xtensa/src/esp32s3/esp32s3_wifi_adapter.c
View file

@ -54,7 +54,7 @@
#include <nuttx/tls.h>
#include "xtensa.h"
#include "xtensa_attr.h"
#include "esp_attr.h"
#include "hardware/esp32s3_system.h"
#include "hardware/esp32s3_rtccntl.h"
#include "hardware/esp32s3_syscon.h"

2
arch/xtensa/src/esp32s3/esp32s3_wireless.h
View file

@ -31,7 +31,7 @@
#include <nuttx/config.h>
#include <nuttx/list.h>
#include "xtensa_attr.h"
#include "esp_attr.h"
#include "esp32s3_rt_timer.h"
#include "esp_log.h"

57
arch/xtensa/src/esp32s3/hal.mk
View file

@ -20,7 +20,9 @@
# Include header paths
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)$(DELIM)include
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)nuttx$(DELIM)$(CHIP_SERIES)$(DELIM)include
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)nuttx$(DELIM)include
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)include
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)efuse$(DELIM)include
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)efuse$(DELIM)private_include
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)efuse$(DELIM)$(CHIP_SERIES)$(DELIM)include
@ -53,8 +55,11 @@ INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)include
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)xtensa$(DELIM)$(CHIP_SERIES)$(DELIM)include
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)xtensa$(DELIM)include
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)nuttx$(DELIM)$(CHIP_SERIES)$(DELIM)include
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)nuttx$(DELIM)include
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)private_include
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)bootloader_flash$(DELIM)include
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)spi_flash$(DELIM)include
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)spi_flash$(DELIM)include$(DELIM)spi_flash
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_app_format$(DELIM)include
# Linker scripts
@ -78,10 +83,15 @@ CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)cpu_region_protect.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)esp_clk_tree.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)rtc_clk.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)rtc_init.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)rtc_clk_init.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)rtc_sleep.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)rtc_time.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)mspi_timing_config.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)esp_clk_tree_common.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)regi2c_ctrl.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_phy$(DELIM)src$(DELIM)phy_init.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)mspi_timing_tuning.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)patches$(DELIM)esp_rom_wdt.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_system$(DELIM)port$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)clk.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_system$(DELIM)port$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)system_internal.c
@ -95,6 +105,9 @@ CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)rmt_hal.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)timer_hal_iram.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)timer_hal.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)cache_hal.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)mpu_hal.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)mmu_hal.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)uart_hal_iram.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)uart_hal.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)log$(DELIM)log_noos.c
@ -103,4 +116,42 @@ CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)ledc_periph.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)rmt_periph.c
ifeq ($(CONFIG_ESPRESSIF_SIMPLE_BOOT),y)
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)nuttx$(DELIM)src$(DELIM)bootloader_banner_wrap.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)bootloader_console.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)bootloader_console_loader.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)${CHIP_SERIES}$(DELIM)bootloader_${CHIP_SERIES}.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)bootloader_init.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)bootloader_common.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)bootloader_common_loader.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)bootloader_flash$(DELIM)src$(DELIM)bootloader_flash.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)bootloader_flash$(DELIM)src$(DELIM)bootloader_flash_config_${CHIP_SERIES}.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)bootloader_clock_init.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)bootloader_clock_loader.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)bootloader_efuse.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)bootloader_mem.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)bootloader_random.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)bootloader_random_${CHIP_SERIES}.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)esp_image_format.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)${CHIP_SERIES}$(DELIM)bootloader_soc.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)${CHIP_SERIES}$(DELIM)bootloader_sha.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)flash_encrypt.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)${CHIP_SERIES}$(DELIM)uart_periph.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)patches$(DELIM)esp_rom_uart.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)patches$(DELIM)esp_rom_sys.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)patches$(DELIM)esp_rom_systimer.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)patches$(DELIM)esp_rom_spiflash.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)patches$(DELIM)esp_rom_cache_esp32s2_esp32s3.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)efuse$(DELIM)${CHIP_SERIES}$(DELIM)esp_efuse_fields.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)efuse$(DELIM)${CHIP_SERIES}$(DELIM)esp_efuse_utility.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)efuse$(DELIM)src$(DELIM)esp_efuse_fields.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)efuse$(DELIM)src$(DELIM)esp_efuse_utility.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)efuse$(DELIM)src$(DELIM)esp_efuse_api.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)efuse$(DELIM)src$(DELIM)efuse_controller$(DELIM)keys$(DELIM)with_key_purposes$(DELIM)esp_efuse_api_key.c
CHIP_ASRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)patches$(DELIM)esp_rom_cache_writeback_esp32s3.S
LDFLAGS += --wrap=bootloader_print_banner
endif
CFLAGS += ${DEFINE_PREFIX}ESP_PLATFORM=1

74
arch/xtensa/src/esp32s3/hardware/esp32s3_cache_memory.h
View file

@ -25,73 +25,12 @@
#include <stdint.h>
#include "esp32s3_soc.h"
#include "soc/ext_mem_defs.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* IRAM0 is connected with Cache IBUS0 */
#define IRAM0_ADDRESS_LOW 0x40000000
#define IRAM0_ADDRESS_HIGH 0x44000000
#define IRAM0_CACHE_ADDRESS_LOW 0x42000000
#define IRAM0_CACHE_ADDRESS_HIGH 0x44000000
/* DRAM0 is connected with Cache DBUS0 */
#define DRAM0_ADDRESS_LOW 0x3c000000
#define DRAM0_ADDRESS_HIGH 0x40000000
#define DRAM0_CACHE_ADDRESS_LOW 0x3c000000
#define DRAM0_CACHE_ADDRESS_HIGH 0x3e000000
#define DRAM0_CACHE_OPERATION_HIGH DRAM0_CACHE_ADDRESS_HIGH
#define ESP_CACHE_TEMP_ADDR 0x3c800000
#define BUS_SIZE(bus_name) (bus_name##_ADDRESS_HIGH - \
bus_name##_ADDRESS_LOW)
#define ADDRESS_IN_BUS(bus_name, vaddr) ((vaddr) >= bus_name##_ADDRESS_LOW \
&& (vaddr) < \
bus_name##_ADDRESS_HIGH)
#define ADDRESS_IN_IRAM0(vaddr) ADDRESS_IN_BUS(IRAM0, vaddr)
#define ADDRESS_IN_IRAM0_CACHE(vaddr) ADDRESS_IN_BUS(IRAM0_CACHE, vaddr)
#define ADDRESS_IN_DRAM0(vaddr) ADDRESS_IN_BUS(DRAM0, vaddr)
#define ADDRESS_IN_DRAM0_CACHE(vaddr) ADDRESS_IN_BUS(DRAM0_CACHE, vaddr)
#define BUS_IRAM0_CACHE_SIZE BUS_SIZE(IRAM0_CACHE)
#define BUS_DRAM0_CACHE_SIZE BUS_SIZE(DRAM0_CACHE)
#define CACHE_IBUS 0
#define CACHE_IBUS_MMU_START 0
#define CACHE_IBUS_MMU_END 0x800
#define CACHE_DBUS 1
#define CACHE_DBUS_MMU_START 0
#define CACHE_DBUS_MMU_END 0x800
#define CACHE_IROM_MMU_START 0
#define CACHE_IROM_MMU_END Cache_Get_IROM_MMU_End()
#define CACHE_IROM_MMU_SIZE (CACHE_IROM_MMU_END - CACHE_IROM_MMU_START)
#define CACHE_DROM_MMU_START CACHE_IROM_MMU_END
#define CACHE_DROM_MMU_END Cache_Get_DROM_MMU_End()
#define CACHE_DROM_MMU_SIZE (CACHE_DROM_MMU_END - CACHE_DROM_MMU_START)
#define CACHE_DROM_MMU_MAX_END 0x400
#define ICACHE_MMU_SIZE 0x800
#define DCACHE_MMU_SIZE 0x800
#define MMU_BUS_START(i) 0
#define MMU_BUS_SIZE(i) 0x800
#define MMU_INVALID BIT(14)
#define MMU_TYPE BIT(15)
#define MMU_ACCESS_FLASH 0
#define MMU_ACCESS_SPIRAM BIT(15)
#define CACHE_MAX_SYNC_NUM 0x400000
#define CACHE_MAX_LOCK_NUM 0x8000
#define FLASH_MMU_TABLE ((volatile uint32_t *)DR_REG_MMU_TABLE)
#define FLASH_MMU_TABLE_SIZE (ICACHE_MMU_SIZE / sizeof(uint32_t))
@ -104,15 +43,4 @@
#define BUS_ADDR_SIZE 0x200000
#define BUS_ADDR_MASK (BUS_ADDR_SIZE - 1)
#define CACHE_ICACHE_LOW_SHIFT 0
#define CACHE_ICACHE_HIGH_SHIFT 2
#define CACHE_DCACHE_LOW_SHIFT 4
#define CACHE_DCACHE_HIGH_SHIFT 6
#define CACHE_MEMORY_IBANK0_ADDR 0x40370000
#define CACHE_MEMORY_IBANK1_ADDR 0x40374000
#define CACHE_MEMORY_DBANK0_ADDR 0x3fcf0000
#define CACHE_MEMORY_DBANK1_ADDR 0x3fcf8000
#endif /* __ARCH_XTENSA_SRC_ESP32S3_HARDWARE_ESP32S3_CACHE_MEMORY_H */

2761
arch/xtensa/src/esp32s3/hardware/esp32s3_extmem.h
View file

File diff suppressed because it is too large Load diff

402
arch/xtensa/src/esp32s3/hardware/esp32s3_soc.h
View file

@ -30,268 +30,25 @@
#include <stdbool.h>
#endif
#include "xtensa_attr.h"
#include <nuttx/bits.h>
#include "soc/soc.h"
#include "esp_attr.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Register Bits */
#define BIT31 0x80000000
#define BIT30 0x40000000
#define BIT29 0x20000000
#define BIT28 0x10000000
#define BIT27 0x08000000
#define BIT26 0x04000000
#define BIT25 0x02000000
#define BIT24 0x01000000
#define BIT23 0x00800000
#define BIT22 0x00400000
#define BIT21 0x00200000
#define BIT20 0x00100000
#define BIT19 0x00080000
#define BIT18 0x00040000
#define BIT17 0x00020000
#define BIT16 0x00010000
#define BIT15 0x00008000
#define BIT14 0x00004000
#define BIT13 0x00002000
#define BIT12 0x00001000
#define BIT11 0x00000800
#define BIT10 0x00000400
#define BIT9 0x00000200
#define BIT8 0x00000100
#define BIT7 0x00000080
#define BIT6 0x00000040
#define BIT5 0x00000020
#define BIT4 0x00000010
#define BIT3 0x00000008
#define BIT2 0x00000004
#define BIT1 0x00000002
#define BIT0 0x00000001
#define PRO_CPU_NUM (0)
#define APP_CPU_NUM (1)
#define PRO_CPUID (0xcdcd)
#define APP_CPUID (0xabab)
/* Largest span of contiguous memory (DRAM or IRAM) in the address space */
#define SOC_MAX_CONTIGUOUS_RAM_SIZE (SOC_EXTRAM_DATA_HIGH - SOC_EXTRAM_DATA_LOW)
#define DR_REG_UART_BASE 0x60000000
#define DR_REG_SPI1_BASE 0x60002000
#define DR_REG_SPI0_BASE 0x60003000
#define DR_REG_GPIO_BASE 0x60004000
#define DR_REG_GPIO_SD_BASE 0x60004f00
#define DR_REG_FE2_BASE 0x60005000
#define DR_REG_FE_BASE 0x60006000
#define DR_REG_EFUSE_BASE 0x60007000
#define DR_REG_RTCCNTL_BASE 0x60008000
#define DR_REG_RTCIO_BASE 0x60008400
#define DR_REG_SENS_BASE 0x60008800
#define DR_REG_RTC_I2C_BASE 0x60008C00
#define DR_REG_IO_MUX_BASE 0x60009000
#define DR_REG_HINF_BASE 0x6000B000
#define DR_REG_UHCI1_BASE 0x6000C000
#define DR_REG_I2S_BASE 0x6000F000
#define DR_REG_UART1_BASE 0x60010000
#define DR_REG_BT_BASE 0x60011000
#define DR_REG_I2C_EXT_BASE 0x60013000
#define DR_REG_UHCI0_BASE 0x60014000
#define DR_REG_SLCHOST_BASE 0x60015000
#define DR_REG_RMT_BASE 0x60016000
#define DR_REG_PCNT_BASE 0x60017000
#define DR_REG_SLC_BASE 0x60018000
#define DR_REG_LEDC_BASE 0x60019000
#define DR_REG_NRX_BASE 0x6001CC00
#define DR_REG_BB_BASE 0x6001D000
#define DR_REG_PWM0_BASE 0x6001E000
#define DR_REG_TIMERGROUP0_BASE 0x6001F000
#define DR_REG_TIMERGROUP1_BASE 0x60020000
#define DR_REG_RTC_SLOWMEM_BASE 0x60021000
#define DR_REG_SYSTIMER_BASE 0x60023000
#define DR_REG_SPI2_BASE 0x60024000
#define DR_REG_SPI3_BASE 0x60025000
#define DR_REG_SYSCON_BASE 0x60026000
#define DR_REG_APB_CTRL_BASE 0x60026000 /* Old name for SYSCON, to be removed */
#define DR_REG_I2C1_EXT_BASE 0x60027000
#define DR_REG_SDMMC_BASE 0x60028000
#define REG_SPI_BASE(i) (DR_REG_SPI2_BASE + (((i) > 3) ? ((((i) - 2) * 0x1000) + 0x10000) : (((i) - 2) * 0x1000)))
#define DR_REG_PERI_BACKUP_BASE 0x6002A000
#define DR_REG_TWAI_BASE 0x6002B000
#define DR_REG_PWM1_BASE 0x6002C000
#define DR_REG_I2S1_BASE 0x6002D000
#define DR_REG_UART2_BASE 0x6002E000
#define DR_REG_USB_DEVICE_BASE 0x60038000
#define DR_REG_USB_WRAP_BASE 0x60039000
#define DR_REG_AES_BASE 0x6003A000
#define DR_REG_SHA_BASE 0x6003B000
#define DR_REG_RSA_BASE 0x6003C000
#define DR_REG_HMAC_BASE 0x6003E000
#define DR_REG_DIGITAL_SIGNATURE_BASE 0x6003D000
#define DR_REG_GDMA_BASE 0x6003F000
#define DR_REG_APB_SARADC_BASE 0x60040000
#define DR_REG_LCD_CAM_BASE 0x60041000
#define DR_REG_USB_BASE 0x60080000
#define DR_REG_SYSTEM_BASE 0x600C0000
#define DR_REG_SENSITIVE_BASE 0x600C1000
#define DR_REG_INTERRUPT_BASE 0x600C2000
/* Cache configuration */
#define DR_REG_EXTMEM_BASE 0x600C4000
#define DR_REG_MMU_TABLE 0x600C5000
#define DR_REG_ITAG_TABLE 0x600C6000
#define DR_REG_DTAG_TABLE 0x600C8000
#define DR_REG_EXT_MEM_ENC 0x600CC000
#define DR_REG_ASSIST_DEBUG_BASE 0x600CE000
#define DR_REG_WORLD_CNTL_BASE 0x600D0000
#define DR_REG_DPORT_END 0x600D3FFC
#define REG_UHCI_BASE(i) (DR_REG_UHCI0_BASE - (i) * 0x8000)
#define REG_UART_BASE( i ) (DR_REG_UART_BASE + (i) * 0x10000 + ((i) > 1 ? 0xe000 : 0))
#define REG_UART_AHB_BASE(i) (0x60000000 + (i) * 0x10000 + ((i) > 1 ? 0xe000 : 0 ))
#define UART_FIFO_AHB_REG(i) (REG_UART_AHB_BASE(i) + 0x0)
#define REG_I2S_BASE( i ) (DR_REG_I2S_BASE + (i) * 0x1E000)
#define REG_TIMG_BASE(i) (DR_REG_TIMERGROUP0_BASE + (i)*0x1000)
#define REG_SPI_MEM_BASE(i) (DR_REG_SPI0_BASE - (i) * 0x1000)
#define REG_I2C_BASE(i) (DR_REG_I2C_EXT_BASE + (i) * 0x14000)
/* Registers Operation */
#define ETS_UNCACHED_ADDR(addr) (addr)
#define ETS_CACHED_ADDR(addr) (addr)
#ifndef __ASSEMBLY__
/* Write value to register */
#define REG_WRITE(_r, _v) (*(volatile uint32_t *)(_r)) = (_v)
/* Read value from register */
#define REG_READ(_r) (*(volatile uint32_t *)(_r))
/* Get bit or get bits from register */
#define REG_GET_BIT(_r, _b) (*(volatile uint32_t *)(_r) & (_b))
/* Set bit or set bits to register */
#define REG_SET_BIT(_r, _b) (*(volatile uint32_t *)(_r) |= (_b))
/* Clear bit or clear bits of register */
#define REG_CLR_BIT(_r, _b) (*(volatile uint32_t *)(_r) &= ~(_b))
/* Set bits of register controlled by mask */
#define REG_SET_BITS(_r, _b, _m) (*(volatile uint32_t *)(_r) = (*(volatile uint32_t *)(_r) & ~(_m)) | ((_b) & (_m)))
/* Get field from register,
* used when _f is not left shifted by _f##_S
*/
#define REG_GET_FIELD(addr, field) ((getreg32(addr) >> (field##_S)) & (field##_V))
/* Set field to register,
* used when _f is not left shifted by _f##_S
*/
#define REG_SET_FIELD(addr, field, val) (modifyreg32((addr), (field##_M), (((uint32_t) val) & (field##_V)) << (field##_S)))
/* Get field value from a variable,
* used when _f is not left shifted by _f##_S
*/
#define VALUE_GET_FIELD(_r, _f) (((_r) >> (_f##_S)) & (_f))
/* Get field value from a variable,
* used when _f is left shifted by _f##_S
*/
#define VALUE_GET_FIELD2(_r, _f) (((_r) & (_f))>> (_f##_S))
/* Set field value to a variable,
* used when _f is not left shifted by _f##_S
*/
#define VALUE_SET_FIELD(_r, _f, _v) ((_r)=(((_r) & ~((_f) << (_f##_S)))|((_v)<<(_f##_S))))
/* Set field value to a variable,
* used when _f is left shifted by _f##_S
*/
#define VALUE_SET_FIELD2(_r, _f, _v) ((_r)=(((_r) & ~(_f))|((_v)<<(_f##_S))))
/* Generate a value from a field value,
* used when _f is not left shifted by _f##_S
*/
#define FIELD_TO_VALUE(_f, _v) (((_v)&(_f))<<_f##_S)
/* Generate a value from a field value,
* used when _f is left shifted by _f##_S
*/
#define FIELD_TO_VALUE2(_f, _v) (((_v)<<_f##_S) & (_f))
/* Read value from register */
#define READ_PERI_REG(addr) (*((volatile uint32_t *)ETS_UNCACHED_ADDR(addr)))
/* Write value to register */
#define WRITE_PERI_REG(addr, val) (*((volatile uint32_t *)ETS_UNCACHED_ADDR(addr))) = (uint32_t)(val)
/* Clear bits of register controlled by mask */
#define CLEAR_PERI_REG_MASK(reg, mask) WRITE_PERI_REG((reg), (READ_PERI_REG(reg)&(~(mask))))
/* Set bits of register controlled by mask */
#define SET_PERI_REG_MASK(reg, mask) WRITE_PERI_REG((reg), (READ_PERI_REG(reg)|(mask)))
/* Get bits of register controlled by mask */
#define GET_PERI_REG_MASK(reg, mask) (READ_PERI_REG(reg) & (mask))
/* Get bits of register controlled by highest bit and lowest bit */
#define GET_PERI_REG_BITS(reg, hipos,lowpos) ((READ_PERI_REG(reg)>>(lowpos))&((1<<((hipos)-(lowpos)+1))-1))
/* Set bits of register controlled by mask and shift */
#define SET_PERI_REG_BITS(reg,bit_map,value,shift) (WRITE_PERI_REG((reg),(READ_PERI_REG(reg)&(~((bit_map)<<(shift))))|(((value) & bit_map)<<(shift)) ))
/* Get field of register */
#define GET_PERI_REG_BITS2(reg, mask,shift) ((READ_PERI_REG(reg)>>(shift))&(mask))
/* Extract the field from the register and shift it to avoid wrong reading */
#define REG_MASK(_reg, _field) ((_reg & (_field##_M)) >> (_field##_S))
@ -304,129 +61,7 @@
/* Peripheral Clock */
#define APB_CLK_FREQ_ROM (40*1000000)
#define CPU_CLK_FREQ_ROM (40*1000000)
#define UART_CLK_FREQ_ROM (40*1000000)
#define EFUSE_CLK_FREQ_ROM (20*1000000)
#define CPU_CLK_FREQ APB_CLK_FREQ
#define APB_CLK_FREQ (80*1000000)
#define REF_CLK_FREQ (1000000)
#define RTC_CLK_FREQ (20*1000000)
#define XTAL_CLK_FREQ (40*1000000)
#define UART_CLK_FREQ APB_CLK_FREQ
#define WDT_CLK_FREQ APB_CLK_FREQ
#define TIMER_CLK_FREQ (80000000>>4)
#define SPI_CLK_DIV 4
#define TICKS_PER_US_ROM 40
#define GPIO_MATRIX_DELAY_NS 0
/* Overall memory map */
#define SOC_DROM_LOW 0x3C000000
#define SOC_DROM_HIGH 0x3D000000
#define SOC_IROM_LOW 0x42000000
#define SOC_IROM_HIGH 0x44000000
#define SOC_IRAM_LOW 0x40370000
#define SOC_IRAM_HIGH 0x403E0000
#define SOC_DRAM_LOW 0x3FC88000
#define SOC_DRAM_HIGH 0x3FD00000
#define SOC_RTC_IRAM_LOW 0x600FE000
#define SOC_RTC_IRAM_HIGH 0x60100000
#define SOC_RTC_DRAM_LOW 0x600FE000
#define SOC_RTC_DRAM_HIGH 0x60100000
#define SOC_RTC_DATA_LOW 0x50000000
#define SOC_RTC_DATA_HIGH 0x50002000
#define SOC_EXTRAM_DATA_LOW 0x3C000000
#define SOC_EXTRAM_DATA_HIGH 0x3E000000
#define SOC_IROM_MASK_LOW 0x40000000
#define SOC_IROM_MASK_HIGH 0x4001A100
#define SOC_EXTRAM_DATA_SIZE (SOC_EXTRAM_DATA_HIGH - SOC_EXTRAM_DATA_LOW)
/* First and last words of the D/IRAM region, for both the DRAM address
* as well as the IRAM alias.
*/
#define SOC_DIRAM_IRAM_LOW 0x40378000
#define SOC_DIRAM_IRAM_HIGH 0x403E0000
#define SOC_DIRAM_DRAM_LOW 0x3FC88000
#define SOC_DIRAM_DRAM_HIGH 0x3FCF0000
/* Region of memory accessible via DMA in internal memory.
* See esp_ptr_dma_capable().
*/
#define SOC_DMA_LOW 0x3FC88000
#define SOC_DMA_HIGH 0x3FD00000
/* Region of memory accessible via DMA in external memory.
* See esp_ptr_dma_ext_capable().
*/
#define SOC_DMA_EXT_LOW SOC_EXTRAM_DATA_LOW
#define SOC_DMA_EXT_HIGH SOC_EXTRAM_DATA_HIGH
/* Region of memory that is byte-accessible.
* See esp_ptr_byte_accessible().
*/
#define SOC_BYTE_ACCESSIBLE_LOW 0x3FC88000
#define SOC_BYTE_ACCESSIBLE_HIGH 0x3FD00000
/* Region of memory that is internal, as in on the same silicon die as the
* ESP32 CPUs (excluding RTC data region, that's checked separately.)
* See esp_ptr_internal().
*/
#define SOC_MEM_INTERNAL_LOW 0x3FC88000
#define SOC_MEM_INTERNAL_HIGH 0x403E2000
/* Start (highest address) of ROM boot stack, only relevant during
* early boot
*/
#define SOC_ROM_STACK_START 0x3fcebf10
/* Interrupt cpu using table, Please see the core-isa.h */
/****************************************************************************
* Intr num Level Type PRO CPU usage APP CPU usage
* 0 1 extern level WMAC Reserved
* 1 1 extern level BT/BLE Host HCI DMA BT/BLE Host HCI DMA
* 2 1 extern level
* 3 1 extern level
* 4 1 extern level WBB
* 5 1 extern level BT/BLE Controller BT/BLE Controller
* 6 1 timer FreeRTOS Tick(L1) FreeRTOS Tick(L1)
* 7 1 software BT/BLE VHCI BT/BLE VHCI
* 8 1 extern level BT/BLE BB(RX/TX) BT/BLE BB(RX/TX)
* 9 1 extern level
* 10 1 extern edge
* 11 3 profiling
* 12 1 extern level
* 13 1 extern level
* 14 7 nmi Reserved Reserved
* 15 3 timer FreeRTOS Tick(L3) FreeRTOS Tick(L3)
* 16 5 timer
* 17 1 extern level
* 18 1 extern level
* 19 2 extern level
* 20 2 extern level
* 21 2 extern level
* 22 3 extern edge
* 23 3 extern level
* 24 4 extern level TG1_WDT
* 25 4 extern level CACHEERR
* 26 5 extern level
* 27 3 extern level Reserved Reserved
* 28 4 extern edge DPORT ACCESS DPORT ACCESS
* 29 3 software Reserved Reserved
* 30 4 extern edge Reserved Reserved
* 31 5 extern level
****************************************************************************/
/* Core voltage needs to be increased in two cases:
* 1. running at 240 MHz
@ -442,37 +77,6 @@
#define DIG_DBIAS_XTAL RTC_CNTL_DBIAS_1V10
#define DIG_DBIAS_2M RTC_CNTL_DBIAS_1V00
/* CPU0 Interrupt number reserved, not touch this. */
#define ETS_WMAC_INUM 0
#define ETS_BT_HOST_INUM 1
#define ETS_WBB_INUM 4
#define ETS_TG0_T1_INUM 10 /* use edge interrupt*/
#define ETS_FRC1_INUM 22
#define ETS_T1_WDT_INUM 24
#define ETS_CACHEERR_INUM 25
#define ETS_DPORT_INUM 28
/* CPU0 Interrupt number used in ROM, should be cancelled in SDK */
#define ETS_SLC_INUM 1
#define ETS_UART0_INUM 5
#define ETS_UART1_INUM 5
#define ETS_SPI2_INUM 1
/* CPU0 Interrupt number used in ROM code only when module init function
* called, should pay attention here.
*/
#define ETS_FRC_TIMER2_INUM 10 /* use edge*/
#define ETS_GPIO_INUM 4
/* Other interrupt number should be managed by the user */
/* Invalid interrupt for number interrupt matrix */
#define ETS_INVALID_INUM 6
#define MHZ (1000000)
#define RTC_PLL_FREQ_320M 320
#define RTC_PLL_FREQ_480M 480

3586
arch/xtensa/src/esp32s3/hardware/esp32s3_spi_mem_reg.h
View file

File diff suppressed because it is too large Load diff

40
arch/xtensa/src/esp32s3/hardware/esp32s3_usb_serial_jtag.h
View file

@ -37,7 +37,7 @@
* USB_SERIAL_JTAG_EP1_REG.
*/
#define USB_SERIAL_JTAG_EP1_REG (DR_REG_USB_DEVICE_BASE + 0x0)
#define USB_SERIAL_JTAG_EP1_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x0)
/* USB_SERIAL_JTAG_RDWR_BYTE : R/W; bitpos: [8:0]; default: 0;
* Write and read byte data to/from UART Tx/Rx FIFO through this field.
@ -59,7 +59,7 @@
* USB_SERIAL_JTAG_CONF0_REG.
*/
#define USB_SERIAL_JTAG_CONF0_REG (DR_REG_USB_DEVICE_BASE + 0x18)
#define USB_SERIAL_JTAG_CONF0_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x18)
/* USB_SERIAL_JTAG_PHY_SEL : R/W; bitpos: [0]; default: 0;
* Select internal/external PHY. 1’b0: internal PHY, 1’b1: external
@ -195,7 +195,7 @@
* USB_SERIAL_JTAG_TEST_REG.
*/
#define USB_SERIAL_JTAG_TEST_REG (DR_REG_USB_DEVICE_BASE + 0x1c)
#define USB_SERIAL_JTAG_TEST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x1c)
/* USB_SERIAL_JTAG_TEST_ENABLE : R/W; bitpos: [0]; default: 0;
* Enable test of the USB
@ -241,7 +241,7 @@
* USB_SERIAL_JTAG_MISC_CONF_REG.
*/
#define USB_SERIAL_JTAG_MISC_CONF_REG (DR_REG_USB_DEVICE_BASE + 0x44)
#define USB_SERIAL_JTAG_MISC_CONF_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x44)
/* USB_SERIAL_JTAG_CLK_EN : R/W; bitpos: [0]; default: 0;
* 1'h1: Force clock on for register. 1'h0: Support clock only when
@ -258,7 +258,7 @@
* USB_SERIAL_JTAG_MEM_CONF_REG.
*/
#define USB_SERIAL_JTAG_MEM_CONF_REG (DR_REG_USB_DEVICE_BASE + 0x48)
#define USB_SERIAL_JTAG_MEM_CONF_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x48)
/* USB_SERIAL_JTAG_USB_MEM_PD : R/W; bitpos: [0]; default: 0;
* 1: power down usb
@ -286,7 +286,7 @@
* USB_SERIAL_JTAG_EP1_CONF_REG.
*/
#define USB_SERIAL_JTAG_EP1_CONF_REG (DR_REG_USB_DEVICE_BASE + 0x4)
#define USB_SERIAL_JTAG_EP1_CONF_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x4)
/* USB_SERIAL_JTAG_WR_DONE : WT; bitpos: [0]; default: 0;
* Set this bit to indicate writing byte data to UART Tx FIFO is done.
@ -325,7 +325,7 @@
* USB_SERIAL_JTAG_JFIFO_ST_REG.
*/
#define USB_SERIAL_JTAG_JFIFO_ST_REG (DR_REG_USB_DEVICE_BASE + 0x20)
#define USB_SERIAL_JTAG_JFIFO_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x20)
/* USB_SERIAL_JTAG_IN_FIFO_CNT : RO; bitpos: [2:0]; default: 0;
* JTAG in fifo
* counter.
@ -410,7 +410,7 @@
* USB_SERIAL_JTAG_FRAM_NUM_REG.
*/
#define USB_SERIAL_JTAG_FRAM_NUM_REG (DR_REG_USB_DEVICE_BASE + 0x24)
#define USB_SERIAL_JTAG_FRAM_NUM_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x24)
/* USB_SERIAL_JTAG_SOF_FRAME_INDEX : RO; bitpos: [11:0]; default: 0;
* Frame index of received SOF
@ -426,7 +426,7 @@
* USB_SERIAL_JTAG_IN_EP0_ST_REG.
*/
#define USB_SERIAL_JTAG_IN_EP0_ST_REG (DR_REG_USB_DEVICE_BASE + 0x28)
#define USB_SERIAL_JTAG_IN_EP0_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x28)
/* USB_SERIAL_JTAG_IN_EP0_STATE : RO; bitpos: [2:0]; default: 1;
* State of IN Endpoint 0.
@ -459,7 +459,7 @@
* USB_SERIAL_JTAG_IN_EP1_ST_REG.
*/
#define USB_SERIAL_JTAG_IN_EP1_ST_REG (DR_REG_USB_DEVICE_BASE + 0x2c)
#define USB_SERIAL_JTAG_IN_EP1_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x2c)
/* USB_SERIAL_JTAG_IN_EP1_STATE : RO; bitpos: [2:0]; default: 1;
* State of IN Endpoint 1.
@ -493,7 +493,7 @@
* USB_SERIAL_JTAG_IN_EP2_ST_REG.
*/
#define USB_SERIAL_JTAG_IN_EP2_ST_REG (DR_REG_USB_DEVICE_BASE + 0x30)
#define USB_SERIAL_JTAG_IN_EP2_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x30)
/* USB_SERIAL_JTAG_IN_EP2_STATE : RO; bitpos: [2:0]; default: 1;
* State of IN Endpoint
@ -529,7 +529,7 @@
* USB_SERIAL_JTAG_IN_EP3_ST_REG.
*/
#define USB_SERIAL_JTAG_IN_EP3_ST_REG (DR_REG_USB_DEVICE_BASE + 0x34)
#define USB_SERIAL_JTAG_IN_EP3_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x34)
/* USB_SERIAL_JTAG_IN_EP3_STATE : RO; bitpos: [2:0]; default: 1;
* State of IN Endpoint
@ -565,7 +565,7 @@
* USB_SERIAL_JTAG_OUT_EP0_ST_REG.
*/
#define USB_SERIAL_JTAG_OUT_EP0_ST_REG (DR_REG_USB_DEVICE_BASE + 0x38)
#define USB_SERIAL_JTAG_OUT_EP0_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x38)
/* USB_SERIAL_JTAG_OUT_EP0_STATE : RO; bitpos: [2:0]; default: 0;
* State of OUT Endpoint
@ -603,7 +603,7 @@
* USB_SERIAL_JTAG_OUT_EP1_ST_REG.
*/
#define USB_SERIAL_JTAG_OUT_EP1_ST_REG (DR_REG_USB_DEVICE_BASE + 0x3c)
#define USB_SERIAL_JTAG_OUT_EP1_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x3c)
/* USB_SERIAL_JTAG_OUT_EP1_STATE : RO; bitpos: [2:0]; default: 0;
* State of OUT Endpoint
@ -651,7 +651,7 @@
* USB_SERIAL_JTAG_OUT_EP2_ST_REG.
*/
#define USB_SERIAL_JTAG_OUT_EP2_ST_REG (DR_REG_USB_DEVICE_BASE + 0x40)
#define USB_SERIAL_JTAG_OUT_EP2_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x40)
/* USB_SERIAL_JTAG_OUT_EP2_STATE : RO; bitpos: [2:0]; default: 0;
* State of OUT Endpoint
@ -691,7 +691,7 @@
* USB_SERIAL_JTAG_INT_RAW_REG.
*/
#define USB_SERIAL_JTAG_INT_RAW_REG (DR_REG_USB_DEVICE_BASE + 0x8)
#define USB_SERIAL_JTAG_INT_RAW_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x8)
/* USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
* The raw interrupt bit turns to high level when a flush command is
@ -828,7 +828,7 @@
* USB_SERIAL_JTAG_INT_ST_REG.
*/
#define USB_SERIAL_JTAG_INT_ST_REG (DR_REG_USB_DEVICE_BASE + 0xc)
#define USB_SERIAL_JTAG_INT_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0xc)
/* USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST : RO; bitpos: [0]; default: 0;
* The raw interrupt status bit for the USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT
@ -959,7 +959,7 @@
* USB_SERIAL_JTAG_INT_ENA_REG.
*/
#define USB_SERIAL_JTAG_INT_ENA_REG (DR_REG_USB_DEVICE_BASE + 0x10)
#define USB_SERIAL_JTAG_INT_ENA_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x10)
/* USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA : R/W; bitpos: [0]; default: 0;
* The interrupt enable bit for the USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT
* interrupt.
@ -1090,7 +1090,7 @@
* USB_SERIAL_JTAG_INT_CLR_REG.
*/
#define USB_SERIAL_JTAG_INT_CLR_REG (DR_REG_USB_DEVICE_BASE + 0x14)
#define USB_SERIAL_JTAG_INT_CLR_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x14)
/* USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR : WT; bitpos: [0]; default: 0;
* Set this bit to clear the USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT
@ -1219,7 +1219,7 @@
* USB_SERIAL_JTAG_DATE_REG.
*/
#define USB_SERIAL_JTAG_DATE_REG (DR_REG_USB_DEVICE_BASE + 0x80)
#define USB_SERIAL_JTAG_DATE_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x80)
/* USB_SERIAL_JTAG_DATE : R/W; bitpos: [32:0]; default: 33583872;
* register version.

355
arch/xtensa/src/esp32s3/rom/esp32s3_opi_flash.h
View file

@ -1,355 +0,0 @@
/*****************************************************************************
* arch/xtensa/src/esp32s3/rom/esp32s3_opi_flash.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
*****************************************************************************/
#ifndef __ARCH_XTENSA_SRC_ESP32S3_ROM_ESP32S3_OPI_FLASH_H
#define __ARCH_XTENSA_SRC_ESP32S3_ROM_ESP32S3_OPI_FLASH_H
/*****************************************************************************
* Included Files
*****************************************************************************/
#include <stdio.h>
#include <string.h>
#include <stdint.h>
#include <stdbool.h>
#ifdef __cplusplus
extern "C"
{
#endif
typedef struct
{
uint8_t mode;
uint8_t cmd_bit_len;
uint16_t cmd;
uint32_t addr;
uint8_t addr_bit_len;
uint8_t dummy_bit_len;
uint8_t data_bit_len;
uint8_t cs_sel: 4;
uint8_t is_pe: 4;
} esp_rom_opiflash_cmd_t;
typedef struct
{
uint8_t addr_bit_len;
uint8_t dummy_bit_len;
uint16_t cmd;
uint8_t cmd_bit_len;
uint8_t var_dummy_en;
} esp_rom_opiflash_spi0rd_t;
typedef struct
{
esp_rom_opiflash_cmd_t rdid;
esp_rom_opiflash_cmd_t rdsr;
esp_rom_opiflash_cmd_t wren;
esp_rom_opiflash_cmd_t se;
esp_rom_opiflash_cmd_t be64k;
esp_rom_opiflash_cmd_t read;
esp_rom_opiflash_cmd_t pp;
esp_rom_opiflash_spi0rd_t cache_rd_cmd;
} esp_rom_opiflash_def_t;
typedef struct
{
uint16_t cmd; /* !< Command value */
uint16_t cmd_bit_len; /* !< Command byte length */
uint32_t *addr; /* !< Point to address value */
uint32_t addr_bit_len; /* !< Address byte length */
uint32_t *tx_data; /* !< Point to send data buffer */
uint32_t tx_data_bit_len; /* !< Send data byte length. */
uint32_t *rx_data; /* !< Point to recevie data buffer */
uint32_t rx_data_bit_len; /* !< Recevie Data byte length. */
uint32_t dummy_bit_len;
} esp_rom_spi_cmd_t;
#define ESP_ROM_OPIFLASH_MUX_TAKE()
#define ESP_ROM_OPIFLASH_MUX_GIVE()
#define ESP_ROM_OPIFLASH_SEL_CS0 (BIT(0))
#define ESP_ROM_OPIFLASH_SEL_CS1 (BIT(1))
/* Definition of MX25UM25645G Octa Flash
* SPI status register
*/
#define ESP_ROM_SPIFLASH_BUSY_FLAG BIT0
#define ESP_ROM_SPIFLASH_WRENABLE_FLAG BIT1
#define ESP_ROM_SPIFLASH_BP0 BIT2
#define ESP_ROM_SPIFLASH_BP1 BIT3
#define ESP_ROM_SPIFLASH_BP2 BIT4
#define ESP_ROM_SPIFLASH_QE BIT9
#define FLASH_OP_MODE_RDCMD_DOUT 0x3B
#define ESP_ROM_FLASH_SECTOR_SIZE 0x1000
#define ESP_ROM_FLASH_BLOCK_SIZE_64K 0x10000
#define ESP_ROM_FLASH_PAGE_SIZE 256
/* FLASH commands */
#define ROM_FLASH_CMD_RDID 0x9F
#define ROM_FLASH_CMD_WRSR 0x01
#define ROM_FLASH_CMD_WRSR2 0x31 /* Not all SPI flash uses this command */
#define ROM_FLASH_CMD_WREN 0x06
#define ROM_FLASH_CMD_WRDI 0x04
#define ROM_FLASH_CMD_RDSR 0x05
#define ROM_FLASH_CMD_RDSR2 0x35 /* Not all SPI flash uses this command */
#define ROM_FLASH_CMD_ERASE_SEC 0x20
#define ROM_FLASH_CMD_ERASE_BLK_32K 0x52
#define ROM_FLASH_CMD_ERASE_BLK_64K 0xD8
#define ROM_FLASH_CMD_OTPEN 0x3A /* Enable OTP mode, not all SPI flash uses this command */
#define ROM_FLASH_CMD_RSTEN 0x66
#define ROM_FLASH_CMD_RST 0x99
#define ROM_FLASH_CMD_SE4B 0x21
#define ROM_FLASH_CMD_SE4B_OCT 0xDE21
#define ROM_FLASH_CMD_BE4B 0xDC
#define ROM_FLASH_CMD_BE4B_OCT 0x23DC
#define ROM_FLASH_CMD_RSTEN_OCT 0x9966
#define ROM_FLASH_CMD_RST_OCT 0x6699
#define ROM_FLASH_CMD_FSTRD4B_STR 0x13EC
#define ROM_FLASH_CMD_FSTRD4B_DTR 0x11EE
#define ROM_FLASH_CMD_FSTRD4B 0x0C
#define ROM_FLASH_CMD_PP4B 0x12
#define ROM_FLASH_CMD_PP4B_OCT 0xED12
#define ROM_FLASH_CMD_RDID_OCT 0x609F
#define ROM_FLASH_CMD_WREN_OCT 0xF906
#define ROM_FLASH_CMD_RDSR_OCT 0xFA05
#define ROM_FLASH_CMD_RDCR2 0x71
#define ROM_FLASH_CMD_RDCR2_OCT 0x8E71
#define ROM_FLASH_CMD_WRCR2 0x72
#define ROM_FLASH_CMD_WRCR2_OCT 0x8D72
/* Definitions for GigaDevice GD25LX256E Flash */
#define ROM_FLASH_CMD_RDFSR_GD 0x70
#define ROM_FLASH_CMD_RD_GD 0x03
#define ROM_FLASH_CMD_RD4B_GD 0x13
#define ROM_FLASH_CMD_FSTRD_GD 0x0B
#define ROM_FLASH_CMD_FSTRD4B_GD 0x0C
#define ROM_FLASH_CMD_FSTRD_OOUT_GD 0x8B
#define ROM_FLASH_CMD_FSTRD4B_OOUT_GD 0x7C
#define ROM_FLASH_CMD_FSTRD_OIOSTR_GD 0xCB
#define ROM_FLASH_CMD_FSTRD4B_OIOSTR_GD 0xCC
#define ROM_FLASH_CMD_FSTRD4B_OIODTR_GD 0xFD
#define ROM_FLASH_CMD_PP_GD 0x02
#define ROM_FLASH_CMD_PP4B_GD 0x12
#define ROM_FLASH_CMD_PP_OOUT_GD 0x82
#define ROM_FLASH_CMD_PP4B_OOUT_GD 0x84
#define ROM_FLASH_CMD_PP_OIO_GD 0xC2
#define ROM_FLASH_CMD_PP4B_OIOSTR_GD 0x8E
#define ROM_FLASH_CMD_SE_GD 0x20
#define ROM_FLASH_CMD_SE4B_GD 0x21
#define ROM_FLASH_CMD_BE32K_GD 0x52
#define ROM_FLASH_CMD_BE32K4B_GD 0x5C
#define ROM_FLASH_CMD_BE64K_GD 0xD8
#define ROM_FLASH_CMD_BE64K4B_GD 0xDC
#define ROM_FLASH_CMD_EN4B_GD 0xB7
#define ROM_FLASH_CMD_DIS4B_GD 0xE9
extern const esp_rom_opiflash_def_t *rom_opiflash_cmd_def;
/* Init legacy driver for Octal Flash */
void esp_rom_opiflash_legacy_driver_init(const esp_rom_opiflash_def_t
*flash_cmd_def);
/* Config the spi user command
* spi_num spi port
* pcmd pointer to accept the spi command struct
*/
void esp_rom_spi_cmd_config(int spi_num, esp_rom_spi_cmd_t *pcmd);
/* Start a spi user command sequence
* spi_num spi port
* rx_buf buffer pointer to receive data
* rx_len receive data length in byte
* cs_en_mask decide which cs to use, 0 for cs0, 1 for cs1
* is_write_erase to indicate whether this is a write or erase
* operation, since the CPU would check permission
*/
void esp_rom_spi_cmd_start(int spi_num, uint8_t *rx_buf, uint16_t rx_len,
uint8_t cs_en_mask, bool is_write_erase);
/* Config opi flash pads according to efuse settings. */
void esp_rom_opiflash_pin_config(void);
/* Set SPI read/write operation mode
* spi_num spi port
* mode Flash Read Mode
*/
void esp_rom_spi_set_op_mode(int spi_num, esp_rom_spiflash_read_mode_t mode);
/* Set data swap mode in DTR(DDR) mode
* spi_num spi port
* wr_swap to decide whether to swap fifo data in dtr write operation
* rd_swap to decide whether to swap fifo data in dtr read operation
*/
void esp_rom_spi_set_dtr_swap_mode(int spi, bool wr_swap, bool rd_swap);
/* To send reset command in spi/opi-str/opi-dtr mode(for MX25UM25645G)
* spi_num spi port
*/
void esp_rom_opiflash_mode_reset(int spi_num);
/* To execute a flash operation command
* spi_num spi port
* mode Flash Read Mode
* cmd data to send in command field
* cmd_bit_len bit length of command field
* addr data to send in address field
* addr_bit_len bit length of address field
* dummy_bits bit length of dummy field
* mosi_data data buffer to be sent in mosi field
* mosi_bit_len bit length of data buffer to be sent in mosi field
* miso_data data buffer to accept data in miso field
* miso_bit_len bit length of data buffer to accept data in miso field
* cs_mark decide which cs pin to use. 0: cs0, 1: cs1
* is_write_erase_operation to indicate whether this a write or erase
* flash operation
*/
void esp_rom_opiflash_exec_cmd(int spi_num, esp_rom_spiflash_read_mode_t mode,
uint32_t cmd, int cmd_bit_len,
uint32_t addr, int addr_bit_len,
int dummy_bits,
uint8_t *mosi_data, int mosi_bit_len,
uint8_t *miso_data, int miso_bit_len,
uint32_t cs_mask,
bool is_write_erase_operation);
/* Send reset command to opi flash
* spi_num spi port
* mode Flash Operation Mode
*/
void esp_rom_opiflash_soft_reset(int spi_num,
esp_rom_spiflash_read_mode_t mode);
/* To read opi flash ID
* command format would be defined in initialization
* out_id buffer to accept id
* Return flash operation result
*/
esp_rom_spiflash_result_t esp_rom_opiflash_read_id(uint8_t *out_id);
/* To read opi flash status register
* command format would be defined in initialization
* Return opi flash status value
*/
uint8_t esp_rom_opiflash_rdsr(void);
/* Wait opi flash status register to be idle
* command format would be defined in initialization
* Return flash operation result
*/
esp_rom_spiflash_result_t esp_rom_opiflash_wait_idle(void);
/* To erase flash sector
* command format would be defined in initialization
* sector_num the sector to be erased
* Return flash operation result
*/
esp_rom_spiflash_result_t
esp_rom_opiflash_erase_sector(uint32_t sector_num);
/* Erase flash block
* command format would be defined in initialization
* block_num the block to be erased
* Return flash operation result
*/
esp_rom_spiflash_result_t
esp_rom_opiflash_erase_block_64k(uint32_t block_num);
/* To erase a flash area define by start address and length
* command format would be defined in initialization
* start_addr the start address to be erased
* area_len the erea length to be erased
* Return flash operation result
*/
esp_rom_spiflash_result_t esp_rom_opiflash_erase_area(uint32_t start_addr,
uint32_t area_len);
/* To read data from opi flash
* command format would be defined in initialization
* flash_addr flash address to read data from
* data_addr data buffer to accept the data
* len data length to be read
* Return flash operation result
*/
esp_rom_spiflash_result_t esp_rom_opiflash_read(uint32_t flash_addr,
void *data_addr,
int len);
/* To write data to opi flash
* command format would be defined in initialization
* flash_addr flash address to write data to
* data_addr data buffer to write to flash
* len data length to write
* Return flash operation result
*/
esp_rom_spiflash_result_t esp_rom_opiflash_write(uint32_t flash_addr,
const uint32_t *data_addr,
int len);
/* Send WREN command
* command format would be defined in initialization
* arg not used, set to NULL
* Return flash operation result
*/
esp_rom_spiflash_result_t esp_rom_opiflash_wren(void *arg);
/* To configure SPI0 read flash command format for cache
* command format would be defined in initialization
*/
void
esp_rom_opiflash_cache_mode_config(esp_rom_spiflash_read_mode_t mode,
const esp_rom_opiflash_spi0rd_t *cache);
esp_rom_spiflash_result_t esp_rom_opiflash_read_raw(uint32_t flash_addr,
uint8_t *buf, int len);
#ifdef __cplusplus
}
#endif
#endif /* __ARCH_XTENSA_SRC_ESP32S3_ROM_ESP32S3_OPI_FLASH_H */

127
arch/xtensa/src/esp32s3/rom/esp32s3_spiflash.h
View file

@ -28,6 +28,11 @@
#include <stdint.h>
#include <stdbool.h>
#include "esp_rom_spiflash.h"
#include "rom/spi_flash.h"
#include "rom/opi_flash.h"
#include "esp_private/spi_flash_os.h"
#ifdef __cplusplus
extern "C"
{
@ -37,118 +42,16 @@ extern "C"
* Pre-processor Definitions
*****************************************************************************/
#define PERIPHS_SPI_FLASH_CMD SPI_CMD_REG(1)
#define PERIPHS_SPI_FLASH_ADDR SPI_ADDR_REG(1)
#define PERIPHS_SPI_FLASH_CTRL SPI_CTRL_REG(1)
#define PERIPHS_SPI_FLASH_CTRL1 SPI_CTRL1_REG(1)
#define PERIPHS_SPI_FLASH_STATUS SPI_RD_STATUS_REG(1)
#define PERIPHS_SPI_FLASH_USRREG SPI_USER_REG(1)
#define PERIPHS_SPI_FLASH_USRREG1 SPI_USER1_REG(1)
#define PERIPHS_SPI_FLASH_USRREG2 SPI_USER2_REG(1)
#define PERIPHS_SPI_FLASH_C0 SPI_W0_REG(1)
#define PERIPHS_SPI_FLASH_C1 SPI_W1_REG(1)
#define PERIPHS_SPI_FLASH_C2 SPI_W2_REG(1)
#define PERIPHS_SPI_FLASH_C3 SPI_W3_REG(1)
#define PERIPHS_SPI_FLASH_C4 SPI_W4_REG(1)
#define PERIPHS_SPI_FLASH_C5 SPI_W5_REG(1)
#define PERIPHS_SPI_FLASH_C6 SPI_W6_REG(1)
#define PERIPHS_SPI_FLASH_C7 SPI_W7_REG(1)
#define PERIPHS_SPI_FLASH_TX_CRC SPI_TX_CRC_REG(1)
#define SPI1_R_QIO_DUMMY_CYCLELEN 5
#define SPI1_R_QIO_ADDR_BITSLEN 23
#define SPI1_R_FAST_DUMMY_CYCLELEN 7
#define SPI1_R_DIO_DUMMY_CYCLELEN 3
#define SPI1_R_DIO_ADDR_BITSLEN 23
#define SPI1_R_FAST_ADDR_BITSLEN 23
#define SPI1_R_SIO_ADDR_BITSLEN 23
#define ESP_ROM_SPIFLASH_W_SIO_ADDR_BITSLEN 23
#define ESP_ROM_SPIFLASH_TWO_BYTE_STATUS_EN SPI_WRSR_2B
/* SPI address register */
#define ESP_ROM_SPIFLASH_BYTES_LEN 24
#define ESP_ROM_SPIFLASH_BUFF_BYTE_WRITE_NUM 32
#define ESP_ROM_SPIFLASH_BUFF_BYTE_READ_NUM 64
#define ESP_ROM_SPIFLASH_BUFF_BYTE_READ_BITS 0x3f
/* SPI status register */
#define ESP_ROM_SPIFLASH_BUSY_FLAG BIT0
#define ESP_ROM_SPIFLASH_WRENABLE_FLAG BIT1
#define ESP_ROM_SPIFLASH_BP0 BIT2
#define ESP_ROM_SPIFLASH_BP1 BIT3
#define ESP_ROM_SPIFLASH_BP2 BIT4
#define ESP_ROM_SPIFLASH_WR_PROTECT (ESP_ROM_SPIFLASH_BP0 | \
ESP_ROM_SPIFLASH_BP1 | \
ESP_ROM_SPIFLASH_BP2)
#define ESP_ROM_SPIFLASH_QE BIT9
/* Extra dummy for flash read */
#define ESP_ROM_SPIFLASH_DUMMY_LEN_PLUS_20M 0
#define ESP_ROM_SPIFLASH_DUMMY_LEN_PLUS_40M 1
#define ESP_ROM_SPIFLASH_DUMMY_LEN_PLUS_80M 2
#define FLASH_ID_GD25LQ32C 0xC86016
/*****************************************************************************
* Public Types
*****************************************************************************/
typedef enum
{
ESP_ROM_SPIFLASH_QIO_MODE = 0,
ESP_ROM_SPIFLASH_QOUT_MODE,
ESP_ROM_SPIFLASH_DIO_MODE,
ESP_ROM_SPIFLASH_DOUT_MODE,
ESP_ROM_SPIFLASH_FASTRD_MODE,
ESP_ROM_SPIFLASH_SLOWRD_MODE,
ESP_ROM_SPIFLASH_OPI_STR_MODE,
ESP_ROM_SPIFLASH_OPI_DTR_MODE,
ESP_ROM_SPIFLASH_OOUT_MODE,
ESP_ROM_SPIFLASH_OIO_STR_MODE,
ESP_ROM_SPIFLASH_OIO_DTR_MODE,
} esp_rom_spiflash_read_mode_t;
typedef enum
{
ESP_ROM_SPIFLASH_RESULT_OK,
ESP_ROM_SPIFLASH_RESULT_ERR,
ESP_ROM_SPIFLASH_RESULT_TIMEOUT
} esp_rom_spiflash_result_t;
typedef struct
{
uint32_t device_id;
uint32_t chip_size; /* chip size in bytes */
uint32_t block_size;
uint32_t sector_size;
uint32_t page_size;
uint32_t status_mask;
} esp32s3_spiflash_chip_t;
typedef struct
{
uint8_t data_length;
uint8_t read_cmd0;
uint8_t read_cmd1;
uint8_t write_cmd;
uint16_t data_mask;
uint16_t data;
} esp_rom_spiflash_common_cmd_t;
/* Global ROM spiflash data, as used by legacy SPI flash functions */
struct spiflash_legacy_data_s
{
esp32s3_spiflash_chip_t chip;
uint8_t dummy_len_plus[3];
uint8_t sig_matrix;
};
/* Structure holding SPI flash access critical sections management functions.
*
* Flash API uses two types of functions for flash access management:
@ -330,7 +233,7 @@ void esp_rom_spiflash_attach(uint32_t ishspi, bool legacy);
* Please do not call this function in SDK.
*
* Input Parameters:
* esp32s3_spiflash_chip_t *spi : The information for Flash, which is
* esp_rom_spiflash_chip_t *spi : The information for Flash, which is
* exported from ld file.
*
* uint32_t *status : The pointer to which to return the Flash status value.
@ -343,7 +246,7 @@ void esp_rom_spiflash_attach(uint32_t ishspi, bool legacy);
*****************************************************************************/
esp_rom_spiflash_result_t
esp_rom_spiflash_read_status(esp32s3_spiflash_chip_t *spi,
esp_rom_spiflash_read_status(esp_rom_spiflash_chip_t *spi,
uint32_t *status);
/*****************************************************************************
@ -355,7 +258,7 @@ esp_rom_spiflash_read_status(esp32s3_spiflash_chip_t *spi,
* Please do not call this function in SDK.
*
* Input Parameters:
* esp32s3_spiflash_chip_t *spi : The information for Flash, which is
* esp_rom_spiflash_chip_t *spi : The information for Flash, which is
* exported from ld file.
*
* uint32_t *status : The pointer to which to return the Flash status value.
@ -368,7 +271,7 @@ esp_rom_spiflash_read_status(esp32s3_spiflash_chip_t *spi,
*****************************************************************************/
esp_rom_spiflash_result_t
esp32s3_spiflash_read_statushigh(esp32s3_spiflash_chip_t *spi,
esp32s3_spiflash_read_statushigh(esp_rom_spiflash_chip_t *spi,
uint32_t *status);
/*****************************************************************************
@ -380,7 +283,7 @@ esp32s3_spiflash_read_statushigh(esp32s3_spiflash_chip_t *spi,
* Please do not call this function in SDK.
*
* Input Parameters:
* esp32s3_spiflash_chip_t *spi : The information for Flash, which is
* esp_rom_spiflash_chip_t *spi : The information for Flash, which is
* exported from ld file.
*
* uint32_t status_value : Value to .
@ -393,7 +296,7 @@ esp32s3_spiflash_read_statushigh(esp32s3_spiflash_chip_t *spi,
*****************************************************************************/
esp_rom_spiflash_result_t
esp32s3_spiflash_write_status(esp32s3_spiflash_chip_t *spi,
esp32s3_spiflash_write_status(esp_rom_spiflash_chip_t *spi,
uint32_t status_value);
/*****************************************************************************
@ -405,7 +308,7 @@ esp32s3_spiflash_write_status(esp32s3_spiflash_chip_t *spi,
* Please do not call this function in SDK.
*
* Input Parameters:
* esp32s3_spiflash_chip_t *spi : The information for Flash, which is
* esp_rom_spiflash_chip_t *spi : The information for Flash, which is
* exported from ld file.
*
* uint32_t*status : The pointer to which to return the Flash status value.
@ -803,7 +706,7 @@ esp_rom_spiflash_write_encrypted(uint32_t flash_addr,
*
*****************************************************************************/
esp_rom_spiflash_result_t esp_rom_spiflash_wait_idle(esp32s3_spiflash_chip_t
esp_rom_spiflash_result_t esp_rom_spiflash_wait_idle(esp_rom_spiflash_chip_t
*spi);
/*****************************************************************************
@ -851,7 +754,7 @@ void esp_rom_spiflash_select_qio_pins(uint8_t wp_gpio_num,
*
*****************************************************************************/
void spi_flash_guard_set(const struct spiflash_guard_funcs *funcs);
void spi_flash_guard_set(const spi_flash_guard_funcs_t *funcs);
/*****************************************************************************
* Name: spi_flash_write_encrypted
@ -1005,8 +908,6 @@ void spi_flash_enable_cache(uint32_t cpuid);
* Public Data
*****************************************************************************/
extern struct spiflash_legacy_data_s *rom_spiflash_legacy_data;
#ifdef __cplusplus
}
#endif

41
boards/xtensa/esp32s3/common/scripts/flat_memory.ld
View file

@ -48,6 +48,8 @@
#ifdef CONFIG_ESP32S3_APP_FORMAT_MCUBOOT
#define SRAM_IRAM_END 0x403ba000
#elif defined (CONFIG_ESPRESSIF_SIMPLE_BOOT)
#define SRAM_IRAM_END 0x403c0000
#else
#define SRAM_IRAM_END 0x403cc700
#endif
@ -77,6 +79,8 @@
# define FLASH_SIZE 0x2000000
#endif
#define RESERVE_RTC_MEM 24
MEMORY
{
#ifdef CONFIG_ESP32S3_APP_FORMAT_MCUBOOT
@ -92,6 +96,16 @@ MEMORY
metadata (RX) : org = CONFIG_ESP32S3_APP_MCUBOOT_HEADER_SIZE, len = 0x20
ROM (RX) : org = ORIGIN(metadata) + LENGTH(metadata),
len = FLASH_SIZE - ORIGIN(ROM)
#elif defined (CONFIG_ESPRESSIF_SIMPLE_BOOT)
/* The 0x20 offset is a convenience for the app binary image generation.
* Flash cache has 64KB pages. The .bin file which is flashed to the chip
* has a 0x18 byte file header, and each segment has a 0x08 byte segment
* header. Setting this offset makes it simple to meet the flash cache MMU's
* constraint that (paddr % 64KB == vaddr % 64KB).
*/
ROM (RX) : org = 0x20,
len = FLASH_SIZE - ORIGIN(ROM)
#endif
/* Below values assume the flash cache is on, and have the blocks this
@ -109,12 +123,7 @@ MEMORY
#ifdef CONFIG_ESP32S3_APP_FORMAT_MCUBOOT
irom0_0_seg (RX) : org = 0x42000000, len = FLASH_SIZE
#else
/* The 0x20 offset is a convenience for the app binary image generation.
* Flash cache has 64KB pages. The .bin file which is flashed to the chip
* has a 0x18 byte file header, and each segment has a 0x08 byte segment
* header. Setting this offset makes it simple to meet the flash cache MMU's
* constraint that (paddr % 64KB == vaddr % 64KB).
*/
/* (See ROM segment above for meaning of 0x20 offset.) */
irom0_0_seg (RX) : org = 0x42000020, len = FLASH_SIZE - 0x20
#endif
@ -144,23 +153,27 @@ MEMORY
drom0_0_seg (R) : org = 0x3c000000 + ORIGIN(ROM),
len = FLASH_SIZE - ORIGIN(ROM)
#else
/* The 0x20 offset is a convenience for the app binary image generation.
* Flash cache has 64KB pages. The .bin file which is flashed to the chip
* has a 0x18 byte file header, and each segment has a 0x08 byte segment
* header. Setting this offset makes it simple to meet the flash cache MMU's
* constraint that (paddr % 64KB == vaddr % 64KB).
*/
/* (See ROM segment above for meaning of 0x20 offset.) */
drom0_0_seg (R) : org = 0x3c000020, len = FLASH_SIZE - 0x20
#endif
/* RTC fast memory (executable). Persists over deep sleep. */
rtc_iram_seg(RWX) : org = 0x600fe000, len = 0x2000
rtc_iram_seg(RWX) : org = 0x600fe000, len = 0x2000 - RESERVE_RTC_MEM
/* RTC fast memory (same block as above), viewed from data bus */
rtc_data_seg(RW) : org = 0x600fe000, len = 0x2000
rtc_data_seg(RW) : org = 0x600fe000, len = 0x2000 - RESERVE_RTC_MEM
/* We reduced the size of rtc_iram_seg by RESERVE_RTC_MEM value.
It reserves the amount of RTC fast memory that we use for this memory segment.
This segment is intended for keeping:
- (lower addr) rtc timer data (s_rtc_timer_retain_mem, see esp_clk.c files).
- (higher addr) bootloader rtc data (s_bootloader_retain_mem, when a Kconfig option is on).
The aim of this is to keep data that will not be moved around and have a fixed address.
*/
rtc_reserved_seg(RW) : org = 0x600fe000 + 0x2000 - RESERVE_RTC_MEM, len = RESERVE_RTC_MEM
/* RTC slow memory (data accessible). Persists over deep sleep.
* Start of RTC slow memory is reserved for ULP co-processor code + data,

9
boards/xtensa/esp32s3/common/scripts/kernel-space.ld
View file

@ -118,6 +118,8 @@ SECTIONS
*libsched.a:irq_csection.*(.literal .text .literal.* .text.*)
*libsched.a:irq_dispatch.*(.literal .text .literal.* .text.*)
*libc.a:*lib_instrument.*(.text .text.* .literal .literal.*)
*(.wifirxiram .wifirxiram.*)
*(.wifi0iram .wifi0iram.*)
*(.wifiorslpiram .wifiorslpiram.*)
@ -168,6 +170,8 @@ SECTIONS
*libsched.a:irq_csection.*(.bss .bss.* COMMON)
*libsched.a:irq_dispatch.*(.bss .bss.* COMMON)
*libc.a:*lib_instrument.*(.bss .bss.* COMMON)
. = ALIGN(8);
_ebss = ABSOLUTE(.);
} >KDRAM
@ -214,6 +218,8 @@ SECTIONS
*libsched.a:irq_csection.*(.rodata .rodata.*)
*libsched.a:irq_dispatch.*(.rodata .rodata.*)
*libc.a:*lib_instrument.*(.rodata .rodata.*)
. = ALIGN(4);
_edata = ABSOLUTE(.);
@ -225,6 +231,8 @@ SECTIONS
.flash.text :
{
_stext = .;
_instruction_reserved_start = ABSOLUTE(.);
*(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
*(.irom0.text) /* catch stray ICACHE_RODATA_ATTR */
*(.fini.literal)
@ -239,6 +247,7 @@ SECTIONS
. += 16;
_instruction_reserved_end = ABSOLUTE(.);
_etext = .;
} >KIROM

3
boards/xtensa/esp32s3/common/scripts/legacy_sections.ld
View file

@ -237,6 +237,8 @@ SECTIONS
.flash.text :
{
_stext = .;
_instruction_reserved_start = ABSOLUTE(.);
*(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
*(.irom0.text) /* catch stray ICACHE_RODATA_ATTR */
*(.fini.literal)
@ -251,6 +253,7 @@ SECTIONS
. += 16;
_instruction_reserved_end = ABSOLUTE(.);
_etext = .;
} >default_code_seg

23
boards/xtensa/esp32s3/common/scripts/mcuboot_sections.ld
View file

@ -61,7 +61,7 @@ SECTIONS
_image_drom_lma = LOADADDR(.flash.rodata);
_image_drom_size = LOADADDR(.flash.rodata) + SIZEOF(.flash.rodata) - _image_drom_lma;
.flash.rodata :
.flash.rodata : ALIGN(4)
{
_rodata_reserved_start = .;
@ -69,8 +69,6 @@ SECTIONS
*(EXCLUDE_FILE (esp32s3_start.*) .rodata)
*(EXCLUDE_FILE (esp32s3_start.*) .rodata.*)
*(.rodata)
*(.rodata.*)
#ifdef CONFIG_ESP32S3_WIRELESS
*(.rodata_wlog_verbose.*)
*(.rodata_wlog_debug.*)
@ -128,7 +126,7 @@ SECTIONS
/* Send .iram0 code to iram */
.iram0.vectors :
.iram0.vectors : ALIGN(4)
{
_iram_start = ABSOLUTE(.);
@ -168,7 +166,7 @@ SECTIONS
*(.init)
} >iram0_0_seg AT>ROM
.iram0.text :
.iram0.text : ALIGN(4)
{
/* Code marked as running out of IRAM */
@ -185,6 +183,10 @@ SECTIONS
*libarch.a:xtensa_irqdispatch.*(.literal .text .literal.* .text.*)
*libarch.a:xtensa_modifyreg32.*(.literal .text .literal.* .text.*)
*libarch.a:xtensa_testset.*(.literal .text .literal.* .text.*)
*libarch.a:*cache_hal.*(.text .text.* .literal .literal.*)
*libarch.a:*uart_hal.*(.text .text.* .literal .literal.*)
*libarch.a:*mpu_hal.*(.text .text.* .literal .literal.*)
*libarch.a:*mmu_hal.*(.text .text.* .literal .literal.*)
#ifdef CONFIG_ESP32S3_BLE
*libc.a:sq_remlast.*(.literal .text .literal.* .text.*)
@ -299,7 +301,7 @@ SECTIONS
. = ALIGN(4);
} >dram0_0_seg
.dram0.data :
.dram0.data : ALIGN(4)
{
/* .data initialized on power-up in ROMed configurations. */
@ -320,6 +322,12 @@ SECTIONS
*libphy.a:(.rodata .rodata.*)
*libarch.a:xtensa_context.*(.rodata .rodata.*)
*libarch.a:esp32s3_spiflash.*(.rodata .rodata.*)
*libarch.a:*cache_hal.*(.rodata .rodata.*)
*libarch.a:*uart_hal.*(.rodata .rodata.*)
*libarch.a:*mpu_hal.*(.rodata .rodata.*)
*libarch.a:*mmu_hal.*(.rodata .rodata.*)
#if defined(CONFIG_STACK_CANARIES) && \
(defined(CONFIG_ESP32S3_SPIFLASH) || \
defined(CONFIG_ESP32S3_SPIRAM))
@ -393,6 +401,8 @@ SECTIONS
.flash.text : ALIGN(0x00010000)
{
_stext = .;
_instruction_reserved_start = ABSOLUTE(.);
*(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
*(.irom0.text) /* catch stray ICACHE_RODATA_ATTR */
*(.fini.literal)
@ -407,6 +417,7 @@ SECTIONS
. += 16;
_instruction_reserved_end = ABSOLUTE(.);
_etext = .;
} >irom0_0_seg AT>ROM

572
boards/xtensa/esp32s3/common/scripts/simple_boot_sections.ld Normal file
View file

@ -0,0 +1,572 @@
/****************************************************************************
* boards/xtensa/esp32s3/common/scripts/mcuboot_sections.ld
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#include <nuttx/config.h>
/* Default entry point: */
ENTRY(__start);
_diram_i_start = 0x40378000;
SECTIONS
{
/* Send .iram0 code to iram */
.iram0.vectors :
{
_iram_start = ABSOLUTE(.);
/* Vectors go to IRAM. */
_init_start = ABSOLUTE(.);
/* Vectors according to builds/RF-2015.2-win32/esp108_v1_2_s5_512int_2/config.html */
. = 0x0;
KEEP (*(.window_vectors.text));
. = 0x180;
KEEP (*(.xtensa_level2_vector.text));
. = 0x1c0;
KEEP (*(.xtensa_level3_vector.text));
. = 0x200;
KEEP (*(.xtensa_level4_vector.text));
. = 0x240;
KEEP (*(.xtensa_level5_vector.text));
. = 0x280;
KEEP (*(.debug_exception_vector.text));
. = 0x2c0;
KEEP (*(.nmi_vector.text));
. = 0x300;
KEEP (*(.kernel_exception_vector.text));
. = 0x340;
KEEP (*(.user_exception_vector.text));
. = 0x3c0;
KEEP (*(.double_exception_vector.text));
. = 0x400;
*(.*_vector.literal)
. = ALIGN(16);
*(.entry.text)
*(.init.literal)
*(.init)
_init_end = ABSOLUTE(.);
} >iram0_0_seg AT>ROM
.iram0.text :
{
/* Code marked as running out of IRAM */
*(.iram1 .iram1.*)
esp32s3_start.*(.literal .text .literal.* .text.*)
*libarch.a:esp32s3_cpuindex.*(.literal .text .literal.* .text.*)
*libarch.a:esp32s3_irq.*(.literal .text .literal.* .text.*)
*libarch.a:esp32s3_user.*(.literal .text .literal.* .text.*)
*libarch.a:esp32s3_spiflash.*(.literal .text .literal.* .text.*)
*libarch.a:xtensa_assert.*(.literal .text .literal.* .text.*)
*libarch.a:xtensa_cpuint.*(.literal .text .literal.* .text.*)
*libarch.a:xtensa_cpupause.*(.literal .text .literal.* .text.*)
*libarch.a:xtensa_irqdispatch.*(.literal .text .literal.* .text.*)
*libarch.a:xtensa_modifyreg32.*(.literal .text .literal.* .text.*)
*libarch.a:xtensa_testset.*(.literal .text .literal.* .text.*)
#ifdef CONFIG_ESP32S3_BLE
*libc.a:sq_remlast.*(.literal .text .literal.* .text.*)
#endif
*libdrivers.a:syslog_flush.*(.literal .text .literal.* .text.*)
*libsched.a:assert.*(.literal .text .literal.* .text.*)
*libsched.a:irq_csection.*(.literal .text .literal.* .text.*)
*libsched.a:irq_dispatch.*(.literal .text .literal.* .text.*)
*libsched.a:irq_spinlock.*(.literal .text .literal.* .text.*)
*libsched.a:sched_note.*(.literal .text .literal.* .text.*)
*libsched.a:sched_suspendscheduler.*(.literal .text .literal.* .text.*)
*libsched.a:sched_thistask.*(.literal .text .literal.* .text.*)
*libsched.a:spinlock.*(.literal .text .literal.* .text.*)
*libsched.a:*sched_get_stackinfo.*(.literal .text .literal.* .text.*)
#ifdef CONFIG_ESP32S3_SPEED_UP_ISR
*libarch.a:xtensa_switchcontext.*(.literal.up_switch_context .text.up_switch_context)
*libarch.a:esp32s3_timerisr.*(.literal.systimer_isr .text.systimer_isr)
*libarch.a:esp32s3_idle.*(.literal.up_idle .text.up_idle)
*libarch.a:esp32s3_dma.*(.literal.esp32s3_dma_load .text.esp32s3_dma_load \
.literal.esp32s3_dma_enable .text.esp32s3_dma_enable)
*libsched.a:sched_processtimer.*(.literal.nxsched_process_timer .text.nxsched_process_timer)
*libsched.a:clock_initialize.*(.literal.clock_timer .text.clock_timer)
*libsched.a:wd_start.*(.literal.wd_timer .text.wd_timer)
*libsched.a:sched_roundrobin.*(.literal.nxsched_process_roundrobin .text.nxsched_process_roundrobin)
*libsched.a:sched_reprioritizertr.*(.literal.nxsched_reprioritize_rtr .text.nxsched_reprioritize_rtr)
*libsched.a:sched_removereadytorun.*(.literal.nxsched_remove_readytorun .text.nxsched_remove_readytorun)
*libsched.a:sched_addreadytorun.*(.literal.nxsched_add_readytorun .text.nxsched_add_readytorun)
*libsched.a:sched_addprioritized.*(.literal.nxsched_add_prioritized .text.nxsched_add_prioritized)
*libsched.a:sched_mergepending.*(.literal.nxsched_merge_pending .text.nxsched_merge_pending)
*libsched.a:sched_resumescheduler.*(.literal.nxsched_resume_scheduler .text.nxsched_resume_scheduler)
*libc.a:sq_remfirst.*(.literal.sq_remfirst .text.sq_remfirst)
#endif
*libarch.a:esp32s3_spi_timing.*(.literal .text .literal.* .text.*)
#ifdef CONFIG_ESP32S3_SPIRAM_MODE_QUAD
*libarch.a:esp32s3_psram_quad.*(.literal .text .literal.* .text.*)
#endif
#ifdef CONFIG_ESP32S3_SPIRAM_MODE_OCT
*libarch.a:esp32s3_psram_octal.*(.literal .text .literal.* .text.*)
#endif
#if defined(CONFIG_STACK_CANARIES) && \
(defined(CONFIG_ESP32S3_SPIFLASH) || \
defined(CONFIG_ESP32S3_SPIRAM))
*libc.a:lib_stackchk.*(.literal .text .literal.* .text.*)
#endif
*libarch.a:*brownout_hal.*(.text .text.* .literal .literal.*)
*libarch.a:*cpu.*(.text .text.* .literal .literal.*)
*libarch.a:*gpio_hal.*(.text .text.* .literal .literal.*)
*libarch.a:*periph_ctrl.*(.text .text.* .literal .literal.*)
*libarch.a:*clk.*(.text .text.* .literal .literal.*)
*libarch.a:*efuse_hal.*(.literal.is_eco0 .text.is_eco0)
*libarch.a:*esp_clk.*(.text .text.* .literal .literal.*)
*libarch.a:*esp_clk_tree.*(.text .text.* .literal .literal.*)
*libarch.a:*esp_clk_tree_common.*(.text .text.* .literal .literal.*)
*libarch.a:*clk_tree_hal.*(.text .text.* .literal .literal.*)
*libarch.a:*rtc_init.*(.text .text.* .literal .literal.*)
*libarch.a:*rtc_clk.*(.text .text.* .literal .literal.*)
*libarch.a:*rtc_clk_init.*(.text .text.* .literal .literal.*)
*libarch.a:*rtc_sleep.*(.text .text.* .literal .literal.*)
*libarch.a:*rtc_time.*(.text .text.* .literal .literal.*)
*libarch.a:*regi2c_ctrl.*(.text .text.* .literal .literal.*)
*libarch.a:*uart_hal_iram.*(.text .text.* .literal .literal.*)
*libarch.a:*wdt_hal_iram.*(.text .text.* .literal .literal.*)
*libarch.a:*bootloader_banner_wrap.*(.text .text.* .literal .literal.*)
*libarch.a:*bootloader_init.*(.text .text.* .literal .literal.*)
*libarch.a:*bootloader_common.*(.text .text.* .literal .literal.*)
*libarch.a:*bootloader_common_loader.*(.text .text.* .literal .literal.*)
*libarch.a:*bootloader_console.*(.text .text.* .literal .literal.*)
*libarch.a:*bootloader_console_loader.*(.text .text.* .literal .literal.*)
*libarch.a:*bootloader_esp32s3.*(.text .text.* .literal .literal.*)
*libarch.a:*bootloader_flash.*(.text .text.* .literal .literal.*)
*libarch.a:*bootloader_flash_config_esp32s3.*(.text .text.* .literal .literal.*)
*libarch.a:*bootloader_clock_init.*(.text .text.* .literal .literal.*)
*libarch.a:*bootloader_clock_loader.*(.text .text.* .literal .literal.*)
*libarch.a:*bootloader_efuse.*(.text .text.* .literal .literal.*)
*libarch.a:*bootloader_panic.*(.text .text.* .literal .literal.*)
*libarch.a:*bootloader_mem.*(.text .text.* .literal .literal.*)
*libarch.a:*bootloader_random.*(.text .text.* .literal .literal.*)
*libarch.a:*bootloader_random*.*(.literal.bootloader_random_disable .text.bootloader_random_disable)
*libarch.a:*bootloader_random*.*(.literal.bootloader_random_enable .text.bootloader_random_enable)
*libarch.a:*bootloader_random_esp32s3.*(.text .text.* .literal .literal.*)
*libarch.a:*esp_image_format.*(.text .text.* .literal .literal.*)
*libarch.a:*bootloader_soc.*(.text .text.* .literal .literal.*)
*libarch.a:*bootloader_sha.*(.text .text.* .literal .literal.*)
*libarch.a:*flash_encrypt.*(.text .text.* .literal .literal.*)
*libarch.a:*cache_hal.*(.text .text.* .literal .literal.*)
*libarch.a:*uart_hal.*(.text .text.* .literal .literal.*)
*libarch.a:*mpu_hal.*(.text .text.* .literal .literal.*)
*libarch.a:*mmu_hal.*(.text .text.* .literal .literal.*)
*libarch.a:*efuse_hal.*(.text .text.* .literal .literal.*)
*libarch.a:*uart_periph.*(.text .text.* .literal .literal.*)
*libarch.a:*esp_rom_uart.*(.text .text.* .literal .literal.*)
*libarch.a:*esp_rom_sys.*(.text .text.* .literal .literal.*)
*libarch.a:*esp_rom_spiflash.*(.text .text.* .literal .literal.*)
*libarch.a:*esp_rom_cache_esp32s2_esp32s3.*(.text .text.* .literal .literal.*)
*libarch.a:*esp_rom_wdt.*(.text .text.* .literal .literal.*)
*libarch.a:*esp_efuse_fields.*(.text .text.* .literal .literal.*)
*libarch.a:*esp_efuse_api_key.*(.text .text.* .literal .literal.*)
*libarch.a:*log.*(.text .text.* .literal .literal.*)
*libarch.a:*log_noos.*(.text .text.* .literal .literal.*)
*libarch.a:*cpu_region_protect.*(.text .text.* .literal .literal.*)
*libarch.a:*mspi_timing_tuning.*(.text .text.* .literal .literal.*)
*libc.a:*lib_instrument.*(.text .text.* .literal .literal.*)
*(.wifirxiram .wifirxiram.*)
*(.wifi0iram .wifi0iram.*)
*(.wifiorslpiram .wifiorslpiram.*)
*(.wifislpiram .wifislpiram.*)
*(.wifislprxiram .wifislprxiram.*)
*(.phyiram .phyiram.*)
/* align + add 16B for CPU dummy speculative instr. fetch */
. = ALIGN(4) + 16;
_iram_text = ABSOLUTE(.);
} >iram0_0_seg AT > ROM
.dram0.dummy (NOLOAD) :
{
/* This section is required to skip .iram0.text area because iram0_0_seg
* and dram0_0_seg reflect the same address space on different buses.
*/
. = ORIGIN(dram0_0_seg) + MAX(_iram_end, _diram_i_start) - _diram_i_start;
} >dram0_0_seg
/* Shared RAM */
.dram0.bss (NOLOAD) :
{
/* .bss initialized on power-up */
. = ALIGN(8);
_bss_start = ABSOLUTE(.);
_sbss = ABSOLUTE(.);
*(.bss .bss.*)
*(COMMON)
*(.dynsbss)
*(.sbss)
*(.sbss.*)
*(.gnu.linkonce.sb.*)
*(.scommon)
*(.sbss2)
*(.sbss2.*)
*(.gnu.linkonce.sb2.*)
*(.dynbss)
*(.share.mem)
*(.gnu.linkonce.b.*)
. = ALIGN(8);
_ebss = ABSOLUTE(.);
_bss_end = ABSOLUTE(.);
} >dram0_0_seg
.noinit (NOLOAD) :
{
/* This section contains data that is not initialized during load,
* or during the application's initialization sequence.
*/
. = ALIGN(4);
*(.noinit .noinit.*)
. = ALIGN(4);
} >dram0_0_seg
.dram0.data :
{
/* .data initialized on power-up in ROMed configurations. */
. = ALIGN (16);
_data_start = ABSOLUTE(.);
_sdata = ABSOLUTE(.);
KEEP (*(.data))
KEEP (*(.data.*))
KEEP (*(.gnu.linkonce.d.*))
KEEP (*(.data1))
KEEP (*(.sdata))
KEEP (*(.sdata.*))
KEEP (*(.gnu.linkonce.s.*))
KEEP (*(.sdata2))
KEEP (*(.sdata2.*))
KEEP (*(.gnu.linkonce.s2.*))
KEEP (*(.jcr))
*(.dram1 .dram1.*)
esp32s3_start.*(.rodata .rodata.*)
*libphy.a:(.rodata .rodata.*)
*libarch.a:xtensa_context.*(.rodata .rodata.*)
#if defined(CONFIG_STACK_CANARIES) && \
(defined(CONFIG_ESP32S3_SPIFLASH) || \
defined(CONFIG_ESP32S3_SPIRAM))
*libc.a:lib_stackchk.*(.rodata .rodata.*)
#endif
*libsched.a:*sched_get_stackinfo.*(.rodata .rodata.*)
*libarch.a:esp32s3_spiflash.*(.rodata .rodata.*)
*libarch.a:*brownout.*(.rodata .rodata.*)
*libarch.a:*cpu.*(.rodata .rodata.*)
*libarch.a:*gpio_hal.*(.rodata .rodata.*)
*libarch.a:*periph_ctrl.*(.rodata .rodata.*)
*libarch.a:*clk.*(.rodata .rodata.*)
*libarch.a:*esp_clk.*(.rodata .rodata.*)
*libarch.a:*esp_clk_tree.*(.rodata .rodata.*)
*libarch.a:*esp_clk_tree_common.*(.rodata .rodata.*)
*libarch.a:*clk_tree_hal.*(.rodata .rodata.*)
*libarch.a:*rtc_init.*(.rodata .rodata.*)
*libarch.a:*rtc_clk.*(.rodata .rodata.*)
*libarch.a:*rtc_clk_init.*(.rodata .rodata.*)
*libarch.a:*rtc_sleep.*(.rodata .rodata.*)
*libarch.a:*rtc_time.*(.rodata .rodata.*)
*libarch.a:*regi2c_ctrl.*(.rodata .rodata.*)
*libarch.a:*uart_hal_iram.*(.rodata .rodata.*)
*libarch.a:*wdt_hal_iram.*(.rodata .rodata.*)
*libarch.a:*bootloader_banner_wrap.*(.rodata .rodata.*)
*libarch.a:*bootloader_init.*(.rodata .rodata.*)
*libarch.a:*bootloader_common.*(.rodata .rodata.*)
*libarch.a:*bootloader_common_loader.*(.rodata .rodata.*)
*libarch.a:*bootloader_console.*(.rodata .rodata.*)
*libarch.a:*bootloader_console_loader.*(.rodata .rodata.*)
*libarch.a:*bootloader_esp32s3.*(.rodata .rodata.*)
*libarch.a:*bootloader_flash.*(.rodata .rodata.*)
*libarch.a:*bootloader_flash_config_esp32s3.*(.rodata .rodata.*)
*libarch.a:*bootloader_clock_init.*(.rodata .rodata.*)
*libarch.a:*bootloader_clock_loader.*(.rodata .rodata.*)
*libarch.a:*bootloader_efuse.*(.rodata .rodata.*)
*libarch.a:*bootloader_panic.*(.rodata .rodata.*)
*libarch.a:*bootloader_mem.*(.rodata .rodata.*)
*libarch.a:*bootloader_random.*(.rodata .rodata.*)
*libarch.a:*bootloader_random_esp32s3.*(.rodata .rodata.*)
*libarch.a:*esp_image_format.*(.rodata .rodata.*)
*libarch.a:*bootloader_soc.*(.rodata .rodata.*)
*libarch.a:*bootloader_sha.*(.rodata .rodata.*)
*libarch.a:*flash_encrypt.*(.rodata .rodata.*)
*libarch.a:*cache_hal.*(.rodata .rodata.*)
*libarch.a:*uart_hal.*(.rodata .rodata.*)
*libarch.a:*mpu_hal.*(.rodata .rodata.*)
*libarch.a:*mmu_hal.*(.rodata .rodata.*)
*libarch.a:*uart_periph.*(.rodata .rodata.*)
*libarch.a:*esp_rom_uart.*(.rodata .rodata.*)
*libarch.a:*esp_rom_sys.*(.rodata .rodata.*)
*libarch.a:*esp_rom_spiflash.*(.rodata .rodata.*)
*libarch.a:*esp_rom_cache_esp32s2_esp32s3.*(.rodata .rodata.*)
*libarch.a:*esp_rom_wdt.*(.rodata .rodata.*)
*libarch.a:*esp_efuse_fields.*(.rodata .rodata.*)
*libarch.a:*esp_efuse_api_key.*(.rodata .rodata.*)
*libarch.a:*log.*(.rodata .rodata.*)
*libarch.a:*log_noos.*(.rodata .rodata.*)
*libarch.a:*cpu_region_protect.*(.rodata .rodata.*)
*libarch.a:*mspi_timing_tuning.*(.rodata .rodata.*)
#ifdef CONFIG_ESP32S3_SPIRAM_MODE_QUAD
*libarch.a:esp32s3_psram_quad.*(.rodata .rodata.*)
#endif
#ifdef CONFIG_ESP32S3_SPIRAM_MODE_OCT
*libarch.a:esp32s3_psram_octal.*(.rodata .rodata.*)
#endif
. = ALIGN(4);
_edata = ABSOLUTE(.);
_data_end = ABSOLUTE(.);
/* Heap starts at the end of .data */
_sheap = ABSOLUTE(.);
} >dram0_0_seg AT>ROM
_image_drom_vma = ADDR(.flash.rodata);
_image_drom_lma = LOADADDR(.flash.rodata);
_image_drom_size = LOADADDR(.flash.rodata) + SIZEOF(.flash.rodata) - _image_drom_lma;
/* The alignment of the ".flash.rodata" output section is forced to
* 0x00010000 (64KB) to ensure that it will be allocated at the beginning
* of the next available Flash block.
* This is required to meet the following constraint from the external
* flash MMU:
* VMA % 64KB == LMA % 64KB
* i.e. the lower 16 bits of both the virtual address (address seen by the
* CPU) and the load address (physical address of the external flash) must
* be equal.
*/
.flash.rodata_dummy (NOLOAD) :
{
. = ALIGN(0x10000);
} > ROM
.flash.rodata :
{
_rodata_reserved_start = ABSOLUTE(.);
_srodata = ABSOLUTE(.);
*(EXCLUDE_FILE (esp32s3_start.*) .rodata)
*(EXCLUDE_FILE (esp32s3_start.*) .rodata.*)
*(.rodata)
*(.rodata.*)
#ifdef CONFIG_ESP32S3_WIRELESS
*(.rodata_wlog_verbose.*)
*(.rodata_wlog_debug.*)
*(.rodata_wlog_info.*)
*(.rodata_wlog_warning.*)
*(.rodata_wlog_error.*)
#endif
*(.irom1.text) /* catch stray ICACHE_RODATA_ATTR */
*(.gnu.linkonce.r.*)
*(.rodata1)
__XT_EXCEPTION_TABLE_ = ABSOLUTE(.);
*(.xt_except_table)
*(.gcc_except_table)
*(.gcc_except_table.*)
*(.gnu.linkonce.e.*)
*(.gnu.version_r)
*(.eh_frame)
. = ALIGN(4);
/* C++ constructor and destructor tables, properly ordered: */
_sinit = ABSOLUTE(.);
KEEP (*crtbegin.o(.ctors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*(.ctors))
_einit = ABSOLUTE(.);
KEEP (*crtbegin.o(.dtors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*(.dtors))
/* C++ exception handlers table: */
__XT_EXCEPTION_DESCS_ = ABSOLUTE(.);
*(.xt_except_desc)
*(.gnu.linkonce.h.*)
__XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);
*(.xt_except_desc_end)
*(.dynamic)
*(.gnu.version_d)
_erodata = ABSOLUTE(.);
/* Literals are also RO data. */
_lit4_start = ABSOLUTE(.);
*(*.lit4)
*(.lit4.*)
*(.gnu.linkonce.lit4.*)
_lit4_end = ABSOLUTE(.);
. = ALIGN(4);
} >drom0_0_seg AT>ROM
.flash.rodata_noload (NOLOAD) :
{
/*
This is a symbol marking the flash.rodata end, this can be
used for mmu driver to maintain virtual address
We don't need to include the noload rodata in this section
*/
_rodata_reserved_end = ABSOLUTE(.);
. = ALIGN (4);
mapping[rodata_noload]
} >drom0_0_seg
_image_irom_vma = ADDR(.flash.text);
_image_irom_lma = LOADADDR(.flash.text);
_image_irom_size = LOADADDR(.flash.text) + SIZEOF(.flash.text) - _image_irom_lma;
.flash.text_dummy (NOLOAD) :
{
. += SIZEOF(.flash.rodata);
. = ALIGN(0x10000);
} >default_code_seg AT> ROM
.flash.text :
{
_stext = .;
_instruction_reserved_start = ABSOLUTE(.);
*(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
*(.irom0.text) /* catch stray ICACHE_RODATA_ATTR */
*(.fini.literal)
*(.fini)
*(.gnu.version)
/* CPU will try to prefetch up to 16 bytes of instructions.
* This means that any configuration (e.g. MMU, PMS) must allow
* safe access to up to 16 bytes after the last real instruction, add
* dummy bytes to ensure this
*/
. += 16;
_instruction_reserved_end = ABSOLUTE(.);
_etext = .;
} >irom0_0_seg AT>ROM
/* Marks the end of IRAM code segment */
.iram0.text_end (NOLOAD) :
{
/* ESP32-S3 memprot requires 16B padding for possible CPU prefetch and
* 256B alignment for PMS split lines.
*/
. += 16;
. = ALIGN(256);
_iram_end = ABSOLUTE(.);
} >iram0_0_seg
.iram0.data :
{
. = ALIGN(4);
*(.iram.data)
*(.iram.data.*)
} >iram0_0_seg
.iram0.bss (NOLOAD) :
{
. = ALIGN(4);
*(.iram.bss)
*(.iram.bss.*)
. = ALIGN(4);
_iram_end = ABSOLUTE(.);
} >iram0_0_seg
.rtc.text :
{
. = ALIGN(4);
*(.rtc.literal .rtc.text)
} >rtc_iram_seg AT>ROM
/* RTC BSS section. */
.rtc.bss (NOLOAD) :
{
*(.rtc.bss)
} >rtc_slow_seg
.rtc.data :
{
. = ALIGN(4);
*(.rtc.data)
*(.rtc.data.*)
*(.rtc.rodata)
*(.rtc.rodata.*)
/* Whatever is left from the RTC memory is used as a special heap. */
. = ALIGN (4);
_srtcheap = ABSOLUTE(.);
} >rtc_slow_seg
/*
* This section holds RTC data that should have fixed addresses.
* The data are not initialized at power-up and are retained during deep sleep.
*/
.rtc_reserved (NOLOAD):
{
. = ALIGN(4);
_rtc_reserved_start = ABSOLUTE(.);
/* New data can only be added here to ensure existing data are not moved.
Because data have adhered to the end of the segment and code is relied on it.
>> put new data here << */
*(.rtc_timer_data_in_rtc_mem .rtc_timer_data_in_rtc_mem.*)
KEEP(*(.bootloader_data_rtc_mem .bootloader_data_rtc_mem.*))
_rtc_reserved_end = ABSOLUTE(.);
} > rtc_reserved_seg
}

7
boards/xtensa/esp32s3/common/src/esp32s3_lan9250.c
View file

@ -35,14 +35,13 @@
#include <arch/board/board.h>
#include "xtensa.h"
#include "esp32s3_efuse.h"
#include "esp32s3_gpio.h"
#ifdef CONFIG_LAN9250_SPI
#include "esp32s3_spi.h"
#else
#include "esp32s3_qspi.h"
#endif
#include "hardware/esp32s3_efuse.h"
#include "hardware/esp32s3_gpio_sigmap.h"
/****************************************************************************
* Pre-processor Definitions
@ -175,8 +174,8 @@ static void lan9250_getmac(const struct lan9250_lower_s *lower, uint8_t *mac)
uint32_t regval[2];
uint8_t *data = (uint8_t *)regval;
regval[0] = getreg32(EFUSE_RD_MAC_SPI_SYS_0_REG);
regval[1] = getreg32(EFUSE_RD_MAC_SPI_SYS_1_REG);
regval[0] = esp32s3_efuse_read_reg(EFUSE_BLK1, 0);
regval[1] = esp32s3_efuse_read_reg(EFUSE_BLK1, 1);
for (int i = 0; i < 6; i++)
{

2
boards/xtensa/esp32s3/esp32s3-box/scripts/Make.defs
View file

@ -38,6 +38,8 @@ else
ARCHSCRIPT += $(call FINDSCRIPT,flat_memory.ld)
ifeq ($(CONFIG_ESP32S3_APP_FORMAT_MCUBOOT),y)
ARCHSCRIPT += $(call FINDSCRIPT,mcuboot_sections.ld)
else ifeq ($(CONFIG_ESPRESSIF_SIMPLE_BOOT),y)
ARCHSCRIPT += $(call FINDSCRIPT,simple_boot_sections.ld)
else
ARCHSCRIPT += $(call FINDSCRIPT,legacy_sections.ld)
endif

1
boards/xtensa/esp32s3/esp32s3-devkit/configs/eth_lan9250/defconfig
View file

@ -25,6 +25,7 @@ CONFIG_ARCH_XTENSA=y
CONFIG_BOARD_LOOPSPERMSEC=16717
CONFIG_BUILTIN=y
CONFIG_DEFAULT_TASK_STACKSIZE=4096
CONFIG_ESP32S3_EFUSE=y
CONFIG_ESP32S3_GPIO_IRQ=y
CONFIG_ESP32S3_SPI2=y
CONFIG_ESP32S3_SPI_SWCS=y

2
boards/xtensa/esp32s3/esp32s3-devkit/scripts/Make.defs
View file

@ -38,6 +38,8 @@ else
ARCHSCRIPT += $(call FINDSCRIPT,flat_memory.ld)
ifeq ($(CONFIG_ESP32S3_APP_FORMAT_MCUBOOT),y)
ARCHSCRIPT += $(call FINDSCRIPT,mcuboot_sections.ld)
else ifeq ($(CONFIG_ESPRESSIF_SIMPLE_BOOT),y)
ARCHSCRIPT += $(call FINDSCRIPT,simple_boot_sections.ld)
else
ARCHSCRIPT += $(call FINDSCRIPT,legacy_sections.ld)
endif

1
boards/xtensa/esp32s3/esp32s3-devkit/src/esp32s3_ledc.c
View file

@ -33,7 +33,6 @@
#include <arch/board/board.h>
#include "chip.h"
#include "esp32s3_ledc.h"
/****************************************************************************

2
boards/xtensa/esp32s3/esp32s3-devkit/src/esp32s3_twai.c
View file

@ -30,8 +30,6 @@
#include <nuttx/can/can.h>
#include <arch/board/board.h>
#include "chip.h"
#include "esp32s3_twai.h"
#include "esp32s3-devkit.h"

8
boards/xtensa/esp32s3/esp32s3-eye/scripts/Make.defs
View file

@ -36,7 +36,13 @@ ifeq ($(CONFIG_BUILD_PROTECTED),y)
ARCHSCRIPT += $(call FINDSCRIPT,kernel-space.ld)
else
ARCHSCRIPT += $(call FINDSCRIPT,flat_memory.ld)
ARCHSCRIPT += $(call FINDSCRIPT,legacy_sections.ld)
ifeq ($(CONFIG_ESP32S3_APP_FORMAT_MCUBOOT),y)
ARCHSCRIPT += $(call FINDSCRIPT,mcuboot_sections.ld)
else ifeq ($(CONFIG_ESPRESSIF_SIMPLE_BOOT),y)
ARCHSCRIPT += $(call FINDSCRIPT,simple_boot_sections.ld)
else
ARCHSCRIPT += $(call FINDSCRIPT,legacy_sections.ld)
endif
endif
ifneq ($(CONFIG_DEBUG_NOOPT),y)

2
boards/xtensa/esp32s3/esp32s3-lcd-ev/scripts/Make.defs
View file

@ -38,6 +38,8 @@ else
ARCHSCRIPT += $(call FINDSCRIPT,flat_memory.ld)
ifeq ($(CONFIG_ESP32S3_APP_FORMAT_MCUBOOT),y)
ARCHSCRIPT += $(call FINDSCRIPT,mcuboot_sections.ld)
else ifeq ($(CONFIG_ESPRESSIF_SIMPLE_BOOT),y)
ARCHSCRIPT += $(call FINDSCRIPT,simple_boot_sections.ld)
else
ARCHSCRIPT += $(call FINDSCRIPT,legacy_sections.ld)
endif

8
boards/xtensa/esp32s3/esp32s3-meadow/scripts/Make.defs
View file

@ -36,7 +36,13 @@ ifeq ($(CONFIG_BUILD_PROTECTED),y)
ARCHSCRIPT += $(call FINDSCRIPT,kernel-space.ld)
else
ARCHSCRIPT += $(call FINDSCRIPT,flat_memory.ld)
ARCHSCRIPT += $(call FINDSCRIPT,legacy_sections.ld)
ifeq ($(CONFIG_ESP32S3_APP_FORMAT_MCUBOOT),y)
ARCHSCRIPT += $(call FINDSCRIPT,mcuboot_sections.ld)
else ifeq ($(CONFIG_ESPRESSIF_SIMPLE_BOOT),y)
ARCHSCRIPT += $(call FINDSCRIPT,simple_boot_sections.ld)
else
ARCHSCRIPT += $(call FINDSCRIPT,legacy_sections.ld)
endif
endif
ifneq ($(CONFIG_DEBUG_NOOPT),y)

26
tools/esp32s3/Config.mk
View file

@ -98,6 +98,13 @@ else ifeq ($(CONFIG_ESP32S3_APP_FORMAT_MCUBOOT),y)
IMGTOOL_SIGN_ARGS := --pad $(VERIFIED) $(IMGTOOL_ALIGN_ARGS) -v 0 -s auto \
-H $(CONFIG_ESP32S3_APP_MCUBOOT_HEADER_SIZE) --pad-header \
-S $(CONFIG_ESP32S3_OTA_SLOT_SIZE)
else
# CONFIG_ESPRESSIF_SIMPLE_BOOT
APP_OFFSET := 0x0000
APP_IMAGE := nuttx.bin
FLASH_APP := $(APP_OFFSET) $(APP_IMAGE)
ESPTOOL_BINDIR := .
endif
ESPTOOL_BINS += $(FLASH_APP)
@ -157,6 +164,25 @@ define MKIMAGE
$(Q) echo nuttx.bin >> nuttx.manifest
$(Q) echo "Generated: nuttx.bin (MCUboot compatible)"
endef
else
define MKIMAGE
$(Q) echo "MKIMAGE: ESP32-S3 binary"
$(Q) if ! esptool.py version 1>/dev/null 2>&1; then \
echo ""; \
echo "esptool.py not found. Please run: \"pip install esptool\""; \
echo ""; \
echo "Run make again to create the nuttx.bin image."; \
exit 1; \
fi
$(Q) if [ -z $(FLASH_SIZE) ]; then \
echo "Missing Flash memory size configuration."; \
exit 1; \
fi
$(eval ELF2IMAGE_OPTS := $(if $(CONFIG_ESPRESSIF_SIMPLE_BOOT),--ram-only-header) -fs $(FLASH_SIZE) -fm $(FLASH_MODE) -ff $(FLASH_FREQ))
esptool.py -c esp32s3 elf2image $(ELF2IMAGE_OPTS) -o nuttx.bin nuttx
$(Q) echo nuttx.bin >> nuttx.manifest
$(Q) echo "Generated: nuttx.bin"
endef
endif
# PREBUILD -- Perform pre build operations