forked from nuttx/nuttx-update
drivers/pci: add MSI/MSI-X support
Add support for MSI and MSI-X in PCI framework Signed-off-by: p-szafonimateusz <p-szafonimateusz@xiaomi.com>
This commit is contained in:
p-szafonimateusz
Xiang Xiao
parent
e4ad92cb03
commit
db6d0bd356
4 changed files with 520 additions and 1 deletions
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@ -12,6 +12,13 @@ menuconfig PCI
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if PCI
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config PCI_MSIX
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bool "PCI MSI-X support"
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default n
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---help---
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Enables support for PCI MSI-X. When enabled, MSI-X takse priority
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over MSI when a device supports it.
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config PCI_ASSIGN_ALL_BUSES
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bool "Assign resource to all buses"
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default !ARCH_X86 && !ARCH_X86_64
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@ -450,7 +450,9 @@ static uint8_t pci_bus_find_start_cap(FAR struct pci_bus_s *bus,
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return 0;
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}
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switch (hdr_type)
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/* Ignore MF bit */
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switch (hdr_type & 0x7f)
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{
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case PCI_HEADER_TYPE_NORMAL:
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case PCI_HEADER_TYPE_BRIDGE:
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@ -1056,6 +1058,244 @@ static void pci_scan_bus(FAR struct pci_bus_s *bus)
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}
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}
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/****************************************************************************
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* Name: pci_get_msi_base
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*
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* Description:
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* Get MSI and MSI-X base
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*
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* Input Parameters:
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* dev - device
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* msi - returned MSI base
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* msix - returned MSI-X base
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*
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* Return value:
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* None
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*
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****************************************************************************/
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static void pci_get_msi_base(FAR struct pci_device_s *dev, FAR uint8_t *msi,
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FAR uint8_t *msix)
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{
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if (msi != NULL)
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{
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*msi = pci_find_capability(dev, PCI_CAP_ID_MSI);
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}
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if (msix != NULL)
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{
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*msix = pci_find_capability(dev, PCI_CAP_ID_MSIX);
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}
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}
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/****************************************************************************
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* Name: pci_enable_msi
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*
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* Description:
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* Configure and enable MSI.
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*
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* Input Parameters:
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* dev - device
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* irq - allocated vectors
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* num - number of vectors
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* msi - MSI base address
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*
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* Return value:
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* OK on success or a negative error code on failure
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*
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****************************************************************************/
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static int pci_enable_msi(FAR struct pci_device_s *dev, FAR int *irq,
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int num, uint8_t msi)
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{
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uint32_t mdr = 0;
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uint16_t flags = 0;
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uintptr_t mar = 0;
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uint16_t mme = 0;
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uint32_t mmc = 0;
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int ret = OK;
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/* Suppoted messages */
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for (mme = 0; (1 << mme) < num; mme++);
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/* Get Message Control Register */
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pci_read_config_word(dev, msi + PCI_MSI_FLAGS, &flags);
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mmc = (flags & PCI_MSI_FLAGS_QMASK) >> PCI_MSI_FLAGS_QMASK_SHIFT;
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if (mme > mmc)
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{
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mme = mmc;
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num = 1 << mme;
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pciinfo("Limit MME to %x, num to %d\n", mmc, num);
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}
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/* Configure MSI (arch-specific) */
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ret = dev->bus->ctrl->ops->connect_irq(dev->bus, irq, num, &mar, &mdr);
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if (ret < 0)
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{
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return ret;
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}
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/* Write Message Address Regsiter */
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pci_write_config_dword(dev, msi + PCI_MSI_ADDRESS_LO, mar);
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/* Write Message Data Register */
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if ((flags & PCI_MSI_FLAGS_64BIT) != 0)
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{
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pci_write_config_dword(dev, msi + PCI_MSI_ADDRESS_HI, (mar >> 32));
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pci_write_config_dword(dev, msi + PCI_MSI_DATA_64, mdr);
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}
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else
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{
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pci_write_config_word(dev, msi + PCI_MSI_DATA_32, mdr);
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}
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flags |= mme << PCI_MSI_FLAGS_QSIZE_SHIFT;
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/* Enable MSI */
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flags |= PCI_MSI_FLAGS_ENABLE;
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/* Write Message Control Register */
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pci_write_config_word(dev, msi + PCI_MSI_FLAGS, flags);
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return OK;
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}
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#ifdef CONFIG_PCI_MSIX
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/****************************************************************************
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* Name: pci_disable_msi
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*
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* Description:
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* Disable MSI.
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*
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* Input Parameters:
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* dev - device
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* msi - MSI base address
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*
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* Return value:
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* None
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*
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****************************************************************************/
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static void pci_disable_msi(FAR struct pci_device_s *dev, uint8_t msi)
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{
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uint16_t flags = 0;
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pci_read_config_word(dev, msi + PCI_MSI_FLAGS, &flags);
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flags &= ~PCI_MSI_FLAGS_ENABLE;
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pci_write_config_word(dev, msi + PCI_MSI_FLAGS, flags);
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}
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/****************************************************************************
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* Name: pci_enable_msix
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*
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* Description:
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* Configure and enable MSI-X.
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*
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* Input Parameters:
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* dev - device
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* irq - allocated vectors
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* num - number of vectors
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* msix - MSI-X base address
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*
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* Return value:
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* OK on success or a negative error code on failure
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*
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****************************************************************************/
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static int pci_enable_msix(FAR struct pci_device_s *dev, FAR int *irq,
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int num, uint8_t msix)
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{
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uint32_t mdr = 0;
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uint16_t flags = 0;
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uintptr_t mar = 0;
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uintptr_t tbladdr = 0;
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uintptr_t tblend = 0;
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uint32_t tbloffset = 0;
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uint32_t tblbar = 0;
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uint32_t tbl = 0;
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uint16_t tblsize = 0;
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int i = 0;
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int ret = OK;
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/* Get Flags */
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pci_read_config_word(dev, msix + PCI_MSIX_FLAGS, &flags);
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/* Table Size is N - 1 encoded */
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tblsize = (flags & PCI_MSIX_FLAGS_QSIZE) + 1;
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/* Get MSI-X table */
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pci_read_config_dword(dev, msix + PCI_MSIX_TABLE, &tbl);
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/* Extract table address */
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tblbar = tbl & PCI_MSIX_TABLE_BIR;
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tbladdr = pci_resource_start(dev, tblbar);
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tbloffset = (tbl & PCI_MSIX_TABLE_OFFSET) >> PCI_MSIX_TABLE_OFFSET_SHIFT;
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tbladdr += tbloffset;
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/* Map MSI-X table */
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tblend = tbladdr + tblsize * PCI_MSIX_ENTRY_SIZE;
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tbladdr = dev->bus->ctrl->ops->map(dev->bus, tbladdr, tblend);
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/* Limit tblsize */
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if (num > tblsize)
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{
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pciinfo("Limit tblszie to %xu\n", tblsize);
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num = tblsize;
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}
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for (i = 0; i < num; i++)
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{
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/* Connect MSI-X (arch-specific) */
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ret = dev->bus->ctrl->ops->connect_irq(dev->bus, &irq[i], 1,
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&mar, &mdr);
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if (ret < 0)
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{
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return ret;
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}
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/* Write Message Address Register */
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pci_write_mmio_dword(dev, tbladdr + PCI_MSIX_ENTRY_LOWER_ADDR, mar);
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pci_write_mmio_dword(dev, tbladdr + PCI_MSIX_ENTRY_UPPER_ADDR,
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(mar >> 32));
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/* Write Message Data Register */
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pci_write_mmio_dword(dev, tbladdr + PCI_MSIX_ENTRY_DATA, mdr);
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/* Write Vector Control register */
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pci_write_mmio_dword(dev, tbladdr + PCI_MSIX_ENTRY_VECTOR_CTRL, 0);
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/* Next vector */
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tbladdr += PCI_MSIX_ENTRY_SIZE;
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}
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/* Enable MSI-X */
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flags |= PCI_MSIX_FLAGS_ENABLE;
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pci_write_config_word(dev, msix + PCI_MSIX_FLAGS, flags);
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return OK;
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}
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#endif /* CONFIG_PCI_MSIX */
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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@ -1408,6 +1648,154 @@ uint8_t pci_find_next_capability(FAR struct pci_device_s *dev, uint8_t pos,
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pos + PCI_CAP_LIST_NEXT, cap);
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}
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/****************************************************************************
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* Name: pci_stat_line
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*
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* Description:
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* Determine if the interrupt line is active for a given device
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*
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* Input Parameters:
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* dev - device
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*
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* Return value:
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* True if interrupt is active
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*
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****************************************************************************/
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bool pci_stat_line(FAR struct pci_device_s *dev)
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{
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uint16_t tmp1;
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uint16_t tmp2;
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/* Interrupts enabled if Interrupt Disable is not set and Interrupt Status
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* is set.
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*/
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pci_read_config_word(dev, PCI_COMMAND, &tmp1);
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pci_read_config_word(dev, PCI_STATUS, &tmp2);
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return (!(tmp1 & PCI_COMMAND_INTX_DISABLE) &&
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(tmp2 & PCI_STATUS_INTERRUPT));
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}
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/****************************************************************************
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* Name: pci_get_irq
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*
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* Description:
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* Get interrupt number associated with a device PCI interrupt line
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*
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* Input Parameters:
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* dev - PCI device
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*
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* Return value:
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* Return interrupt number associated with a given INTx.
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*
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****************************************************************************/
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int pci_get_irq(FAR struct pci_device_s *dev)
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{
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uint8_t line = 0;
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pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &line);
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return dev->bus->ctrl->ops->get_irq(dev->bus, line);
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}
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/****************************************************************************
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* Name: pci_alloc_irq
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*
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* Description:
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* Allocate MSI or MSI-X vectors
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*
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* Input Parameters:
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* dev - PCI device
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* irq - allocated vectors
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* num - number of vectors
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*
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* Return value:
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* Return the number of allocated vectors on succes or negative errno
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* on failure.
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*
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****************************************************************************/
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int pci_alloc_irq(FAR struct pci_device_s *dev, FAR int *irq, int num)
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{
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return dev->bus->ctrl->ops->alloc_irq(dev->bus, irq, num);
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}
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/****************************************************************************
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* Name: pci_release_irq
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*
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* Description:
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* Release MSI or MSI-X vectors
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*
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* Input Parameters:
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* dev - PCI device
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* irq - allocated vectors
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* num - number of vectors
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*
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* Return value:
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* Failed if return a negative value, otherwise success
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*
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****************************************************************************/
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void pci_release_irq(FAR struct pci_device_s *dev, FAR int *irq, int num)
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{
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dev->bus->ctrl->ops->release_irq(dev->bus, irq, num);
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}
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/****************************************************************************
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* Name: pci_connect_irq
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*
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* Description:
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* Connect MSI or MSI-X if available.
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*
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* Input Parameters:
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* dev - PCI device
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* irq - allocated vectors
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* num - number of vectors
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*
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* Return value:
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* Return -ENOSETUP if MSI/MSI-X not available. Return OK on success.
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*
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****************************************************************************/
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int pci_connect_irq(FAR struct pci_device_s *dev, FAR int *irq, int num)
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{
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uint8_t msi = 0;
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uint8_t msix = 0;
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/* Get MSI base */
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pci_get_msi_base(dev, &msi, &msix);
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if (msi == 0 && msix == 0)
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{
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/* MSI and MSI-X not supported */
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return -ENOTSUP;
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}
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/* Configure MSI or MSI-X */
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#ifdef CONFIG_PCI_MSIX
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if (msix != 0)
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{
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/* Disalbe MSI */
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pci_disable_msi(dev, msi);
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/* Enable MSI-X */
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return pci_enable_msix(dev, irq, num, msix);
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}
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else
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#endif
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{
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/* Enable MSI */
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return pci_enable_msi(dev, irq, num, msi);
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}
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}
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/****************************************************************************
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* Name: pci_register_driver
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*
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@ -170,6 +170,24 @@
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#define pci_write_io_dword(dev, addr, val) \
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pci_bus_write_io_dword((dev)->bus, addr, val)
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#define pci_write_mmio_byte(dev, addr, val) \
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(*((FAR volatile uint8_t *)(addr))) = val
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#define pci_write_mmio_word(dev, addr, val) \
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(*((FAR volatile uint16_t *)(addr))) = val
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#define pci_write_mmio_dword(dev, addr, val) \
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(*((FAR volatile uint32_t *)(addr))) = val
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#define pci_read_mmio_byte(dev, addr, val) \
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(*val) = *((FAR volatile uint8_t *)(addr))
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#define pci_read_mmio_word(dev, addr, val) \
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(*val) = *((FAR volatile uint16_t *)(addr))
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#define pci_read_mmio_dword(dev, addr, val) \
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(*val) = *((FAR volatile uint32_t *)(addr))
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/****************************************************************************
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* Public Types
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****************************************************************************/
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@ -254,6 +272,21 @@ struct pci_ops_s
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int size, FAR uint32_t *val);
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CODE int (*write_io)(FAR struct pci_bus_s *bus, uintptr_t addr,
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int size, uint32_t val);
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/* Get interrupt number associated with a given INTx line */
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CODE int (*get_irq)(FAR struct pci_bus_s *bus, uint8_t line);
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/* Allocate interrupt for MSI/MSI-X */
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CODE int (*alloc_irq)(FAR struct pci_bus_s *bus, FAR int *irq, int num);
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CODE void (*release_irq)(FAR struct pci_bus_s *bus, FAR int *irq, int num);
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/* Connect interrupt for MSI/MSI-X */
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CODE int (*connect_irq)(FAR struct pci_bus_s *bus, FAR int *irq,
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int num, FAR uintptr_t *mar, FAR uint32_t *mdr);
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};
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/* Each pci channel is a top-level PCI bus seem by CPU. A machine with
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@ -522,6 +555,93 @@ uint8_t pci_find_capability(FAR struct pci_device_s *dev, int cap);
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uint8_t pci_find_next_capability(FAR struct pci_device_s *dev, uint8_t pos,
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int cap);
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/****************************************************************************
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* Name: pci_stat_line
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*
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* Description:
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* Determine if the interrupt line is active for a given device
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*
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* Input Parameters:
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* dev - device
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*
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* Return value:
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* True if interrupt is active
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*
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****************************************************************************/
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bool pci_stat_line(FAR struct pci_device_s *dev);
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/****************************************************************************
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* Name: pci_get_irq
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*
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* Description:
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* Get interrupt number associated with a device PCI interrupt line
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*
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* Input Parameters:
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* dev - PCI device
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*
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* Return value:
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* Return interrupt number associated with a given INTx.
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*
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****************************************************************************/
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int pci_get_irq(FAR struct pci_device_s *dev);
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/****************************************************************************
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* Name: pci_alloc_irq
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*
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* Description:
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* Allocate MSI or MSI-X vectors
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*
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* Input Parameters:
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* dev - PCI device
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* irq - allocated vectors
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* num - number of vectors
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*
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* Return value:
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* Return the number of allocated vectors on succes or negative errno
|
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* on failure.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
int pci_alloc_irq(FAR struct pci_device_s *dev, FAR int *irq, int num);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: pci_release_irq
|
||||
*
|
||||
* Description:
|
||||
* Release MSI or MSI-X vectors
|
||||
*
|
||||
* Input Parameters:
|
||||
* dev - PCI device
|
||||
* irq - allocated vectors
|
||||
* num - number of vectors
|
||||
*
|
||||
* Return value:
|
||||
* None
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void pci_release_irq(FAR struct pci_device_s *dev, FAR int *irq, int num);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: pci_connect_irq
|
||||
*
|
||||
* Description:
|
||||
* Connect MSI or MSI-X if available.
|
||||
*
|
||||
* Input Parameters:
|
||||
* dev - PCI device
|
||||
* irq - allocated vectors
|
||||
* num - number of vectors
|
||||
*
|
||||
* Return value:
|
||||
* Return -ENOSETUP if MSI/MSI-X not available. Return OK on success.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
int pci_connect_irq(FAR struct pci_device_s *dev, FAR int *irq, int num);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: pci_register_driver
|
||||
*
|
||||
|
|
|
|||
|
|
@ -313,7 +313,9 @@
|
|||
#define PCI_MSI_FLAGS 2 /* Message Control */
|
||||
#define PCI_MSI_FLAGS_ENABLE 0x0001 /* MSI feature enabled */
|
||||
#define PCI_MSI_FLAGS_QMASK 0x000e /* Maximum queue size available */
|
||||
#define PCI_MSI_FLAGS_QMASK_SHIFT 0x0001
|
||||
#define PCI_MSI_FLAGS_QSIZE 0x0070 /* Message queue size configured */
|
||||
#define PCI_MSI_FLAGS_QSIZE_SHIFT 0x0004
|
||||
#define PCI_MSI_FLAGS_64BIT 0x0080 /* 64-bit addresses allowed */
|
||||
#define PCI_MSI_FLAGS_MASKBIT 0x0100 /* Per-vector masking capable */
|
||||
|
||||
|
|
@ -323,6 +325,7 @@
|
|||
#define PCI_MSI_ADDRESS_LO 4 /* Lower 32 bits */
|
||||
#define PCI_MSI_ADDRESS_HI 8 /* Upper 32 bits (if PCI_MSI_FLAGS_64BIT set) */
|
||||
#define PCI_MSI_DATA_32 8 /* 16 bits of data for 32-bit devices */
|
||||
#define PCI_MSI_DATA_CPUID_SHIFT 12 /* Destination CPU ID */
|
||||
#define PCI_MSI_MASK_32 12 /* Mask bits register for 32-bit devices */
|
||||
#define PCI_MSI_PENDING_32 16 /* Pending intrs for 32-bit devices */
|
||||
#define PCI_MSI_DATA_64 12 /* 16 bits of data for 64-bit devices */
|
||||
|
|
@ -338,6 +341,7 @@
|
|||
#define PCI_MSIX_TABLE 4 /* Table offset */
|
||||
#define PCI_MSIX_TABLE_BIR 0x00000007 /* BAR index */
|
||||
#define PCI_MSIX_TABLE_OFFSET 0xfffffff8 /* Offset into specified BAR */
|
||||
#define PCI_MSIX_TABLE_OFFSET_SHIFT 3
|
||||
#define PCI_MSIX_PBA 8 /* Pending Bit Array offset */
|
||||
#define PCI_MSIX_PBA_BIR 0x00000007 /* BAR index */
|
||||
#define PCI_MSIX_PBA_OFFSET 0xfffffff8 /* Offset into specified BAR */
|
||||
|
|
|
|||
Loading…
Reference in a new issue