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Initial support for NUCLEO-U5A5ZJ-Q board

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Fix for ci error

Typo changes

Fixed typo in boards/arm/stm32u5/nucleo-u5a5zj-q/src/stm32_bringup.c

Typo changes

Typo fixes

Typo fixes

Typo changes

Typo changes

Typo changes
This commit is contained in:
kcheshmedzhiev 2023-07-18 19:27:19 +03:00 committed by Xiang Xiao
parent 0c5145b7d1
commit ea87d008a0
43 changed files with 5058 additions and 158 deletions
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1
arch/arm/Kconfig
View file

@ -523,6 +523,7 @@ config ARCH_CHIP_STM32U5
select ARM_HAVE_DSP
select ARCH_HAVE_FETCHADD
select ARCH_HAVE_HEAPCHECK
select ARCH_HAVE_HEAP2
select ARCH_HAVE_PROGMEM
select ARCH_HAVE_SPI_BITORDER
select ARCH_HAVE_TICKLESS

22
arch/arm/include/stm32u5/chip.h
View file

@ -31,15 +31,23 @@
* Pre-processor Prototypes
****************************************************************************/
#if defined(CONFIG_STM32U5_STM32U585XX)
# define STM32_SRAM1_SIZE (192*1024) /* 192Kb SRAM1 on AHB bus Matrix */
# define STM32_SRAM2_SIZE (64*1024) /* 64kB SRAM2 on AHB bus Matrix */
# define STM32_SRAM3_SIZE (512*1024) /* 512kB SRAM3 on AHB bus Matrix */
#if defined(CONFIG_STM32U5_STM32U535XX) || defined(CONFIG_STM32U5_STM32U545XX)
# define STM32_SRAM1_SIZE (0x00030000) /* 192Kb SRAM1 */
# define STM32_SRAM2_SIZE (0x00010000) /* 64kB SRAM2 */
#elif defined(CONFIG_STM32U5_STM32U575XX) || defined(CONFIG_STM32U5_STM32U585XX)
# define STM32_SRAM1_SIZE (0x00030000) /* 192Kb SRAM1 */
# define STM32_SRAM2_SIZE (0x00010000) /* 64kB SRAM2 */
# define STM32_SRAM3_SIZE (0x00080000) /* 512kB SRAM3 */
#elif defined(CONFIG_STM32U5_STM32U59XX) || defined(CONFIG_STM32U5_STM32U59AXX) || defined(CONFIG_STM32U5_STM32U5A5XX) || defined(CONFIG_STM32U5_STM32U5A9XX)
# define STM32_SRAM1_SIZE (0x000C0000) /* 768Kb SRAM1 */
# define STM32_SRAM2_SIZE (0x00010000) /* 64kB SRAM2 */
# define STM32_SRAM3_SIZE (0x000d0000) /* 832kB SRAM3 */
# define STM32_SRAM5_SIZE (0x000d0000) /* 832kB SRAM5 */
#else
# error "Unsupported STM32U5 chip"
#endif
#if defined(CONFIG_STM32U5_STM32U585XX)
#if defined(CONFIG_STM32U5_STM32U585XX) || defined(CONFIG_STM32U5_STM32U5A5XX)
# define STM32_NFSMC 1 /* Have FSMC memory controller */
# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */
# define STM32_NGTIM32 2 /* 32-bit general timers TIM2 and 5 with DMA */
@ -70,6 +78,10 @@
# define STM32_NOPAMP 2 /* Operational Amplifiers */
#endif /* CONFIG_STM32U5_STM32U585XX */
#if defined(CONFIG_STM32U5_STM32U5A5ZJT)
# define STM32_NUSBOTGHS 1 /* USB OTG HS */
#endif
/* NVIC priority levels *****************************************************/
/* 16 Programmable interrupt levels */

7
arch/arm/include/stm32u5/irq.h
View file

@ -31,8 +31,11 @@
#include <nuttx/config.h>
#if defined(CONFIG_STM32U5_STM32U585XX)
# include <arch/stm32u5/stm32u585xx_irq.h>
#if defined(CONFIG_STM32U5_STM32U535XX) || defined(CONFIG_STM32U5_STM32U545XX) || \
defined(CONFIG_STM32U5_STM32U575XX) || defined(CONFIG_STM32U5_STM32U585XX) || \
defined(CONFIG_STM32U5_STM32U59XX) || defined(CONFIG_STM32U5_STM32U59AXX) || \
defined(CONFIG_STM32U5_STM32U5A5XX) || defined(CONFIG_STM32U5_STM32U5A9XX)
# include <arch/stm32u5/stm32u5xx_irq.h>
#else
# error "Unsupported STM32U5 chip"
#endif

23
arch/arm/include/stm32u5/stm32u585xx_irq.h → arch/arm/include/stm32u5/stm32u5xx_irq.h
View file

@ -1,5 +1,5 @@
/****************************************************************************
* arch/arm/include/stm32u5/stm32u585xx_irq.h
* arch/arm/include/stm32u5/stm32u5xx_irq.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
@ -18,8 +18,8 @@
*
****************************************************************************/
#ifndef __ARCH_ARM_INCLUDE_STM32U5_STM32U585XX_IRQ_H
#define __ARCH_ARM_INCLUDE_STM32U5_STM32U585XX_IRQ_H
#ifndef __ARCH_ARM_INCLUDE_STM32U5_STM32U5XX_IRQ_H
#define __ARCH_ARM_INCLUDE_STM32U5_STM32U5XX_IRQ_H
/****************************************************************************
* Included Files
@ -128,7 +128,15 @@
#define STM32_IRQ_TIM16 (STM32_IRQ_FIRST + 70) /* 70: TIM16 global interrupt */
#define STM32_IRQ_TIM17 (STM32_IRQ_FIRST + 71) /* 71: TIM17 global interrupt */
#define STM32_IRQ_COMP (STM32_IRQ_FIRST + 72) /* 72: COMP1/COMP2 interrupts */
#define STM32_IRQ_OTG_FS (STM32_IRQ_FIRST + 73) /* 73: USB OTG FS global interrupt */
#if defined(CONFIG_STM32U5_STM32U535XX) || defined(CONFIG_STM32U5_STM32U545XX) || \
defined(CONFIG_STM32U5_STM32U575XX) || defined(CONFIG_STM32U5_STM32U585XX)
# define STM32_IRQ_OTG_FS (STM32_IRQ_FIRST + 73) /* 73: USB OTG FS global interrupt */
#elif defined(CONFIG_STM32U5_STM32U59XX) || defined(CONFIG_STM32U5_STM32U59AXX) || \
defined(CONFIG_STM32U5_STM32U5A5XX) || defined(CONFIG_STM32U5_STM32U5A9XX)
# define STM32_IRQ_OTG_HS (STM32_IRQ_FIRST + 73) /* 73: USB OTG HS global interrupt */
#else
# error "Unsupported STM32U5 chip"
#endif
#define STM32_IRQ_CRS (STM32_IRQ_FIRST + 74) /* 74: CRS global interrupt */
#define STM32_IRQ_FMC (STM32_IRQ_FIRST + 75) /* 75: FMC global interrupt */
#define STM32_IRQ_OCTOSPI1 (STM32_IRQ_FIRST + 76) /* 76: OCTOSPI1 global interrupt */
@ -181,7 +189,10 @@
#define STM32_IRQ_CORDIC (STM32_IRQ_FIRST + 123) /* 123: CORDIC interrupt */
#define STM32_IRQ_FMAC (STM32_IRQ_FIRST + 124) /* 124: FMAC interrupt */
#if defined(CONFIG_STM32U5_STM32U585XX)
#if defined(CONFIG_STM32U5_STM32U535XX) || defined(CONFIG_STM32U5_STM32U545XX) || \
defined(CONFIG_STM32U5_STM32U575XX) || defined(CONFIG_STM32U5_STM32U585XX) || \
defined(CONFIG_STM32U5_STM32U59XX) || defined(CONFIG_STM32U5_STM32U59AXX) || \
defined(CONFIG_STM32U5_STM32U5A5XX) || defined(CONFIG_STM32U5_STM32U5A9XX)
# define STM32_IRQ_NEXTINTS 125
#else
# error "Unsupported STM32U5 chip"
@ -191,4 +202,4 @@
#define NR_IRQS (STM32_IRQ_FIRST + STM32_IRQ_NEXTINTS)
#endif /* __ARCH_ARM_INCLUDE_STM32U5_STM32U585XX_IRQ_H */
#endif /* __ARCH_ARM_INCLUDE_STM32U5_STM32U5XX_IRQ_H */

164
arch/arm/src/stm32u5/Kconfig
View file

@ -20,10 +20,29 @@ config ARCH_CHIP_STM32U585AI
---help---
STM32 U5 Cortex M33, 2048 Kb FLASH, 768 Kb SRAM
endchoice # STM32 L5 Chip Selection
config ARCH_CHIP_STM32U5A5ZJT
bool "STM32U5A5ZJT"
select STM32U5_STM32U5A5XX
select STM32U5_IO_CONFIG_A
---help---
STM32 U5 Cortex M33, 4096 Kb FLASH, 2500 Kb SRAM, tqfp144
endchoice # STM32 U5 Chip Selection
# Chip families:
config STM32U5_STM32U5A5XX
# STM32U575 and STM32U585 devices documented in RM0456
bool
default n
select ARCH_HAVE_FPU
select STM32U5_HAVE_LPUART1
select STM32U5_HAVE_USART1
select STM32U5_HAVE_USART2
select STM32U5_HAVE_USART3
select STM32U5_HAVE_UART4
select STM32U5_HAVE_UART5
config STM32U5_STM32U585XX
# STM32U575 and STM32U585 devices documented in RM0456
bool
@ -155,34 +174,6 @@ config STM32U5_IO_CONFIG_A
bool
default n
comment "STM32U5 SRAM2 Options"
config STM32U5_SRAM2_HEAP
bool "SRAM2 is used for heap"
default n
select STM32U5_SRAM2_INIT
---help---
The STM32U5 SRAM2 region has special properties (power, protection, parity)
which may be used by the application for special purposes. But if these
special properties are not needed, it may be instead added to the heap for
use by malloc().
NOTE: you must also select an appropriate number of memory regions in the
'Memory Management' section.
config STM32U5_SRAM2_INIT
bool "SRAM2 is initialized to zero"
default n
---help---
The STM32U5 SRAM2 region has parity checking. However, when the system
powers on, the memory is in an unknown state, and reads from uninitialized
memory can trigger parity faults from the random data. This can be
avoided by first writing to all locations to force the parity into a valid
state.
However, if the SRAM2 is being used for it's battery-backed capability,
this may be undesirable (because it will destroy the contents). In that
case, the board should handle the initialization itself at the appropriate
time.
comment "STM32U5 Peripherals"
menu "STM32U5 Peripheral Support"
@ -284,6 +275,62 @@ config STM32U5_DCACHE1
config STM32U5_SRAM1
bool "SRAM1"
default y
config STM32U5_SRAM2
bool "SRAM2"
default n
config STM32U5_SRAM3
bool "SRAM3"
default n
depends on STM32U5_STM32U575XX || STM32U5_STM32U585XX || STM32U5_STM32U59XX || STM32U5_STM32U59AXX || \
STM32U5_STM32U5A5XX || STM32U5_STM32U5A9XX
config STM32U5_SRAM5
bool "SRAM5"
default n
depends on STM32U5_STM32U575XX || STM32U5_STM32U585XX || STM32U5_STM32U59XX || STM32U5_STM32U59AXX || \
STM32U5_STM32U5A5XX || STM32U5_STM32U5A9XX
comment "SRAM Options"
config STM32U5_SRAM2_HEAP
bool "SRAM2 is used for heap"
default n
depends on STM32U5_SRAM2
select STM32U5_SRAM2_INIT
---help---
The STM32U5 SRAM2 region has special properties (power, protection, parity)
which may be used by the application for special purposes. But if these
special properties are not needed, it may be instead added to the heap for
use by malloc().
NOTE: you must also select an appropriate number of memory regions in the
'Memory Management' section.
config STM32U5_SRAM2_INIT
bool "SRAM2 is initialized to zero"
default n
depends on STM32U5_SRAM2
---help---
The STM32U5 SRAM2 region has parity checking. However, when the system
powers on, the memory is in an unknown state, and reads from uninitialized
memory can trigger parity faults from the random data. This can be
avoided by first writing to all locations to force the parity into a valid
state.
However, if the SRAM2 is being used for it's battery-backed capability,
this may be undesirable (because it will destroy the contents). In that
case, the board should handle the initialization itself at the appropriate
time.
config STM32U5_SRAM3_HEAP
bool "SRAM3 is used for heap"
depends on STM32U5_SRAM3
default n
config STM32U5_SRAM5_HEAP
bool "SRAM5 is used for heap"
depends on STM32U5_SRAM5
default n
comment "AHB2 Peripherals"
@ -296,8 +343,14 @@ config STM32U5_DCMI_PSSI
bool "DCMI_PSSI"
default n
config STM32U5_OTG
bool "OTG"
config STM32U5_OTGFS
bool "OTG FS"
depends on STM32U5_STM32U535XX || CONFIG_STM32U5_STM32U545XX || STM32U5_STM32U575XX || STM32U5_STM32U585XX
default n
config STM32U5_OTGHS
bool "OTG HS"
depends on STM32U5_STM32U59XX || STM32U5_STM32U59AXX || STM32U5_STM32U5A5XX || STM32U5_STM32U5A9XX
default n
config STM32U5_AES
@ -340,14 +393,6 @@ config STM32U5_SDMMC2
bool "SDMMC2"
default n
config STM32U5_SRAM2
bool "SRAM2"
default n
config STM32U5_SRAM3
bool "SRAM3"
default n
config STM32U5_FSMC
bool "FSMC"
default n
@ -390,10 +435,6 @@ config STM32U5_GTZC2
bool "GTZC2"
default n
config STM32U5_SRAM4
bool "SRAM4"
default n
comment "APB1 Peripherals"
config STM32U5_TIM2
@ -457,18 +498,38 @@ config STM32U5_UART5
config STM32U5_I2C1
bool "I2C1"
default n
select STM32U5_I2C
config STM32U5_I2C2
bool "I2C2"
default n
select STM32U5_I2C
config STM32U5_CRS
bool "CRS"
config STM32U5_I2C3
bool "I2C3"
default n
select STM32U5_I2C
config STM32U5_I2C4
bool "I2C4"
default n
select STM32U5_I2C
config STM32U5_I2C5
bool "I2C5"
depends on STM32U5_STM32U59XX || STM32U5_STM32U59AXX || STM32U5_STM32U5A5XX || STM32U5_STM32U5A9XX
default n
select STM32U5_I2C
config STM32U5_I2C6
bool "I2C6"
depends on STM32U5_STM32U59XX || STM32U5_STM32U59AXX || STM32U5_STM32U5A5XX || STM32U5_STM32U5A9XX
default n
select STM32U5_I2C
config STM32U5_CRS
bool "CRS"
default n
config STM32U5_LPTIM2
bool "LPTIM2"
@ -542,10 +603,6 @@ config STM32U5_LPUART1
select ARCH_HAVE_SERIAL_TERMIOS
select STM32U5_USART
config STM32U5_I2C3
bool "I2C3"
default n
config STM32U5_LPTIM1
bool "LPTIM1"
default n
@ -614,11 +671,6 @@ config ARCH_BOARD_STM32U5_CUSTOM_CLOCKCONFIG
---help---
Enables special, board-specific STM32 clock configuration.
config STM32U5_HAVE_RTC_SUBSECONDS
bool
select ARCH_HAVE_RTC_SUBSECONDS
default y
menu "RTC Configuration"
depends on STM32U5_RTC
@ -3171,6 +3223,10 @@ config STM32U5_SPI_DMA
endmenu
config STM32U5_I2C
bool
default n
menu "I2C Configuration"
depends on STM32U5_I2C

8
arch/arm/src/stm32u5/Make.defs
View file

@ -31,9 +31,9 @@ include armv8-m/Make.defs
CHIP_ASRCS =
CHIP_CSRCS = stm32_allocateheap.c stm32_exti_gpio.c stm32_gpio.c
CHIP_CSRCS += stm32_irq.c stm32_lowputc.c stm32_rcc.c
CHIP_CSRCS += stm32_irq.c stm32_lowputc.c stm32_rcc.c stm32_i2c.c
CHIP_CSRCS += stm32_serial.c stm32_start.c stm32_waste.c stm32_uid.c
CHIP_CSRCS += stm32_spi.c stm32_lse.c stm32_lsi.c
CHIP_CSRCS += stm32_spi.c stm32_lse.c stm32_lsi.c stm32u5xx_rcc.c
CHIP_CSRCS += stm32_pwr.c stm32_tim.c stm32_flash.c stm32_timerisr.c
ifneq ($(CONFIG_ARCH_IDLE_CUSTOM),y)
@ -54,6 +54,6 @@ endif
# Required chip type specific files
ifeq ($(CONFIG_STM32U5_STM32U585XX),y)
CHIP_CSRCS += stm32u585xx_rcc.c
ifeq ($(CONFIG_USBDEV),y)
CHIP_CSRCS += stm32_otgdev.c
endif

44
arch/arm/src/stm32u5/hardware/stm32_flash.h
View file

@ -41,38 +41,46 @@
* Parts STM32U585 and STM32U575 have 2048Kb of FLASH
*/
#if !defined(CONFIG_STM32U5_FLASH_OVERRIDE_DEFAULT) && \
#if defined(CONFIG_ARCH_CHIP_STM32U585AI)
# if !defined(CONFIG_STM32U5_FLASH_OVERRIDE_DEFAULT) && \
!defined(CONFIG_STM32U5_FLASH_OVERRIDE_C) && \
!defined(CONFIG_STM32U5_FLASH_OVERRIDE_E) && \
!defined(CONFIG_STM32U5_FLASH_CONFIG_C) && \
!defined(CONFIG_STM32U5_FLASH_CONFIG_E)
# define CONFIG_STM32U5_FLASH_OVERRIDE_E
# warning "Flash size not defined defaulting to 512KiB (E)"
#endif
# define CONFIG_STM32U5_FLASH_OVERRIDE_E
# warning "Flash size not defined defaulting to 512KiB (E)"
# endif
/* Override of the Flash has been chosen */
#if !defined(CONFIG_STM32U5_FLASH_OVERRIDE_DEFAULT)
# undef CONFIG_STM32U5_FLASH_CONFIG_C
# undef CONFIG_STM32U5_FLASH_CONFIG_E
# if defined(CONFIG_STM32U5_FLASH_OVERRIDE_C)
# define CONFIG_STM32U5_FLASH_CONFIG_C
# elif defined(CONFIG_STM32U5_FLASH_OVERRIDE_E)
# define CONFIG_STM32U5_FLASH_CONFIG_E
# if !defined(CONFIG_STM32U5_FLASH_OVERRIDE_DEFAULT)
# undef CONFIG_STM32U5_FLASH_CONFIG_C
# undef CONFIG_STM32U5_FLASH_CONFIG_E
# if defined(CONFIG_STM32U5_FLASH_OVERRIDE_C)
# define CONFIG_STM32U5_FLASH_CONFIG_C
# elif defined(CONFIG_STM32U5_FLASH_OVERRIDE_E)
# define CONFIG_STM32U5_FLASH_CONFIG_E
# endif
# endif
#endif
/* Define the valid configuration */
#if defined(CONFIG_STM32U5_FLASH_CONFIG_I) /* 2048 kB */
# define STM32_FLASH_NPAGES 256
# define STM32_FLASH_PAGESIZE 8192
#else
# error "unknown flash configuration!"
# if defined(CONFIG_STM32U5_FLASH_CONFIG_I) /* 2048 kB */
# define STM32_FLASH_NPAGES 256
# define STM32_FLASH_PAGESIZE 8192
# else
# error "unknown flash configuration!"
# endif
#endif
#ifdef STM32_FLASH_PAGESIZE
# define STM32_FLASH_SIZE (STM32_FLASH_NPAGES * STM32_FLASH_PAGESIZE)
# define STM32_FLASH_SIZE (STM32_FLASH_NPAGES * STM32_FLASH_PAGESIZE)
#endif
#if defined(CONFIG_STM32U5_STM32U5A5XX)
# define STM32_FLASH_NPAGES 512
# define STM32_FLASH_PAGESIZE 8192
# define STM32_FLASH_SIZE (STM32_FLASH_NPAGES * STM32_FLASH_PAGESIZE)
#endif
/* Register Offsets *********************************************************/

250
arch/arm/src/stm32u5/hardware/stm32_i2c.h Normal file
View file

@ -0,0 +1,250 @@
/****************************************************************************
* arch/arm/src/stm32u5/hardware/stm32_i2c.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32U5_HARDWARE_STM32_I2C_H
#define __ARCH_ARM_SRC_STM32U5_HARDWARE_STM32_I2C_H
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Register Offsets *********************************************************/
#define STM32_I2C_CR1_OFFSET 0x0000 /* Control register 1 (32-bit) */
#define STM32_I2C_CR2_OFFSET 0x0004 /* Control register 2 (32-bit) */
#define STM32_I2C_OAR1_OFFSET 0x0008 /* Own address register 1 (16-bit) */
#define STM32_I2C_OAR2_OFFSET 0x000c /* Own address register 2 (16-bit) */
#define STM32_I2C_TIMINGR_OFFSET 0x0010 /* Timing register */
#define STM32_I2C_TIMEOUTR_OFFSET 0x0014 /* Timeout register */
#define STM32_I2C_ISR_OFFSET 0x0018 /* Interrupt and Status register */
#define STM32_I2C_ICR_OFFSET 0x001c /* Interrupt clear register */
#define STM32_I2C_PECR_OFFSET 0x0020 /* Packet error checking register */
#define STM32_I2C_RXDR_OFFSET 0x0024 /* Receive data register */
#define STM32_I2C_TXDR_OFFSET 0x0028 /* Transmit data register */
/* Register Addresses *******************************************************/
#if STM32_NI2C > 0
# define STM32_I2C1_CR1 (STM32_I2C1_BASE+STM32_I2C_CR1_OFFSET)
# define STM32_I2C1_CR2 (STM32_I2C1_BASE+STM32_I2C_CR2_OFFSET)
# define STM32_I2C1_OAR1 (STM32_I2C1_BASE+STM32_I2C_OAR1_OFFSET)
# define STM32_I2C1_OAR2 (STM32_I2C1_BASE+STM32_I2C_OAR2_OFFSET)
# define STM32_I2C1_TIMINGR (STM32_I2C1_BASE+STM32_I2C_TIMINGR_OFFSET)
# define STM32_I2C1_TIMEOUTR (STM32_I2C1_BASE+STM32_I2C_TIMEOUTR_OFFSET)
# define STM32_I2C1_ISR (STM32_I2C1_BASE+STM32_I2C_ISR_OFFSET)
# define STM32_I2C1_ICR (STM32_I2C1_BASE+STM32_I2C_ICR_OFFSET)
# define STM32_I2C1_PECR (STM32_I2C1_BASE+STM32_I2C_PECR_OFFSET)
# define STM32_I2C1_RXDR (STM32_I2C1_BASE+STM32_I2C_RXDR_OFFSET)
# define STM32_I2C1_TXDR (STM32_I2C1_BASE+STM32_I2C_TXDR_OFFSET)
#endif
#if STM32_NI2C > 1
# define STM32_I2C2_CR1 (STM32_I2C2_BASE+STM32_I2C_CR1_OFFSET)
# define STM32_I2C2_CR2 (STM32_I2C2_BASE+STM32_I2C_CR2_OFFSET)
# define STM32_I2C2_OAR1 (STM32_I2C2_BASE+STM32_I2C_OAR1_OFFSET)
# define STM32_I2C2_OAR2 (STM32_I2C2_BASE+STM32_I2C_OAR2_OFFSET)
# define STM32_I2C2_TIMINGR (STM32_I2C2_BASE+STM32_I2C_TIMINGR_OFFSET)
# define STM32_I2C2_TIMEOUTR (STM32_I2C2_BASE+STM32_I2C_TIMEOUTR_OFFSET)
# define STM32_I2C2_ISR (STM32_I2C2_BASE+STM32_I2C_ISR_OFFSET)
# define STM32_I2C2_ICR (STM32_I2C2_BASE+STM32_I2C_ICR_OFFSET)
# define STM32_I2C2_PECR (STM32_I2C2_BASE+STM32_I2C_PECR_OFFSET)
# define STM32_I2C2_RXDR (STM32_I2C2_BASE+STM32_I2C_RXDR_OFFSET)
# define STM32_I2C2_TXDR (STM32_I2C2_BASE+STM32_I2C_TXDR_OFFSET)
#endif
#if STM32_NI2C > 2
# define STM32_I2C3_CR1 (STM32_I2C3_BASE+STM32_I2C_CR1_OFFSET)
# define STM32_I2C3_CR2 (STM32_I2C3_BASE+STM32_I2C_CR2_OFFSET)
# define STM32_I2C3_OAR1 (STM32_I2C3_BASE+STM32_I2C_OAR1_OFFSET)
# define STM32_I2C3_OAR2 (STM32_I2C3_BASE+STM32_I2C_OAR2_OFFSET)
# define STM32_I2C3_TIMINGR (STM32_I2C3_BASE+STM32_I2C_TIMINGR_OFFSET)
# define STM32_I2C3_TIMEOUTR (STM32_I2C3_BASE+STM32_I2C_TIMEOUTR_OFFSET)
# define STM32_I2C3_ISR (STM32_I2C3_BASE+STM32_I2C_ISR_OFFSET)
# define STM32_I2C3_ICR (STM32_I2C3_BASE+STM32_I2C_ICR_OFFSET)
# define STM32_I2C3_PECR (STM32_I2C3_BASE+STM32_I2C_PECR_OFFSET)
# define STM32_I2C3_RXDR (STM32_I2C3_BASE+STM32_I2C_RXDR_OFFSET)
# define STM32_I2C3_TXDR (STM32_I2C3_BASE+STM32_I2C_TXDR_OFFSET)
#endif
#if STM32_NI2C > 3
# define STM32_I2C4_CR1 (STM32_I2C4_BASE+STM32_I2C_CR1_OFFSET)
# define STM32_I2C4_CR2 (STM32_I2C4_BASE+STM32_I2C_CR2_OFFSET)
# define STM32_I2C4_OAR1 (STM32_I2C4_BASE+STM32_I2C_OAR1_OFFSET)
# define STM32_I2C4_OAR2 (STM32_I2C4_BASE+STM32_I2C_OAR2_OFFSET)
# define STM32_I2C4_TIMINGR (STM32_I2C4_BASE+STM32_I2C_TIMINGR_OFFSET)
# define STM32_I2C4_TIMEOUTR (STM32_I2C4_BASE+STM32_I2C_TIMEOUTR_OFFSET)
# define STM32_I2C4_ISR (STM32_I2C4_BASE+STM32_I2C_ISR_OFFSET)
# define STM32_I2C4_ICR (STM32_I2C4_BASE+STM32_I2C_ICR_OFFSET)
# define STM32_I2C4_PECR (STM32_I2C4_BASE+STM32_I2C_PECR_OFFSET)
# define STM32_I2C4_RXDR (STM32_I2C4_BASE+STM32_I2C_RXDR_OFFSET)
# define STM32_I2C4_TXDR (STM32_I2C4_BASE+STM32_I2C_TXDR_OFFSET)
#endif
/* Register Bitfield Definitions ********************************************/
/* Control register 1 */
#define I2C_CR1_PE (1 << 0) /* Bit 0: Peripheral Enable */
#define I2C_CR1_TXIE (1 << 1) /* Bit 1: TX Interrupt enable */
#define I2C_CR1_RXIE (1 << 2) /* Bit 2: RX Interrupt enable */
#define I2C_CR1_ADDRIE (1 << 3) /* Bit 3: Address match interrupt enable (slave) */
#define I2C_CR1_NACKIE (1 << 4) /* Bit 4: Not acknowledge received interrupt enable */
#define I2C_CR1_STOPIE (1 << 5) /* Bit 5: STOP detection interrupt enable */
#define I2C_CR1_TCIE (1 << 6) /* Bit 6: Transfer Complete interrupt enable */
#define I2C_CR1_ERRIE (1 << 7) /* Bit 7: Error interrupts enable */
#define I2C_CR1_DNF_SHIFT (8) /* Bits 8-11: Digital noise filter */
#define I2C_CR1_DNF_MASK (15 << I2C_CR1_DNF_SHIFT)
# define I2C_CR1_DNF_DISABLE (0 << I2C_CR1_DNF_SHIFT)
# define I2C_CR1_DNF(n) ((n) << I2C_CR1_DNF_SHIFT) /* Up to n * Ti2cclk, n=1..15 */
#define I2C_CR1_ANFOFF (1 << 12) /* Bit 12: Analog noise filter OFF */
#define I2C_CR1_TXDMAEN (1 << 14) /* Bit 14: DMA transmission requests enable */
#define I2C_CR1_RXDMAEN (1 << 15) /* Bit 15: DMA reception requests enable */
#define I2C_CR1_SBC (1 << 16) /* Bit 16: Slave byte control */
#define I2C_CR1_NOSTRETCH (1 << 17) /* Bit 17: Clock stretching disable */
#define I2C_CR1_WUPEN (1 << 18) /* Bit 18: Wakeup from STOP enable */
#define I2C_CR1_GCEN (1 << 19) /* Bit 19: General call enable */
#define I2C_CR1_SMBHEN (1 << 20) /* Bit 20: SMBus Host address enable */
#define I2C_CR1_SMBDEN (1 << 21) /* Bit 21: SMBus Device Default address enable */
#define I2C_CR1_ALERTEN (1 << 22) /* Bit 22: SMBus alert enable */
#define I2C_CR1_PECEN (1 << 23) /* Bit 23: PEC enable */
/* Control register 2 */
#define I2C_CR2_SADD10_SHIFT (0) /* Bits 0-9: Slave 10-bit address (master) */
#define I2C_CR2_SADD10_MASK (0x3ff << I2C_CR2_SADD10_SHIFT)
#define I2C_CR2_SADD7_SHIFT (1) /* Bits 1-7: Slave 7-bit address (master) */
#define I2C_CR2_SADD7_MASK (0x7f << I2C_CR2_SADD7_SHIFT)
#define I2C_CR2_RD_WRN (1 << 10) /* Bit 10: Transfer direction (master) */
#define I2C_CR2_ADD10 (1 << 11) /* Bit 11: 10-bit addressing mode (master) */
#define I2C_CR2_HEAD10R (1 << 12) /* Bit 12: 10-bit address header only read direction (master) */
#define I2C_CR2_START (1 << 13) /* Bit 13: Start generation */
#define I2C_CR2_STOP (1 << 14) /* Bit 14: Stop generation (master) */
#define I2C_CR2_NACK (1 << 15) /* Bit 15: NACK generation (slave) */
#define I2C_CR2_NBYTES_SHIFT (16) /* Bits 16-23: Number of bytes */
#define I2C_CR2_NBYTES_MASK (0xff << I2C_CR2_NBYTES_SHIFT)
#define I2C_CR2_RELOAD (1 << 24) /* Bit 24: NBYTES reload mode */
#define I2C_CR2_AUTOEND (1 << 25) /* Bit 25: Automatic end mode (master) */
#define I2C_CR2_PECBYTE (1 << 26) /* Bit 26: Packet error checking byte */
/* Own address register 1 */
#define I2C_OAR1_OA1_10_SHIFT (0) /* Bits 0-9: 10-bit interface address */
#define I2C_OAR1_OA1_10_MASK (0x3ff << I2C_OAR1_OA1_10_SHIFT)
#define I2C_OAR1_OA1_7_SHIFT (1) /* Bits 1-7: 7-bit interface address */
#define I2C_OAR1_OA1_7_MASK (0x7f << I2C_OAR1_OA1_7_SHIFT)
#define I2C_OAR1_OA1MODE (1 << 10) /* Bit 10: Own Address 1 10-bit mode */
#define I2C_OAR1_OA1EN (1 << 15) /* Bit 15: Own Address 1 enable */
/* Own address register 2 */
#define I2C_OAR2_OA2_SHIFT (1) /* Bits 1-7: 7-bit interface address */
#define I2C_OAR2_OA2_MASK (0x7f << I2C_OAR2_OA2_SHIFT)
#define I2C_OAR2_OA2MSK_SHIFT (8) /* Bits 8-10: Own Address 2 masks */
#define I2C_OAR2_OA2MSK_MASK (7 << I2C_OAR2_OA2MSK_SHIFT)
# define I2C_OAR2_OA2MSK_NONE (0 << I2C_OAR2_OA2MSK_SHIFT) /* No mask */
# define I2C_OAR2_OA2MSK_2_7 (1 << I2C_OAR2_OA2MSK_SHIFT) /* Only OA2[7:2] are compared */
# define I2C_OAR2_OA2MSK_3_7 (2 << I2C_OAR2_OA2MSK_SHIFT) /* Only OA2[7:3] are compared */
# define I2C_OAR2_OA2MSK_4_7 (3 << I2C_OAR2_OA2MSK_SHIFT) /* Only OA2[7:4] are compared */
# define I2C_OAR2_OA2MSK_5_7 (4 << I2C_OAR2_OA2MSK_SHIFT) /* Only OA2[7:5] are compared */
# define I2C_OAR2_OA2MSK_6_7 (5 << I2C_OAR2_OA2MSK_SHIFT) /* Only OA2[7:6] are compared */
# define I2C_OAR2_OA2MSK_7 (6 << I2C_OAR2_OA2MSK_SHIFT) /* Only OA2[7] is compared */
# define I2C_OAR2_OA2MSK_ALL (7 << I2C_OAR2_OA2MSK_SHIFT) /* All 7-bit addresses acknowledged */
#define I2C_OAR2_OA2EN (1 << 15) /* Bit 15: Own Address 2 enable */
/* Timing register */
#define I2C_TIMINGR_SCLL_SHIFT (0) /* Bits 0-7: SCL low period (master) */
#define I2C_TIMINGR_SCLL_MASK (0xff << I2C_TIMINGR_SCLL_SHIFT)
# define I2C_TIMINGR_SCLL(n) (((n)-1) << I2C_TIMINGR_SCLL_SHIFT) /* tSCLL = n x tPRESC */
#define I2C_TIMINGR_SCLH_SHIFT (8) /* Bits 8-15: SCL high period (master) */
#define I2C_TIMINGR_SCLH_MASK (0xff << I2C_TIMINGR_SCLH_SHIFT)
# define I2C_TIMINGR_SCLH(n) (((n)-1) << I2C_TIMINGR_SCLH_SHIFT) /* tSCLH = n x tPRESC */
#define I2C_TIMINGR_SDADEL_SHIFT (16) /* Bits 16-19: Data hold time */
#define I2C_TIMINGR_SDADEL_MASK (15 << I2C_TIMINGR_SDADEL_SHIFT)
# define I2C_TIMINGR_SDADEL(n) ((n) << I2C_TIMINGR_SDADEL_SHIFT) /* tSDADEL= n x tPRESC */
#define I2C_TIMINGR_SCLDEL_SHIFT (20) /* Bits 20-23: Data setup time */
#define I2C_TIMINGR_SCLDEL_MASK (15 << I2C_TIMINGR_SCLDEL_SHIFT)
# define I2C_TIMINGR_SCLDEL(n) (((n)-1) << I2C_TIMINGR_SCLDEL_SHIFT) /* tSCLDEL = n x tPRESC */
#define I2C_TIMINGR_PRESC_SHIFT (28) /* Bits 28-31: Timing prescaler */
#define I2C_TIMINGR_PRESC_MASK (15 << I2C_TIMINGR_PRESC_SHIFT)
# define I2C_TIMINGR_PRESC(n) (((n)-1) << I2C_TIMINGR_PRESC_SHIFT) /* tPRESC = n x tI2CCLK */
/* Timeout register */
#define I2C_TIMEOUTR_A_SHIFT (0) /* Bits 0-11: Bus Timeout A */
#define I2C_TIMEOUTR_A_MASK (0x0fff << I2C_TIMEOUTR_A_SHIFT)
# define I2C_TIMEOUTR_A(n) ((n) << I2C_TIMEOUTR_A_SHIFT)
#define I2C_TIMEOUTR_TIDLE (1 << 12) /* Bit 12: Idle clock timeout detection */
#define I2C_TIMEOUTR_TIMOUTEN (1 << 15) /* Bit 15: Clock timeout enable */
#define I2C_TIMEOUTR_B_SHIFT (16) /* Bits 16-27: Bus Timeout B */
#define I2C_TIMEOUTR_B_MASK (0x0fff << I2C_TIMEOUTR_B_SHIFT)
# define I2C_TIMEOUTR_B(n) ((n) << I2C_TIMEOUTR_B_SHIFT)
#define I2C_TIMEOUTR_TEXTEN (1 << 31) /* Bits 31: Extended clock timeout enable */
/* Interrupt and Status register and interrupt clear register */
/* Common interrupt bits */
#define I2C_INT_ADDR (1 << 3) /* Bit 3: Address matched (slave) */
#define I2C_INT_NACK (1 << 4) /* Bit 4: Not Acknowledge received flag */
#define I2C_INT_STOP (1 << 5) /* Bit 5: Stop detection flag */
#define I2C_INT_BERR (1 << 8) /* Bit 8: Bus error */
#define I2C_INT_ARLO (1 << 9) /* Bit 9: Arbitration lost */
#define I2C_INT_OVR (1 << 10) /* Bit 10: Overrun/Underrun (slave) */
#define I2C_INT_PECERR (1 << 11) /* Bit 11: PEC Error in reception */
#define I2C_INT_TIMEOUT (1 << 12) /* Bit 12: Timeout or tLOW detection flag */
#define I2C_INT_ALERT (1 << 13) /* Bit 13: SMBus alert */
/* Fields unique to the Interrupt and Status register */
#define I2C_ISR_TXE (1 << 0) /* Bit 0: Transmit data register empty (transmitters) */
#define I2C_ISR_TXIS (1 << 1) /* Bit 1: Transmit interrupt status (transmitters) */
#define I2C_ISR_RXNE (1 << 2) /* Bit 2: Receive data register not empty (receivers) */
#define I2C_ISR_TC (1 << 6) /* Bit 6: Transfer Complete (master) */
#define I2C_ISR_TCR (1 << 7) /* Bit 7: Transfer Complete Reload */
#define I2C_ISR_BUSY (1 << 15) /* Bit 15: Bus busy */
#define I2C_ISR_DIR (1 << 16) /* Bit 16: Transfer direction (slave) */
#define I2C_ISR_ADDCODE_SHIFT (17) /* Bits 17-23: Address match code (slave) */
#define I2C_ISR_ADDCODE_MASK (0x7f << I2C_ISR_ADDCODE_SHIFT)
#define I2C_ISR_ERRORMASK (I2C_INT_BERR | I2C_INT_ARLO | I2C_INT_OVR | I2C_INT_PECERR | I2C_INT_TIMEOUT)
#define I2C_ICR_CLEARMASK (I2C_INT_ADDR | I2C_INT_NACK | I2C_INT_STOP | I2C_INT_BERR | I2C_INT_ARLO \
| I2C_INT_OVR | I2C_INT_PECERR | I2C_INT_TIMEOUT | I2C_INT_ALERT)
/* Packet error checking register */
#define I2C_PECR_MASK (0xff)
/* Receive data register */
#define I2C_RXDR_MASK (0xff)
/* Transmit data register */
#define I2C_TXDR_MASK (0xff)
#endif /* __ARCH_ARM_SRC_STM32U5_HARDWARE_STM32_I2C_H */

34
arch/arm/src/stm32u5/hardware/stm32_memorymap.h
View file

@ -43,11 +43,34 @@
/* Code Base Addresses ******************************************************/
#define STM32_BOOT_BASE 0x00000000 /* 0x00000000-0x000fffff: Aliased boot memory */
#define STM32_FLASH_BASE 0x08000000 /* 0x08000000-0x081fffff: FLASH memory */
#define STM32_SRAM1_BASE 0x20000000 /* 0x20000000-0x2002ffff: 192k SRAM1 */
#define STM32_SRAM2_BASE 0x20030000 /* 0x20030000-0x2003ffff: 64k SRAM2 */
#define STM32_SRAM3_BASE 0x20040000 /* 0x20040000-0x200bffff: 512k SRAM3 */
#if defined(CONFIG_STM32U5_STM32U535XX) || defined(CONFIG_STM32U5_STM32U545XX)
# define STM32_BOOT_BASE 0x00000000 /* 0x00000000-0x000fffff: Aliased boot memory */
# define STM32_FLASH_BASE 0x08000000 /* 0x08000000-0x081fffff: FLASH memory */
# define STM32_SRAM1_BASE 0x20000000 /* 0x20000000-0x2002ffff: 192k SRAM1 */
# define STM32_SRAM2_BASE 0x20030000 /* 0x20030000-0x2003ffff: 64k SRAM2 */
#elif defined(CONFIG_STM32U5_STM32U575XX) || defined(CONFIG_STM32U5_STM32U585XX)
# define STM32_BOOT_BASE 0x00000000 /* 0x00000000-0x000fffff: Aliased boot memory */
# define STM32_FLASH_BASE 0x08000000 /* 0x08000000-0x081fffff: FLASH memory */
# define STM32_SRAM1_BASE 0x20000000 /* 0x20000000-0x2002ffff: 192k SRAM1 */
# define STM32_SRAM2_BASE 0x20030000 /* 0x20030000-0x2003ffff: 64k SRAM2 */
# define STM32_SRAM3_BASE 0x20040000 /* 0x20040000-0x200bffff: 512k SRAM3 */
#elif defined(CONFIG_STM32U5_STM32U59XX) || defined(CONFIG_STM32U5_STM32U59AXX) || \
defined(CONFIG_STM32U5_STM32U5A5XX) || defined(CONFIG_STM32U5_STM32U5A9XX)
# define STM32_BOOT_BASE 0x00000000 /* 0x00000000-0x000fffff: Aliased boot memory */
# define STM32_FLASH_BASE 0x08000000 /* 0x08000000-0x081fffff: FLASH memory */
# define STM32_SRAM1_BASE 0x20000000 /* 0x20000000-0x200bffff: 768k SRAM1 */
# define STM32_SRAM2_BASE 0x200c0000 /* 0x200c0000-0x200cffff: 64k SRAM2 */
# define STM32_SRAM3_BASE 0x200d0000 /* 0x200d0000-0x2019ffff: 832k SRAM3 */
# define STM32_SRAM4_BASE 0x28000000 /* 0x28000000-0x20003fff: 16k SRAM4 */
# define STM32_SRAM5_BASE 0x201a0000 /* 0x201a0000-0x2027ffff: 832k SRAM5 */
#else
# error "stm32_memorymap: unsupported STM32U5 memory map"
#endif
/* System Memory Addresses **************************************************/
@ -135,6 +158,7 @@
#define STM32_DCMI_BASE 0x4202c000
#define STM32_PSSI_BASE 0x4202c400
#define STM32_OTG_FS_BASE 0x42040000
#define STM32_USBOTGHS_BASE 0x42040000 /* HS */
#define STM32_AES_BASE 0x420c0000
#define STM32_HASH_BASE 0x420c0400
#define STM32_RNG_BASE 0x420c0800

4
arch/arm/src/stm32u5/hardware/stm32_pinmap.h
View file

@ -28,8 +28,8 @@
#include <nuttx/config.h>
#include "chip.h"
#if defined(CONFIG_STM32U5_STM32U585XX)
# include "hardware/stm32u585xx_pinmap.h"
#if defined(CONFIG_STM32U5_STM32U585XX) || defined(CONFIG_STM32U5_STM32U5A5XX)
# include "hardware/stm32u5xx_pinmap.h"
#else
# error "Unsupported STM32U5 pin map"
#endif

9
arch/arm/src/stm32u5/hardware/stm32_spi.h
View file

@ -28,10 +28,13 @@
#include <nuttx/config.h>
#include "chip.h"
#if defined(CONFIG_STM32U5_STM32U585XX)
# include "hardware/stm32u585xx_spi.h"
#if defined(CONFIG_STM32U5_STM32U535XX) || defined(CONFIG_STM32U5_STM32U545XX) || \
defined(CONFIG_STM32U5_STM32U575XX) || defined(CONFIG_STM32U5_STM32U585XX) || \
defined(CONFIG_STM32U5_STM32U59XX) || defined(CONFIG_STM32U5_STM32U59AXX) || \
defined(CONFIG_STM32U5_STM32U5A5XX) || defined(CONFIG_STM32U5_STM32U5A9XX)
# include "hardware/stm32u5xx_spi.h"
#else
# error "Unsupported STM32 U5 sub family"
# error "Unsupported STM32U5 chip"
#endif
#endif /* __ARCH_ARM_SRC_STM32U5_HARDWARE_STM32_SPI_H */

4
arch/arm/src/stm32u5/hardware/stm32_syscfg.h
View file

@ -28,8 +28,8 @@
#include <nuttx/config.h>
#include "chip.h"
#if defined(CONFIG_STM32U5_STM32U585XX)
# include "hardware/stm32u585xx_syscfg.h"
#if defined(CONFIG_STM32U5_STM32U585XX) || defined(CONFIG_STM32U5_STM32U5A5XX)
# include "hardware/stm32u5xx_syscfg.h"
#else
# error "Unsupported STM32U5 chip"
#endif

8
arch/arm/src/stm32u5/hardware/stm32u585xx_dbgmcu.h → arch/arm/src/stm32u5/hardware/stm32u5xx_dbgmcu.h
View file

@ -1,5 +1,5 @@
/****************************************************************************
* arch/arm/src/stm32u5/hardware/stm32u585xx_dbgmcu.h
* arch/arm/src/stm32u5/hardware/stm32u5xx_dbgmcu.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
@ -18,8 +18,8 @@
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32U5_HARDWARE_STM32U585XX_DBGMCU_H
#define __ARCH_ARM_SRC_STM32U5_HARDWARE_STM32U585XX_DBGMCU_H
#ifndef __ARCH_ARM_SRC_STM32U5_HARDWARE_STM32U5XX_DBGMCU_H
#define __ARCH_ARM_SRC_STM32U5_HARDWARE_STM32U5XX_DBGMCU_H
/****************************************************************************
* Included Files
@ -93,4 +93,4 @@
#define DBGMCU_APB2_TIM16STOP (1 << 17) /* Bit 17: TIM16 stopped when core is halted */
#define DBGMCU_APB2_TIM17STOP (1 << 18) /* Bit 18: TIM17 stopped when core is halted */
#endif /* __ARCH_ARM_SRC_STM32U5_HARDWARE_STM32U585XXDBGMCU_H */
#endif /* __ARCH_ARM_SRC_STM32U5_HARDWARE_STM32U5XXD_BGMCU_H */

28
arch/arm/src/stm32u5/hardware/stm32u585xx_pinmap.h → arch/arm/src/stm32u5/hardware/stm32u5xx_pinmap.h
View file

@ -1,5 +1,5 @@
/****************************************************************************
* arch/arm/src/stm32u5/hardware/stm32u585xx_pinmap.h
* arch/arm/src/stm32u5/hardware/stm32u5xx_pinmap.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
@ -18,8 +18,8 @@
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32U5_HARDWARE_STM32U585XX_PINMAP_H
#define __ARCH_ARM_SRC_STM32U5_HARDWARE_STM32U585XX_PINMAP_H
#ifndef __ARCH_ARM_SRC_STM32U5_HARDWARE_STM32U5XX_PINMAP_H
#define __ARCH_ARM_SRC_STM32U5_HARDWARE_STM32U5XX_PINMAP_H
/****************************************************************************
* Included Files
@ -409,8 +409,8 @@
#define GPIO_I2C1_SCL_2 (GPIO_ALT|GPIO_AF4|GPIO_PORTB|GPIO_PIN8)
#define GPIO_I2C1_SCL_3 (GPIO_ALT|GPIO_AF4|GPIO_PORTG|GPIO_PIN14)
#define GPIO_I2C1_SDA_1 (GPIO_ALT|GPIO_AF4|GPIO_PORTB|GPIO_PIN3)
#define GPIO_I2C1_SDA_2 (GPIO_ALT|GPIO_AF4|GPIO_PORTB|GPIO_PIN7)
#define GPIO_I2C1_SDA_3 (GPIO_ALT|GPIO_AF4|GPIO_PORTB|GPIO_PIN9)
#define GPIO_I2C1_SDA_3 (GPIO_ALT|GPIO_AF4|GPIO_PORTB|GPIO_PIN7)
#define GPIO_I2C1_SDA_2 (GPIO_ALT|GPIO_AF4|GPIO_PORTB|GPIO_PIN9)
#define GPIO_I2C1_SDA_4 (GPIO_ALT|GPIO_AF4|GPIO_PORTG|GPIO_PIN13)
#define GPIO_I2C1_SMBA_1 (GPIO_ALT|GPIO_AF4|GPIO_PORTA|GPIO_PIN1)
#define GPIO_I2C1_SMBA_2 (GPIO_ALT|GPIO_AF4|GPIO_PORTA|GPIO_PIN14)
@ -666,15 +666,15 @@
#define GPIO_OCTOSPIM_P2_NCS_4 (GPIO_ALT|GPIO_AF5|GPIO_PORTI|GPIO_PIN5)
#define GPIO_OCTOSPIM_P2_NCS_5 (GPIO_ALT|GPIO_AF10|GPIO_PORTD|GPIO_PIN3)
/* OTG_FS - USB on-the-go full-speed */
/* OTG_HS - USB on-the-go high-speed */
#define GPIO_OTG_FS_DM_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTA|GPIO_PIN11)
#define GPIO_OTG_FS_DP_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTA|GPIO_PIN12)
#define GPIO_OTG_FS_ID_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTA|GPIO_PIN10)
#define GPIO_OTG_FS_NOE_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTA|GPIO_PIN13)
#define GPIO_OTG_FS_NOE_2 (GPIO_ALT|GPIO_AF10|GPIO_PORTC|GPIO_PIN9)
#define GPIO_OTG_FS_SOF_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTA|GPIO_PIN8)
#define GPIO_OTG_FS_SOF_2 (GPIO_ALT|GPIO_AF10|GPIO_PORTA|GPIO_PIN14)
#define GPIO_OTG_HS_DM_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTA|GPIO_PIN11)
#define GPIO_OTG_HS_DP_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTA|GPIO_PIN12)
#define GPIO_OTG_HS_ID_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTA|GPIO_PIN10)
#define GPIO_OTG_HS_NOE_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTA|GPIO_PIN13)
#define GPIO_OTG_HS_NOE_2 (GPIO_ALT|GPIO_AF10|GPIO_PORTC|GPIO_PIN9)
#define GPIO_OTG_HS_SOF_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTA|GPIO_PIN8)
#define GPIO_OTG_HS_SOF_2 (GPIO_ALT|GPIO_AF10|GPIO_PORTA|GPIO_PIN14)
/* PSSI - Parallel synchronous slave interface */
@ -1177,4 +1177,4 @@
#define GPIO_USART3_TX_4 (GPIO_ALT|GPIO_AF7|GPIO_PORTC|GPIO_PIN10)
#define GPIO_USART3_TX_5 (GPIO_ALT|GPIO_AF7|GPIO_PORTD|GPIO_PIN8)
#endif /* __ARCH_ARM_SRC_STM32U5_HARDWARE_STM32U585XX_PINMAP_H */
#endif /* __ARCH_ARM_SRC_STM32U5_HARDWARE_STM32U5XX_PINMAP_H */

20
arch/arm/src/stm32u5/hardware/stm32u585xx_rcc.h → arch/arm/src/stm32u5/hardware/stm32u5xx_rcc.h
View file

@ -1,5 +1,5 @@
/****************************************************************************
* arch/arm/src/stm32u5/hardware/stm32u585xx_rcc.h
* arch/arm/src/stm32u5/hardware/stm32u5xx_rcc.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
@ -18,8 +18,8 @@
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32U5_HARDWARE_STM32U585xx_RCC_H
#define __ARCH_ARM_SRC_STM32U5_HARDWARE_STM32U585xx_RCC_H
#ifndef __ARCH_ARM_SRC_STM32U5_HARDWARE_STM32U5xx_RCC_H
#define __ARCH_ARM_SRC_STM32U5_HARDWARE_STM32U5xx_RCC_H
/****************************************************************************
* Included Files
@ -27,7 +27,10 @@
#include <nuttx/config.h>
#if defined(CONFIG_STM32U5_STM32U585XX)
#if defined(CONFIG_STM32U5_STM32U535XX) || defined(CONFIG_STM32U5_STM32U545XX) || \
defined(CONFIG_STM32U5_STM32U575XX) || defined(CONFIG_STM32U5_STM32U585XX) || \
defined(CONFIG_STM32U5_STM32U59XX) || defined(CONFIG_STM32U5_STM32U59AXX) || \
defined(CONFIG_STM32U5_STM32U5A5XX) || defined(CONFIG_STM32U5_STM32U5A9XX)
/****************************************************************************
* Pre-processor Definitions
@ -416,6 +419,7 @@
#define RCC_AHB2ENR1_ADC1EN (1 << 10) /* Bit 10: ADC1 interface enable */
#define RCC_AHB2ENR1_DCMI_PCSSI_EN (1 << 12) /* Bit 12: DCMI and PSSI enable */
#define RCC_AHB2ENR1_OTGEN (1 << 14) /* Bit 14: OTG_FS module enable */
#define RCC_AHB2ENR1_OTGPHYEN (1 << 15) /* Bit 14: OTG_HS module PHY enable */
#define RCC_AHB2ENR1_AESEN (1 << 16) /* Bit 16: AES Cryptographic module enable */
#define RCC_AHB2ENR1_HASHEN (1 << 17) /* Bit 17: HASH module enable */
#define RCC_AHB2ENR1_RNGEN (1 << 18) /* Bit 18: Random number generator module enable */
@ -434,6 +438,8 @@
#define RCC_AHB2ENR2_FSMCEN (1 << 0) /* Bit 0: FSMC clock enable */
#define RCC_AHB2ENR2_OCTOSPI1EN (1 << 4) /* Bit 4: OCTOSPI1 clock enable */
#define RCC_AHB2ENR2_OCTOSPI2EN (1 << 8) /* Bit 8: OCTOSPI2 clock enable */
#define RCC_AHB2ENR2_SRAM6EN (1 << 30) /* Bit 30: SRAM6 clock enable */
#define RCC_AHB2ENR2_SRAM5EN (1 << 31) /* Bit 31: SRAM5 clock enable */
/* RCC AHB3 peripheral clock enable register */
@ -537,7 +543,6 @@
# define RCC_BCDR_LSIPREDIV_NONE 0 /* LSI not divided */
# define RCC_BCDR_LSIPREDIV_128 1 /* LSI divided by 128 */
#if 0
#define RCC_CR_MSIRGSEL (1 << 3) /* Bit 3: MSI clock range selection */
#define RCC_CR_MSIRANGE_SHIFT (4) /* Bits 7-4: MSI clock range */
#define RCC_CR_MSIRANGE_MASK (0x0f << RCC_CR_MSIRANGE_SHIFT)
@ -1246,7 +1251,6 @@
# define RCC_CCIPR2_OSPISEL_SYSCLK (0 << RCC_CCIPR2_OSPISEL_SHIFT)
# define RCC_CCIPR2_OSPISEL_MSI (1 << RCC_CCIPR2_OSPISEL_SHIFT)
# define RCC_CCIPR2_OSPISEL_PLL48M1CLK (2 << RCC_CCIPR2_OSPISEL_SHIFT)
#endif
#endif /* CONFIG_STM32U5_STM32U585XX */
#endif /* __ARCH_ARM_SRC_STM32U5_HARDWARE_STM32U585XX_RCC_H */
#endif /* CONFIG_STM32U5_STM32U5XX */
#endif /* __ARCH_ARM_SRC_STM32U5_HARDWARE_STM32U5XX_RCC_H */

15
arch/arm/src/stm32u5/hardware/stm32u585xx_spi.h → arch/arm/src/stm32u5/hardware/stm32u5xx_spi.h
View file

@ -1,5 +1,5 @@
/****************************************************************************
* arch/arm/src/stm32u5/hardware/stm32u585xx_spi.h
* arch/arm/src/stm32u5/hardware/stm32u5xx_spi.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
@ -18,8 +18,8 @@
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32U5_HARDWARE_STM32U585XX_SPI_H
#define __ARCH_ARM_SRC_STM32U5_HARDWARE_STM32U585XX_SPI_H
#ifndef __ARCH_ARM_SRC_STM32U5_HARDWARE_STM32U5XX_SPI_H
#define __ARCH_ARM_SRC_STM32U5_HARDWARE_STM32U5XX_SPI_H
/****************************************************************************
* Included Files
@ -27,7 +27,10 @@
#include <nuttx/config.h>
#if defined(CONFIG_STM32U5_STM32U585XX)
#if defined(CONFIG_STM32U5_STM32U535XX) || defined(CONFIG_STM32U5_STM32U545XX) || \
defined(CONFIG_STM32U5_STM32U575XX) || defined(CONFIG_STM32U5_STM32U585XX) || \
defined(CONFIG_STM32U5_STM32U59XX) || defined(CONFIG_STM32U5_STM32U59AXX) || \
defined(CONFIG_STM32U5_STM32U5A5XX) || defined(CONFIG_STM32U5_STM32U5A9XX)
/****************************************************************************
* Pre-processor Definitions
@ -403,5 +406,5 @@
#define SPI_UDRDR_UDRDR_MASK (0xffff << SPI_UDRDR_UDRDR_SHIFT)
/* Bits 16-31: read zero */
#endif /* CONFIG_STM32U5_STM32U585XX */
#endif /* __ARCH_ARM_SRC_STM32U5_HARDWARE_STM32U585XX_SPI_H */
#endif /* CONFIG_STM32U5_STM32U5XX ... */
#endif /* __ARCH_ARM_SRC_STM32U5_HARDWARE_STM32U5XX_SPI_H */

15
arch/arm/src/stm32u5/hardware/stm32u585xx_syscfg.h → arch/arm/src/stm32u5/hardware/stm32u5xx_syscfg.h
View file

@ -1,5 +1,5 @@
/****************************************************************************
* arch/arm/src/stm32u5/hardware/stm32u585xx_syscfg.h
* arch/arm/src/stm32u5/hardware/stm32u5xx_syscfg.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
@ -18,8 +18,8 @@
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32U5_HARDWARE_STM32U585XX_SYSCFG_H
#define __ARCH_ARM_SRC_STM32U5_HARDWARE_STM32U585XX_SYSCFG_H
#ifndef __ARCH_ARM_SRC_STM32U5_HARDWARE_STM32U5XX_SYSCFG_H
#define __ARCH_ARM_SRC_STM32U5_HARDWARE_STM32U5XX_SYSCFG_H
/****************************************************************************
* Included Files
@ -28,7 +28,10 @@
#include <nuttx/config.h>
#include "chip.h"
#if defined(CONFIG_STM32U5_STM32U585XX)
#if defined(CONFIG_STM32U5_STM32U535XX) || defined(CONFIG_STM32U5_STM32U545XX) || \
defined(CONFIG_STM32U5_STM32U575XX) || defined(CONFIG_STM32U5_STM32U585XX) || \
defined(CONFIG_STM32U5_STM32U59XX) || defined(CONFIG_STM32U5_STM32U59AXX) || \
defined(CONFIG_STM32U5_STM32U5A5XX) || defined(CONFIG_STM32U5_STM32U5A9XX)
/****************************************************************************
* Pre-processor Definitions
@ -131,5 +134,5 @@
#define SYSCFG_RSSCMDR_SHIFT 0
#define SYSCFG_RSSCMDR_MASK (0xFFFF << SYSCFG_RSSCMDR_SHIFT)
#endif /* CONFIG_STM32U5_STM32U585XX */
#endif /* __ARCH_ARM_SRC_STM32U5_HARDWARE_STM32U585XX_SYSCFG_H */
#endif /* CONFIG_STM32U5_STM32U5XX ... */
#endif /* __ARCH_ARM_SRC_STM32U5_HARDWARE_STM32U5XX_SYSCFG_H */

41
arch/arm/src/stm32u5/stm32_allocateheap.c
View file

@ -94,7 +94,7 @@
/* Set the range of system SRAM */
#define SRAM1_START STM32_SRAM_BASE
#define SRAM1_START STM32_SRAM1_BASE
#define SRAM1_END (SRAM1_START + STM32_SRAM1_SIZE)
/* Set the range of SRAM2 as well, requires a second memory region */
@ -109,6 +109,11 @@
# define SRAM3_END (SRAM3_START + STM32_SRAM3_SIZE)
#endif
#ifdef STM32_SRAM5_SIZE
# define SRAM5_START STM32_SRAM5_BASE
# define SRAM5_END (SRAM3_START + STM32_SRAM5_SIZE)
#endif
/* Some sanity checking. If multiple memory regions are defined, verify
* that CONFIG_MM_REGIONS is set to match the number of memory regions
* that we have been asked to add to the heap.
@ -116,12 +121,14 @@
#if CONFIG_MM_REGIONS < defined(CONFIG_STM32U5_SRAM2_HEAP) + \
defined(CONFIG_STM32U5_SRAM3_HEAP) + \
defined(CONFIG_STM32U5_SRAM5_HEAP) + \
defined(CONFIG_STM32U5_FSMC_SRAM_HEAP) + 1
# error "You need more memory manager regions to support selected heap components"
#endif
#if CONFIG_MM_REGIONS > defined(CONFIG_STM32U5_SRAM2_HEAP) + \
defined(CONFIG_STM32U5_SRAM3_HEAP) + \
defined(CONFIG_STM32U5_SRAM5_HEAP) + \
defined(CONFIG_STM32U5_FSMC_SRAM_HEAP) + 1
# warning "CONFIG_MM_REGIONS large enough but I do not know what some of the region(s) are"
#endif
@ -312,13 +319,13 @@ void arm_addregion(void)
{
#ifdef CONFIG_STM32U5_SRAM2_HEAP
#if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP)
# if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP)
/* Allow user-mode access to the SRAM2 heap */
stm32_mpu_uheap((uintptr_t)SRAM2_START, SRAM2_END - SRAM2_START);
#endif
# endif
/* Colorize the heap for debug */
@ -332,13 +339,13 @@ void arm_addregion(void)
#ifdef CONFIG_STM32U5_SRAM3_HEAP
#if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP)
# if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP)
/* Allow user-mode access to the SRAM3 heap */
stm32_mpu_uheap((uintptr_t)SRAM3_START, SRAM3_END - SRAM3_START);
#endif
# endif
/* Colorize the heap for debug */
@ -350,14 +357,34 @@ void arm_addregion(void)
#endif /* SRAM3 */
#ifdef CONFIG_STM32U5_SRAM5_HEAP
# if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP)
/* Allow user-mode access to the SRAM5 heap */
stm32_mpu_uheap((uintptr_t)SRAM5_START, STM32_SRAM5_SIZE);
# endif
/* Colorize the heap for debug */
up_heap_color((void *)SRAM5_START, STM32_SRAM5_SIZE);
/* Add the SRAM5 user heap region. */
kumm_addregion((void *)SRAM5_START, STM32_SRAM5_SIZE);
#endif /* SRAM5 */
#ifdef CONFIG_STM32U5_FSMC_SRAM_HEAP
#if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP)
# if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP)
/* Allow user-mode access to the FSMC SRAM user heap memory */
stm32_mpu_uheap((uintptr_t)CONFIG_HEAP2_BASE, CONFIG_HEAP2_SIZE);
#endif
# endif
/* Colorize the heap for debug */

4
arch/arm/src/stm32u5/stm32_dbgmcu.h
View file

@ -29,8 +29,8 @@
#include "chip.h"
#if defined(CONFIG_STM32U5_STM32U585XX)
# include "hardware/stm32u585xx_dbgmcu.h"
#if defined(CONFIG_STM32U5_STM32U585XX) || defined(CONFIG_STM32U5_STM32U5A5XX)
# include "hardware/stm32u5xx_dbgmcu.h"
#else
# error "Unsupported STM32U5 chip"
#endif

2
arch/arm/src/stm32u5/stm32_flash.c
View file

@ -49,6 +49,8 @@
#include "arm_internal.h"
#if !defined(CONFIG_STM32U5_STM32U585XX)
#elif !defined(CONFIG_STM32U5_STM32U5A5XX)
#else
# error "Unrecognized STM32 chip"
#endif

2
arch/arm/src/stm32u5/stm32_gpio.h
View file

@ -37,7 +37,7 @@
#include "chip.h"
#if defined(CONFIG_STM32U5_STM32U585XX)
#if defined(CONFIG_STM32U5_STM32U585XX) || defined(CONFIG_STM32U5_STM32U5A5XX)
# include "hardware/stm32_gpio.h"
#else
# error "Unsupported STM32U5 chip"

3078
arch/arm/src/stm32u5/stm32_i2c.c Normal file
View file

File diff suppressed because it is too large Load diff

89
arch/arm/src/stm32u5/stm32_i2c.h Normal file
View file

@ -0,0 +1,89 @@
/****************************************************************************
* arch/arm/src/stm32u5/stm32_i2c.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32U5_STM32L4_I2C_H
#define __ARCH_ARM_SRC_STM32U5_STM32L4_I2C_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <nuttx/i2c/i2c_master.h>
#include "chip.h"
#include "hardware/stm32_i2c.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* If a dynamic timeout is selected, then a non-negative, non-zero micro-
* seconds per byte value must be provided as well.
*/
#ifdef CONFIG_STM32U5_I2C_DYNTIMEO
# if CONFIG_STM32U5_I2C_DYNTIMEO_USECPERBYTE < 1
# warning "Ignoring CONFIG_STM32U5_I2C_DYNTIMEO because of CONFIG_STM32U5_I2C_DYNTIMEO_USECPERBYTE"
# undef CONFIG_STM32U5_I2C_DYNTIMEO
# endif
#endif
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: stm32_i2cbus_initialize
*
* Description:
* Initialize the selected I2C port. And return a unique instance of struct
* struct i2c_master_s. This function may be called to obtain multiple
* instances of the interface, each of which may be set up with a
* different frequency and slave address.
*
* Input Parameters:
* Port number (for hardware that has multiple I2C interfaces)
*
* Returned Value:
* Valid I2C device structure reference on success; a NULL on failure
*
****************************************************************************/
struct i2c_master_s *stm32_i2cbus_initialize(int port);
/****************************************************************************
* Name: stm32_i2cbus_uninitialize
*
* Description:
* De-initialize the selected I2C port, and power down the device.
*
* Input Parameters:
* Device structure as returned by the stm32_i2cbus_initialize()
*
* Returned Value:
* OK on success, ERROR when internal reference count mismatch or dev
* points to invalid hardware device.
*
****************************************************************************/
int stm32_i2cbus_uninitialize(struct i2c_master_s *dev);
#endif /* __ARCH_ARM_SRC_STM32U5_STM32L4_I2C_H */

4
arch/arm/src/stm32u5/stm32_rcc.h
View file

@ -30,8 +30,8 @@
#include "arm_internal.h"
#include "chip.h"
#if defined(CONFIG_STM32U5_STM32U585XX)
# include "hardware/stm32u585xx_rcc.h"
#if defined(CONFIG_STM32U5_STM32U585XX) || defined(CONFIG_STM32U5_STM32U5A5XX)
# include "hardware/stm32u5xx_rcc.h"
#else
# error "Unsupported STM32U5 chip"
#endif

4
arch/arm/src/stm32u5/stm32_start.c
View file

@ -60,8 +60,8 @@
* 0x2003:ffff - End of internal SRAM2
*/
#define SRAM2_START STM32U5_SRAM2_BASE
#define SRAM2_END (SRAM2_START + STM32U5_SRAM2_SIZE)
#define SRAM2_START STM32_SRAM2_BASE
#define SRAM2_END (SRAM2_START + STM32_SRAM2_SIZE)
#define HEAP_BASE ((uintptr_t)_ebss + CONFIG_IDLETHREAD_STACKSIZE)

2
arch/arm/src/stm32u5/stm32_uart.h
View file

@ -30,7 +30,7 @@
#include "chip.h"
#if defined(CONFIG_STM32U5_STM32U585XX)
#if defined(CONFIG_STM32U5_STM32U585XX) || defined(CONFIG_STM32U5_STM32U5A5XX)
# include "hardware/stm32_uart.h"
#else
# error "Unsupported STM32U5 chip"

12
arch/arm/src/stm32u5/stm32u585xx_rcc.c → arch/arm/src/stm32u5/stm32u5xx_rcc.c
View file

@ -1,5 +1,5 @@
/****************************************************************************
* arch/arm/src/stm32u5/stm32u585xx_rcc.c
* arch/arm/src/stm32u5/stm32u5xx_rcc.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
@ -195,10 +195,14 @@ static inline void rcc_enableahb2(void)
regval |= RCC_AHB2ENR1_DCMI_PSSIEN;
#endif
#ifdef CONFIG_STM32U5_OTG
#ifdef CONFIG_STM32U5_OTGHS
regval |= RCC_AHB2ENR1_OTGEN;
#endif
#ifdef CONFIG_STM32U5_OTGHS
regval |= RCC_AHB2ENR1_OTGPHYEN;
#endif
#ifdef CONFIG_STM32U5_AES
regval |= RCC_AHB2ENR1_AESEN;
#endif
@ -263,6 +267,10 @@ static inline void rcc_enableahb2(void)
regval |= RCC_AHB2ENR2_OCTOSPI2EN;
#endif
#ifdef CONFIG_STM32U5_SRAM5
regval |= RCC_AHB2ENR2_SRAM5EN;
#endif
putreg32(regval, STM32_RCC_AHB2ENR2);
}

12
boards/Kconfig
View file

@ -2428,6 +2428,14 @@ config ARCH_BOARD_B_U585I_IOT02A
MCU. The STM32U585AI is a Cortex-M33 optimised for low-power operation
at up to 160MHz operation with 2048Kb Flash memory and 768Kb SRAM.
config ARCH_BOARD_NUCLEO_U5A5ZJ_Q
bool "STMicro NUCLEO-U5A5ZJ-Q board"
depends on ARCH_CHIP_STM32U5A5ZJT
---help---
STMicro development board featuring the STM32U5A5
MCU. The STM32U5A5 is a Cortex-M33 optimised for low-power operation
at up to 160MHz operation with 4MB Flash memory and 2.5MB SRAM.
config ARCH_BOARD_STM32L476VG_DISCO
bool "STMicro STM32L476VG -Discovery board"
depends on ARCH_CHIP_STM32L476RG
@ -3106,6 +3114,7 @@ config ARCH_BOARD
default "b-l072z-lrwan1" if ARCH_BOARD_B_L072Z_LRWAN1
default "b-l475e-iot01a" if ARCH_BOARD_B_L475E_IOT01A
default "b-u585i-iot02a" if ARCH_BOARD_B_U585I_IOT02A
default "nucleo-u5a5zj-q" if ARCH_BOARD_NUCLEO_U5A5ZJ_Q
default "stm32l476vg-disco" if ARCH_BOARD_STM32L476VG_DISCO
default "stm32l476-mdk" if ARCH_BOARD_STM32L476_MDK
default "stm32l4r9ai-disco" if ARCH_BOARD_STM32L4R9AI_DISCO
@ -3570,6 +3579,9 @@ endif
if ARCH_BOARD_B_U585I_IOT02A
source "boards/arm/stm32u5/b-u585i-iot02a/Kconfig"
endif
if ARCH_BOARD_NUCLEO_U5A5ZJ_Q
source "boards/arm/stm32u5/nucleo-u5a5zj-q/Kconfig"
endif
if ARCH_BOARD_NUCLEO_L432KC
source "boards/arm/stm32l4/nucleo-l432kc/Kconfig"
endif

2
boards/arm/stm32u5/b-u585i-iot02a/configs/nsh/defconfig
View file

@ -53,9 +53,7 @@ CONFIG_SCHED_WAITPID=y
CONFIG_STACK_COLORATION=y
CONFIG_STM32U5_PWR=y
CONFIG_STM32U5_SPI1=y
CONFIG_STM32U5_SRAM1=y
CONFIG_STM32U5_SRAM3=y
CONFIG_STM32U5_SRAM4=y
CONFIG_STM32U5_USART1=y
CONFIG_SYSTEM_NSH=y
CONFIG_SYSTEM_SPITOOL=y

8
boards/arm/stm32u5/nucleo-u5a5zj-q/Kconfig Normal file
View file

@ -0,0 +1,8 @@
#
# For a description of the syntax of this configuration file,
# see the file kconfig-language.txt in the NuttX tools repository.
#
if ARCH_BOARD_NUCLEO_U5A5ZJ_Q
endif

88
boards/arm/stm32u5/nucleo-u5a5zj-q/README.txt Normal file
View file

@ -0,0 +1,88 @@
NUCLEO-U5A5ZJ-Q README
======================
This README file discusses the port of NuttX to the STMicroelectronics
NUCLEO-U5A5ZJ-Q board. That board features the STM32U5A5ZJT6Q MCU with 4MiB
of Flash and 2500KiB of SRAM.
Contents
========
- Status
- Serial Console
- Configurations
Status
======
2023-07-16: Initial port - works all ram memory and i2c(not extensively tested)
The i2c driver is based on stm32l4 one
Clock Source
============
Only the low speed external (LSE) 32.768kHz crystal (X2) is installed in
default configurations.
FUNC GPIO
--------- ----
OSC32_IN PC14
OSC32_OUT PC15
--------- ----
Serial Consoles
===============
Virtual COM Port on USART1
--------------------------
Default board is configured to use USART1 as console. USART1 is connected
to the ST-LINKV3E Virtual COM port as well as made available on connector
CN10 (need some rework on PCB).
Pins and Connectors:
FUNC GPIO Connector
Pin NAME
---- ---- ------ --------
TXD: PA9 CN10 14 T.VCP_TX
RXD: PA10 CN9 13 T.VCP_RX
---- ---- ------ --------
Configurations
==============
Information Common to All Configurations
----------------------------------------
There is only one configuration which can be selected as follow:
tools/configure.sh nucleo-u5a5zj-q:nsh
Before building, make sure the PATH environment variable includes the
correct path to the directory than holds your toolchain binaries.
And then build NuttX by simply typing the following. At the conclusion of
the make, the nuttx binary will reside in an ELF file called, simply, nuttx.
make menuconfig
make
The <subdir> that is provided above as an argument to the tools/configure.sh
must be is one of the following.
NOTES:
1. These configurations use the mconf-based configuration tool. To
change any of these configurations using that tool, you should:
a. Build and install the kconfig-mconf tool. See nuttx/README.txt
see additional README.txt files in the NuttX tools repository.
b. Execute 'make menuconfig' in nuttx/ in order to start the
reconfiguration process.
2. All of these configurations are set up to build under Linux using the
"GNU Tools for ARM Embedded Processors" that is maintained by ARM
(unless stated otherwise in the description of the configuration).
https://developer.arm.com/open-source/gnu-toolchain/gnu-rm

70
boards/arm/stm32u5/nucleo-u5a5zj-q/configs/nsh/defconfig Normal file
View file

@ -0,0 +1,70 @@
#
# This file is autogenerated: PLEASE DO NOT EDIT IT.
#
# You can use "make menuconfig" to make any modifications to the installed .config file.
# You can then do "make savedefconfig" to generate a new defconfig file that includes your
# modifications.
#
# CONFIG_NSH_ARGCAT is not set
# CONFIG_NSH_DISABLE_DATE is not set
# CONFIG_STANDARD_SERIAL is not set
CONFIG_ARCH="arm"
CONFIG_ARCH_BOARD="nucleo-u5a5zj-q"
CONFIG_ARCH_BOARD_NUCLEO_U5A5ZJ_Q=y
CONFIG_ARCH_CHIP="stm32u5"
CONFIG_ARCH_CHIP_STM32U5=y
CONFIG_ARCH_CHIP_STM32U5A5ZJT=y
CONFIG_ARCH_INTERRUPTSTACK=2048
CONFIG_ARCH_STACKDUMP=y
CONFIG_ARCH_TRUSTZONE_NONSECURE=y
CONFIG_ARMV8M_USEBASEPRI=y
CONFIG_BOARD_LOOPSPERMSEC=7997
CONFIG_BUILTIN=y
CONFIG_DEBUG_ASSERTIONS=y
CONFIG_DEBUG_ERROR=y
CONFIG_DEBUG_FEATURES=y
CONFIG_DEBUG_INFO=y
CONFIG_DEBUG_SYMBOLS=y
CONFIG_DEBUG_WARN=y
CONFIG_DEFAULT_TASK_STACKSIZE=4096
CONFIG_FS_PROCFS=y
CONFIG_FS_PROCFS_REGISTER=y
CONFIG_INIT_ENTRYNAME="nsh"
CONFIG_INIT_ENTRYPOINT="nsh_main"
CONFIG_INIT_STACKSIZE=2048
CONFIG_INPUT=y
CONFIG_INTELHEX_BINARY=y
CONFIG_LIBM=y
CONFIG_MM_REGIONS=4
CONFIG_NSH_ARCHINIT=y
CONFIG_NSH_BUILTIN_APPS=y
CONFIG_NSH_DISABLE_IFUPDOWN=y
CONFIG_NSH_FILEIOSIZE=512
CONFIG_NSH_LINELEN=64
CONFIG_NSH_READLINE=y
CONFIG_POSIX_SPAWN_DEFAULT_STACKSIZE=2048
CONFIG_PREALLOC_TIMERS=4
CONFIG_PTHREAD_STACK_DEFAULT=2048
CONFIG_RAM_SIZE=131072
CONFIG_RAM_START=0x20000000
CONFIG_RAW_BINARY=y
CONFIG_READLINE_CMD_HISTORY=y
CONFIG_READLINE_TABCOMPLETION=y
CONFIG_RR_INTERVAL=200
CONFIG_SCHED_WAITPID=y
CONFIG_STACK_COLORATION=y
CONFIG_STM32U5_PWR=y
CONFIG_STM32U5_SRAM2=y
CONFIG_STM32U5_SRAM2_HEAP=y
CONFIG_STM32U5_SRAM3=y
CONFIG_STM32U5_SRAM3_HEAP=y
CONFIG_STM32U5_SRAM5=y
CONFIG_STM32U5_SRAM5_HEAP=y
CONFIG_STM32U5_USART1=y
CONFIG_SYSTEM_NSH=y
CONFIG_SYSTEM_NSH_STACKSIZE=2048
CONFIG_SYSTEM_RAMTEST=y
CONFIG_SYSTEM_RAMTEST_STACKSIZE=2048
CONFIG_SYSTEM_TEE=y
CONFIG_TASK_NAME_SIZE=0
CONFIG_USART1_SERIAL_CONSOLE=y

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/****************************************************************************
* boards/arm/stm32u5/nucleo-u5a5zj-q/include/board.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __BOARDS_ARM_STM32U5_NUCLEO_U5A5ZJ_Q_INCLUDE_BOARD_H
#define __BOARDS_ARM_STM32U5_NUCLEO_U5A5ZJ_Q_INCLUDE_BOARD_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stm32_gpio.h>
#ifndef __ASSEMBLY__
# include <stdint.h>
#endif
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Clocking *****************************************************************/
/* The B-U585I-IOT02A board supports both HSE and LSE crystals (X1 and X2).
* However, as shipped, the X1 crystal is not populated. Therefore the board
* will need to run off the 32kHz-sync'ed MSIS.
*
* System Clock source : PLL (MSIS)
* SYSCLK(Hz) : 160000000 Determined by PLL configuration
* HCLK(Hz) : 160000000
* AHB Prescaler : 1 (STM32_RCC_CFGR2_HPRE) (160MHz)
* APB1 Prescaler : 1 (STM32_RCC_CFGR2_PPRE1) (160MHz)
* APB2 Prescaler : 1 (STM32_RCC_CFGR2_PPRE2) (160MHz)
* APB3 Prescaler : 1 (STM32_RCC_CFGR3_PPRE3) (160MHz)
* MSIS Frequency(Hz) : 4000000 (nominal)
* MSIK Frequency(Hz) : 4000000 (nominal)
* PLL_MBOOST : 1 (Embedded power distribution booster)
* PLLM : 1 (STM32_PLLCFG_PLLM)
* PLLN : 80 (STM32_PLLCFG_PLLN)
* PLLP : 2 (STM32_PLLCFG_PLLP)
* PLLQ : 2 (STM32_PLLCFG_PLLQ)
* PLLR : 2 (STM32_PLLCFG_PLLR)
* Flash Latency(WS) : 4
*/
/* HSI - 16 MHz RC factory-trimmed
* LSI - 32 KHz RC
* MSI - 4 MHz, autotrimmed via LSE
* HSE - not installed
* LSE - 32.768 kHz installed
*/
#define STM32_HSI_FREQUENCY 16000000ul
#define STM32_LSI_FREQUENCY 32000
#define STM32_LSE_FREQUENCY 32768
#define STM32_BOARD_USEMSIS 1
#define STM32_BOARD_MSISRANGE RCC_ICSCR1_MSISRANGE_4MHZ
#define STM32_BOARD_MSIKRANGE RCC_ICSCR1_MSIKRANGE_4MHZ
/* PLL1 config; we use this to generate our system clock */
#define STM32_RCC_PLL1CFGR_PLL1M RCC_PLL1CFGR_PLL1M(1)
#define STM32_RCC_PLL1DIVR_PLL1N RCC_PLL1DIVR_PLL1N(80)
#define STM32_RCC_PLL1DIVR_PLL1P 0
#undef STM32_RCC_PLL1CFGR_PLL1P_ENABLED
#define STM32_RCC_PLL1DIVR_PLL1Q 0
#undef STM32_RCC_PLL1CFGR_PLL1Q_ENABLED
#define STM32_RCC_PLL1DIVR_PLL1R RCC_PLL1DIVR_PLL1R(2)
#define STM32_RCC_PLL1CFGR_PLL1R_ENABLED
#define STM32_SYSCLK_FREQUENCY 160000000ul
/* Enable LSE (for the RTC and for MSIS autotrimming) */
#define STM32_USE_LSE 1
/* Configure the HCLK divisor (for the AHB bus, core, memory, and DMA */
#define STM32_RCC_CFGR2_HPRE RCC_CFGR2_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */
#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY
/* Configure the APB1 prescaler */
#define STM32_RCC_CFGR2_PPRE1 RCC_CFGR2_PPRE1_HCLK /* PCLK1 = HCLK / 1 */
#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY / 1)
#define STM32_APB1_TIM2_CLKIN (STM32_PCLK1_FREQUENCY)
#define STM32_APB1_TIM3_CLKIN (STM32_PCLK1_FREQUENCY)
#define STM32_APB1_TIM4_CLKIN (STM32_PCLK1_FREQUENCY)
#define STM32_APB1_TIM5_CLKIN (STM32_PCLK1_FREQUENCY)
#define STM32_APB1_TIM6_CLKIN (STM32_PCLK1_FREQUENCY)
#define STM32_APB1_TIM7_CLKIN (STM32_PCLK1_FREQUENCY)
/* Configure the APB2 prescaler */
#define STM32_RCC_CFGR2_PPRE2 RCC_CFGR2_PPRE2_HCLK /* PCLK2 = HCLK / 1 */
#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY / 1)
#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY)
#define STM32_APB2_TIM15_CLKIN (STM32_PCLK2_FREQUENCY)
#define STM32_APB2_TIM16_CLKIN (STM32_PCLK2_FREQUENCY)
/* Configure the APB3 prescaler */
#define STM32_RCC_CFGR3_PPRE3 RCC_CFGR3_PPRE3_HCLK /* PCLK3 = HCLK / 1 */
#define STM32_PCLK3_FREQUENCY (STM32_HCLK_FREQUENCY / 1)
/* The timer clock frequencies are automatically defined by hardware. If the
* APB prescaler equals 1, the timer clock frequencies are set to the same
* frequency as that of the APB domain. Otherwise they are set to twice.
* Note: TIM1,15,16 are on APB2, others on APB1
*/
#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY
#define BOARD_TIM2_FREQUENCY STM32_HCLK_FREQUENCY
#define BOARD_TIM3_FREQUENCY STM32_HCLK_FREQUENCY
#define BOARD_TIM4_FREQUENCY STM32_HCLK_FREQUENCY
#define BOARD_TIM5_FREQUENCY STM32_HCLK_FREQUENCY
#define BOARD_TIM6_FREQUENCY STM32_HCLK_FREQUENCY
#define BOARD_TIM7_FREQUENCY STM32_HCLK_FREQUENCY
#define BOARD_TIM15_FREQUENCY STM32_HCLK_FREQUENCY
#define BOARD_TIM16_FREQUENCY STM32_HCLK_FREQUENCY
#define BOARD_LPTIM1_FREQUENCY STM32_HCLK_FREQUENCY
#define BOARD_LPTIM2_FREQUENCY STM32_HCLK_FREQUENCY
/* DMA Channel/Stream Selections ********************************************/
/* Alternate function pin selections ****************************************/
/* USART1: Connected to STLink VCP and to CN10 with small rework of pcb. */
#define GPIO_USART1_RX GPIO_USART1_RX_1 /* PA10 */
#define GPIO_USART1_TX GPIO_USART1_TX_1 /* PA9 */
/* SPI1: Arduino Connector CN13 */
#define GPIO_SPI1_NSS (GPIO_OUTPUT|GPIO_SPEED_2MHZ| \
GPIO_PUSHPULL|GPIO_OUTPUT_SET| \
GPIO_PORTE|GPIO_PIN12) /* PE12 */
#define GPIO_SPI1_SCK (GPIO_SPI1_SCK_4|GPIO_SPEED_25MHZ) /* PE13 */
#define GPIO_SPI1_MISO (GPIO_SPI1_MISO_4) /* PE14 */
#define GPIO_SPI1_MOSI (GPIO_SPI1_MOSI_4|GPIO_SPEED_25MHZ) /* PE15 */
#define GPIO_I2C1_SCL GPIO_I2C1_SCL_2 | GPIO_SPEED_50MHZ | GPIO_OPENDRAIN
#define GPIO_I2C1_SDA GPIO_I2C1_SDA_2 | GPIO_SPEED_50MHZ | GPIO_OPENDRAIN
#define GPIO_I2C2_SCL GPIO_I2C2_SCL_4 | GPIO_SPEED_50MHZ | GPIO_OPENDRAIN
#define GPIO_I2C2_SDA GPIO_I2C2_SDA_4 | GPIO_SPEED_50MHZ | GPIO_OPENDRAIN
/****************************************************************************
* Public Data
****************************************************************************/
#ifndef __ASSEMBLY__
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: stm32_board_initialize
*
* Description:
* All STM32 architectures must provide the following entry point.
* This entry point is called early in the initialization -- after all
* memory has been configured and mapped but before any devices
* have been initialized.
*
****************************************************************************/
void stm32_board_initialize(void);
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __BOARDS_ARM_STM32U5_NUCLEO_U5A5ZJ_Q_INCLUDE_BOARD_H */

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##############################################################################
# boards/arm/stm32u5/b-u585i-iot02a/scripts/Make.defs
#
# Licensed to the Apache Software Foundation (ASF) under one or more
# contributor license agreements. See the NOTICE file distributed with
# this work for additional information regarding copyright ownership. The
# ASF licenses this file to you under the Apache License, Version 2.0 (the
# "License"); you may not use this file except in compliance with the
# License. You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
# License for the specific language governing permissions and limitations
# under the License.
#
##############################################################################
include ${TOPDIR}/.config
include ${TOPDIR}/tools/Config.mk
include ${TOPDIR}/arch/arm/src/armv8-m/Toolchain.defs
ARCHSCRIPT = $(BOARD_DIR)$(DELIM)scripts$(DELIM)flash.ld
ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10
CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -pipe
CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS)
CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -pipe
CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS)
CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS)
AFLAGS := $(CFLAGS) -D__ASSEMBLY__
NXFLATLDFLAGS1 = -r -d -warn-common
NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)$(DELIM)binfmt$(DELIM)libnxflat$(DELIM)gnu-nxflat-pcrel.ld -no-check-sections
LDNXFLATFLAGS = -e main -s 2048

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/****************************************************************************
* boards/arm/stm32u5/nucleo-u5a5zj-q/scripts/flash.ld
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/* The STM32Uxx has 4 MiB of FLASH beginning at address 0x0800:0000 and
* 768 KiB of SRAM beginning at address 0x2000:0000. When booting from
* FLASH, FLASH memory is aliased to address 0x0000:0000 where the code
* expects to begin execution by jumping to the entry point in the
* 0x0800:0000 address range.
*/
MEMORY
{
flash (rx) : ORIGIN = 0x08000000, LENGTH = 4096K
sram (rwx) : ORIGIN = 0x20000000, LENGTH = 768K
}
OUTPUT_ARCH(arm)
ENTRY(_stext)
SECTIONS
{
.text : {
_stext = ABSOLUTE(.);
*(.vectors)
*(.text .text.*)
*(.fixup)
*(.gnu.warning)
*(.rodata .rodata.*)
*(.gnu.linkonce.t.*)
*(.glue_7)
*(.glue_7t)
*(.got)
*(.gcc_except_table)
*(.gnu.linkonce.r.*)
_etext = ABSOLUTE(.);
} > flash
.init_section : {
_sinit = ABSOLUTE(.);
*(.init_array .init_array.*)
_einit = ABSOLUTE(.);
} > flash
.ARM.extab : {
*(.ARM.extab*)
} > flash
__exidx_start = ABSOLUTE(.);
.ARM.exidx : {
*(.ARM.exidx*)
} > flash
__exidx_end = ABSOLUTE(.);
_eronly = ABSOLUTE(.);
.data : {
_sdata = ABSOLUTE(.);
*(.data .data.*)
*(.gnu.linkonce.d.*)
CONSTRUCTORS
. = ALIGN(4);
_edata = ABSOLUTE(.);
} > sram AT > flash
.bss : {
_sbss = ABSOLUTE(.);
*(.bss .bss.*)
*(.gnu.linkonce.b.*)
*(COMMON)
. = ALIGN(4);
_ebss = ABSOLUTE(.);
} > sram
/* Stabs debugging sections. */
.stab 0 : { *(.stab) }
.stabstr 0 : { *(.stabstr) }
.stab.excl 0 : { *(.stab.excl) }
.stab.exclstr 0 : { *(.stab.exclstr) }
.stab.index 0 : { *(.stab.index) }
.stab.indexstr 0 : { *(.stab.indexstr) }
.comment 0 : { *(.comment) }
.debug_abbrev 0 : { *(.debug_abbrev) }
.debug_info 0 : { *(.debug_info) }
.debug_line 0 : { *(.debug_line) }
.debug_pubnames 0 : { *(.debug_pubnames) }
.debug_aranges 0 : { *(.debug_aranges) }
}

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boards/arm/stm32u5/nucleo-u5a5zj-q/scripts/tfm-ns.ld Normal file
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/****************************************************************************
* boards/arm/stm32u5/b-u585i-iot02a/scripts/tfm-ns.ld
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/* This linker script supports running NuttX in the 'Non-Secure' (ns) domain
* in conjunction with TrustedFirmware-M (tfm).
*
* NuttX will run as the 'Non secure application' in the 'Non-Secure image
* primary primary slot Area 1' in internal flash. Compare [UM2851],
* Figure 7. Furthermore, see Figure 18 for the SRAM1 area used for 'Non-
* Secure application volatile data'
*
* While the 'Non-Secure Image primary slot Area 1' is actually 640KiB large
* in the referenced setup, the image will be enriched with a header of 0x400
* bytes and a trailer of 0x2000 bytes. Thus the 'flash' statement in the
* MEMORY definition below.
*
* References
* [UM2851] STMicroelectronics. UM2851: Getting started with STM32CubeU5 TFM
* application, Rev 1, June 2021
*/
MEMORY
{
flash (rx) : ORIGIN = 0x08052400, LENGTH = 0x9DC00
sram (rwx) : ORIGIN = 0x20000000, LENGTH = 192K
}
OUTPUT_ARCH(arm)
ENTRY(_stext)
SECTIONS
{
.text : {
_stext = ABSOLUTE(.);
*(.vectors)
*(.text .text.*)
*(.fixup)
*(.gnu.warning)
*(.rodata .rodata.*)
*(.gnu.linkonce.t.*)
*(.glue_7)
*(.glue_7t)
*(.got)
*(.gcc_except_table)
*(.gnu.linkonce.r.*)
_etext = ABSOLUTE(.);
} > flash
.init_section : {
_sinit = ABSOLUTE(.);
*(.init_array .init_array.*)
_einit = ABSOLUTE(.);
} > flash
.ARM.extab : {
*(.ARM.extab*)
} > flash
__exidx_start = ABSOLUTE(.);
.ARM.exidx : {
*(.ARM.exidx*)
} > flash
__exidx_end = ABSOLUTE(.);
_eronly = ABSOLUTE(.);
.data : {
_sdata = ABSOLUTE(.);
*(.data .data.*)
*(.gnu.linkonce.d.*)
CONSTRUCTORS
. = ALIGN(4);
_edata = ABSOLUTE(.);
} > sram AT > flash
.bss : {
_sbss = ABSOLUTE(.);
*(.bss .bss.*)
*(.gnu.linkonce.b.*)
*(COMMON)
. = ALIGN(4);
_ebss = ABSOLUTE(.);
} > sram
/* Stabs debugging sections. */
.stab 0 : { *(.stab) }
.stabstr 0 : { *(.stabstr) }
.stab.excl 0 : { *(.stab.excl) }
.stab.exclstr 0 : { *(.stab.exclstr) }
.stab.index 0 : { *(.stab.index) }
.stab.indexstr 0 : { *(.stab.indexstr) }
.comment 0 : { *(.comment) }
.debug_abbrev 0 : { *(.debug_abbrev) }
.debug_info 0 : { *(.debug_info) }
.debug_line 0 : { *(.debug_line) }
.debug_pubnames 0 : { *(.debug_pubnames) }
.debug_aranges 0 : { *(.debug_aranges) }
}

38
boards/arm/stm32u5/nucleo-u5a5zj-q/src/Makefile Normal file
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##############################################################################
# boards/arm/stm32u5/nucleo-u5a5zj-q/src/Makefile
#
# Licensed to the Apache Software Foundation (ASF) under one or more
# contributor license agreements. See the NOTICE file distributed with
# this work for additional information regarding copyright ownership. The
# ASF licenses this file to you under the Apache License, Version 2.0 (the
# "License"); you may not use this file except in compliance with the
# License. You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
# License for the specific language governing permissions and limitations
# under the License.
#
##############################################################################
-include $(TOPDIR)/Make.defs
ASRCS =
CSRCS = stm32_boot.c stm32_bringup.c stm32_spi.c
ifeq ($(CONFIG_BOARDCTL),y)
CSRCS += stm32_appinit.c
endif
ifeq ($(CONFIG_ARCH_BOARD_STM32U5_CUSTOM_CLOCKCONFIG),y)
CSRCS += stm32_clockconfig.c
endif
ifeq ($(CONFIG_USBDEV),y)
CSRCS += stm32_usb.c
endif
include $(TOPDIR)/boards/Board.mk

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boards/arm/stm32u5/nucleo-u5a5zj-q/src/nucleo-u5a5zj-q.h Normal file
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/****************************************************************************
* boards/arm/stm32u5/nucleo-u5a5zj-q/src/nucleo-u5a5zj-q.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __BOARDS_ARM_STM32U5_NUCLEO_U5A5ZJ_Q_SRC_NUCLEO_U5A5ZJ_Q_H
#define __BOARDS_ARM_STM32U5_NUCLEO_U5A5ZJ_Q_SRC_NUCLEO_U5A5ZJ_Q_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <nuttx/compiler.h>
#include <stdint.h>
#include "stm32_gpio.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Configuration ************************************************************/
#define HAVE_PROC 1
#define HAVE_RTC_DRIVER 1
#if !defined(CONFIG_FS_PROCFS)
# undef HAVE_PROC
#endif
#if defined(HAVE_PROC) && defined(CONFIG_DISABLE_MOUNTPOINT)
# warning Mountpoints disabled. No procfs support
# undef HAVE_PROC
#endif
/* Check if we can support the RTC driver */
#if !defined(CONFIG_RTC) || !defined(CONFIG_RTC_DRIVER)
# undef HAVE_RTC_DRIVER
#endif
/****************************************************************************
* Public Types
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
#ifndef __ASSEMBLY__
/****************************************************************************
* Public Function Declarations
****************************************************************************/
/****************************************************************************
* Name: stm32_spidev_initialize
*
* Description:
* Called to configure SPI chip select GPIO pins.
*
****************************************************************************/
#ifdef CONFIG_SPI
void stm32_spidev_initialize(void);
#endif
/****************************************************************************
* Name: stm32_bringup
*
* Description:
* Perform architecture-specific initialization
*
* CONFIG_BOARD_LATE_INITIALIZE=y :
* Called from board_late_initialize().
*
* CONFIG_BOARD_LATE_INITIALIZE=n && CONFIG_BOARDCTL=y :
* Called from the NSH library
*
****************************************************************************/
int stm32_bringup(void);
#endif /* __ASSEMBLY__ */
#endif /* __BOARDS_ARM_STM32U5_NUCLEO_U5A5ZJ_Q_SRC_NUCLEO_U5A5ZJ_Q_H */

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/****************************************************************************
* boards/arm/stm32u5/nucleo-u5a5zj-q/src/stm32_appinit.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include "nucleo-u5a5zj-q.h"
#include <nuttx/board.h>
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: board_app_initialize
*
* Description:
* Perform application specific initialization. This function is never
* called directly from application code, but only indirectly via the
* (non-standard) boardctl() interface using the command BOARDIOC_INIT.
*
* Input Parameters:
* arg - The boardctl() argument is passed to the board_app_initialize()
* implementation without modification. The argument has no
* meaning to NuttX; the meaning of the argument is a contract
* between the board-specific initialization logic and the
* matching application logic. The value cold be such things as a
* mode enumeration value, a set of DIP switch switch settings, a
* pointer to configuration data read from a file or serial FLASH,
* or whatever you would like to do with it. Every implementation
* should accept zero/NULL as a default configuration.
*
* Returned Value:
* Zero (OK) is returned on success; a negated errno value is returned on
* any failure to indicate the nature of the failure.
*
****************************************************************************/
int board_app_initialize(uintptr_t arg)
{
/* Did we already initialize via board_late_initialize()? */
#ifndef CONFIG_BOARD_LATE_INITIALIZE
return stm32_bringup();
#else
return OK;
#endif
}

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/****************************************************************************
* boards/arm/stm32u5/nucleo-u5a5zj-q/src/stm32_boot.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <debug.h>
#include <nuttx/board.h>
#include "arm_internal.h"
#include "nucleo-u5a5zj-q.h"
#include <arch/board/board.h>
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: stm32_board_initialize
*
* Description:
* All STM32 architectures must provide the following entry point. This
* entry point is called early in the initialization -- after all memory
* has been configured and mapped but before any devices have been
* initialized.
*
****************************************************************************/
void stm32_board_initialize(void)
{
#ifdef CONFIG_SPI
/* Configure SPI chip selects */
stm32_spidev_initialize();
#endif
}
/****************************************************************************
* Name: board_late_initialize
*
* Description:
* If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional
* initialization call will be performed in the boot-up sequence to a
* function called board_late_initialize(). board_late_initialize() will
* be called immediately after up_initialize() is called and just before
* the initial application is started. This additional initialization
* phase may be used, for example, to initialize board-specific device
* drivers.
*
****************************************************************************/
#ifdef CONFIG_BOARD_LATE_INITIALIZE
void board_late_initialize(void)
{
/* Perform board-specific initialization here if so configured */
stm32_bringup();
}
#endif

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/****************************************************************************
* boards/arm/stm32u5/nucleo-u5a5zj-q/src/stm32_bringup.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <sys/mount.h>
#include <sys/types.h>
#include <debug.h>
#include <nuttx/input/buttons.h>
#include <nuttx/leds/userled.h>
#include <nuttx/spi/spi_transfer.h>
#include <nuttx/board.h>
#include <nuttx/clock.h>
#include "nucleo-u5a5zj-q.h"
#include <arch/board/board.h>
#include <stm32_spi.h>
#if defined(CONFIG_I2C)
#include "stm32_i2c.h"
FAR struct i2c_master_s *i2c1_m;
FAR struct i2c_master_s *i2c2_m;
# ifdef CONFIG_RTC_DSXXXX
# include <nuttx/timers/rtc.h>
# include <nuttx/timers/ds3231.h>
# endif /* CONFIG_RTC_DSXXXX */
#endif /* CONFIG_I2C */
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#define DEVNO_ZERO 0
#define DEVNO_ONE 1
#define DEVNO_TWO 2
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Should not be here, but there is a bug in clock_initalize logic that
* prevents external RTC to be used when no internal RTC !
* **************************************************************************/
#if defined(CONFIG_RTC) && defined(CONFIG_RTC_EXTERNAL)
int up_rtc_initialize(void)
{
return OK;
}
#endif
/****************************************************************************
* Name: stm32_bringup
*
* Description:
* Perform architecture-specific initialization
*
* CONFIG_BOARD_LATE_INITIALIZE=y :
* Called from board_late_initialize().
*
* CONFIG_BOARD_LATE_INITIALIZE=n && CONFIG_BOARDCTL=y :
* Called from the NSH library
*
****************************************************************************/
int stm32_bringup(void)
{
int ret;
#ifdef CONFIG_FS_PROCFS
/* Mount the procfs file system */
ret = mount(NULL, "/proc", "procfs", 0, NULL);
if (ret < 0)
{
ferr("ERROR: Failed to mount procfs at /proc: %d\n", ret);
}
#endif
#if defined(CONFIG_I2C)
i2c1_m = stm32_i2cbus_initialize(1);
if (i2c1_m == NULL)
{
syslog(LOG_ERR, "ERROR: Failed to init i2c controller\n");
return(-1);
}
ret = i2c_register(i2c1_m, DEVNO_ONE);
if (ret < 0)
{
syslog(LOG_ERR, "ERROR: Failed to register I2C%d driver: %d\n",
DEVNO_ONE, ret);
stm32_i2cbus_uninitialize(i2c1_m);
return -1;
}
#if defined(STM32U5_I2C2)
i2c2_m = stm32_i2cbus_initialize(2);
if (i2c2_m == NULL)
{
syslog(LOG_ERR, "ERROR: Failed to init i2c controller\n");
return(-1);
}
ret = i2c_register(i2c2_m, DEVNO_TWO);
if (ret < 0)
{
syslog(LOG_ERR, "ERROR: Failed to register I2C%d driver: %d\n",
DEVNO_TWO, ret);
stm32_i2cbus_uninitialize(i2c1_m);
stm32_i2cbus_uninitialize(i2c2_m);
return -1;
}
#endif /* STM32_I2C2 */
#endif /* CONFIG_I2C */
#if defined(CONFIG_RTC) && defined(CONFIG_RTC_EXTERNAL) && defined(CONFIG_RTC_DSXXXX)
ret = dsxxxx_rtc_initialize(i2c1_m);
if (ret < 0)
{
syslog(LOG_ERR, "ERROR: dsxxxx_rtc_initialize() failed: %d\n", ret);
}
else
{
/* Synchronize the system time to the RTC time */
syslog(LOG_INFO, "INFO: clock sync\n");
clock_synchronize(NULL);
}
#endif /* CONFIG_RTC */
UNUSED(ret);
return OK;
}

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/****************************************************************************
* boards/arm/stm32u5/nucleo-u5a5zj-q/src/stm32_clockconfig.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: stm32_board_clockconfig
*
* Description:
* Currently the B-U585I-IOT02A board support is restricted to running
* NuttX in the Non-Secure domain together with TrustedFirmware-M (TFM).
* In this setup the clock configuration is done by TFM, not by NuttX.
* Thus, the board's configuration sets
* CONFIG_ARCH_BOARD_STM32L5_CUSTOM_CLOCKCONFIG to avoid the standard clock
* config logic to run and instead do just nothing in this function.
*
****************************************************************************/
#if defined(CONFIG_ARCH_BOARD_STM32U5_CUSTOM_CLOCKCONFIG)
void stm32_board_clockconfig(void)
{
}
#endif

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/****************************************************************************
* boards/arm/stm32u5/nucleo-u5a5zj-q/src/stm32_spi.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <stdbool.h>
#include <errno.h>
#include <debug.h>
#include <nuttx/spi/spi.h>
#include "arm_internal.h"
#include "chip.h"
#include "stm32_gpio.h"
#include "stm32_spi.h"
#include "nucleo-u5a5zj-q.h"
#include <arch/board/board.h>
#ifdef CONFIG_STM32U5_SPI
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: stm32_spidev_initialize
*
* Description:
* Called to configure SPI chip select GPIO pins for the B-U585I-IOT02A
* board.
*
****************************************************************************/
void stm32_spidev_initialize(void)
{
/* NOTE: Clocking for SPI1 and/or SPI3 was already provided in stm32_rcc.c.
* Configurations of SPI pins is performed in stm32_spi.c.
* Here, we only initialize chip select pins unique to the board
* architecture.
*/
#ifdef CONFIG_STM32U5_SPI1
stm32_configgpio(GPIO_SPI1_NSS);
#endif
}
/****************************************************************************
* Name: stm32_spi1/2/3/4/5select and stm32_spi1/2/3/4/5status
*
* Description:
* The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status
* must be provided by board-specific logic. They are implementations of
* the select and status methods of the SPI interface defined by struct
* spi_ops_s (see include/nuttx/spi/spi.h). All other methods (including
* stm32_spibus_initialize()) are provided by common STM32 logic. To use
* this common SPI logic on your board:
*
* 1. Provide logic in stm32_boardinitialize() to configure SPI chip select
* pins.
* 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() functions
* in your board-specific logic. These functions will perform chip
* selection and status operations using GPIOs in the way your board is
* configured.
* 3. Add a calls to stm32_spibus_initialize() in your low level
* application initialization logic
* 4. The handle returned by stm32_spibus_initialize() may then be used
* to bind the SPI driver to higher level logic (e.g., calling
* mmcsd_spislotinitialize(), for example, will bind the SPI driver to
* the SPI MMC/SD driver).
*
****************************************************************************/
#ifdef CONFIG_STM32U5_SPI1
void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid,
bool selected)
{
spiinfo("devid: %08lx CS: %s\n",
(unsigned long)devid, selected ? "assert" : "de-assert");
stm32_gpiowrite(GPIO_SPI1_NSS, !selected);
}
uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid)
{
return 0;
}
#endif
#ifdef CONFIG_STM32U5_SPI2
void stm32_spi2select(struct spi_dev_s *dev, uint32_t devid,
bool selected)
{
spiinfo("devid: %08lx CS: %s\n",
(unsigned long)devid, selected ? "assert" : "de-assert");
}
uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid)
{
return 0;
}
#endif
#ifdef CONFIG_STM32U5_SPI3
void stm32_spi3select(struct spi_dev_s *dev, uint32_t devid,
bool selected)
{
spiinfo("devid: %08lx CS: %s\n",
(unsigned long)devid, selected ? "assert" : "de-assert");
}
uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid)
{
return 0;
}
#endif
/****************************************************************************
* Name: stm32_spi1cmddata
*
* Description:
* This function must be provided by platform-specific logic. This is an
* implementation of the cmddata method of the SPI interface defined by
* struct spi_ops_s (see include/nuttx/spi/spi.h).
*
* Input Parameters:
*
* spi - SPI device that controls the bus the device that requires the CMD/
* DATA selection.
* devid - If there are multiple devices on the bus, this selects which one
* to select cmd or data. NOTE: This design restricts, for example,
* one one SPI display per SPI bus.
* cmd - true: select command; false: select data
*
* Returned Value:
* None
*
****************************************************************************/
#ifdef CONFIG_SPI_CMDDATA
#ifdef CONFIG_STM32U5_SPI1
int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd)
{
return -ENODEV;
}
#endif
#ifdef CONFIG_STM32U5_SPI2
int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd)
{
return -ENODEV;
}
#endif
#ifdef CONFIG_STM32U5_SPI3
int stm32_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd)
{
return -ENODEV;
}
#endif
#endif /* CONFIG_SPI_CMDDATA */
#endif /* CONFIG_STM32U5_SPI */