forked from nuttx/nuttx-update
1.arch/arm/src/stm32/stm32_rtcounter.c up_rtc_initialize Possible stall
2.arch/arm/src/stm32/stm32_rtcounter.c up_rtc_settime memory hardfault
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6a4495e3b7
commit
f0107683d5
1 changed files with 43 additions and 28 deletions
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@ -171,6 +171,30 @@ volatile bool g_rtc_enabled = false;
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* Private Functions
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****************************************************************************/
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/****************************************************************************
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* Name: stm32_rtc_waitlasttask
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*
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* Description:
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* wait task done
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*
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* Input Parameters:
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* None
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*
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* Returned Value:
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* None
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*
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****************************************************************************/
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static inline void stm32_rtc_waitlasttask(void)
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{
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/* Previous write is done? */
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while ((getreg16(STM32_RTC_CRL) & RTC_CRL_RTOFF) == 0)
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{
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stm32_waste();
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}
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}
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/****************************************************************************
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* Name: stm32_rtc_beginwr
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*
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@ -187,12 +211,7 @@ volatile bool g_rtc_enabled = false;
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static inline void stm32_rtc_beginwr(void)
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{
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/* Previous write is done? */
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while ((getreg16(STM32_RTC_CRL) & RTC_CRL_RTOFF) == 0)
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{
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stm32_waste();
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}
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stm32_rtc_waitlasttask();
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/* Enter Config mode, Set Value and Exit */
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@ -216,13 +235,7 @@ static inline void stm32_rtc_beginwr(void)
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static inline void stm32_rtc_endwr(void)
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{
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modifyreg16(STM32_RTC_CRL, RTC_CRL_CNF, 0);
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/* Wait for the write to actually reach RTC registers */
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while ((getreg16(STM32_RTC_CRL) & RTC_CRL_RTOFF) == 0)
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{
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stm32_waste();
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}
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stm32_rtc_waitlasttask();
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}
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/****************************************************************************
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@ -384,6 +397,15 @@ int up_rtc_initialize(void)
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putreg16(RTC_MAGIC, RTC_MAGIC_REG);
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}
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modifyreg16(STM32_RCC_BDCR, 0, RCC_BDCR_LSEON);
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/* Wait for the LSE clock to be ready */
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while ((getreg16(STM32_RCC_BDCR) & RCC_BDCR_LSERDY) == 0)
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{
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stm32_waste();
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}
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/* Select the lower power external 32,768Hz (Low-Speed External, LSE)
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* oscillator as RTC Clock Source and enable the Clock.
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*/
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@ -393,12 +415,10 @@ int up_rtc_initialize(void)
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/* Enable RTC and wait for RSF */
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modifyreg16(STM32_RCC_BDCR, 0, RCC_BDCR_RTCEN);
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/* TODO: Possible stall?
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* should we set the timeout period? and return with -1
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*/
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stm32_rtc_waitlasttask();
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stm32_rtc_wait4rsf();
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stm32_rtc_waitlasttask();
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/* Configure prescaler, note that these are write-only registers */
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@ -408,6 +428,7 @@ int up_rtc_initialize(void)
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stm32_rtc_endwr();
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stm32_rtc_wait4rsf();
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stm32_rtc_waitlasttask();
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#ifdef CONFIG_RTC_HIRES
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/* Enable overflow interrupt - alarm interrupt is enabled in
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@ -631,7 +652,6 @@ int up_rtc_settime(const struct timespec *tp)
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{
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struct rtc_regvals_s regvals;
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irqstate_t flags;
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uint16_t cntl;
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/* Break out the time values */
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@ -646,16 +666,11 @@ int up_rtc_settime(const struct timespec *tp)
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* register (hi-res mode only)
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*/
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do
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{
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stm32_rtc_beginwr();
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putreg16(RTC_MAGIC, RTC_MAGIC_TIME_SET);
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putreg16(regvals.cnth, STM32_RTC_CNTH);
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putreg16(regvals.cntl, STM32_RTC_CNTL);
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cntl = getreg16(STM32_RTC_CNTL);
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stm32_rtc_endwr();
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}
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while (cntl != regvals.cntl);
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stm32_rtc_beginwr();
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putreg16(regvals.cnth, STM32_RTC_CNTH);
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putreg16(regvals.cntl, STM32_RTC_CNTL);
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stm32_rtc_endwr();
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putreg16(RTC_MAGIC_TIME_SET, RTC_MAGIC_REG);
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#ifdef CONFIG_RTC_HIRES
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putreg16(regvals.ovf, RTC_TIMEMSB_REG);
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