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1.arch/arm/src/stm32/stm32_rtcounter.c   up_rtc_initialize Possible stall

2.arch/arm/src/stm32/stm32_rtcounter.c up_rtc_settime memory hardfault
This commit is contained in:
lpxiao 2023-07-05 22:17:53 +08:00 committed by Xiang Xiao
parent 6a4495e3b7
commit f0107683d5

View file

@ -171,6 +171,30 @@ volatile bool g_rtc_enabled = false;
* Private Functions
****************************************************************************/
/****************************************************************************
* Name: stm32_rtc_waitlasttask
*
* Description:
* wait task done
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
static inline void stm32_rtc_waitlasttask(void)
{
/* Previous write is done? */
while ((getreg16(STM32_RTC_CRL) & RTC_CRL_RTOFF) == 0)
{
stm32_waste();
}
}
/****************************************************************************
* Name: stm32_rtc_beginwr
*
@ -187,12 +211,7 @@ volatile bool g_rtc_enabled = false;
static inline void stm32_rtc_beginwr(void)
{
/* Previous write is done? */
while ((getreg16(STM32_RTC_CRL) & RTC_CRL_RTOFF) == 0)
{
stm32_waste();
}
stm32_rtc_waitlasttask();
/* Enter Config mode, Set Value and Exit */
@ -216,13 +235,7 @@ static inline void stm32_rtc_beginwr(void)
static inline void stm32_rtc_endwr(void)
{
modifyreg16(STM32_RTC_CRL, RTC_CRL_CNF, 0);
/* Wait for the write to actually reach RTC registers */
while ((getreg16(STM32_RTC_CRL) & RTC_CRL_RTOFF) == 0)
{
stm32_waste();
}
stm32_rtc_waitlasttask();
}
/****************************************************************************
@ -384,6 +397,15 @@ int up_rtc_initialize(void)
putreg16(RTC_MAGIC, RTC_MAGIC_REG);
}
modifyreg16(STM32_RCC_BDCR, 0, RCC_BDCR_LSEON);
/* Wait for the LSE clock to be ready */
while ((getreg16(STM32_RCC_BDCR) & RCC_BDCR_LSERDY) == 0)
{
stm32_waste();
}
/* Select the lower power external 32,768Hz (Low-Speed External, LSE)
* oscillator as RTC Clock Source and enable the Clock.
*/
@ -393,12 +415,10 @@ int up_rtc_initialize(void)
/* Enable RTC and wait for RSF */
modifyreg16(STM32_RCC_BDCR, 0, RCC_BDCR_RTCEN);
/* TODO: Possible stall?
* should we set the timeout period? and return with -1
*/
stm32_rtc_waitlasttask();
stm32_rtc_wait4rsf();
stm32_rtc_waitlasttask();
/* Configure prescaler, note that these are write-only registers */
@ -408,6 +428,7 @@ int up_rtc_initialize(void)
stm32_rtc_endwr();
stm32_rtc_wait4rsf();
stm32_rtc_waitlasttask();
#ifdef CONFIG_RTC_HIRES
/* Enable overflow interrupt - alarm interrupt is enabled in
@ -631,7 +652,6 @@ int up_rtc_settime(const struct timespec *tp)
{
struct rtc_regvals_s regvals;
irqstate_t flags;
uint16_t cntl;
/* Break out the time values */
@ -646,16 +666,11 @@ int up_rtc_settime(const struct timespec *tp)
* register (hi-res mode only)
*/
do
{
stm32_rtc_beginwr();
putreg16(RTC_MAGIC, RTC_MAGIC_TIME_SET);
putreg16(regvals.cnth, STM32_RTC_CNTH);
putreg16(regvals.cntl, STM32_RTC_CNTL);
cntl = getreg16(STM32_RTC_CNTL);
stm32_rtc_endwr();
}
while (cntl != regvals.cntl);
stm32_rtc_beginwr();
putreg16(regvals.cnth, STM32_RTC_CNTH);
putreg16(regvals.cntl, STM32_RTC_CNTL);
stm32_rtc_endwr();
putreg16(RTC_MAGIC_TIME_SET, RTC_MAGIC_REG);
#ifdef CONFIG_RTC_HIRES
putreg16(regvals.ovf, RTC_TIMEMSB_REG);