forked from nuttx/nuttx-update
STM32F7: Completes architecture support for the STM32 F72x and F73x families. Adds support for the Nucleo-144 boards with STM32F722.
This commit is contained in:
Bob Feretich
Gregory Nutt
parent
d7bb824c69
commit
fab5faf097
18 changed files with 387 additions and 38 deletions
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@ -1,9 +1,10 @@
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/************************************************************************************
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* arch/arm/include/stm32f7/chip.h
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*
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* Copyright (C) 2015-2016 Gregory Nutt. All rights reserved.
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* Copyright (C) 2015-2017 Gregory Nutt. All rights reserved.
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* Authors: Gregory Nutt <gnutt@nuttx.org>
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* David Sidrane <david_s5@nscdg.com>
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* Bob Feretich <bob.feretich@rafresearch.com>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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@ -46,13 +47,23 @@
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/************************************************************************************
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* Pre-processor Definitions
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************************************************************************************/
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/* STM32F745xx, STM32F746xx, STM32F756xx, STM32F765xx, STM32F767xx, STM32F768xx,
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/* STM32F722xx, STM32F723xx,
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* STM32F745xx, STM32F746xx, STM32F756xx, STM32F765xx, STM32F767xx, STM32F768xx,
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* STM32F769xx, STM32F777xx and STM32F779xx Differences between family members:
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*
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* ----------- ---------------- ----- ---- ----- ---- ---- ---- ---- ---- ----- ----- ---- ------------ ------
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* SPI ADC LCD
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* PART PACKAGE GPIOs I2S CHAN TFT MIPI JPEG CAN ETH DFSDM CRYPTO FPU RAM L1
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* ----------- ---------------- ----- ---- ----- ---- ---- ---- ---- ---- ----- ----- ---- ------------ ------
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* STM32F722Rx LQFP64 50 3/3 16 No No No 1 No No No SFPU (176+16+64) 8+8
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* STM32F722Vx LQFP100 82 4/3 16 No No No 1 No No No SFPU (176+16+64) 8+8
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* STM32F722Zx LQFP144 114 5/3 24 No No No 1 No No No SFPU (176+16+64) 8+8
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* STM32F722Ix UFBGA176/LQFP176 140 5/3 24 No No No 1 No No No SFPU (176+16+64) 8+8
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*
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* STM32F723Vx WLCSP100 79 4/3 16 No No No 1 No No No SFPU (176+16+64) 8+8
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* STM32F723Zx UFBGA144/LQFP144 112 5/3 24 No No No 1 No No No SFPU (176+16+64) 8+8
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* STM32F723Ix UFBGA176/LQFP176 138 5/3 24 No No No 1 No No No SFPU (176+16+64) 8+8
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*
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* STM32F745Vx LQFP100 82 4/3 16 No No No 2 Yes No No SFPU (240+16+64) 4+4
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* STM32F745Zx WLCSP143/LQFP144 114 6/3 24 No No No 2 Yes No No SFPU (240+16+64) 4+4
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* STM32F745Ix UFBGA176/LQFP176 140 6/3 24 No No No 2 Yes No No SFPU (240+16+64) 4+4
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@ -108,6 +119,8 @@
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* STM32F779Ax WLCSP180 129 6/3 24 Yes Yes Yes 3 No Yes Yes DFPU (368+16+128) 16+16
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* ----------- ---------------- ----- ---- ----- ---- ---- ---- ---- ---- ----- ----- ---- ------------ ------
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*
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* Parts STM32F72xxC & STM32F73xxC have 256Kb of FLASH
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* Parts STM32F72xxE & STM32F73xxE have 512Kb of FLASH
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* Parts STM32F74xxE have 512Kb of FLASH
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* Parts STM32F74xxG have 1024Kb of FLASH
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* Parts STM32F74xxI have 2048Kb of FLASH
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@ -116,7 +129,23 @@
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* with CONFIG_STM32F7_FLASH_OVERRIDE_x
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*
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*/
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#if defined(CONFIG_ARCH_CHIP_STM32F745VG) || \
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#if defined(CONFIG_ARCH_CHIP_STM32F722RC) || \
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defined(CONFIG_ARCH_CHIP_STM32F722RE) || \
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defined(CONFIG_ARCH_CHIP_STM32F722VC) || \
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defined(CONFIG_ARCH_CHIP_STM32F722VE) || \
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defined(CONFIG_ARCH_CHIP_STM32F722ZC) || \
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defined(CONFIG_ARCH_CHIP_STM32F722ZE) || \
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defined(CONFIG_ARCH_CHIP_STM32F722IC) || \
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defined(CONFIG_ARCH_CHIP_STM32F722IE) || \
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defined(CONFIG_ARCH_CHIP_STM32F723RC) || \
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defined(CONFIG_ARCH_CHIP_STM32F723RE) || \
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defined(CONFIG_ARCH_CHIP_STM32F723VC) || \
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defined(CONFIG_ARCH_CHIP_STM32F723VE) || \
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defined(CONFIG_ARCH_CHIP_STM32F723ZC) || \
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defined(CONFIG_ARCH_CHIP_STM32F723ZE) || \
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defined(CONFIG_ARCH_CHIP_STM32F723IC) || \
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defined(CONFIG_ARCH_CHIP_STM32F723IE) || \
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defined(CONFIG_ARCH_CHIP_STM32F745VG) || \
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defined(CONFIG_ARCH_CHIP_STM32F745VE) || \
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defined(CONFIG_ARCH_CHIP_STM32F745IG) || \
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defined(CONFIG_ARCH_CHIP_STM32F745IE) || \
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@ -179,7 +208,20 @@
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/* Size SRAM */
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#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX)
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#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX)
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# define STM32F7_SRAM1_SIZE (176*1024) /* 176Kb SRAM1 on AHB bus Matrix */
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# define STM32F7_SRAM2_SIZE (16*1024) /* 16Kb SRAM2 on AHB bus Matrix */
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# if defined(CONFIG_ARMV7M_HAVE_DTCM)
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# define STM32F7_DTCM_SRAM_SIZE (64*1024) /* 64Kb DTCM SRAM on TCM interface */
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# else
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# define STM32F7_DTCM_SRAM_SIZE (0) /* No DTCM SRAM on TCM interface */
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# endif
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# if defined(CONFIG_ARMV7M_HAVE_ITCM)
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# define STM32F7_ITCM_SRAM_SIZE (16*1024) /* 16Kb ITCM SRAM on TCM interface */
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# else
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# define STM32F7_ITCM_SRAM_SIZE (0) /* No ITCM SRAM on TCM interface */
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# endif
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#elif defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX)
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# define STM32F7_SRAM1_SIZE (240*1024) /* 240Kb SRAM1 on AHB bus Matrix */
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# define STM32F7_SRAM2_SIZE (16*1024) /* 16Kb SRAM2 on AHB bus Matrix */
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# if defined(CONFIG_ARMV7M_HAVE_DTCM)
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@ -209,6 +251,18 @@
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# error STM32 F7 chip Family not identified
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#endif
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/* Common to all Advanced (vs Foundation) Family members */
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#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX)
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# define STM32F7_NSPDIFRX 0 /* Not supported */
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# define STM32F7_NGPIO 9 /* 9 GPIO ports, GPIOA-I */
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# define STM32F7_NI2C 3 /* I2C1-3 */
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#else
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# define STM32F7_NSPDIFRX 4 /* 4 SPDIFRX inputs */
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# define STM32F7_NGPIO 11 /* 11 GPIO ports, GPIOA-K */
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# define STM32F7_NI2C 4 /* I2C1-4 */
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#endif
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/* Common to all Family members */
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# define STM32F7_NATIM 2 /* Two advanced timers TIM1 and 8 */
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@ -219,14 +273,11 @@
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# define STM32F7_NUART 4 /* UART 4-5 and 7-8 */
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# define STM32F7_NUSART 4 /* USART1-3 and 6 */
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# define STM32F7_NI2S 3 /* I2S1-2 (multiplexed with SPI1-3) */
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# define STM32F7_NI2C 4 /* I2C1-4 */
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# define STM32F7_NUSBOTGFS 1 /* USB OTG FS */
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# define STM32F7_NUSBOTGHS 1 /* USB OTG HS */
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# define STM32F7_NSAI 2 /* SAI1-2 */
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# define STM32F7_NSPDIFRX 4 /* 4 SPDIFRX inputs */
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# define STM32F7_NDMA 2 /* DMA1-2 */
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# define STM32F7_NGPIO 11 /* 11 GPIO ports, GPIOA-K */
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# define STM32F7_NADC 3 /* 12-bit ADC1-3, 24 channels *except V series) */
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# define STM32F7_NADC 3 /* 12-bit ADC1-3, number of channels vary */
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# define STM32F7_NDAC 2 /* 12-bit DAC1-2 */
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# define STM32F7_NCAPSENSE 0 /* No capacitive sensing channels */
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# define STM32F7_NCRC 1 /* CRC */
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@ -258,11 +309,17 @@
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#else
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# define STM32F7_NRNG 0 /* No Random number generator (RNG) */
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#endif
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#if defined(CONFIG_STM32F7_HAVE_SPI5) && defined(CONFIG_STM32F7_HAVE_SPI6)
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# define STM32F7_NSPI 6 /* SPI1-6 (Except V series) */
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#else
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# define STM32F7_NSPI 6 /* SPI1-6 (Advanced Family Except V series) */
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#elif defined(CONFIG_STM32F7_HAVE_SPI5)
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# define STM32F7_NSPI 5 /* SPI1-5 (Foundation Family Except V & R series) */
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#elif defined(CONFIG_STM32F7_HAVE_SPI4)
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# define STM32F7_NSPI 4 /* SPI1-4 V series */
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#else
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# define STM32F7_NSPI 3 /* SPI1-3 R series */
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#endif
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#if defined(CONFIG_STM32F7_HAVE_SDMMC2)
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# define STM32F7_NSDMMC 2 /* 2 SDMMC interfaces */
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#else
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@ -270,8 +327,10 @@
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#endif
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#if defined(CONFIG_STM32F7_HAVE_CAN3)
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# define STM32F7_NCAN 3 /* CAN1-3 */
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#else
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#elif defined(CONFIG_STM32F7_HAVE_CAN2)
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# define STM32F7_NCAN 2 /* CAN1-2 */
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#else
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# define STM32F7_NCAN 1 /* CAN1 only */
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#endif
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#if defined(CONFIG_STM32F7_HAVE_DCMI)
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# define STM32F7_NDCMI 1 /* Digital camera interface (DCMI) */
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@ -288,10 +347,10 @@
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#else
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# define STM32F7_NLCDTFT 0 /* No LCD-TFT */
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#endif
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#if defined(CONFIG_STM32F7_HAVE_DMA2D)
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# define STM32F7_NDMA2D 0 /* No DChrom-ART Accelerator™ (DMA2D) */
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#else
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#if defined(CONFIG_STM32F7_HAVE_DMA2D) /* bf20171107 Swapped defines they were reversed. */
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# define STM32F7_NDMA2D 1 /* DChrom-ART Accelerator™ (DMA2D) */
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#else
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# define STM32F7_NDMA2D 0 /* No DChrom-ART Accelerator™ (DMA2D) */
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#endif
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#if defined(CONFIG_STM32F7_HAVE_JPEG)
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#define STM32F7_NJPEG 1 /* One JPEG Converter */
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@ -1,8 +1,9 @@
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/************************************************************************************
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* arch/arm/include/stm32f7/irq.h
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*
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* Copyright (C) 2015 Gregory Nutt. All rights reserved.
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* Copyright (C) 2015, 2017 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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* Bob Feretich <bob.feretich@rafresearch.com>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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@ -76,7 +77,9 @@
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#define STM32_IRQ_FIRST (16) /* Vector number of the first external interrupt */
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#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX)
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#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX)
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# include <arch/stm32f7/stm32f72xx73xx_irq.h>
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#elif defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX)
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# include <arch/stm32f7/stm32f74xx75xx_irq.h>
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#elif defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX)
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# include <arch/stm32f7/stm32f76xx77xx_irq.h>
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@ -12,6 +12,134 @@ choice
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default ARCH_CHIP_STM32F746
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depends on ARCH_CHIP_STM32F7
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config ARCH_CHIP_STM32F722RC
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bool "STM32F722RC"
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select STM32F7_STM32F722XX
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select STM32F7_FLASH_CONFIG_C
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select STM32F7_IO_CONFIG_R
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---help---
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STM32 F7 Cortex M7, 256 FLASH, 256K (176+16+64) Kb SRAM
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config ARCH_CHIP_STM32F722RE
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bool "STM32F722RE"
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select STM32F7_STM32F722XX
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select STM32F7_FLASH_CONFIG_E
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select STM32F7_IO_CONFIG_R
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---help---
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STM32 F7 Cortex M7, 512 FLASH, 256K (176+16+64) Kb SRAM
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config ARCH_CHIP_STM32F722VC
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bool "STM32F722VC"
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select STM32F7_STM32F722XX
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select STM32F7_FLASH_CONFIG_C
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select STM32F7_IO_CONFIG_V
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---help---
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STM32 F7 Cortex M7, 256 FLASH, 256K (176+16+64) Kb SRAM
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config ARCH_CHIP_STM32F722VE
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bool "STM32F722VE"
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select STM32F7_STM32F722XX
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select STM32F7_FLASH_CONFIG_E
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select STM32F7_IO_CONFIG_V
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---help---
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STM32 F7 Cortex M7, 512 FLASH, 256K (176+16+64) Kb SRAM
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config ARCH_CHIP_STM32F722ZC
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bool "STM32F722ZC"
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select STM32F7_STM32F722XX
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select STM32F7_FLASH_CONFIG_C
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select STM32F7_IO_CONFIG_Z
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---help---
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STM32 F7 Cortex M7, 256 FLASH, 256K (176+16+64) Kb SRAM
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config ARCH_CHIP_STM32F722ZE
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bool "STM32F722ZE"
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select STM32F7_STM32F722XX
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select STM32F7_FLASH_CONFIG_E
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select STM32F7_IO_CONFIG_Z
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---help---
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STM32 F7 Cortex M7, 512 FLASH, 256K (176+16+64) Kb SRAM
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config ARCH_CHIP_STM32F722IC
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bool "STM32F722IC"
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select STM32F7_STM32F722XX
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select STM32F7_FLASH_CONFIG_C
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select STM32F7_IO_CONFIG_I
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---help---
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STM32 F7 Cortex M7, 256 FLASH, 256K (176+16+64) Kb SRAM
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config ARCH_CHIP_STM32F722IE
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bool "STM32F722IE"
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select STM32F7_STM32F722XX
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select STM32F7_FLASH_CONFIG_E
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select STM32F7_IO_CONFIG_I
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---help---
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STM32 F7 Cortex M7, 512 FLASH, 256K (176+16+64) Kb SRAM
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config ARCH_CHIP_STM32F723RC
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bool "STM32F723RC"
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select STM32F7_STM32F723XX
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select STM32F7_FLASH_CONFIG_C
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select STM32F7_IO_CONFIG_R
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---help---
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STM32 F7 Cortex M7, 256 FLASH, 256K (176+16+64) Kb SRAM
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config ARCH_CHIP_STM32F723RE
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bool "STM32F723RE"
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select STM32F7_STM32F723XX
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select STM32F7_FLASH_CONFIG_E
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select STM32F7_IO_CONFIG_R
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---help---
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STM32 F7 Cortex M7, 512 FLASH, 256K (176+16+64) Kb SRAM
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config ARCH_CHIP_STM32F723VC
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bool "STM32F723VC"
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select STM32F7_STM32F723XX
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select STM32F7_FLASH_CONFIG_C
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select STM32F7_IO_CONFIG_V
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---help---
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STM32 F7 Cortex M7, 256 FLASH, 256K (176+16+64) Kb SRAM
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config ARCH_CHIP_STM32F723VE
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bool "STM32F723VE"
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select STM32F7_STM32F723XX
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select STM32F7_FLASH_CONFIG_E
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select STM32F7_IO_CONFIG_V
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---help---
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STM32 F7 Cortex M7, 512 FLASH, 256K (176+16+64) Kb SRAM
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config ARCH_CHIP_STM32F723ZC
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bool "STM32F723ZC"
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select STM32F7_STM32F723XX
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select STM32F7_FLASH_CONFIG_C
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select STM32F7_IO_CONFIG_Z
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---help---
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STM32 F7 Cortex M7, 256 FLASH, 256K (176+16+64) Kb SRAM
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config ARCH_CHIP_STM32F723ZE
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bool "STM32F723ZE"
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select STM32F7_STM32F723XX
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select STM32F7_FLASH_CONFIG_E
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select STM32F7_IO_CONFIG_Z
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---help---
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STM32 F7 Cortex M7, 512 FLASH, 256K (176+16+64) Kb SRAM
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config ARCH_CHIP_STM32F723IC
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bool "STM32F723IC"
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select STM32F7_STM32F723XX
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select STM32F7_FLASH_CONFIG_C
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select STM32F7_IO_CONFIG_I
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---help---
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STM32 F7 Cortex M7, 256 FLASH, 256K (176+16+64) Kb SRAM
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config ARCH_CHIP_STM32F723IE
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bool "STM32F723IE"
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select STM32F7_STM32F723XX
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select STM32F7_FLASH_CONFIG_E
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select STM32F7_IO_CONFIG_I
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---help---
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STM32 F7 Cortex M7, 512 FLASH, 256K (176+16+64) Kb SRAM
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config ARCH_CHIP_STM32F745VG
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bool "STM32F745VG"
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select STM32F7_STM32F745XX
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@ -470,6 +598,14 @@ config ARCH_CHIP_STM32F779AI
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endchoice # STM32 F7 Chip Selection
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config STM32F7_STM32F72XX
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bool
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default n
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config STM32F7_STM32F73XX
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bool
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default n
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config STM32F7_STM32F74XX
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bool
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default n
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@ -486,6 +622,10 @@ config STM32F7_STM32F77XX
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bool
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default n
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config STM32F7_IO_CONFIG_R
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bool
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default n
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config STM32F7_IO_CONFIG_V
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bool
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default n
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@ -510,6 +650,22 @@ config STM32F7_IO_CONFIG_A
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bool
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default n
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config STM32F7_STM32F722XX
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bool
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default n
|
||||
select STM32F7_STM32F72XX
|
||||
select ARCH_HAVE_FPU
|
||||
select ARMV7M_HAVE_ICACHE
|
||||
select ARMV7M_HAVE_DCACHE
|
||||
select ARMV7M_HAVE_ITCM
|
||||
select ARMV7M_HAVE_DTCM
|
||||
select STM32F7_HAVE_FMC
|
||||
select STM32F7_HAVE_RNG
|
||||
select STM32F7_HAVE_SPI4 if !STM32F7_IO_CONFIG_R
|
||||
select STM32F7_HAVE_SPI5 if !(STM32F7_IO_CONFIG_R || STM32F7_IO_CONFIG_V)
|
||||
select STM32F7_HAVE_CRYP
|
||||
select STM32F7_HAVE_SDMMC2 if !STM32F7_IO_CONFIG_R
|
||||
|
||||
config STM32F7_STM32F745XX
|
||||
bool
|
||||
default n
|
||||
|
|
@ -526,6 +682,8 @@ config STM32F7_STM32F745XX
|
|||
select STM32F7_HAVE_SPI6 if !STM32F7_IO_CONFIG_V
|
||||
select STM32F7_HAVE_DCMI
|
||||
select STM32F7_HAVE_DMA2D
|
||||
select STM32F7_HAVE_CAN2
|
||||
select STM32F7_HAVE_SPI4
|
||||
|
||||
config STM32F7_STM32F746XX
|
||||
bool
|
||||
|
|
@ -544,6 +702,8 @@ config STM32F7_STM32F746XX
|
|||
select STM32F7_HAVE_DCMI
|
||||
select STM32F7_HAVE_LTDC
|
||||
select STM32F7_HAVE_DMA2D
|
||||
select STM32F7_HAVE_CAN2
|
||||
select STM32F7_HAVE_SPI4
|
||||
|
||||
config STM32F7_STM32F756XX
|
||||
bool
|
||||
|
|
@ -563,6 +723,8 @@ config STM32F7_STM32F756XX
|
|||
select STM32F7_HAVE_DMA2D
|
||||
select STM32F7_HAVE_CRYP
|
||||
select STM32F7_HAVE_HASH
|
||||
select STM32F7_HAVE_CAN2
|
||||
select STM32F7_HAVE_SPI4
|
||||
|
||||
config STM32F7_STM32F765XX
|
||||
bool
|
||||
|
|
@ -584,6 +746,8 @@ config STM32F7_STM32F765XX
|
|||
select STM32F7_HAVE_DCMI
|
||||
select STM32F7_HAVE_DMA2D
|
||||
select STM32F7_HAVE_DFSDM1
|
||||
select STM32F7_HAVE_CAN2
|
||||
select STM32F7_HAVE_SPI4
|
||||
|
||||
config STM32F7_STM32F767XX
|
||||
bool
|
||||
|
|
@ -608,6 +772,8 @@ config STM32F7_STM32F767XX
|
|||
select STM32F7_HAVE_DMA2D
|
||||
select STM32F7_HAVE_JPEG
|
||||
select STM32F7_HAVE_DFSDM1
|
||||
select STM32F7_HAVE_CAN2
|
||||
select STM32F7_HAVE_SPI4
|
||||
|
||||
config STM32F7_STM32F768XX # Revisit Wehn parts released
|
||||
bool
|
||||
|
|
@ -632,6 +798,8 @@ config STM32F7_STM32F768XX # Revisit Wehn parts released
|
|||
select STM32F7_HAVE_DMA2D
|
||||
select STM32F7_HAVE_JPEG
|
||||
select STM32F7_HAVE_DFSDM1
|
||||
select STM32F7_HAVE_CAN2
|
||||
select STM32F7_HAVE_SPI4
|
||||
|
||||
config STM32F7_STM32F768AX # Revisit When parts released
|
||||
bool
|
||||
|
|
@ -655,6 +823,8 @@ config STM32F7_STM32F768AX # Revisit When parts released
|
|||
select STM32F7_HAVE_DMA2D
|
||||
select STM32F7_HAVE_JPEG
|
||||
select STM32F7_HAVE_DFSDM1
|
||||
select STM32F7_HAVE_CAN2
|
||||
select STM32F7_HAVE_SPI4
|
||||
|
||||
config STM32F7_STM32F769XX
|
||||
bool
|
||||
|
|
@ -679,6 +849,8 @@ config STM32F7_STM32F769XX
|
|||
select STM32F7_HAVE_DMA2D
|
||||
select STM32F7_HAVE_JPEG
|
||||
select STM32F7_HAVE_DFSDM1
|
||||
select STM32F7_HAVE_CAN2
|
||||
select STM32F7_HAVE_SPI4
|
||||
|
||||
config STM32F7_STM32F769AX # Revisit When parts released
|
||||
bool
|
||||
|
|
@ -702,6 +874,8 @@ config STM32F7_STM32F769AX # Revisit When parts released
|
|||
select STM32F7_HAVE_DMA2D
|
||||
select STM32F7_HAVE_JPEG
|
||||
select STM32F7_HAVE_DFSDM1
|
||||
select STM32F7_HAVE_CAN2
|
||||
select STM32F7_HAVE_SPI4
|
||||
|
||||
config STM32F7_STM32F777XX
|
||||
bool
|
||||
|
|
@ -728,6 +902,8 @@ config STM32F7_STM32F777XX
|
|||
select STM32F7_HAVE_CRYP
|
||||
select STM32F7_HAVE_HASH
|
||||
select STM32F7_HAVE_DFSDM1
|
||||
select STM32F7_HAVE_CAN2
|
||||
select STM32F7_HAVE_SPI4
|
||||
|
||||
config STM32F7_STM32F778XX # Revisit when parts released
|
||||
bool
|
||||
|
|
@ -754,6 +930,8 @@ config STM32F7_STM32F778XX # Revisit when parts released
|
|||
select STM32F7_HAVE_CRYP
|
||||
select STM32F7_HAVE_HASH
|
||||
select STM32F7_HAVE_DFSDM1
|
||||
select STM32F7_HAVE_CAN2
|
||||
select STM32F7_HAVE_SPI4
|
||||
|
||||
config STM32F7_STM32F778AX
|
||||
bool
|
||||
|
|
@ -779,6 +957,8 @@ config STM32F7_STM32F778AX
|
|||
select STM32F7_HAVE_CRYP
|
||||
select STM32F7_HAVE_HASH
|
||||
select STM32F7_HAVE_DFSDM1
|
||||
select STM32F7_HAVE_CAN2
|
||||
select STM32F7_HAVE_SPI4
|
||||
|
||||
config STM32F7_STM32F779XX
|
||||
bool
|
||||
|
|
@ -805,6 +985,8 @@ config STM32F7_STM32F779XX
|
|||
select STM32F7_HAVE_CRYP
|
||||
select STM32F7_HAVE_HASH
|
||||
select STM32F7_HAVE_DFSDM1
|
||||
select STM32F7_HAVE_CAN2
|
||||
select STM32F7_HAVE_SPI4
|
||||
|
||||
config STM32F7_STM32F779AX
|
||||
bool
|
||||
|
|
@ -830,6 +1012,8 @@ config STM32F7_STM32F779AX
|
|||
select STM32F7_HAVE_CRYP
|
||||
select STM32F7_HAVE_HASH
|
||||
select STM32F7_HAVE_DFSDM1
|
||||
select STM32F7_HAVE_CAN2
|
||||
select STM32F7_HAVE_SPI4
|
||||
|
||||
config STM32F7_FLASH_CONFIG_E
|
||||
bool
|
||||
|
|
@ -852,6 +1036,7 @@ choice
|
|||
that designates the FLASH size.
|
||||
|
||||
Designator Size in KiB
|
||||
C 256
|
||||
E 512
|
||||
G 1024
|
||||
I 2048
|
||||
|
|
@ -871,6 +1056,9 @@ choice
|
|||
config STM32F7_FLASH_OVERRIDE_DEFAULT
|
||||
bool "Default"
|
||||
|
||||
config STM32F7_FLASH_OVERRIDE_C
|
||||
bool "C 256KiB"
|
||||
|
||||
config STM32F7_FLASH_OVERRIDE_E
|
||||
bool "E 512KiB"
|
||||
|
||||
|
|
@ -913,6 +1101,10 @@ config STM32F7_HAVE_RNG
|
|||
bool
|
||||
default n
|
||||
|
||||
config STM32F7_HAVE_SPI4
|
||||
bool
|
||||
default n
|
||||
|
||||
config STM32F7_HAVE_SPI5
|
||||
bool
|
||||
default n
|
||||
|
|
@ -937,6 +1129,10 @@ config STM32F7_HAVE_ADC3_DMA
|
|||
bool
|
||||
default n
|
||||
|
||||
config STM32F7_HAVE_CAN2
|
||||
bool
|
||||
default n
|
||||
|
||||
config STM32F7_HAVE_CAN3
|
||||
bool
|
||||
default n
|
||||
|
|
@ -1269,6 +1465,7 @@ config STM32F7_SPI3
|
|||
config STM32F7_SPI4
|
||||
bool "SPI4"
|
||||
default n
|
||||
depends on STM32F7_HAVE_SPI4
|
||||
select SPI
|
||||
select STM32F7_SPI
|
||||
|
||||
|
|
|
|||
|
|
@ -1,9 +1,10 @@
|
|||
/************************************************************************************
|
||||
* arch/arm/src/stm32f7/chip/stm32_exti.h
|
||||
*
|
||||
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
|
||||
* Copyright (C) 2015, 2017 Gregory Nutt. All rights reserved.
|
||||
* Authors: Gregory Nutt <gnutt@nuttx.org>
|
||||
* David Sidrane <david_s5@nscdg.com>
|
||||
* Bob Feretich <bob.feretich@rafresearch.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
|
|
@ -48,7 +49,8 @@
|
|||
* families
|
||||
*/
|
||||
|
||||
#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) || \
|
||||
#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX) || \
|
||||
defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) || \
|
||||
defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX)
|
||||
|
||||
/************************************************************************************
|
||||
|
|
|
|||
|
|
@ -1,9 +1,10 @@
|
|||
/************************************************************************************
|
||||
* arch/arm/src/stm32f7/chip/stm32_i2c.h
|
||||
*
|
||||
* Copyright (C) 2016 Gregory Nutt. All rights reserved.
|
||||
* Copyright (C) 2016-2017 Gregory Nutt. All rights reserved.
|
||||
* Authors: Gregory Nutt <gnutt@nuttx.org>
|
||||
* David Sidrane <david_s5@nscdg.com>
|
||||
* Bob Feretich <bob.feretich@rafresearch.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
|
|
@ -44,7 +45,8 @@
|
|||
#include <nuttx/config.h>
|
||||
#include "chip.h"
|
||||
|
||||
#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) || \
|
||||
#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX) || \
|
||||
defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) || \
|
||||
defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX)
|
||||
# include "chip/stm32f74xx77xx_i2c.h"
|
||||
#else
|
||||
|
|
|
|||
|
|
@ -1,9 +1,10 @@
|
|||
/************************************************************************************
|
||||
* arch/arm/src/stm32f7/chip/stm32_sdmmc.h
|
||||
*
|
||||
* Copyright (C) 2016 Gregory Nutt. All rights reserved.
|
||||
* Copyright (C) 2016-2017 Gregory Nutt. All rights reserved.
|
||||
* Authors: Gregory Nutt <gnutt@nuttx.org>
|
||||
* David Sidrane <david_s5@nscdg.com>
|
||||
* Bob Feretich <bob.feretich@rafresearch.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
|
|
@ -44,7 +45,8 @@
|
|||
#include <nuttx/config.h>
|
||||
#include "chip.h"
|
||||
|
||||
#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) || \
|
||||
#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX) || \
|
||||
defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) || \
|
||||
defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX)
|
||||
# include "stm32f74xx77xx_sdmmc.h"
|
||||
#else
|
||||
|
|
|
|||
|
|
@ -1,9 +1,10 @@
|
|||
/************************************************************************************
|
||||
* arch/arm/src/stm32f7/chip/stm32_spi.h
|
||||
*
|
||||
* Copyright (C) 2016 Gregory Nutt. All rights reserved.
|
||||
* Copyright (C) 2016-2017 Gregory Nutt. All rights reserved.
|
||||
* Authors: Gregory Nutt <gnutt@nuttx.org>
|
||||
* David Sidrane <david_s5@nscdg.com>
|
||||
* Bob Feretich <bob.feretich@rafresearch.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
|
|
@ -44,7 +45,8 @@
|
|||
#include <nuttx/config.h>
|
||||
#include "chip.h"
|
||||
|
||||
#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) || \
|
||||
#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX) || \
|
||||
defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) || \
|
||||
defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX)
|
||||
# include "chip/stm32f74xx77xx_spi.h"
|
||||
#else
|
||||
|
|
|
|||
|
|
@ -7,6 +7,7 @@
|
|||
* Diego Sanchez <dsanchez@nx-engineering.com>
|
||||
* Paul Alexander Patience <paul-a.patience@polymtl.ca>
|
||||
* David Sidrane <david_s5@nscdg.com>
|
||||
* Bob Feretich <bob.feretich@rafresearch.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
|
|
@ -85,7 +86,8 @@
|
|||
|
||||
/* This implementation is for the STM32 F7[4-7] only */
|
||||
|
||||
#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) || \
|
||||
#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX) || \
|
||||
defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) || \
|
||||
defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX)
|
||||
|
||||
/****************************************************************************
|
||||
|
|
|
|||
|
|
@ -3,6 +3,7 @@
|
|||
*
|
||||
* Copyright (C) 2015-2017 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
* Bob Feretich <bob.feretich@rafresearch.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
|
|
@ -59,7 +60,8 @@
|
|||
* families
|
||||
*/
|
||||
|
||||
#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) \
|
||||
#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM33F75XX) \
|
||||
|| defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) \
|
||||
|| defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX)
|
||||
|
||||
/****************************************************************************
|
||||
|
|
|
|||
|
|
@ -1,9 +1,10 @@
|
|||
/****************************************************************************
|
||||
* arch/arm/src/stm32f7/stm32_dtcm.h
|
||||
*
|
||||
* Copyright (C) 2015-2016 Gregory Nutt. All rights reserved.
|
||||
* Copyright (C) 2015-2017 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
* David Sidrane <david_s5@nscdg.com>
|
||||
* Bob Feretich <bob.feretich@rafresearch.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
|
|
@ -55,7 +56,8 @@
|
|||
|
||||
/* The STM32 F7 have DTCM memory */
|
||||
|
||||
#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX)
|
||||
#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX) \
|
||||
|| defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX)
|
||||
# define DTCM_START 0x20000000
|
||||
# define DTCM_END 0x20010000
|
||||
#elif defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX)
|
||||
|
|
|
|||
|
|
@ -1,8 +1,9 @@
|
|||
/****************************************************************************
|
||||
* arch/arm/src/stm32f7/stm32_gpio.c
|
||||
*
|
||||
* Copyright (C) 2015-2016 Gregory Nutt. All rights reserved.
|
||||
* Copyright (C) 2015-2017 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
* Bob Feretich <bob.feretich@rafresearch.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
|
|
@ -58,6 +59,7 @@
|
|||
*/
|
||||
|
||||
#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) \
|
||||
|| defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) \
|
||||
|| defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX)
|
||||
|
||||
/****************************************************************************
|
||||
|
|
|
|||
|
|
@ -11,6 +11,7 @@
|
|||
* Copyright (C) 2011 Uros Platise. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
* Uros Platise <uros.platise@isotel.eu>
|
||||
* Bob Feretich <bob.feretich@rafresearch.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
|
|
@ -65,7 +66,8 @@
|
|||
* families
|
||||
*/
|
||||
|
||||
#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) \
|
||||
#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX) \
|
||||
|| defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) \
|
||||
|| defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX)
|
||||
|
||||
/****************************************************************************
|
||||
|
|
|
|||
|
|
@ -1,8 +1,9 @@
|
|||
/****************************************************************************
|
||||
* arch/arm/src/stm32f7/stm32_gpio.c
|
||||
*
|
||||
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
|
||||
* Copyright (C) 2015, 2017 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
* Bob Feretich <bob.feretich@rafresearch.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
|
|
@ -57,7 +58,8 @@
|
|||
* families
|
||||
*/
|
||||
|
||||
#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) \
|
||||
#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX) \
|
||||
|| defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) \
|
||||
|| defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX)
|
||||
|
||||
/****************************************************************************
|
||||
|
|
|
|||
|
|
@ -11,6 +11,7 @@
|
|||
* Authors: Gregroy Nutt <gnutt@nuttx.org>
|
||||
* John Wharington
|
||||
* David Sidrane <david_s5@nscdg.com>
|
||||
* Bob Feretich <bob.feretich@rafresearch.com>
|
||||
*
|
||||
* Major rewrite of ISR and supporting methods, including support
|
||||
* for NACK and RELOAD by:
|
||||
|
|
@ -159,6 +160,8 @@
|
|||
*
|
||||
* One of:
|
||||
*
|
||||
* CONFIG_STM32F7_STM32F72XX
|
||||
* CONFIG_STM32F7_STM32F73XX
|
||||
* CONFIG_STM32F7_STM32F74XX
|
||||
* CONFIG_STM32F7_STM32F75XX
|
||||
* CONFIG_STM32F7_STM32F76XX
|
||||
|
|
@ -195,6 +198,10 @@
|
|||
*
|
||||
* References:
|
||||
*
|
||||
* RM0431:
|
||||
* ST STM32F72xxx and STM32F73xxx Reference Manual
|
||||
* Document ID: DocID029480 Revision 1, Jan 2017.
|
||||
*
|
||||
* RM0316:
|
||||
* ST STM32F76xxx and STM32F77xxx Reference Manual
|
||||
* Document ID: DocID028270 Revision 2, April 2016.
|
||||
|
|
|
|||
|
|
@ -699,7 +699,7 @@ config ARCH_BOARD_NR5M100_NEXYS4
|
|||
|
||||
config ARCH_BOARD_NUCLEO_144
|
||||
bool "STMicro NUCLEO-144"
|
||||
depends on ARCH_CHIP_STM32F746ZG || ARCH_CHIP_STM32F767ZI
|
||||
depends on ARCH_CHIP_STM32F722ZE || ARCH_CHIP_STM32F746ZG || ARCH_CHIP_STM32F767ZI
|
||||
select ARCH_HAVE_LEDS
|
||||
select ARCH_HAVE_BUTTONS
|
||||
select ARCH_HAVE_IRQBUTTONS
|
||||
|
|
@ -713,6 +713,7 @@ config ARCH_BOARD_NUCLEO_144
|
|||
STM32F303ZET6 NUCLEO-F303ZE
|
||||
STM32F429ZIT6 NUCLEO-F429ZI
|
||||
STM32F446ZET6 NUCLEO-F446ZE
|
||||
STM32F722ZET6 NUCLEO-F722ZE
|
||||
STM32F746ZGT6 NUCLEO-F746ZG
|
||||
STM32F767ZIT6 NUCLEO-F767ZI
|
||||
STM32L496ZGT6 NUCLEO-L496ZG
|
||||
|
|
@ -720,6 +721,8 @@ config ARCH_BOARD_NUCLEO_144
|
|||
|
||||
Supported in this configuration are:
|
||||
|
||||
NUCLEO-F722ZE - STM32F722ZET6 a 216MHz Cortex-M7, w/FPU -
|
||||
512KiB Flash memory and 256KiB SRAM.
|
||||
NUCLEO-F746ZG - STM32F746ZGT6 a 216MHz Cortex-M7, w/FPU -
|
||||
1024KiB Flash memory and 320KiB SRAM.
|
||||
NUCLEO-F767ZI - STM32F767ZIT6 a 216MHz Cortex-M7, w/DPFPU -
|
||||
|
|
|
|||
|
|
@ -40,10 +40,22 @@ choice
|
|||
STM32F7
|
||||
MORPHO FUNCTION GPIO
|
||||
-------- --------- -----
|
||||
CN12-64 USART8_RX PE0
|
||||
CN11-61 USART8_TX PE1
|
||||
CN12-64 UART8_RX PE0
|
||||
CN11-61 UART8_TX PE1
|
||||
-------- --------- -----
|
||||
|
||||
OR
|
||||
|
||||
Morpho Connector UART4:
|
||||
|
||||
STM32F7
|
||||
MORPHO FUNCTION GPIO
|
||||
-------- --------- -----
|
||||
CN11-30 UART4_RX PA0
|
||||
CN11-28 UART4_TX PA1
|
||||
-------- --------- -----
|
||||
Note: SB13 must be removed to disable Ethernet.
|
||||
|
||||
config NUCLEO_CONSOLE_ARDUINO
|
||||
bool "Arduino Connector"
|
||||
select STM32F7_USART6
|
||||
|
|
@ -62,6 +74,12 @@ config NUCLEO_CONSOLE_MORPHO
|
|||
select UART8_SERIALDRIVER
|
||||
select UART8_SERIAL_CONSOLE
|
||||
|
||||
config NUCLEO_CONSOLE_MORPHO_UART4
|
||||
bool "Morpho Connector UART4"
|
||||
select STM32F7_UART4
|
||||
select UART4_SERIALDRIVER
|
||||
select UART4_SERIAL_CONSOLE
|
||||
|
||||
config NUCLEO_CONSOLE_NONE
|
||||
bool "No Console"
|
||||
|
||||
|
|
|
|||
|
|
@ -10,6 +10,7 @@ Contents
|
|||
========
|
||||
|
||||
- Nucleo-144 Boards
|
||||
- Nucleo F722ZE
|
||||
- Nucleo F746ZG
|
||||
- Nucleo F767ZI
|
||||
- Development Environment
|
||||
|
|
@ -38,6 +39,7 @@ LQFP144 package. Variants include
|
|||
STM32F303ZET6 NUCLEO-F303ZE
|
||||
STM32F429ZIT6 NUCLEO-F429ZI
|
||||
STM32F446ZET6 NUCLEO-F446ZE
|
||||
STM32F722ZET6 NUCLEO-F722ZE
|
||||
STM32F746ZGT6 NUCLEO-F746ZG
|
||||
STM32F767ZIT6 NUCLEO-F767ZI
|
||||
STM32L496ZGT6 NUCLEO-L496ZG
|
||||
|
|
@ -229,10 +231,11 @@ Hardware
|
|||
debugging. Because so many pins can be multiplexed with so many functions,
|
||||
the above mentioned graphic may be helpful in indentifying a serial port.
|
||||
|
||||
There are 4 choices that can be made from the menuconfig:
|
||||
There are 5 choices that can be made from the menuconfig:
|
||||
|
||||
CONFIG_NUCLEO_CONSOLE_ARDUINO or CONFIG_NUCLEO_CONSOLE_MORPHO or
|
||||
CONFIG_NUCLEO_CONSOLE_VIRTUAL or CONFIG_NUCLEO_CONSOLE_NONE
|
||||
CONFIG_NUCLEO_CONSOLE_MORPHO_UART4 or CONFIG_NUCLEO_CONSOLE_VIRTUAL or
|
||||
CONFIG_NUCLEO_CONSOLE_NONE
|
||||
|
||||
The CONFIG_NUCLEO_CONSOLE_NONE makes no preset for the console. YOu shuld still visit
|
||||
the U[S]ART selection and Device Drivers to disable any U[S]ART reamaing.
|
||||
|
|
@ -256,6 +259,14 @@ Hardware
|
|||
SERIAL_RX PE_0
|
||||
SERIAL_TX PE_1
|
||||
|
||||
The CONFIG_NUCLEO_CONSOLE_MORPHO_UART4 configurations uses Serial Port 4 (UART4)
|
||||
with TX on PA1 and RX on PA0. Zero Ohm resistor / solder short at
|
||||
SB13 must be removed/open. (Disables Ethernet MII clocking.)
|
||||
Serial
|
||||
------
|
||||
SERIAL_RX PA_1 CN11 30
|
||||
SERIAL_TX PA_0 CN11 28
|
||||
|
||||
The CONFIG_NUCLEO_CONSOLE_VIRTUAL configurations uses Serial Port 3 (USART3)
|
||||
with TX on PD8 and RX on PD9.
|
||||
Serial
|
||||
|
|
|
|||
|
|
@ -1,10 +1,11 @@
|
|||
/************************************************************************************
|
||||
* configs/nucleo-144/include/board.h
|
||||
*
|
||||
* Copyright (C) 2016 Gregory Nutt. All rights reserved.
|
||||
* Copyright (C) 2016-2017 Gregory Nutt. All rights reserved.
|
||||
* Authors: Gregory Nutt <gnutt@nuttx.org>
|
||||
* Mark Olsson <post@markolsson.se>
|
||||
* David Sidrane <david_s5@nscdg.com>
|
||||
* Bob Feretich <bob.feretich@rafresearch.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
|
|
@ -374,6 +375,36 @@
|
|||
# define GPIO_USART3_TX GPIO_USART3_TX_3
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_NUCLEO_CONSOLE_MORPHO_UART4)
|
||||
/* UART4:
|
||||
*
|
||||
* This configuration assumes that you disabled Ethernet MII clocking
|
||||
* by removing SB13 to free PA1.
|
||||
*
|
||||
* -------- ---------------
|
||||
* STM32F7
|
||||
* Pin FUNCTION GPIO
|
||||
* ------- --------- -----
|
||||
* CN11 30 UART4_RX PA1
|
||||
* CN11 28 UART4_TX PA0
|
||||
* ------- --------- -----
|
||||
*/
|
||||
|
||||
# define GPIO_UART4_RX GPIO_UART4_RX_1
|
||||
# define GPIO_UART4_TX GPIO_UART4_TX_1
|
||||
|
||||
/* USART3 seems to be forced selected by the Nucleo-F746ZG kconfig - bug */
|
||||
|
||||
# define GPIO_USART3_RX GPIO_USART3_RX_1
|
||||
# define GPIO_USART3_TX GPIO_USART3_TX_1
|
||||
|
||||
/* USART6 seems to be forced selected by the Nucleo-F722E kconfig - bug */
|
||||
|
||||
# define GPIO_USART6_RX GPIO_USART6_RX_2
|
||||
# define GPIO_USART6_TX GPIO_USART6_TX_2
|
||||
|
||||
#endif
|
||||
|
||||
/* USART8:
|
||||
*
|
||||
* This configurations assume that you are connecting to the Morpho connector
|
||||
|
|
|
|||
Loading…
Reference in a new issue