In https://github.com/apache/nuttx/pull/13044,
LIBC_ARCH_ATOMIC was finally removed.
Howerver, the following chips still have the config.
- ARCH_CHIP_ESP32S3
- ARCH_CHIP_ESP32C3_GENERIC
- ARCH_CHIP_ESP32H2
This commit fixes the issue.
1. Excerpted from: https://github.com/ARM-software/LLVM-embedded-toolchain-for-Arm/blob/main/samples/src/cpp-baremetal-semihosting-prof/proflib.c
2. Since llvm profile supports more than just gcov, and some features have not yet been explored, two clang gcov implementations are supported after this patch
3. Using this lib only supports the gcov compilation options of "-fprofile-instr-generate -fcoverage-mapping"
4. This file is heavily dependent on the compiler clang version, and is currently aligned with ci, supporting 17.0.1 and below. 18 and above are not supported by this library due to different internal implementations of the compiler
Signed-off-by: wangmingrong1 <wangmingrong1@xiaomi.com>
`ARCH_HAVE_RAMFUNCS` has no actual effect on the ESP32-C3,
but ESP32-C3 has RAM functions, so select it to mark that is OK,
and then we can also suppress the RWX memory region warning.
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
Some armv7-m-based SoCs do not work with atomic instructions,
even though armv7-m supports them.
To avoid using atomic instructions generated by gcc,
CONFIG_LIBC_ARCH_ATOMIC is newly introduced with which
arch_atomic.c is linked explicitly.
However, the function names need to be changed to avoid
build errors, since the functions described in stdatomic.h
are gcc built-in and inlined when the code is compiled.
Signed-off-by: Takuya Miyasita <Takuya.Miyashita@sony.com>
Suppress the warning message "nuttx has a LOAD segment with RWX permissions" in case of RAM boot mode is selected.
RAM MODE: BOOT_RUNFROMEXTSRAM/BOOT_RUNFROMISRAM/BOOT_RUNFROMSDRAM/BOOT_COPYTORAM
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
when we build mbedtls in vela with ghs compiler, the mbedtls need to
access __ARM_ARCH and __ARM_FEATURE_DSP, and to construct the inline asm
code based on these two macros.
With ghs compiler, these two macros are not defined, and will be
evaluated as 0 by default, and thus will using to wrong inline asm code,
in order to handle this issue, we need to add conversion between the ghs
and gcc with __ARM_ARCH, __ARM_FEATURE_DSP
Signed-off-by: guoshichao <guoshichao@xiaomi.com>
when build with greenhills_202354, the naked_function should only
contains the basic asm statements, so if the naked_function contains the
statements that using to accept params from C lang runtime, then build
error will reported:
error #101112: Only basic asm expressions are allowed for functions
with __attribute__((naked)): dispatch_syscall
Signed-off-by: guoshichao <guoshichao@xiaomi.com>
This commit adds files in preperation of adding ethernet drivers for the STM32H563 and Nucleo-H563ZI board.
It also modifies the pinmap to include ethernet pins (and cleaned up leftover comments from L5 file), as well as
add those pins to the board.h for the nucleo-h563zi.
Files added:
- arch/arm/src/stm32h5/hardware/stm32_ethernet.h
- arch/arm/src/stm32h5/hardware/stm32_sbs.h
- Not fully implemented, just register necessary for ethernet driver.
The naming scheme in board.h changed from STM32H5_ to STM32_. As a result we needed to adjust the naming of the STM32H5_BOARD_USExxx variables in stm32h5xx_rcc.c. Also made changes to allow the enabling of all 3 of HSI, CSI, or HSE in stm32_stdclockconfig. Lastly, the HSIDIV bits in RCC_CR were not being cleared before being set. Added logic to clear these bits.
defined CSIRDY_TIMEOUT
There is an enormous error in the system call dispatch logic; if a task
is inside a critical section (local interrupts disabled) there is a chance
that during a context switch when the task resumes, local interrupts are
erroneously ENABLED. This obviously leads to unexpected crashes and such.
This happens when the CPU status has Previous Interrupt Enable (PIE) set
to 1, even though Interrupt Enable (IE) is set to 0.
When the system call returns via ERET, the CPU sets PIE->IE and if PIE=1
interrupts get enabled.
This is fixed easily by explicitly CLEARING PIE from the register save
area, if IE=0 when the system call was started.
In the virtualized environment, each time an SGI is sent, the value of IGROUPR0 needs to be read once. Since the GIC Redistributor is a purely emulated device, each read of IGROUPR0 will cause a VM exit, causing serious performance degradation. This patch replaces the read with the value previously set in `gicv3_cpuif_init`, and we assume that this value has not been modified after initialization.
Signed-off-by: ouyangxiangzhen <ouyangxiangzhen@xiaomi.com>
This is a combination of 2 commits:
H5 Kconfig ethernet options added.
- This commit cleans up unecessary comments in the Kconfig and adds the the Ethernet/MAC menu.
The menu is copied from the H7 menu, since the peripheral IP is identical.
Remove trailing whitespaces.
Update suggested mask
PLL1FRACN was being set improperly. stm32h5xxx_rcc.c does not shift the value provided by board.h. So it was being set wrong. The defintions in stm32h5xxx_rcc.h shift the FRACN value and are now used by board.h. Also, board.h was not setting PLL1P properly. PLL1P can not have odd divisors. Therefore a value of 0 was invalid. Set it to a value of 1 (divide by 2), then adjust PLL1N to 31 and PLL1FRAC1 to 2048 to actually set SYSCLK to 250MHz.
Made fixes to issues from CI. Nxstyle and defconfig syntax.
This is a combination of 6 commits.
Adding STM32H5 arch files. With comments addressed.
Created stm32h5 directory to add support for the H5 chip, and used a Nucleo-H563ZI dev board during development. The goal was to get a working nutshell through the STLink connector on the board.
Remove board/docs changes for PR update.
Squash commits into one for PR guideline conformity.
trying to fix build issues
Fix format from review
Nucleo-H563ZI support for NSH.
Created stm32h5 directory to add support for the H5 chip, and used a Nucleo-H563ZI dev board during development. The goal was to get a working nutshell through the STLink connector on the board.
Fix switch default case placement.
NXstyle fixes
Renaming files
rename stm32h5_gpio.x files
rename h5 hsi48 files
Rename h5 idle file
rename stm32h5_irq.c
Rename some rcc functions and stm32h5_rcc.c
rename stm32h5_rcc.h
Rename stm32h5_pwr.x
lowputc renames
timerisr renames
uart renamed
rename serial file
rename start
Turn off the defines that enable DMA on serial
remove DMA Kconfig options
Remove H5 documentation. Will add in a future PR.
Fix styling and defconfig improper syntax.
Created stm32h5 directory to add support for the H5 chip, and used a Nucleo-H563ZI dev board during development. The goal was to get a working nutshell through the STLink connector on the board.
Remove board/docs changes for PR update.
Squash commits into one for PR guideline conformity.
trying to fix build issues
Fix format from review
The reason for removing math.h is that undefining __GLIBC__ does not take effect. By default, sim will use the toolchain's math library and undef __GLIBC__ in the source file.
Signed-off-by: cuiziwei <cuiziwei@xiaomi.com>
This patch fixed userspace headers conflict. Architecture-related definition and API should not be exposed to users.
Signed-off-by: ouyangxiangzhen <ouyangxiangzhen@xiaomi.com>
reason:
Replace "inline" with "inline_function" for "up_interrupt_context" to ensure consistency with other arch
Signed-off-by: hujun5 <hujun5@xiaomi.com>
