Ville Juven 51171d66f2 riscv/riscv_ipi.h: Do not write to CSR_MIP.MSIP as it is read-only ... From the RISV-V Privileged Spec v1.10 (3.1.14 MIP/MIE): Only the bits corresponding to lower-privilege software interrupts (USIP, SSIP), timer interrupts (UTIP, STIP), and external interrupts (UEIP, SEIP) in mip are writable through this CSR address; the remaining bits are read-only. Thus, it is futile to write to the M-mode status bit via the CSR, only access via RISCV_IPI is valid.		2024-11-28 09:14:07 +08:00
..
include	riscv/syscall.h: Update comment for syscall	2024-11-20 10:50:50 +01:00
src	riscv/riscv_ipi.h: Do not write to CSR_MIP.MSIP as it is read-only	2024-11-28 09:14:07 +08:00
CMakeLists.txt	cmake:init RISC-V cmake qemu-rv build	2023-10-26 21:01:46 +08:00
Kconfig	risc-v and xtensa Kconfig : Remove LIBC_ARCH_ATOMIC	2024-11-13 15:30:53 +08:00