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UART Input works OK yay!

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Lee Lup Yuen 2023-12-05 13:34:04 +08:00
parent 2e98ebdeba
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@ -3754,6 +3754,10 @@ Offset 8c: uart_fifo_rdata (Receive Data)
RX FIFO. OK to ignore this.
```
Nope still the same.
# Fix the UART Interrupt for Ox64 BL808
TODO: Check rxavailable
https://github.com/lupyuen2/wip-pinephone-nuttx/blob/ox64c/arch/risc-v/src/jh7110/bl602_serial.c#L1026-L1044
@ -3812,7 +3816,58 @@ PLIC Interrupt Pending (0xe0001000):
0000 00 00 00 00 00 00 00 00 ........
```
TODO: Is C906 read-caching the entire page?
_Is C906 read-caching the entire page?_
Let's uncache and retest: [riscv_mmu.c](https://github.com/lupyuen2/wip-pinephone-nuttx/blob/ox64c/arch/risc-v/src/common/riscv_mmu.c#L100-L127)
```c
/* Save it */
lntable[index] = (paddr | mmuflags);
//// Begin Test
// From https://github.com/torvalds/linux/blob/master/arch/riscv/include/asm/pgtable-64.h#L126-L142
/*
* [63:59] T-Head Memory Type definitions:
* bit[63] SO - Strong Order
* bit[62] C - Cacheable
* bit[61] B - Bufferable
* bit[60] SH - Shareable
* bit[59] Sec - Trustable
* 00110 - NC Weakly-ordered, Non-cacheable, Bufferable, Shareable, Non-trustable
* 01110 - PMA Weakly-ordered, Cacheable, Bufferable, Shareable, Non-trustable
* 10010 - IO Strongly-ordered, Non-cacheable, Non-bufferable, Shareable, Non-trustable
*/
#define _PAGE_PMA_THEAD ((1UL << 62) | (1UL << 61) | (1UL << 60))
#define _PAGE_NOCACHE_THEAD ((1UL < 61) | (1UL << 60))
#define _PAGE_IO_THEAD ((1UL << 63) | (1UL << 60))
#define _PAGE_MTMASK_THEAD (_PAGE_PMA_THEAD | _PAGE_IO_THEAD | (1UL << 59))
if ((mmuflags & PTE_R) &&
(vaddr < 0x40000000UL || vaddr >= 0xe0000000UL))
{
lntable[index] = lntable[index] | _PAGE_MTMASK_THEAD;
_info("vaddr=%p, lntable[index]=%p\n", vaddr, lntable[index]);
}
//// End Test
```
Yep [UART Input works OK](https://gist.github.com/lupyuen/6f3e24278c4700f73da72b9efd703167) yay!
```text
nx_start: CPU0: Beginning Idle Loop
bl602_receive: rxdata=0x31
riscv_dispatch_irq: Clear Pending Interrupts, irq=45, claim=0
PLIC Interrupt Pending (0xe0001000):
0000 00 00 00 00 00 00 00 00 ........
1riscv_dispatch_irq: Clear Pending Interrupts, irq=45, claim=0
PLIC Interrupt Pending (0xe0001000):
0000 00 00 00 00 00 00 00 00 ........
bl602_receive: rxdata=0x32
riscv_dispatch_irq: Clear Pending Interrupts, irq=45, claim=0
PLIC Interrupt Pending (0xe0001000):
0000 00 00 00 00 00 00 00 00 ........
2
```
# Documentation for Ox64 BL808