From 81e561f53b1882cd6a7ff4b3eef715420487feee Mon Sep 17 00:00:00 2001 From: Lee Lup Yuen Date: Thu, 20 Jul 2023 10:02:59 +0800 Subject: [PATCH] Initial RAM Disk --- README.md | 23 +++ qemu-riscv64.dtb | Bin 0 -> 1048576 bytes qemu-riscv64.dts | 355 +++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 378 insertions(+) create mode 100644 qemu-riscv64.dtb create mode 100644 qemu-riscv64.dts diff --git a/README.md b/README.md index 89114a6..f741b92 100644 --- a/README.md +++ b/README.md @@ -2899,6 +2899,29 @@ $ qemu-system-riscv64 -M virt -smp 4 -m 2G \ TODO: Address of the Initial RAM Disk +Let's dump the Device Tree for QEMU RISC-V... + +```bash +## Dump Device Tree for QEMU RISC-V +qemu-system-riscv64 \ + -semihosting \ + -M virt,aclint=on,dumpdtb=qemu-riscv64.dtb \ + -cpu rv64 \ + -smp 8 \ + -bios none \ + -kernel nuttx \ + -nographic + +## Convert Device Tree to text format +dtc \ + -o qemu-riscv64.dts \ + -O dts \ + -I dtb \ + qemu-riscv64.dtb +``` + +This produces Device Tree for QEMU RISC-V: [qemu-riscv64.dts](https://github.com/lupyuen/nuttx-star64/blob/main/qemu-riscv64.dts) + # TODO TODO: Port [__up_mtimer_initialize__](https://github.com/lupyuen2/wip-pinephone-nuttx/blob/star64a/arch/risc-v/src/qemu-rv/qemu_rv_timerisr.c#L151-L210) to Star64 diff --git a/qemu-riscv64.dtb b/qemu-riscv64.dtb new file mode 100644 index 0000000000000000000000000000000000000000..118637444fb368079fb2da410b3f1e145be94d56 GIT binary patch literal 1048576 zcmeI$yN)DDxd-qp;57HcauFBfpgF9BFuI^;Z>+G&!oUFoj&v-#raF73*siXos(NMz zhj{^9goS~423*7&pyQuM0AXSQ-#@FOrn>3f)vmP0NWYMxBO@a7i-=!l=cWGq*?;_{ z>%R7%UDv(Ybzk{?mEWrT`N}Um zcQ5T`T$^95oW9KADB+H`fyRqPjlG?3<~BONn64j9UKxUK!w<*RdPe`V+b?nMRX(je zY^2P=N#EEOt)6{9RrzRkJ|7RUyY7osAI6$JTCV%c;ehN{exqr(Ue0Pe_1bUrgYQ)R zJJ-|Irk1=--N&nMIDXMDmaC_eH(STprn9xAVBVUhkSSZaa55 zpRFFZq*i~m`^~SPRedzOx}FSY;d$RxwSVql-?Q4Ms{3P4Q>m0#|55pWmv2pUSCB`1HT12A`?9-!OQ!8Y;Cl$KaC(^}7tR z?~81Z``ZnJ*Q%k?p+W9Rt$vq5{;ytSgWOJU7`$E$mD-wf9poBs^}7sO|BL#+ko)!x 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z009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBly zK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF z5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk k1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C7J~V-U0l@tLRR910 literal 0 HcmV?d00001 diff --git a/qemu-riscv64.dts b/qemu-riscv64.dts new file mode 100644 index 0000000..83a90c1 --- /dev/null +++ b/qemu-riscv64.dts @@ -0,0 +1,355 @@ +/dts-v1/; + +/ { + #address-cells = <0x02>; + #size-cells = <0x02>; + compatible = "riscv-virtio"; + model = "riscv-virtio,qemu"; + + fw-cfg@10100000 { + dma-coherent; + reg = <0x00 0x10100000 0x00 0x18>; + compatible = "qemu,fw-cfg-mmio"; + }; + + flash@20000000 { + bank-width = <0x04>; + reg = <0x00 0x20000000 0x00 0x2000000 0x00 0x22000000 0x00 0x2000000>; + compatible = "cfi-flash"; + }; + + chosen { + bootargs = [00]; + stdout-path = "/soc/uart@10000000"; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x00 0x80000000 0x00 0x8000000>; + }; + + cpus { + #address-cells = <0x01>; + #size-cells = <0x00>; + timebase-frequency = <0x989680>; + + cpu@0 { + phandle = <0x0f>; + device_type = "cpu"; + reg = <0x00>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdcsuh"; + mmu-type = "riscv,sv48"; + + interrupt-controller { + #interrupt-cells = <0x01>; + interrupt-controller; + compatible = "riscv,cpu-intc"; + phandle = <0x10>; + }; + }; + + cpu@1 { + phandle = <0x0d>; + device_type = "cpu"; + reg = <0x01>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdcsuh"; + mmu-type = "riscv,sv48"; + + interrupt-controller { + #interrupt-cells = <0x01>; + interrupt-controller; + compatible = "riscv,cpu-intc"; + phandle = <0x0e>; + }; + }; + + cpu@2 { + phandle = <0x0b>; + device_type = "cpu"; + reg = <0x02>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdcsuh"; + mmu-type = "riscv,sv48"; + + interrupt-controller { + #interrupt-cells = <0x01>; + interrupt-controller; + compatible = "riscv,cpu-intc"; + phandle = <0x0c>; + }; + }; + + cpu@3 { + phandle = <0x09>; + device_type = "cpu"; + reg = <0x03>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdcsuh"; + mmu-type = "riscv,sv48"; + + interrupt-controller { + #interrupt-cells = <0x01>; + interrupt-controller; + compatible = "riscv,cpu-intc"; + phandle = <0x0a>; + }; + }; + + cpu@4 { + phandle = <0x07>; + device_type = "cpu"; + reg = <0x04>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdcsuh"; + mmu-type = "riscv,sv48"; + + interrupt-controller { + #interrupt-cells = <0x01>; + interrupt-controller; + compatible = "riscv,cpu-intc"; + phandle = <0x08>; + }; + }; + + cpu@5 { + phandle = <0x05>; + device_type = "cpu"; + reg = <0x05>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdcsuh"; + mmu-type = "riscv,sv48"; + + interrupt-controller { + #interrupt-cells = <0x01>; + interrupt-controller; + compatible = "riscv,cpu-intc"; + phandle = <0x06>; + }; + }; + + cpu@6 { + phandle = <0x03>; + device_type = "cpu"; + reg = <0x06>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdcsuh"; + mmu-type = "riscv,sv48"; + + interrupt-controller { + #interrupt-cells = <0x01>; + interrupt-controller; + compatible = "riscv,cpu-intc"; + phandle = <0x04>; + }; + }; + + cpu@7 { + phandle = <0x01>; + device_type = "cpu"; + reg = <0x07>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdcsuh"; + mmu-type = "riscv,sv48"; + + interrupt-controller { + #interrupt-cells = <0x01>; + interrupt-controller; + compatible = "riscv,cpu-intc"; + phandle = <0x02>; + }; + }; + + cpu-map { + + cluster0 { + + core0 { + cpu = <0x0f>; + }; + + core1 { + cpu = <0x0d>; + }; + + core2 { + cpu = <0x0b>; + }; + + core3 { + cpu = <0x09>; + }; + + core4 { + cpu = <0x07>; + }; + + core5 { + cpu = <0x05>; + }; + + core6 { + cpu = <0x03>; + }; + + core7 { + cpu = <0x01>; + }; + }; + }; + }; + + soc { + #address-cells = <0x02>; + #size-cells = <0x02>; + compatible = "simple-bus"; + ranges; + + rtc@101000 { + interrupts = <0x0b>; + interrupt-parent = <0x11>; + reg = <0x00 0x101000 0x00 0x1000>; + compatible = "google,goldfish-rtc"; + }; + + uart@10000000 { + interrupts = <0x0a>; + interrupt-parent = <0x11>; + clock-frequency = "\08@"; + reg = <0x00 0x10000000 0x00 0x100>; + compatible = "ns16550a"; + }; + + poweroff { + value = <0x5555>; + offset = <0x00>; + regmap = <0x12>; + compatible = "syscon-poweroff"; + }; + + reboot { + value = <0x7777>; + offset = <0x00>; + regmap = <0x12>; + compatible = "syscon-reboot"; + }; + + test@100000 { + phandle = <0x12>; + reg = <0x00 0x100000 0x00 0x1000>; + compatible = "sifive,test1\0sifive,test0\0syscon"; + }; + + pci@30000000 { + interrupt-map-mask = <0x1800 0x00 0x00 0x07>; + interrupt-map = <0x00 0x00 0x00 0x01 0x11 0x20 0x00 0x00 0x00 0x02 0x11 0x21 0x00 0x00 0x00 0x03 0x11 0x22 0x00 0x00 0x00 0x04 0x11 0x23 0x800 0x00 0x00 0x01 0x11 0x21 0x800 0x00 0x00 0x02 0x11 0x22 0x800 0x00 0x00 0x03 0x11 0x23 0x800 0x00 0x00 0x04 0x11 0x20 0x1000 0x00 0x00 0x01 0x11 0x22 0x1000 0x00 0x00 0x02 0x11 0x23 0x1000 0x00 0x00 0x03 0x11 0x20 0x1000 0x00 0x00 0x04 0x11 0x21 0x1800 0x00 0x00 0x01 0x11 0x23 0x1800 0x00 0x00 0x02 0x11 0x20 0x1800 0x00 0x00 0x03 0x11 0x21 0x1800 0x00 0x00 0x04 0x11 0x22>; + ranges = <0x1000000 0x00 0x00 0x00 0x3000000 0x00 0x10000 0x2000000 0x00 0x40000000 0x00 0x40000000 0x00 0x40000000 0x3000000 0x04 0x00 0x04 0x00 0x04 0x00>; + reg = <0x00 0x30000000 0x00 0x10000000>; + dma-coherent; + bus-range = <0x00 0xff>; + linux,pci-domain = <0x00>; + device_type = "pci"; + compatible = "pci-host-ecam-generic"; + #size-cells = <0x02>; + #interrupt-cells = <0x01>; + #address-cells = <0x03>; + }; + + virtio_mmio@10008000 { + interrupts = <0x08>; + interrupt-parent = <0x11>; + reg = <0x00 0x10008000 0x00 0x1000>; + compatible = "virtio,mmio"; + }; + + virtio_mmio@10007000 { + interrupts = <0x07>; + interrupt-parent = <0x11>; + reg = <0x00 0x10007000 0x00 0x1000>; + compatible = "virtio,mmio"; + }; + + virtio_mmio@10006000 { + interrupts = <0x06>; + interrupt-parent = <0x11>; + reg = <0x00 0x10006000 0x00 0x1000>; + compatible = "virtio,mmio"; + }; + + virtio_mmio@10005000 { + interrupts = <0x05>; + interrupt-parent = <0x11>; + reg = <0x00 0x10005000 0x00 0x1000>; + compatible = "virtio,mmio"; + }; + + virtio_mmio@10004000 { + interrupts = <0x04>; + interrupt-parent = <0x11>; + reg = <0x00 0x10004000 0x00 0x1000>; + compatible = "virtio,mmio"; + }; + + virtio_mmio@10003000 { + interrupts = <0x03>; + interrupt-parent = <0x11>; + reg = <0x00 0x10003000 0x00 0x1000>; + compatible = "virtio,mmio"; + }; + + virtio_mmio@10002000 { + interrupts = <0x02>; + interrupt-parent = <0x11>; + reg = <0x00 0x10002000 0x00 0x1000>; + compatible = "virtio,mmio"; + }; + + virtio_mmio@10001000 { + interrupts = <0x01>; + interrupt-parent = <0x11>; + reg = <0x00 0x10001000 0x00 0x1000>; + compatible = "virtio,mmio"; + }; + + plic@c000000 { + phandle = <0x11>; + riscv,ndev = <0x35>; + reg = <0x00 0xc000000 0x00 0x600000>; + interrupts-extended = <0x10 0x0b 0x10 0x09 0x0e 0x0b 0x0e 0x09 0x0c 0x0b 0x0c 0x09 0x0a 0x0b 0x0a 0x09 0x08 0x0b 0x08 0x09 0x06 0x0b 0x06 0x09 0x04 0x0b 0x04 0x09 0x02 0x0b 0x02 0x09>; + interrupt-controller; + compatible = "sifive,plic-1.0.0\0riscv,plic0"; + #interrupt-cells = <0x01>; + }; + + sswi@2f00000 { + #interrupt-cells = <0x00>; + interrupt-controller; + interrupts-extended = <0x10 0x01 0x0e 0x01 0x0c 0x01 0x0a 0x01 0x08 0x01 0x06 0x01 0x04 0x01 0x02 0x01>; + reg = <0x00 0x2f00000 0x00 0x4000>; + compatible = "riscv,aclint-sswi"; + }; + + mtimer@2004000 { + interrupts-extended = <0x10 0x07 0x0e 0x07 0x0c 0x07 0x0a 0x07 0x08 0x07 0x06 0x07 0x04 0x07 0x02 0x07>; + reg = <0x00 0x200bff8 0x00 0x4008 0x00 0x2004000 0x00 0x7ff8>; + compatible = "riscv,aclint-mtimer"; + }; + + mswi@2000000 { + #interrupt-cells = <0x00>; + interrupt-controller; + interrupts-extended = <0x10 0x03 0x0e 0x03 0x0c 0x03 0x0a 0x03 0x08 0x03 0x06 0x03 0x04 0x03 0x02 0x03>; + reg = <0x00 0x2000000 0x00 0x4000>; + compatible = "riscv,aclint-mswi"; + }; + }; +};