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https://github.com/lupyuen/nuttx-star64.git
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IRQ 57 OK yay!
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1 changed files with 131 additions and 526 deletions
657
README.md
657
README.md
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@ -3810,6 +3810,36 @@ Star64 UART is [RISC-V IRQ 32](https://doc-en.rvspace.org/VisionFive2/DG_UART/JH
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CONFIG_16550_UART0_IRQ=57
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```
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Check the Device Tree...
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```text
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dtc \
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-o jh7110-visionfive-v2.dts \
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-O dts \
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-I dtb \
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jh7110-visionfive-v2.dtb
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```
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Which produces [jh7110-visionfive-v2.dts](https://github.com/lupyuen/nuttx-star64/blob/main/jh7110-visionfive-v2.dts)
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UART0 is indeed IRQ 32: [jh7110-visionfive-v2.dts](https://github.com/lupyuen/nuttx-star64/blob/main/jh7110-visionfive-v2.dts#L619-L631)
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```text
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serial@10000000 {
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compatible = "snps,dw-apb-uart";
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reg = <0x00 0x10000000 0x00 0x10000>;
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reg-io-width = <0x04>;
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reg-shift = <0x02>;
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clocks = <0x08 0x92 0x08 0x91>;
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clock-names = "baudclk\0apb_pclk";
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resets = <0x21 0x53 0x21 0x54>;
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interrupts = <0x20>;
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <0x24>;
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};
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```
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[JH7110 Interrupt Connections](https://doc-en.rvspace.org/JH7110/TRM/JH7110_TRM/interrupt_connections.html) says that Global Interrupts are 0 to 126 (127 total interrupts)
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From [qemu-rv/irq.h](https://github.com/lupyuen2/wip-pinephone-nuttx/blob/star64d/arch/risc-v/include/qemu-rv/irq.h#L31-L40):
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@ -3841,78 +3871,27 @@ void up_irqinitialize(void)
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}
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```
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Check the Device Tree...
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Needs fixing: [qemu_rv_irq.c](https://github.com/lupyuen2/wip-pinephone-nuttx/blob/star64d/arch/risc-v/src/qemu-rv/qemu_rv_irq.c#L143-L198)
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```text
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dtc \
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-o jh7110-visionfive-v2.dts \
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-O dts \
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-I dtb \
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jh7110-visionfive-v2.dtb
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```c
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void up_enable_irq(int irq)
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{
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...
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else if (irq > RISCV_IRQ_EXT)
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{
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extirq = irq - RISCV_IRQ_EXT;
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_info("extirq=%d, RISCV_IRQ_EXT=%d\n", extirq, RISCV_IRQ_EXT);////
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/* Set enable bit for the irq */
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if (0 <= extirq && extirq <= 63) ////TODO: Why 63?
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{
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modifyreg32(QEMU_RV_PLIC_ENABLE1 + (4 * (extirq / 32)),
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0, 1 << (extirq % 32));
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}
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```
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Which produces [jh7110-visionfive-v2.dts](https://github.com/lupyuen/nuttx-star64/blob/main/jh7110-visionfive-v2.dts)
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UART0 is indeed IRQ 32: [jh7110-visionfive-v2.dts](https://github.com/lupyuen/nuttx-star64/blob/main/jh7110-visionfive-v2.dts#L619-L631)
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```text
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serial@10000000 {
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compatible = "snps,dw-apb-uart";
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reg = <0x00 0x10000000 0x00 0x10000>;
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reg-io-width = <0x04>;
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reg-shift = <0x02>;
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clocks = <0x08 0x92 0x08 0x91>;
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clock-names = "baudclk\0apb_pclk";
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resets = <0x21 0x53 0x21 0x54>;
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interrupts = <0x20>;
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <0x24>;
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};
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```
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Try [UART0 RISC-V IRQ 27](https://doc-en.rvspace.org/JH7110/TRM/JH7110_TRM/interrupt_connections.html), which is NuttX IRQ 52.
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```bash
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CONFIG_16550_UART0_IRQ=52
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```
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Also no response...
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```text
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clk u5_dw_i2c_clk_core already disabled
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clk u5_dw_i2c_clk_apb already disabled
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123067BCnx_start: Entry
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up_irq_enable:
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up_enable_irq: irq=17
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up_enable_irq: RISCV_IRQ_SOFT=17
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uart_register: Registering /dev/console
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uart_register: Registering /dev/ttyS0
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up_enable_irq: irq=52
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up_enable_irq: extirq=27, RISCV_IRQ_EXT=25
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work_start_lowpri: Starting low-priority kernel worker thread(s)
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board_late_initialize:
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nx_start_application: Starting init task: /system/bin/init
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elf_symname: Symbol has no name
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elf_symvalue: SHN_UNDEF: Failed to get symbol name: -3
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elf_relocateadd: Section 2 reloc 2: Undefined symbol[0] has no name: -3
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nx_start_application: ret=3
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up_exit: TCB=0x404088d0 exiting
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###############uart_write (0xc0200428):
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0000 2a 2a 2a 6d 61 69 6e 0a ***main.
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AAAAAAAAAD#####uart_write (0xc000a610):
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0000 0a 4e 75 74 74 53 68 65 6c 6c 20 28 4e 53 48 29 .NuttShell (NSH)
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0010 20 4e 75 74 74 58 2d 31 32 2e 30 2e 33 0a NuttX-12.0.3.
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AAAAAAAAAAAAAAAuart_write (0xc0015338):
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0000 6e 73 68 3e 20 nsh>
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AAAAAD#uart_write (0xc0015310):
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0000 1b 5b 4b .[K
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AAAD#nx_start: CPU0: Beginning Idle Loop
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```
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TODO: Check [PLIC Code](https://github.com/lupyuen2/wip-pinephone-nuttx/blob/star64d/arch/risc-v/src/qemu-rv/qemu_rv_irq.c#L45-L214) based on [PLIC Spec](https://github.com/riscv/riscv-plic-spec/blob/master/riscv-plic.adoc)
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TODO: What is a PLIC Context? Why context is 0 for Machine Mode, 1 for Supervisor Mode?
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We update the [PLIC Code](https://github.com/lupyuen2/wip-pinephone-nuttx/blob/star64d/arch/risc-v/src/qemu-rv/qemu_rv_irq.c#L45-L214) based on [PLIC Spec](https://github.com/riscv/riscv-plic-spec/blob/master/riscv-plic.adoc)
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From [SiFive U74-MC Core Complex Manual](https://starfivetech.com/uploads/u74mc_core_complex_manual_21G1.pdf):
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@ -3941,9 +3920,12 @@ Page 193: PLIC Memory Map
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| 0x0C20_8000 | 4B | RW | Hart 4 S-Mode priority threshold
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| 0x0C20_8004 | 4B | RW | Hart 4 S-Mode claim/complete
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From the above doc...
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- Hart 0: S7 Core
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- Harts 1 to 4: U7 Cores
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According to OpenSBI, we are now running on Hart 1. (NuttX thinks it's Hart 0)
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According to [U74 Memory Map](https://doc-en.rvspace.org/JH7110/TRM/JH7110_TRM/u74_memory_map.html):
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```text
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@ -3958,6 +3940,37 @@ Which is correct: [qemu_rv_memorymap.h](https://github.com/lupyuen2/wip-pinephon
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#define QEMU_RV_PLIC_BASE 0x0c000000
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```
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We fix the PLIC Addresses: [qemu_rv_plic.h](https://github.com/lupyuen2/wip-pinephone-nuttx/blob/star64d/arch/risc-v/src/qemu-rv/hardware/qemu_rv_plic.h#L33-L59)
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```c
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// | 0x0C00_0004 | 4B | RW | Source 1 priority
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#define QEMU_RV_PLIC_PRIORITY (QEMU_RV_PLIC_BASE + 0x000000)
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// | 0x0C00_1000 | 4B | RO | Start of pending array
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#define QEMU_RV_PLIC_PENDING1 (QEMU_RV_PLIC_BASE + 0x001000)
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// Previously:
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// #define QEMU_RV_PLIC_PRIORITY (QEMU_RV_PLIC_BASE + 0x000000)
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// #define QEMU_RV_PLIC_PENDING1 (QEMU_RV_PLIC_BASE + 0x001000)
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#ifdef CONFIG_ARCH_USE_S_MODE
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// | 0x0C00_2100 | 4B | RW | Start Hart 1 S-Mode interrupt enables
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# define QEMU_RV_PLIC_ENABLE1 (QEMU_RV_PLIC_BASE + 0x002100)
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# define QEMU_RV_PLIC_ENABLE2 (QEMU_RV_PLIC_BASE + 0x002104)
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// | 0x0C20_2000 | 4B | RW | Hart 1 S-Mode priority threshold
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# define QEMU_RV_PLIC_THRESHOLD (QEMU_RV_PLIC_BASE + 0x202000)
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// | 0x0C20_2004 | 4B | RW | Hart 1 S-Mode claim/complete
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# define QEMU_RV_PLIC_CLAIM (QEMU_RV_PLIC_BASE + 0x202004)
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// Previously:
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// # define QEMU_RV_PLIC_ENABLE1 (QEMU_RV_PLIC_BASE + 0x002080)
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// # define QEMU_RV_PLIC_ENABLE2 (QEMU_RV_PLIC_BASE + 0x002084)
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// # define QEMU_RV_PLIC_THRESHOLD (QEMU_RV_PLIC_BASE + 0x201000)
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// # define QEMU_RV_PLIC_CLAIM (QEMU_RV_PLIC_BASE + 0x201004)
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```
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From [SiFive Interrupt Cookbook](https://sifive.cdn.prismic.io/sifive/0d163928-2128-42be-a75a-464df65e04e0_sifive-interrupt-cookbook.pdf):
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Machine Mode:
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@ -3979,14 +3992,14 @@ if a CPU is in Machine mode. While operating in Supervisor mode, a CPU does not
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[What is mideleg](https://five-embeddev.com/riscv-isa-manual/latest/machine.html#machine-trap-delegation-registers-medeleg-and-mideleg)
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From [OpenSBI Log](https://lupyuen.github.io/articles/linux#appendix-opensbi-log-for-star64):
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From [OpenSBI Log](https://lupyuen.github.io/articles/linux#appendix-opensbi-log-for-star64): MIDELEG and MEDELEG are...
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```bash
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Boot HART MIDELEG: 0x0000000000000222
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Boot HART MEDELEG: 0x000000000000b109
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```
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From [csr.h](https://github.com/lupyuen2/wip-pinephone-nuttx/blob/star64d/arch/risc-v/include/csr.h#L343-L346):
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Which have the following bits: [csr.h](https://github.com/lupyuen2/wip-pinephone-nuttx/blob/star64d/arch/risc-v/include/csr.h#L343-L346):
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```c
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#define MIP_SSIP (0x1 << 1)
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@ -4020,6 +4033,53 @@ Which is same as NuttX SBI: [nuttsbi/sbi_start.c](https://github.com/lupyuen2/wi
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WRITE_CSR(medeleg, reg);
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```
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From [JH7110 Interrupt Connections](https://doc-en.rvspace.org/JH7110/TRM/JH7110_TRM/interrupt_connections.html): `u0_uart` is at `global_interrupts[27]`
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Which is correct because [SiFive U74-MC Core Complex Manual](https://starfivetech.com/uploads/u74mc_core_complex_manual_21G1.pdf) (Page 198) says that `global_interrupts[0]` is PLIC Interrupt ID 5.
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Thus `u0_uart`(IRQ 32) is at `global_interrupts[27]`.
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IRQ 57 is now OK yay! But it's not triggered by UART Input. Why?
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```text
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123067BCnx_start: Entry
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up_irq_enable:
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up_enable_irq: irq=17
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up_enable_irq: RISCV_IRQ_SOFT=17
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uart_register: Registering /dev/console
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uart_register: Registering /dev/ttyS0
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up_enable_irq: irq=57
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up_enable_irq: extirq=32, RISCV_IRQ_EXT=25
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$%^&riscv_doirq: irq=57
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#*$%^&riscv_doirq: irq=57
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#*$%^&riscv_doirq: irq=57
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#*$%^&riscv_doirq: irq=57
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#*$%^&riscv_doirq: irq=57
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...
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#*$%^&riscv_doirq: irq=57
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#*$%^&riscv_doirq: irq=57
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#*$%^&riscv_doirq: irq=57
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#*$%^&riscv_doirq: irq=57
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#*$%^&nx_start: CPU0: Beginning Idle Loop
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```
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TODO: Check why no UART Output
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```text
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123067BCnx_start: Entry
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up_irq_enable:
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up_enable_irq: irq=17
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up_enable_irq: RISCV_IRQ_SOFT=17
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uart_register: Registering /dev/console
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uart_register: Registering /dev/ttyS0
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up_enable_irq: irq=57
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up_enable_irq: extirq=32, RISCV_IRQ_EXT=25
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```
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TODO
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TODO: Check PolarFire Icicle
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https://lupyuen.github.io/articles/privilege#other-risc-v-ports-of-nuttx
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@ -4036,461 +4096,6 @@ TODO: Handle Machine Exception
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https://github.com/lupyuen2/wip-pinephone-nuttx/blob/star64d/arch/risc-v/src/qemu-rv/qemu_rv_exception_m.S#L64
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IRQ 57 OK yay!
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```text
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123067BCnx_start: Entry
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up_irq_enable:
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up_enable_irq: irq=17
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up_enable_irq: RISCV_IRQ_SOFT=17
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uart_register: Registering /dev/console
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uart_register: Registering /dev/ttyS0
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up_enable_irq: irq=57
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up_enable_irq: extirq=32, RISCV_IRQ_EXT=25
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```
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TODO
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```text
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123067BCnx_start: Entry
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up_irq_enable:
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up_enable_irq: irq=17
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up_enable_irq: RISCV_IRQ_SOFT=17
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uart_register: Registering /dev/console
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uart_register: Registering /dev/ttyS0
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up_enable_irq: irq=57
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up_enable_irq: extirq=32, RISCV_IRQ_EXT=25
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$%^&riscv_doirq: irq=57
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#*$%^&riscv_doirq: irq=57
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#*$%^&riscv_doirq: irq=57
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#*$%^&riscv_doirq: irq=57
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#*$%^&riscv_doirq: irq=57
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#*$%^&riscv_doirq: irq=57
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#*$%^&riscv_doirq: irq=57
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#*$%^&riscv_doirq: irq=57
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#*$%^&riscv_doirq: irq=57
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#*$%^&riscv_doirq: irq=57
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#*$%^&riscv_doirq: irq=57
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#*$%^&riscv_doirq: irq=57
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#*$%^&riscv_doirq: irq=57
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#*$%^&riscv_doirq: irq=57
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#*$%^&riscv_doirq: irq=57
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#*$%^&riscv_doirq: irq=57
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#*$%^&riscv_doirq: irq=57
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#*$%^&riscv_doirq: irq=57
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#*$%^&riscv_doirq: irq=57
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#*$%^&riscv_doirq: irq=57
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#*$%^&riscv_doirq: irq=57
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#*$%^&riscv_doirq: irq=57
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#*$%^&riscv_doirq: irq=57
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#*$%^&riscv_doirq: irq=57
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#*$%^&riscv_doirq: irq=57
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#*$%^&riscv_doirq: irq=57
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#*$%^&riscv_doirq: irq=57
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#*$%^&riscv_doirq: irq=57
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#*$%^&riscv_doirq: irq=57
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#*$%^&riscv_doirq: irq=57
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#*$%^&riscv_doirq: irq=57
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#*$%^&riscv_doirq: irq=57
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#*$%^&riscv_doirq: irq=57
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#*$%^&riscv_doirq: irq=57
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#*$%^&riscv_doirq: irq=57
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#*$%^&riscv_doirq: irq=57
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#*$%^&riscv_doirq: irq=57
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#*$%^&riscv_doirq: irq=57
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#*$%^&riscv_doirq: irq=57
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#*$%^&riscv_doirq: irq=57
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#*$%^&riscv_doirq: irq=57
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#*$%^&riscv_doirq: irq=57
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#*$%^&riscv_doirq: irq=57
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#*$%^&riscv_doirq: irq=57
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#*$%^&riscv_doirq: irq=57
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#*$%^&riscv_doirq: irq=57
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#*$%^&riscv_doirq: irq=57
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#*$%^&riscv_doirq: irq=57
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#*$%^&riscv_doirq: irq=57
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#*$%^&riscv_doirq: irq=57
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#*$%^&riscv_doirq: irq=57
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#*w$%^&riscv_doirq: irq=57
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#*o$%^&riscv_doirq: irq=57
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#*r$%^&riscv_doirq: irq=57
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#*k$%^&riscv_doirq: irq=57
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#*_$%^&riscv_doirq: irq=57
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#*s$%^&riscv_doirq: irq=57
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#*t$%^&riscv_doirq: irq=57
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#*a$%^&riscv_doirq: irq=57
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#*r$%^&riscv_doirq: irq=57
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#*t$%^&riscv_doirq: irq=57
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#*_$%^&riscv_doirq: irq=57
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#*l$%^&riscv_doirq: irq=57
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#*o$%^&riscv_doirq: irq=57
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#*w$%^&riscv_doirq: irq=57
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#*p$%^&riscv_doirq: irq=57
|
||||
#*r$%^&riscv_doirq: irq=57
|
||||
#*i$%^&riscv_doirq: irq=57
|
||||
#*:$%^&riscv_doirq: irq=57
|
||||
#* $%^&riscv_doirq: irq=57
|
||||
#*S$%^&riscv_doirq: irq=57
|
||||
#*t$%^&riscv_doirq: irq=57
|
||||
#*a$%^&riscv_doirq: irq=57
|
||||
#*r$%^&riscv_doirq: irq=57
|
||||
#*t$%^&riscv_doirq: irq=57
|
||||
#*i$%^&riscv_doirq: irq=57
|
||||
#*n$%^&riscv_doirq: irq=57
|
||||
#*g$%^&riscv_doirq: irq=57
|
||||
#* $%^&riscv_doirq: irq=57
|
||||
#*l$%^&riscv_doirq: irq=57
|
||||
#*o$%^&riscv_doirq: irq=57
|
||||
#*w$%^&riscv_doirq: irq=57
|
||||
#*-$%^&riscv_doirq: irq=57
|
||||
#*p$%^&riscv_doirq: irq=57
|
||||
#*r$%^&riscv_doirq: irq=57
|
||||
#*i$%^&riscv_doirq: irq=57
|
||||
#*o$%^&riscv_doirq: irq=57
|
||||
#*r$%^&riscv_doirq: irq=57
|
||||
#*i$%^&riscv_doirq: irq=57
|
||||
#*t$%^&riscv_doirq: irq=57
|
||||
#*y$%^&riscv_doirq: irq=57
|
||||
#* $%^&riscv_doirq: irq=57
|
||||
#*k$%^&riscv_doirq: irq=57
|
||||
#*e$%^&riscv_doirq: irq=57
|
||||
#*r$%^&riscv_doirq: irq=57
|
||||
#*n$%^&riscv_doirq: irq=57
|
||||
#*e$%^&riscv_doirq: irq=57
|
||||
#*l$%^&riscv_doirq: irq=57
|
||||
#* $%^&riscv_doirq: irq=57
|
||||
#*w$%^&riscv_doirq: irq=57
|
||||
#*o$%^&riscv_doirq: irq=57
|
||||
#*r$%^&riscv_doirq: irq=57
|
||||
#*k$%^&riscv_doirq: irq=57
|
||||
#*e$%^&riscv_doirq: irq=57
|
||||
#*r$%^&riscv_doirq: irq=57
|
||||
#* $%^&riscv_doirq: irq=57
|
||||
#*t$%^&riscv_doirq: irq=57
|
||||
#*h$%^&riscv_doirq: irq=57
|
||||
#*r$%^&riscv_doirq: irq=57
|
||||
#*e$%^&riscv_doirq: irq=57
|
||||
#*a$%^&riscv_doirq: irq=57
|
||||
#*d$%^&riscv_doirq: irq=57
|
||||
#*($%^&riscv_doirq: irq=57
|
||||
#*s$%^&riscv_doirq: irq=57
|
||||
#*)$%^&riscv_doirq: irq=57
|
||||
#*
|
||||
$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&riscv_doirq: irq=57
|
||||
#*$%^&nx_start: CPU0: Beginning Idle Loop
|
||||
```
|
||||
|
||||
# RAM Disk Address for RISC-V QEMU
|
||||
|
||||
Read the article...
|
||||
|
|
|
|||
Loading…
Reference in a new issue