mirror of
https://github.com/lupyuen/nuttx-star64.git
synced 2025-01-12 20:58:32 +08:00
2627 lines
65 KiB
Text
2627 lines
65 KiB
Text
/dts-v1/;
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/ {
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compatible = "starfive,visionfive-v2\0starfive,jh7110";
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#address-cells = <0x02>;
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#size-cells = <0x02>;
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model = "StarFive VisionFive V2";
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osc {
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compatible = "fixed-clock";
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#clock-cells = <0x00>;
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clock-frequency = <0x16e3600>;
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phandle = <0x0f>;
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};
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clk-ext-camera {
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compatible = "fixed-clock";
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#clock-cells = <0x00>;
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clock-frequency = <0x16e3600>;
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phandle = <0x31>;
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};
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gmac1_rmii_refin {
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compatible = "fixed-clock";
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#clock-cells = <0x00>;
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clock-frequency = <0x2faf080>;
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phandle = <0x10>;
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};
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gmac1_rgmii_rxin {
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compatible = "fixed-clock";
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#clock-cells = <0x00>;
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clock-frequency = <0x7735940>;
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phandle = <0x11>;
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};
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i2stx_bclk_ext {
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compatible = "fixed-clock";
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#clock-cells = <0x00>;
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clock-frequency = <0xbb8000>;
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phandle = <0x12>;
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};
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i2stx_lrck_ext {
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compatible = "fixed-clock";
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#clock-cells = <0x00>;
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clock-frequency = <0x2ee00>;
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phandle = <0x13>;
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};
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i2srx_bclk_ext {
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compatible = "fixed-clock";
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#clock-cells = <0x00>;
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clock-frequency = <0xbb8000>;
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phandle = <0x14>;
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};
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i2srx_lrck_ext {
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compatible = "fixed-clock";
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#clock-cells = <0x00>;
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clock-frequency = <0x2ee00>;
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phandle = <0x15>;
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};
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tdm_ext {
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compatible = "fixed-clock";
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#clock-cells = <0x00>;
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clock-frequency = <0x2ee0000>;
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phandle = <0x16>;
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};
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mclk_ext {
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compatible = "fixed-clock";
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#clock-cells = <0x00>;
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clock-frequency = <0xbb8000>;
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phandle = <0x17>;
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};
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jtag_tck_inner {
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compatible = "fixed-clock";
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#clock-cells = <0x00>;
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clock-frequency = <0x2faf080>;
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phandle = <0x18>;
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};
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bist_apb {
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compatible = "fixed-clock";
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#clock-cells = <0x00>;
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clock-frequency = <0x2faf080>;
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phandle = <0x19>;
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};
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gmac0_rmii_refin {
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compatible = "fixed-clock";
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#clock-cells = <0x00>;
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clock-frequency = <0x2faf080>;
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phandle = <0x1b>;
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};
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gmac0_rgmii_rxin {
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compatible = "fixed-clock";
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#clock-cells = <0x00>;
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clock-frequency = <0x7735940>;
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phandle = <0x1c>;
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};
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clk_rtc {
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compatible = "fixed-clock";
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#clock-cells = <0x00>;
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clock-frequency = <0x8000>;
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phandle = <0x1a>;
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};
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hdmitx0_pixelclk {
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compatible = "fixed-clock";
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#clock-cells = <0x00>;
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clock-frequency = <0x11b3dc40>;
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phandle = <0x1e>;
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};
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mipitx_dphy_rxesc {
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compatible = "fixed-clock";
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#clock-cells = <0x00>;
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clock-frequency = <0x989680>;
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phandle = <0x1f>;
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};
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mipitx_dphy_txbytehs {
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compatible = "fixed-clock";
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#clock-cells = <0x00>;
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clock-frequency = <0x11b3dc40>;
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phandle = <0x20>;
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};
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wm8960_mclk {
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compatible = "fixed-clock";
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#clock-cells = <0x00>;
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clock-frequency = <0x1770000>;
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};
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ac108_mclk {
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compatible = "fixed-clock";
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#clock-cells = <0x00>;
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clock-frequency = <0x16e3600>;
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};
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opp-table-0 {
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compatible = "operating-points-v2";
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opp-shared;
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phandle = <0x06>;
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opp-375000000 {
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opp-hz = <0x00 0x165a0bc0>;
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opp-microvolt = "\0\f5";
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};
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opp-500000000 {
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opp-hz = <0x00 0x1dcd6500>;
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opp-microvolt = "\0\f5";
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};
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opp-750000000 {
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opp-hz = <0x00 0x2cb41780>;
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opp-microvolt = "\0\f5";
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opp-suspend;
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};
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opp-1500000000 {
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opp-hz = <0x00 0x59682f00>;
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opp-microvolt = <0xfde80>;
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};
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opp-312500000 {
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opp-hz = <0x00 0x12a05f20>;
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opp-microvolt = "\0\f5";
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};
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opp-417000000 {
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opp-hz = <0x00 0x18daea40>;
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opp-microvolt = "\0\f5";
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};
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opp-625000000 {
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opp-hz = <0x00 0x2540be40>;
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opp-microvolt = "\0\f5";
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opp-suspend;
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};
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opp-1250000000 {
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opp-hz = <0x00 0x4a817c80>;
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opp-microvolt = <0xf4240>;
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};
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};
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cpus {
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#address-cells = <0x01>;
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#size-cells = <0x00>;
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timebase-frequency = "\0=\t";
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cpu-map {
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cluster0 {
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core0 {
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cpu = <0x01>;
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};
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core1 {
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cpu = <0x02>;
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};
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core2 {
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cpu = <0x03>;
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};
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core3 {
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cpu = <0x04>;
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};
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};
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};
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cpu@0 {
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compatible = "sifive,s7\0riscv";
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reg = <0x00>;
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d-cache-block-size = <0x40>;
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d-cache-sets = <0x40>;
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d-cache-size = <0x2000>;
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d-tlb-sets = <0x01>;
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d-tlb-size = <0x28>;
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device_type = "cpu";
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i-cache-block-size = <0x40>;
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i-cache-sets = <0x40>;
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i-cache-size = <0x4000>;
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i-tlb-sets = <0x01>;
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i-tlb-size = <0x28>;
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mmu-type = "riscv,sv39";
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next-level-cache = <0x05>;
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riscv,isa = "rv64imac_zba_zbb";
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tlb-split;
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#cooling-cells = <0x02>;
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status = "disabled";
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phandle = <0x27>;
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interrupt-controller {
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#interrupt-cells = <0x01>;
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compatible = "riscv,cpu-intc";
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interrupt-controller;
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phandle = <0x0a>;
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};
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};
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cpu@1 {
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compatible = "sifive,u74-mc\0riscv";
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reg = <0x01>;
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d-cache-block-size = <0x40>;
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d-cache-sets = <0x40>;
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d-cache-size = <0x8000>;
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d-tlb-sets = <0x01>;
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d-tlb-size = <0x28>;
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device_type = "cpu";
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i-cache-block-size = <0x40>;
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i-cache-sets = <0x40>;
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i-cache-size = <0x8000>;
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i-tlb-sets = <0x01>;
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i-tlb-size = <0x28>;
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mmu-type = "riscv,sv39";
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next-level-cache = <0x05>;
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riscv,isa = "rv64imafdc_zba_zbb";
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tlb-split;
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#cooling-cells = <0x02>;
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status = "okay";
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operating-points-v2 = <0x06>;
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cpu-supply = <0x07>;
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clocks = <0x08 0x01>;
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clock-names = "cpu";
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phandle = <0x01>;
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interrupt-controller {
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#interrupt-cells = <0x01>;
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compatible = "riscv,cpu-intc";
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interrupt-controller;
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phandle = <0x0b>;
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};
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};
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cpu@2 {
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compatible = "sifive,u74-mc\0riscv";
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reg = <0x02>;
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d-cache-block-size = <0x40>;
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d-cache-sets = <0x40>;
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d-cache-size = <0x8000>;
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d-tlb-sets = <0x01>;
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d-tlb-size = <0x28>;
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device_type = "cpu";
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i-cache-block-size = <0x40>;
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i-cache-sets = <0x40>;
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i-cache-size = <0x8000>;
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i-tlb-sets = <0x01>;
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i-tlb-size = <0x28>;
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mmu-type = "riscv,sv39";
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next-level-cache = <0x05>;
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riscv,isa = "rv64imafdc_zba_zbb";
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tlb-split;
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#cooling-cells = <0x02>;
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status = "okay";
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operating-points-v2 = <0x06>;
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phandle = <0x02>;
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interrupt-controller {
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#interrupt-cells = <0x01>;
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compatible = "riscv,cpu-intc";
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interrupt-controller;
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phandle = <0x0c>;
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};
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};
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cpu@3 {
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compatible = "sifive,u74-mc\0riscv";
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reg = <0x03>;
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d-cache-block-size = <0x40>;
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d-cache-sets = <0x40>;
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d-cache-size = <0x8000>;
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d-tlb-sets = <0x01>;
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d-tlb-size = <0x28>;
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device_type = "cpu";
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i-cache-block-size = <0x40>;
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i-cache-sets = <0x40>;
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i-cache-size = <0x8000>;
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i-tlb-sets = <0x01>;
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i-tlb-size = <0x28>;
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mmu-type = "riscv,sv39";
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next-level-cache = <0x05>;
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riscv,isa = "rv64imafdc_zba_zbb";
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tlb-split;
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#cooling-cells = <0x02>;
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status = "okay";
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operating-points-v2 = <0x06>;
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phandle = <0x03>;
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interrupt-controller {
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#interrupt-cells = <0x01>;
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compatible = "riscv,cpu-intc";
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interrupt-controller;
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phandle = <0x0d>;
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};
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};
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cpu@4 {
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compatible = "sifive,u74-mc\0riscv";
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reg = <0x04>;
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d-cache-block-size = <0x40>;
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d-cache-sets = <0x40>;
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d-cache-size = <0x8000>;
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d-tlb-sets = <0x01>;
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d-tlb-size = <0x28>;
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device_type = "cpu";
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i-cache-block-size = <0x40>;
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i-cache-sets = <0x40>;
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i-cache-size = <0x8000>;
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i-tlb-sets = <0x01>;
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i-tlb-size = <0x28>;
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mmu-type = "riscv,sv39";
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next-level-cache = <0x05>;
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riscv,isa = "rv64imafdc_zba_zbb";
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tlb-split;
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#cooling-cells = <0x02>;
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status = "okay";
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operating-points-v2 = <0x06>;
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phandle = <0x04>;
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interrupt-controller {
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#interrupt-cells = <0x01>;
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compatible = "riscv,cpu-intc";
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interrupt-controller;
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phandle = <0x0e>;
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};
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};
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};
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soc {
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compatible = "simple-bus";
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interrupt-parent = <0x09>;
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#address-cells = <0x02>;
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#size-cells = <0x02>;
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#clock-cells = <0x01>;
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ranges;
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cache-controller@2010000 {
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compatible = "sifive,fu740-c000-ccache\0cache";
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reg = <0x00 0x2010000 0x00 0x4000 0x00 0x8000000 0x00 0x2000000>;
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reg-names = "control\0sideband";
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interrupts = <0x01 0x03 0x04 0x02>;
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cache-block-size = <0x40>;
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cache-level = <0x02>;
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cache-sets = <0x800>;
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cache-size = <0x200000>;
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cache-unified;
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phandle = <0x05>;
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};
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aon_syscon@17010000 {
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compatible = "syscon";
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reg = <0x00 0x17010000 0x00 0x1000>;
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phandle = <0x39>;
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};
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multi-phyctrl@10210000 {
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compatible = "starfive,phyctrl";
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reg = <0x00 0x10210000 0x00 0x10000>;
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phandle = <0x45>;
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};
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pcie1-phyctrl@10220000 {
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compatible = "starfive,phyctrl";
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reg = <0x00 0x10220000 0x00 0x10000>;
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phandle = <0x48>;
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};
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stg_syscon@10240000 {
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compatible = "syscon";
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reg = <0x00 0x10240000 0x00 0x1000>;
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phandle = <0x23>;
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};
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sys_syscon@13030000 {
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compatible = "syscon";
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reg = <0x00 0x13030000 0x00 0x1000>;
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phandle = <0x1d>;
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};
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clint@2000000 {
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compatible = "riscv,clint0";
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reg = <0x00 0x2000000 0x00 0x10000>;
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reg-names = "control";
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interrupts-extended = <0x0a 0x03 0x0a 0x07 0x0b 0x03 0x0b 0x07 0x0c 0x03 0x0c 0x07 0x0d 0x03 0x0d 0x07 0x0e 0x03 0x0e 0x07>;
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#interrupt-cells = <0x01>;
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};
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plic@c000000 {
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compatible = "riscv,plic0";
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reg = <0x00 0xc000000 0x00 0x4000000>;
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reg-names = "control";
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interrupts-extended = <0x0a 0x0b 0x0b 0x0b 0x0b 0x09 0x0c 0x0b 0x0c 0x09 0x0d 0x0b 0x0d 0x09 0x0e 0x0b 0x0e 0x09>;
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interrupt-controller;
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#interrupt-cells = <0x01>;
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riscv,max-priority = <0x07>;
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riscv,ndev = <0x88>;
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phandle = <0x09>;
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};
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clock-controller {
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compatible = "starfive,jh7110-clkgen";
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reg = <0x00 0x13020000 0x00 0x10000 0x00 0x10230000 0x00 0x10000 0x00 0x17000000 0x00 0x10000>;
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reg-names = "sys\0stg\0aon";
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clocks = <0x0f 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1a 0x1b 0x1c>;
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clock-names = "osc\0gmac1_rmii_refin\0gmac1_rgmii_rxin\0i2stx_bclk_ext\0i2stx_lrck_ext\0i2srx_bclk_ext\0i2srx_lrck_ext\0tdm_ext\0mclk_ext\0jtag_tck_inner\0bist_apb\0clk_rtc\0gmac0_rmii_refin\0gmac0_rgmii_rxin";
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#clock-cells = <0x01>;
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starfive,sys-syscon = <0x1d 0x18 0x1c 0x20 0x24 0x28 0x2c 0x30 0x34>;
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status = "okay";
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phandle = <0x08>;
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};
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clock-controller@295C0000 {
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compatible = "starfive,jh7110-clk-vout";
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reg = <0x00 0x295c0000 0x00 0x10000>;
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reg-names = "vout";
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clocks = <0x1e 0x1f 0x20 0x08 0x3a 0x08 0x3d>;
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clock-names = "hdmitx0_pixelclk\0mipitx_dphy_rxesc\0mipitx_dphy_txbytehs\0vout_src\0vout_top_ahb";
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resets = <0x21 0x2b>;
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reset-names = "vout_src";
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#clock-cells = <0x01>;
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power-domains = <0x22 0x04>;
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status = "okay";
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phandle = <0x4e>;
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};
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clock-controller@19810000 {
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compatible = "starfive,jh7110-clk-isp";
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reg = <0x00 0x19810000 0x00 0x10000>;
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reg-names = "isp";
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#clock-cells = <0x01>;
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clocks = <0x08 0x10a 0x08 0x33 0x08 0x34 0x08 0x35>;
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clock-names = "u0_dom_isp_top_clk_dom_isp_top_clk_dvp\0u0_dom_isp_top_clk_dom_isp_top_clk_ispcore_2x\0u0_dom_isp_top_clk_dom_isp_top_clk_isp_axi\0u0_sft7110_noc_bus_clk_isp_axi";
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resets = <0x21 0x29 0x21 0x2a 0x21 0x1c>;
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reset-names = "rst_isp_top_n\0rst_isp_top_axi\0rst_isp_noc_bus_n";
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power-domains = <0x22 0x05>;
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status = "okay";
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phandle = <0x38>;
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};
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spi@13010000 {
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compatible = "cdns,qspi-nor";
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
reg = <0x00 0x13010000 0x00 0x10000 0x00 0x21000000 0x00 0x400000>;
|
|
interrupts = <0x19>;
|
|
clocks = <0x08 0x5a 0x08 0x58 0x08 0x0a 0x08 0x57 0x08 0x59>;
|
|
clock-names = "clk_ref\0clk_apb\0ahb1\0clk_ahb\0clk_src";
|
|
resets = <0x21 0x3e 0x21 0x3d 0x21 0x3f>;
|
|
cdns,fifo-depth = <0x100>;
|
|
cdns,fifo-width = <0x04>;
|
|
cdns,trigger-address = <0x00>;
|
|
spi-max-frequency = <0xee6b280>;
|
|
|
|
nor-flash@0 {
|
|
compatible = "jedec,spi-nor";
|
|
reg = <0x00>;
|
|
cdns,read-delay = <0x05>;
|
|
spi-max-frequency = <0x5f5e100>;
|
|
cdns,tshsl-ns = <0x01>;
|
|
cdns,tsd2d-ns = <0x01>;
|
|
cdns,tchsh-ns = <0x01>;
|
|
cdns,tslch-ns = <0x01>;
|
|
|
|
partitions {
|
|
compatible = "fixed-partitions";
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x01>;
|
|
|
|
spl@0 {
|
|
reg = <0x00 0x40000>;
|
|
};
|
|
|
|
uboot@100000 {
|
|
reg = <0x100000 0x300000>;
|
|
};
|
|
|
|
data@f00000 {
|
|
reg = <0xf00000 0x100000>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
otp@17050000 {
|
|
compatible = "starfive,jh7110-otp";
|
|
reg = <0x00 0x17050000 0x00 0x10000>;
|
|
clock-frequency = "\0=\t";
|
|
clocks = <0x08 0xe4>;
|
|
clock-names = "apb";
|
|
};
|
|
|
|
usbdrd {
|
|
compatible = "starfive,jh7110-cdns3";
|
|
reg = <0x00 0x10210000 0x00 0x1000 0x00 0x10200000 0x00 0x1000>;
|
|
clocks = <0x08 0x5f 0x08 0xc4 0x08 0xc2 0x08 0xc3 0x08 0xbf 0x08 0xc1 0x08 0xc0>;
|
|
clock-names = "125m\0app\0lpm\0stb\0apb\0axi\0utmi";
|
|
resets = <0x21 0x8a 0x21 0x88 0x21 0x87 0x21 0x89>;
|
|
reset-names = "pwrup\0apb\0axi\0utmi";
|
|
starfive,stg-syscon = <0x23 0x04 0xc4 0x148 0x1f4>;
|
|
starfive,sys-syscon = <0x1d 0x18>;
|
|
status = "okay";
|
|
#address-cells = <0x02>;
|
|
#size-cells = <0x02>;
|
|
#interrupt-cells = <0x01>;
|
|
ranges;
|
|
starfive,usb2-only;
|
|
dr_mode = "peripheral";
|
|
|
|
usb@10100000 {
|
|
compatible = "cdns,usb3";
|
|
reg = <0x00 0x10100000 0x00 0x10000 0x00 0x10110000 0x00 0x10000 0x00 0x10120000 0x00 0x10000>;
|
|
reg-names = "otg\0xhci\0dev";
|
|
interrupts = <0x64 0x6c 0x6e>;
|
|
interrupt-names = "host\0peripheral\0otg";
|
|
phy-names = "cdns3,usb3-phy\0cnds3,usb2-phy";
|
|
maximum-speed = "super-speed";
|
|
};
|
|
};
|
|
|
|
timer@13050000 {
|
|
compatible = "starfive,jh7110-timers";
|
|
reg = <0x00 0x13050000 0x00 0x10000>;
|
|
interrupts = <0x45 0x46 0x47 0x48>;
|
|
interrupt-names = "timer0\0timer1\0timer2\0timer3";
|
|
clocks = <0x08 0x7d 0x08 0x7e 0x08 0x7f 0x08 0x80 0x08 0x7c>;
|
|
clock-names = "timer0\0timer1\0timer2\0timer3\0apb_clk";
|
|
resets = <0x21 0x76 0x21 0x77 0x21 0x78 0x21 0x79 0x21 0x75>;
|
|
reset-names = "timer0\0timer1\0timer2\0timer3\0apb_rst";
|
|
clock-frequency = <0x16e3600>;
|
|
status = "okay";
|
|
};
|
|
|
|
wdog@13070000 {
|
|
compatible = "starfive,jh7110-wdt";
|
|
reg = <0x00 0x13070000 0x00 0x10000>;
|
|
interrupts = <0x44>;
|
|
interrupt-names = "wdog";
|
|
clocks = <0x08 0x7b 0x08 0x7a>;
|
|
clock-names = "core_clk\0apb_clk";
|
|
resets = <0x21 0x6d 0x21 0x6e>;
|
|
reset-names = "rst_apb\0rst_core";
|
|
timeout-sec = <0x0f>;
|
|
status = "okay";
|
|
};
|
|
|
|
rtc@17040000 {
|
|
compatible = "starfive,jh7110-rtc";
|
|
reg = <0x00 0x17040000 0x00 0x10000>;
|
|
interrupts = <0x0a 0x0b 0x0c>;
|
|
interrupt-names = "rtc_ms_pulse\0rtc_sec_pulse\0rtc";
|
|
clocks = <0x08 0xe5 0x08 0xe8>;
|
|
clock-names = "pclk\0cal_clk";
|
|
resets = <0x21 0xa7 0x21 0xa5 0x21 0xa6>;
|
|
reset-names = "rst_osc\0rst_apb\0rst_cal";
|
|
rtc,cal-clock-freq = <0xf4240>;
|
|
status = "okay";
|
|
};
|
|
|
|
power-controller@17030000 {
|
|
compatible = "starfive,jh7110-pmu";
|
|
reg = <0x00 0x17030000 0x00 0x10000>;
|
|
interrupts = <0x6f>;
|
|
#power-domain-cells = <0x01>;
|
|
status = "okay";
|
|
phandle = <0x22>;
|
|
};
|
|
|
|
serial@10000000 {
|
|
compatible = "snps,dw-apb-uart";
|
|
reg = <0x00 0x10000000 0x00 0x10000>;
|
|
reg-io-width = <0x04>;
|
|
reg-shift = <0x02>;
|
|
clocks = <0x08 0x92 0x08 0x91>;
|
|
clock-names = "baudclk\0apb_pclk";
|
|
resets = <0x21 0x53 0x21 0x54>;
|
|
interrupts = <0x20>;
|
|
status = "okay";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x24>;
|
|
};
|
|
|
|
serial@10010000 {
|
|
compatible = "snps,dw-apb-uart";
|
|
reg = <0x00 0x10010000 0x00 0x10000>;
|
|
reg-io-width = <0x04>;
|
|
reg-shift = <0x02>;
|
|
clocks = <0x08 0x94 0x08 0x93>;
|
|
clock-names = "baudclk\0apb_pclk";
|
|
resets = <0x21 0x55 0x21 0x56>;
|
|
interrupts = <0x21>;
|
|
status = "disabled";
|
|
};
|
|
|
|
serial@10020000 {
|
|
compatible = "snps,dw-apb-uart";
|
|
reg = <0x00 0x10020000 0x00 0x10000>;
|
|
reg-io-width = <0x04>;
|
|
reg-shift = <0x02>;
|
|
clocks = <0x08 0x96 0x08 0x95>;
|
|
clock-names = "baudclk\0apb_pclk";
|
|
resets = <0x21 0x57 0x21 0x58>;
|
|
interrupts = <0x22>;
|
|
status = "disabled";
|
|
};
|
|
|
|
serial@12000000 {
|
|
compatible = "snps,dw-apb-uart";
|
|
reg = <0x00 0x12000000 0x00 0x10000>;
|
|
reg-io-width = <0x04>;
|
|
reg-shift = <0x02>;
|
|
clocks = <0x08 0x98 0x08 0x97>;
|
|
clock-names = "baudclk\0apb_pclk";
|
|
resets = <0x21 0x59 0x21 0x5a>;
|
|
interrupts = <0x2d>;
|
|
status = "disabled";
|
|
};
|
|
|
|
serial@12010000 {
|
|
compatible = "snps,dw-apb-uart";
|
|
reg = <0x00 0x12010000 0x00 0x10000>;
|
|
reg-io-width = <0x04>;
|
|
reg-shift = <0x02>;
|
|
clocks = <0x08 0x9a 0x08 0x99>;
|
|
clock-names = "baudclk\0apb_pclk";
|
|
resets = <0x21 0x5b 0x21 0x5c>;
|
|
interrupts = <0x2e>;
|
|
status = "disabled";
|
|
};
|
|
|
|
serial@12020000 {
|
|
compatible = "snps,dw-apb-uart";
|
|
reg = <0x00 0x12020000 0x00 0x10000>;
|
|
reg-io-width = <0x04>;
|
|
reg-shift = <0x02>;
|
|
clocks = <0x08 0x9c 0x08 0x9b>;
|
|
clock-names = "baudclk\0apb_pclk";
|
|
resets = <0x21 0x5d 0x21 0x5e>;
|
|
interrupts = <0x2f>;
|
|
status = "disabled";
|
|
};
|
|
|
|
dma-controller@16050000 {
|
|
compatible = "starfive,jh7110-dma\0snps,axi-dma-1.01a";
|
|
reg = <0x00 0x16050000 0x00 0x10000>;
|
|
clocks = <0x08 0xd9 0x08 0xda 0x08 0x60>;
|
|
clock-names = "core-clk\0cfgr-clk\0stg_clk";
|
|
resets = <0x21 0x85 0x21 0x86 0x21 0x1e>;
|
|
reset-names = "rst_axi\0rst_ahb\0rst_stg";
|
|
interrupts = <0x49>;
|
|
#dma-cells = <0x02>;
|
|
dma-channels = <0x04>;
|
|
snps,dma-masters = <0x01>;
|
|
snps,data-width = <0x03>;
|
|
snps,num-hs-if = <0x38>;
|
|
snps,block-size = <0x10000 0x10000 0x10000 0x10000>;
|
|
snps,priority = <0x00 0x01 0x02 0x03>;
|
|
snps,axi-max-burst-len = <0x10>;
|
|
status = "okay";
|
|
phandle = <0x3d>;
|
|
};
|
|
|
|
gpio@13040000 {
|
|
compatible = "starfive,jh7110-sys-pinctrl";
|
|
reg = <0x00 0x13040000 0x00 0x10000>;
|
|
reg-names = "control";
|
|
clocks = <0x08 0x70>;
|
|
resets = <0x21 0x02>;
|
|
interrupts = <0x56>;
|
|
interrupt-controller;
|
|
#gpio-cells = <0x02>;
|
|
ngpios = <0x40>;
|
|
status = "okay";
|
|
phandle = <0x2c>;
|
|
|
|
i2c0-pins {
|
|
phandle = <0x29>;
|
|
|
|
i2c0-pins-scl {
|
|
starfive,pins = <0x39>;
|
|
starfive,pinmux = <0x2ac 0x0c 0x7000 0x00>;
|
|
starfive,pin-ioconfig = <0x09>;
|
|
starfive,pin-gpio-dout = <0x00>;
|
|
starfive,pin-gpio-doen = <0x05>;
|
|
starfive,pin-gpio-din = <0x09>;
|
|
};
|
|
|
|
i2c0-pins-sda {
|
|
starfive,pins = <0x3a>;
|
|
starfive,pinmux = <0x2ac 0x0f 0x38000 0x00>;
|
|
starfive,pin-ioconfig = <0x09>;
|
|
starfive,pin-gpio-dout = <0x00>;
|
|
starfive,pin-gpio-doen = <0x06>;
|
|
starfive,pin-gpio-din = <0x0a>;
|
|
};
|
|
};
|
|
|
|
i2c5-pins {
|
|
phandle = <0x2f>;
|
|
|
|
i2c5-pins-scl {
|
|
starfive,pins = <0x13>;
|
|
starfive,pinmux = <0x29c 0x1d 0xe0000000 0x00>;
|
|
starfive,pin-ioconfig = <0x09>;
|
|
starfive,pin-gpio-dout = <0x00>;
|
|
starfive,pin-gpio-doen = <0x2a>;
|
|
starfive,pin-gpio-din = <0x4f>;
|
|
};
|
|
|
|
i2c5-pins-sda {
|
|
starfive,pins = <0x14>;
|
|
starfive,pinmux = <0x2a0 0x00 0x07 0x00>;
|
|
starfive,pin-ioconfig = <0x09>;
|
|
starfive,pin-gpio-dout = <0x00>;
|
|
starfive,pin-gpio-doen = <0x2b>;
|
|
starfive,pin-gpio-din = <0x50>;
|
|
};
|
|
};
|
|
|
|
i2c6-pins {
|
|
phandle = <0x30>;
|
|
|
|
i2c6-pins-scl {
|
|
starfive,pins = <0x10>;
|
|
starfive,pinmux = <0x29c 0x14 0x700000 0x00>;
|
|
starfive,pin-ioconfig = <0x09>;
|
|
starfive,pin-gpio-dout = <0x00>;
|
|
starfive,pin-gpio-doen = <0x2e>;
|
|
starfive,pin-gpio-din = <0x56>;
|
|
};
|
|
|
|
i2c6-pins-sda {
|
|
starfive,pins = <0x11>;
|
|
starfive,pinmux = <0x29c 0x17 0x3800000 0x00>;
|
|
starfive,pin-ioconfig = <0x09>;
|
|
starfive,pin-gpio-dout = <0x00>;
|
|
starfive,pin-gpio-doen = <0x2f>;
|
|
starfive,pin-gpio-din = <0x57>;
|
|
};
|
|
};
|
|
|
|
pwmdac0-pins {
|
|
phandle = <0x3e>;
|
|
|
|
pwmdac0-pins-left {
|
|
starfive,pins = <0x21>;
|
|
starfive,pinmux = <0x2a4 0x09 0xe00 0x00>;
|
|
starfive,pin-ioconfig = <0x09>;
|
|
starfive,pin-gpio-dout = <0x1c>;
|
|
starfive,pin-gpio-doen = <0x00>;
|
|
};
|
|
|
|
pwmdac0-pins-right {
|
|
starfive,pins = <0x22>;
|
|
starfive,pinmux = <0x2a4 0x0c 0x7000 0x00>;
|
|
starfive,pin-ioconfig = <0x09>;
|
|
starfive,pin-gpio-dout = <0x1d>;
|
|
starfive,pin-gpio-doen = <0x00>;
|
|
};
|
|
};
|
|
|
|
pwm-pins {
|
|
phandle = <0x43>;
|
|
|
|
pwm_ch0-pins {
|
|
starfive,pins = <0x2e>;
|
|
starfive,pinmux = <0x2a8 0x0f 0x38000 0x00>;
|
|
starfive,pin-ioconfig = <0x01>;
|
|
starfive,pin-gpio-dout = <0x18>;
|
|
starfive,pin-gpio-doen = <0x09>;
|
|
};
|
|
|
|
pwm_ch1-pins {
|
|
starfive,pins = <0x3b>;
|
|
starfive,pinmux = <0x2ac 0x12 0x1c0000 0x00>;
|
|
starfive,pin-ioconfig = <0x01>;
|
|
starfive,pin-gpio-dout = <0x19>;
|
|
starfive,pin-gpio-doen = <0x0a>;
|
|
};
|
|
};
|
|
|
|
ssp0-pins {
|
|
phandle = <0x44>;
|
|
|
|
ssp0-pins_tx {
|
|
starfive,pins = <0x34>;
|
|
starfive,pinmux = <0x2ac 0x00 0x03 0x00>;
|
|
starfive,pin-ioconfig = <0x01>;
|
|
starfive,pin-gpio-dout = <0x20>;
|
|
starfive,pin-gpio-doen = <0x00>;
|
|
};
|
|
|
|
ssp0-pins_rx {
|
|
starfive,pins = <0x35>;
|
|
starfive,pinmux = <0x2ac 0x02 0x0c 0x00>;
|
|
starfive,pin-ioconfig = <0x01>;
|
|
starfive,pin-gpio-doen = <0x01>;
|
|
starfive,pin-gpio-din = <0x1c>;
|
|
};
|
|
|
|
ssp0-pins_clk {
|
|
starfive,pins = <0x30>;
|
|
starfive,pinmux = <0x2a8 0x15 0xe00000 0x00>;
|
|
starfive,pin-ioconfig = <0x01>;
|
|
starfive,pin-gpio-dout = <0x1e>;
|
|
starfive,pin-gpio-doen = <0x00>;
|
|
};
|
|
|
|
ssp0-pins_cs {
|
|
starfive,pins = <0x31>;
|
|
starfive,pinmux = <0x2a8 0x18 0x7000000 0x00>;
|
|
starfive,pin-ioconfig = <0x01>;
|
|
starfive,pin-gpio-dout = <0x1f>;
|
|
starfive,pin-gpio-doen = <0x00>;
|
|
};
|
|
};
|
|
|
|
pcie0_perst_default {
|
|
|
|
perst-pins {
|
|
starfive,pins = <0x1a>;
|
|
starfive,pinmux = <0x2a0 0x12 0x1c0000 0x00>;
|
|
starfive,pin-ioconfig = <0x01>;
|
|
starfive,pin-gpio-dout = <0x01>;
|
|
starfive,pin-gpio-doen = <0x00>;
|
|
};
|
|
};
|
|
|
|
pcie0_perst_active {
|
|
|
|
perst-pins {
|
|
starfive,pins = <0x1a>;
|
|
starfive,pinmux = <0x2a0 0x12 0x1c0000 0x00>;
|
|
starfive,pin-ioconfig = <0x01>;
|
|
starfive,pin-gpio-dout = <0x00>;
|
|
starfive,pin-gpio-doen = <0x00>;
|
|
};
|
|
};
|
|
|
|
pcie0_wake_default {
|
|
phandle = <0x46>;
|
|
|
|
wake-pins {
|
|
starfive,pins = <0x20>;
|
|
starfive,pinmux = <0x2a4 0x06 0x1c0 0x00>;
|
|
starfive,pin-ioconfig = <0x01>;
|
|
starfive,pin-gpio-doen = <0x01>;
|
|
};
|
|
};
|
|
|
|
pcie0_clkreq_default {
|
|
phandle = <0x47>;
|
|
|
|
clkreq-pins {
|
|
starfive,pins = <0x1b>;
|
|
starfive,pinmux = <0x2a0 0x15 0xe00000 0x00>;
|
|
starfive,pin-ioconfig = <0x01>;
|
|
starfive,pin-gpio-doen = <0x01>;
|
|
};
|
|
};
|
|
|
|
pcie1_perst_default {
|
|
|
|
perst-pins {
|
|
starfive,pins = <0x1c>;
|
|
starfive,pinmux = <0x2a0 0x18 0x7000000 0x00>;
|
|
starfive,pin-ioconfig = <0x01>;
|
|
starfive,pin-gpio-dout = <0x01>;
|
|
starfive,pin-gpio-doen = <0x00>;
|
|
};
|
|
};
|
|
|
|
pcie1_perst_active {
|
|
|
|
perst-pins {
|
|
starfive,pins = <0x1c>;
|
|
starfive,pinmux = <0x2a0 0x18 0x7000000 0x00>;
|
|
starfive,pin-ioconfig = <0x01>;
|
|
starfive,pin-gpio-dout = <0x00>;
|
|
starfive,pin-gpio-doen = <0x00>;
|
|
};
|
|
};
|
|
|
|
pcie1_wake_default {
|
|
phandle = <0x49>;
|
|
|
|
wake-pins {
|
|
starfive,pins = <0x15>;
|
|
starfive,pinmux = <0x2a0 0x03 0x38 0x00>;
|
|
starfive,pin-ioconfig = <0x01>;
|
|
starfive,pin-gpio-doen = <0x01>;
|
|
};
|
|
};
|
|
|
|
pcie1_clkreq_default {
|
|
phandle = <0x4a>;
|
|
|
|
clkreq-pins {
|
|
starfive,pins = <0x1d>;
|
|
starfive,pinmux = <0x2a0 0x1b 0x38000000 0x00>;
|
|
starfive,pin-ioconfig = <0x01>;
|
|
starfive,pin-gpio-doen = <0x01>;
|
|
};
|
|
};
|
|
|
|
usb-pins {
|
|
|
|
drive-vbus-pin {
|
|
starfive,pins = <0x19>;
|
|
starfive,pinmux = <0x2a0 0x0f 0x38000 0x00>;
|
|
starfive,pin-ioconfig = <0x01>;
|
|
starfive,pin-gpio-dout = <0x07>;
|
|
starfive,pin-gpio-doen = <0x00>;
|
|
};
|
|
};
|
|
|
|
i2srx-pins {
|
|
phandle = <0x40>;
|
|
|
|
i2srx-pins0 {
|
|
starfive,pins = <0x3d>;
|
|
starfive,pinmux = <0x2ac 0x18 0x7000000 0x00>;
|
|
starfive,pin-ioconfig = <0x01>;
|
|
starfive,pin-gpio-doen = <0x01>;
|
|
starfive,pin-gpio-din = <0x17>;
|
|
};
|
|
};
|
|
|
|
i2s-clk0 {
|
|
phandle = <0x3f>;
|
|
|
|
i2s-clk0_bclk {
|
|
starfive,pins = <0x26>;
|
|
starfive,pinmux = <0x2a4 0x17 0x3800000 0x00>;
|
|
starfive,pin-ioconfig = <0x01>;
|
|
starfive,pin-gpio-din = <0x21 0x1f>;
|
|
starfive,pin-gpio-doen = <0x01>;
|
|
};
|
|
|
|
i2s-clk0_lrclk {
|
|
starfive,pins = <0x3f>;
|
|
starfive,pinmux = <0x2ac 0x1e 0xc0000000 0x00>;
|
|
starfive,pin-ioconfig = <0x01>;
|
|
starfive,pin-gpio-din = <0x22 0x20>;
|
|
starfive,pin-gpio-doen = <0x01>;
|
|
};
|
|
};
|
|
|
|
i2stx-pins {
|
|
phandle = <0x42>;
|
|
|
|
i2stx-pins0 {
|
|
starfive,pins = <0x2c>;
|
|
starfive,pinmux = <0x2a8 0x09 0xe00 0x00>;
|
|
starfive,pin-ioconfig = <0x01>;
|
|
starfive,pin-gpio-dout = <0x45>;
|
|
starfive,pin-gpio-doen = <0x00>;
|
|
};
|
|
};
|
|
|
|
uart0-pins {
|
|
phandle = <0x24>;
|
|
|
|
uart0-pins-tx {
|
|
starfive,pins = <0x05>;
|
|
starfive,pin-ioconfig = <0x07>;
|
|
starfive,pin-gpio-dout = <0x14>;
|
|
starfive,pin-gpio-doen = <0x00>;
|
|
};
|
|
|
|
uart0-pins-rx {
|
|
starfive,pins = <0x06>;
|
|
starfive,pinmux = <0x2b0 0x00 0x03 0x00>;
|
|
starfive,pin-ioconfig = <0x09>;
|
|
starfive,pin-gpio-doen = <0x01>;
|
|
starfive,pin-gpio-din = <0x0e>;
|
|
};
|
|
};
|
|
|
|
i2c2-pins {
|
|
phandle = <0x2a>;
|
|
|
|
i2c2-pins-scl {
|
|
starfive,pins = <0x03>;
|
|
starfive,pin-ioconfig = <0x09>;
|
|
starfive,pin-gpio-dout = <0x00>;
|
|
starfive,pin-gpio-doen = <0x1e>;
|
|
starfive,pin-gpio-din = <0x3b>;
|
|
};
|
|
|
|
i2c2-pins-sda {
|
|
starfive,pins = <0x02>;
|
|
starfive,pin-ioconfig = <0x09>;
|
|
starfive,pin-gpio-dout = <0x00>;
|
|
starfive,pin-gpio-doen = <0x1f>;
|
|
starfive,pin-gpio-din = <0x3c>;
|
|
};
|
|
};
|
|
|
|
mmc0-pins {
|
|
phandle = <0x36>;
|
|
|
|
mmc0-pins-rest {
|
|
starfive,pins = <0x3e>;
|
|
starfive,pinmux = <0x2ac 0x1b 0x38000000 0x00>;
|
|
starfive,pin-ioconfig = <0x09>;
|
|
starfive,pin-gpio-dout = <0x13>;
|
|
starfive,pin-gpio-doen = <0x00>;
|
|
};
|
|
|
|
mmc0-pins-cLK {
|
|
starfive,pins = <0x40>;
|
|
starfive,pin-ioconfig = <0x2d>;
|
|
};
|
|
|
|
mmc0-pins-cmd {
|
|
starfive,pins = <0x41>;
|
|
starfive,pin-ioconfig = <0x0b>;
|
|
};
|
|
|
|
mmc0-pins-data0 {
|
|
starfive,pins = <0x42>;
|
|
starfive,pin-ioconfig = <0x0b>;
|
|
};
|
|
|
|
mmc0-pins-data1 {
|
|
starfive,pins = <0x43>;
|
|
starfive,pin-ioconfig = <0x0b>;
|
|
};
|
|
|
|
mmc0-pins-data2 {
|
|
starfive,pins = <0x44>;
|
|
starfive,pin-ioconfig = <0x0b>;
|
|
};
|
|
|
|
mmc0-pins-data3 {
|
|
starfive,pins = <0x45>;
|
|
starfive,pin-ioconfig = <0x0b>;
|
|
};
|
|
|
|
mmc0-pins-data4 {
|
|
starfive,pins = <0x46>;
|
|
starfive,pin-ioconfig = <0x0b>;
|
|
};
|
|
|
|
mmc0-pins-data5 {
|
|
starfive,pins = <0x47>;
|
|
starfive,pin-ioconfig = <0x0b>;
|
|
};
|
|
|
|
mmc0-pins-data6 {
|
|
starfive,pins = <0x48>;
|
|
starfive,pin-ioconfig = <0x0b>;
|
|
};
|
|
|
|
mmc0-pins-data7 {
|
|
starfive,pins = <0x49>;
|
|
starfive,pin-ioconfig = <0x0b>;
|
|
};
|
|
};
|
|
|
|
sdcard1-pins {
|
|
phandle = <0x37>;
|
|
|
|
sdcard1-pins0 {
|
|
starfive,pins = <0x0a>;
|
|
starfive,pinmux = <0x29c 0x02 0x1c 0x00>;
|
|
starfive,pin-ioconfig = <0x2d>;
|
|
starfive,pin-gpio-dout = <0x37>;
|
|
starfive,pin-gpio-doen = <0x00>;
|
|
};
|
|
|
|
sdcard1-pins1 {
|
|
starfive,pins = <0x09>;
|
|
starfive,pinmux = <0x2b0 0x08 0x700 0x00>;
|
|
starfive,pin-ioconfig = <0x0b>;
|
|
starfive,pin-gpio-dout = <0x39>;
|
|
starfive,pin-gpio-doen = <0x13>;
|
|
starfive,pin-gpio-din = <0x2c>;
|
|
};
|
|
|
|
sdcard1-pins2 {
|
|
starfive,pins = <0x0b>;
|
|
starfive,pinmux = <0x29c 0x05 0xe0 0x00>;
|
|
starfive,pin-ioconfig = <0x0b>;
|
|
starfive,pin-gpio-dout = <0x3a>;
|
|
starfive,pin-gpio-doen = <0x14>;
|
|
starfive,pin-gpio-din = <0x2d>;
|
|
};
|
|
|
|
sdcard1-pins3 {
|
|
starfive,pins = <0x0c>;
|
|
starfive,pinmux = <0x29c 0x08 0x700 0x00>;
|
|
starfive,pin-ioconfig = <0x0b>;
|
|
starfive,pin-gpio-dout = <0x3b>;
|
|
starfive,pin-gpio-doen = <0x15>;
|
|
starfive,pin-gpio-din = <0x2e>;
|
|
};
|
|
|
|
sdcard1-pins4 {
|
|
starfive,pins = <0x07>;
|
|
starfive,pinmux = <0x2b0 0x02 0x1c 0x00>;
|
|
starfive,pin-ioconfig = <0x0b>;
|
|
starfive,pin-gpio-dout = <0x3c>;
|
|
starfive,pin-gpio-doen = <0x16>;
|
|
starfive,pin-gpio-din = <0x2f>;
|
|
};
|
|
|
|
sdcard1-pins5 {
|
|
starfive,pins = <0x08>;
|
|
starfive,pinmux = <0x2b0 0x05 0xe0 0x00>;
|
|
starfive,pin-ioconfig = <0x0b>;
|
|
starfive,pin-gpio-dout = <0x3d>;
|
|
starfive,pin-gpio-doen = <0x17>;
|
|
starfive,pin-gpio-din = <0x30>;
|
|
};
|
|
};
|
|
|
|
inno_hdmi-pins {
|
|
phandle = <0x59>;
|
|
|
|
inno_hdmi-scl {
|
|
starfive,pins = <0x00>;
|
|
starfive,pin-ioconfig = <0x09>;
|
|
starfive,pin-gpio-dout = <0x0b>;
|
|
starfive,pin-gpio-doen = <0x03>;
|
|
starfive,pin-gpio-din = <0x06>;
|
|
};
|
|
|
|
inno_hdmi-sda {
|
|
starfive,pins = <0x01>;
|
|
starfive,pin-ioconfig = <0x09>;
|
|
starfive,pin-gpio-dout = <0x0c>;
|
|
starfive,pin-gpio-doen = <0x04>;
|
|
starfive,pin-gpio-din = <0x07>;
|
|
};
|
|
|
|
inno_hdmi-cec-pins {
|
|
starfive,pins = <0x0e>;
|
|
starfive,pin-ioconfig = <0x09>;
|
|
starfive,pin-gpio-doen = <0x02>;
|
|
starfive,pin-gpio-dout = <0x0a>;
|
|
starfive,pin-gpio-din = <0x05>;
|
|
};
|
|
|
|
inno_hdmi-hpd-pins {
|
|
starfive,pins = <0x0f>;
|
|
starfive,pin-ioconfig = <0x01>;
|
|
starfive,pin-gpio-doen = <0x01>;
|
|
starfive,pin-gpio-din = <0x08>;
|
|
};
|
|
};
|
|
|
|
mclk_ext_pins {
|
|
phandle = <0x41>;
|
|
|
|
mclk_ext_pins {
|
|
starfive,pins = <0x04>;
|
|
starfive,pin-ioconfig = <0x01>;
|
|
starfive,pin-gpio-din = <0x1e>;
|
|
starfive,pin-gpio-doen = <0x01>;
|
|
};
|
|
};
|
|
};
|
|
|
|
gpio@17020000 {
|
|
compatible = "starfive,jh7110-aon-pinctrl";
|
|
reg = <0x00 0x17020000 0x00 0x10000>;
|
|
reg-names = "control";
|
|
resets = <0x21 0xa2>;
|
|
interrupts = <0x55>;
|
|
interrupt-controller;
|
|
#gpio-cells = <0x02>;
|
|
ngpios = <0x04>;
|
|
status = "okay";
|
|
phandle = <0x62>;
|
|
};
|
|
|
|
tmon@120e0000 {
|
|
compatible = "starfive,jh7110-temp";
|
|
reg = <0x00 0x120e0000 0x00 0x10000>;
|
|
interrupts = <0x51>;
|
|
clocks = <0x08 0x82 0x08 0x81>;
|
|
clock-names = "sense\0bus";
|
|
resets = <0x21 0x7c 0x21 0x7b>;
|
|
reset-names = "sense\0bus";
|
|
#thermal-sensor-cells = <0x00>;
|
|
status = "okay";
|
|
phandle = <0x25>;
|
|
};
|
|
|
|
thermal-zones {
|
|
|
|
cpu-thermal {
|
|
polling-delay-passive = <0xfa>;
|
|
polling-delay = <0x3a98>;
|
|
thermal-sensors = <0x25>;
|
|
|
|
trips {
|
|
|
|
cpu_alert0 {
|
|
temperature = <0x14c08>;
|
|
hysteresis = <0x7d0>;
|
|
type = "passive";
|
|
phandle = <0x26>;
|
|
};
|
|
|
|
cpu_crit {
|
|
temperature = <0x186a0>;
|
|
hysteresis = <0x7d0>;
|
|
type = "critical";
|
|
};
|
|
};
|
|
|
|
cooling-maps {
|
|
|
|
map0 {
|
|
trip = <0x26>;
|
|
cooling-device = <0x27 0xffffffff 0xffffffff 0x01 0xffffffff 0xffffffff 0x02 0xffffffff 0xffffffff 0x03 0xffffffff 0xffffffff>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
trng@1600C000 {
|
|
compatible = "starfive,jh7110-trng";
|
|
reg = <0x00 0x1600c000 0x00 0x4000>;
|
|
clocks = <0x08 0xcd 0x08 0xce>;
|
|
clock-names = "hclk\0ahb";
|
|
resets = <0x21 0x83>;
|
|
interrupts = <0x1e>;
|
|
status = "okay";
|
|
};
|
|
|
|
sec_dma@16008000 {
|
|
compatible = "arm,pl080\0arm,primecell";
|
|
arm,primecell-periphid = <0x41080>;
|
|
reg = <0x00 0x16008000 0x00 0x4000>;
|
|
reg-names = "sec_dma";
|
|
interrupts = <0x1d>;
|
|
clocks = <0x08 0xcd 0x08 0xce>;
|
|
clock-names = "sec_hclk\0apb_pclk";
|
|
resets = <0x21 0x83>;
|
|
reset-names = "sec_hre";
|
|
lli-bus-interface-ahb1;
|
|
mem-bus-interface-ahb1;
|
|
memcpy-burst-size = <0x100>;
|
|
memcpy-bus-width = <0x20>;
|
|
#dma-cells = <0x02>;
|
|
status = "okay";
|
|
phandle = <0x28>;
|
|
};
|
|
|
|
crypto@16000000 {
|
|
compatible = "starfive,jh7110-sec";
|
|
reg = <0x00 0x16000000 0x00 0x4000 0x00 0x16008000 0x00 0x4000>;
|
|
reg-names = "secreg\0secdma";
|
|
interrupts = <0x1c 0x1d>;
|
|
interrupt-names = "secirq\0dmairq";
|
|
clocks = <0x08 0xcd 0x08 0xce>;
|
|
clock-names = "sec_hclk\0sec_ahb";
|
|
resets = <0x21 0x83>;
|
|
reset-names = "sec_hre";
|
|
enable-side-channel-mitigation = "true";
|
|
enable-dma = "true";
|
|
dmas = <0x28 0x01 0x02 0x28 0x00 0x02>;
|
|
dma-names = "sec_m\0sec_p";
|
|
status = "okay";
|
|
};
|
|
|
|
i2c@10030000 {
|
|
compatible = "snps,designware-i2c";
|
|
reg = <0x00 0x10030000 0x00 0x10000>;
|
|
clocks = <0x08 0x125 0x08 0x8a>;
|
|
clock-names = "ref\0pclk";
|
|
resets = <0x21 0x4c>;
|
|
interrupts = <0x23>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
status = "okay";
|
|
clock-frequency = <0x186a0>;
|
|
i2c-sda-hold-time-ns = <0x12c>;
|
|
i2c-sda-falling-time-ns = <0x1fe>;
|
|
i2c-scl-falling-time-ns = <0x1fe>;
|
|
auto_calc_scl_lhcnt;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x29>;
|
|
};
|
|
|
|
i2c@10040000 {
|
|
compatible = "snps,designware-i2c";
|
|
reg = <0x00 0x10040000 0x00 0x10000>;
|
|
clocks = <0x08 0x126 0x08 0x8b>;
|
|
clock-names = "ref\0pclk";
|
|
resets = <0x21 0x4d>;
|
|
interrupts = <0x24>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c@10050000 {
|
|
compatible = "snps,designware-i2c";
|
|
reg = <0x00 0x10050000 0x00 0x10000>;
|
|
clocks = <0x08 0x127 0x08 0x8c>;
|
|
clock-names = "ref\0pclk";
|
|
resets = <0x21 0x4e>;
|
|
interrupts = <0x25>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
status = "okay";
|
|
clock-frequency = <0x186a0>;
|
|
i2c-sda-hold-time-ns = <0x12c>;
|
|
i2c-sda-falling-time-ns = <0x1fe>;
|
|
i2c-scl-falling-time-ns = <0x1fe>;
|
|
auto_calc_scl_lhcnt;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x2a>;
|
|
|
|
seeed_plane_i2c@45 {
|
|
compatible = "seeed_panel";
|
|
reg = <0x45>;
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x2b>;
|
|
phandle = <0x55>;
|
|
};
|
|
};
|
|
};
|
|
|
|
tinker_ft5406@38 {
|
|
compatible = "tinker_ft5406";
|
|
reg = <0x38>;
|
|
};
|
|
|
|
panel_radxa@19 {
|
|
compatible = "starfive_jadard";
|
|
reg = <0x19>;
|
|
reset-gpio = <0x2c 0x17 0x00>;
|
|
enable-gpio = <0x2c 0x16 0x00>;
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x2d>;
|
|
phandle = <0x56>;
|
|
};
|
|
};
|
|
};
|
|
|
|
touchscreen@14 {
|
|
compatible = "goodix,gt911";
|
|
reg = <0x14>;
|
|
irq-gpios = <0x2c 0x1e 0x00>;
|
|
reset-gpios = <0x2c 0x1f 0x00>;
|
|
};
|
|
|
|
panel_10inch@20 {
|
|
compatible = "panel_10inch";
|
|
reg = <0x20>;
|
|
reset-gpio = <0x2c 0x17 0x00>;
|
|
enable-gpio = <0x2c 0x16 0x00>;
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x2e>;
|
|
phandle = <0x57>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
i2c@12030000 {
|
|
compatible = "snps,designware-i2c";
|
|
reg = <0x00 0x12030000 0x00 0x10000>;
|
|
clocks = <0x08 0x128 0x08 0x8d>;
|
|
clock-names = "ref\0pclk";
|
|
resets = <0x21 0x4f>;
|
|
interrupts = <0x30>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c@12040000 {
|
|
compatible = "snps,designware-i2c";
|
|
reg = <0x00 0x12040000 0x00 0x10000>;
|
|
clocks = <0x08 0x129 0x08 0x8e>;
|
|
clock-names = "ref\0pclk";
|
|
resets = <0x21 0x50>;
|
|
interrupts = <0x31>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c@12050000 {
|
|
compatible = "snps,designware-i2c";
|
|
reg = <0x00 0x12050000 0x00 0x10000>;
|
|
clocks = <0x08 0x12a 0x08 0x8f>;
|
|
clock-names = "ref\0pclk";
|
|
resets = <0x21 0x51>;
|
|
interrupts = <0x32>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
status = "okay";
|
|
clock-frequency = <0x186a0>;
|
|
i2c-sda-hold-time-ns = <0x12c>;
|
|
i2c-sda-falling-time-ns = <0x1fe>;
|
|
i2c-scl-falling-time-ns = <0x1fe>;
|
|
auto_calc_scl_lhcnt;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x2f>;
|
|
|
|
eeprom@50 {
|
|
compatible = "atmel,24c04";
|
|
reg = <0x50>;
|
|
pagesize = <0x10>;
|
|
};
|
|
|
|
axp15060_reg@36 {
|
|
compatible = "stf,axp15060-regulator";
|
|
reg = <0x36>;
|
|
|
|
regulators {
|
|
|
|
ALDO1 {
|
|
regulator-boot-on;
|
|
regulator-compatible = "mipi_0p9";
|
|
regulator-name = "mipi_0p9";
|
|
regulator-min-microvolt = <0xdbba0>;
|
|
regulator-max-microvolt = <0xdbba0>;
|
|
};
|
|
|
|
ALDO5 {
|
|
regulator-boot-on;
|
|
regulator-compatible = "hdmi_0p9";
|
|
regulator-name = "hdmi_0p9";
|
|
regulator-min-microvolt = <0xdbba0>;
|
|
regulator-max-microvolt = <0xdbba0>;
|
|
};
|
|
|
|
ALDO3 {
|
|
regulator-boot-on;
|
|
regulator-compatible = "hdmi_1p8";
|
|
regulator-name = "hdmi_1p8";
|
|
regulator-min-microvolt = <0x1b7740>;
|
|
regulator-max-microvolt = <0x1b7740>;
|
|
};
|
|
|
|
ALDO4 {
|
|
regulator-boot-on;
|
|
regulator-always-on;
|
|
regulator-compatible = "sdio_vdd";
|
|
regulator-name = "sdio_vdd";
|
|
regulator-min-microvolt = <0x1b7740>;
|
|
regulator-max-microvolt = <0x1b7740>;
|
|
phandle = <0x35>;
|
|
};
|
|
|
|
DCDC1 {
|
|
regulator-boot-on;
|
|
regulator-always-on;
|
|
regulator-compatible = "vcc_3v3";
|
|
regulator-name = "vcc_3v3";
|
|
regulator-min-microvolt = <0x325aa0>;
|
|
regulator-max-microvolt = <0x325aa0>;
|
|
phandle = <0x34>;
|
|
};
|
|
|
|
DCDC2 {
|
|
regulator-boot-on;
|
|
regulator-always-on;
|
|
regulator-compatible = "cpu_vdd";
|
|
regulator-name = "cpu_vdd";
|
|
regulator-min-microvolt = <0x7a120>;
|
|
regulator-max-microvolt = <0x177fa0>;
|
|
phandle = <0x07>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
i2c@12060000 {
|
|
compatible = "snps,designware-i2c";
|
|
reg = <0x00 0x12060000 0x00 0x10000>;
|
|
clocks = <0x08 0x12b 0x08 0x90>;
|
|
clock-names = "ref\0pclk";
|
|
resets = <0x21 0x52>;
|
|
interrupts = <0x33>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
status = "okay";
|
|
clock-frequency = <0x186a0>;
|
|
i2c-sda-hold-time-ns = <0x12c>;
|
|
i2c-sda-falling-time-ns = <0x1fe>;
|
|
i2c-scl-falling-time-ns = <0x1fe>;
|
|
auto_calc_scl_lhcnt;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x30>;
|
|
|
|
imx219@10 {
|
|
compatible = "sony,imx219";
|
|
reg = <0x10>;
|
|
clocks = <0x31>;
|
|
clock-names = "xclk";
|
|
reset-gpio = <0x2c 0x12 0x00>;
|
|
rotation = <0x00>;
|
|
orientation = <0x01>;
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x32>;
|
|
bus-type = <0x04>;
|
|
clock-lanes = <0x04>;
|
|
data-lanes = <0x00 0x01>;
|
|
lane-polarities = <0x00 0x00 0x00>;
|
|
link-frequencies = <0x00 0x1b2e0200>;
|
|
phandle = <0x3a>;
|
|
};
|
|
};
|
|
};
|
|
|
|
imx708@1a {
|
|
compatible = "sony,imx708";
|
|
reg = <0x1a>;
|
|
clocks = <0x31>;
|
|
reset-gpio = <0x2c 0x12 0x00>;
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x33>;
|
|
data-lanes = <0x01 0x02>;
|
|
clock-noncontinuous;
|
|
link-frequencies = <0x00 0x1ad27480>;
|
|
phandle = <0x3b>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
sdio0@16010000 {
|
|
compatible = "starfive,jh7110-sdio";
|
|
reg = <0x00 0x16010000 0x00 0x10000>;
|
|
clocks = <0x08 0x5b 0x08 0x5d>;
|
|
clock-names = "biu\0ciu";
|
|
resets = <0x21 0x40>;
|
|
reset-names = "reset";
|
|
interrupts = <0x4a>;
|
|
fifo-depth = <0x20>;
|
|
fifo-watermark-aligned;
|
|
data-addr = <0x00>;
|
|
starfive,sys-syscon = <0x1d 0x14 0x1a 0x7c000000>;
|
|
status = "okay";
|
|
max-frequency = <0x5f5e100>;
|
|
card-detect-delay = <0x12c>;
|
|
bus-width = <0x08>;
|
|
cap-mmc-highspeed;
|
|
non-removable;
|
|
cap-mmc-hw-reset;
|
|
post-power-on-delay-ms = <0xc8>;
|
|
vmmc-supply = <0x34>;
|
|
vqmmc-supply = <0x35>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x36>;
|
|
};
|
|
|
|
sdio1@16020000 {
|
|
compatible = "starfive,jh7110-sdio";
|
|
reg = <0x00 0x16020000 0x00 0x10000>;
|
|
clocks = <0x08 0x5c 0x08 0x5e>;
|
|
clock-names = "biu\0ciu";
|
|
resets = <0x21 0x41>;
|
|
reset-names = "reset";
|
|
interrupts = <0x4b>;
|
|
fifo-depth = <0x20>;
|
|
fifo-watermark-aligned;
|
|
data-addr = <0x00>;
|
|
starfive,sys-syscon = <0x1d 0x9c 0x01 0x3e>;
|
|
status = "okay";
|
|
max-frequency = <0x5f5e100>;
|
|
card-detect-delay = <0x12c>;
|
|
bus-width = <0x04>;
|
|
no-sdio;
|
|
no-mmc;
|
|
broken-cd;
|
|
cap-sd-highspeed;
|
|
post-power-on-delay-ms = <0xc8>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x37>;
|
|
};
|
|
|
|
vin_sysctl@19800000 {
|
|
compatible = "starfive,jh7110-vin";
|
|
reg = <0x00 0x19800000 0x00 0x10000 0x00 0x19810000 0x00 0x10000 0x00 0x19820000 0x00 0x10000 0x00 0x19840000 0x00 0x10000 0x00 0x19870000 0x00 0x30000 0x00 0x11840000 0x00 0x10000 0x00 0x17030000 0x00 0x10000 0x00 0x13020000 0x00 0x10000>;
|
|
reg-names = "csi2rx\0vclk\0vrst\0sctrl\0isp\0trst\0pmu\0syscrg";
|
|
clocks = <0x38 0x00 0x38 0x06 0x38 0x07 0x38 0x0d 0x38 0x02 0x38 0x0c 0x38 0x01 0x38 0x08 0x38 0x09 0x38 0x0a 0x38 0x0b 0x38 0x03 0x38 0x04 0x38 0x05 0x08 0x33 0x08 0x34>;
|
|
clock-names = "clk_apb_func\0clk_pclk\0clk_sys_clk\0clk_wrapper_clk_c\0clk_dvp_inv\0clk_axiwr\0clk_mipi_rx0_pxl\0clk_pixel_clk_if0\0clk_pixel_clk_if1\0clk_pixel_clk_if2\0clk_pixel_clk_if3\0clk_m31dphy_cfgclk_in\0clk_m31dphy_refclk_in\0clk_m31dphy_txclkesc_lan0\0clk_ispcore_2x\0clk_isp_axi";
|
|
resets = <0x21 0xc0 0x21 0xc1 0x21 0xc4 0x21 0xc9 0x21 0xca 0x21 0xcb 0x21 0xc5 0x21 0xc6 0x21 0xc7 0x21 0xc8 0x21 0xc2 0x21 0xc3 0x21 0x29 0x21 0x2a>;
|
|
reset-names = "rst_wrapper_p\0rst_wrapper_c\0rst_pclk\0rst_sys_clk\0rst_axird\0rst_axiwr\0rst_pixel_clk_if0\0rst_pixel_clk_if1\0rst_pixel_clk_if2\0rst_pixel_clk_if3\0rst_m31dphy_hw\0rst_m31dphy_b09_always_on\0rst_isp_top_n\0rst_isp_top_axi";
|
|
starfive,aon-syscon = <0x39 0x00>;
|
|
power-domains = <0x22 0x05>;
|
|
interrupts = <0x5c 0x57 0x58 0x59 0x5a>;
|
|
status = "okay";
|
|
|
|
ports {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
port@1 {
|
|
reg = <0x01>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
endpoint@0 {
|
|
reg = <0x00>;
|
|
remote-endpoint = <0x3a>;
|
|
bus-type = <0x04>;
|
|
clock-lanes = <0x04>;
|
|
data-lanes = <0x00 0x01>;
|
|
lane-polarities = <0x00 0x00 0x00>;
|
|
status = "okay";
|
|
phandle = <0x32>;
|
|
};
|
|
|
|
endpoint@1 {
|
|
reg = <0x01>;
|
|
remote-endpoint = <0x3b>;
|
|
bus-type = <0x04>;
|
|
clock-lanes = <0x04>;
|
|
data-lanes = <0x00 0x01>;
|
|
lane-polarities = <0x00 0x00 0x00>;
|
|
status = "okay";
|
|
phandle = <0x33>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
jpu@11900000 {
|
|
compatible = "starfive,jpu";
|
|
reg = <0x00 0x13090000 0x00 0x300>;
|
|
interrupts = <0x0e>;
|
|
clocks = <0x08 0x42 0x08 0x43 0x08 0x44 0x08 0x4c>;
|
|
clock-names = "axi_clk\0core_clk\0apb_clk\0noc_bus";
|
|
resets = <0x21 0x2c 0x21 0x2d 0x21 0x2e>;
|
|
reset-names = "rst_axi\0rst_core\0rst_apb";
|
|
power-domains = <0x22 0x03>;
|
|
status = "okay";
|
|
};
|
|
|
|
vpu_dec@130A0000 {
|
|
compatible = "starfive,vdec";
|
|
reg = <0x00 0x130a0000 0x00 0x10000>;
|
|
interrupts = <0x0d>;
|
|
clocks = <0x08 0x46 0x08 0x47 0x08 0x48 0x08 0x49 0x08 0x4c>;
|
|
clock-names = "axi_clk\0bpu_clk\0vce_clk\0apb_clk\0noc_bus";
|
|
resets = <0x21 0x2f 0x21 0x30 0x21 0x31 0x21 0x32 0x21 0x35>;
|
|
reset-names = "rst_axi\0rst_bpu\0rst_vce\0rst_apb\0rst_sram";
|
|
starfive,vdec_noc_ctrl;
|
|
power-domains = <0x22 0x03>;
|
|
status = "okay";
|
|
};
|
|
|
|
vpu_enc@130B0000 {
|
|
compatible = "starfive,venc";
|
|
reg = <0x00 0x130b0000 0x00 0x10000>;
|
|
interrupts = <0x0f>;
|
|
clocks = <0x08 0x4e 0x08 0x4f 0x08 0x50 0x08 0x51 0x08 0x52>;
|
|
clock-names = "axi_clk\0bpu_clk\0vce_clk\0apb_clk\0noc_bus";
|
|
resets = <0x21 0x36 0x21 0x37 0x21 0x38 0x21 0x39 0x21 0x3a>;
|
|
reset-names = "rst_axi\0rst_bpu\0rst_vce\0rst_apb\0rst_sram";
|
|
starfive,venc_noc_ctrl;
|
|
power-domains = <0x22 0x06>;
|
|
status = "okay";
|
|
};
|
|
|
|
reset-controller {
|
|
compatible = "starfive,jh7110-reset";
|
|
reg = <0x00 0x13020000 0x00 0x10000 0x00 0x10230000 0x00 0x10000 0x00 0x17000000 0x00 0x10000 0x00 0x19810000 0x00 0x10000 0x00 0x295c0000 0x00 0x10000>;
|
|
reg-names = "syscrg\0stgcrg\0aoncrg\0ispcrg\0voutcrg";
|
|
#reset-cells = <0x01>;
|
|
status = "okay";
|
|
phandle = <0x21>;
|
|
};
|
|
|
|
stmmac-axi-config {
|
|
snps,wr_osr_lmt = <0x0f>;
|
|
snps,rd_osr_lmt = <0x0f>;
|
|
snps,blen = <0x100 0x80 0x40 0x20 0x00 0x00 0x00>;
|
|
phandle = <0x3c>;
|
|
};
|
|
|
|
ethernet@16030000 {
|
|
compatible = "starfive,dwmac\0snps,dwmac-5.10a";
|
|
reg = <0x00 0x16030000 0x00 0x10000>;
|
|
clock-names = "gtx\0tx\0ptp_ref\0stmmaceth\0pclk\0gtxc\0rmii_rtx";
|
|
clocks = <0x08 0x6c 0x08 0xe0 0x08 0x6d 0x08 0xdd 0x08 0xde 0x08 0x6f 0x08 0xdf>;
|
|
resets = <0x21 0xa1 0x21 0xa0>;
|
|
reset-names = "ahb\0stmmaceth";
|
|
interrupts = <0x07 0x06 0x05>;
|
|
interrupt-names = "macirq\0eth_wake_irq\0eth_lpi";
|
|
max-frame-size = <0x2328>;
|
|
phy-mode = "rgmii-id";
|
|
snps,multicast-filter-bins = <0x40>;
|
|
snps,perfect-filter-entries = <0x80>;
|
|
rx-fifo-depth = <0x800>;
|
|
tx-fifo-depth = <0x800>;
|
|
snps,fixed-burst;
|
|
snps,no-pbl-x8;
|
|
snps,force_thresh_dma_mode;
|
|
snps,axi-config = <0x3c>;
|
|
snps,tso;
|
|
snps,en-tx-lpi-clockgating;
|
|
snps,en-lpi;
|
|
snps,write-requests = <0x04>;
|
|
snps,read-requests = <0x04>;
|
|
snps,burst-map = <0x07>;
|
|
snps,txpbl = <0x10>;
|
|
snps,rxpbl = <0x10>;
|
|
status = "okay";
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
ethernet-phy@0 {
|
|
rgmii_sw_dr_2 = <0x00>;
|
|
rgmii_sw_dr = <0x03>;
|
|
rgmii_sw_dr_rxc = <0x06>;
|
|
rxc_dly_en = <0x00>;
|
|
rx_delay_sel = <0x0a>;
|
|
tx_delay_sel_fe = <0x05>;
|
|
tx_delay_sel = <0x0a>;
|
|
tx_inverted_10 = <0x01>;
|
|
tx_inverted_100 = <0x01>;
|
|
tx_inverted_1000 = <0x01>;
|
|
};
|
|
};
|
|
|
|
ethernet@16040000 {
|
|
compatible = "starfive,dwmac\0snps,dwmac-5.10a";
|
|
reg = <0x00 0x16040000 0x00 0x10000>;
|
|
clock-names = "gtx\0tx\0ptp_ref\0stmmaceth\0pclk\0gtxc\0rmii_rtx";
|
|
clocks = <0x08 0x64 0x08 0x69 0x08 0x66 0x08 0x61 0x08 0x62 0x08 0x6b 0x08 0x65>;
|
|
resets = <0x21 0x43 0x21 0x42>;
|
|
reset-names = "ahb\0stmmaceth";
|
|
interrupts = <0x4e 0x4d 0x4c>;
|
|
interrupt-names = "macirq\0eth_wake_irq\0eth_lpi";
|
|
max-frame-size = <0x2328>;
|
|
phy-mode = "rgmii-id";
|
|
snps,multicast-filter-bins = <0x40>;
|
|
snps,perfect-filter-entries = <0x80>;
|
|
rx-fifo-depth = <0x800>;
|
|
tx-fifo-depth = <0x800>;
|
|
snps,fixed-burst;
|
|
snps,no-pbl-x8;
|
|
snps,force_thresh_dma_mode;
|
|
snps,axi-config = <0x3c>;
|
|
snps,tso;
|
|
snps,en-tx-lpi-clockgating;
|
|
snps,en-lpi;
|
|
snps,write-requests = <0x04>;
|
|
snps,read-requests = <0x04>;
|
|
snps,burst-map = <0x07>;
|
|
snps,txpbl = <0x10>;
|
|
snps,rxpbl = <0x10>;
|
|
status = "okay";
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
ethernet-phy@1 {
|
|
rgmii_sw_dr_2 = <0x00>;
|
|
rgmii_sw_dr = <0x03>;
|
|
rgmii_sw_dr_rxc = <0x06>;
|
|
tx_delay_sel_fe = <0x05>;
|
|
tx_delay_sel = <0x00>;
|
|
rxc_dly_en = <0x00>;
|
|
rx_delay_sel = <0x02>;
|
|
tx_inverted_10 = <0x01>;
|
|
tx_inverted_100 = <0x01>;
|
|
tx_inverted_1000 = <0x00>;
|
|
};
|
|
};
|
|
|
|
gpu@18000000 {
|
|
compatible = "img-gpu";
|
|
reg = <0x00 0x18000000 0x00 0x100000 0x00 0x130c000 0x00 0x10000>;
|
|
clocks = <0x08 0x2d 0x08 0x30 0x08 0x31 0x08 0x2e 0x08 0x2f 0x08 0x32>;
|
|
clock-names = "clk_bv\0clk_apb\0clk_rtc\0clk_core\0clk_sys\0clk_axi";
|
|
resets = <0x21 0x15 0x21 0x16>;
|
|
reset-names = "rst_apb\0rst_doma";
|
|
power-domains = <0x22 0x02>;
|
|
interrupts = <0x52>;
|
|
current-clock = <0x7a1200>;
|
|
status = "okay";
|
|
};
|
|
|
|
can@130d0000 {
|
|
compatible = "starfive,jh7110-can\0ipms,can";
|
|
reg = <0x00 0x130d0000 0x00 0x1000>;
|
|
interrupts = <0x70>;
|
|
clocks = <0x08 0x73 0x08 0x75 0x08 0x74>;
|
|
clock-names = "apb_clk\0core_clk\0timer_clk";
|
|
resets = <0x21 0x6f 0x21 0x70 0x21 0x71>;
|
|
reset-names = "rst_apb\0rst_core\0rst_timer";
|
|
frequency = <0x2625a00>;
|
|
starfive,sys-syscon = <0x1d 0x10 0x03 0x08>;
|
|
syscon,can_or_canfd = <0x00>;
|
|
status = "disabled";
|
|
};
|
|
|
|
can@130e0000 {
|
|
compatible = "starfive,jh7110-can\0ipms,can";
|
|
reg = <0x00 0x130e0000 0x00 0x1000>;
|
|
interrupts = <0x71>;
|
|
clocks = <0x08 0x76 0x08 0x78 0x08 0x77>;
|
|
clock-names = "apb_clk\0core_clk\0timer_clk";
|
|
resets = <0x21 0x72 0x21 0x73 0x21 0x74>;
|
|
reset-names = "rst_apb\0rst_core\0rst_timer";
|
|
frequency = <0x2625a00>;
|
|
starfive,sys-syscon = <0x1d 0x88 0x12 0x40000>;
|
|
syscon,can_or_canfd = <0x01>;
|
|
status = "disabled";
|
|
};
|
|
|
|
tdm@10090000 {
|
|
compatible = "starfive,jh7110-tdm";
|
|
reg = <0x00 0x10090000 0x00 0x1000>;
|
|
reg-names = "tdm";
|
|
clocks = <0x08 0xb8 0x08 0xb9 0x08 0xba 0x16 0x08 0xbb 0x08 0x11>;
|
|
clock-names = "clk_tdm_ahb\0clk_tdm_apb\0clk_tdm_internal\0clk_tdm_ext\0clk_tdm\0mclk_inner";
|
|
resets = <0x21 0x69 0x21 0x6b 0x21 0x6a>;
|
|
reset-names = "tdm_ahb\0tdm_apb\0tdm_rst";
|
|
dmas = <0x3d 0x14 0x01 0x3d 0x15 0x01>;
|
|
dma-names = "rx\0tx";
|
|
#sound-dai-cells = <0x00>;
|
|
status = "disabled";
|
|
};
|
|
|
|
spdif0@100a0000 {
|
|
compatible = "starfive,jh7110-spdif";
|
|
reg = <0x00 0x100a0000 0x00 0x1000>;
|
|
clocks = <0x08 0x9f 0x08 0xa0 0x08 0x10 0x08 0x11 0x17 0x08 0x12>;
|
|
clock-names = "spdif-apb\0spdif-core\0audroot\0mclk_inner\0mclk_ext\0mclk";
|
|
resets = <0x21 0x5f>;
|
|
reset-names = "rst_apb";
|
|
interrupts = <0x54>;
|
|
interrupt-names = "tx";
|
|
#sound-dai-cells = <0x00>;
|
|
status = "disabled";
|
|
};
|
|
|
|
pwmdac@100b0000 {
|
|
compatible = "starfive,jh7110-pwmdac";
|
|
reg = <0x00 0x100b0000 0x00 0x1000>;
|
|
clocks = <0x08 0x0c 0x08 0x9d 0x08 0x9e>;
|
|
clock-names = "apb0\0pwmdac-apb\0pwmdac-core";
|
|
resets = <0x21 0x60>;
|
|
reset-names = "rst-apb";
|
|
dmas = <0x3d 0x16 0x01>;
|
|
dma-names = "tx";
|
|
#sound-dai-cells = <0x00>;
|
|
status = "okay";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x3e>;
|
|
phandle = <0x5f>;
|
|
};
|
|
|
|
i2stx@100c0000 {
|
|
compatible = "snps,designware-i2stx";
|
|
reg = <0x00 0x100c0000 0x00 0x1000>;
|
|
interrupt-names = "tx";
|
|
#sound-dai-cells = <0x00>;
|
|
dmas = <0x3d 0x1c 0x01>;
|
|
dma-names = "rx";
|
|
status = "disabled";
|
|
};
|
|
|
|
pdm@100d0000 {
|
|
compatible = "starfive,jh7110-pdm";
|
|
reg = <0x00 0x100d0000 0x00 0x1000>;
|
|
reg-names = "pdm";
|
|
clocks = <0x08 0xb6 0x08 0xb7 0x08 0x12 0x17>;
|
|
clock-names = "pdm_mclk\0pdm_apb\0clk_mclk\0mclk_ext";
|
|
resets = <0x21 0x61 0x21 0x62>;
|
|
reset-names = "pdm_dmic\0pdm_apb";
|
|
#sound-dai-cells = <0x00>;
|
|
};
|
|
|
|
i2srx_mst@100e0000 {
|
|
compatible = "starfive,jh7110-i2srx-master";
|
|
reg = <0x00 0x100e0000 0x00 0x1000>;
|
|
clocks = <0x08 0x0c 0x08 0xaf 0x08 0xb0 0x08 0xb2 0x08 0xb3 0x08 0xb5 0x08 0x12 0x17>;
|
|
clock-names = "apb0\0i2srx_apb\0i2srx_bclk_mst\0i2srx_lrck_mst\0i2srx_bclk\0i2srx_lrck\0mclk\0mclk_ext";
|
|
resets = <0x21 0x63 0x21 0x64>;
|
|
reset-names = "rst_apb_rx\0rst_bclk_rx";
|
|
dmas = <0x3d 0x18 0x01>;
|
|
dma-names = "rx";
|
|
starfive,sys-syscon = <0x1d 0x18 0x34>;
|
|
#sound-dai-cells = <0x00>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2srx_3ch@100e0000 {
|
|
compatible = "starfive,jh7110-i2srx\0snps,designware-i2s";
|
|
reg = <0x00 0x100e0000 0x00 0x1000>;
|
|
clocks = <0x08 0x0c 0x08 0xaf 0x08 0x10 0x08 0x11 0x08 0xb0 0x08 0xb2 0x08 0xb3 0x08 0xb5 0x08 0x12 0x17 0x14 0x15>;
|
|
clock-names = "apb0\03ch-apb\0audioroot\0mclk-inner\0bclk_mst\03ch-lrck\0rx-bclk\0rx-lrck\0mclk\0mclk_ext\0bclk-ext\0lrck-ext";
|
|
resets = <0x21 0x63 0x21 0x64>;
|
|
dmas = <0x3d 0x18 0x01>;
|
|
dma-names = "rx";
|
|
starfive,sys-syscon = <0x1d 0x18 0x34>;
|
|
#sound-dai-cells = <0x00>;
|
|
status = "disabled";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x3f 0x40>;
|
|
};
|
|
|
|
i2stx_4ch0@120b0000 {
|
|
compatible = "starfive,jh7110-i2stx-4ch0\0snps,designware-i2s";
|
|
reg = <0x00 0x120b0000 0x00 0x1000>;
|
|
clocks = <0x08 0x11 0x08 0xa2 0x08 0xa4 0x08 0x12 0x08 0xa5 0x08 0xa7 0x08 0xa1 0x17>;
|
|
clock-names = "inner\0bclk-mst\0lrck-mst\0mclk\0bclk0\0lrck0\0i2s_apb\0mclk_ext";
|
|
resets = <0x21 0x65 0x21 0x66>;
|
|
reset-names = "rst_apb\0rst_bclk";
|
|
dmas = <0x3d 0x2f 0x01>;
|
|
dma-names = "tx";
|
|
#sound-dai-cells = <0x00>;
|
|
status = "okay";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x41>;
|
|
phandle = <0x5c>;
|
|
};
|
|
|
|
i2stx_4ch1@120c0000 {
|
|
compatible = "starfive,jh7110-i2stx-4ch1\0snps,designware-i2s";
|
|
reg = <0x00 0x120c0000 0x00 0x1000>;
|
|
clocks = <0x08 0x10 0x08 0x11 0x08 0xa9 0x08 0xab 0x08 0x12 0x08 0xac 0x08 0xae 0x08 0x13 0x08 0x0c 0x08 0xa8 0x17 0x12 0x13>;
|
|
clock-names = "audroot\0mclk_inner\0bclk_mst\0lrck_mst\0mclk\04chbclk\04chlrck\0mclk_out\0apb0\0clk_apb\0mclk_ext\0bclk_ext\0lrck_ext";
|
|
resets = <0x21 0x67 0x21 0x68>;
|
|
dmas = <0x3d 0x30 0x01>;
|
|
dma-names = "tx";
|
|
#sound-dai-cells = <0x00>;
|
|
status = "disabled";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x42>;
|
|
};
|
|
|
|
pwm@120d0000 {
|
|
compatible = "starfive,jh7110-pwm";
|
|
reg = <0x00 0x120d0000 0x00 0x10000>;
|
|
reg-names = "control";
|
|
clocks = <0x08 0x79>;
|
|
resets = <0x21 0x6c>;
|
|
starfive,approx-freq = <0x1e8480>;
|
|
#pwm-cells = <0x03>;
|
|
starfive,npwm = <0x08>;
|
|
status = "okay";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x43>;
|
|
};
|
|
|
|
spdif_transmitter {
|
|
compatible = "linux,spdif-dit";
|
|
#sound-dai-cells = <0x00>;
|
|
status = "disabled";
|
|
};
|
|
|
|
pwmdac-transmitter {
|
|
compatible = "starfive,jh7110-pwmdac-dit";
|
|
#sound-dai-cells = <0x00>;
|
|
status = "okay";
|
|
phandle = <0x60>;
|
|
};
|
|
|
|
dmic_codec {
|
|
compatible = "dmic-codec";
|
|
#sound-dai-cells = <0x00>;
|
|
status = "disabled";
|
|
};
|
|
|
|
spi@10060000 {
|
|
compatible = "arm,pl022\0arm,primecell";
|
|
reg = <0x00 0x10060000 0x00 0x10000>;
|
|
clocks = <0x08 0x83>;
|
|
clock-names = "apb_pclk";
|
|
resets = <0x21 0x45>;
|
|
reset-names = "rst_apb";
|
|
interrupts = <0x26>;
|
|
arm,primecell-periphid = <0x41022>;
|
|
num-cs = <0x01>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
status = "okay";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x44>;
|
|
|
|
spi@0 {
|
|
compatible = "rohm,dh2228fv";
|
|
pl022,com-mode = <0x01>;
|
|
spi-max-frequency = <0x989680>;
|
|
reg = <0x00>;
|
|
status = "okay";
|
|
};
|
|
};
|
|
|
|
spi@10070000 {
|
|
compatible = "arm,pl022\0arm,primecell";
|
|
reg = <0x00 0x10070000 0x00 0x10000>;
|
|
clocks = <0x08 0x84>;
|
|
clock-names = "apb_pclk";
|
|
resets = <0x21 0x46>;
|
|
reset-names = "rst_apb";
|
|
interrupts = <0x27>;
|
|
arm,primecell-periphid = <0x41022>;
|
|
num-cs = <0x01>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
status = "disabled";
|
|
};
|
|
|
|
spi@10080000 {
|
|
compatible = "arm,pl022\0arm,primecell";
|
|
reg = <0x00 0x10080000 0x00 0x10000>;
|
|
clocks = <0x08 0x85>;
|
|
clock-names = "apb_pclk";
|
|
resets = <0x21 0x47>;
|
|
reset-names = "rst_apb";
|
|
interrupts = <0x28>;
|
|
arm,primecell-periphid = <0x41022>;
|
|
num-cs = <0x01>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
status = "disabled";
|
|
};
|
|
|
|
spi@12070000 {
|
|
compatible = "arm,pl022\0arm,primecell";
|
|
reg = <0x00 0x12070000 0x00 0x10000>;
|
|
clocks = <0x08 0x86>;
|
|
clock-names = "apb_pclk";
|
|
resets = <0x21 0x48>;
|
|
reset-names = "rst_apb";
|
|
interrupts = <0x34>;
|
|
arm,primecell-periphid = <0x41022>;
|
|
num-cs = <0x01>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
status = "disabled";
|
|
};
|
|
|
|
spi@12080000 {
|
|
compatible = "arm,pl022\0arm,primecell";
|
|
reg = <0x00 0x12080000 0x00 0x10000>;
|
|
clocks = <0x08 0x87>;
|
|
clock-names = "apb_pclk";
|
|
resets = <0x21 0x49>;
|
|
reset-names = "rst_apb";
|
|
interrupts = <0x35>;
|
|
arm,primecell-periphid = <0x41022>;
|
|
num-cs = <0x01>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
status = "disabled";
|
|
};
|
|
|
|
spi@12090000 {
|
|
compatible = "arm,pl022\0arm,primecell";
|
|
reg = <0x00 0x12090000 0x00 0x10000>;
|
|
clocks = <0x08 0x88>;
|
|
clock-names = "apb_pclk";
|
|
resets = <0x21 0x4a>;
|
|
reset-names = "rst_apb";
|
|
interrupts = <0x36>;
|
|
arm,primecell-periphid = <0x41022>;
|
|
num-cs = <0x01>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
status = "disabled";
|
|
};
|
|
|
|
spi@120A0000 {
|
|
compatible = "arm,pl022\0arm,primecell";
|
|
reg = <0x00 0x120a0000 0x00 0x10000>;
|
|
clocks = <0x08 0x89>;
|
|
clock-names = "apb_pclk";
|
|
resets = <0x21 0x4b>;
|
|
reset-names = "rst_apb";
|
|
interrupts = <0x37>;
|
|
arm,primecell-periphid = <0x41022>;
|
|
num-cs = <0x01>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
status = "disabled";
|
|
};
|
|
|
|
pcie@2B000000 {
|
|
compatible = "starfive,jh7110-pcie\0plda,pci-xpressrich3-axi";
|
|
#address-cells = <0x03>;
|
|
#size-cells = <0x02>;
|
|
#interrupt-cells = <0x01>;
|
|
reg = <0x00 0x2b000000 0x00 0x1000000 0x09 0x40000000 0x00 0x10000000>;
|
|
reg-names = "reg\0config";
|
|
device_type = "pci";
|
|
starfive,stg-syscon = <0x23 0xc0 0xc4 0x130 0x1b8>;
|
|
starfive,phyctrl = <0x45 0x28 0x80>;
|
|
bus-range = <0x00 0xff>;
|
|
ranges = <0x82000000 0x00 0x30000000 0x00 0x30000000 0x00 0x8000000 0xc3000000 0x09 0x00 0x09 0x00 0x00 0x40000000>;
|
|
msi-parent = <0x09>;
|
|
interrupts = <0x38>;
|
|
interrupt-controller;
|
|
interrupt-names = "msi";
|
|
interrupt-parent = <0x09>;
|
|
interrupt-map-mask = <0x00 0x00 0x00 0x07>;
|
|
interrupt-map = <0x00 0x00 0x00 0x01 0x09 0x01 0x00 0x00 0x00 0x02 0x09 0x02 0x00 0x00 0x00 0x03 0x09 0x03 0x00 0x00 0x00 0x04 0x09 0x04>;
|
|
resets = <0x21 0x8b 0x21 0x8c 0x21 0x8d 0x21 0x8e 0x21 0x8f 0x21 0x90>;
|
|
reset-names = "rst_mst0\0rst_slv0\0rst_slv\0rst_brg\0rst_core\0rst_apb";
|
|
clocks = <0x08 0x60 0x08 0xc8 0x08 0xc6 0x08 0xc7>;
|
|
clock-names = "noc\0tl\0axi_mst0\0apb";
|
|
status = "okay";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x46 0x47>;
|
|
reset-gpios = <0x2c 0x1a 0x01>;
|
|
};
|
|
|
|
pcie@2C000000 {
|
|
compatible = "starfive,jh7110-pcie\0plda,pci-xpressrich3-axi";
|
|
#address-cells = <0x03>;
|
|
#size-cells = <0x02>;
|
|
#interrupt-cells = <0x01>;
|
|
reg = <0x00 0x2c000000 0x00 0x1000000 0x09 0xc0000000 0x00 0x10000000>;
|
|
reg-names = "reg\0config";
|
|
device_type = "pci";
|
|
starfive,stg-syscon = <0x23 0x270 0x274 0x2e0 0x368>;
|
|
starfive,phyctrl = <0x48 0x28 0x80>;
|
|
bus-range = <0x00 0xff>;
|
|
ranges = <0x82000000 0x00 0x38000000 0x00 0x38000000 0x00 0x8000000 0xc3000000 0x09 0x80000000 0x09 0x80000000 0x00 0x40000000>;
|
|
msi-parent = <0x09>;
|
|
interrupts = <0x39>;
|
|
interrupt-controller;
|
|
interrupt-names = "msi";
|
|
interrupt-parent = <0x09>;
|
|
interrupt-map-mask = <0x00 0x00 0x00 0x07>;
|
|
interrupt-map = <0x00 0x00 0x00 0x01 0x09 0x01 0x00 0x00 0x00 0x02 0x09 0x02 0x00 0x00 0x00 0x03 0x09 0x03 0x00 0x00 0x00 0x04 0x09 0x04>;
|
|
resets = <0x21 0x91 0x21 0x92 0x21 0x93 0x21 0x94 0x21 0x95 0x21 0x96>;
|
|
reset-names = "rst_mst0\0rst_slv0\0rst_slv\0rst_brg\0rst_core\0rst_apb";
|
|
clocks = <0x08 0x60 0x08 0xcb 0x08 0xc9 0x08 0xca>;
|
|
clock-names = "noc\0tl\0axi_mst0\0apb";
|
|
status = "okay";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x49 0x4a>;
|
|
reset-gpios = <0x2c 0x1c 0x01>;
|
|
};
|
|
|
|
mailbox@0 {
|
|
compatible = "starfive,mail_box";
|
|
reg = <0x00 0x13060000 0x00 0x1000>;
|
|
clocks = <0x08 0x71>;
|
|
clock-names = "clk_apb";
|
|
resets = <0x21 0x44>;
|
|
reset-names = "mbx_rre";
|
|
interrupts = <0x1a 0x1b>;
|
|
#mbox-cells = <0x02>;
|
|
status = "okay";
|
|
phandle = <0x4b>;
|
|
};
|
|
|
|
mailbox_client@0 {
|
|
compatible = "starfive,mailbox-test";
|
|
mbox-names = "rx\0tx";
|
|
mboxes = <0x4b 0x00 0x01 0x4b 0x01 0x00>;
|
|
status = "okay";
|
|
};
|
|
|
|
display-subsystem {
|
|
compatible = "starfive,jh7110-display\0verisilicon,display-subsystem";
|
|
ports = <0x4c>;
|
|
status = "okay";
|
|
};
|
|
|
|
dssctrl@295B0000 {
|
|
compatible = "starfive,jh7110-dssctrl\0verisilicon,dss-ctrl\0syscon";
|
|
reg = <0x00 0x295b0000 0x00 0x90>;
|
|
phandle = <0x4d>;
|
|
};
|
|
|
|
tda988x_pin {
|
|
compatible = "starfive,tda998x_rgb_pin";
|
|
status = "disabled";
|
|
};
|
|
|
|
rgb-output {
|
|
compatible = "starfive,jh7110-rgb_output\0verisilicon,rgb-encoder";
|
|
status = "disabled";
|
|
|
|
ports {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
port@0 {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
reg = <0x00>;
|
|
|
|
endpoint@0 {
|
|
reg = <0x00>;
|
|
remote-endpoint = <0x4c>;
|
|
phandle = <0x4f>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
dc8200@29400000 {
|
|
compatible = "starfive,jh7110-dc8200\0verisilicon,dc8200";
|
|
verisilicon,dss-syscon = <0x4d>;
|
|
reg = <0x00 0x29400000 0x00 0x100 0x00 0x29400800 0x00 0x2000 0x00 0x17030000 0x00 0x1000>;
|
|
interrupts = <0x5f>;
|
|
status = "okay";
|
|
clocks = <0x08 0x3c 0x08 0x3a 0x08 0x3e 0x08 0x3d 0x4e 0x07 0x4e 0x08 0x4e 0x04 0x4e 0x05 0x4e 0x06 0x08 0x3e 0x4e 0x09 0x1e 0x4e 0x01 0x4e 0x27 0x4e 0x28>;
|
|
clock-names = "noc_disp\0vout_src\0top_vout_axi\0top_vout_ahb\0pix_clk\0vout_pix1\0axi_clk\0core_clk\0vout_ahb\0vout_top_axi\0vout_top_lcd\0hdmitx0_pixelclk\0dc8200_pix0\0dc8200_pix0_out\0dc8200_pix1_out";
|
|
resets = <0x21 0x2b 0x21 0xe0 0x21 0xe1 0x21 0xe2 0x21 0x1a>;
|
|
reset-names = "rst_vout_src\0rst_axi\0rst_ahb\0rst_core\0rst_noc_disp";
|
|
|
|
port {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
endpoint@0 {
|
|
reg = <0x00>;
|
|
remote-endpoint = <0x4f>;
|
|
phandle = <0x4c>;
|
|
};
|
|
|
|
endpoint@1 {
|
|
reg = <0x01>;
|
|
remote-endpoint = <0x50>;
|
|
phandle = <0x5a>;
|
|
};
|
|
|
|
endpoint@2 {
|
|
reg = <0x02>;
|
|
remote-endpoint = <0x51>;
|
|
phandle = <0x52>;
|
|
};
|
|
};
|
|
};
|
|
|
|
dsi-output {
|
|
compatible = "starfive,jh7110-display-encoder\0verisilicon,dsi-encoder";
|
|
status = "okay";
|
|
|
|
ports {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
port@0 {
|
|
reg = <0x00>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x52>;
|
|
phandle = <0x51>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <0x01>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x53>;
|
|
phandle = <0x58>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
mipi-dphy@295e0000 {
|
|
compatible = "starfive,jh7110-mipi-dphy-tx\0m31,mipi-dphy-tx";
|
|
reg = <0x00 0x295e0000 0x00 0x10000>;
|
|
clocks = <0x4e 0x0e>;
|
|
clock-names = "dphy_txesc";
|
|
resets = <0x21 0xea 0x21 0xeb>;
|
|
reset-names = "dphy_sys\0dphy_txbytehs";
|
|
#phy-cells = <0x00>;
|
|
status = "okay";
|
|
phandle = <0x54>;
|
|
};
|
|
|
|
mipi@295d0000 {
|
|
compatible = "starfive,jh7110-mipi_dsi\0cdns,dsi";
|
|
reg = <0x00 0x295d0000 0x00 0x10000>;
|
|
interrupts = <0x62>;
|
|
reg-names = "dsi";
|
|
clocks = <0x4e 0x0b 0x4e 0x0a 0x4e 0x0d 0x4e 0x0c>;
|
|
clock-names = "sys\0apb\0txesc\0dpi";
|
|
resets = <0x21 0xe3 0x21 0xe4 0x21 0xe5 0x21 0xe6 0x21 0xe7 0x21 0xe8>;
|
|
reset-names = "dsi_dpi\0dsi_apb\0dsi_rxesc\0dsi_sys\0dsi_txbytehs\0dsi_txesc";
|
|
phys = <0x54>;
|
|
phy-names = "dphy";
|
|
status = "okay";
|
|
|
|
ports {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
port@0 {
|
|
reg = <0x00>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
endpoint@0 {
|
|
reg = <0x00>;
|
|
remote-endpoint = <0x55>;
|
|
phandle = <0x2b>;
|
|
};
|
|
|
|
endpoint@1 {
|
|
reg = <0x01>;
|
|
remote-endpoint = <0x56>;
|
|
phandle = <0x2d>;
|
|
};
|
|
|
|
endpoint@2 {
|
|
reg = <0x02>;
|
|
remote-endpoint = <0x57>;
|
|
phandle = <0x2e>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <0x01>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x58>;
|
|
phandle = <0x53>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
hdmi@29590000 {
|
|
compatible = "starfive,jh7110-hdmi\0inno,hdmi";
|
|
reg = <0x00 0x29590000 0x00 0x4000>;
|
|
interrupts = <0x63>;
|
|
status = "okay";
|
|
clocks = <0x4e 0x11 0x4e 0x0f 0x4e 0x10 0x1e>;
|
|
clock-names = "sysclk\0mclk\0bclk\0pclk";
|
|
resets = <0x21 0xe9>;
|
|
reset-names = "hdmi_tx";
|
|
#sound-dai-cells = <0x00>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x59>;
|
|
hpd-gpio = <0x2c 0x0f 0x00>;
|
|
phandle = <0x5d>;
|
|
|
|
port {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
endpoint@0 {
|
|
reg = <0x00>;
|
|
remote-endpoint = <0x5a>;
|
|
phandle = <0x50>;
|
|
};
|
|
};
|
|
};
|
|
|
|
snd-card0 {
|
|
compatible = "simple-audio-card";
|
|
simple-audio-card,name = "Starfive-AC108-Sound-Card";
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
};
|
|
|
|
snd-card1 {
|
|
compatible = "simple-audio-card";
|
|
simple-audio-card,name = "Starfive-HDMI-Sound-Card";
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
simple-audio-card,dai-link@0 {
|
|
reg = <0x00>;
|
|
format = "i2s";
|
|
bitclock-master = <0x5b>;
|
|
frame-master = <0x5b>;
|
|
mclk-fs = <0x100>;
|
|
status = "okay";
|
|
|
|
cpu {
|
|
sound-dai = <0x5c>;
|
|
phandle = <0x5b>;
|
|
};
|
|
|
|
codec {
|
|
sound-dai = <0x5d>;
|
|
};
|
|
};
|
|
};
|
|
|
|
snd-card2 {
|
|
compatible = "simple-audio-card";
|
|
simple-audio-card,name = "Starfive-PDM-Sound-Card";
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
};
|
|
|
|
snd-card3 {
|
|
compatible = "simple-audio-card";
|
|
simple-audio-card,name = "Starfive-PWMDAC-Sound-Card";
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
simple-audio-card,dai-link@0 {
|
|
reg = <0x00>;
|
|
format = "left_j";
|
|
bitclock-master = <0x5e>;
|
|
frame-master = <0x5e>;
|
|
status = "okay";
|
|
|
|
cpu {
|
|
sound-dai = <0x5f>;
|
|
phandle = <0x5e>;
|
|
};
|
|
|
|
codec {
|
|
sound-dai = <0x60>;
|
|
};
|
|
};
|
|
};
|
|
|
|
snd-card4 {
|
|
compatible = "simple-audio-card";
|
|
simple-audio-card,name = "Starfive-SPDIF-Sound-Card";
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
};
|
|
|
|
snd-card5 {
|
|
compatible = "simple-audio-card";
|
|
simple-audio-card,name = "Starfive-TDM-Sound-Card";
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
};
|
|
|
|
snd-card6 {
|
|
compatible = "simple-audio-card";
|
|
simple-audio-card,name = "Starfive-WM8960-Sound-Card";
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
};
|
|
|
|
e24@0 {
|
|
compatible = "starfive,e24";
|
|
reg = <0x00 0xc0110000 0x00 0x1000 0x00 0xc0111000 0x00 0x1f000>;
|
|
reg-names = "ecmd\0espace";
|
|
clocks = <0x08 0xd6 0x08 0xd7 0x08 0xd8>;
|
|
clock-names = "clk_rtc\0clk_core\0clk_dbg";
|
|
resets = <0x21 0x84>;
|
|
reset-names = "e24_core";
|
|
starfive,stg-syscon = <0x23>;
|
|
interrupt-parent = <0x09>;
|
|
firmware-name = "e24_elf";
|
|
irq-mode = <0x01>;
|
|
mbox-names = "tx\0rx";
|
|
mboxes = <0x4b 0x00 0x02 0x4b 0x02 0x00>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x01>;
|
|
ranges = <0xc0000000 0x00 0xc0000000 0x200000>;
|
|
status = "okay";
|
|
|
|
dsp@0 {
|
|
};
|
|
};
|
|
|
|
xrp@0 {
|
|
compatible = "cdns,xrp";
|
|
reg = <0x00 0x10230000 0x00 0x10000 0x00 0x10240000 0x00 0x10000>;
|
|
memory-region = <0x61>;
|
|
clocks = <0x08 0xbe>;
|
|
clock-names = "core_clk";
|
|
resets = <0x21 0x81 0x21 0x82>;
|
|
reset-names = "rst_core\0rst_axi";
|
|
starfive,stg-syscon = <0x23>;
|
|
firmware-name = "hifi4_elf";
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x01>;
|
|
ranges = <0x40000000 0x00 0x20000000 0x40000 0xf0000000 0x00 0xf0000000 0x3000000>;
|
|
status = "okay";
|
|
|
|
dsp@0 {
|
|
};
|
|
};
|
|
|
|
starfive,jh7110-cpufreq {
|
|
compatible = "starfive,jh7110-cpufreq";
|
|
clocks = <0x08 0x01>;
|
|
clock-names = "cpu_clk";
|
|
};
|
|
};
|
|
|
|
aliases {
|
|
spi0 = "/soc/spi@13010000";
|
|
gpio0 = "/soc/gpio@13040000";
|
|
ethernet0 = "/soc/ethernet@16030000";
|
|
ethernet1 = "/soc/ethernet@16040000";
|
|
mmc0 = "/soc/sdio0@16010000";
|
|
mmc1 = "/soc/sdio1@16020000";
|
|
serial0 = "/soc/serial@10000000";
|
|
serial3 = "/soc/serial@12000000";
|
|
i2c0 = "/soc/i2c@10030000";
|
|
i2c1 = "/soc/i2c@10040000";
|
|
i2c2 = "/soc/i2c@10050000";
|
|
i2c3 = "/soc/i2c@12030000";
|
|
i2c4 = "/soc/i2c@12040000";
|
|
i2c5 = "/soc/i2c@12050000";
|
|
i2c6 = "/soc/i2c@12060000";
|
|
};
|
|
|
|
chosen {
|
|
linux,initrd-start = <0x00 0x46100000>;
|
|
linux,initrd-end = <0x00 0x4c000000>;
|
|
stdout-path = "serial0:115200";
|
|
#bootargs = "debug console=ttyS0 rootwait";
|
|
};
|
|
|
|
memory@40000000 {
|
|
device_type = "memory";
|
|
reg = <0x00 0x40000000 0x01 0x00>;
|
|
};
|
|
|
|
reserved-memory {
|
|
#address-cells = <0x02>;
|
|
#size-cells = <0x02>;
|
|
ranges;
|
|
|
|
linux,cma {
|
|
compatible = "shared-dma-pool";
|
|
reusable;
|
|
size = <0x00 0x20000000>;
|
|
alignment = <0x00 0x1000>;
|
|
alloc-ranges = <0x00 0x80000000 0x00 0x20000000>;
|
|
linux,cma-default;
|
|
};
|
|
|
|
e24@c0000000 {
|
|
no-map;
|
|
reg = <0x00 0xc0110000 0x00 0xf0000>;
|
|
};
|
|
|
|
xrpbuffer@f0000000 {
|
|
reg = <0x00 0xf0000000 0x00 0x1ffffff 0x00 0xf2000000 0x00 0x1000 0x00 0xf2001000 0x00 0xfff000 0x00 0xf3000000 0x00 0x1000>;
|
|
phandle = <0x61>;
|
|
};
|
|
};
|
|
|
|
leds {
|
|
compatible = "gpio-leds";
|
|
|
|
led-ack {
|
|
gpios = <0x62 0x03 0x00>;
|
|
color = <0x02>;
|
|
function = "heartbeat";
|
|
linux,default-trigger = "heartbeat";
|
|
label = "ack";
|
|
};
|
|
};
|
|
|
|
gpio-restart {
|
|
compatible = "gpio-restart";
|
|
gpios = <0x2c 0x23 0x00>;
|
|
priority = <0xa0>;
|
|
};
|
|
};
|