mirror of
https://github.com/lupyuen/nuttx-star64.git
synced 2025-01-12 20:58:32 +08:00
355 lines
7.7 KiB
Text
355 lines
7.7 KiB
Text
/dts-v1/;
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/ {
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#address-cells = <0x02>;
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#size-cells = <0x02>;
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compatible = "riscv-virtio";
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model = "riscv-virtio,qemu";
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fw-cfg@10100000 {
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dma-coherent;
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reg = <0x00 0x10100000 0x00 0x18>;
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compatible = "qemu,fw-cfg-mmio";
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};
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flash@20000000 {
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bank-width = <0x04>;
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reg = <0x00 0x20000000 0x00 0x2000000 0x00 0x22000000 0x00 0x2000000>;
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compatible = "cfi-flash";
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};
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chosen {
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bootargs = [00];
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stdout-path = "/soc/uart@10000000";
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};
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memory@80000000 {
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device_type = "memory";
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reg = <0x00 0x80000000 0x00 0x8000000>;
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};
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cpus {
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#address-cells = <0x01>;
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#size-cells = <0x00>;
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timebase-frequency = <0x989680>;
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cpu@0 {
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phandle = <0x0f>;
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device_type = "cpu";
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reg = <0x00>;
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status = "okay";
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compatible = "riscv";
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riscv,isa = "rv64imafdcsuh";
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mmu-type = "riscv,sv48";
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interrupt-controller {
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#interrupt-cells = <0x01>;
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interrupt-controller;
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compatible = "riscv,cpu-intc";
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phandle = <0x10>;
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};
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};
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cpu@1 {
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phandle = <0x0d>;
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device_type = "cpu";
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reg = <0x01>;
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status = "okay";
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compatible = "riscv";
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riscv,isa = "rv64imafdcsuh";
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mmu-type = "riscv,sv48";
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interrupt-controller {
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#interrupt-cells = <0x01>;
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interrupt-controller;
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compatible = "riscv,cpu-intc";
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phandle = <0x0e>;
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};
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};
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cpu@2 {
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phandle = <0x0b>;
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device_type = "cpu";
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reg = <0x02>;
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status = "okay";
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compatible = "riscv";
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riscv,isa = "rv64imafdcsuh";
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mmu-type = "riscv,sv48";
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interrupt-controller {
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#interrupt-cells = <0x01>;
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interrupt-controller;
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compatible = "riscv,cpu-intc";
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phandle = <0x0c>;
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};
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};
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cpu@3 {
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phandle = <0x09>;
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device_type = "cpu";
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reg = <0x03>;
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status = "okay";
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compatible = "riscv";
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riscv,isa = "rv64imafdcsuh";
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mmu-type = "riscv,sv48";
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interrupt-controller {
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#interrupt-cells = <0x01>;
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interrupt-controller;
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compatible = "riscv,cpu-intc";
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phandle = <0x0a>;
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};
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};
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cpu@4 {
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phandle = <0x07>;
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device_type = "cpu";
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reg = <0x04>;
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status = "okay";
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compatible = "riscv";
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riscv,isa = "rv64imafdcsuh";
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mmu-type = "riscv,sv48";
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interrupt-controller {
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#interrupt-cells = <0x01>;
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interrupt-controller;
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compatible = "riscv,cpu-intc";
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phandle = <0x08>;
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};
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};
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cpu@5 {
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phandle = <0x05>;
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device_type = "cpu";
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reg = <0x05>;
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status = "okay";
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compatible = "riscv";
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riscv,isa = "rv64imafdcsuh";
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mmu-type = "riscv,sv48";
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interrupt-controller {
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#interrupt-cells = <0x01>;
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interrupt-controller;
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compatible = "riscv,cpu-intc";
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phandle = <0x06>;
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};
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};
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cpu@6 {
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phandle = <0x03>;
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device_type = "cpu";
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reg = <0x06>;
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status = "okay";
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compatible = "riscv";
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riscv,isa = "rv64imafdcsuh";
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mmu-type = "riscv,sv48";
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interrupt-controller {
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#interrupt-cells = <0x01>;
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interrupt-controller;
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compatible = "riscv,cpu-intc";
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phandle = <0x04>;
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};
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};
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cpu@7 {
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phandle = <0x01>;
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device_type = "cpu";
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reg = <0x07>;
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status = "okay";
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compatible = "riscv";
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riscv,isa = "rv64imafdcsuh";
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mmu-type = "riscv,sv48";
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interrupt-controller {
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#interrupt-cells = <0x01>;
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interrupt-controller;
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compatible = "riscv,cpu-intc";
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phandle = <0x02>;
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};
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};
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cpu-map {
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cluster0 {
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core0 {
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cpu = <0x0f>;
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};
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core1 {
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cpu = <0x0d>;
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};
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core2 {
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cpu = <0x0b>;
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};
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core3 {
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cpu = <0x09>;
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};
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core4 {
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cpu = <0x07>;
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};
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core5 {
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cpu = <0x05>;
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};
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core6 {
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cpu = <0x03>;
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};
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core7 {
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cpu = <0x01>;
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};
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};
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};
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};
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soc {
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#address-cells = <0x02>;
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#size-cells = <0x02>;
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compatible = "simple-bus";
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ranges;
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rtc@101000 {
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interrupts = <0x0b>;
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interrupt-parent = <0x11>;
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reg = <0x00 0x101000 0x00 0x1000>;
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compatible = "google,goldfish-rtc";
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};
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uart@10000000 {
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interrupts = <0x0a>;
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interrupt-parent = <0x11>;
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clock-frequency = "\08@";
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reg = <0x00 0x10000000 0x00 0x100>;
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compatible = "ns16550a";
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};
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poweroff {
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value = <0x5555>;
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offset = <0x00>;
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regmap = <0x12>;
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compatible = "syscon-poweroff";
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};
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reboot {
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value = <0x7777>;
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offset = <0x00>;
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regmap = <0x12>;
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compatible = "syscon-reboot";
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};
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test@100000 {
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phandle = <0x12>;
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reg = <0x00 0x100000 0x00 0x1000>;
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compatible = "sifive,test1\0sifive,test0\0syscon";
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};
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pci@30000000 {
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interrupt-map-mask = <0x1800 0x00 0x00 0x07>;
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interrupt-map = <0x00 0x00 0x00 0x01 0x11 0x20 0x00 0x00 0x00 0x02 0x11 0x21 0x00 0x00 0x00 0x03 0x11 0x22 0x00 0x00 0x00 0x04 0x11 0x23 0x800 0x00 0x00 0x01 0x11 0x21 0x800 0x00 0x00 0x02 0x11 0x22 0x800 0x00 0x00 0x03 0x11 0x23 0x800 0x00 0x00 0x04 0x11 0x20 0x1000 0x00 0x00 0x01 0x11 0x22 0x1000 0x00 0x00 0x02 0x11 0x23 0x1000 0x00 0x00 0x03 0x11 0x20 0x1000 0x00 0x00 0x04 0x11 0x21 0x1800 0x00 0x00 0x01 0x11 0x23 0x1800 0x00 0x00 0x02 0x11 0x20 0x1800 0x00 0x00 0x03 0x11 0x21 0x1800 0x00 0x00 0x04 0x11 0x22>;
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ranges = <0x1000000 0x00 0x00 0x00 0x3000000 0x00 0x10000 0x2000000 0x00 0x40000000 0x00 0x40000000 0x00 0x40000000 0x3000000 0x04 0x00 0x04 0x00 0x04 0x00>;
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reg = <0x00 0x30000000 0x00 0x10000000>;
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dma-coherent;
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bus-range = <0x00 0xff>;
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linux,pci-domain = <0x00>;
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device_type = "pci";
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compatible = "pci-host-ecam-generic";
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#size-cells = <0x02>;
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#interrupt-cells = <0x01>;
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#address-cells = <0x03>;
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};
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virtio_mmio@10008000 {
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interrupts = <0x08>;
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interrupt-parent = <0x11>;
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reg = <0x00 0x10008000 0x00 0x1000>;
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compatible = "virtio,mmio";
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};
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virtio_mmio@10007000 {
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interrupts = <0x07>;
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interrupt-parent = <0x11>;
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reg = <0x00 0x10007000 0x00 0x1000>;
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compatible = "virtio,mmio";
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};
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virtio_mmio@10006000 {
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interrupts = <0x06>;
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interrupt-parent = <0x11>;
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reg = <0x00 0x10006000 0x00 0x1000>;
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compatible = "virtio,mmio";
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};
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virtio_mmio@10005000 {
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interrupts = <0x05>;
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interrupt-parent = <0x11>;
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reg = <0x00 0x10005000 0x00 0x1000>;
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compatible = "virtio,mmio";
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};
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virtio_mmio@10004000 {
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interrupts = <0x04>;
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interrupt-parent = <0x11>;
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reg = <0x00 0x10004000 0x00 0x1000>;
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compatible = "virtio,mmio";
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};
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virtio_mmio@10003000 {
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interrupts = <0x03>;
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interrupt-parent = <0x11>;
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reg = <0x00 0x10003000 0x00 0x1000>;
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compatible = "virtio,mmio";
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};
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virtio_mmio@10002000 {
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interrupts = <0x02>;
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interrupt-parent = <0x11>;
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reg = <0x00 0x10002000 0x00 0x1000>;
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compatible = "virtio,mmio";
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};
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virtio_mmio@10001000 {
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interrupts = <0x01>;
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interrupt-parent = <0x11>;
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reg = <0x00 0x10001000 0x00 0x1000>;
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compatible = "virtio,mmio";
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};
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plic@c000000 {
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phandle = <0x11>;
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riscv,ndev = <0x35>;
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reg = <0x00 0xc000000 0x00 0x600000>;
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interrupts-extended = <0x10 0x0b 0x10 0x09 0x0e 0x0b 0x0e 0x09 0x0c 0x0b 0x0c 0x09 0x0a 0x0b 0x0a 0x09 0x08 0x0b 0x08 0x09 0x06 0x0b 0x06 0x09 0x04 0x0b 0x04 0x09 0x02 0x0b 0x02 0x09>;
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interrupt-controller;
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compatible = "sifive,plic-1.0.0\0riscv,plic0";
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#interrupt-cells = <0x01>;
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};
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sswi@2f00000 {
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#interrupt-cells = <0x00>;
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interrupt-controller;
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interrupts-extended = <0x10 0x01 0x0e 0x01 0x0c 0x01 0x0a 0x01 0x08 0x01 0x06 0x01 0x04 0x01 0x02 0x01>;
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reg = <0x00 0x2f00000 0x00 0x4000>;
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compatible = "riscv,aclint-sswi";
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};
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mtimer@2004000 {
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interrupts-extended = <0x10 0x07 0x0e 0x07 0x0c 0x07 0x0a 0x07 0x08 0x07 0x06 0x07 0x04 0x07 0x02 0x07>;
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reg = <0x00 0x200bff8 0x00 0x4008 0x00 0x2004000 0x00 0x7ff8>;
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compatible = "riscv,aclint-mtimer";
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};
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mswi@2000000 {
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#interrupt-cells = <0x00>;
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interrupt-controller;
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interrupts-extended = <0x10 0x03 0x0e 0x03 0x0c 0x03 0x0a 0x03 0x08 0x03 0x06 0x03 0x04 0x03 0x02 0x03>;
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reg = <0x00 0x2000000 0x00 0x4000>;
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compatible = "riscv,aclint-mswi";
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};
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};
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};
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