diff --git a/.gitignore b/.gitignore index a2cc0cb..b862219 100644 --- a/.gitignore +++ b/.gitignore @@ -1,2 +1,3 @@ zig-cache *.o +test/test diff --git a/test/arm64_arch.h b/test/arm64_arch.h new file mode 100644 index 0000000..968b078 --- /dev/null +++ b/test/arm64_arch.h @@ -0,0 +1,11 @@ +/// Modify the specified bits in a memory mapped register. +/// Based on https://github.com/apache/nuttx/blob/master/arch/arm64/src/common/arm64_arch.h#L473 +void modreg32( + uint32_t val, // Bits to set, like (1 << bit) + uint32_t mask, // Bits to clear, like (1 << bit) + unsigned long addr // Address to modify +); + +uint32_t getreg32(unsigned long addr); + +void putreg32(uint32_t data, unsigned long addr); diff --git a/test/debug.h b/test/debug.h new file mode 100644 index 0000000..0d46a3e --- /dev/null +++ b/test/debug.h @@ -0,0 +1,2 @@ +#define _err printf +#define _info printf diff --git a/test/expected.log b/test/expected.log new file mode 100644 index 0000000..054d695 --- /dev/null +++ b/test/expected.log @@ -0,0 +1,734 @@ +nsh> hello 3 +task_spawn: name=hello entry=0x4009b4f8 file_actions=0x40a80580 attr=0x40a80588 argv=0x40a806d0 +spawn_execattrs: Setting policy=2 priority=100 for pid=3 +ABHello, World!! +pd_cfg2_reg=0x77711177 +pd_data_reg=0x1c0000 +test_render: start, channels=3 +backlight_enable: start, percent=90 +Configure PL10 for PWM + *0x1f02c04: clear 0x700, set 0x200 + *0x1f02c04 = 0x77277 +Disable R_PWM + *0x1f03800: clear 0x40, set 0x0 + *0x1f03800 = 0x0 +Configure R_PWM Period + *0x1f03804 = 0x4af0437 +Enable R_PWM + *0x1f03800 = 0x5f +Configure PH10 for Output + *0x1c20900: clear 0x700, set 0x100 + *0x1c20900 = 0x7177 +Set PH10 to High + *0x1c2090c: clear 0x400, set 0x400 + *0x1c2090c = 0x400 +backlight_enable: end +tcon0_init: start +Configure PLL_VIDEO0 + *0x1c20010 = 0x81006207 +Enable LDO1 and LDO2 + *0x1c20040 = 0xc00000 +Configure MIPI PLL + *0x1c20040 = 0x80c0071a +Set TCON0 Clock Source to MIPI PLL + *0x1c20118 = 0x80000000 +Enable TCON0 Clock + *0x1c20064 = 0x8 +Deassert TCON0 Reset + *0x1c202c4 = 0x8 +Disable TCON0 and Interrupts + *0x1c0c000 = 0x0 + *0x1c0c004 = 0x0 + *0x1c0c008 = 0x0 +Enable Tristate Output + *0x1c0c08c = 0xffffffff + *0x1c0c0f4 = 0xffffffff +Set DCLK to MIPI PLL / 6 + *0x1c0c044 = 0x80000006 + *0x1c0c040 = 0x81000000 + *0x1c0c048 = 0x2cf059f + *0x1c0c0f8 = 0x8 + *0x1c0c060 = 0x10010005 +Set CPU Panel Trigger + *0x1c0c160 = 0x2f02cf + *0x1c0c164 = 0x59f + *0x1c0c168 = 0x1bc2000a +Set Safe Period + *0x1c0c1f0 = 0xbb80003 +Enable Output Triggers + *0x1c0c08c = 0xe0000000 +Enable TCON0 + *0x1c0c000: clear 0x80000000, set 0x80000000 + *0x1c0c000 = 0x80000000 +tcon0_init: end +display_board_init: start +Configure PD23 for Output + *0x1c20874: clear 0x70000000, set 0x10000000 + *0x1c20874 = 0x17711177 +Set PD23 to Low + *0x1c2087c: clear 0x800000, set 0x0 + *0x1c2087c = 0x1c0000 +Set DLDO1 Voltage to 3.3V + pmic_write: reg=0x15, val=0x1a + rsb_write: rt_addr=0x2d, reg_addr=0x15, value=0x1a + *0x1f0342c = 0x4e + *0x1f03430 = 0x2d0000 + *0x1f03410 = 0x15 + *0x1f0341c = 0x1a + *0x1f03400 = 0x80 + pmic_clrsetbits: reg=0x12, clr_mask=0x0, set_mask=0x8 + rsb_read: rt_addr=0x2d, reg_addr=0x12 + *0x1f0342c = 0x8b + *0x1f03430 = 0x2d0000 + *0x1f03410 = 0x12 + *0x1f03400 = 0x80 + rsb_write: rt_addr=0x2d, reg_addr=0x12, value=0xd9 + *0x1f0342c = 0x4e + *0x1f03430 = 0x2d0000 + *0x1f03410 = 0x12 + *0x1f0341c = 0xd9 + *0x1f03400 = 0x80 +Set LDO Voltage to 3.3V + pmic_write: reg=0x91, val=0x1a + rsb_write: rt_addr=0x2d, reg_addr=0x91, value=0x1a + *0x1f0342c = 0x4e + *0x1f03430 = 0x2d0000 + *0x1f03410 = 0x91 + *0x1f0341c = 0x1a + *0x1f03400 = 0x80 +Enable LDO mode on GPIO0 + pmic_write: reg=0x90, val=0x3 + rsb_write: rt_addr=0x2d, reg_addr=0x90, value=0x3 + *0x1f0342c = 0x4e + *0x1f03430 = 0x2d0000 + *0x1f03410 = 0x90 + *0x1f0341c = 0x3 + *0x1f03400 = 0x80 +Set DLDO2 Voltage to 1.8V + pmic_write: reg=0x16, val=0xb + rsb_write: rt_addr=0x2d, reg_addr=0x16, value=0xb + *0x1f0342c = 0x4e + *0x1f03430 = 0x2d0000 + *0x1f03410 = 0x16 + *0x1f0341c = 0xb + *0x1f03400 = 0x80 + pmic_clrsetbits: reg=0x12, clr_mask=0x0, set_mask=0x10 + rsb_read: rt_addr=0x2d, reg_addr=0x12 + *0x1f0342c = 0x8b + *0x1f03430 = 0x2d0000 + *0x1f03410 = 0x12 + *0x1f03400 = 0x80 + rsb_write: rt_addr=0x2d, reg_addr=0x12, value=0xd9 + *0x1f0342c = 0x4e + *0x1f03430 = 0x2d0000 + *0x1f03410 = 0x12 + *0x1f0341c = 0xd9 + *0x1f03400 = 0x80 +Wait for power supply and power-on init +display_board_init: end +enable_dsi_block: start +Enable MIPI DSI Bus + *0x1c20060: clear 0x2, set 0x2 + *0x1c20060 = 0x4742 + *0x1c202c0: clear 0x2, set 0x2 + *0x1c202c0 = 0x4742 +Enable DSI Block + *0x1ca0000 = 0x1 + *0x1ca0010 = 0x30000 + *0x1ca0060 = 0xa + *0x1ca0078 = 0x0 +Set Instructions + *0x1ca0020 = 0x1f + *0x1ca0024 = 0x10000001 + *0x1ca0028 = 0x20000010 + *0x1ca002c = 0x2000000f + *0x1ca0030 = 0x30100001 + *0x1ca0034 = 0x40000010 + *0x1ca0038 = 0xf + *0x1ca003c = 0x5000001f +Configure Jump Instructions + *0x1ca004c = 0x560001 + *0x1ca02f8 = 0xff +Set Video Start Delay + *0x1ca0014 = 0x5bc7 +Set Burst + *0x1ca007c = 0x10000007 +Set Instruction Loop + *0x1ca0040 = 0x30000002 + *0x1ca0044 = 0x310031 + *0x1ca0054 = 0x310031 +Set Pixel Format + *0x1ca0090 = 0x1308703e + *0x1ca0098 = 0xffff + *0x1ca009c = 0xffffffff + *0x1ca0080 = 0x10008 +Set Sync Timings + *0x1ca000c = 0x0 + *0x1ca00b0 = 0x12000021 + *0x1ca00b4 = 0x1000031 + *0x1ca00b8 = 0x7000001 + *0x1ca00bc = 0x14000011 +Set Basic Size + *0x1ca0018 = 0x11000a + *0x1ca001c = 0x5cd05a0 +Set Horizontal Blanking + *0x1ca00c0 = 0x9004a19 + *0x1ca00c4 = 0x50b40000 + *0x1ca00c8 = 0x35005419 + *0x1ca00cc = 0x757a0000 + *0x1ca00d0 = 0x9004a19 + *0x1ca00d4 = 0x50b40000 + *0x1ca00e0 = 0xc091a19 + *0x1ca00e4 = 0x72bd0000 +Set Vertical Blanking + *0x1ca00e8 = 0x1a000019 + *0x1ca00ec = 0xffff0000 +enable_dsi_block: end +dphy_enable: start +Set DSI Clock to 150 MHz + *0x1c20168 = 0x8203 +Power on DPHY Tx + *0x1ca1004 = 0x10000000 + *0x1ca1010 = 0xa06000e + *0x1ca1014 = 0xa033207 + *0x1ca1018 = 0x1e + *0x1ca101c = 0x0 + *0x1ca1020 = 0x303 +Enable DPHY + *0x1ca1000 = 0x31 + *0x1ca104c = 0x9f007f00 + *0x1ca1050 = 0x17000000 + *0x1ca105c = 0x1f01555 + *0x1ca1054 = 0x2 +Enable LDOR, LDOC, LDOD + *0x1ca1058 = 0x3040000 + *0x1ca1058: clear 0xf8000000, set 0xf8000000 + *0x1ca1058 = 0xfb040000 + *0x1ca1058: clear 0x4000000, set 0x4000000 + *0x1ca1058 = 0xff040000 + *0x1ca1054: clear 0x10, set 0x10 + *0x1ca1054 = 0x12 + *0x1ca1050: clear 0x80000000, set 0x80000000 + *0x1ca1050 = 0x97000000 + *0x1ca1054: clear 0xf000000, set 0xf000000 + *0x1ca1054 = 0xf000012 +dphy_enable: end +panel_reset: start +Configure PD23 for Output + *0x1c20874: clear 0x70000000, set 0x10000000 + *0x1c20874 = 0x17711177 +Set PD23 to High + *0x1c2087c: clear 0x800000, set 0x800000 + *0x1c2087c = 0x9c0000 +wait for initialization +panel_reset: end +panel_init: start +writeDcs: len=4 +b9 f1 12 83 +mipi_dsi_dcs_write: channel=0, cmd=0x39, len=4 +composeLongPacket: channel=0, cmd=0x39, len=4 +packet: len=10 +39 04 00 2c b9 f1 12 83 +84 5d + *0x1ca0300: clear 0xffffffff, set 0x2c000439 + *0x1ca0304: clear 0xffffffff, set 0x8312f1b9 + *0x1ca0308: clear 0xffffffff, set 0x5d84 + *0x1ca0200: clear 0xff, set 0x9 + *0x1ca0010: clear 0x1, set 0x0 + *0x1ca0010: clear 0x1, set 0x1 +writeDcs: len=28 +ba 33 81 05 f9 0e 0e 20 +00 00 00 00 00 00 00 44 +25 00 91 0a 00 00 02 4f +11 00 00 37 +mipi_dsi_dcs_write: channel=0, cmd=0x39, len=28 +composeLongPacket: channel=0, cmd=0x39, len=28 +packet: len=34 +39 1c 00 2f ba 33 81 05 +f9 0e 0e 20 00 00 00 00 +00 00 00 44 25 00 91 0a +00 00 02 4f 11 00 00 37 +2c e2 + *0x1ca0300: clear 0xffffffff, set 0x2f001c39 + *0x1ca0304: clear 0xffffffff, set 0x58133ba + *0x1ca0308: clear 0xffffffff, set 0x200e0ef9 + *0x1ca030c: clear 0xffffffff, set 0x0 + *0x1ca0310: clear 0xffffffff, set 0x44000000 + *0x1ca0314: clear 0xffffffff, set 0xa910025 + *0x1ca0318: clear 0xffffffff, set 0x4f020000 + *0x1ca031c: clear 0xffffffff, set 0x37000011 + *0x1ca0320: clear 0xffffffff, set 0xe22c + *0x1ca0200: clear 0xff, set 0x21 + *0x1ca0010: clear 0x1, set 0x0 + *0x1ca0010: clear 0x1, set 0x1 +writeDcs: len=5 +b8 25 22 20 03 +mipi_dsi_dcs_write: channel=0, cmd=0x39, len=5 +composeLongPacket: channel=0, cmd=0x39, len=5 +packet: len=11 +39 05 00 36 b8 25 22 20 +03 03 72 + *0x1ca0300: clear 0xffffffff, set 0x36000539 + *0x1ca0304: clear 0xffffffff, set 0x202225b8 + *0x1ca0308: clear 0xffffffff, set 0x720303 + *0x1ca0200: clear 0xff, set 0xa + *0x1ca0010: clear 0x1, set 0x0 + *0x1ca0010: clear 0x1, set 0x1 +writeDcs: len=11 +b3 10 10 05 05 03 ff 00 +00 00 00 +mipi_dsi_dcs_write: channel=0, cmd=0x39, len=11 +composeLongPacket: channel=0, cmd=0x39, len=11 +packet: len=17 +39 0b 00 2c b3 10 10 05 +05 03 ff 00 00 00 00 6f +bc + *0x1ca0300: clear 0xffffffff, set 0x2c000b39 + *0x1ca0304: clear 0xffffffff, set 0x51010b3 + *0x1ca0308: clear 0xffffffff, set 0xff0305 + *0x1ca030c: clear 0xffffffff, set 0x6f000000 + *0x1ca0310: clear 0xffffffff, set 0xbc + *0x1ca0200: clear 0xff, set 0x10 + *0x1ca0010: clear 0x1, set 0x0 + *0x1ca0010: clear 0x1, set 0x1 +writeDcs: len=10 +c0 73 73 50 50 00 c0 08 +70 00 +mipi_dsi_dcs_write: channel=0, cmd=0x39, len=10 +composeLongPacket: channel=0, cmd=0x39, len=10 +packet: len=16 +39 0a 00 36 c0 73 73 50 +50 00 c0 08 70 00 1b 6a + + *0x1ca0300: clear 0xffffffff, set 0x36000a39 + *0x1ca0304: clear 0xffffffff, set 0x507373c0 + *0x1ca0308: clear 0xffffffff, set 0x8c00050 + *0x1ca030c: clear 0xffffffff, set 0x6a1b0070 + *0x1ca0200: clear 0xff, set 0xf + *0x1ca0010: clear 0x1, set 0x0 + *0x1ca0010: clear 0x1, set 0x1 +writeDcs: len=2 +bc 4e +mipi_dsi_dcs_write: channel=0, cmd=0x15, len=2 +composeShortPacket: channel=0, cmd=0x15, len=2 +packet: len=4 +15 bc 4e 35 + *0x1ca0300: clear 0xffffffff, set 0x354ebc15 + *0x1ca0200: clear 0xff, set 0x3 + *0x1ca0010: clear 0x1, set 0x0 + *0x1ca0010: clear 0x1, set 0x1 +writeDcs: len=2 +cc 0b +mipi_dsi_dcs_write: channel=0, cmd=0x15, len=2 +composeShortPacket: channel=0, cmd=0x15, len=2 +packet: len=4 +15 cc 0b 22 + *0x1ca0300: clear 0xffffffff, set 0x220bcc15 + *0x1ca0200: clear 0xff, set 0x3 + *0x1ca0010: clear 0x1, set 0x0 + *0x1ca0010: clear 0x1, set 0x1 +writeDcs: len=2 +b4 80 +mipi_dsi_dcs_write: channel=0, cmd=0x15, len=2 +composeShortPacket: channel=0, cmd=0x15, len=2 +packet: len=4 +15 b4 80 22 + *0x1ca0300: clear 0xffffffff, set 0x2280b415 + *0x1ca0200: clear 0xff, set 0x3 + *0x1ca0010: clear 0x1, set 0x0 + *0x1ca0010: clear 0x1, set 0x1 +writeDcs: len=4 +b2 f0 12 f0 +mipi_dsi_dcs_write: channel=0, cmd=0x39, len=4 +composeLongPacket: channel=0, cmd=0x39, len=4 +packet: len=10 +39 04 00 2c b2 f0 12 f0 +51 86 + *0x1ca0300: clear 0xffffffff, set 0x2c000439 + *0x1ca0304: clear 0xffffffff, set 0xf012f0b2 + *0x1ca0308: clear 0xffffffff, set 0x8651 + *0x1ca0200: clear 0xff, set 0x9 + *0x1ca0010: clear 0x1, set 0x0 + *0x1ca0010: clear 0x1, set 0x1 +writeDcs: len=15 +e3 00 00 0b 0b 10 10 00 +00 00 00 ff 00 c0 10 +mipi_dsi_dcs_write: channel=0, cmd=0x39, len=15 +composeLongPacket: channel=0, cmd=0x39, len=15 +packet: len=21 +39 0f 00 0f e3 00 00 0b +0b 10 10 00 00 00 00 ff +00 c0 10 36 0f + *0x1ca0300: clear 0xffffffff, set 0xf000f39 + *0x1ca0304: clear 0xffffffff, set 0xb0000e3 + *0x1ca0308: clear 0xffffffff, set 0x10100b + *0x1ca030c: clear 0xffffffff, set 0xff000000 + *0x1ca0310: clear 0xffffffff, set 0x3610c000 + *0x1ca0314: clear 0xffffffff, set 0xf + *0x1ca0200: clear 0xff, set 0x14 + *0x1ca0010: clear 0x1, set 0x0 + *0x1ca0010: clear 0x1, set 0x1 +writeDcs: len=6 +c6 01 00 ff ff 00 +mipi_dsi_dcs_write: channel=0, cmd=0x39, len=6 +composeLongPacket: channel=0, cmd=0x39, len=6 +packet: len=12 +39 06 00 30 c6 01 00 ff +ff 00 8e 25 + *0x1ca0300: clear 0xffffffff, set 0x30000639 + *0x1ca0304: clear 0xffffffff, set 0xff0001c6 + *0x1ca0308: clear 0xffffffff, set 0x258e00ff + *0x1ca0200: clear 0xff, set 0xb + *0x1ca0010: clear 0x1, set 0x0 + *0x1ca0010: clear 0x1, set 0x1 +writeDcs: len=13 +c1 74 00 32 32 77 f1 ff +ff cc cc 77 77 +mipi_dsi_dcs_write: channel=0, cmd=0x39, len=13 +composeLongPacket: channel=0, cmd=0x39, len=13 +packet: len=19 +39 0d 00 13 c1 74 00 32 +32 77 f1 ff ff cc cc 77 +77 69 e4 + *0x1ca0300: clear 0xffffffff, set 0x13000d39 + *0x1ca0304: clear 0xffffffff, set 0x320074c1 + *0x1ca0308: clear 0xffffffff, set 0xfff17732 + *0x1ca030c: clear 0xffffffff, set 0x77ccccff + *0x1ca0310: clear 0xffffffff, set 0xe46977 + *0x1ca0200: clear 0xff, set 0x12 + *0x1ca0010: clear 0x1, set 0x0 + *0x1ca0010: clear 0x1, set 0x1 +writeDcs: len=3 +b5 07 07 +mipi_dsi_dcs_write: channel=0, cmd=0x39, len=3 +composeLongPacket: channel=0, cmd=0x39, len=3 +packet: len=9 +39 03 00 09 b5 07 07 7b +b3 + *0x1ca0300: clear 0xffffffff, set 0x9000339 + *0x1ca0304: clear 0xffffffff, set 0x7b0707b5 + *0x1ca0308: clear 0xffffffff, set 0xb3 + *0x1ca0200: clear 0xff, set 0x8 + *0x1ca0010: clear 0x1, set 0x0 + *0x1ca0010: clear 0x1, set 0x1 +writeDcs: len=3 +b6 2c 2c +mipi_dsi_dcs_write: channel=0, cmd=0x39, len=3 +composeLongPacket: channel=0, cmd=0x39, len=3 +packet: len=9 +39 03 00 09 b6 2c 2c 55 +04 + *0x1ca0300: clear 0xffffffff, set 0x9000339 + *0x1ca0304: clear 0xffffffff, set 0x552c2cb6 + *0x1ca0308: clear 0xffffffff, set 0x4 + *0x1ca0200: clear 0xff, set 0x8 + *0x1ca0010: clear 0x1, set 0x0 + *0x1ca0010: clear 0x1, set 0x1 +writeDcs: len=4 +bf 02 11 00 +mipi_dsi_dcs_write: channel=0, cmd=0x39, len=4 +composeLongPacket: channel=0, cmd=0x39, len=4 +packet: len=10 +39 04 00 2c bf 02 11 00 +b5 e9 + *0x1ca0300: clear 0xffffffff, set 0x2c000439 + *0x1ca0304: clear 0xffffffff, set 0x1102bf + *0x1ca0308: clear 0xffffffff, set 0xe9b5 + *0x1ca0200: clear 0xff, set 0x9 + *0x1ca0010: clear 0x1, set 0x0 + *0x1ca0010: clear 0x1, set 0x1 +writeDcs: len=64 +e9 82 10 06 05 a2 0a a5 +12 31 23 37 83 04 bc 27 +38 0c 00 03 00 00 00 0c +00 03 00 00 00 75 75 31 +88 88 88 88 88 88 13 88 +64 64 20 88 88 88 88 88 +88 02 88 00 00 00 00 00 +00 00 00 00 00 00 00 00 + +mipi_dsi_dcs_write: channel=0, cmd=0x39, len=64 +composeLongPacket: channel=0, cmd=0x39, len=64 +packet: len=70 +39 40 00 25 e9 82 10 06 +05 a2 0a a5 12 31 23 37 +83 04 bc 27 38 0c 00 03 +00 00 00 0c 00 03 00 00 +00 75 75 31 88 88 88 88 +88 88 13 88 64 64 20 88 +88 88 88 88 88 02 88 00 +00 00 00 00 00 00 00 00 +00 00 00 00 65 03 + *0x1ca0300: clear 0xffffffff, set 0x25004039 + *0x1ca0304: clear 0xffffffff, set 0x61082e9 + *0x1ca0308: clear 0xffffffff, set 0xa50aa205 + *0x1ca030c: clear 0xffffffff, set 0x37233112 + *0x1ca0310: clear 0xffffffff, set 0x27bc0483 + *0x1ca0314: clear 0xffffffff, set 0x3000c38 + *0x1ca0318: clear 0xffffffff, set 0xc000000 + *0x1ca031c: clear 0xffffffff, set 0x300 + *0x1ca0320: clear 0xffffffff, set 0x31757500 + *0x1ca0324: clear 0xffffffff, set 0x88888888 + *0x1ca0328: clear 0xffffffff, set 0x88138888 + *0x1ca032c: clear 0xffffffff, set 0x88206464 + *0x1ca0330: clear 0xffffffff, set 0x88888888 + *0x1ca0334: clear 0xffffffff, set 0x880288 + *0x1ca0338: clear 0xffffffff, set 0x0 + *0x1ca033c: clear 0xffffffff, set 0x0 + *0x1ca0340: clear 0xffffffff, set 0x0 + *0x1ca0344: clear 0xffffffff, set 0x365 + *0x1ca0200: clear 0xff, set 0x45 + *0x1ca0010: clear 0x1, set 0x0 + *0x1ca0010: clear 0x1, set 0x1 +writeDcs: len=62 +ea 02 21 00 00 00 00 00 +00 00 00 00 00 02 46 02 +88 88 88 88 88 88 64 88 +13 57 13 88 88 88 88 88 +88 75 88 23 14 00 00 02 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 03 +0a a5 00 00 00 00 +mipi_dsi_dcs_write: channel=0, cmd=0x39, len=62 +composeLongPacket: channel=0, cmd=0x39, len=62 +packet: len=68 +39 3e 00 1a ea 02 21 00 +00 00 00 00 00 00 00 00 +00 02 46 02 88 88 88 88 +88 88 64 88 13 57 13 88 +88 88 88 88 88 75 88 23 +14 00 00 02 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 03 0a a5 00 00 +00 00 24 1b + *0x1ca0300: clear 0xffffffff, set 0x1a003e39 + *0x1ca0304: clear 0xffffffff, set 0x2102ea + *0x1ca0308: clear 0xffffffff, set 0x0 + *0x1ca030c: clear 0xffffffff, set 0x0 + *0x1ca0310: clear 0xffffffff, set 0x2460200 + *0x1ca0314: clear 0xffffffff, set 0x88888888 + *0x1ca0318: clear 0xffffffff, set 0x88648888 + *0x1ca031c: clear 0xffffffff, set 0x88135713 + *0x1ca0320: clear 0xffffffff, set 0x88888888 + *0x1ca0324: clear 0xffffffff, set 0x23887588 + *0x1ca0328: clear 0xffffffff, set 0x2000014 + *0x1ca032c: clear 0xffffffff, set 0x0 + *0x1ca0330: clear 0xffffffff, set 0x0 + *0x1ca0334: clear 0xffffffff, set 0x0 + *0x1ca0338: clear 0xffffffff, set 0x3000000 + *0x1ca033c: clear 0xffffffff, set 0xa50a + *0x1ca0340: clear 0xffffffff, set 0x1b240000 + *0x1ca0200: clear 0xff, set 0x43 + *0x1ca0010: clear 0x1, set 0x0 + *0x1ca0010: clear 0x1, set 0x1 +writeDcs: len=35 +e0 00 09 0d 23 27 3c 41 +35 07 0d 0e 12 13 10 12 +12 18 00 09 0d 23 27 3c +41 35 07 0d 0e 12 13 10 +12 12 18 +mipi_dsi_dcs_write: channel=0, cmd=0x39, len=35 +composeLongPacket: channel=0, cmd=0x39, len=35 +packet: len=41 +39 23 00 20 e0 00 09 0d +23 27 3c 41 35 07 0d 0e +12 13 10 12 12 18 00 09 +0d 23 27 3c 41 35 07 0d +0e 12 13 10 12 12 18 93 +bf + *0x1ca0300: clear 0xffffffff, set 0x20002339 + *0x1ca0304: clear 0xffffffff, set 0xd0900e0 + *0x1ca0308: clear 0xffffffff, set 0x413c2723 + *0x1ca030c: clear 0xffffffff, set 0xe0d0735 + *0x1ca0310: clear 0xffffffff, set 0x12101312 + *0x1ca0314: clear 0xffffffff, set 0x9001812 + *0x1ca0318: clear 0xffffffff, set 0x3c27230d + *0x1ca031c: clear 0xffffffff, set 0xd073541 + *0x1ca0320: clear 0xffffffff, set 0x1013120e + *0x1ca0324: clear 0xffffffff, set 0x93181212 + *0x1ca0328: clear 0xffffffff, set 0xbf + *0x1ca0200: clear 0xff, set 0x28 + *0x1ca0010: clear 0x1, set 0x0 + *0x1ca0010: clear 0x1, set 0x1 +writeDcs: len=1 +11 +mipi_dsi_dcs_write: channel=0, cmd=0x5, len=1 +composeShortPacket: channel=0, cmd=0x5, len=1 +packet: len=4 +05 11 00 36 + *0x1ca0300: clear 0xffffffff, set 0x36001105 + *0x1ca0200: clear 0xff, set 0x3 + *0x1ca0010: clear 0x1, set 0x0 + *0x1ca0010: clear 0x1, set 0x1 +writeDcs: len=1 +29 +mipi_dsi_dcs_write: channel=0, cmd=0x5, len=1 +composeShortPacket: channel=0, cmd=0x5, len=1 +packet: len=4 +05 29 00 1c + *0x1ca0300: clear 0xffffffff, set 0x1c002905 + *0x1ca0200: clear 0xff, set 0x3 + *0x1ca0010: clear 0x1, set 0x0 + *0x1ca0010: clear 0x1, set 0x1 +panel_init: end +start_dsi: start +Start HSC + *0x1ca0048 = 0xf02 +Commit + *0x1ca0010: clear 0x1, set 0x1 + *0x1ca0010 = 0x30001 +Instruction Function Lane + *0x1ca0020: clear 0x10, set 0x0 + *0x1ca0020 = 0xf +Start HSD + *0x1ca0048 = 0x63f07006 +Commit + *0x1ca0010: clear 0x1, set 0x1 + *0x1ca0010 = 0x30001 +start_dsi: end +de2_init: start +Set High Speed SRAM to DMA Mode + *0x1c00004 = 0x0 +Set Display Engine PLL to 297 MHz + *0x1c20048 = 0x81001701 +Wait for Display Engine PLL to be stable +Set Special Clock to Display Engine PLL + *0x1c20104: clear 0x87000000, set 0x81000000 + *0x1c20104 = 0x81000000 +Enable AHB for Display Engine: De-Assert Display Engine + *0x1c202c4: clear 0x1000, set 0x1000 + *0x1c202c4 = 0x1008 +Enable AHB for Display Engine: Pass Display Engine + *0x1c20064: clear 0x1000, set 0x1000 + *0x1c20064 = 0x1008 +Enable Clock for MIXER0: SCLK Clock Pass + *0x1000000: clear 0x1, set 0x1 + *0x1000000 = 0x1 +Enable Clock for MIXER0: HCLK Clock Reset Off + *0x1000008: clear 0x1, set 0x1 + *0x1000008 = 0x1 +Enable Clock for MIXER0: HCLK Clock Pass + *0x1000004: clear 0x1, set 0x1 + *0x1000004 = 0x1 +Route MIXER0 to TCON0 + *0x1000010: clear 0x1, set 0x0 + *0x1000010 = 0x0 +Clear MIXER0 Registers: GLB, BLD, OVL_V, OVL_UI + *0x1100000 = 0x0 + to *0x1105fff = 0x0 +Disable MIXER0 VSU + *0x1120000 = 0x0 +Disable MIXER0 Undocumented + *0x1130000 = 0x0 +Disable MIXER0 UI_SCALER1 + *0x1140000 = 0x0 +Disable MIXER0 UI_SCALER2 + *0x1150000 = 0x0 +Disable MIXER0 FCE + *0x11a0000 = 0x0 +Disable MIXER0 BWS + *0x11a2000 = 0x0 +Disable MIXER0 LTI + *0x11a4000 = 0x0 +Disable MIXER0 PEAKING + *0x11a6000 = 0x0 +Disable MIXER0 ASE + *0x11a8000 = 0x0 +Disable MIXER0 FCC + *0x11aa000 = 0x0 +Disable MIXER0 DRC + *0x11b0000 = 0x0 +Enable MIXER0 + *0x1100000 = 0x1 +de2_init: end +renderGraphics: start +initUiBlender: start +Set Blender Background + *0x1101088 = 0xff000000 +Set Blender Pre-Multiply + *0x1101084 = 0x0 +initUiBlender: end +initUiChannel: start +Channel 1: Set Overlay (720 x 1440) + *0x1103000 = 0xff000405 + *0x1103010 = 0x4012c000 + *0x110300c = 0xb40 + *0x1103004 = 0x59f02cf + *0x1103088 = 0x59f02cf + *0x1103008 = 0x0 +Channel 1: Set Blender Output + *0x110108c = 0x59f02cf + *0x110000c = 0x59f02cf +Channel 1: Set Blender Input Pipe 0 (720 x 1440) + *0x1101008 = 0x59f02cf + *0x1101004 = 0xff000000 + *0x110100c = 0x0 + *0x1101090 = 0x3010301 +Channel 1: Disable Scaler + *0x1140000 = 0x0 +initUiChannel: end +initUiChannel: start +Channel 2: Set Overlay (600 x 600) + *0x1104000 = 0xff000005 + *0x1104010 = 0x40521000 + *0x110400c = 0x960 + *0x1104004 = 0x2570257 + *0x1104088 = 0x2570257 + *0x1104008 = 0x0 +Channel 2: Set Blender Input Pipe 1 (600 x 600) + *0x1101018 = 0x2570257 + *0x1101014 = 0xff000000 + *0x110101c = 0x340034 + *0x1101094 = 0x3010301 +Channel 2: Disable Scaler + *0x1150000 = 0x0 +initUiChannel: end +initUiChannel: start +Channel 3: Set Overlay (720 x 1440) + *0x1105000 = 0x7f000005 + *0x1105010 = 0x40681000 + *0x110500c = 0xb40 + *0x1105004 = 0x59f02cf + *0x1105088 = 0x59f02cf + *0x1105008 = 0x0 +Channel 3: Set Blender Input Pipe 2 (720 x 1440) + *0x1101028 = 0x59f02cf + *0x1101024 = 0xff000000 + *0x110102c = 0x0 + *0x1101098 = 0x3010301 +Channel 3: Disable Scaler + *0x1160000 = 0x0 +initUiChannel: end +applySettings: start +Set Blender Route + *0x1101080 = 0x321 +Enable Blender Pipes + *0x1101000 = 0x701 +Apply Settings + *0x1100008 = 0x1 +applySettings: end +renderGraphics: end +test_render: end +HELLO ZIG ON PINEPHONE! +test_zig: start +Testing Compose Short Packet (Without Parameter)... +composeShortPacket: channel=0, cmd=0x5, len=1 +Result: +05 11 00 36 +Testing Compose Short Packet (With Parameter)... +composeShortPacket: channel=0, cmd=0x15, len=2 +Result: +15 bc 4e 35 +Testing Compose Long Packet... +composeLongPacket: channel=0, cmd=0x39, len=64 +Result: +39 40 00 25 e9 82 10 06 +05 a2 0a a5 12 31 23 37 +83 04 bc 27 38 0c 00 03 +00 00 00 0c 00 03 00 00 +00 75 75 31 88 88 88 88 +88 88 13 88 64 64 20 88 +88 88 88 88 88 02 88 00 +00 00 00 00 00 00 00 00 +00 00 00 00 65 03 +test_zig: end \ No newline at end of file diff --git a/test/nuttx/arch.h b/test/nuttx/arch.h new file mode 100644 index 0000000..81ed60e --- /dev/null +++ b/test/nuttx/arch.h @@ -0,0 +1 @@ +void up_udelay(unsigned long microseconds); diff --git a/test/nuttx/config.h b/test/nuttx/config.h new file mode 100644 index 0000000..c80eb6e --- /dev/null +++ b/test/nuttx/config.h @@ -0,0 +1,7 @@ +#include +#include + +#define DEBUGASSERT assert +#define DEBUGPANIC() assert(false) +#define FAR +#define OK 0 diff --git a/test/run.sh b/test/run.sh new file mode 100755 index 0000000..28c1ac4 --- /dev/null +++ b/test/run.sh @@ -0,0 +1,19 @@ +#!/usr/bin/env bash +## Test Locally + +set -e # Exit when any command fails +set -x # Echo commands + +clear + +## Compile test code +gcc \ + -o test \ + -I ../../nuttx/arch/arm64/src/a64 \ + test.c \ + ../../nuttx/arch/arm64/src/a64/a64_mipi_dphy.c \ + ../../nuttx/arch/arm64/src/a64/a64_mipi_dsi.c \ + ../../nuttx/arch/arm64/src/a64/mipi_dsi.c + +## Run the test +./test diff --git a/test/test.c b/test/test.c new file mode 100644 index 0000000..49c6dd1 --- /dev/null +++ b/test/test.c @@ -0,0 +1,519 @@ +#include +#include +#include +#include +#include + +#include +#include "arm64_arch.h" +#include "mipi_dsi.h" +#include "a64_mipi_dsi.h" +#include "a64_mipi_dphy.h" + +/// MIPI DSI Virtual Channel +#define VIRTUAL_CHANNEL 0 + +static int panel_init(void); +static int write_dcs(FAR const uint8_t *buf, size_t len); +void dump_buffer(const uint8_t *data, size_t len); + +int main() +{ + int ret; + + // Enable MIPI DSI Block + ret = a64_mipi_dsi_enable(); + assert(ret == OK); + + // Enable MIPI Display Physical Layer (DPHY) + ret = a64_mipi_dphy_enable(); + assert(ret == OK); + + // Initialise LCD Controller (ST7703) + ret = panel_init(); + assert(ret == OK); + + // Start MIPI DSI HSC and HSD + ret = a64_mipi_dsi_start(); + assert(ret == OK); + + // Test MIPI DSI + void mipi_dsi_test(void); + mipi_dsi_test(); +} + +/// Initialise the ST7703 LCD Controller in Xingbangda XBD599 LCD Panel. +/// See https://lupyuen.github.io/articles/dsi#initialise-lcd-controller +static int panel_init(void) { + int ret; + _info("panel_init: start\n"); + + // Most of these commands are documented in the ST7703 Datasheet: + // https://files.pine64.org/doc/datasheet/pinephone/ST7703_DS_v01_20160128.pdf + + // Command #1 + const uint8_t cmd1[] = { + 0xB9, // SETEXTC (Page 131): Enable USER Command + 0xF1, // Enable User command + 0x12, // (Continued) + 0x83 // (Continued) + }; + ret = write_dcs(cmd1, sizeof(cmd1)); + assert(ret == OK); + + // Command #2 + const uint8_t cmd2[] = { + 0xBA, // SETMIPI (Page 144): Set MIPI related register + 0x33, // Virtual Channel = 0 (VC_Main = 0) ; Number of Lanes = 4 (Lane_Number = 3) + 0x81, // LDO = 1.7 V (DSI_LDO_SEL = 4) ; Terminal Resistance = 90 Ohm (RTERM = 1) + 0x05, // MIPI Low High Speed driving ability = x6 (IHSRX = 5) + 0xF9, // TXCLK speed in DSI LP mode = fDSICLK / 16 (Tx_clk_sel = 2) + 0x0E, // Min HFP number in DSI mode = 14 (HFP_OSC = 14) + 0x0E, // Min HBP number in DSI mode = 14 (HBP_OSC = 14) + 0x20, // Undocumented + 0x00, // Undocumented + 0x00, // Undocumented + 0x00, // Undocumented + 0x00, // Undocumented + 0x00, // Undocumented + 0x00, // Undocumented + 0x00, // Undocumented + 0x44, // Undocumented + 0x25, // Undocumented + 0x00, // Undocumented + 0x91, // Undocumented + 0x0a, // Undocumented + 0x00, // Undocumented + 0x00, // Undocumented + 0x02, // Undocumented + 0x4F, // Undocumented + 0x11, // Undocumented + 0x00, // Undocumented + 0x00, // Undocumented + 0x37 // Undocumented + }; + ret = write_dcs(cmd2, sizeof(cmd2)); + assert(ret == OK); + + // Command #3 + const uint8_t cmd3[] = { + 0xB8, // SETPOWER_EXT (Page 142): Set display related register + 0x25, // External power IC or PFM: VSP = FL1002, VSN = FL1002 (PCCS = 2) ; VCSW1 / VCSW2 Frequency for Pumping VSP / VSN = 1/4 Hsync (ECP_DC_DIV = 5) + 0x22, // VCSW1/VCSW2 soft start time = 15 ms (DT = 2) ; Pumping ratio of VSP / VSN with VCI = x2 (XDK_ECP = 1) + 0x20, // PFM operation frequency FoscD = Fosc/1 (PFM_DC_DIV = 0) + 0x03 // Enable power IC pumping frequency synchronization = Synchronize with external Hsync (ECP_SYNC_EN = 1) ; Enable VGH/VGL pumping frequency synchronization = Synchronize with external Hsync (VGX_SYNC_EN = 1) + }; + ret = write_dcs(cmd3, sizeof(cmd3)); + assert(ret == OK); + + // Command #4 + const uint8_t cmd4[] = { + 0xB3, // SETRGBIF (Page 134): Control RGB I/F porch timing for internal use + 0x10, // Vertical back porch HS number in Blank Frame Period = Hsync number 16 (VBP_RGB_GEN = 16) + 0x10, // Vertical front porch HS number in Blank Frame Period = Hsync number 16 (VFP_RGB_GEN = 16) + 0x05, // HBP OSC number in Blank Frame Period = OSC number 5 (DE_BP_RGB_GEN = 5) + 0x05, // HFP OSC number in Blank Frame Period = OSC number 5 (DE_FP_RGB_GEN = 5) + 0x03, // Undocumented + 0xFF, // Undocumented + 0x00, // Undocumented + 0x00, // Undocumented + 0x00, // Undocumented + 0x00 // Undocumented + }; + ret = write_dcs(cmd4, sizeof(cmd4)); + assert(ret == OK); + + // Command #5 + const uint8_t cmd5[] = { + 0xC0, // SETSCR (Page 147): Set related setting of Source driving + 0x73, // Source OP Amp driving period for positive polarity in Normal Mode: Source OP Period = 115*4/Fosc (N_POPON = 115) + 0x73, // Source OP Amp driving period for negative polarity in Normal Mode: Source OP Period = 115*4/Fosc (N_NOPON = 115) + 0x50, // Source OP Amp driving period for positive polarity in Idle mode: Source OP Period = 80*4/Fosc (I_POPON = 80) + 0x50, // Source OP Amp dirivng period for negative polarity in Idle Mode: Source OP Period = 80*4/Fosc (I_NOPON = 80) + 0x00, // (SCR Bits 24-31 = 0x00) + 0xC0, // (SCR Bits 16-23 = 0xC0) + 0x08, // Gamma bias current fine tune: Current xIbias = 4 (SCR Bits 9-13 = 4) ; (SCR Bits 8-15 = 0x08) + 0x70, // Source and Gamma bias current core tune: Ibias = 1 (SCR Bits 0-3 = 0) ; Source bias current fine tune: Current xIbias = 7 (SCR Bits 4-8 = 7) ; (SCR Bits 0-7 = 0x70) + 0x00 // Undocumented + }; + ret = write_dcs(cmd5, sizeof(cmd5)); + assert(ret == OK); + + // Command #6 + const uint8_t cmd6[] = { + 0xBC, // SETVDC (Page 146): Control NVDDD/VDDD Voltage + 0x4E // NVDDD voltage = -1.8 V (NVDDD_SEL = 4) ; VDDD voltage = 1.9 V (VDDD_SEL = 6) + }; + ret = write_dcs(cmd6, sizeof(cmd6)); + assert(ret == OK); + + // Command #7 + const uint8_t cmd7[] = { + 0xCC, // SETPANEL (Page 154): Set display related register + 0x0B // Enable reverse the source scan direction (SS_PANEL = 1) ; Normal vertical scan direction (GS_PANEL = 0) ; Normally black panel (REV_PANEL = 1) ; S1:S2:S3 = B:G:R (BGR_PANEL = 1) + }; + ret = write_dcs(cmd7, sizeof(cmd7)); + assert(ret == OK); + + // Command #8 + const uint8_t cmd8[] = { + 0xB4, // SETCYC (Page 135): Control display inversion type + 0x80 // Extra source for Zig-Zag Inversion = S2401 (ZINV_S2401_EN = 1) ; Row source data dislocates = Even row (ZINV_G_EVEN_EN = 0) ; Disable Zig-Zag Inversion (ZINV_EN = 0) ; Enable Zig-Zag1 Inversion (ZINV2_EN = 0) ; Normal mode inversion type = Column inversion (N_NW = 0) + }; + ret = write_dcs(cmd8, sizeof(cmd8)); + assert(ret == OK); + + // Command #9 + const uint8_t cmd9[] = { + 0xB2, // SETDISP (Page 132): Control the display resolution + 0xF0, // Gate number of vertical direction = 480 + (240*4) (NL = 240) + 0x12, // (RES_V_LSB = 0) ; Non-display area source output control: Source output = VSSD (BLK_CON = 1) ; Channel number of source direction = 720RGB (RESO_SEL = 2) + 0xF0 // Source voltage during Blanking Time when accessing Sleep-Out / Sleep-In command = GND (WHITE_GND_EN = 1) ; Blank timing control when access sleep out command: Blank Frame Period = 7 Frames (WHITE_FRAME_SEL = 7) ; Source output refresh control: Refresh Period = 0 Frames (ISC = 0) + }; + ret = write_dcs(cmd9, sizeof(cmd9)); + assert(ret == OK); + + // Command #10 + const uint8_t cmd10[] = { + 0xE3, // SETEQ (Page 159): Set EQ related register + 0x00, // Temporal spacing between HSYNC and PEQGND = 0*4/Fosc (PNOEQ = 0) + 0x00, // Temporal spacing between HSYNC and NEQGND = 0*4/Fosc (NNOEQ = 0) + 0x0B, // Source EQ GND period when Source up to positive voltage = 11*4/Fosc (PEQGND = 11) + 0x0B, // Source EQ GND period when Source down to negative voltage = 11*4/Fosc (NEQGND = 11) + 0x10, // Source EQ VCI period when Source up to positive voltage = 16*4/Fosc (PEQVCI = 16) + 0x10, // Source EQ VCI period when Source down to negative voltage = 16*4/Fosc (NEQVCI = 16) + 0x00, // Temporal period of PEQVCI1 = 0*4/Fosc (PEQVCI1 = 0) + 0x00, // Temporal period of NEQVCI1 = 0*4/Fosc (NEQVCI1 = 0) + 0x00, // (Reserved) + 0x00, // (Reserved) + 0xFF, // (Undocumented) + 0x00, // (Reserved) + 0xC0, // White pattern to protect GOA glass (ESD_DET_DATA_WHITE = 1) ; Enable ESD detection function to protect GOA glass (ESD_WHITE_EN = 1) + 0x10 // No Need VSYNC (additional frame) after Sleep-In command to display sleep-in blanking frame then into Sleep-In State (SLPIN_OPTION = 1) ; Enable video function detection (VEDIO_NO_CHECK_EN = 0) ; Disable ESD white pattern scanning voltage pull ground (ESD_WHITE_GND_EN = 0) ; ESD detection function period = 0 Frames (ESD_DET_TIME_SEL = 0) + }; + ret = write_dcs(cmd10, sizeof(cmd10)); + assert(ret == OK); + + // Command #11 + const uint8_t cmd11[] = { + 0xC6, // Undocumented + 0x01, // Undocumented + 0x00, // Undocumented + 0xFF, // Undocumented + 0xFF, // Undocumented + 0x00 // Undocumented + }; + ret = write_dcs(cmd11, sizeof(cmd11)); + assert(ret == OK); + + // Command #12 + const uint8_t cmd12[] = { + 0xC1, // SETPOWER (Page 149): Set related setting of power + 0x74, // VGH Voltage Adjustment = 17 V (VBTHS = 7) ; VGL Voltage Adjustment = -11 V (VBTLS = 4) + 0x00, // Enable VGH feedback voltage detection. Output voltage = VBTHS (FBOFF_VGH = 0) ; Enable VGL feedback voltage detection. Output voltage = VBTLS (FBOFF_VGL = 0) + 0x32, // VSPROUT Voltage = (VRH[5:0] x 0.05 + 3.3) x (VREF/4.8) if VREF [4]=0 (VRP = 50) + 0x32, // VSNROUT Voltage = (VRH[5:0] x 0.05 + 3.3) x (VREF/5.6) if VREF [4]=1 (VRN = 50) + 0x77, // Undocumented + 0xF1, // Enable VGL voltage Detect Function = VGL voltage Abnormal (VGL_DET_EN = 1) ; Enable VGH voltage Detect Function = VGH voltage Abnormal (VGH_DET_EN = 1) ; Enlarge VGL Voltage at "FBOFF_VGL=1" = "VGL=-15V" (VGL_TURBO = 1) ; Enlarge VGH Voltage at "FBOFF_VGH=1" = "VGH=20V" (VGH_TURBO = 1) ; (APS = 1) + 0xFF, // Left side VGH stage 1 pumping frequency = 1.5 MHz (VGH1_L_DIV = 15) ; Left side VGL stage 1 pumping frequency = 1.5 MHz (VGL1_L_DIV = 15) + 0xFF, // Right side VGH stage 1 pumping frequency = 1.5 MHz (VGH1_R_DIV = 15) ; Right side VGL stage 1 pumping frequency = 1.5 MHz (VGL1_R_DIV = 15) + 0xCC, // Left side VGH stage 2 pumping frequency = 2.6 MHz (VGH2_L_DIV = 12) ; Left side VGL stage 2 pumping frequency = 2.6 MHz (VGL2_L_DIV = 12) + 0xCC, // Right side VGH stage 2 pumping frequency = 2.6 MHz (VGH2_R_DIV = 12) ; Right side VGL stage 2 pumping frequency = 2.6 MHz (VGL2_R_DIV = 12) + 0x77, // Left side VGH stage 3 pumping frequency = 4.5 MHz (VGH3_L_DIV = 7) ; Left side VGL stage 3 pumping frequency = 4.5 MHz (VGL3_L_DIV = 7) + 0x77 // Right side VGH stage 3 pumping frequency = 4.5 MHz (VGH3_R_DIV = 7) ; Right side VGL stage 3 pumping frequency = 4.5 MHz (VGL3_R_DIV = 7) + }; + ret = write_dcs(cmd12, sizeof(cmd12)); + assert(ret == OK); + + // Command #13 + const uint8_t cmd13[] = { + 0xB5, // SETBGP (Page 136): Internal reference voltage setting + 0x07, // VREF Voltage: 4.2 V (VREF_SEL = 7) + 0x07 // NVREF Voltage: 4.2 V (NVREF_SEL = 7) + }; + ret = write_dcs(cmd13, sizeof(cmd13)); + assert(ret == OK); + + // Command #14 + const uint8_t cmd14[] = { + 0xB6, // SETVCOM (Page 137): Set VCOM Voltage + 0x2C, // VCOMDC voltage at "GS_PANEL=0" = -0.67 V (VCOMDC_F = 0x2C) + 0x2C // VCOMDC voltage at "GS_PANEL=1" = -0.67 V (VCOMDC_B = 0x2C) + }; + ret = write_dcs(cmd14, sizeof(cmd14)); + assert(ret == OK); + + // Command #15 + const uint8_t cmd15[] = { + 0xBF, // Undocumented + 0x02, // Undocumented + 0x11, // Undocumented + 0x00 // Undocumented + }; + ret = write_dcs(cmd15, sizeof(cmd15)); + assert(ret == OK); + + // Command #16 + const uint8_t cmd16[] = { + 0xE9, // SETGIP1 (Page 163): Set forward GIP timing + 0x82, // SHR0, SHR1, CHR, CHR2 refer to Internal DE (REF_EN = 1) ; (PANEL_SEL = 2) + 0x10, // Starting position of GIP STV group 0 = 4102 HSYNC (SHR0 Bits 8-12 = 0x10) + 0x06, // (SHR0 Bits 0-7 = 0x06) + 0x05, // Starting position of GIP STV group 1 = 1442 HSYNC (SHR1 Bits 8-12 = 0x05) + 0xA2, // (SHR1 Bits 0-7 = 0xA2) + 0x0A, // Distance of STV rising edge and HYSNC = 10*2 Fosc (SPON Bits 0-7 = 0x0A) + 0xA5, // Distance of STV falling edge and HYSNC = 165*2 Fosc (SPOFF Bits 0-7 = 0xA5) + 0x12, // STV0_1 distance with STV0_0 = 1 HSYNC (SHR0_1 = 1) ; STV0_2 distance with STV0_0 = 2 HSYNC (SHR0_2 = 2) + 0x31, // STV0_3 distance with STV0_0 = 3 HSYNC (SHR0_3 = 3) ; STV1_1 distance with STV1_0 = 1 HSYNC (SHR1_1 = 1) + 0x23, // STV1_2 distance with STV1_0 = 2 HSYNC (SHR1_2 = 2) ; STV1_3 distance with STV1_0 = 3 HSYNC (SHR1_3 = 3) + 0x37, // STV signal high pulse width = 3 HSYNC (SHP = 3) ; Total number of STV signal = 7 (SCP = 7) + 0x83, // Starting position of GIP CKV group 0 (CKV0_0) = 131 HSYNC (CHR = 0x83) + 0x04, // Distance of CKV rising edge and HYSNC = 4*2 Fosc (CON Bits 0-7 = 0x04) + 0xBC, // Distance of CKV falling edge and HYSNC = 188*2 Fosc (COFF Bits 0-7 = 0xBC) + 0x27, // CKV signal high pulse width = 2 HSYNC (CHP = 2) ; Total period cycle of CKV signal = 7 HSYNC (CCP = 7) + 0x38, // Extra gate counter at blanking area: Gate number = 56 (USER_GIP_GATE = 0x38) + 0x0C, // Left side GIP output pad signal = ??? (CGTS_L Bits 16-21 = 0x0C) + 0x00, // (CGTS_L Bits 8-15 = 0x00) + 0x03, // (CGTS_L Bits 0-7 = 0x03) + 0x00, // Normal polarity of Left side GIP output pad signal (CGTS_INV_L Bits 16-21 = 0x00) + 0x00, // (CGTS_INV_L Bits 8-15 = 0x00) + 0x00, // (CGTS_INV_L Bits 0-7 = 0x00) + 0x0C, // Right side GIP output pad signal = ??? (CGTS_R Bits 16-21 = 0x0C) + 0x00, // (CGTS_R Bits 8-15 = 0x00) + 0x03, // (CGTS_R Bits 0-7 = 0x03) + 0x00, // Normal polarity of Right side GIP output pad signal (CGTS_INV_R Bits 16-21 = 0x00) + 0x00, // (CGTS_INV_R Bits 8-15 = 0x00) + 0x00, // (CGTS_INV_R Bits 0-7 = 0x00) + 0x75, // Left side GIP output pad signal = ??? (COS1_L = 7) ; Left side GIP output pad signal = ??? (COS2_L = 5) + 0x75, // Left side GIP output pad signal = ??? (COS3_L = 7) ; (COS4_L = 5) + 0x31, // Left side GIP output pad signal = ??? (COS5_L = 3) ; (COS6_L = 1) + 0x88, // Reserved (Parameter 32) + 0x88, // Reserved (Parameter 33) + 0x88, // Reserved (Parameter 34) + 0x88, // Reserved (Parameter 35) + 0x88, // Reserved (Parameter 36) + 0x88, // Left side GIP output pad signal = ??? (COS17_L = 8) ; Left side GIP output pad signal = ??? (COS18_L = 8) + 0x13, // Left side GIP output pad signal = ??? (COS19_L = 1) ; Left side GIP output pad signal = ??? (COS20_L = 3) + 0x88, // Left side GIP output pad signal = ??? (COS21_L = 8) ; Left side GIP output pad signal = ??? (COS22_L = 8) + 0x64, // Right side GIP output pad signal = ??? (COS1_R = 6) ; Right side GIP output pad signal = ??? (COS2_R = 4) + 0x64, // Right side GIP output pad signal = ??? (COS3_R = 6) ; Right side GIP output pad signal = ??? (COS4_R = 4) + 0x20, // Right side GIP output pad signal = ??? (COS5_R = 2) ; Right side GIP output pad signal = ??? (COS6_R = 0) + 0x88, // Reserved (Parameter 43) + 0x88, // Reserved (Parameter 44) + 0x88, // Reserved (Parameter 45) + 0x88, // Reserved (Parameter 46) + 0x88, // Reserved (Parameter 47) + 0x88, // Right side GIP output pad signal = ??? (COS17_R = 8) ; Right side GIP output pad signal = ??? (COS18_R = 8) + 0x02, // Right side GIP output pad signal = ??? (COS19_R = 0) ; Right side GIP output pad signal = ??? (COS20_R = 2) + 0x88, // Right side GIP output pad signal = ??? (COS21_R = 8) ; Right side GIP output pad signal = ??? (COS22_R = 8) + 0x00, // (TCON_OPT = 0x00) + 0x00, // (GIP_OPT Bits 16-22 = 0x00) + 0x00, // (GIP_OPT Bits 8-15 = 0x00) + 0x00, // (GIP_OPT Bits 0-7 = 0x00) + 0x00, // Starting position of GIP CKV group 1 (CKV1_0) = 0 HSYNC (CHR2 = 0x00) + 0x00, // Distance of CKV1 rising edge and HYSNC = 0*2 Fosc (CON2 Bits 0-7 = 0x00) + 0x00, // Distance of CKV1 falling edge and HYSNC = 0*2 Fosc (COFF2 Bits 0-7 = 0x00) + 0x00, // CKV1 signal high pulse width = 0 HSYNC (CHP2 = 0) ; Total period cycle of CKV1 signal = 0 HSYNC (CCP2 = 0) + 0x00, // (CKS Bits 16-21 = 0x00) + 0x00, // (CKS Bits 8-15 = 0x00) + 0x00, // (CKS Bits 0-7 = 0x00) + 0x00, // (COFF Bits 8-9 = 0) ; (CON Bits 8-9 = 0) ; (SPOFF Bits 8-9 = 0) ; (SPON Bits 8-9 = 0) + 0x00 // (COFF2 Bits 8-9 = 0) ; (CON2 Bits 8-9 = 0) + }; + ret = write_dcs(cmd16, sizeof(cmd16)); + assert(ret == OK); + + // Command #17 + const uint8_t cmd17[] = { + 0xEA, // SETGIP2 (Page 170): Set backward GIP timing + 0x02, // YS2 Signal Mode = INYS1/INYS2 (YS2_SEL = 0) ; YS2 Signal Mode = INYS1/INYS2 (YS1_SEL = 0) ; Don't reverse YS2 signal (YS2_XOR = 0) ; Don't reverse YS1 signal (YS1_XOR = 0) ; Enable YS signal function (YS_FLAG_EN = 1) ; Disable ALL ON function (ALL_ON_EN = 0) + 0x21, // (GATE = 0x21) + 0x00, // (CK_ALL_ON_EN = 0) ; (STV_ALL_ON_EN = 0) ; Timing of YS1 and YS2 signal = ??? (CK_ALL_ON_WIDTH1 = 0) + 0x00, // Timing of YS1 and YS2 signal = ??? (CK_ALL_ON_WIDTH2 = 0) + 0x00, // Timing of YS1 and YS2 signal = ??? (CK_ALL_ON_WIDTH3 = 0) + 0x00, // (YS_FLAG_PERIOD = 0) + 0x00, // (YS2_SEL_2 = 0) ; (YS1_SEL_2 = 0) ; (YS2_XOR_2 = 0) ; (YS_FLAG_EN_2 = 0) ; (ALL_ON_EN_2 = 0) + 0x00, // Distance of GIP ALL On rising edge and DE = ??? (USER_GIP_GATE1_2 = 0) + 0x00, // (CK_ALL_ON_EN_2 = 0) ; (STV_ALL_ON_EN_2 = 0) ; (CK_ALL_ON_WIDTH1_2 = 0) + 0x00, // (CK_ALL_ON_WIDTH2_2 = 0) + 0x00, // (CK_ALL_ON_WIDTH3_2 = 0) + 0x00, // (YS_FLAG_PERIOD_2 = 0) + 0x02, // (COS1_L_GS = 0) ; (COS2_L_GS = 2) + 0x46, // (COS3_L_GS = 4) ; (COS4_L_GS = 6) + 0x02, // (COS5_L_GS = 0) ; (COS6_L_GS = 2) + 0x88, // Reserved (Parameter 16) + 0x88, // Reserved (Parameter 17) + 0x88, // Reserved (Parameter 18) + 0x88, // Reserved (Parameter 19) + 0x88, // Reserved (Parameter 20) + 0x88, // (COS17_L_GS = 8) ; (COS18_L_GS = 8) + 0x64, // (COS19_L_GS = 6) ; (COS20_L_GS = 4) + 0x88, // (COS21_L_GS = 8) ; (COS22_L_GS = 8) + 0x13, // (COS1_R_GS = 1) ; (COS2_R_GS = 3) + 0x57, // (COS3_R_GS = 5) ; (COS4_R_GS = 7) + 0x13, // (COS5_R_GS = 1) ; (COS6_R_GS = 3) + 0x88, // Reserved (Parameter 27) + 0x88, // Reserved (Parameter 28) + 0x88, // Reserved (Parameter 29) + 0x88, // Reserved (Parameter 30) + 0x88, // Reserved (Parameter 31) + 0x88, // (COS17_R_GS = 8) ; (COS18_R_GS = 8) + 0x75, // (COS19_R_GS = 7) ; (COS20_R_GS = 5) + 0x88, // (COS21_R_GS = 8) ; (COS22_R_GS = 8) + 0x23, // GIP output EQ signal: P_EQ = Yes, N_EQ = No (EQOPT = 2) ; GIP output EQ signal level: P_EQ = GND, N_EQ = GND (EQ_SEL = 3) + 0x14, // Distance of EQ rising edge and HYSNC = 20 Fosc (EQ_DELAY = 0x14) + 0x00, // Distance of EQ rising edge and HYSNC = 0 HSYNC (EQ_DELAY_HSYNC = 0) + 0x00, // (HSYNC_TO_CL1_CNT10 Bits 8-9 = 0) + 0x02, // GIP reference HSYNC between external HSYNC = 2 Fosc (HSYNC_TO_CL1_CNT10 Bits 0-7 = 2) + 0x00, // Undocumented (Parameter 40) + 0x00, // Undocumented (Parameter 41) + 0x00, // Undocumented (Parameter 42) + 0x00, // Undocumented (Parameter 43) + 0x00, // Undocumented (Parameter 44) + 0x00, // Undocumented (Parameter 45) + 0x00, // Undocumented (Parameter 46) + 0x00, // Undocumented (Parameter 47) + 0x00, // Undocumented (Parameter 48) + 0x00, // Undocumented (Parameter 49) + 0x00, // Undocumented (Parameter 50) + 0x00, // Undocumented (Parameter 51) + 0x00, // Undocumented (Parameter 52) + 0x00, // Undocumented (Parameter 53) + 0x00, // Undocumented (Parameter 54) + 0x03, // Undocumented (Parameter 55) + 0x0A, // Undocumented (Parameter 56) + 0xA5, // Undocumented (Parameter 57) + 0x00, // Undocumented (Parameter 58) + 0x00, // Undocumented (Parameter 59) + 0x00, // Undocumented (Parameter 60) + 0x00 // Undocumented (Parameter 61) + }; + ret = write_dcs(cmd17, sizeof(cmd17)); + assert(ret == OK); + + // Command #18 + const uint8_t cmd18[] = { + 0xE0, // SETGAMMA (Page 158): Set the gray scale voltage to adjust the gamma characteristics of the TFT panel + 0x00, // (PVR0 = 0x00) + 0x09, // (PVR1 = 0x09) + 0x0D, // (PVR2 = 0x0D) + 0x23, // (PVR3 = 0x23) + 0x27, // (PVR4 = 0x27) + 0x3C, // (PVR5 = 0x3C) + 0x41, // (PPR0 = 0x41) + 0x35, // (PPR1 = 0x35) + 0x07, // (PPK0 = 0x07) + 0x0D, // (PPK1 = 0x0D) + 0x0E, // (PPK2 = 0x0E) + 0x12, // (PPK3 = 0x12) + 0x13, // (PPK4 = 0x13) + 0x10, // (PPK5 = 0x10) + 0x12, // (PPK6 = 0x12) + 0x12, // (PPK7 = 0x12) + 0x18, // (PPK8 = 0x18) + 0x00, // (NVR0 = 0x00) + 0x09, // (NVR1 = 0x09) + 0x0D, // (NVR2 = 0x0D) + 0x23, // (NVR3 = 0x23) + 0x27, // (NVR4 = 0x27) + 0x3C, // (NVR5 = 0x3C) + 0x41, // (NPR0 = 0x41) + 0x35, // (NPR1 = 0x35) + 0x07, // (NPK0 = 0x07) + 0x0D, // (NPK1 = 0x0D) + 0x0E, // (NPK2 = 0x0E) + 0x12, // (NPK3 = 0x12) + 0x13, // (NPK4 = 0x13) + 0x10, // (NPK5 = 0x10) + 0x12, // (NPK6 = 0x12) + 0x12, // (NPK7 = 0x12) + 0x18 // (NPK8 = 0x18) + }; + ret = write_dcs(cmd18, sizeof(cmd18)); + assert(ret == OK); + + // Command #19 + const uint8_t cmd19[] = { + 0x11 // SLPOUT (Page 89): Turns off sleep mode (MIPI_DCS_EXIT_SLEEP_MODE) + }; + ret = write_dcs(cmd19, sizeof(cmd19)); + assert(ret == OK); + + // Wait 120 milliseconds + up_udelay(120 * 1000); + + // Command #20 + const uint8_t cmd20[] = { + 0x29 // Display On (Page 97): Recover from DISPLAY OFF mode (MIPI_DCS_SET_DISPLAY_ON) + }; + ret = write_dcs(cmd20, sizeof(cmd20)); + assert(ret == OK); + + _info("panel_init: end\n"); + return OK; +} + +/// Write the DCS Command to MIPI DSI +static int write_dcs(FAR const uint8_t *buf, size_t len) +{ + int ret = -1; + _info("writeDcs: len=%d\n", (int) len); + dump_buffer(buf, len); + assert(len > 0); + + // Do DCS Short Write or Long Write depending on command length + switch (len) + { + // DCS Short Write (without parameter) + case 1: + ret = a64_mipi_dsi_write(VIRTUAL_CHANNEL, + MIPI_DSI_DCS_SHORT_WRITE, + buf, len); + break; + + // DCS Short Write (with parameter) + case 2: + ret = a64_mipi_dsi_write(VIRTUAL_CHANNEL, + MIPI_DSI_DCS_SHORT_WRITE_PARAM, + buf, len); + break; + + // DCS Long Write + default: + ret = a64_mipi_dsi_write(VIRTUAL_CHANNEL, + MIPI_DSI_DCS_LONG_WRITE, + buf, len); + break; + }; + _info("ret=%d\n", ret); + DEBUGASSERT(ret == len); + + return OK; +} + +/// Modify the specified bits in a memory mapped register. +/// Based on https://github.com/apache/nuttx/blob/master/arch/arm64/src/common/arm64_arch.h#L473 +void modreg32( + uint32_t val, // Bits to set, like (1 << bit) + uint32_t mask, // Bits to clear, like (1 << bit) + unsigned long addr // Address to modify +) +{ + _info(" *0x%lx: clear 0x%x, set 0x%x\n", addr, mask, val & mask); + assert((val & mask) == val); +} + +uint32_t getreg32(unsigned long addr) +{ + return 0; +} + +void putreg32(uint32_t data, unsigned long addr) +{ + _info(" *0x%lx = 0x%x\n", addr, data); +} + +void up_udelay(unsigned long microseconds) +{ + _info(" up_udelay %ld\n", microseconds); +} diff --git a/test/test.log b/test/test.log new file mode 100644 index 0000000..3b58973 --- /dev/null +++ b/test/test.log @@ -0,0 +1,522 @@ +Enable MIPI DSI Bus + *0x1c20060: clear 0x2, set 0x2 + *0x1c202c0: clear 0x2, set 0x2 +Enable DSI Block + *0x1ca0000 = 0x1 + *0x1ca0010 = 0x30000 + *0x1ca0060 = 0xa + *0x1ca0078 = 0x0 +Set Instructions + *0x1ca0020 = 0x1f + *0x1ca0024 = 0x10000001 + *0x1ca0028 = 0x20000010 + *0x1ca002c = 0x2000000f + *0x1ca0030 = 0x30100001 + *0x1ca0034 = 0x40000010 + *0x1ca0038 = 0xf + *0x1ca003c = 0x5000001f +Configure Jump Instructions + *0x1ca004c = 0x560001 + *0x1ca02f8 = 0xff +Set Video Start Delay + *0x1ca0014 = 0x5bc7 +Set Burst + *0x1ca007c = 0x10000007 +Set Instruction Loop + *0x1ca0040 = 0x30000002 + *0x1ca0044 = 0x310031 + *0x1ca0054 = 0x310031 +Set Pixel Format + *0x1ca0090 = 0x1308703e + *0x1ca0098 = 0xffff + *0x1ca009c = 0xffffffff + *0x1ca0080 = 0x10008 +Set Sync Timings + *0x1ca000c = 0x0 + *0x1ca00b0 = 0x12000021 + *0x1ca00b4 = 0x1000031 + *0x1ca00b8 = 0x7000001 + *0x1ca00bc = 0x14000011 +Set Basic Size + *0x1ca0018 = 0x11000a + *0x1ca001c = 0x5cd05a0 +Set Horizontal Blanking + *0x1ca00c0 = 0x9004a19 + *0x1ca00c4 = 0x50b40000 + *0x1ca00c8 = 0x35005419 + *0x1ca00cc = 0x757a0000 + *0x1ca00d0 = 0x9004a19 + *0x1ca00d4 = 0x50b40000 + *0x1ca00e0 = 0xc091a19 + *0x1ca00e4 = 0x72bd0000 +Set Vertical Blanking + *0x1ca00e8 = 0x1a000019 + *0x1ca00ec = 0xffff0000 +Set DSI Clock to 150 MHz + *0x1c20168 = 0x8203 +Power on DPHY Tx + *0x1ca1004 = 0x10000000 + *0x1ca1010 = 0xa06000e + *0x1ca1014 = 0xa033207 + *0x1ca1018 = 0x1e + *0x1ca101c = 0x0 + *0x1ca1020 = 0x303 +Enable DPHY + *0x1ca1000 = 0x31 + *0x1ca104c = 0x9f007f00 + *0x1ca1050 = 0x17000000 + *0x1ca105c = 0x1f01555 + *0x1ca1054 = 0x2 + up_udelay 5 +Enable LDOR, LDOC, LDOD + *0x1ca1058 = 0x3040000 + up_udelay 1 + *0x1ca1058: clear 0xf8000000, set 0xf8000000 + up_udelay 1 + *0x1ca1058: clear 0x4000000, set 0x4000000 + up_udelay 1 + *0x1ca1054: clear 0x10, set 0x10 + up_udelay 1 + *0x1ca1050: clear 0x80000000, set 0x80000000 + *0x1ca1054: clear 0xf000000, set 0xf000000 +panel_init: start +writeDcs: len=4 +b9 f1 12 83 +channel=0, cmd=0x39, txlen=4 +channel=0, cmd=0x39, txlen=4 +packet: pktlen=10 +39 04 00 2c b9 f1 12 83 +84 5d + *0x1ca0200 = 0x6000200 + *0x1ca0300: clear 0xffffffff, set 0x2c000439 + *0x1ca0304: clear 0xffffffff, set 0x8312f1b9 + *0x1ca0308: clear 0xffffffff, set 0x5d84 + *0x1ca0200: clear 0xff, set 0x9 + *0x1ca0048 = 0xf0004 + *0x1ca0010: clear 0x1, set 0x0 + *0x1ca0010: clear 0x1, set 0x1 +ret=4 +writeDcs: len=28 +ba 33 81 05 f9 0e 0e 20 +00 00 00 00 00 00 00 44 +25 00 91 0a 00 00 02 4f +11 00 00 37 +channel=0, cmd=0x39, txlen=28 +channel=0, cmd=0x39, txlen=28 +packet: pktlen=34 +39 1c 00 2f ba 33 81 05 +f9 0e 0e 20 00 00 00 00 +00 00 00 44 25 00 91 0a +00 00 02 4f 11 00 00 37 +2c e2 + *0x1ca0200 = 0x6000200 + *0x1ca0300: clear 0xffffffff, set 0x2f001c39 + *0x1ca0304: clear 0xffffffff, set 0x58133ba + *0x1ca0308: clear 0xffffffff, set 0x200e0ef9 + *0x1ca030c: clear 0xffffffff, set 0x0 + *0x1ca0310: clear 0xffffffff, set 0x44000000 + *0x1ca0314: clear 0xffffffff, set 0xa910025 + *0x1ca0318: clear 0xffffffff, set 0x4f020000 + *0x1ca031c: clear 0xffffffff, set 0x37000011 + *0x1ca0320: clear 0xffffffff, set 0xe22c + *0x1ca0200: clear 0xff, set 0x21 + *0x1ca0048 = 0xf0004 + *0x1ca0010: clear 0x1, set 0x0 + *0x1ca0010: clear 0x1, set 0x1 +ret=28 +writeDcs: len=5 +b8 25 22 20 03 +channel=0, cmd=0x39, txlen=5 +channel=0, cmd=0x39, txlen=5 +packet: pktlen=11 +39 05 00 36 b8 25 22 20 +03 03 72 + *0x1ca0200 = 0x6000200 + *0x1ca0300: clear 0xffffffff, set 0x36000539 + *0x1ca0304: clear 0xffffffff, set 0x202225b8 + *0x1ca0308: clear 0xffffffff, set 0x720303 + *0x1ca0200: clear 0xff, set 0xa + *0x1ca0048 = 0xf0004 + *0x1ca0010: clear 0x1, set 0x0 + *0x1ca0010: clear 0x1, set 0x1 +ret=5 +writeDcs: len=11 +b3 10 10 05 05 03 ff 00 +00 00 00 +channel=0, cmd=0x39, txlen=11 +channel=0, cmd=0x39, txlen=11 +packet: pktlen=17 +39 0b 00 2c b3 10 10 05 +05 03 ff 00 00 00 00 6f +bc + *0x1ca0200 = 0x6000200 + *0x1ca0300: clear 0xffffffff, set 0x2c000b39 + *0x1ca0304: clear 0xffffffff, set 0x51010b3 + *0x1ca0308: clear 0xffffffff, set 0xff0305 + *0x1ca030c: clear 0xffffffff, set 0x6f000000 + *0x1ca0310: clear 0xffffffff, set 0xbc + *0x1ca0200: clear 0xff, set 0x10 + *0x1ca0048 = 0xf0004 + *0x1ca0010: clear 0x1, set 0x0 + *0x1ca0010: clear 0x1, set 0x1 +ret=11 +writeDcs: len=10 +c0 73 73 50 50 00 c0 08 +70 00 +channel=0, cmd=0x39, txlen=10 +channel=0, cmd=0x39, txlen=10 +packet: pktlen=16 +39 0a 00 36 c0 73 73 50 +50 00 c0 08 70 00 1b 6a + + *0x1ca0200 = 0x6000200 + *0x1ca0300: clear 0xffffffff, set 0x36000a39 + *0x1ca0304: clear 0xffffffff, set 0x507373c0 + *0x1ca0308: clear 0xffffffff, set 0x8c00050 + *0x1ca030c: clear 0xffffffff, set 0x6a1b0070 + *0x1ca0200: clear 0xff, set 0xf + *0x1ca0048 = 0xf0004 + *0x1ca0010: clear 0x1, set 0x0 + *0x1ca0010: clear 0x1, set 0x1 +ret=10 +writeDcs: len=2 +bc 4e +channel=0, cmd=0x15, txlen=2 +channel=0, cmd=0x15, txlen=2 +packet: pktlen=4 +15 bc 4e 35 + *0x1ca0200 = 0x6000200 + *0x1ca0300: clear 0xffffffff, set 0x354ebc15 + *0x1ca0200: clear 0xff, set 0x3 + *0x1ca0048 = 0xf0004 + *0x1ca0010: clear 0x1, set 0x0 + *0x1ca0010: clear 0x1, set 0x1 +ret=2 +writeDcs: len=2 +cc 0b +channel=0, cmd=0x15, txlen=2 +channel=0, cmd=0x15, txlen=2 +packet: pktlen=4 +15 cc 0b 22 + *0x1ca0200 = 0x6000200 + *0x1ca0300: clear 0xffffffff, set 0x220bcc15 + *0x1ca0200: clear 0xff, set 0x3 + *0x1ca0048 = 0xf0004 + *0x1ca0010: clear 0x1, set 0x0 + *0x1ca0010: clear 0x1, set 0x1 +ret=2 +writeDcs: len=2 +b4 80 +channel=0, cmd=0x15, txlen=2 +channel=0, cmd=0x15, txlen=2 +packet: pktlen=4 +15 b4 80 22 + *0x1ca0200 = 0x6000200 + *0x1ca0300: clear 0xffffffff, set 0x2280b415 + *0x1ca0200: clear 0xff, set 0x3 + *0x1ca0048 = 0xf0004 + *0x1ca0010: clear 0x1, set 0x0 + *0x1ca0010: clear 0x1, set 0x1 +ret=2 +writeDcs: len=4 +b2 f0 12 f0 +channel=0, cmd=0x39, txlen=4 +channel=0, cmd=0x39, txlen=4 +packet: pktlen=10 +39 04 00 2c b2 f0 12 f0 +51 86 + *0x1ca0200 = 0x6000200 + *0x1ca0300: clear 0xffffffff, set 0x2c000439 + *0x1ca0304: clear 0xffffffff, set 0xf012f0b2 + *0x1ca0308: clear 0xffffffff, set 0x8651 + *0x1ca0200: clear 0xff, set 0x9 + *0x1ca0048 = 0xf0004 + *0x1ca0010: clear 0x1, set 0x0 + *0x1ca0010: clear 0x1, set 0x1 +ret=4 +writeDcs: len=15 +e3 00 00 0b 0b 10 10 00 +00 00 00 ff 00 c0 10 +channel=0, cmd=0x39, txlen=15 +channel=0, cmd=0x39, txlen=15 +packet: pktlen=21 +39 0f 00 0f e3 00 00 0b +0b 10 10 00 00 00 00 ff +00 c0 10 36 0f + *0x1ca0200 = 0x6000200 + *0x1ca0300: clear 0xffffffff, set 0xf000f39 + *0x1ca0304: clear 0xffffffff, set 0xb0000e3 + *0x1ca0308: clear 0xffffffff, set 0x10100b + *0x1ca030c: clear 0xffffffff, set 0xff000000 + *0x1ca0310: clear 0xffffffff, set 0x3610c000 + *0x1ca0314: clear 0xffffffff, set 0xf + *0x1ca0200: clear 0xff, set 0x14 + *0x1ca0048 = 0xf0004 + *0x1ca0010: clear 0x1, set 0x0 + *0x1ca0010: clear 0x1, set 0x1 +ret=15 +writeDcs: len=6 +c6 01 00 ff ff 00 +channel=0, cmd=0x39, txlen=6 +channel=0, cmd=0x39, txlen=6 +packet: pktlen=12 +39 06 00 30 c6 01 00 ff +ff 00 8e 25 + *0x1ca0200 = 0x6000200 + *0x1ca0300: clear 0xffffffff, set 0x30000639 + *0x1ca0304: clear 0xffffffff, set 0xff0001c6 + *0x1ca0308: clear 0xffffffff, set 0x258e00ff + *0x1ca0200: clear 0xff, set 0xb + *0x1ca0048 = 0xf0004 + *0x1ca0010: clear 0x1, set 0x0 + *0x1ca0010: clear 0x1, set 0x1 +ret=6 +writeDcs: len=13 +c1 74 00 32 32 77 f1 ff +ff cc cc 77 77 +channel=0, cmd=0x39, txlen=13 +channel=0, cmd=0x39, txlen=13 +packet: pktlen=19 +39 0d 00 13 c1 74 00 32 +32 77 f1 ff ff cc cc 77 +77 69 e4 + *0x1ca0200 = 0x6000200 + *0x1ca0300: clear 0xffffffff, set 0x13000d39 + *0x1ca0304: clear 0xffffffff, set 0x320074c1 + *0x1ca0308: clear 0xffffffff, set 0xfff17732 + *0x1ca030c: clear 0xffffffff, set 0x77ccccff + *0x1ca0310: clear 0xffffffff, set 0xe46977 + *0x1ca0200: clear 0xff, set 0x12 + *0x1ca0048 = 0xf0004 + *0x1ca0010: clear 0x1, set 0x0 + *0x1ca0010: clear 0x1, set 0x1 +ret=13 +writeDcs: len=3 +b5 07 07 +channel=0, cmd=0x39, txlen=3 +channel=0, cmd=0x39, txlen=3 +packet: pktlen=9 +39 03 00 09 b5 07 07 7b +b3 + *0x1ca0200 = 0x6000200 + *0x1ca0300: clear 0xffffffff, set 0x9000339 + *0x1ca0304: clear 0xffffffff, set 0x7b0707b5 + *0x1ca0308: clear 0xffffffff, set 0xb3 + *0x1ca0200: clear 0xff, set 0x8 + *0x1ca0048 = 0xf0004 + *0x1ca0010: clear 0x1, set 0x0 + *0x1ca0010: clear 0x1, set 0x1 +ret=3 +writeDcs: len=3 +b6 2c 2c +channel=0, cmd=0x39, txlen=3 +channel=0, cmd=0x39, txlen=3 +packet: pktlen=9 +39 03 00 09 b6 2c 2c 55 +04 + *0x1ca0200 = 0x6000200 + *0x1ca0300: clear 0xffffffff, set 0x9000339 + *0x1ca0304: clear 0xffffffff, set 0x552c2cb6 + *0x1ca0308: clear 0xffffffff, set 0x4 + *0x1ca0200: clear 0xff, set 0x8 + *0x1ca0048 = 0xf0004 + *0x1ca0010: clear 0x1, set 0x0 + *0x1ca0010: clear 0x1, set 0x1 +ret=3 +writeDcs: len=4 +bf 02 11 00 +channel=0, cmd=0x39, txlen=4 +channel=0, cmd=0x39, txlen=4 +packet: pktlen=10 +39 04 00 2c bf 02 11 00 +b5 e9 + *0x1ca0200 = 0x6000200 + *0x1ca0300: clear 0xffffffff, set 0x2c000439 + *0x1ca0304: clear 0xffffffff, set 0x1102bf + *0x1ca0308: clear 0xffffffff, set 0xe9b5 + *0x1ca0200: clear 0xff, set 0x9 + *0x1ca0048 = 0xf0004 + *0x1ca0010: clear 0x1, set 0x0 + *0x1ca0010: clear 0x1, set 0x1 +ret=4 +writeDcs: len=64 +e9 82 10 06 05 a2 0a a5 +12 31 23 37 83 04 bc 27 +38 0c 00 03 00 00 00 0c +00 03 00 00 00 75 75 31 +88 88 88 88 88 88 13 88 +64 64 20 88 88 88 88 88 +88 02 88 00 00 00 00 00 +00 00 00 00 00 00 00 00 + +channel=0, cmd=0x39, txlen=64 +channel=0, cmd=0x39, txlen=64 +packet: pktlen=70 +39 40 00 25 e9 82 10 06 +05 a2 0a a5 12 31 23 37 +83 04 bc 27 38 0c 00 03 +00 00 00 0c 00 03 00 00 +00 75 75 31 88 88 88 88 +88 88 13 88 64 64 20 88 +88 88 88 88 88 02 88 00 +00 00 00 00 00 00 00 00 +00 00 00 00 65 03 + *0x1ca0200 = 0x6000200 + *0x1ca0300: clear 0xffffffff, set 0x25004039 + *0x1ca0304: clear 0xffffffff, set 0x61082e9 + *0x1ca0308: clear 0xffffffff, set 0xa50aa205 + *0x1ca030c: clear 0xffffffff, set 0x37233112 + *0x1ca0310: clear 0xffffffff, set 0x27bc0483 + *0x1ca0314: clear 0xffffffff, set 0x3000c38 + *0x1ca0318: clear 0xffffffff, set 0xc000000 + *0x1ca031c: clear 0xffffffff, set 0x300 + *0x1ca0320: clear 0xffffffff, set 0x31757500 + *0x1ca0324: clear 0xffffffff, set 0x88888888 + *0x1ca0328: clear 0xffffffff, set 0x88138888 + *0x1ca032c: clear 0xffffffff, set 0x88206464 + *0x1ca0330: clear 0xffffffff, set 0x88888888 + *0x1ca0334: clear 0xffffffff, set 0x880288 + *0x1ca0338: clear 0xffffffff, set 0x0 + *0x1ca033c: clear 0xffffffff, set 0x0 + *0x1ca0340: clear 0xffffffff, set 0x0 + *0x1ca0344: clear 0xffffffff, set 0x365 + *0x1ca0200: clear 0xff, set 0x45 + *0x1ca0048 = 0xf0004 + *0x1ca0010: clear 0x1, set 0x0 + *0x1ca0010: clear 0x1, set 0x1 +ret=64 +writeDcs: len=62 +ea 02 21 00 00 00 00 00 +00 00 00 00 00 02 46 02 +88 88 88 88 88 88 64 88 +13 57 13 88 88 88 88 88 +88 75 88 23 14 00 00 02 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 03 +0a a5 00 00 00 00 +channel=0, cmd=0x39, txlen=62 +channel=0, cmd=0x39, txlen=62 +packet: pktlen=68 +39 3e 00 1a ea 02 21 00 +00 00 00 00 00 00 00 00 +00 02 46 02 88 88 88 88 +88 88 64 88 13 57 13 88 +88 88 88 88 88 75 88 23 +14 00 00 02 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 03 0a a5 00 00 +00 00 24 1b + *0x1ca0200 = 0x6000200 + *0x1ca0300: clear 0xffffffff, set 0x1a003e39 + *0x1ca0304: clear 0xffffffff, set 0x2102ea + *0x1ca0308: clear 0xffffffff, set 0x0 + *0x1ca030c: clear 0xffffffff, set 0x0 + *0x1ca0310: clear 0xffffffff, set 0x2460200 + *0x1ca0314: clear 0xffffffff, set 0x88888888 + *0x1ca0318: clear 0xffffffff, set 0x88648888 + *0x1ca031c: clear 0xffffffff, set 0x88135713 + *0x1ca0320: clear 0xffffffff, set 0x88888888 + *0x1ca0324: clear 0xffffffff, set 0x23887588 + *0x1ca0328: clear 0xffffffff, set 0x2000014 + *0x1ca032c: clear 0xffffffff, set 0x0 + *0x1ca0330: clear 0xffffffff, set 0x0 + *0x1ca0334: clear 0xffffffff, set 0x0 + *0x1ca0338: clear 0xffffffff, set 0x3000000 + *0x1ca033c: clear 0xffffffff, set 0xa50a + *0x1ca0340: clear 0xffffffff, set 0x1b240000 + *0x1ca0200: clear 0xff, set 0x43 + *0x1ca0048 = 0xf0004 + *0x1ca0010: clear 0x1, set 0x0 + *0x1ca0010: clear 0x1, set 0x1 +ret=62 +writeDcs: len=35 +e0 00 09 0d 23 27 3c 41 +35 07 0d 0e 12 13 10 12 +12 18 00 09 0d 23 27 3c +41 35 07 0d 0e 12 13 10 +12 12 18 +channel=0, cmd=0x39, txlen=35 +channel=0, cmd=0x39, txlen=35 +packet: pktlen=41 +39 23 00 20 e0 00 09 0d +23 27 3c 41 35 07 0d 0e +12 13 10 12 12 18 00 09 +0d 23 27 3c 41 35 07 0d +0e 12 13 10 12 12 18 93 +bf + *0x1ca0200 = 0x6000200 + *0x1ca0300: clear 0xffffffff, set 0x20002339 + *0x1ca0304: clear 0xffffffff, set 0xd0900e0 + *0x1ca0308: clear 0xffffffff, set 0x413c2723 + *0x1ca030c: clear 0xffffffff, set 0xe0d0735 + *0x1ca0310: clear 0xffffffff, set 0x12101312 + *0x1ca0314: clear 0xffffffff, set 0x9001812 + *0x1ca0318: clear 0xffffffff, set 0x3c27230d + *0x1ca031c: clear 0xffffffff, set 0xd073541 + *0x1ca0320: clear 0xffffffff, set 0x1013120e + *0x1ca0324: clear 0xffffffff, set 0x93181212 + *0x1ca0328: clear 0xffffffff, set 0xbf + *0x1ca0200: clear 0xff, set 0x28 + *0x1ca0048 = 0xf0004 + *0x1ca0010: clear 0x1, set 0x0 + *0x1ca0010: clear 0x1, set 0x1 +ret=35 +writeDcs: len=1 +11 +channel=0, cmd=0x5, txlen=1 +channel=0, cmd=0x5, txlen=1 +packet: pktlen=4 +05 11 00 36 + *0x1ca0200 = 0x6000200 + *0x1ca0300: clear 0xffffffff, set 0x36001105 + *0x1ca0200: clear 0xff, set 0x3 + *0x1ca0048 = 0xf0004 + *0x1ca0010: clear 0x1, set 0x0 + *0x1ca0010: clear 0x1, set 0x1 +ret=1 + up_udelay 120000 +writeDcs: len=1 +29 +channel=0, cmd=0x5, txlen=1 +channel=0, cmd=0x5, txlen=1 +packet: pktlen=4 +05 29 00 1c + *0x1ca0200 = 0x6000200 + *0x1ca0300: clear 0xffffffff, set 0x1c002905 + *0x1ca0200: clear 0xff, set 0x3 + *0x1ca0048 = 0xf0004 + *0x1ca0010: clear 0x1, set 0x0 + *0x1ca0010: clear 0x1, set 0x1 +ret=1 +panel_init: end +Start HSC + *0x1ca0048 = 0xf02 +Commit + *0x1ca0010: clear 0x1, set 0x1 +Instruction Function Lane + *0x1ca0020: clear 0x10, set 0x0 + up_udelay 1000 +Start HSD + *0x1ca0048 = 0x63f07006 +Commit + *0x1ca0010: clear 0x1, set 0x1 +Testing Compose Short Packet (Without Parameter)... +channel=0, cmd=0x5, txlen=1 +Result: +05 11 00 36 +Testing Compose Short Packet (With Parameter)... +channel=0, cmd=0x15, txlen=2 +Result: +15 bc 4e 35 +Testing Compose Long Packet... +channel=0, cmd=0x39, txlen=64 +Result: +39 40 00 25 e9 82 10 06 +05 a2 0a a5 12 31 23 37 +83 04 bc 27 38 0c 00 03 +00 00 00 0c 00 03 00 00 +00 75 75 31 88 88 88 88 +88 88 13 88 64 64 20 88 +88 88 88 88 88 02 88 00 +00 00 00 00 00 00 00 00 +00 00 00 00 65 03