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https://github.com/lupyuen/pinephone-nuttx.git
synced 2025-01-12 20:58:34 +08:00
Adding annotations
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parent
153751dcac
commit
ff7cd79e79
2 changed files with 57 additions and 38 deletions
75
display.zig
75
display.zig
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@ -1134,8 +1134,9 @@ pub export fn enable_dsi_block() void {
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const DSI_SYNC_HSS_REG = DSI_BASE_ADDRESS + 0xb0;
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comptime{ assert(DSI_SYNC_HSS_REG == 0x1ca00b0); }
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comptime{ assert(0000 == 0000); }
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putreg32(0x12000021, DSI_SYNC_HSS_REG); // TODO: DMB
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const DSI_SYNC_HSS = 0x12000021;
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comptime{ assert(DSI_SYNC_HSS == 0x12000021); }
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putreg32(DSI_SYNC_HSS, DSI_SYNC_HSS_REG); // TODO: DMB
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// DSI_SYNC_HSE_REG: DSI Offset 0xb4 (A31 Page 850)
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// Set ECC (Bits 24 to 31) to 1
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@ -1146,8 +1147,9 @@ pub export fn enable_dsi_block() void {
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const DSI_SYNC_HSE_REG = DSI_BASE_ADDRESS + 0xb4;
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comptime{ assert(DSI_SYNC_HSE_REG == 0x1ca00b4); }
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comptime{ assert(0000 == 0000); }
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putreg32(0x1000031, DSI_SYNC_HSE_REG); // TODO: DMB
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const DSI_SYNC_HSE = 0x1000031;
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comptime{ assert(DSI_SYNC_HSE == 0x1000031); }
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putreg32(DSI_SYNC_HSE, DSI_SYNC_HSE_REG); // TODO: DMB
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// DSI_SYNC_VSS_REG: DSI Offset 0xb8 (A31 Page 851)
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// Set ECC (Bits 24 to 31) to 7
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@ -1158,8 +1160,9 @@ pub export fn enable_dsi_block() void {
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const DSI_SYNC_VSS_REG = DSI_BASE_ADDRESS + 0xb8;
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comptime{ assert(DSI_SYNC_VSS_REG == 0x1ca00b8); }
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comptime{ assert(0000 == 0000); }
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putreg32(0x7000001, DSI_SYNC_VSS_REG); // TODO: DMB
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const DSI_SYNC_VSS = 0x7000001;
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comptime{ assert(DSI_SYNC_VSS == 0x7000001); }
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putreg32(DSI_SYNC_VSS, DSI_SYNC_VSS_REG); // TODO: DMB
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// DSI_SYNC_VSE_REG: DSI Offset 0xbc (A31 Page 851)
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// Set ECC (Bits 24 to 31) to 0x14
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@ -1170,8 +1173,9 @@ pub export fn enable_dsi_block() void {
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const DSI_SYNC_VSE_REG = DSI_BASE_ADDRESS + 0xbc;
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comptime{ assert(DSI_SYNC_VSE_REG == 0x1ca00bc); }
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comptime{ assert(0000 == 0000); }
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putreg32(0x14000011, DSI_SYNC_VSE_REG); // TODO: DMB
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const DSI_SYNC_VSE = 0x14000011;
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comptime{ assert(DSI_SYNC_VSE == 0x14000011); }
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putreg32(DSI_SYNC_VSE, DSI_SYNC_VSE_REG); // TODO: DMB
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// Set Basic Size (Undocumented)
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// DSI_BASIC_SIZE0_REG: DSI Offset 0x18
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@ -1181,8 +1185,9 @@ pub export fn enable_dsi_block() void {
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const DSI_BASIC_SIZE0_REG = DSI_BASE_ADDRESS + 0x18;
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comptime{ assert(DSI_BASIC_SIZE0_REG == 0x1ca0018); }
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comptime{ assert(0000 == 0000); }
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putreg32(0x11000a, DSI_BASIC_SIZE0_REG); // TODO: DMB
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const DSI_BASIC_SIZE0 = 0x11000a;
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comptime{ assert(DSI_BASIC_SIZE0 == 0x11000a); }
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putreg32(DSI_BASIC_SIZE0, DSI_BASIC_SIZE0_REG); // TODO: DMB
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// DSI_BASIC_SIZE1_REG: DSI Offset 0x1c
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// Set Video_VT (Bits 16 to 28) to 1485
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@ -1190,8 +1195,9 @@ pub export fn enable_dsi_block() void {
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const DSI_BASIC_SIZE1_REG = DSI_BASE_ADDRESS + 0x1c;
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comptime{ assert(DSI_BASIC_SIZE1_REG == 0x1ca001c); }
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comptime{ assert(0000 == 0000); }
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putreg32(0x5cd05a0, DSI_BASIC_SIZE1_REG); // TODO: DMB
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const DSI_BASIC_SIZE1 = 0x5cd05a0;
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comptime{ assert(DSI_BASIC_SIZE1 == 0x5cd05a0); }
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putreg32(DSI_BASIC_SIZE1, DSI_BASIC_SIZE1_REG); // TODO: DMB
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// Set Horizontal Blanking
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// DSI_BLK_HSA0_REG: DSI Offset 0xc0 (A31 Page 852)
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@ -1200,8 +1206,9 @@ pub export fn enable_dsi_block() void {
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const DSI_BLK_HSA0_REG = DSI_BASE_ADDRESS + 0xc0;
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comptime{ assert(DSI_BLK_HSA0_REG == 0x1ca00c0); }
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comptime{ assert(0000 == 0000); }
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putreg32(0x9004a19, DSI_BLK_HSA0_REG); // TODO: DMB
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const DSI_BLK_HSA0 = 0x9004a19;
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comptime{ assert(DSI_BLK_HSA0 == 0x9004a19); }
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putreg32(DSI_BLK_HSA0, DSI_BLK_HSA0_REG); // TODO: DMB
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// DSI_BLK_HSA1_REG: DSI Offset 0xc4 (A31 Page 852)
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// Set HSA_PF (Bits 16 to 31) to 0x50b4
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@ -1209,23 +1216,28 @@ pub export fn enable_dsi_block() void {
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const DSI_BLK_HSA1_REG = DSI_BASE_ADDRESS + 0xc4;
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comptime{ assert(DSI_BLK_HSA1_REG == 0x1ca00c4); }
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comptime{ assert(0000 == 0000); }
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putreg32(0x50b40000, DSI_BLK_HSA1_REG); // TODO: DMB
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const DSI_BLK_HSA1 = 0x50b40000;
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comptime{ assert(DSI_BLK_HSA1 == 0x50b40000); }
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putreg32(DSI_BLK_HSA1, DSI_BLK_HSA1_REG); // TODO: DMB
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// DSI_BLK_HBP0_REG: DSI Offset 0xc8 (A31 Page 852)
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// Set HBP_PH (Bits 0 to 31) to 0x3500 5419
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const DSI_BLK_HBP0_REG = DSI_BASE_ADDRESS + 0xc8;
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comptime{ assert(DSI_BLK_HBP0_REG == 0x1ca00c8); }
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comptime{ assert(0000 == 0000); }
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putreg32(0x35005419, DSI_BLK_HBP0_REG); // TODO: DMB
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const DSI_BLK_HBP0 = 0x35005419;
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comptime{ assert(DSI_BLK_HBP0 == 0x35005419); }
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putreg32(DSI_BLK_HBP0, DSI_BLK_HBP0_REG); // TODO: DMB
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// DSI_BLK_HBP1_REG: DSI Offset 0xcc (A31 Page 852)
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// Set HBP_PF (Bits 16 to 31) to 0x757a
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// Set HBP_PD (Bits 0 to 7) to 0
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const DSI_BLK_HBP1_REG = DSI_BASE_ADDRESS + 0xcc;
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comptime{ assert(DSI_BLK_HBP1_REG == 0x1ca00cc); }
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putreg32(0x757a0000, DSI_BLK_HBP1_REG); // TODO: DMB
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const DSI_BLK_HBP1 = 0x757a0000;
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comptime{ assert(DSI_BLK_HBP1 == 0x757a0000); }
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putreg32(DSI_BLK_HBP1, DSI_BLK_HBP1_REG); // TODO: DMB
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// DSI_BLK_HFP0_REG: DSI Offset 0xd0 (A31 Page 852)
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// Set HFP_PH (Bits 0 to 31) to 0x900 4a19
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@ -1239,8 +1251,9 @@ pub export fn enable_dsi_block() void {
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const DSI_BLK_HFP1_REG = DSI_BASE_ADDRESS + 0xd4;
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comptime{ assert(DSI_BLK_HFP1_REG == 0x1ca00d4); }
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comptime{ assert(0000 == 0000); }
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putreg32(0x50b40000, DSI_BLK_HFP1_REG); // TODO: DMB
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const DSI_BLK_HFP1 = 0x50b40000;
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comptime{ assert(DSI_BLK_HFP1 == 0x50b40000); }
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putreg32(DSI_BLK_HFP1, DSI_BLK_HFP1_REG); // TODO: DMB
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// DSI_BLK_HBLK0_REG: DSI Offset 0xe0 (A31 Page 853)
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// Set HBLK_PH (Bits 0 to 31) to 0xc09 1a19
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@ -1254,8 +1267,9 @@ pub export fn enable_dsi_block() void {
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const DSI_BLK_HBLK1_REG = DSI_BASE_ADDRESS + 0xe4;
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comptime{ assert(DSI_BLK_HBLK1_REG == 0x1ca00e4); }
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comptime{ assert(0000 == 0000); }
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putreg32(0x72bd0000, DSI_BLK_HBLK1_REG); // TODO: DMB
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const DSI_BLK_HBLK1 = 0x72bd0000;
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comptime{ assert(DSI_BLK_HBLK1 == 0x72bd0000); }
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putreg32(DSI_BLK_HBLK1, DSI_BLK_HBLK1_REG); // TODO: DMB
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// Set Vertical Blanking
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// DSI_BLK_VBLK0_REG: DSI Offset 0xe8 (A31 Page 854)
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@ -1271,8 +1285,9 @@ pub export fn enable_dsi_block() void {
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const DSI_BLK_VBLK1_REG = DSI_BASE_ADDRESS + 0xec;
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comptime{ assert(DSI_BLK_VBLK1_REG == 0x1ca00ec); }
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comptime{ assert(0000 == 0000); }
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putreg32(0xffff0000, DSI_BLK_VBLK1_REG); // TODO: DMB
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const DSI_BLK_VBLK1 = 0xffff0000;
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comptime{ assert(DSI_BLK_VBLK1 == 0xffff0000); }
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putreg32(DSI_BLK_VBLK1, DSI_BLK_VBLK1_REG); // TODO: DMB
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}
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///////////////////////////////////////////////////////////////////////////////
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@ -1298,9 +1313,8 @@ pub export fn start_dsi() void {
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// Set Instru_En (Bit 0) to 1 (Enable DSI Processing from Instruction 0)
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debug("Commit", .{});
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comptime{ assert(DSI_BASIC_CTL0_REG == 0x1ca0010); }
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comptime{ assert(0000 == 0000); }
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modreg32(0x1, 0x1, DSI_BASIC_CTL0_REG); // TODO: DMB
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comptime{ assert(Instru_En == 0x1); }
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modreg32(Instru_En, Instru_En, DSI_BASIC_CTL0_REG); // TODO: DMB
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// Instruction Function Lane (Undocumented)
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// DSI_INST_FUNC_REG(0): DSI Offset 0x20 (DSI_INST_ID_LP11)
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@ -1325,9 +1339,8 @@ pub export fn start_dsi() void {
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// Set Instru_En (Bit 0) to 1 (Enable DSI Processing from Instruction 0)
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debug("Commit", .{});
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comptime{ assert(DSI_BASIC_CTL0_REG == 0x1ca0010); }
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comptime{ assert(0000 == 0000); }
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modreg32(0x1, 0x1, DSI_BASIC_CTL0_REG); // TODO: DMB
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comptime{ assert(Instru_En == 0x1); }
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modreg32(Instru_En, Instru_En, DSI_BASIC_CTL0_REG); // TODO: DMB
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}
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///////////////////////////////////////////////////////////////////////////////
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20
dphy.zig
20
dphy.zig
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@ -62,8 +62,9 @@ pub export fn dphy_enable() void {
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const MIPI_DSI_CLK_REG = CCU_BASE_ADDRESS + 0x168;
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comptime{ assert(MIPI_DSI_CLK_REG == 0x1c20168); }
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comptime{ assert(0000 == 0000); }
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putreg32(0x8203, MIPI_DSI_CLK_REG); // TODO: DMB
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const MIPI_DSI_CLK = 0x8203;
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comptime{ assert(MIPI_DSI_CLK == 0x8203); }
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putreg32(MIPI_DSI_CLK, MIPI_DSI_CLK_REG); // TODO: DMB
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// Power on DPHY Tx (Undocumented)
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// DPHY_TX_CTL_REG: DPHY Offset 0x04
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@ -152,7 +153,8 @@ pub export fn dphy_enable() void {
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// DPHY_ANA3_REG: DPHY Offset 0x58 (Enable VTTC, VTTD)
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// Set bits 0xf800 0000
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comptime{ assert(DPHY_ANA3_REG == 0x1ca1058); }
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modreg32(0xf8000000, 0xf8000000, DPHY_ANA3_REG); // TODO: DMB
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const EnableVTTC = 0xf8000000;
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modreg32(EnableVTTC, EnableVTTC, DPHY_ANA3_REG); // TODO: DMB
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// Wait 1 microsecond
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_ = c.usleep(1);
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@ -160,14 +162,16 @@ pub export fn dphy_enable() void {
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// DPHY_ANA3_REG: DPHY Offset 0x58 (Enable DIV)
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// Set bits 0x400 0000
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comptime{ assert(DPHY_ANA3_REG == 0x1ca1058); }
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modreg32(0x4000000, 0x4000000, DPHY_ANA3_REG); // TODO: DMB
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const EnableDIV = 0x4000000;
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modreg32(EnableDIV, EnableDIV, DPHY_ANA3_REG); // TODO: DMB
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// Wait 1 microsecond
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_ = c.usleep(1);
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// DPHY_ANA2_REG: DPHY Offset 0x54 (Enable CK_CPU)
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comptime{ assert(DPHY_ANA2_REG == 0x1ca1054); }
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modreg32(0x10, 0x10, DPHY_ANA2_REG); // TODO: DMB
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const EnableCKCPU = 0x10;
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modreg32(EnableCKCPU, EnableCKCPU, DPHY_ANA2_REG); // TODO: DMB
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// Set bits 0x10
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// Wait 1 microsecond
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@ -176,12 +180,14 @@ pub export fn dphy_enable() void {
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// DPHY_ANA1_REG: DPHY Offset 0x50 (VTT Mode)
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// Set bits 0x8000 0000
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comptime{ assert(DPHY_ANA1_REG == 0x1ca1050); }
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modreg32(0x80000000, 0x80000000, DPHY_ANA1_REG); // TODO: DMB
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const VTTMode = 0x80000000;
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modreg32(VTTMode, VTTMode, DPHY_ANA1_REG); // TODO: DMB
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// DPHY_ANA2_REG: DPHY Offset 0x54 (Enable P2S CPU)
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// Set bits 0xf00 0000
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comptime{ assert(DPHY_ANA2_REG == 0x1ca1054); }
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modreg32(0xf000000, 0xf000000, DPHY_ANA2_REG); // TODO: DMB
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const EnableP2SCPU = 0xf000000;
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modreg32(EnableP2SCPU, EnableP2SCPU, DPHY_ANA2_REG); // TODO: DMB
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}
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/// Modify the specified bits in a memory mapped register.
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