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cxd56xx improvements (#48)

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* arch: cxd56xx: Add size limitation for I2C SCU xfer

This is a fw restriction, unroll loop because it can be transfer
up to 16 bytes.

* arch: cxd56xx: Fix lack of leave_critical_section

add the missing leave_critical_section

* arch: cxd56xx: Remove unnecessary file

this header is duplicate and we can remove it

* arch: cxd56xx: Cosmetic change

remove space after function

* arch: cxd56xx: update topreg registers

the topreg registers are updated to match the cxd5602 HW

* arch: cxd56xx: Add voltage setting for low battery notification

Add voltage setting for low battery notification

* arch: cxd56xx: Improve perfomance of SD card

Improve a problem that the clock of SD Host Controller is lower than the
expected value in SDR25 transfer mode.

* arch: cxd56xx: Cosmetic changes

cleanup to comply with coding standard

* boards: cxd56xx: Cosmetic changes

updates to comply with coding standard

* boards: cxd56xx: Fix SD card cannot mount issue

SD card cannot mount when connecting and disconnecting three times
or more due to wrong state of parameter 'initialized'.

This change enables to skip swtching initialized state when mount
failed.
This commit is contained in:
Alin Jerpelea 2020-01-07 16:21:58 +02:00 committed by Alan Carvalho de Assis
parent c5090d38cc
commit 077ef70b0c
92 changed files with 685 additions and 746 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

6
arch/arm/include/cxd56xx/adc.h
View file

@ -33,8 +33,8 @@
*
****************************************************************************/
#ifndef __ARCH_ARM_INCLUDE_CXD56XX_CXD56_ADC_H
#define __ARCH_ARM_INCLUDE_CXD56XX_CXD56_ADC_H
#ifndef __ARCH_ARM_INCLUDE_CXD56XX_ADC_H
#define __ARCH_ARM_INCLUDE_CXD56XX_ADC_H
/****************************************************************************
* include files
@ -93,4 +93,4 @@
int cxd56_adcinitialize(void);
#endif /* __ARCH_ARM_INCLUDE_CXD56XX_CXD56_ADC_H */
#endif /* __ARCH_ARM_INCLUDE_CXD56XX_ADC_H */

6
arch/arm/include/cxd56xx/audio.h
View file

@ -35,8 +35,8 @@
/* audioutils Audio Utility */
#ifndef __ARCH_ARM_INCLUDE_CXD56XX_CXD56_AUDIO_H
#define __ARCH_ARM_INCLUDE_CXD56XX_CXD56_AUDIO_H
#ifndef __ARCH_ARM_INCLUDE_CXD56XX_AUDIO_H
#define __ARCH_ARM_INCLUDE_CXD56XX_AUDIO_H
/* API Documents creater with Doxgen */
@ -948,4 +948,4 @@ bool board_audio_tone_generator(bool en, int16_t vol, uint16_t freq);
} /* end of extern "C" */
#endif /* __cplusplus */
#endif /* __ARCH_ARM_INCLUDE_CXD56XX_CXD56_AUDIO_H */
#endif /* __ARCH_ARM_INCLUDE_CXD56XX_AUDIO_H */

2
arch/arm/include/cxd56xx/battery_ioctl.h
View file

@ -1,5 +1,5 @@
/****************************************************************************
* include/arch/chip/battery_ioctl.h
* arch/arm/include/cxd56xx/battery_ioctl.h
*
* Copyright 2018 Sony Semiconductor Solutions Corporation
*

2
arch/arm/include/cxd56xx/ge2d.h
View file

@ -1,5 +1,5 @@
/****************************************************************************
* arch/arm/include/cxd56xx/cxd56_ge2d.h
* arch/arm/include/cxd56xx/ge2d.h
*
* Copyright 2018 Sony Semiconductor Solutions Corporation
*

2
arch/arm/include/cxd56xx/geofence.h
View file

@ -230,4 +230,4 @@ struct cxd56_geofence_status_s
}
#endif
#endif /* __ARCH_ARM_INCLUDE_ARCH_CXD56XX_GEOFENCE_H */
#endif /* __ARCH_ARM_INCLUDE_CXD56XX_GEOFENCE_H */

2
arch/arm/include/cxd56xx/gnss.h
View file

@ -866,4 +866,4 @@ struct cxd56_gnss_get_var_ephemeris_s
}
#endif
#endif /* ARCH_ARM_INCLUDE_CXD56XX_GNSS_H */
#endif /* __ARCH_ARM_INCLUDE_CXD56XX_GNSS_H */

2
arch/arm/include/cxd56xx/gnss_type.h
View file

@ -707,4 +707,4 @@ struct cxd56_gnss_status_s
}
#endif /* __cplusplus */
#endif /* ARCH_ARM_INCLUDE_CXD56XX_GNSS_TYPE_H */
#endif /* __ARCH_ARM_INCLUDE_CXD56XX_GNSS_TYPE_H */

6
arch/arm/include/cxd56xx/uart0.h
View file

@ -1,5 +1,5 @@
/****************************************************************************
* arch/arm/include/cxd56xx/cxd56_uart0.h
* arch/arm/include/cxd56xx/uart0.h
*
* Copyright 2018 Sony Semiconductor Solutions Corporation
*
@ -33,8 +33,8 @@
*
****************************************************************************/
#ifndef __ARM_ARCH_INCLUDE_CXD56XX_CXD56_UART0_H
#define __ARM_ARCH_INCLUDE_CXD56XX_CXD56_UART0_H
#ifndef __ARM_ARCH_INCLUDE_CXD56XX_UART0_H
#define __ARM_ARCH_INCLUDE_CXD56XX_UART0_H
/****************************************************************************
* Public Types

2
arch/arm/src/cxd56xx/cxd56_cisif.c
View file

@ -359,7 +359,7 @@ static void cisif_ycc_nstorage_int(uint8_t code)
uint32_t size;
size = cisif_reg_read(CISIF_YCC_DSTRG_CONT);
g_ycc_notify_callback_func (0, size, g_storage_addr);
g_ycc_notify_callback_func(0, size, g_storage_addr);
cisif_reg_write(CISIF_YCC_DREAD_CONT, size);
}

1
arch/arm/src/cxd56xx/cxd56_cpufifo.c
View file

@ -182,6 +182,7 @@ int cxd56_cfpush(uint32_t data[2])
if (!sq_empty(&g_pushqueue))
{
ret = cpufifo_reserve(data);
leave_critical_section(flags);
return ret;
}

2
arch/arm/src/cxd56xx/cxd56_dmac.h
View file

@ -39,7 +39,7 @@
#include <stdint.h>
#include "hardware/cxd56_dmac_common.h"
#include "cxd56_dmac_common.h"
/****************************************************************************
* Pre-processor Definitions

53
arch/arm/src/cxd56xx/cxd56_i2c.c
View file

@ -738,40 +738,35 @@ static int cxd56_i2c_scurecv(int port, int addr, uint8_t *buf, ssize_t buflen)
{
return OK;
}
if (buflen > 16)
{
return -EINVAL;
}
rem = buflen;
while (rem)
len0 = rem > 8 ? 8 : rem;
rem -= len0;
len1 = rem > 8 ? 8 : rem;
rem -= len1;
inst[0] = SCU_INST_RECV(len0);
if (len1)
{
len0 = rem > 8 ? 8 : rem;
rem -= len0;
len1 = rem > 8 ? 8 : rem;
rem -= len1;
inst[1] = SCU_INST_RECV(len1);
instn = 2;
}
else
{
instn = 1;
}
inst[0] = SCU_INST_RECV(len0);
if (len1)
{
inst[1] = SCU_INST_RECV(len1);
instn = 2;
}
else
{
instn = 1;
}
inst[instn - 1] |= SCU_INST_LAST;
if (rem == 0)
{
inst[instn - 1] |= SCU_INST_LAST;
}
ret = scu_i2ctransfer(port, addr, inst, instn, buf, len0 + len1);
if (ret < 0)
{
syslog(LOG_ERR, "I2C receive failed. port %d addr %d\n",
port, addr);
break;
}
buf += len0 + len1;
ret = scu_i2ctransfer(port, addr, inst, instn, buf, buflen);
if (ret < 0)
{
syslog(LOG_ERR, "I2C receive failed. port %d addr %d\n",
port, addr);
}
return ret;

2
arch/arm/src/cxd56xx/cxd56_idle.c
View file

@ -1,5 +1,5 @@
/****************************************************************************
* arch/arm/src/cxd56/cxd56_idle.c
* arch/arm/src/cxd56xx/cxd56_idle.c
*
* Copyright 2018 Sony Semiconductor Solutions Corporation
*

2
arch/arm/src/cxd56xx/cxd56_irq.c
View file

@ -1,5 +1,5 @@
/****************************************************************************
* arch/arm/src/cxd56/cxd56_irq.c
* arch/arm/src/cxd56xx/cxd56_irq.c
*
* Copyright 2018 Sony Semiconductor Solutions Corporation
*

61
arch/arm/src/cxd56xx/cxd56_pmic.c
View file

@ -748,9 +748,66 @@ int cxd56_pmic_get_gauge(FAR struct pmic_gauge_s *gauge)
*
****************************************************************************/
int cxd56_pmic_getlowervol(FAR int *vol)
int cxd56_pmic_getlowervol(FAR int *voltage)
{
return PM_PmicControl(PMIC_CMD_GETVSYS, vol);
return PM_PmicControl(PMIC_CMD_GETVSYS, voltage);
}
/****************************************************************************
* Name: cxd56_pmic_setlowervol
*
* Description:
* Set lower limit of voltage for system to be running.
*
* Input Parameter:
* voltage - Lower limit voltage (mV)
*
* Returned Value:
* Return 0 on success. Otherwise, return a negated errno.
*
****************************************************************************/
int cxd56_pmic_setlowervol(int voltage)
{
return PM_PmicControl(PMIC_CMD_SETVSYS, (void *)voltage);
}
/****************************************************************************
* Name: cxd56_pmic_getnotifyvol
*
* Description:
* Get voltage for the low battery notification
*
* Input Parameter:
* voltage - Low battery voltage (mV)
*
* Returned Value:
* Return 0 on success. Otherwise, return a negated errno.
*
****************************************************************************/
int cxd56_pmic_getnotifyvol(FAR int *voltage)
{
return PM_PmicControl(PMIC_CMD_GETPREVSYS, voltage);
}
/****************************************************************************
* Name: cxd56_pmic_setnotifyvol
*
* Description:
* Set voltage for the low battery notification
*
* Input Parameter:
* voltage - Low battery voltage (mV)
*
* Returned Value:
* Return 0 on success. Otherwise, return a negated errno.
*
****************************************************************************/
int cxd56_pmic_setnotifyvol(int voltage)
{
return PM_PmicControl(PMIC_CMD_SETPREVSYS, (void *)voltage);
}
/****************************************************************************

50
arch/arm/src/cxd56xx/cxd56_pmic.h
View file

@ -457,7 +457,55 @@ int cxd56_pmic_get_gauge(FAR struct pmic_gauge_s *gauge);
*
****************************************************************************/
int cxd56_pmic_getlowervol(FAR int *vol);
int cxd56_pmic_getlowervol(FAR int *voltage);
/****************************************************************************
* Name: cxd56_pmic_setlowervol
*
* Description:
* Set lower limit of voltage for system to be running.
*
* Input Parameter:
* voltage - Lower limit voltage (mV)
*
* Returned Value:
* Return 0 on success. Otherwise, return a negated errno.
*
****************************************************************************/
int cxd56_pmic_setlowervol(int voltage);
/****************************************************************************
* Name: cxd56_pmic_getnotifyvol
*
* Description:
* Get voltage for the low battery notification
*
* Input Parameter:
* voltage - Low battery voltage (mV)
*
* Returned Value:
* Return 0 on success. Otherwise, return a negated errno.
*
****************************************************************************/
int cxd56_pmic_getnotifyvol(FAR int *voltage);
/****************************************************************************
* Name: cxd56_pmic_setnotifyvol
*
* Description:
* Set voltage for the low battery notification
*
* Input Parameter:
* voltage - Low battery voltage (mV)
*
* Returned Value:
* Return 0 on success. Otherwise, return a negated errno.
*
****************************************************************************/
int cxd56_pmic_setnotifyvol(int voltage);
/****************************************************************************
* Name: cxd56_pmic_getchargevol

7
arch/arm/src/cxd56xx/cxd56_sdhci.c
View file

@ -119,13 +119,8 @@
# define CONFIG_CXD56_SD1BIT_FREQ 20000000 /* 20MHz SD 1-bit, normal clocking */
#endif
#ifndef CONFIG_CXD56_SD4BIT_FREQ
# define CONFIG_CXD56_SD4BIT_FREQ 25000000 /* 25MHz SD 4-bit, normal clocking */
# define CONFIG_CXD56_SD4BIT_FREQ 50000000 /* SDR25 SD 4-bit, normal clocking */
#endif
#ifndef CONFIG_CXD56_HSSD4BIT_FREQ
# define CONFIG_CXD56_HSSD4BIT_FREQ 50000000 /* 50MHz SD 4-bit, highspeed clocking */
#endif
#define CXD56_SDIO_BASECLK_FREQ (cxd56_get_sdio_baseclock()*2)
/* Timing */

4
arch/arm/src/cxd56xx/cxd56_usbdev.h
View file

@ -36,8 +36,8 @@
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_CXD56XX_CXD56_USB_H
#define __ARCH_ARM_SRC_CXD56XX_CXD56_USB_H
#ifndef __ARCH_ARM_SRC_CXD56XX_CXD56_USBDEV_H
#define __ARCH_ARM_SRC_CXD56XX_CXD56_USBDEV_H
/****************************************************************************
* Included Files

6
arch/arm/src/cxd56xx/hardware/cxd5602_backupmem.h
View file

@ -36,8 +36,8 @@
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_CXD56XX_CHIP_CXD5602_BACKUPMEM_H
#define __ARCH_ARM_SRC_CXD56XX_CHIP_CXD5602_BACKUPMEM_H
#ifndef __ARCH_ARM_SRC_CXD56XX_HARDWARE_CXD5602_BACKUPMEM_H
#define __ARCH_ARM_SRC_CXD56XX_HARDWARE_CXD5602_BACKUPMEM_H
/********************************************************************************************
* Included Files
@ -84,4 +84,4 @@ typedef struct {
* Public Functions
********************************************************************************************/
#endif /* __ARCH_ARM_SRC_CXD56XX_CHIP_CXD5602_BACKUPMEM_H */
#endif /* __ARCH_ARM_SRC_CXD56XX_HARDWARE_CXD5602_BACKUPMEM_H */

6
arch/arm/src/cxd56xx/hardware/cxd5602_pinconfig.h
View file

@ -36,8 +36,8 @@
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_CXD56XX_CHIP_CXD5602_PINCONFIG_H
#define __ARCH_ARM_SRC_CXD56XX_CHIP_CXD5602_PINCONFIG_H
#ifndef __ARCH_ARM_SRC_CXD56XX_HARDWARE_CXD5602_PINCONFIG_H
#define __ARCH_ARM_SRC_CXD56XX_HARDWARE_CXD5602_PINCONFIG_H
/********************************************************************************************
* Included Files
@ -656,4 +656,4 @@
#endif /* CONFIG_CXD56_CUSTOM_PINCONFIG */
#endif /* __ARCH_ARM_SRC_CXD56XX_CHIP_CXD5602_PINCONFIG_H */
#endif /* __ARCH_ARM_SRC_CXD56XX_HARDWARE_CXD5602_PINCONFIG_H */

823
arch/arm/src/cxd56xx/hardware/cxd5602_topreg.h
View file

@ -36,8 +36,8 @@
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_CXD56XX_CHIP_CXD5602_TOPREG_H
#define __ARCH_ARM_SRC_CXD56XX_CHIP_CXD5602_TOPREG_H
#ifndef __ARCH_ARM_SRC_CXD56XX_HARDWARE_CXD5602_TOPREG_H
#define __ARCH_ARM_SRC_CXD56XX_HARDWARE_CXD5602_TOPREG_H
/********************************************************************************************
* Included Files
@ -49,460 +49,375 @@
* Pre-processor Definitions
********************************************************************************************/
#define CXD56_TOPREG_PWD_CTL (CXD56_TOPREG_BASE + 0x0)
#define CXD56_TOPREG_ANA_PW_CTL (CXD56_TOPREG_BASE + 0x4)
#define CXD56_TOPREG_ANA_EN_CTL (CXD56_TOPREG_BASE + 0x8)
#define CXD56_TOPREG_SYSCPU_RAMMODE_SEL (CXD56_TOPREG_BASE + 0x10)
#define CXD56_TOPREG_TOP_SCU_RAMMODE_SEL (CXD56_TOPREG_BASE + 0x18)
#define CXD56_TOPREG_HOSTIFC_RAMMODE_SEL (CXD56_TOPREG_BASE + 0x1c)
#define CXD56_TOPREG_PMU_FAST (CXD56_TOPREG_BASE + 0x20)
#define CXD56_TOPREG_PMU_PW_CTL (CXD56_TOPREG_BASE + 0x30)
#define CXD56_TOPREG_PMU_INT_STAT (CXD56_TOPREG_BASE + 0x40)
#define CXD56_TOPREG_PMU_RAW_INT_STAT (CXD56_TOPREG_BASE + 0x44)
#define CXD56_TOPREG_PMU_INT_CLR (CXD56_TOPREG_BASE + 0x48)
#define CXD56_TOPREG_PMU_INT_MASK (CXD56_TOPREG_BASE + 0x4c)
#define CXD56_TOPREG_PWD_RESET0 (CXD56_TOPREG_BASE + 0x60)
#define CXD56_TOPREG_PMU_DBG (CXD56_TOPREG_BASE + 0x70)
#define CXD56_TOPREG_PMU_TIMEOUT_CTL0 (CXD56_TOPREG_BASE + 0x74)
#define CXD56_TOPREG_PMU_TIMEOUT_CTL1 (CXD56_TOPREG_BASE + 0x78)
#define CXD56_TOPREG_PMU_TIMEOUT_CTL2 (CXD56_TOPREG_BASE + 0x7c)
#define CXD56_TOPREG_PMU_FSM (CXD56_TOPREG_BASE + 0x80)
#define CXD56_TOPREG_PMU_PW_STAT (CXD56_TOPREG_BASE + 0x84)
#define CXD56_TOPREG_PMU_WAIT0 (CXD56_TOPREG_BASE + 0x88)
#define CXD56_TOPREG_PMU_WAIT1 (CXD56_TOPREG_BASE + 0x8c)
#define CXD56_TOPREG_PMU_WAIT2 (CXD56_TOPREG_BASE + 0x90)
#define CXD56_TOPREG_PMU_WAIT3 (CXD56_TOPREG_BASE + 0x94)
#define CXD56_TOPREG_PMU_WAIT4 (CXD56_TOPREG_BASE + 0x98)
#define CXD56_TOPREG_PMU_WAIT5 (CXD56_TOPREG_BASE + 0x9c)
#define CXD56_TOPREG_PMU_WAIT6 (CXD56_TOPREG_BASE + 0xa0)
#define CXD56_TOPREG_PMU_WAIT7 (CXD56_TOPREG_BASE + 0xa4)
#define CXD56_TOPREG_PMU_WAIT8 (CXD56_TOPREG_BASE + 0xa8)
#define CXD56_TOPREG_PMU_WAIT9 (CXD56_TOPREG_BASE + 0xac)
#define CXD56_TOPREG_PMU_DBG_INITEN (CXD56_TOPREG_BASE + 0xb0)
#define CXD56_TOPREG_PMU_DBG_ON_ORDER0 (CXD56_TOPREG_BASE + 0xb4)
#define CXD56_TOPREG_PMU_DBG_ON_ORDER1 (CXD56_TOPREG_BASE + 0xb8)
#define CXD56_TOPREG_PMU_DBG_ON_ORDER2 (CXD56_TOPREG_BASE + 0xbc)
#define CXD56_TOPREG_PMU_DBG_ON_ORDER3 (CXD56_TOPREG_BASE + 0xc0)
#define CXD56_TOPREG_PMU_DBG_ON_ORDER4 (CXD56_TOPREG_BASE + 0xc4)
#define CXD56_TOPREG_PMU_DBG_ON_ORDER5 (CXD56_TOPREG_BASE + 0xc8)
#define CXD56_TOPREG_PMU_DBG_ON_ORDER6 (CXD56_TOPREG_BASE + 0xcc)
#define CXD56_TOPREG_PMU_DBG_ON_ORDER7 (CXD56_TOPREG_BASE + 0xd0)
#define CXD56_TOPREG_PMU_DBG_OFF_ORDER0 (CXD56_TOPREG_BASE + 0xd4)
#define CXD56_TOPREG_PMU_DBG_OFF_ORDER1 (CXD56_TOPREG_BASE + 0xd8)
#define CXD56_TOPREG_PMU_DBG_OFF_ORDER2 (CXD56_TOPREG_BASE + 0xdc)
#define CXD56_TOPREG_PMU_DBG_OFF_ORDER3 (CXD56_TOPREG_BASE + 0xe0)
#define CXD56_TOPREG_PMU_DBG_OFF_ORDER4 (CXD56_TOPREG_BASE + 0xe4)
#define CXD56_TOPREG_PMU_DBG_OFF_ORDER5 (CXD56_TOPREG_BASE + 0xe8)
#define CXD56_TOPREG_PMU_DBG_OFF_ORDER6 (CXD56_TOPREG_BASE + 0xec)
#define CXD56_TOPREG_PMU_DBG_OFF_ORDER7 (CXD56_TOPREG_BASE + 0xf0)
#define CXD56_TOPREG_PMU_DBG_LUMPEN (CXD56_TOPREG_BASE + 0xf4)
#define CXD56_TOPREG_PMU_DBG_ADD (CXD56_TOPREG_BASE + 0xfc)
#define CXD56_TOPREG_PMU_DBG_ADD_WAIT0 (CXD56_TOPREG_BASE + 0x100)
#define CXD56_TOPREG_PMU_DBG_ADD_WAIT1 (CXD56_TOPREG_BASE + 0x104)
#define CXD56_TOPREG_PWD_STAT (CXD56_TOPREG_BASE + 0x200)
#define CXD56_TOPREG_PWD_PGACK_STAT (CXD56_TOPREG_BASE + 0x204)
#define CXD56_TOPREG_ANA_PW_STAT (CXD56_TOPREG_BASE + 0x208)
#define CXD56_TOPREG_SYSCPU_RAMMODE_STAT (CXD56_TOPREG_BASE + 0x20c)
#define CXD56_TOPREG_TOP_SCU_RAMMODE_STAT (CXD56_TOPREG_BASE + 0x214)
#define CXD56_TOPREG_HOSTIFC_RAMMODE_STAT (CXD56_TOPREG_BASE + 0x218)
#define CXD56_TOPREG_PMU_HW_STAT (CXD56_TOPREG_BASE + 0x21c)
#define CXD56_TOPREG_YOBI2_0 (CXD56_TOPREG_BASE + 0x230)
#define CXD56_TOPREG_ANA_PW_CTL_SEL_WAKE (CXD56_TOPREG_BASE + 0x400)
#define CXD56_TOPREG_SYSCPU_RAMMODE_SEL_WAKE (CXD56_TOPREG_BASE + 0x404)
#define CXD56_TOPREG_TOP_SCU_RAMMODE_SEL_WAKE (CXD56_TOPREG_BASE + 0x410)
#define CXD56_TOPREG_CLSELDIV_WAKE (CXD56_TOPREG_BASE + 0x414)
#define CXD56_TOPREG_CKDIV_CPU_DSP_BUS_WAKE (CXD56_TOPREG_BASE + 0x418)
#define CXD56_TOPREG_CKSEL_ROOT_WAKE (CXD56_TOPREG_BASE + 0x41c)
#define CXD56_TOPREG_PMIC_SLEEP_I2C0 (CXD56_TOPREG_BASE + 0x420)
#define CXD56_TOPREG_PMIC_SLEEP_I2C1 (CXD56_TOPREG_BASE + 0x424)
#define CXD56_TOPREG_PMIC_SLEEP_I2C2 (CXD56_TOPREG_BASE + 0x428)
#define CXD56_TOPREG_PMIC_SLEEP_I2C3 (CXD56_TOPREG_BASE + 0x42c)
#define CXD56_TOPREG_PMIC_WAKE_I2C0 (CXD56_TOPREG_BASE + 0x430)
#define CXD56_TOPREG_PMIC_WAKE_I2C1 (CXD56_TOPREG_BASE + 0x434)
#define CXD56_TOPREG_PMIC_WAKE_I2C2 (CXD56_TOPREG_BASE + 0x438)
#define CXD56_TOPREG_PMIC_WAKE_I2C3 (CXD56_TOPREG_BASE + 0x43c)
#define CXD56_TOPREG_PMIC_UNEXP_I2C0 (CXD56_TOPREG_BASE + 0x440)
#define CXD56_TOPREG_PMIC_UNEXP_I2C1 (CXD56_TOPREG_BASE + 0x444)
#define CXD56_TOPREG_PMIC_UNEXP_I2C2 (CXD56_TOPREG_BASE + 0x448)
#define CXD56_TOPREG_PMIC_UNEXP_I2C3 (CXD56_TOPREG_BASE + 0x44c)
#define CXD56_TOPREG_PMIC_UNEXP_I2C (CXD56_TOPREG_BASE + 0x450)
#define CXD56_TOPREG_PMU_WAKE_TRIG_EN0 (CXD56_TOPREG_BASE + 0x454)
#define CXD56_TOPREG_PMU_WAKE_TRIG_EN1 (CXD56_TOPREG_BASE + 0x458)
#define CXD56_TOPREG_PMU_WAKE_TRIG_NEGEN0 (CXD56_TOPREG_BASE + 0x45c)
#define CXD56_TOPREG_PMU_WAKE_TRIG_NEGEN1 (CXD56_TOPREG_BASE + 0x460)
#define CXD56_TOPREG_PMU_WAKE_TRIG_NOISECUTEN0 (CXD56_TOPREG_BASE + 0x464)
#define CXD56_TOPREG_PMU_WAKE_TRIG_CPUINTSEL0 (CXD56_TOPREG_BASE + 0x468)
#define CXD56_TOPREG_PMU_WAKE_TRIG_CPUINTSEL1 (CXD56_TOPREG_BASE + 0x46c)
#define CXD56_TOPREG_PMU_WAKE_TRIG_CPUINTSEL2 (CXD56_TOPREG_BASE + 0x470)
#define CXD56_TOPREG_PMU_WAKE_TRIG_INTDET0 (CXD56_TOPREG_BASE + 0x474)
#define CXD56_TOPREG_PMU_WAKE_TRIG_INTDET1 (CXD56_TOPREG_BASE + 0x478)
#define CXD56_TOPREG_PMU_WAKE_TRIG_INTDET2 (CXD56_TOPREG_BASE + 0x47c)
#define CXD56_TOPREG_PMU_WAKE_PMIC_I2C (CXD56_TOPREG_BASE + 0x480)
#define CXD56_TOPREG_BOOT_CAUSE (CXD56_TOPREG_BASE + 0x484)
#define CXD56_TOPREG_PMU_CORE_CKEN (CXD56_TOPREG_BASE + 0x4c0)
#define CXD56_TOPREG_CKSEL_ROOT (CXD56_TOPREG_BASE + 0x4c4)
#define CXD56_TOPREG_CKSEL_PMU (CXD56_TOPREG_BASE + 0x4c8)
#define CXD56_TOPREG_CKSEL_SYSIOP (CXD56_TOPREG_BASE + 0x4cc)
#define CXD56_TOPREG_CKSEL_SYSIOP_SUB (CXD56_TOPREG_BASE + 0x4d0)
#define CXD56_TOPREG_CKSEL_SCU (CXD56_TOPREG_BASE + 0x4d4)
#define CXD56_TOPREG_CKDIV_CPU_DSP_BUS (CXD56_TOPREG_BASE + 0x4d8)
#define CXD56_TOPREG_CKDIV_COM (CXD56_TOPREG_BASE + 0x4dc)
#define CXD56_TOPREG_CKDIV_HOSTIFC (CXD56_TOPREG_BASE + 0x4e0)
#define CXD56_TOPREG_CKDIV_SCU (CXD56_TOPREG_BASE + 0x4e4)
#define CXD56_TOPREG_CKDIV_PMU (CXD56_TOPREG_BASE + 0x4e8)
#define CXD56_TOPREG_CRG_INT_CLR0 (CXD56_TOPREG_BASE + 0x4ec)
#define CXD56_TOPREG_CRG_INT_MASK0 (CXD56_TOPREG_BASE + 0x4f0)
#define CXD56_TOPREG_CRG_INT_STAT_MSK0 (CXD56_TOPREG_BASE + 0x4f4)
#define CXD56_TOPREG_CRG_INT_STAT_RAW0 (CXD56_TOPREG_BASE + 0x4f8)
#define CXD56_TOPREG_CRG_INT_CLR1 (CXD56_TOPREG_BASE + 0x4fc)
#define CXD56_TOPREG_CRG_INT_MASK1 (CXD56_TOPREG_BASE + 0x500)
#define CXD56_TOPREG_CRG_INT_STAT_MSK1 (CXD56_TOPREG_BASE + 0x504)
#define CXD56_TOPREG_CRG_INT_STAT_RAW1 (CXD56_TOPREG_BASE + 0x508)
#define CXD56_TOPREG_CPU_GATECLK (CXD56_TOPREG_BASE + 0x50c)
#define CXD56_TOPREG_USBPHY_CKEN (CXD56_TOPREG_BASE + 0x510)
#define CXD56_TOPREG_CRG_MON (CXD56_TOPREG_BASE + 0x514)
#define CXD56_TOPREG_GEAR_STAT (CXD56_TOPREG_BASE + 0x518)
#define CXD56_TOPREG_XOSC_CTRL (CXD56_TOPREG_BASE + 0x580)
#define CXD56_TOPREG_XOSC_CTRL2 (CXD56_TOPREG_BASE + 0x584)
#define CXD56_TOPREG_SYS_PLL_CTRL1 (CXD56_TOPREG_BASE + 0x588)
#define CXD56_TOPREG_SYS_PLL_CTRL2 (CXD56_TOPREG_BASE + 0x58c)
#define CXD56_TOPREG_RCOSC_CTRL1 (CXD56_TOPREG_BASE + 0x590)
#define CXD56_TOPREG_RCOSC_CTRL2 (CXD56_TOPREG_BASE + 0x594)
#define CXD56_TOPREG_RF_GPMBI_EN (CXD56_TOPREG_BASE + 0x598)
#define CXD56_TOPREG_BUSPROT_SDMAC (CXD56_TOPREG_BASE + 0x5c0)
#define CXD56_TOPREG_BUSPROT_HDMAC (CXD56_TOPREG_BASE + 0x5c4)
#define CXD56_TOPREG_BUSPROT_SYDMAC (CXD56_TOPREG_BASE + 0x5c8)
#define CXD56_TOPREG_BUSPROT_SYSUBDMAC (CXD56_TOPREG_BASE + 0x5cc)
#define CXD56_TOPREG_BUSPROT_SAKE (CXD56_TOPREG_BASE + 0x5d0)
#define CXD56_TOPREG_BUSPROT_KAKI (CXD56_TOPREG_BASE + 0x5d4)
#define CXD56_TOPREG_BUSPROT_BKUPSRAM (CXD56_TOPREG_BASE + 0x5d8)
#define CXD56_TOPREG_BUSPROT_SPIFLAIF (CXD56_TOPREG_BASE + 0x5dc)
#define CXD56_TOPREG_BUSPROT_TOPREG_0 (CXD56_TOPREG_BASE + 0x5e0)
#define CXD56_TOPREG_BUSPROT_TOPREG_1 (CXD56_TOPREG_BASE + 0x5e4)
#define CXD56_TOPREG_BUSPROT_TOPREG_2 (CXD56_TOPREG_BASE + 0x5e8)
#define CXD56_TOPREG_BUSPROT_TOPREG_3 (CXD56_TOPREG_BASE + 0x5ec)
#define CXD56_TOPREG_BUSPROT_TOPREG_4 (CXD56_TOPREG_BASE + 0x5f0)
#define CXD56_TOPREG_GPIO_PROT_0 (CXD56_TOPREG_BASE + 0x5f4)
#define CXD56_TOPREG_GPIO_PROT_1 (CXD56_TOPREG_BASE + 0x5f8)
#define CXD56_TOPREG_GPIO_PROT_2 (CXD56_TOPREG_BASE + 0x5fc)
#define CXD56_TOPREG_GPIO_PROT_3 (CXD56_TOPREG_BASE + 0x600)
#define CXD56_TOPREG_BUSPROT_CHECKER (CXD56_TOPREG_BASE + 0x610)
#define CXD56_TOPREG_WDT_SRST_EN (CXD56_TOPREG_BASE + 0x640)
#define CXD56_TOPREG_FORCE_CKEN (CXD56_TOPREG_BASE + 0x644)
#define CXD56_TOPREG_SDEBUG_PASS_BYPASS (CXD56_TOPREG_BASE + 0x648)
#define CXD56_TOPREG_SDEBUG_CTRL (CXD56_TOPREG_BASE + 0x64c)
#define CXD56_TOPREG_DBG_HOSTIF_SEL (CXD56_TOPREG_BASE + 0x650)
#define CXD56_TOPREG_WDT_MASK (CXD56_TOPREG_BASE + 0x654)
#define CXD56_TOPREG_CKGATE_CTL (CXD56_TOPREG_BASE + 0x660)
#define CXD56_TOPREG_M0_BOOT_MODE (CXD56_TOPREG_BASE + 0x680)
#define CXD56_TOPREG_M0_BOOT_MODE_EN (CXD56_TOPREG_BASE + 0x684)
#define CXD56_TOPREG_M0_BOOT_ENTRY_POINT (CXD56_TOPREG_BASE + 0x688)
#define CXD56_TOPREG_M0_BOOT_MODE_EXT (CXD56_TOPREG_BASE + 0x690)
#define CXD56_TOPREG_M0_BOOT_REC (CXD56_TOPREG_BASE + 0x694)
#define CXD56_TOPREG_I2CRPT_SADR (CXD56_TOPREG_BASE + 0x6c0)
#define CXD56_TOPREG_I2CRPT_REP (CXD56_TOPREG_BASE + 0x6c4)
#define CXD56_TOPREG_PMIC_I2C (CXD56_TOPREG_BASE + 0x6d0)
#define CXD56_TOPREG_RAMMODE (CXD56_TOPREG_BASE + 0x6e4)
#define CXD56_TOPREG_SWRESET_BUS (CXD56_TOPREG_BASE + 0x700)
#define CXD56_TOPREG_SWRESET_SCU (CXD56_TOPREG_BASE + 0x704)
#define CXD56_TOPREG_BUSROM_CKEN (CXD56_TOPREG_BASE + 0x710)
#define CXD56_TOPREG_SYSIOP_CKEN (CXD56_TOPREG_BASE + 0x714)
#define CXD56_TOPREG_SCU_CKEN (CXD56_TOPREG_BASE + 0x71c)
#define CXD56_TOPREG_RTC0_CTL (CXD56_TOPREG_BASE + 0x730)
#define CXD56_TOPREG_FUSERDCFG0 (CXD56_TOPREG_BASE + 0x740)
#define CXD56_TOPREG_FUSERDCFG1 (CXD56_TOPREG_BASE + 0x744)
#define CXD56_TOPREG_FUSERDCFG2 (CXD56_TOPREG_BASE + 0x748)
#define CXD56_TOPREG_VID0 (CXD56_TOPREG_BASE + 0x750)
#define CXD56_TOPREG_VID1 (CXD56_TOPREG_BASE + 0x754)
#define CXD56_TOPREG_M0_BOOT_FLASH_DIS (CXD56_TOPREG_BASE + 0x758)
#define CXD56_TOPREG_LDOADJ0 (CXD56_TOPREG_BASE + 0x760)
#define CXD56_TOPREG_LDOADJ1 (CXD56_TOPREG_BASE + 0x764)
#define CXD56_TOPREG_FQFIX_CTL0 (CXD56_TOPREG_BASE + 0x770)
#define CXD56_TOPREG_FQFIX_AUTO (CXD56_TOPREG_BASE + 0x774)
#define CXD56_TOPREG_FQFIX_SINGLE (CXD56_TOPREG_BASE + 0x778)
#define CXD56_TOPREG_FQFIX_STATUS (CXD56_TOPREG_BASE + 0x77c)
#define CXD56_TOPREG_SYSTEM_CONFIG (CXD56_TOPREG_BASE + 0x790)
#define CXD56_TOPREG_MON_SEL (CXD56_TOPREG_BASE + 0x7a0)
#define CXD56_TOPREG_IOCSYS_MONSEL0 (CXD56_TOPREG_BASE + 0x7a4)
#define CXD56_TOPREG_IOCSYS_MONSEL1 (CXD56_TOPREG_BASE + 0x7a8)
#define CXD56_TOPREG_IOCSYS_INTSEL0 (CXD56_TOPREG_BASE + 0x7b0)
#define CXD56_TOPREG_IOCSYS_INTSEL1 (CXD56_TOPREG_BASE + 0x7b4)
#define CXD56_TOPREG_IOCSYS_IOMD0 (CXD56_TOPREG_BASE + 0x7c0)
#define CXD56_TOPREG_IOCSYS_IOMD1 (CXD56_TOPREG_BASE + 0x7c4)
#define CXD56_TOPREG_IOOEN_SYS (CXD56_TOPREG_BASE + 0x7e0)
#define CXD56_TOPREG_IO_RTC_CLK_IN (CXD56_TOPREG_BASE + 0x800)
#define CXD56_TOPREG_IO_I2C4_BCK (CXD56_TOPREG_BASE + 0x804)
#define CXD56_TOPREG_IO_I2C4_BDT (CXD56_TOPREG_BASE + 0x808)
#define CXD56_TOPREG_IO_PMIC_INT (CXD56_TOPREG_BASE + 0x80c)
#define CXD56_TOPREG_IO_RTC_IRQ_OUT (CXD56_TOPREG_BASE + 0x810)
#define CXD56_TOPREG_IO_AP_CLK (CXD56_TOPREG_BASE + 0x814)
#define CXD56_TOPREG_IO_GNSS_1PPS_OUT (CXD56_TOPREG_BASE + 0x818)
#define CXD56_TOPREG_IO_SPI0_CS_X (CXD56_TOPREG_BASE + 0x844)
#define CXD56_TOPREG_IO_SPI0_SCK (CXD56_TOPREG_BASE + 0x848)
#define CXD56_TOPREG_IO_SPI0_MOSI (CXD56_TOPREG_BASE + 0x84c)
#define CXD56_TOPREG_IO_SPI0_MISO (CXD56_TOPREG_BASE + 0x850)
#define CXD56_TOPREG_IO_SPI1_CS_X (CXD56_TOPREG_BASE + 0x854)
#define CXD56_TOPREG_IO_SPI1_SCK (CXD56_TOPREG_BASE + 0x858)
#define CXD56_TOPREG_IO_SPI1_IO0 (CXD56_TOPREG_BASE + 0x85c)
#define CXD56_TOPREG_IO_SPI1_IO1 (CXD56_TOPREG_BASE + 0x860)
#define CXD56_TOPREG_IO_SPI1_IO2 (CXD56_TOPREG_BASE + 0x864)
#define CXD56_TOPREG_IO_SPI1_IO3 (CXD56_TOPREG_BASE + 0x868)
#define CXD56_TOPREG_IO_SPI2_CS_X (CXD56_TOPREG_BASE + 0x86c)
#define CXD56_TOPREG_IO_SPI2_SCK (CXD56_TOPREG_BASE + 0x870)
#define CXD56_TOPREG_IO_SPI2_MOSI (CXD56_TOPREG_BASE + 0x874)
#define CXD56_TOPREG_IO_SPI2_MISO (CXD56_TOPREG_BASE + 0x878)
#define CXD56_TOPREG_IO_HIF_IRQ_OUT (CXD56_TOPREG_BASE + 0x87c)
#define CXD56_TOPREG_IO_HIF_GPIO0 (CXD56_TOPREG_BASE + 0x880)
#define CXD56_TOPREG_IO_SEN_IRQ_IN (CXD56_TOPREG_BASE + 0x894)
#define CXD56_TOPREG_IO_SPI3_CS0_X (CXD56_TOPREG_BASE + 0x898)
#define CXD56_TOPREG_IO_SPI3_CS1_X (CXD56_TOPREG_BASE + 0x89c)
#define CXD56_TOPREG_IO_SPI3_CS2_X (CXD56_TOPREG_BASE + 0x8a0)
#define CXD56_TOPREG_IO_SPI3_SCK (CXD56_TOPREG_BASE + 0x8a4)
#define CXD56_TOPREG_IO_SPI3_MOSI (CXD56_TOPREG_BASE + 0x8a8)
#define CXD56_TOPREG_IO_SPI3_MISO (CXD56_TOPREG_BASE + 0x8ac)
#define CXD56_TOPREG_IO_I2C0_BCK (CXD56_TOPREG_BASE + 0x8b0)
#define CXD56_TOPREG_IO_I2C0_BDT (CXD56_TOPREG_BASE + 0x8b4)
#define CXD56_TOPREG_IO_PWM0 (CXD56_TOPREG_BASE + 0x8b8)
#define CXD56_TOPREG_IO_PWM1 (CXD56_TOPREG_BASE + 0x8bc)
#define CXD56_TOPREG_IO_PWM2 (CXD56_TOPREG_BASE + 0x8c0)
#define CXD56_TOPREG_IO_PWM3 (CXD56_TOPREG_BASE + 0x8c4)
#define CXD56_TOPREG_IO_DBG_SWOCLK (CXD56_TOPREG_BASE + 0x8d4)
#define CXD56_TOPREG_IO_DBG_SWO (CXD56_TOPREG_BASE + 0x8d8)
#define CXD56_TOPREG_IO_IS_CLK (CXD56_TOPREG_BASE + 0x8e0)
#define CXD56_TOPREG_IO_IS_VSYNC (CXD56_TOPREG_BASE + 0x8e4)
#define CXD56_TOPREG_IO_IS_HSYNC (CXD56_TOPREG_BASE + 0x8e8)
#define CXD56_TOPREG_IO_IS_DATA0 (CXD56_TOPREG_BASE + 0x8ec)
#define CXD56_TOPREG_IO_IS_DATA1 (CXD56_TOPREG_BASE + 0x8f0)
#define CXD56_TOPREG_IO_IS_DATA2 (CXD56_TOPREG_BASE + 0x8f4)
#define CXD56_TOPREG_IO_IS_DATA3 (CXD56_TOPREG_BASE + 0x8f8)
#define CXD56_TOPREG_IO_IS_DATA4 (CXD56_TOPREG_BASE + 0x8fc)
#define CXD56_TOPREG_IO_IS_DATA5 (CXD56_TOPREG_BASE + 0x900)
#define CXD56_TOPREG_IO_IS_DATA6 (CXD56_TOPREG_BASE + 0x904)
#define CXD56_TOPREG_IO_IS_DATA7 (CXD56_TOPREG_BASE + 0x908)
#define CXD56_TOPREG_IO_UART2_TXD (CXD56_TOPREG_BASE + 0x90c)
#define CXD56_TOPREG_IO_UART2_RXD (CXD56_TOPREG_BASE + 0x910)
#define CXD56_TOPREG_IO_UART2_CTS (CXD56_TOPREG_BASE + 0x914)
#define CXD56_TOPREG_IO_UART2_RTS (CXD56_TOPREG_BASE + 0x918)
#define CXD56_TOPREG_IO_SPI4_CS_X (CXD56_TOPREG_BASE + 0x91c)
#define CXD56_TOPREG_IO_SPI4_SCK (CXD56_TOPREG_BASE + 0x920)
#define CXD56_TOPREG_IO_SPI4_MOSI (CXD56_TOPREG_BASE + 0x924)
#define CXD56_TOPREG_IO_SPI4_MISO (CXD56_TOPREG_BASE + 0x928)
#define CXD56_TOPREG_IO_EMMC_CLK (CXD56_TOPREG_BASE + 0x92c)
#define CXD56_TOPREG_IO_EMMC_CMD (CXD56_TOPREG_BASE + 0x930)
#define CXD56_TOPREG_IO_EMMC_DATA0 (CXD56_TOPREG_BASE + 0x934)
#define CXD56_TOPREG_IO_EMMC_DATA1 (CXD56_TOPREG_BASE + 0x938)
#define CXD56_TOPREG_IO_EMMC_DATA2 (CXD56_TOPREG_BASE + 0x93c)
#define CXD56_TOPREG_IO_EMMC_DATA3 (CXD56_TOPREG_BASE + 0x940)
#define CXD56_TOPREG_IO_SDIO_CLK (CXD56_TOPREG_BASE + 0x944)
#define CXD56_TOPREG_IO_SDIO_CMD (CXD56_TOPREG_BASE + 0x948)
#define CXD56_TOPREG_IO_SDIO_DATA0 (CXD56_TOPREG_BASE + 0x94c)
#define CXD56_TOPREG_IO_SDIO_DATA1 (CXD56_TOPREG_BASE + 0x950)
#define CXD56_TOPREG_IO_SDIO_DATA2 (CXD56_TOPREG_BASE + 0x954)
#define CXD56_TOPREG_IO_SDIO_DATA3 (CXD56_TOPREG_BASE + 0x958)
#define CXD56_TOPREG_IO_SDIO_CD (CXD56_TOPREG_BASE + 0x95c)
#define CXD56_TOPREG_IO_SDIO_WP (CXD56_TOPREG_BASE + 0x960)
#define CXD56_TOPREG_IO_SDIO_CMDDIR (CXD56_TOPREG_BASE + 0x964)
#define CXD56_TOPREG_IO_SDIO_DIR0 (CXD56_TOPREG_BASE + 0x968)
#define CXD56_TOPREG_IO_SDIO_DIR1_3 (CXD56_TOPREG_BASE + 0x96c)
#define CXD56_TOPREG_IO_SDIO_CLKI (CXD56_TOPREG_BASE + 0x970)
#define CXD56_TOPREG_IO_I2S0_BCK (CXD56_TOPREG_BASE + 0x974)
#define CXD56_TOPREG_IO_I2S0_LRCK (CXD56_TOPREG_BASE + 0x978)
#define CXD56_TOPREG_IO_I2S0_DATA_IN (CXD56_TOPREG_BASE + 0x97c)
#define CXD56_TOPREG_IO_I2S0_DATA_OUT (CXD56_TOPREG_BASE + 0x980)
#define CXD56_TOPREG_IO_I2S1_BCK (CXD56_TOPREG_BASE + 0x984)
#define CXD56_TOPREG_IO_I2S1_LRCK (CXD56_TOPREG_BASE + 0x988)
#define CXD56_TOPREG_IO_I2S1_DATA_IN (CXD56_TOPREG_BASE + 0x98c)
#define CXD56_TOPREG_IO_I2S1_DATA_OUT (CXD56_TOPREG_BASE + 0x990)
#define CXD56_TOPREG_IO_MCLK (CXD56_TOPREG_BASE + 0x994)
#define CXD56_TOPREG_IO_PDM_CLK (CXD56_TOPREG_BASE + 0x998)
#define CXD56_TOPREG_IO_PDM_IN (CXD56_TOPREG_BASE + 0x99c)
#define CXD56_TOPREG_IO_PDM_OUT (CXD56_TOPREG_BASE + 0x9a0)
#define CXD56_TOPREG_IO_USB_VBUSINT (CXD56_TOPREG_BASE + 0x9a4)
#define CXD56_TOPREG_FUSEWRST (CXD56_TOPREG_BASE + 0xa00)
#define CXD56_TOPREG_FUSEWRAD (CXD56_TOPREG_BASE + 0xa04)
#define CXD56_TOPREG_FUSEWRDT (CXD56_TOPREG_BASE + 0xa08)
#define CXD56_TOPREG_FUSEWRPG (CXD56_TOPREG_BASE + 0xa0c)
#define CXD56_TOPREG_YOBI2_1 (CXD56_TOPREG_BASE + 0xb00)
#define CXD56_TOPREG_GNSSDSP_RAMMODE_SEL (CXD56_TOPREG_BASE + 0xc00)
#define CXD56_TOPREG_CKSEL_GNSS_BB (CXD56_TOPREG_BASE + 0xc04)
#define CXD56_TOPREG_CKDIV_ITP (CXD56_TOPREG_BASE + 0xc0c)
#define CXD56_TOPREG_GNS_ITP_CKEN (CXD56_TOPREG_BASE + 0xc10)
#define CXD56_TOPREG_RF_CTRL (CXD56_TOPREG_BASE + 0xc20)
#define CXD56_TOPREG_GDSP_BOOT_ENTRY_POINT (CXD56_TOPREG_BASE + 0xc30)
#define CXD56_TOPREG_GNSSDSP_RAMMODE_STAT (CXD56_TOPREG_BASE + 0xc40)
#define CXD56_TOPREG_LOGGERIF (CXD56_TOPREG_BASE + 0xc50)
#define CXD56_TOPREG_YOBI2_2 (CXD56_TOPREG_BASE + 0xc60)
#define CXD56_TOPREG_ADSP1_BOOT_ENTRY_POINT (CXD56_TOPREG_BASE + 0x1010)
#define CXD56_TOPREG_ADSP2_BOOT_ENTRY_POINT (CXD56_TOPREG_BASE + 0x1014)
#define CXD56_TOPREG_ADSP3_BOOT_ENTRY_POINT (CXD56_TOPREG_BASE + 0x1018)
#define CXD56_TOPREG_ADSP4_BOOT_ENTRY_POINT (CXD56_TOPREG_BASE + 0x101c)
#define CXD56_TOPREG_ADSP5_BOOT_ENTRY_POINT (CXD56_TOPREG_BASE + 0x1020)
#define CXD56_TOPREG_YOBI2_3 (CXD56_TOPREG_BASE + 0x1040)
#define CXD56_TOPREG_ADSP0_BOOT_ENTRY_POINT (CXD56_TOPREG_BASE + 0x1400)
#define CXD56_TOPREG_USB_VBUS (CXD56_TOPREG_BASE + 0x1410)
#define CXD56_TOPREG_FUSERD00 (CXD56_TOPREG_BASE + 0x1420)
#define CXD56_TOPREG_FUSERD01 (CXD56_TOPREG_BASE + 0x1424)
#define CXD56_TOPREG_FUSERD02 (CXD56_TOPREG_BASE + 0x1428)
#define CXD56_TOPREG_FUSERD03 (CXD56_TOPREG_BASE + 0x142c)
#define CXD56_TOPREG_FUSERD04 (CXD56_TOPREG_BASE + 0x1430)
#define CXD56_TOPREG_FUSERD05 (CXD56_TOPREG_BASE + 0x1434)
#define CXD56_TOPREG_FUSERD06 (CXD56_TOPREG_BASE + 0x1438)
#define CXD56_TOPREG_FUSERD07 (CXD56_TOPREG_BASE + 0x143c)
#define CXD56_TOPREG_FUSERD08 (CXD56_TOPREG_BASE + 0x1440)
#define CXD56_TOPREG_FUSERD09 (CXD56_TOPREG_BASE + 0x1444)
#define CXD56_TOPREG_FUSERD10 (CXD56_TOPREG_BASE + 0x1448)
#define CXD56_TOPREG_FUSERD11 (CXD56_TOPREG_BASE + 0x144c)
#define CXD56_TOPREG_FUSERD12 (CXD56_TOPREG_BASE + 0x1450)
#define CXD56_TOPREG_FUSERD13 (CXD56_TOPREG_BASE + 0x1454)
#define CXD56_TOPREG_FUSERD14 (CXD56_TOPREG_BASE + 0x1458)
#define CXD56_TOPREG_FUSERD15 (CXD56_TOPREG_BASE + 0x145c)
#define CXD56_TOPREG_AUDIO_IF_SEL (CXD56_TOPREG_BASE + 0x1470)
#define CXD56_TOPREG_IOOEN_APP (CXD56_TOPREG_BASE + 0x1474)
#define CXD56_TOPREG_IOFIX_APP (CXD56_TOPREG_BASE + 0x1478)
#define CXD56_TOPREG_IOCAPP_MONSEL0 (CXD56_TOPREG_BASE + 0x1480)
#define CXD56_TOPREG_IOCAPP_MONSEL1 (CXD56_TOPREG_BASE + 0x1484)
#define CXD56_TOPREG_IOCAPP_INTSEL0 (CXD56_TOPREG_BASE + 0x1490)
#define CXD56_TOPREG_IOCAPP_INTSEL1 (CXD56_TOPREG_BASE + 0x1494)
#define CXD56_TOPREG_IOCAPP_IOMD (CXD56_TOPREG_BASE + 0x14a0)
#define CXD56_TOPREG_YOBI2_4 (CXD56_TOPREG_BASE + 0x14c0)
#define CXD56_TOPREG_GP_I2C4_BCK (CXD56_TOPREG_BASE + 0x2000)
#define CXD56_TOPREG_GP_I2C4_BDT (CXD56_TOPREG_BASE + 0x2004)
#define CXD56_TOPREG_GP_PMIC_INT (CXD56_TOPREG_BASE + 0x2008)
#define CXD56_TOPREG_GP_RTC_IRQ_OUT (CXD56_TOPREG_BASE + 0x200c)
#define CXD56_TOPREG_GP_AP_CLK (CXD56_TOPREG_BASE + 0x2010)
#define CXD56_TOPREG_GP_GNSS_1PPS_OUT (CXD56_TOPREG_BASE + 0x2014)
#define CXD56_TOPREG_GP_SPI0_CS_X (CXD56_TOPREG_BASE + 0x2040)
#define CXD56_TOPREG_GP_SPI0_SCK (CXD56_TOPREG_BASE + 0x2044)
#define CXD56_TOPREG_GP_SPI0_MOSI (CXD56_TOPREG_BASE + 0x2048)
#define CXD56_TOPREG_GP_SPI0_MISO (CXD56_TOPREG_BASE + 0x204c)
#define CXD56_TOPREG_GP_SPI1_CS_X (CXD56_TOPREG_BASE + 0x2050)
#define CXD56_TOPREG_GP_SPI1_SCK (CXD56_TOPREG_BASE + 0x2054)
#define CXD56_TOPREG_GP_SPI1_IO0 (CXD56_TOPREG_BASE + 0x2058)
#define CXD56_TOPREG_GP_SPI1_IO1 (CXD56_TOPREG_BASE + 0x205c)
#define CXD56_TOPREG_GP_SPI1_IO2 (CXD56_TOPREG_BASE + 0x2060)
#define CXD56_TOPREG_GP_SPI1_IO3 (CXD56_TOPREG_BASE + 0x2064)
#define CXD56_TOPREG_GP_SPI2_CS_X (CXD56_TOPREG_BASE + 0x2068)
#define CXD56_TOPREG_GP_SPI2_SCK (CXD56_TOPREG_BASE + 0x206c)
#define CXD56_TOPREG_GP_SPI2_MOSI (CXD56_TOPREG_BASE + 0x2070)
#define CXD56_TOPREG_GP_SPI2_MISO (CXD56_TOPREG_BASE + 0x2074)
#define CXD56_TOPREG_GP_HIF_IRQ_OUT (CXD56_TOPREG_BASE + 0x2078)
#define CXD56_TOPREG_GP_HIF_GPIO0 (CXD56_TOPREG_BASE + 0x207c)
#define CXD56_TOPREG_GP_SEN_IRQ_IN (CXD56_TOPREG_BASE + 0x2090)
#define CXD56_TOPREG_GP_SPI3_CS0_X (CXD56_TOPREG_BASE + 0x2094)
#define CXD56_TOPREG_GP_SPI3_CS1_X (CXD56_TOPREG_BASE + 0x2098)
#define CXD56_TOPREG_GP_SPI3_CS2_X (CXD56_TOPREG_BASE + 0x209c)
#define CXD56_TOPREG_GP_SPI3_SCK (CXD56_TOPREG_BASE + 0x20a0)
#define CXD56_TOPREG_GP_SPI3_MOSI (CXD56_TOPREG_BASE + 0x20a4)
#define CXD56_TOPREG_GP_SPI3_MISO (CXD56_TOPREG_BASE + 0x20a8)
#define CXD56_TOPREG_GP_I2C0_BCK (CXD56_TOPREG_BASE + 0x20ac)
#define CXD56_TOPREG_GP_I2C0_BDT (CXD56_TOPREG_BASE + 0x20b0)
#define CXD56_TOPREG_GP_PWM0 (CXD56_TOPREG_BASE + 0x20b4)
#define CXD56_TOPREG_GP_PWM1 (CXD56_TOPREG_BASE + 0x20b8)
#define CXD56_TOPREG_GP_PWM2 (CXD56_TOPREG_BASE + 0x20bc)
#define CXD56_TOPREG_GP_PWM3 (CXD56_TOPREG_BASE + 0x20c0)
#define CXD56_TOPREG_GP_IS_CLK (CXD56_TOPREG_BASE + 0x20c4)
#define CXD56_TOPREG_GP_IS_VSYNC (CXD56_TOPREG_BASE + 0x20c8)
#define CXD56_TOPREG_GP_IS_HSYNC (CXD56_TOPREG_BASE + 0x20cc)
#define CXD56_TOPREG_GP_IS_DATA0 (CXD56_TOPREG_BASE + 0x20d0)
#define CXD56_TOPREG_GP_IS_DATA1 (CXD56_TOPREG_BASE + 0x20d4)
#define CXD56_TOPREG_GP_IS_DATA2 (CXD56_TOPREG_BASE + 0x20d8)
#define CXD56_TOPREG_GP_IS_DATA3 (CXD56_TOPREG_BASE + 0x20dc)
#define CXD56_TOPREG_GP_IS_DATA4 (CXD56_TOPREG_BASE + 0x20e0)
#define CXD56_TOPREG_GP_IS_DATA5 (CXD56_TOPREG_BASE + 0x20e4)
#define CXD56_TOPREG_GP_IS_DATA6 (CXD56_TOPREG_BASE + 0x20e8)
#define CXD56_TOPREG_GP_IS_DATA7 (CXD56_TOPREG_BASE + 0x20ec)
#define CXD56_TOPREG_GP_UART2_TXD (CXD56_TOPREG_BASE + 0x20f0)
#define CXD56_TOPREG_GP_UART2_RXD (CXD56_TOPREG_BASE + 0x20f4)
#define CXD56_TOPREG_GP_UART2_CTS (CXD56_TOPREG_BASE + 0x20f8)
#define CXD56_TOPREG_GP_UART2_RTS (CXD56_TOPREG_BASE + 0x20fc)
#define CXD56_TOPREG_GP_SPI4_CS_X (CXD56_TOPREG_BASE + 0x2100)
#define CXD56_TOPREG_GP_SPI4_SCK (CXD56_TOPREG_BASE + 0x2104)
#define CXD56_TOPREG_GP_SPI4_MOSI (CXD56_TOPREG_BASE + 0x2108)
#define CXD56_TOPREG_GP_SPI4_MISO (CXD56_TOPREG_BASE + 0x210c)
#define CXD56_TOPREG_GP_EMMC_CLK (CXD56_TOPREG_BASE + 0x2110)
#define CXD56_TOPREG_GP_EMMC_CMD (CXD56_TOPREG_BASE + 0x2114)
#define CXD56_TOPREG_GP_EMMC_DATA0 (CXD56_TOPREG_BASE + 0x2118)
#define CXD56_TOPREG_GP_EMMC_DATA1 (CXD56_TOPREG_BASE + 0x211c)
#define CXD56_TOPREG_GP_EMMC_DATA2 (CXD56_TOPREG_BASE + 0x2120)
#define CXD56_TOPREG_GP_EMMC_DATA3 (CXD56_TOPREG_BASE + 0x2124)
#define CXD56_TOPREG_GP_SDIO_CLK (CXD56_TOPREG_BASE + 0x2128)
#define CXD56_TOPREG_GP_SDIO_CMD (CXD56_TOPREG_BASE + 0x212c)
#define CXD56_TOPREG_GP_SDIO_DATA0 (CXD56_TOPREG_BASE + 0x2130)
#define CXD56_TOPREG_GP_SDIO_DATA1 (CXD56_TOPREG_BASE + 0x2134)
#define CXD56_TOPREG_GP_SDIO_DATA2 (CXD56_TOPREG_BASE + 0x2138)
#define CXD56_TOPREG_GP_SDIO_DATA3 (CXD56_TOPREG_BASE + 0x213c)
#define CXD56_TOPREG_GP_SDIO_CD (CXD56_TOPREG_BASE + 0x2140)
#define CXD56_TOPREG_GP_SDIO_WP (CXD56_TOPREG_BASE + 0x2144)
#define CXD56_TOPREG_GP_SDIO_CMDDIR (CXD56_TOPREG_BASE + 0x2148)
#define CXD56_TOPREG_GP_SDIO_DIR0 (CXD56_TOPREG_BASE + 0x214c)
#define CXD56_TOPREG_GP_SDIO_DIR1_3 (CXD56_TOPREG_BASE + 0x2150)
#define CXD56_TOPREG_GP_SDIO_CLKI (CXD56_TOPREG_BASE + 0x2154)
#define CXD56_TOPREG_GP_I2S0_BCK (CXD56_TOPREG_BASE + 0x2158)
#define CXD56_TOPREG_GP_I2S0_LRCK (CXD56_TOPREG_BASE + 0x215c)
#define CXD56_TOPREG_GP_I2S0_DATA_IN (CXD56_TOPREG_BASE + 0x2160)
#define CXD56_TOPREG_GP_I2S0_DATA_OUT (CXD56_TOPREG_BASE + 0x2164)
#define CXD56_TOPREG_GP_I2S1_BCK (CXD56_TOPREG_BASE + 0x2168)
#define CXD56_TOPREG_GP_I2S1_LRCK (CXD56_TOPREG_BASE + 0x216c)
#define CXD56_TOPREG_GP_I2S1_DATA_IN (CXD56_TOPREG_BASE + 0x2170)
#define CXD56_TOPREG_GP_I2S1_DATA_OUT (CXD56_TOPREG_BASE + 0x2174)
#define CXD56_TOPREG_GP_MCLK (CXD56_TOPREG_BASE + 0x2178)
#define CXD56_TOPREG_GP_PDM_CLK (CXD56_TOPREG_BASE + 0x217c)
#define CXD56_TOPREG_GP_PDM_IN (CXD56_TOPREG_BASE + 0x2180)
#define CXD56_TOPREG_GP_PDM_OUT (CXD56_TOPREG_BASE + 0x2184)
#define CXD56_TOPREG_GP_USB_VBUSINT (CXD56_TOPREG_BASE + 0x2188)
#define CXD56_TOPREG_YOBI3 (CXD56_TOPREG_BASE + 0x21fc)
#define CXD56_TOPREG_PWD_CTL (CXD56_TOPREG_BASE + 0x0000)
#define CXD56_TOPREG_ANA_PW_CTL (CXD56_TOPREG_BASE + 0x0004)
#define CXD56_TOPREG_ANA_EN_CTL (CXD56_TOPREG_BASE + 0x0008)
#define CXD56_TOPREG_SYSCPU_RAMMODE_SEL (CXD56_TOPREG_BASE + 0x0010)
#define CXD56_TOPREG_TOP_SCU_RAMMODE_SEL (CXD56_TOPREG_BASE + 0x0018)
#define CXD56_TOPREG_HOSTIFC_RAMMODE_SEL (CXD56_TOPREG_BASE + 0x001c)
#define CXD56_TOPREG_PMU_FAST (CXD56_TOPREG_BASE + 0x0020)
#define CXD56_TOPREG_PMU_PW_CTL (CXD56_TOPREG_BASE + 0x0030)
#define CXD56_TOPREG_PMU_INT_STAT (CXD56_TOPREG_BASE + 0x0040)
#define CXD56_TOPREG_PMU_RAW_INT_STAT (CXD56_TOPREG_BASE + 0x0044)
#define CXD56_TOPREG_PMU_INT_CLR (CXD56_TOPREG_BASE + 0x0048)
#define CXD56_TOPREG_PMU_INT_MASK (CXD56_TOPREG_BASE + 0x004c)
#define CXD56_TOPREG_PWD_RESET0 (CXD56_TOPREG_BASE + 0x0060)
#define CXD56_TOPREG_PWD_STAT (CXD56_TOPREG_BASE + 0x0200)
#define CXD56_TOPREG_PWD_PGACK_STAT (CXD56_TOPREG_BASE + 0x0204)
#define CXD56_TOPREG_ANA_PW_STAT (CXD56_TOPREG_BASE + 0x0208)
#define CXD56_TOPREG_SYSCPU_RAMMODE_STAT (CXD56_TOPREG_BASE + 0x020c)
#define CXD56_TOPREG_TOP_SCU_RAMMODE_STAT (CXD56_TOPREG_BASE + 0x0214)
#define CXD56_TOPREG_HOSTIFC_RAMMODE_STAT (CXD56_TOPREG_BASE + 0x0218)
#define CXD56_TOPREG_PMU_HW_STAT (CXD56_TOPREG_BASE + 0x021c)
#define CXD56_TOPREG_ANA_PW_CTL_SEL_WAKE (CXD56_TOPREG_BASE + 0x0400)
#define CXD56_TOPREG_SYSCPU_RAMMODE_SEL_WAKE (CXD56_TOPREG_BASE + 0x0404)
#define CXD56_TOPREG_TOP_SCU_RAMMODE_SEL_WAKE (CXD56_TOPREG_BASE + 0x0410)
#define CXD56_TOPREG_CLSELDIV_WAKE (CXD56_TOPREG_BASE + 0x0414)
#define CXD56_TOPREG_CKDIV_CPU_DSP_BUS_WAKE (CXD56_TOPREG_BASE + 0x0418)
#define CXD56_TOPREG_CKSEL_ROOT_WAKE (CXD56_TOPREG_BASE + 0x041c)
#define CXD56_TOPREG_PMIC_SLEEP_I2C0 (CXD56_TOPREG_BASE + 0x0420)
#define CXD56_TOPREG_PMIC_SLEEP_I2C1 (CXD56_TOPREG_BASE + 0x0424)
#define CXD56_TOPREG_PMIC_SLEEP_I2C2 (CXD56_TOPREG_BASE + 0x0428)
#define CXD56_TOPREG_PMIC_SLEEP_I2C3 (CXD56_TOPREG_BASE + 0x042c)
#define CXD56_TOPREG_PMIC_WAKE_I2C0 (CXD56_TOPREG_BASE + 0x0430)
#define CXD56_TOPREG_PMIC_WAKE_I2C1 (CXD56_TOPREG_BASE + 0x0434)
#define CXD56_TOPREG_PMIC_WAKE_I2C2 (CXD56_TOPREG_BASE + 0x0438)
#define CXD56_TOPREG_PMIC_WAKE_I2C3 (CXD56_TOPREG_BASE + 0x043c)
#define CXD56_TOPREG_PMIC_UNEXP_I2C0 (CXD56_TOPREG_BASE + 0x0440)
#define CXD56_TOPREG_PMIC_UNEXP_I2C1 (CXD56_TOPREG_BASE + 0x0444)
#define CXD56_TOPREG_PMIC_UNEXP_I2C2 (CXD56_TOPREG_BASE + 0x0448)
#define CXD56_TOPREG_PMIC_UNEXP_I2C3 (CXD56_TOPREG_BASE + 0x044c)
#define CXD56_TOPREG_PMIC_UNEXP_I2C (CXD56_TOPREG_BASE + 0x0450)
#define CXD56_TOPREG_PMU_WAKE_TRIG_EN0 (CXD56_TOPREG_BASE + 0x0454)
#define CXD56_TOPREG_PMU_WAKE_TRIG_EN1 (CXD56_TOPREG_BASE + 0x0458)
#define CXD56_TOPREG_PMU_WAKE_TRIG_NEGEN0 (CXD56_TOPREG_BASE + 0x045c)
#define CXD56_TOPREG_PMU_WAKE_TRIG_NEGEN1 (CXD56_TOPREG_BASE + 0x0460)
#define CXD56_TOPREG_PMU_WAKE_TRIG_NOISECUTEN0 (CXD56_TOPREG_BASE + 0x0464)
#define CXD56_TOPREG_PMU_WAKE_TRIG_CPUINTSEL0 (CXD56_TOPREG_BASE + 0x0468)
#define CXD56_TOPREG_PMU_WAKE_TRIG_CPUINTSEL1 (CXD56_TOPREG_BASE + 0x046c)
#define CXD56_TOPREG_PMU_WAKE_TRIG_CPUINTSEL2 (CXD56_TOPREG_BASE + 0x0470)
#define CXD56_TOPREG_PMU_WAKE_TRIG_INTDET0 (CXD56_TOPREG_BASE + 0x0474)
#define CXD56_TOPREG_PMU_WAKE_TRIG_INTDET1 (CXD56_TOPREG_BASE + 0x0478)
#define CXD56_TOPREG_PMU_WAKE_TRIG_INTDET2 (CXD56_TOPREG_BASE + 0x047c)
#define CXD56_TOPREG_PMU_WAKE_PMIC_I2C (CXD56_TOPREG_BASE + 0x0480)
#define CXD56_TOPREG_BOOT_CAUSE (CXD56_TOPREG_BASE + 0x0484)
#define CXD56_TOPREG_PMU_CORE_CKEN (CXD56_TOPREG_BASE + 0x04c0)
#define CXD56_TOPREG_CKSEL_ROOT (CXD56_TOPREG_BASE + 0x04c4)
#define CXD56_TOPREG_CKSEL_PMU (CXD56_TOPREG_BASE + 0x04c8)
#define CXD56_TOPREG_CKSEL_SYSIOP (CXD56_TOPREG_BASE + 0x04cc)
#define CXD56_TOPREG_CKSEL_SYSIOP_SUB (CXD56_TOPREG_BASE + 0x04d0)
#define CXD56_TOPREG_CKSEL_SCU (CXD56_TOPREG_BASE + 0x04d4)
#define CXD56_TOPREG_CKDIV_CPU_DSP_BUS (CXD56_TOPREG_BASE + 0x04d8)
#define CXD56_TOPREG_CKDIV_COM (CXD56_TOPREG_BASE + 0x04dc)
#define CXD56_TOPREG_CKDIV_HOSTIFC (CXD56_TOPREG_BASE + 0x04e0)
#define CXD56_TOPREG_CKDIV_SCU (CXD56_TOPREG_BASE + 0x04e4)
#define CXD56_TOPREG_CKDIV_PMU (CXD56_TOPREG_BASE + 0x04e8)
#define CXD56_TOPREG_CRG_INT_CLR0 (CXD56_TOPREG_BASE + 0x04ec)
#define CXD56_TOPREG_CRG_INT_MASK0 (CXD56_TOPREG_BASE + 0x04f0)
#define CXD56_TOPREG_CRG_INT_STAT_MSK0 (CXD56_TOPREG_BASE + 0x04f4)
#define CXD56_TOPREG_CRG_INT_STAT_RAW0 (CXD56_TOPREG_BASE + 0x04f8)
#define CXD56_TOPREG_CRG_INT_CLR1 (CXD56_TOPREG_BASE + 0x04fc)
#define CXD56_TOPREG_CRG_INT_MASK1 (CXD56_TOPREG_BASE + 0x0500)
#define CXD56_TOPREG_CRG_INT_STAT_MSK1 (CXD56_TOPREG_BASE + 0x0504)
#define CXD56_TOPREG_CRG_INT_STAT_RAW1 (CXD56_TOPREG_BASE + 0x0508)
#define CXD56_TOPREG_CPU_GATECLK (CXD56_TOPREG_BASE + 0x050c)
#define CXD56_TOPREG_USBPHY_CKEN (CXD56_TOPREG_BASE + 0x0510)
#define CXD56_TOPREG_CRG_MON (CXD56_TOPREG_BASE + 0x0514)
#define CXD56_TOPREG_GEAR_STAT (CXD56_TOPREG_BASE + 0x0518)
#define CXD56_TOPREG_XOSC_CTRL (CXD56_TOPREG_BASE + 0x0580)
#define CXD56_TOPREG_XOSC_CTRL2 (CXD56_TOPREG_BASE + 0x0584)
#define CXD56_TOPREG_SYS_PLL_CTRL1 (CXD56_TOPREG_BASE + 0x0588)
#define CXD56_TOPREG_SYS_PLL_CTRL2 (CXD56_TOPREG_BASE + 0x058c)
#define CXD56_TOPREG_RCOSC_CTRL1 (CXD56_TOPREG_BASE + 0x0590)
#define CXD56_TOPREG_RCOSC_CTRL2 (CXD56_TOPREG_BASE + 0x0594)
#define CXD56_TOPREG_RF_GPMBI_EN (CXD56_TOPREG_BASE + 0x0598)
#define CXD56_TOPREG_WDT_SRST_EN (CXD56_TOPREG_BASE + 0x0640)
#define CXD56_TOPREG_FORCE_CKEN (CXD56_TOPREG_BASE + 0x0644)
#define CXD56_TOPREG_DBG_HOSTIF_SEL (CXD56_TOPREG_BASE + 0x0650)
#define CXD56_TOPREG_WDT_MASK (CXD56_TOPREG_BASE + 0x0654)
#define CXD56_TOPREG_CKGATE_CTL (CXD56_TOPREG_BASE + 0x0660)
#define CXD56_TOPREG_I2CRPT_SADR (CXD56_TOPREG_BASE + 0x06c0)
#define CXD56_TOPREG_I2CRPT_REP (CXD56_TOPREG_BASE + 0x06c4)
#define CXD56_TOPREG_PMIC_I2C (CXD56_TOPREG_BASE + 0x06d0)
#define CXD56_TOPREG_RAMMODE (CXD56_TOPREG_BASE + 0x06e4)
#define CXD56_TOPREG_SWRESET_BUS (CXD56_TOPREG_BASE + 0x0700)
#define CXD56_TOPREG_SWRESET_SCU (CXD56_TOPREG_BASE + 0x0704)
#define CXD56_TOPREG_BUSROM_CKEN (CXD56_TOPREG_BASE + 0x0710)
#define CXD56_TOPREG_SYSIOP_CKEN (CXD56_TOPREG_BASE + 0x0714)
#define CXD56_TOPREG_SCU_CKEN (CXD56_TOPREG_BASE + 0x071c)
#define CXD56_TOPREG_RTC0_CTL (CXD56_TOPREG_BASE + 0x0730)
#define CXD56_TOPREG_FUSERDCFG0 (CXD56_TOPREG_BASE + 0x0740)
#define CXD56_TOPREG_FUSERDCFG1 (CXD56_TOPREG_BASE + 0x0744)
#define CXD56_TOPREG_FUSERDCFG2 (CXD56_TOPREG_BASE + 0x0748)
#define CXD56_TOPREG_VID0 (CXD56_TOPREG_BASE + 0x0750)
#define CXD56_TOPREG_VID1 (CXD56_TOPREG_BASE + 0x0754)
#define CXD56_TOPREG_M0_BOOT_FLASH_DIS (CXD56_TOPREG_BASE + 0x0758)
#define CXD56_TOPREG_LDOADJ0 (CXD56_TOPREG_BASE + 0x0760)
#define CXD56_TOPREG_LDOADJ1 (CXD56_TOPREG_BASE + 0x0764)
#define CXD56_TOPREG_FQFIX_CTL0 (CXD56_TOPREG_BASE + 0x0770)
#define CXD56_TOPREG_FQFIX_AUTO (CXD56_TOPREG_BASE + 0x0774)
#define CXD56_TOPREG_FQFIX_SINGLE (CXD56_TOPREG_BASE + 0x0778)
#define CXD56_TOPREG_FQFIX_STATUS (CXD56_TOPREG_BASE + 0x077c)
#define CXD56_TOPREG_SYSTEM_CONFIG (CXD56_TOPREG_BASE + 0x0790)
#define CXD56_TOPREG_MON_SEL (CXD56_TOPREG_BASE + 0x07a0)
#define CXD56_TOPREG_IOCSYS_MONSEL0 (CXD56_TOPREG_BASE + 0x07a4)
#define CXD56_TOPREG_IOCSYS_MONSEL1 (CXD56_TOPREG_BASE + 0x07a8)
#define CXD56_TOPREG_IOCSYS_INTSEL0 (CXD56_TOPREG_BASE + 0x07b0)
#define CXD56_TOPREG_IOCSYS_INTSEL1 (CXD56_TOPREG_BASE + 0x07b4)
#define CXD56_TOPREG_IOCSYS_IOMD0 (CXD56_TOPREG_BASE + 0x07c0)
#define CXD56_TOPREG_IOCSYS_IOMD1 (CXD56_TOPREG_BASE + 0x07c4)
#define CXD56_TOPREG_IOOEN_SYS (CXD56_TOPREG_BASE + 0x07e0)
#define CXD56_TOPREG_IO_RTC_CLK_IN (CXD56_TOPREG_BASE + 0x0800)
#define CXD56_TOPREG_IO_I2C4_BCK (CXD56_TOPREG_BASE + 0x0804)
#define CXD56_TOPREG_IO_I2C4_BDT (CXD56_TOPREG_BASE + 0x0808)
#define CXD56_TOPREG_IO_PMIC_INT (CXD56_TOPREG_BASE + 0x080c)
#define CXD56_TOPREG_IO_RTC_IRQ_OUT (CXD56_TOPREG_BASE + 0x0810)
#define CXD56_TOPREG_IO_AP_CLK (CXD56_TOPREG_BASE + 0x0814)
#define CXD56_TOPREG_IO_GNSS_1PPS_OUT (CXD56_TOPREG_BASE + 0x0818)
#define CXD56_TOPREG_IO_SPI0_CS_X (CXD56_TOPREG_BASE + 0x0844)
#define CXD56_TOPREG_IO_SPI0_SCK (CXD56_TOPREG_BASE + 0x0848)
#define CXD56_TOPREG_IO_SPI0_MOSI (CXD56_TOPREG_BASE + 0x084c)
#define CXD56_TOPREG_IO_SPI0_MISO (CXD56_TOPREG_BASE + 0x0850)
#define CXD56_TOPREG_IO_SPI1_CS_X (CXD56_TOPREG_BASE + 0x0854)
#define CXD56_TOPREG_IO_SPI1_SCK (CXD56_TOPREG_BASE + 0x0858)
#define CXD56_TOPREG_IO_SPI1_IO0 (CXD56_TOPREG_BASE + 0x085c)
#define CXD56_TOPREG_IO_SPI1_IO1 (CXD56_TOPREG_BASE + 0x0860)
#define CXD56_TOPREG_IO_SPI1_IO2 (CXD56_TOPREG_BASE + 0x0864)
#define CXD56_TOPREG_IO_SPI1_IO3 (CXD56_TOPREG_BASE + 0x0868)
#define CXD56_TOPREG_IO_SPI2_CS_X (CXD56_TOPREG_BASE + 0x086c)
#define CXD56_TOPREG_IO_SPI2_SCK (CXD56_TOPREG_BASE + 0x0870)
#define CXD56_TOPREG_IO_SPI2_MOSI (CXD56_TOPREG_BASE + 0x0874)
#define CXD56_TOPREG_IO_SPI2_MISO (CXD56_TOPREG_BASE + 0x0878)
#define CXD56_TOPREG_IO_HIF_IRQ_OUT (CXD56_TOPREG_BASE + 0x087c)
#define CXD56_TOPREG_IO_HIF_GPIO0 (CXD56_TOPREG_BASE + 0x0880)
#define CXD56_TOPREG_IO_SEN_IRQ_IN (CXD56_TOPREG_BASE + 0x0894)
#define CXD56_TOPREG_IO_SPI3_CS0_X (CXD56_TOPREG_BASE + 0x0898)
#define CXD56_TOPREG_IO_SPI3_CS1_X (CXD56_TOPREG_BASE + 0x089c)
#define CXD56_TOPREG_IO_SPI3_CS2_X (CXD56_TOPREG_BASE + 0x08a0)
#define CXD56_TOPREG_IO_SPI3_SCK (CXD56_TOPREG_BASE + 0x08a4)
#define CXD56_TOPREG_IO_SPI3_MOSI (CXD56_TOPREG_BASE + 0x08a8)
#define CXD56_TOPREG_IO_SPI3_MISO (CXD56_TOPREG_BASE + 0x08ac)
#define CXD56_TOPREG_IO_I2C0_BCK (CXD56_TOPREG_BASE + 0x08b0)
#define CXD56_TOPREG_IO_I2C0_BDT (CXD56_TOPREG_BASE + 0x08b4)
#define CXD56_TOPREG_IO_PWM0 (CXD56_TOPREG_BASE + 0x08b8)
#define CXD56_TOPREG_IO_PWM1 (CXD56_TOPREG_BASE + 0x08bc)
#define CXD56_TOPREG_IO_PWM2 (CXD56_TOPREG_BASE + 0x08c0)
#define CXD56_TOPREG_IO_PWM3 (CXD56_TOPREG_BASE + 0x08c4)
#define CXD56_TOPREG_IO_DBG_SWOCLK (CXD56_TOPREG_BASE + 0x08d4)
#define CXD56_TOPREG_IO_DBG_SWO (CXD56_TOPREG_BASE + 0x08d8)
#define CXD56_TOPREG_IO_IS_CLK (CXD56_TOPREG_BASE + 0x08e0)
#define CXD56_TOPREG_IO_IS_VSYNC (CXD56_TOPREG_BASE + 0x08e4)
#define CXD56_TOPREG_IO_IS_HSYNC (CXD56_TOPREG_BASE + 0x08e8)
#define CXD56_TOPREG_IO_IS_DATA0 (CXD56_TOPREG_BASE + 0x08ec)
#define CXD56_TOPREG_IO_IS_DATA1 (CXD56_TOPREG_BASE + 0x08f0)
#define CXD56_TOPREG_IO_IS_DATA2 (CXD56_TOPREG_BASE + 0x08f4)
#define CXD56_TOPREG_IO_IS_DATA3 (CXD56_TOPREG_BASE + 0x08f8)
#define CXD56_TOPREG_IO_IS_DATA4 (CXD56_TOPREG_BASE + 0x08fc)
#define CXD56_TOPREG_IO_IS_DATA5 (CXD56_TOPREG_BASE + 0x0900)
#define CXD56_TOPREG_IO_IS_DATA6 (CXD56_TOPREG_BASE + 0x0904)
#define CXD56_TOPREG_IO_IS_DATA7 (CXD56_TOPREG_BASE + 0x0908)
#define CXD56_TOPREG_IO_UART2_TXD (CXD56_TOPREG_BASE + 0x090c)
#define CXD56_TOPREG_IO_UART2_RXD (CXD56_TOPREG_BASE + 0x0910)
#define CXD56_TOPREG_IO_UART2_CTS (CXD56_TOPREG_BASE + 0x0914)
#define CXD56_TOPREG_IO_UART2_RTS (CXD56_TOPREG_BASE + 0x0918)
#define CXD56_TOPREG_IO_SPI4_CS_X (CXD56_TOPREG_BASE + 0x091c)
#define CXD56_TOPREG_IO_SPI4_SCK (CXD56_TOPREG_BASE + 0x0920)
#define CXD56_TOPREG_IO_SPI4_MOSI (CXD56_TOPREG_BASE + 0x0924)
#define CXD56_TOPREG_IO_SPI4_MISO (CXD56_TOPREG_BASE + 0x0928)
#define CXD56_TOPREG_IO_EMMC_CLK (CXD56_TOPREG_BASE + 0x092c)
#define CXD56_TOPREG_IO_EMMC_CMD (CXD56_TOPREG_BASE + 0x0930)
#define CXD56_TOPREG_IO_EMMC_DATA0 (CXD56_TOPREG_BASE + 0x0934)
#define CXD56_TOPREG_IO_EMMC_DATA1 (CXD56_TOPREG_BASE + 0x0938)
#define CXD56_TOPREG_IO_EMMC_DATA2 (CXD56_TOPREG_BASE + 0x093c)
#define CXD56_TOPREG_IO_EMMC_DATA3 (CXD56_TOPREG_BASE + 0x0940)
#define CXD56_TOPREG_IO_SDIO_CLK (CXD56_TOPREG_BASE + 0x0944)
#define CXD56_TOPREG_IO_SDIO_CMD (CXD56_TOPREG_BASE + 0x0948)
#define CXD56_TOPREG_IO_SDIO_DATA0 (CXD56_TOPREG_BASE + 0x094c)
#define CXD56_TOPREG_IO_SDIO_DATA1 (CXD56_TOPREG_BASE + 0x0950)
#define CXD56_TOPREG_IO_SDIO_DATA2 (CXD56_TOPREG_BASE + 0x0954)
#define CXD56_TOPREG_IO_SDIO_DATA3 (CXD56_TOPREG_BASE + 0x0958)
#define CXD56_TOPREG_IO_SDIO_CD (CXD56_TOPREG_BASE + 0x095c)
#define CXD56_TOPREG_IO_SDIO_WP (CXD56_TOPREG_BASE + 0x0960)
#define CXD56_TOPREG_IO_SDIO_CMDDIR (CXD56_TOPREG_BASE + 0x0964)
#define CXD56_TOPREG_IO_SDIO_DIR0 (CXD56_TOPREG_BASE + 0x0968)
#define CXD56_TOPREG_IO_SDIO_DIR1_3 (CXD56_TOPREG_BASE + 0x096c)
#define CXD56_TOPREG_IO_SDIO_CLKI (CXD56_TOPREG_BASE + 0x0970)
#define CXD56_TOPREG_IO_I2S0_BCK (CXD56_TOPREG_BASE + 0x0974)
#define CXD56_TOPREG_IO_I2S0_LRCK (CXD56_TOPREG_BASE + 0x0978)
#define CXD56_TOPREG_IO_I2S0_DATA_IN (CXD56_TOPREG_BASE + 0x097c)
#define CXD56_TOPREG_IO_I2S0_DATA_OUT (CXD56_TOPREG_BASE + 0x0980)
#define CXD56_TOPREG_IO_I2S1_BCK (CXD56_TOPREG_BASE + 0x0984)
#define CXD56_TOPREG_IO_I2S1_LRCK (CXD56_TOPREG_BASE + 0x0988)
#define CXD56_TOPREG_IO_I2S1_DATA_IN (CXD56_TOPREG_BASE + 0x098c)
#define CXD56_TOPREG_IO_I2S1_DATA_OUT (CXD56_TOPREG_BASE + 0x0990)
#define CXD56_TOPREG_IO_MCLK (CXD56_TOPREG_BASE + 0x0994)
#define CXD56_TOPREG_IO_PDM_CLK (CXD56_TOPREG_BASE + 0x0998)
#define CXD56_TOPREG_IO_PDM_IN (CXD56_TOPREG_BASE + 0x099c)
#define CXD56_TOPREG_IO_PDM_OUT (CXD56_TOPREG_BASE + 0x09a0)
#define CXD56_TOPREG_IO_USB_VBUSINT (CXD56_TOPREG_BASE + 0x09a4)
#define CXD56_TOPREG_FUSEWRST (CXD56_TOPREG_BASE + 0x0a00)
#define CXD56_TOPREG_FUSEWRAD (CXD56_TOPREG_BASE + 0x0a04)
#define CXD56_TOPREG_FUSEWRDT (CXD56_TOPREG_BASE + 0x0a08)
#define CXD56_TOPREG_FUSEWRPG (CXD56_TOPREG_BASE + 0x0a0c)
#define CXD56_TOPREG_ADSP1_BOOT_ENTRY_POINT (CXD56_TOPREG_BASE + 0x1010)
#define CXD56_TOPREG_ADSP2_BOOT_ENTRY_POINT (CXD56_TOPREG_BASE + 0x1014)
#define CXD56_TOPREG_ADSP3_BOOT_ENTRY_POINT (CXD56_TOPREG_BASE + 0x1018)
#define CXD56_TOPREG_ADSP4_BOOT_ENTRY_POINT (CXD56_TOPREG_BASE + 0x101c)
#define CXD56_TOPREG_ADSP5_BOOT_ENTRY_POINT (CXD56_TOPREG_BASE + 0x1020)
#define CXD56_TOPREG_ADSP0_BOOT_ENTRY_POINT (CXD56_TOPREG_BASE + 0x1400)
#define CXD56_TOPREG_USB_VBUS (CXD56_TOPREG_BASE + 0x1410)
#define CXD56_TOPREG_FUSERD00 (CXD56_TOPREG_BASE + 0x1420)
#define CXD56_TOPREG_FUSERD01 (CXD56_TOPREG_BASE + 0x1424)
#define CXD56_TOPREG_FUSERD02 (CXD56_TOPREG_BASE + 0x1428)
#define CXD56_TOPREG_FUSERD03 (CXD56_TOPREG_BASE + 0x142c)
#define CXD56_TOPREG_FUSERD04 (CXD56_TOPREG_BASE + 0x1430)
#define CXD56_TOPREG_FUSERD05 (CXD56_TOPREG_BASE + 0x1434)
#define CXD56_TOPREG_FUSERD06 (CXD56_TOPREG_BASE + 0x1438)
#define CXD56_TOPREG_FUSERD07 (CXD56_TOPREG_BASE + 0x143c)
#define CXD56_TOPREG_FUSERD08 (CXD56_TOPREG_BASE + 0x1440)
#define CXD56_TOPREG_FUSERD09 (CXD56_TOPREG_BASE + 0x1444)
#define CXD56_TOPREG_FUSERD10 (CXD56_TOPREG_BASE + 0x1448)
#define CXD56_TOPREG_FUSERD11 (CXD56_TOPREG_BASE + 0x144c)
#define CXD56_TOPREG_FUSERD12 (CXD56_TOPREG_BASE + 0x1450)
#define CXD56_TOPREG_FUSERD13 (CXD56_TOPREG_BASE + 0x1454)
#define CXD56_TOPREG_FUSERD14 (CXD56_TOPREG_BASE + 0x1458)
#define CXD56_TOPREG_FUSERD15 (CXD56_TOPREG_BASE + 0x145c)
#define CXD56_TOPREG_AUDIO_IF_SEL (CXD56_TOPREG_BASE + 0x1470)
#define CXD56_TOPREG_IOOEN_APP (CXD56_TOPREG_BASE + 0x1474)
#define CXD56_TOPREG_IOFIX_APP (CXD56_TOPREG_BASE + 0x1478)
#define CXD56_TOPREG_IOCAPP_MONSEL0 (CXD56_TOPREG_BASE + 0x1480)
#define CXD56_TOPREG_IOCAPP_MONSEL1 (CXD56_TOPREG_BASE + 0x1484)
#define CXD56_TOPREG_IOCAPP_INTSEL0 (CXD56_TOPREG_BASE + 0x1490)
#define CXD56_TOPREG_IOCAPP_INTSEL1 (CXD56_TOPREG_BASE + 0x1494)
#define CXD56_TOPREG_IOCAPP_IOMD (CXD56_TOPREG_BASE + 0x14a0)
#define CXD56_TOPREG_GP_I2C4_BCK (CXD56_TOPREG_BASE + 0x2000)
#define CXD56_TOPREG_GP_I2C4_BDT (CXD56_TOPREG_BASE + 0x2004)
#define CXD56_TOPREG_GP_PMIC_INT (CXD56_TOPREG_BASE + 0x2008)
#define CXD56_TOPREG_GP_RTC_IRQ_OUT (CXD56_TOPREG_BASE + 0x200c)
#define CXD56_TOPREG_GP_AP_CLK (CXD56_TOPREG_BASE + 0x2010)
#define CXD56_TOPREG_GP_GNSS_1PPS_OUT (CXD56_TOPREG_BASE + 0x2014)
#define CXD56_TOPREG_GP_SPI0_CS_X (CXD56_TOPREG_BASE + 0x2040)
#define CXD56_TOPREG_GP_SPI0_SCK (CXD56_TOPREG_BASE + 0x2044)
#define CXD56_TOPREG_GP_SPI0_MOSI (CXD56_TOPREG_BASE + 0x2048)
#define CXD56_TOPREG_GP_SPI0_MISO (CXD56_TOPREG_BASE + 0x204c)
#define CXD56_TOPREG_GP_SPI1_CS_X (CXD56_TOPREG_BASE + 0x2050)
#define CXD56_TOPREG_GP_SPI1_SCK (CXD56_TOPREG_BASE + 0x2054)
#define CXD56_TOPREG_GP_SPI1_IO0 (CXD56_TOPREG_BASE + 0x2058)
#define CXD56_TOPREG_GP_SPI1_IO1 (CXD56_TOPREG_BASE + 0x205c)
#define CXD56_TOPREG_GP_SPI1_IO2 (CXD56_TOPREG_BASE + 0x2060)
#define CXD56_TOPREG_GP_SPI1_IO3 (CXD56_TOPREG_BASE + 0x2064)
#define CXD56_TOPREG_GP_SPI2_CS_X (CXD56_TOPREG_BASE + 0x2068)
#define CXD56_TOPREG_GP_SPI2_SCK (CXD56_TOPREG_BASE + 0x206c)
#define CXD56_TOPREG_GP_SPI2_MOSI (CXD56_TOPREG_BASE + 0x2070)
#define CXD56_TOPREG_GP_SPI2_MISO (CXD56_TOPREG_BASE + 0x2074)
#define CXD56_TOPREG_GP_HIF_IRQ_OUT (CXD56_TOPREG_BASE + 0x2078)
#define CXD56_TOPREG_GP_HIF_GPIO0 (CXD56_TOPREG_BASE + 0x207c)
#define CXD56_TOPREG_GP_SEN_IRQ_IN (CXD56_TOPREG_BASE + 0x2090)
#define CXD56_TOPREG_GP_SPI3_CS0_X (CXD56_TOPREG_BASE + 0x2094)
#define CXD56_TOPREG_GP_SPI3_CS1_X (CXD56_TOPREG_BASE + 0x2098)
#define CXD56_TOPREG_GP_SPI3_CS2_X (CXD56_TOPREG_BASE + 0x209c)
#define CXD56_TOPREG_GP_SPI3_SCK (CXD56_TOPREG_BASE + 0x20a0)
#define CXD56_TOPREG_GP_SPI3_MOSI (CXD56_TOPREG_BASE + 0x20a4)
#define CXD56_TOPREG_GP_SPI3_MISO (CXD56_TOPREG_BASE + 0x20a8)
#define CXD56_TOPREG_GP_I2C0_BCK (CXD56_TOPREG_BASE + 0x20ac)
#define CXD56_TOPREG_GP_I2C0_BDT (CXD56_TOPREG_BASE + 0x20b0)
#define CXD56_TOPREG_GP_PWM0 (CXD56_TOPREG_BASE + 0x20b4)
#define CXD56_TOPREG_GP_PWM1 (CXD56_TOPREG_BASE + 0x20b8)
#define CXD56_TOPREG_GP_PWM2 (CXD56_TOPREG_BASE + 0x20bc)
#define CXD56_TOPREG_GP_PWM3 (CXD56_TOPREG_BASE + 0x20c0)
#define CXD56_TOPREG_GP_IS_CLK (CXD56_TOPREG_BASE + 0x20c4)
#define CXD56_TOPREG_GP_IS_VSYNC (CXD56_TOPREG_BASE + 0x20c8)
#define CXD56_TOPREG_GP_IS_HSYNC (CXD56_TOPREG_BASE + 0x20cc)
#define CXD56_TOPREG_GP_IS_DATA0 (CXD56_TOPREG_BASE + 0x20d0)
#define CXD56_TOPREG_GP_IS_DATA1 (CXD56_TOPREG_BASE + 0x20d4)
#define CXD56_TOPREG_GP_IS_DATA2 (CXD56_TOPREG_BASE + 0x20d8)
#define CXD56_TOPREG_GP_IS_DATA3 (CXD56_TOPREG_BASE + 0x20dc)
#define CXD56_TOPREG_GP_IS_DATA4 (CXD56_TOPREG_BASE + 0x20e0)
#define CXD56_TOPREG_GP_IS_DATA5 (CXD56_TOPREG_BASE + 0x20e4)
#define CXD56_TOPREG_GP_IS_DATA6 (CXD56_TOPREG_BASE + 0x20e8)
#define CXD56_TOPREG_GP_IS_DATA7 (CXD56_TOPREG_BASE + 0x20ec)
#define CXD56_TOPREG_GP_UART2_TXD (CXD56_TOPREG_BASE + 0x20f0)
#define CXD56_TOPREG_GP_UART2_RXD (CXD56_TOPREG_BASE + 0x20f4)
#define CXD56_TOPREG_GP_UART2_CTS (CXD56_TOPREG_BASE + 0x20f8)
#define CXD56_TOPREG_GP_UART2_RTS (CXD56_TOPREG_BASE + 0x20fc)
#define CXD56_TOPREG_GP_SPI4_CS_X (CXD56_TOPREG_BASE + 0x2100)
#define CXD56_TOPREG_GP_SPI4_SCK (CXD56_TOPREG_BASE + 0x2104)
#define CXD56_TOPREG_GP_SPI4_MOSI (CXD56_TOPREG_BASE + 0x2108)
#define CXD56_TOPREG_GP_SPI4_MISO (CXD56_TOPREG_BASE + 0x210c)
#define CXD56_TOPREG_GP_EMMC_CLK (CXD56_TOPREG_BASE + 0x2110)
#define CXD56_TOPREG_GP_EMMC_CMD (CXD56_TOPREG_BASE + 0x2114)
#define CXD56_TOPREG_GP_EMMC_DATA0 (CXD56_TOPREG_BASE + 0x2118)
#define CXD56_TOPREG_GP_EMMC_DATA1 (CXD56_TOPREG_BASE + 0x211c)
#define CXD56_TOPREG_GP_EMMC_DATA2 (CXD56_TOPREG_BASE + 0x2120)
#define CXD56_TOPREG_GP_EMMC_DATA3 (CXD56_TOPREG_BASE + 0x2124)
#define CXD56_TOPREG_GP_SDIO_CLK (CXD56_TOPREG_BASE + 0x2128)
#define CXD56_TOPREG_GP_SDIO_CMD (CXD56_TOPREG_BASE + 0x212c)
#define CXD56_TOPREG_GP_SDIO_DATA0 (CXD56_TOPREG_BASE + 0x2130)
#define CXD56_TOPREG_GP_SDIO_DATA1 (CXD56_TOPREG_BASE + 0x2134)
#define CXD56_TOPREG_GP_SDIO_DATA2 (CXD56_TOPREG_BASE + 0x2138)
#define CXD56_TOPREG_GP_SDIO_DATA3 (CXD56_TOPREG_BASE + 0x213c)
#define CXD56_TOPREG_GP_SDIO_CD (CXD56_TOPREG_BASE + 0x2140)
#define CXD56_TOPREG_GP_SDIO_WP (CXD56_TOPREG_BASE + 0x2144)
#define CXD56_TOPREG_GP_SDIO_CMDDIR (CXD56_TOPREG_BASE + 0x2148)
#define CXD56_TOPREG_GP_SDIO_DIR0 (CXD56_TOPREG_BASE + 0x214c)
#define CXD56_TOPREG_GP_SDIO_DIR1_3 (CXD56_TOPREG_BASE + 0x2150)
#define CXD56_TOPREG_GP_SDIO_CLKI (CXD56_TOPREG_BASE + 0x2154)
#define CXD56_TOPREG_GP_I2S0_BCK (CXD56_TOPREG_BASE + 0x2158)
#define CXD56_TOPREG_GP_I2S0_LRCK (CXD56_TOPREG_BASE + 0x215c)
#define CXD56_TOPREG_GP_I2S0_DATA_IN (CXD56_TOPREG_BASE + 0x2160)
#define CXD56_TOPREG_GP_I2S0_DATA_OUT (CXD56_TOPREG_BASE + 0x2164)
#define CXD56_TOPREG_GP_I2S1_BCK (CXD56_TOPREG_BASE + 0x2168)
#define CXD56_TOPREG_GP_I2S1_LRCK (CXD56_TOPREG_BASE + 0x216c)
#define CXD56_TOPREG_GP_I2S1_DATA_IN (CXD56_TOPREG_BASE + 0x2170)
#define CXD56_TOPREG_GP_I2S1_DATA_OUT (CXD56_TOPREG_BASE + 0x2174)
#define CXD56_TOPREG_GP_MCLK (CXD56_TOPREG_BASE + 0x2178)
#define CXD56_TOPREG_GP_PDM_CLK (CXD56_TOPREG_BASE + 0x217c)
#define CXD56_TOPREG_GP_PDM_IN (CXD56_TOPREG_BASE + 0x2180)
#define CXD56_TOPREG_GP_PDM_OUT (CXD56_TOPREG_BASE + 0x2184)
#define CXD56_TOPREG_GP_USB_VBUSINT (CXD56_TOPREG_BASE + 0x2188)
/* Topreg sub */
#define CXD56_TOPREG_PSW_CHECK (CXD56_TOPREG_SUB_BASE + 0x0000)
#define CXD56_TOPREG_UNEXP_PSW_DIG (CXD56_TOPREG_SUB_BASE + 0x0004)
#define CXD56_TOPREG_UNEXP_PSW_ANA (CXD56_TOPREG_SUB_BASE + 0x0008)
#define CXD56_TOPREG_UNEXP_OTHER (CXD56_TOPREG_SUB_BASE + 0x000c)
#define CXD56_TOPREG_UNEXP_CLR (CXD56_TOPREG_SUB_BASE + 0x0010)
#define CXD56_TOPREG_PMU_WAIT10 (CXD56_TOPREG_SUB_BASE + 0x0020)
#define CXD56_TOPREG_PMU_WAIT11 (CXD56_TOPREG_SUB_BASE + 0x0024)
#if 0
#define CXD56_TOPREG_PMU_DBG_INITEN (CXD56_TOPREG_SUB_BASE + 0x0030)
#define CXD56_TOPREG_PMU_DBG_LUMPEN (CXD56_TOPREG_SUB_BASE + 0x0034)
#endif
#define CXD56_TOPREG_SWRESET_DBG (CXD56_TOPREG_SUB_BASE + 0x0400)
#define CXD56_TOPREG_SWRESET_GNSDSP (CXD56_TOPREG_SUB_BASE + 0x0404)
#define CXD56_TOPREG_SWRESET_APP (CXD56_TOPREG_SUB_BASE + 0x0408)
#define CXD56_TOPREG_SYSCPU_CKEN (CXD56_TOPREG_SUB_BASE + 0x0410)
#define CXD56_TOPREG_APP_CKEN (CXD56_TOPREG_SUB_BASE + 0x0414)
#define CXD56_TOPREG_APP_CKSEL (CXD56_TOPREG_SUB_BASE + 0x0418)
#define CXD56_TOPREG_APP_DIV (CXD56_TOPREG_SUB_BASE + 0x041c)
#define CXD56_TOPREG_SYSIOP_SUB_CKEN (CXD56_TOPREG_SUB_BASE + 0x0420)
#define CXD56_TOPREG_ROSC_MON (CXD56_TOPREG_SUB_BASE + 0x0428)
#define CXD56_TOPREG_TDC_MON (CXD56_TOPREG_SUB_BASE + 0x042c)
#define CXD56_TOPREG_PMU_WAKE_TRIG0_CLR (CXD56_TOPREG_SUB_BASE + 0x0430)
#define CXD56_TOPREG_PMU_WAKE_TRIG1_CLR (CXD56_TOPREG_SUB_BASE + 0x0434)
#define CXD56_TOPREG_PMU_WAKE_TRIG0_RAW (CXD56_TOPREG_SUB_BASE + 0x0438)
#define CXD56_TOPREG_PMU_WAKE_TRIG1_RAW (CXD56_TOPREG_SUB_BASE + 0x043c)
#define CXD56_TOPREG_PMU_WAKE_TRIG0 (CXD56_TOPREG_SUB_BASE + 0x0440)
#define CXD56_TOPREG_PMU_WAKE_TRIG1 (CXD56_TOPREG_SUB_BASE + 0x0444)
#define CXD56_TOPREG_RTC1_CTL (CXD56_TOPREG_SUB_BASE + 0x0470)
#define CXD56_TOPREG_GNSS_RAMMODE_SEL (CXD56_TOPREG_SUB_BASE + 0x0c00)
#define CXD56_TOPREG_SWRESET_GNSDSP2 (CXD56_TOPREG_SUB_BASE + 0x0c10)
#define CXD56_TOPREG_SWRESET_BB (CXD56_TOPREG_SUB_BASE + 0x0c14)
#define CXD56_TOPREG_GNSDSP_CKEN (CXD56_TOPREG_SUB_BASE + 0x0c20)
#define CXD56_TOPREG_GNSS_BB_CKEN (CXD56_TOPREG_SUB_BASE + 0x0c24)
#define CXD56_TOPREG_GNSS_DIV (CXD56_TOPREG_SUB_BASE + 0x0c28)
#define CXD56_TOPREG_GNSS_RAMMODE_STAT (CXD56_TOPREG_SUB_BASE + 0x0c30)
#define CXD56_TOPREG_APPDSP_RAMMODE_SEL0 (CXD56_TOPREG_SUB_BASE + 0x1400)
#define CXD56_TOPREG_APPDSP_RAMMODE_SEL1 (CXD56_TOPREG_SUB_BASE + 0x1404)
#define CXD56_TOPREG_APPDSP_RAMMODE_STAT0 (CXD56_TOPREG_SUB_BASE + 0x1420)
#define CXD56_TOPREG_APPDSP_RAMMODE_STAT1 (CXD56_TOPREG_SUB_BASE + 0x1424)
#define CXD56_TOPREG_BUSERR0 (CXD56_TOPREG_SUB_BASE + 0x1470)
#define CXD56_TOPREG_BUSERR1 (CXD56_TOPREG_SUB_BASE + 0x1474)
#define CXD56_TOPREG_BUSERR2 (CXD56_TOPREG_SUB_BASE + 0x1478)
#define CXD56_TOPREG_CHIP_ID (CXD56_TOPREG_SUB_BASE + 0x1490)
#define CXD56_TOPREG_CUID0 (CXD56_TOPREG_SUB_BASE + 0x1494)
#define CXD56_TOPREG_CUID1 (CXD56_TOPREG_SUB_BASE + 0x1498)
#define CXD56_TOPREG_UDID0 (CXD56_TOPREG_SUB_BASE + 0x149c)
#define CXD56_TOPREG_UDID1 (CXD56_TOPREG_SUB_BASE + 0x14a0)
#define CXD56_TOPREG_FUSE_STATUS (CXD56_TOPREG_SUB_BASE + 0x14a4)
#define CXD56_TOPREG_SDBG_ENB (CXD56_TOPREG_SUB_BASE + 0x14a8)
#define CXD56_TOPREG_DBG_MONSEL (CXD56_TOPREG_SUB_BASE + 0x14c0)
#define CXD56_TOPREG_PSW_CHECK (CXD56_TOPREG_SUB_BASE + 0x0000)
#define CXD56_TOPREG_UNEXP_PSW_DIG (CXD56_TOPREG_SUB_BASE + 0x0004)
#define CXD56_TOPREG_UNEXP_PSW_ANA (CXD56_TOPREG_SUB_BASE + 0x0008)
#define CXD56_TOPREG_UNEXP_OTHER (CXD56_TOPREG_SUB_BASE + 0x000c)
#define CXD56_TOPREG_UNEXP_CLR (CXD56_TOPREG_SUB_BASE + 0x0010)
#define CXD56_TOPREG_PMU_WAIT10 (CXD56_TOPREG_SUB_BASE + 0x0020)
#define CXD56_TOPREG_PMU_WAIT11 (CXD56_TOPREG_SUB_BASE + 0x0024)
#define CXD56_TOPREG_SWRESET_DBG (CXD56_TOPREG_SUB_BASE + 0x0400)
#define CXD56_TOPREG_SWRESET_GNSDSP (CXD56_TOPREG_SUB_BASE + 0x0404)
#define CXD56_TOPREG_SWRESET_APP (CXD56_TOPREG_SUB_BASE + 0x0408)
#define CXD56_TOPREG_SYSCPU_CKEN (CXD56_TOPREG_SUB_BASE + 0x0410)
#define CXD56_TOPREG_APP_CKEN (CXD56_TOPREG_SUB_BASE + 0x0414)
#define CXD56_TOPREG_APP_CKSEL (CXD56_TOPREG_SUB_BASE + 0x0418)
#define CXD56_TOPREG_APP_DIV (CXD56_TOPREG_SUB_BASE + 0x041c)
#define CXD56_TOPREG_SYSIOP_SUB_CKEN (CXD56_TOPREG_SUB_BASE + 0x0420)
#define CXD56_TOPREG_ROSC_MON (CXD56_TOPREG_SUB_BASE + 0x0428)
#define CXD56_TOPREG_TDC_MON (CXD56_TOPREG_SUB_BASE + 0x042c)
#define CXD56_TOPREG_PMU_WAKE_TRIG0_CLR (CXD56_TOPREG_SUB_BASE + 0x0430)
#define CXD56_TOPREG_PMU_WAKE_TRIG1_CLR (CXD56_TOPREG_SUB_BASE + 0x0434)
#define CXD56_TOPREG_PMU_WAKE_TRIG0_RAW (CXD56_TOPREG_SUB_BASE + 0x0438)
#define CXD56_TOPREG_PMU_WAKE_TRIG1_RAW (CXD56_TOPREG_SUB_BASE + 0x043c)
#define CXD56_TOPREG_PMU_WAKE_TRIG0 (CXD56_TOPREG_SUB_BASE + 0x0440)
#define CXD56_TOPREG_PMU_WAKE_TRIG1 (CXD56_TOPREG_SUB_BASE + 0x0444)
#define CXD56_TOPREG_RTC1_CTL (CXD56_TOPREG_SUB_BASE + 0x0470)
#define CXD56_TOPREG_GNSDSP_CKEN (CXD56_TOPREG_SUB_BASE + 0x0c20)
#define CXD56_TOPREG_GNSS_DIV (CXD56_TOPREG_SUB_BASE + 0x0c28)
#define CXD56_TOPREG_APPDSP_RAMMODE_SEL0 (CXD56_TOPREG_SUB_BASE + 0x1400)
#define CXD56_TOPREG_APPDSP_RAMMODE_SEL1 (CXD56_TOPREG_SUB_BASE + 0x1404)
#define CXD56_TOPREG_APPDSP_RAMMODE_STAT0 (CXD56_TOPREG_SUB_BASE + 0x1420)
#define CXD56_TOPREG_APPDSP_RAMMODE_STAT1 (CXD56_TOPREG_SUB_BASE + 0x1424)
#define CXD56_TOPREG_BUSERR0 (CXD56_TOPREG_SUB_BASE + 0x1470)
#define CXD56_TOPREG_BUSERR1 (CXD56_TOPREG_SUB_BASE + 0x1474)
#define CXD56_TOPREG_BUSERR2 (CXD56_TOPREG_SUB_BASE + 0x1478)
#define CXD56_TOPREG_CHIP_ID (CXD56_TOPREG_SUB_BASE + 0x1490)
#define CXD56_TOPREG_CUID0 (CXD56_TOPREG_SUB_BASE + 0x1494)
#define CXD56_TOPREG_CUID1 (CXD56_TOPREG_SUB_BASE + 0x1498)
#define CXD56_TOPREG_UDID0 (CXD56_TOPREG_SUB_BASE + 0x149c)
#define CXD56_TOPREG_UDID1 (CXD56_TOPREG_SUB_BASE + 0x14a0)
#define CXD56_TOPREG_FUSE_STATUS (CXD56_TOPREG_SUB_BASE + 0x14a4)
#define CXD56_TOPREG_SDBG_ENB (CXD56_TOPREG_SUB_BASE + 0x14a8)
#define CXD56_TOPREG_DBG_MONSEL (CXD56_TOPREG_SUB_BASE + 0x14c0)
/* PWD_CTL, PWD_STAT */

6
arch/arm/src/cxd56xx/hardware/cxd56_adc.h
View file

@ -33,8 +33,8 @@
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_CXD56XX_CHIP_CXD56_ADC_H
#define __ARCH_ARM_SRC_CXD56XX_CHIP_CXD56_ADC_H
#ifndef __ARCH_ARM_SRC_CXD56XX_HARDWARE_CXD56_ADC_H
#define __ARCH_ARM_SRC_CXD56XX_HARDWARE_CXD56_ADC_H
#define SCUADCIF_LPADC_A0 (CXD56_SCU_ADCIF_BASE + 0x200)
#define SCUADCIF_LPADC_A1 (CXD56_SCU_ADCIF_BASE + 0x204)
@ -72,4 +72,4 @@
#define SCUADCIF_ADCIF_DCT (CXD56_SCU_ADCIF_BASE + 0x3d0)
#define SCUADCIF_SCU_ADCIF_CKPOWER (CXD56_SCU_ADCIF_BASE + 0x3d4)
#endif /* __ARCH_ARM_SRC_CXD56XX_CHIP_CXD56_ADC_H */
#endif /* __ARCH_ARM_SRC_CXD56XX_HARDWARE_CXD56_ADC_H */

6
arch/arm/src/cxd56xx/hardware/cxd56_cisif.h
View file

@ -33,8 +33,8 @@
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_CXD56XX_CHIP__CXD56_CISIF_H
#define __ARCH_ARM_SRC_CXD56XX_CHIP__CXD56_CISIF_H
#ifndef __ARCH_ARM_SRC_CXD56XX_HARDWARE_CXD56_CISIF_H
#define __ARCH_ARM_SRC_CXD56XX_HARDWARE_CXD56_CISIF_H
/****************************************************************************
* Included Files
@ -110,4 +110,4 @@
#define MODE_JPG_TRS_EN (0x00000109)
#define MODE_INTLEV_TRS_EN (0x0000010E)
#endif /* __ARCH_ARM_SRC_CXD56XX_CHIP__CXD56_CISIF_H */
#endif /* __ARCH_ARM_SRC_CXD56XX_HARDWARE_CXD56_CISIF_H */

6
arch/arm/src/cxd56xx/hardware/cxd56_cpufifo.h
View file

@ -33,8 +33,8 @@
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_CXD56XX_CHIP_CXD56_CPUFIFO_H
#define __ARCH_ARM_SRC_CXD56XX_CHIP_CXD56_CPUFIFO_H
#ifndef __ARCH_ARM_SRC_CXD56XX_HARDWARE_CXD56_CPUFIFO_H
#define __ARCH_ARM_SRC_CXD56XX_HARDWARE_CXD56_CPUFIFO_H
/************************************************************************************
* Included Files
@ -55,4 +55,4 @@
#define CXD56_FIF_PULL_WRD1 (CXD56_CPUFIFO_BASE + 0x18)
#define CXD56_FIF_PULL_CMP (CXD56_CPUFIFO_BASE + 0x1c)
#endif /* __ARCH_ARM_SRC_CXD56XX_CHIP_CXD56_CPUFIFO_H */
#endif /* __ARCH_ARM_SRC_CXD56XX_HARDWARE_CXD56_CPUFIFO_H */

4
arch/arm/src/cxd56xx/hardware/cxd56_crg.h
View file

@ -36,8 +36,8 @@
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_CXD56XX_CHIP_CXD56_CRG_H
#define __ARCH_ARM_SRC_CXD56XX_CHIP_CXD56_CRG_H
#ifndef __ARCH_ARM_SRC_CXD56XX_HARDWARE_CXD56_CRG_H
#define __ARCH_ARM_SRC_CXD56XX_HARDWARE_CXD56_CRG_H
/********************************************************************************************
* Included Files

77
arch/arm/src/cxd56xx/hardware/cxd56_dmac_common.h
View file

@ -1,77 +0,0 @@
/****************************************************************************
* arch/arm/src/cxd56xx/cxd56_dmac_common.h
*
* Copyright (C) 2009, 2011-2013 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
* Copyright 2018 Sony Semiconductor Solutions Corporation
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_CXD56XX_CXD56_DMAC_COMMON_H
#define __ARCH_ARM_SRC_CXD56XX_CXD56_DMAC_COMMON_H
#include <stdint.h>
/************************************************************************************
* Public Types
************************************************************************************/
/* DMA_HANDLE provides an opaque are reference that can be used to represent a DMA
* channel.
*/
typedef FAR void *DMA_HANDLE;
/* Description:
* This is the type of the callback that is used to inform the user of the the
* completion of the DMA.
*
* Input Parameters:
* handle - Refers tot he DMA channel or stream
* status - A bit encoded value that provides the completion status. See the
* DMASTATUS_* definitions above.
* arg - A user-provided value that was provided when cxd56_dmastart() was
* called.
*/
typedef void (*dma_callback_t)(DMA_HANDLE handle, uint8_t status, void *arg);
/* Type of 'config' argument passed to cxd56_rxdmasetup() and cxd56_txdmasetup.
* See CXD56_DMA_* encodings above. If these encodings exceed 16-bits, then this
* should be changed to a uint32_t.
*/
typedef struct {
uint16_t channel_cfg;
uint8_t dest_width;
uint8_t src_width;
} dma_config_t;
#endif /* __ARCH_ARM_SRC_CXD56XX_CXD56_DMAC_COMMON_H */

6
arch/arm/src/cxd56xx/hardware/cxd56_emmc.h
View file

@ -33,8 +33,8 @@
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_CXD56XX_CHIP_CXD56_EMMC_H
#define __ARCH_ARM_SRC_CXD56XX_CHIP_CXD56_EMMC_H
#ifndef __ARCH_ARM_SRC_CXD56XX_HARDWARE_CXD56_EMMC_H
#define __ARCH_ARM_SRC_CXD56XX_HARDWARE_CXD56_EMMC_H
#define EMMC_CTRL (CXD56_EMMC_BASE + 0x00u)
#define EMMC_PWREN (CXD56_EMMC_BASE + 0x04u)
@ -343,4 +343,4 @@
#define EXTCSD_PON_POWERED_ON (0x01u)
#define EXTCSD_PON_POWERED_OFF_LONG (0x03u)
#endif /* __ARCH_ARM_SRC_CXD56XX_CHIP_CXD56_EMMC_H */
#endif /* __ARCH_ARM_SRC_CXD56XX_HARDWARE_CXD56_EMMC_H */

6
arch/arm/src/cxd56xx/hardware/cxd56_ge2d.h
View file

@ -33,8 +33,8 @@
*
****************************************************************************/
#ifndef __SRC_CHIP_CXD56_GE2D_H
#define __SRC_CHIP_CXD56_GE2D_H
#ifndef __ARCH_ARM_SRC_CXD56XX_CXD56_GE2D_H
#define __ARCH_ARM_SRC_CXD56XX_CXD56_GE2D_H
#include "hardware/cxd5602_memorymap.h"
@ -79,4 +79,4 @@
#define GE2D_EXEC 1
#define GE2D_STOP 3
#endif /* __SRC_CHIP_CXD56_GE2D_H */
#endif /* __ARCH_ARM_SRC_CXD56XX_CXD56_GE2D_H */

6
arch/arm/src/cxd56xx/hardware/cxd56_i2c.h
View file

@ -33,8 +33,8 @@
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_CXD56XX_CHIP_CXD56_I2C_H
#define __ARCH_ARM_SRC_CXD56XX_CHIP_CXD56_I2C_H
#ifndef __ARCH_ARM_SRC_CXD56XX_HARDWARE_CXD56_I2C_H
#define __ARCH_ARM_SRC_CXD56XX_HARDWARE_CXD56_I2C_H
/****************************************************************************
* Included Files
@ -206,4 +206,4 @@
* Public Functions
****************************************************************************/
#endif /* __ARCH_ARM_SRC_CXD56XX_CHIP_CXD56_I2C_H */
#endif /* __ARCH_ARM_SRC_CXD56XX_HARDWARE_CXD56_I2C_H */

6
arch/arm/src/cxd56xx/hardware/cxd56_rtc.h
View file

@ -33,8 +33,8 @@
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_CXD56XX_CHIP_CXD56_RTC_H
#define __ARCH_ARM_SRC_CXD56XX_CHIP_CXD56_RTC_H
#ifndef __ARCH_ARM_SRC_CXD56XX_HARDWARE_CXD56_RTC_H
#define __ARCH_ARM_SRC_CXD56XX_HARDWARE_CXD56_RTC_H
/****************************************************************************************
* Included Files
@ -137,4 +137,4 @@
#define RTCREG_ALM_ERRDBG_MASK (1u << 31)
#endif /* __ARCH_ARM_SRC_CXD56XX_CHIP_CXD56_RTC_H */
#endif /* __ARCH_ARM_SRC_CXD56XX_HARDWARE_CXD56_RTC_H */

6
arch/arm/src/cxd56xx/hardware/cxd56_scu.h
View file

@ -33,8 +33,8 @@
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_CXD56XX_CHIP_CXD56_SCU_H
#define __ARCH_ARM_SRC_CXD56XX_CHIP_CXD56_SCU_H
#ifndef __ARCH_ARM_SRC_CXD56XX_HARDWARE_CXD56_SCU_H
#define __ARCH_ARM_SRC_CXD56XX_HARDWARE_CXD56_SCU_H
#define SCU_PWM0_PARAM (CXD56_SCU_BASE + 0x0000)
#define SCU_PWM0_EN (CXD56_SCU_BASE + 0x0004)
@ -194,4 +194,4 @@
#define SCU_INT_MASKED_STT_ERR_2 (CXD56_SCU_BASE + 0x0470)
#define SCU_RAM_TEST (CXD56_SCU_BASE + 0x0500)
#endif /* __ARCH_ARM_SRC_CXD56XX_CHIP_CXD56_SCU_H */
#endif /* __ARCH_ARM_SRC_CXD56XX_HARDWARE_CXD56_SCU_H */

6
arch/arm/src/cxd56xx/hardware/cxd56_scufifo.h
View file

@ -33,8 +33,8 @@
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_CXD56XX_CHIP_CXD56_SCUFIFO_H
#define __ARCH_ARM_SRC_CXD56XX_CHIP_CXD56_SCUFIFO_H
#ifndef __ARCH_ARM_SRC_CXD56XX_HARDWARE_CXD56_SCUFIFO_H
#define __ARCH_ARM_SRC_CXD56XX_HARDWARE_CXD56_SCUFIFO_H
#define SCUFIFO_R_CTRL0(fn) (((fn) * 0x20) + SCUFIFO_D0_R1_C_CTRL0)
#define SCUFIFO_R_CTRL1(fn) (((fn) * 0x20) + SCUFIFO_D0_R1_C_CTRL1)
@ -422,4 +422,4 @@
#define SCUFIFO_FIFO_DATA(x) (CXD56_SCU_FIFO_REG_BASE + 0x2100 + (0x4 * (x)))
#endif /* __ARCH_ARM_SRC_CXD56XX_CHIP_CXD56_SCUFIFO_H */
#endif /* __ARCH_ARM_SRC_CXD56XX_HARDWARE_CXD56_SCUFIFO_H */

6
arch/arm/src/cxd56xx/hardware/cxd56_scuseq.h
View file

@ -33,8 +33,8 @@
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_CXD56XX_CHIP_CXD56_SCUSEQ_H
#define __ARCH_ARM_SRC_CXD56XX_CHIP_CXD56_SCUSEQ_H
#ifndef __ARCH_ARM_SRC_CXD56XX_HARDWARE_CXD56_SCUSEQ_H
#define __ARCH_ARM_SRC_CXD56XX_HARDWARE_CXD56_SCUSEQ_H
#define SCUSEQ_SRC_SEL (CXD56_SCU_SEQ_DRAM_BASE + 0x00c)
#define SCUSEQ_PROPERTY(s) (CXD56_SCU_SEQ_DRAM_BASE + 0x020 + ((s) * 0x20))
@ -52,4 +52,4 @@
#define SCUSEQ_SYNCRO_ISOP2CPU (CXD56_SCU_SEQ_DRAM_BASE + 0x2C8)
#define SCUSEQ_RAM_OUT_DATA0 (CXD56_SCU_SEQ_DRAM_BASE + 0x2CC)
#endif /* __ARCH_ARM_SRC_CXD56XX_CHIP_CXD56_SCUSEQ_H */
#endif /* __ARCH_ARM_SRC_CXD56XX_HARDWARE_CXD56_SCUSEQ_H */

2
arch/arm/src/cxd56xx/hardware/cxd56_sph.h
View file

@ -67,4 +67,4 @@
#define LOCK_OWNER(sts) (((sts) >> 16) & 0x1f)
#define RESV_OWNER(sts) (((sts) >> 24) & 0x1f)
#endif
#endif /* __ARCH_ARM_SRC_CXD56XX_HARDWARE_CXD56_SPH_H */

6
arch/arm/src/cxd56xx/hardware/cxd56_spi.h
View file

@ -34,8 +34,8 @@
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_CXD56XX_CHIP_CXD56_SPI_H
#define __ARCH_ARM_SRC_CXD56XX_CHIP_CXD56_SPI_H
#ifndef __ARCH_ARM_SRC_CXD56XX_HARDWARE_CXD56_SPI_H
#define __ARCH_ARM_SRC_CXD56XX_HARDWARE_CXD56_SPI_H
/****************************************************************************
* Included Files
@ -208,4 +208,4 @@
* Public Functions
****************************************************************************/
#endif /* __ARCH_ARM_SRC_CXD56XX_CHIP_CXD56_SPI_H */
#endif /* __ARCH_ARM_SRC_CXD56XX_HARDWARE_CXD56_SPI_H */

6
arch/arm/src/cxd56xx/hardware/cxd56_timer.h
View file

@ -33,8 +33,8 @@
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_CXD56XX_CHIP_CXD56_TIMER_H
#define __ARCH_ARM_SRC_CXD56XX_CHIP_CXD56_TIMER_H
#ifndef __ARCH_ARM_SRC_CXD56XX_HARDWARE_CXD56_TIMER_H
#define __ARCH_ARM_SRC_CXD56XX_HARDWARE_CXD56_TIMER_H
/****************************************************************************************
* Included Files
@ -114,4 +114,4 @@
* Public Functions
****************************************************************************************/
#endif /* __ARCH_ARM_SRC_CXD56XX_CHIP_CXD56_TIMER_H */
#endif /* __ARCH_ARM_SRC_CXD56XX_HARDWARE_CXD56_TIMER_H */

6
arch/arm/src/cxd56xx/hardware/cxd56_udmac.h
View file

@ -33,8 +33,8 @@
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_CXD56XX_CHIP_CXD56_UDMAC_H
#define __ARCH_ARM_SRC_CXD56XX_CHIP_CXD56_UDMAC_H
#ifndef __ARCH_ARM_SRC_CXD56XX_HARDWARE_CXD56_UDMAC_H
#define __ARCH_ARM_SRC_CXD56XX_HARDWARE_CXD56_UDMAC_H
/****************************************************************************
* Included Files
@ -163,4 +163,4 @@ struct dma_descriptor_s {
* Public Functions
****************************************************************************/
#endif /* __ARCH_ARM_SRC_CXD56XX_CHIP_CXD56_UDMAC_H */
#endif /* __ARCH_ARM_SRC_CXD56XX_HARDWARE_CXD56_UDMAC_H */

6
arch/arm/src/cxd56xx/hardware/cxd56_wdt.h
View file

@ -33,8 +33,8 @@
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_CXD56XX_CHIP_CXD56_WDT_H
#define __ARCH_ARM_SRC_CXD56XX_CHIP_CXD56_WDT_H
#ifndef __ARCH_ARM_SRC_CXD56XX_HARDWARE_CXD56_WDT_H
#define __ARCH_ARM_SRC_CXD56XX_HARDWARE_CXD56_WDT_H
/****************************************************************************************
* Included Files
@ -105,4 +105,4 @@
* Public Functions
****************************************************************************************/
#endif /* __ARCH_ARM_SRC_CXD56XX_CHIP_CXD56_WDT_H */
#endif /* __ARCH_ARM_SRC_CXD56XX_HARDWARE_CXD56_WDT_H */

2
boards/arm/cxd56xx/common/src/cxd56_ak09912_i2c.c
View file

@ -1,5 +1,5 @@
/****************************************************************************
* boards/arm/cxd56xx/common/src/cxd56_ak09912.c
* boards/arm/cxd56xx/common/src/cxd56_ak09912_i2c.c
*
* Copyright 2018 Sony Semiconductor Solutions Corporation
*

2
boards/arm/cxd56xx/common/src/cxd56_ak09912_scu.c
View file

@ -1,5 +1,5 @@
/****************************************************************************
* boards/arm/cxd56xx/common/src/cxd56_ak09912.c
* boards/arm/cxd56xx/common/src/cxd56_ak09912_scu.c
*
* Copyright 2018 Sony Semiconductor Solutions Corporation
*

2
boards/arm/cxd56xx/drivers/Make.defs
View file

@ -1,5 +1,5 @@
############################################################################
# drivers/Makefile
# boards/arm/cxd56xx/drivers/Make.defs
#
# Copyright 2018 Sony Semiconductor Solutions Corporation
#

2
boards/arm/cxd56xx/drivers/audio/Make.defs
View file

@ -1,5 +1,5 @@
############################################################################
# drivers/platform/audio/Make.defs
# boards/arm/cxd56xx/drivers/audio/Make.defs
#
# Copyright 2018 Sony Semiconductor Solutions Corporation
#

2
boards/arm/cxd56xx/drivers/audio/cxd56_audio.c
View file

@ -1,5 +1,5 @@
/***************************************************************************
* arch/arm/src/cxd56xx/cxd56_audio.c
* boards/arm/cxd56xx/drivers/audio/cxd56_audio.c
*
* Copyright 2018 Sony Semiconductor Solutions Corporation
*

2
boards/arm/cxd56xx/drivers/audio/cxd56_audio_ac_reg.c
View file

@ -1,5 +1,5 @@
/****************************************************************************
* arch/arm/src/cxd56xx/cxd56_audio_ac_reg.c
* boards/arm/cxd56xx/drivers/audio/cxd56_audio_ac_reg.c
*
* Copyright 2018 Sony Semiconductor Solutions Corporation
*

9
boards/arm/cxd56xx/drivers/audio/cxd56_audio_ac_reg.h
View file

@ -1,5 +1,5 @@
/***************************************************************************
* arch/arm/src/cxd56xx/cxd56_audio_ac_reg.h
* boards/arm/cxd56xx/drivers/audio/cxd56_audio_ac_reg.h
*
* Copyright 2018 Sony Semiconductor Solutions Corporation
*
@ -33,8 +33,8 @@
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_CXD56XX_CXD56_AUDIO_AC_REG_H
#define __ARCH_ARM_SRC_CXD56XX_CXD56_AUDIO_AC_REG_H
#ifndef __BOARDS_ARM_CXD56XX_DRIVERS_AUDIO_CXD56_AUDIO_AC_REG_H
#define __BOARDS_ARM_CXD56XX_DRIVERS_AUDIO_CXD56_AUDIO_AC_REG_H
/***************************************************************************
* Included Files
@ -451,4 +451,5 @@ void cxd56_audio_ac_reg_disable_cstereo(void);
void cxd56_audio_ac_reg_set_vol_sdin1(uint32_t vol);
void cxd56_audio_ac_reg_set_vol_sdin2(uint32_t vol);
void cxd56_audio_ac_reg_set_vol_dac(uint32_t vol);
#endif /* __ARCH_ARM_SRC_CXD56XX_CXD56_AUDIO_AC_REG_H */
#endif /* __BOARDS_ARM_CXD56XX_DRIVERS_AUDIO_CXD56_AUDIO_AC_REG_H */

2
boards/arm/cxd56xx/drivers/audio/cxd56_audio_aca.c
View file

@ -1,5 +1,5 @@
/***************************************************************************
* arch/arm/src/cxd56xx/cxd56_audio_aca.c
* boards/arm/cxd56xx/drivers/audio/cxd56_audio_aca.c
*
* Copyright 2018 Sony Semiconductor Solutions Corporation
*

8
boards/arm/cxd56xx/drivers/audio/cxd56_audio_aca.h
View file

@ -1,5 +1,5 @@
/***************************************************************************
* arch/arm/src/cxd56xx/cxd56_audio_aca.h
* boards/arm/cxd56xx/drivers/audio/cxd56_audio_aca.h
*
* Copyright 2018 Sony Semiconductor Solutions Corporation
*
@ -33,8 +33,8 @@
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_CXD56XX_CXD56_AUDIO_ACA_H
#define __ARCH_ARM_SRC_CXD56XX_CXD56_AUDIO_ACA_H
#ifndef __BOARDS_ARM_CXD56XX_DRIVERS_AUDIO_CXD56_AUDIO_ACA_H
#define __BOARDS_ARM_CXD56XX_DRIVERS_AUDIO_CXD56_AUDIO_ACA_H
/***************************************************************************
* Included Files
@ -80,4 +80,4 @@ CXD56_AUDIO_ECODE cxd56_audio_aca_disable_output(void);
CXD56_AUDIO_ECODE cxd56_audio_aca_set_micgain(FAR cxd56_audio_mic_gain_t *gain);
CXD56_AUDIO_ECODE cxd56_audio_aca_notify_micbootdone(void);
#endif /* __ARCH_ARM_SRC_CXD56XX_CXD56_AUDIO_ACA_H */
#endif /* __BOARDS_ARM_CXD56XX_DRIVERS_AUDIO_CXD56_AUDIO_ACA_H */

2
boards/arm/cxd56xx/drivers/audio/cxd56_audio_analog.c
View file

@ -1,5 +1,5 @@
/****************************************************************************
* arch/arm/src/cxd56xx/cxd56_audio_analog.c
* boards/arm/cxd56xx/drivers/audio/cxd56_audio_analog.c
*
* Copyright 2018 Sony Semiconductor Solutions Corporation
*

8
boards/arm/cxd56xx/drivers/audio/cxd56_audio_analog.h
View file

@ -1,5 +1,5 @@
/***************************************************************************
* arch/arm/src/cxd56xx/cxd56_audio_analog.h
* boards/arm/cxd56xx/drivers/audio/cxd56_audio_analog.h
*
* Copyright 2018 Sony Semiconductor Solutions Corporation
*
@ -33,8 +33,8 @@
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_CXD56XX_CXD56_AUDIO_ANALOG_H
#define __ARCH_ARM_SRC_CXD56XX_CXD56_AUDIO_ANALOG_H
#ifndef __BOARDS_ARM_CXD56XX_DRIVERS_AUDIO_CXD56_AUDIO_ANALOG_H
#define __BOARDS_ARM_CXD56XX_DRIVERS_AUDIO_CXD56_AUDIO_ANALOG_H
/***************************************************************************
* Included Files
@ -73,4 +73,4 @@ CXD56_AUDIO_ECODE cxd56_audio_analog_disable_output(void);
CXD56_AUDIO_ECODE cxd56_audio_analog_set_micgain(FAR cxd56_audio_mic_gain_t *gain);
CXD56_AUDIO_ECODE cxd56_audio_analog_wait_input_standby(void);
#endif /* __ARCH_ARM_SRC_CXD56XX_CXD56_AUDIO_ANALOG_H */
#endif /* __BOARDS_ARM_CXD56XX_DRIVERS_AUDIO_CXD56_AUDIO_ANALOG_H */

2
boards/arm/cxd56xx/drivers/audio/cxd56_audio_bca_reg.c
View file

@ -1,5 +1,5 @@
/***************************************************************************
* arch/arm/src/cxd56xx/cxd56_audio_bca_reg.c
* boards/arm/cxd56xx/drivers/audio/cxd56_audio_bca_reg.c
*
* Copyright 2018 Sony Semiconductor Solutions Corporation
*

8
boards/arm/cxd56xx/drivers/audio/cxd56_audio_bca_reg.h
View file

@ -1,5 +1,5 @@
/***************************************************************************
* arch/arm/src/cxd56xx/cxd56_audio_bca_reg.h
* boards/arm/cxd56xx/drivers/audio/cxd56_audio_bca_reg.h
*
* Copyright 2018 Sony Semiconductor Solutions Corporation
*
@ -33,8 +33,8 @@
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_CXD56XX_CXD56_AUDIO_BCA_REG_H
#define __ARCH_ARM_SRC_CXD56XX_CXD56_AUDIO_BCA_REG_H
#ifndef __BOARDS_ARM_CXD56XX_DRIVERS_AUDIO_CXD56_AUDIO_BCA_REG_H
#define __BOARDS_ARM_CXD56XX_DRIVERS_AUDIO_CXD56_AUDIO_BCA_REG_H
/***************************************************************************
* Included Files
@ -309,4 +309,4 @@ uint32_t cxd56_audio_bca_reg_get_mon_state_buf(cxd56_audio_dma_t handle);
uint32_t cxd56_audio_bca_reg_get_dma_state(cxd56_audio_dma_t handle);
void cxd56_audio_bca_reg_reset_chsel(cxd56_audio_dma_t handle);
#endif /* __ARCH_ARM_SRC_CXD56XX_CXD56_AUDIO_BCA_REG_H */
#endif /* __BOARDS_ARM_CXD56XX_DRIVERS_AUDIO_CXD56_AUDIO_BCA_REG_H */

2
boards/arm/cxd56xx/drivers/audio/cxd56_audio_beep.c
View file

@ -1,5 +1,5 @@
/***************************************************************************
* arch/arm/src/cxd56xx/cxd56_audio_beep.c
* boards/arm/cxd56xx/drivers/audio/cxd56_audio_beep.c
*
* Copyright 2018 Sony Semiconductor Solutions Corporation
*

8
boards/arm/cxd56xx/drivers/audio/cxd56_audio_beep.h
View file

@ -1,5 +1,5 @@
/***************************************************************************
* arch/arm/src/cxd56xx/cxd56_audio_beep.h
* boards/arm/cxd56xx/drivers/audio/cxd56_audio_beep.h
*
* Copyright 2018 Sony Semiconductor Solutions Corporation
*
@ -33,8 +33,8 @@
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_CXD56XX_CXD56_AUDIO_BEEP_H
#define __ARCH_ARM_SRC_CXD56XX_CXD56_AUDIO_BEEP_H
#ifndef __BOARDS_ARM_CXD56XX_DRIVERS_AUDIO_CXD56_AUDIO_BEEP_H
#define __BOARDS_ARM_CXD56XX_DRIVERS_AUDIO_CXD56_AUDIO_BEEP_H
/***************************************************************************
* Included Files
@ -67,4 +67,4 @@ CXD56_AUDIO_ECODE cxd56_audio_beep_set_vol(int16_t vol);
void cxd56_audio_beep_play(void);
void cxd56_audio_beep_stop(void);
#endif /* __ARCH_ARM_SRC_CXD56XX_CXD56_AUDIO_BEEP_H */
#endif /* __BOARDS_ARM_CXD56XX_DRIVERS_AUDIO_CXD56_AUDIO_BEEP_H */

2
boards/arm/cxd56xx/drivers/audio/cxd56_audio_config.c
View file

@ -1,5 +1,5 @@
/***************************************************************************
* arch/arm/src/cxd56xx/cxd56_audio_config.c
* boards/arm/cxd56xx/drivers/audio/cxd56_audio_config.c
*
* Copyright 2018 Sony Semiconductor Solutions Corporation
*

8
boards/arm/cxd56xx/drivers/audio/cxd56_audio_config.h
View file

@ -1,5 +1,5 @@
/***************************************************************************
* arch/arm/src/cxd56xx/cxd56_audio_config.h
* boards/arm/cxd56xx/drivers/audio/cxd56_audio_config.h
*
* Copyright 2018 Sony Semiconductor Solutions Corporation
*
@ -33,8 +33,8 @@
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_CXD56XX_CXD56_AUDIO_CONFIG_H
#define __ARCH_ARM_SRC_CXD56XX_CXD56_AUDIO_CONFIG_H
#ifndef __BOARDS_ARM_CXD56XX_DRIVERS_AUDIO_CXD56_AUDIO_CONFIG_H
#define __BOARDS_ARM_CXD56XX_DRIVERS_AUDIO_CXD56_AUDIO_CONFIG_H
/***************************************************************************
* Included Files
@ -380,4 +380,4 @@ cxd56_audio_clkmode_t cxd56_audio_config_get_clkmode(void);
void cxd56_audio_config_set_micmap(uint32_t map);
uint32_t cxd56_audio_config_get_micmap(void);
#endif /* __ARCH_ARM_SRC_CXD56XX_CXD56_AUDIO_CONFIG_H */
#endif /* __BOARDS_ARM_CXD56XX_DRIVERS_AUDIO_CXD56_AUDIO_CONFIG_H */

2
boards/arm/cxd56xx/drivers/audio/cxd56_audio_digital.c
View file

@ -1,5 +1,5 @@
/***************************************************************************
* arch/arm/src/cxd56xx/cxd56_audio_digital.c
* boards/arm/cxd56xx/drivers/audio/cxd56_audio_digital.c
*
* Copyright 2018 Sony Semiconductor Solutions Corporation
*

8
boards/arm/cxd56xx/drivers/audio/cxd56_audio_digital.h
View file

@ -1,5 +1,5 @@
/***************************************************************************
* arch/arm/src/cxd56xx/cxd56_audio_digital.h
* boards/arm/cxd56xx/drivers/audio/cxd56_audio_digital.h
*
* Copyright 2018 Sony Semiconductor Solutions Corporation
*
@ -33,8 +33,8 @@
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_CXD56XX_CXD56_AUDIO_DIGITAL_H
#define __ARCH_ARM_SRC_CXD56XX_CXD56_AUDIO_DIGITAL_H
#ifndef __BOARDS_ARM_CXD56XX_DRIVERS_AUDIO_CXD56_AUDIO_DIGITAL_H
#define __BOARDS_ARM_CXD56XX_DRIVERS_AUDIO_CXD56_AUDIO_DIGITAL_H
/***************************************************************************
* Included Files
@ -65,4 +65,4 @@
void cxd56_audio_digital_poweron(void);
void cxd56_audio_digital_enable(void);
#endif /* __ARCH_ARM_SRC_CXD56XX_CXD56_AUDIO_DIGITAL_H */
#endif /* __BOARDS_ARM_CXD56XX_DRIVERS_AUDIO_CXD56_AUDIO_DIGITAL_H */

2
boards/arm/cxd56xx/drivers/audio/cxd56_audio_dma.c
View file

@ -1,5 +1,5 @@
/***************************************************************************
* arch/arm/src/cxd56xx/cxd56_audio_dma.c
* boards/arm/cxd56xx/drivers/audio/cxd56_audio_dma.c
*
* Copyright 2018 Sony Semiconductor Solutions Corporation
*

9
boards/arm/cxd56xx/drivers/audio/cxd56_audio_dma.h
View file

@ -1,5 +1,5 @@
/***************************************************************************
* arch/arm/src/cxd56xx/cxd56_audio_dma.h
* boards/arm/cxd56xx/drivers/audio/cxd56_audio_dma.h
*
* Copyright 2018 Sony Semiconductor Solutions Corporation
*
@ -33,8 +33,8 @@
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_CXD56XX_CXD56_AUDIO_DMA_H
#define __ARCH_ARM_SRC_CXD56XX_CXD56_AUDIO_DMA_H
#ifndef __BOARDS_ARM_CXD56XX_DRIVERS_AUDIO_CXD56_AUDIO_DMA_H
#define __BOARDS_ARM_CXD56XX_DRIVERS_AUDIO_CXD56_AUDIO_DMA_H
/***************************************************************************
* Included Files
@ -78,4 +78,5 @@ CXD56_AUDIO_ECODE cxd56_audio_dma_start(cxd56_audio_dma_t handle,
uint32_t addr,
uint32_t sample);
CXD56_AUDIO_ECODE cxd56_audio_dma_stop(cxd56_audio_dma_t handle);
#endif /* __ARCH_ARM_SRC_CXD56XX_CXD56_AUDIO_DMA_H */
#endif /* __BOARDS_ARM_CXD56XX_DRIVERS_AUDIO_CXD56_AUDIO_DMA_H */

2
boards/arm/cxd56xx/drivers/audio/cxd56_audio_filter.c
View file

@ -1,5 +1,5 @@
/***************************************************************************
* arch/arm/src/cxd56xx/cxd56_audio_filter.c
* boards/arm/cxd56xx/drivers/audio/cxd56_audio_filter.c
*
* Copyright 2018 Sony Semiconductor Solutions Corporation
*

8
boards/arm/cxd56xx/drivers/audio/cxd56_audio_filter.h
View file

@ -1,5 +1,5 @@
/***************************************************************************
* arch/arm/src/cxd56xx/cxd56_audio_filter.h
* boards/arm/cxd56xx/drivers/audio/cxd56_audio_filter.h
*
* Copyright 2018 Sony Semiconductor Solutions Corporation
*
@ -33,8 +33,8 @@
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_CXD56XX_CXD56_AUDIO_FILTER_H
#define __ARCH_ARM_SRC_CXD56XX_CXD56_AUDIO_FILTER_H
#ifndef __BOARDS_ARM_CXD56XX_DRIVERS_AUDIO_CXD56_AUDIO_FILTER_H
#define __BOARDS_ARM_CXD56XX_DRIVERS_AUDIO_CXD56_AUDIO_FILTER_H
/***************************************************************************
* Included Files
@ -73,4 +73,4 @@ void cxd56_audio_filter_set_dnc(cxd56_audio_dnc_id_t id,
void cxd56_audio_filter_set_deq(bool en,
FAR cxd56_audio_deq_coef_t *deq);
#endif /* __ARCH_ARM_SRC_CXD56XX_CXD56_AUDIO_FILTER_H */
#endif /* __BOARDS_ARM_CXD56XX_DRIVERS_AUDIO_CXD56_AUDIO_FILTER_H */

2
boards/arm/cxd56xx/drivers/audio/cxd56_audio_irq.c
View file

@ -1,5 +1,5 @@
/***************************************************************************
* arch/arm/src/cxd56xx/cxd56_audio_irq.c
* boards/arm/cxd56xx/drivers/audio/cxd56_audio_irq.c
*
* Copyright 2018 Sony Semiconductor Solutions Corporation
*

8
boards/arm/cxd56xx/drivers/audio/cxd56_audio_irq.h
View file

@ -1,5 +1,5 @@
/***************************************************************************
* arch/arm/src/cxd56xx/cxd56_audio_irq.h
* boards/arm/cxd56xx/drivers/audio/cxd56_audio_irq.h
*
* Copyright 2018 Sony Semiconductor Solutions Corporation
*
@ -33,8 +33,8 @@
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_CXD56XX_CXD56_AUDIO_IRQ_H
#define __ARCH_ARM_SRC_CXD56XX_CXD56_AUDIO_IRQ_H
#ifndef __BOARDS_ARM_CXD56XX_DRIVERS_AUDIO_CXD56_AUDIO_IRQ_H
#define __BOARDS_ARM_CXD56XX_DRIVERS_AUDIO_CXD56_AUDIO_IRQ_H
/***************************************************************************
* Included Files
@ -67,4 +67,4 @@ void cxd56_audio_irq_detach(void);
void cxd56_audio_irq_enable(void);
void cxd56_audio_irq_disable(void);
#endif /* __ARCH_ARM_SRC_CXD56XX_CXD56_AUDIO_IRQ_H */
#endif /* __BOARDS_ARM_CXD56XX_DRIVERS_AUDIO_CXD56_AUDIO_IRQ_H */

2
boards/arm/cxd56xx/drivers/audio/cxd56_audio_mic.c
View file

@ -1,5 +1,5 @@
/***************************************************************************
* arch/arm/src/cxd56xx/cxd56_audio_mic.c
* boards/arm/cxd56xx/drivers/audio/cxd56_audio_mic.c
*
* Copyright 2018 Sony Semiconductor Solutions Corporation
*

8
boards/arm/cxd56xx/drivers/audio/cxd56_audio_mic.h
View file

@ -1,5 +1,5 @@
/***************************************************************************
* arch/arm/src/cxd56xx/cxd56_audio_mic.h
* boards/arm/cxd56xx/drivers/audio/cxd56_audio_mic.h
*
* Copyright 2018 Sony Semiconductor Solutions Corporation
*
@ -33,8 +33,8 @@
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_CXD56XX_CXD56_AUDIO_MIC_H
#define __ARCH_ARM_SRC_CXD56XX_CXD56_AUDIO_MIC_H
#ifndef __BOARDS_ARM_CXD56XX_DRIVERS_AUDIO_CXD56_AUDIO_MIC_H
#define __BOARDS_ARM_CXD56XX_DRIVERS_AUDIO_CXD56_AUDIO_MIC_H
/***************************************************************************
* Included Files
@ -68,4 +68,4 @@ CXD56_AUDIO_ECODE cxd56_audio_mic_set_gain(FAR cxd56_audio_mic_gain_t *gain);
CXD56_AUDIO_ECODE cxd56_audio_mic_set_seloutch(uint8_t mic_num,
cxd56_audio_samp_fmt_t format);
#endif /* __ARCH_ARM_SRC_CXD56XX_CXD56_AUDIO_MIC_H */
#endif /* __BOARDS_ARM_CXD56XX_DRIVERS_AUDIO_CXD56_AUDIO_MIC_H */

2
boards/arm/cxd56xx/drivers/audio/cxd56_audio_pin.c
View file

@ -1,5 +1,5 @@
/***************************************************************************
* arch/arm/src/cxd56xx/cxd56_audio_pin.c
* boards/arm/cxd56xx/drivers/audio/cxd56_audio_pin.c
*
* Copyright 2018 Sony Semiconductor Solutions Corporation
*

8
boards/arm/cxd56xx/drivers/audio/cxd56_audio_pin.h
View file

@ -1,5 +1,5 @@
/***************************************************************************
* arch/arm/src/cxd56xx/cxd56_audio_pin.h
* boards/arm/cxd56xx/drivers/audio/cxd56_audio_pin.h
*
* Copyright 2018 Sony Semiconductor Solutions Corporation
*
@ -33,8 +33,8 @@
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_CXD56XX_CXD56_AUDIO_PIN_H
#define __ARCH_ARM_SRC_CXD56XX_CXD56_AUDIO_PIN_H
#ifndef __BOARDS_ARM_CXD56XX_DRIVERS_AUDIO_CXD56_AUDIO_PIN_H
#define __BOARDS_ARM_CXD56XX_DRIVERS_AUDIO_CXD56_AUDIO_PIN_H
/***************************************************************************
* Included Files
@ -65,4 +65,4 @@
void cxd56_audio_pin_i2s_set(void);
void cxd56_audio_pin_i2s_unset(void);
#endif /* __ARCH_ARM_SRC_CXD56XX_CXD56_AUDIO_PIN_H */
#endif /* __BOARDS_ARM_CXD56XX_DRIVERS_AUDIO_CXD56_AUDIO_PIN_H */

2
boards/arm/cxd56xx/drivers/audio/cxd56_audio_power.c
View file

@ -1,5 +1,5 @@
/***************************************************************************
* arch/arm/src/cxd56xx/cxd56_audio_power.c
* boards/arm/cxd56xx/drivers/audio/cxd56_audio_power.c
*
* Copyright 2018 Sony Semiconductor Solutions Corporation
*

8
boards/arm/cxd56xx/drivers/audio/cxd56_audio_power.h
View file

@ -1,5 +1,5 @@
/***************************************************************************
* arch/arm/src/cxd56xx/cxd56_audio_power.h
* boards/arm/cxd56xx/drivers/audio/cxd56_audio_power.h
*
* Copyright 2018 Sony Semiconductor Solutions Corporation
*
@ -33,8 +33,8 @@
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_CXD56XX_CXD56_AUDIO_POWER_H
#define __ARCH_ARM_SRC_CXD56XX_CXD56_AUDIO_POWER_H
#ifndef __BOARDS_ARM_CXD56XX_DRIVERS_AUDIO_CXD56_AUDIO_POWER_H
#define __BOARDS_ARM_CXD56XX_DRIVERS_AUDIO_CXD56_AUDIO_POWER_H
/***************************************************************************
* Included Files
@ -65,4 +65,4 @@
CXD56_AUDIO_ECODE cxd56_audio_power_on(void);
CXD56_AUDIO_ECODE cxd56_audio_power_off(void);
#endif /* __ARCH_ARM_SRC_CXD56XX_CXD56_AUDIO_POWER_H */
#endif /* __BOARDS_ARM_CXD56XX_DRIVERS_AUDIO_CXD56_AUDIO_POWER_H */

2
boards/arm/cxd56xx/drivers/audio/cxd56_audio_volume.c
View file

@ -1,5 +1,5 @@
/****************************************************************************
* arch/arm/src/cxd56xx/cxd56_audio_volume.c
* boards/arm/cxd56xx/drivers/audio/cxd56_audio_volume.c
*
* Copyright 2018 Sony Semiconductor Solutions Corporation
*

9
boards/arm/cxd56xx/drivers/audio/cxd56_audio_volume.h
View file

@ -1,5 +1,5 @@
/***************************************************************************
* arch/arm/src/cxd56xx/cxd56_audio_volume.h
* boards/arm/cxd56xx/drivers/audio/cxd56_audio_volume.h
*
* Copyright 2018 Sony Semiconductor Solutions Corporation
*
@ -33,8 +33,8 @@
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_CXD56XX_CXD56_AUDIO_VOLUME_H
#define __ARCH_ARM_SRC_CXD56XX_CXD56_AUDIO_VOLUME_H
#ifndef __BOARDS_ARM_CXD56XX_DRIVERS_AUDIO_CXD56_AUDIO_VOLUME_H
#define __BOARDS_ARM_CXD56XX_DRIVERS_AUDIO_CXD56_AUDIO_VOLUME_H
/***************************************************************************
* Included Files
@ -69,4 +69,5 @@ CXD56_AUDIO_ECODE cxd56_audio_volume_mute_fade(cxd56_audio_volid_t id,
bool wait);
CXD56_AUDIO_ECODE cxd56_audio_volume_unmute_fade(cxd56_audio_volid_t id,
bool wait);
#endif /* __ARCH_ARM_SRC_CXD56XX_CXD56_AUDIO_VOLUME_H */
#endif /* __BOARDS_ARM_CXD56XX_DRIVERS_AUDIO_CXD56_AUDIO_VOLUME_H */

2
boards/arm/cxd56xx/drivers/sensors/Make.defs
View file

@ -1,5 +1,5 @@
############################################################################
# drivers/platform/sensors/Make.defs
# boards/arm/cxd56xx/drivers/sensors/Make.defs
#
# Copyright 2018 Sony Semiconductor Solutions Corporation
#

2
boards/arm/cxd56xx/drivers/sensors/ak09912_scu.c
View file

@ -1,5 +1,5 @@
/****************************************************************************
* drivers/platform/sensors/ak09912_scu.c
* boards/arm/cxd56xx/drivers/sensors/ak09912_scu.c
*
* Copyright 2018 Sony Semiconductor Solutions Corporation
*

2
boards/arm/cxd56xx/drivers/sensors/apds9930_scu.c
View file

@ -1,5 +1,5 @@
/****************************************************************************
* drivers/platform/sensors/apds9930_scu.c
* boards/arm/cxd56xx/drivers/sensors/apds9930_scu.c
*
* Copyright 2018 Sony Semiconductor Solutions Corporation
*

2
boards/arm/cxd56xx/drivers/sensors/bh1721fvc_scu.c
View file

@ -1,5 +1,5 @@
/****************************************************************************
* drivers/platform/sensors/bh1721fvc_scu.c
* boards/arm/cxd56xx/drivers/sensors/bh1721fvc_scu.c
*
* Copyright 2018 Sony Semiconductor Solutions Corporation
*

2
boards/arm/cxd56xx/drivers/sensors/bh1745nuc_scu.c
View file

@ -1,5 +1,5 @@
/****************************************************************************
* drivers/platform/sensors/bh1745nuc_scu.c
* boards/arm/cxd56xx/drivers/sensors/bh1745nuc_scu.c
*
* Copyright 2018 Sony Semiconductor Solutions Corporation
*

2
boards/arm/cxd56xx/drivers/sensors/bm1383glv_scu.c
View file

@ -1,5 +1,5 @@
/****************************************************************************
* drivers/platform/sensors/bm1383glv_scu.c
* boards/arm/cxd56xx/drivers/sensors/bm1383glv_scu.c
*
* Copyright 2018 Sony Semiconductor Solutions Corporation
*

2
boards/arm/cxd56xx/drivers/sensors/bm1422gmv_scu.c
View file

@ -1,5 +1,5 @@
/****************************************************************************
* drivers/platform/sensors/bm1422gmv_scu.c
* boards/arm/cxd56xx/drivers/sensors/bm1422gmv_scu.c
*
* Copyright 2018 Sony Semiconductor Solutions Corporation
*

2
boards/arm/cxd56xx/drivers/sensors/bmi160_scu.c
View file

@ -1,5 +1,5 @@
/****************************************************************************
* drivers/platform/sensors/bmi160_scu.c
* boards/arm/cxd56xx/drivers/sensors/bmi160_scu.c
*
* Copyright 2018 Sony Semiconductor Solutions Corporation
*

2
boards/arm/cxd56xx/drivers/sensors/bmp280_scu.c
View file

@ -1,5 +1,5 @@
/****************************************************************************
* drivers/platform/sensors/bmp280_scu.c
* boards/arm/cxd56xx/drivers/sensors/bmp280_scu.c
*
* Copyright 2018 Sony Semiconductor Solutions Corporation
*

2
boards/arm/cxd56xx/drivers/sensors/kx022_scu.c
View file

@ -1,5 +1,5 @@
/****************************************************************************
* drivers/platform/sensors/kx022_scu.c
* boards/arm/cxd56xx/drivers/sensors/kx022_scu.c
*
* Copyright 2018 Sony Semiconductor Solutions Corporation
*

2
boards/arm/cxd56xx/drivers/sensors/lt1pa01_scu.c
View file

@ -1,5 +1,5 @@
/****************************************************************************
* drivers/platform/sensors/lt1pa01_scu.c
* boards/arm/cxd56xx/drivers/sensors/lt1pa01_scu.c
*
* Copyright 2018 Sony Semiconductor Solutions Corporation
*

2
boards/arm/cxd56xx/drivers/sensors/rpr0521rs_scu.c
View file

@ -1,5 +1,5 @@
/****************************************************************************
* drivers/sensors/rpr0521rs_scu.c
* boards/arm/cxd56xx/drivers/sensors/rpr0521rs_scu.c
*
* Copyright 2018 Sony Semiconductor Solutions Corporation
*

6
boards/arm/cxd56xx/spresense/include/board_pinconfig.h
View file

@ -33,8 +33,8 @@
*
****************************************************************************/
#ifndef __BOARDS_ARM_CXD56XX_SPRESENCE_INCLUDE_BOARD_PINCONFIG_H
#define __BOARDS_ARM_CXD56XX_SPRESENCE_INCLUDE_BOARD_PINCONFIG_H
#ifndef __BOARDS_ARM_CXD56XX_SPRESENSE_INCLUDE_BOARD_PINCONFIG_H
#define __BOARDS_ARM_CXD56XX_SPRESENSE_INCLUDE_BOARD_PINCONFIG_H
/****************************************************************************
* Included Files
@ -99,4 +99,4 @@
#undef PINCONF_SDIO_CD_GPIO
#define PINCONF_SDIO_CD_GPIO PINCONF(PIN_SDIO_CD, 0, 0, 0, PINCONF_PULLUP)
#endif /* __BOARDS_ARM_CXD56XX_SPRESENCE_INCLUDE_BOARD_PINCONFIG_H */
#endif /* __BOARDS_ARM_CXD56XX_SPRESENSE_INCLUDE_BOARD_PINCONFIG_H */

1
boards/arm/cxd56xx/spresense/include/cxd56_bh1721fvc.h
View file

@ -72,6 +72,7 @@ extern "C"
* Initialize BH1721FVC i2c driver and register the BH1721FVC device.
*
****************************************************************************/
#if defined(CONFIG_SENSORS_BH1721FVC) || defined(CONFIG_SENSORS_BH1721FVC_SCU)
int board_bh1721fvc_initialize(FAR const char *devpath, int bus);
#endif

8
boards/arm/cxd56xx/spresense/include/cxd56_bmp280.h
View file

@ -1,5 +1,5 @@
/****************************************************************************
* board/arm/cxd56xx/spresense/include/cxd56_bmp280.h
* boards/arm/cxd56xx/spresense/include/cxd56_bmp280.h
*
* Copyright 2018 Sony Semiconductor Solutions Corporation
*
@ -33,8 +33,8 @@
*
****************************************************************************/
#ifndef __BOARDS_ARM_CXD56X_SPRESENSE_INCLUDE_CXD56_BMP280_H
#define __BOARDS_ARM_CXD56X_SPRESENSE_INCLUDE_CXD56_BMP280_H
#ifndef __BOARDS_ARM_CXD56XX_SPRESENSE_INCLUDE_CXD56_BMP280_H
#define __BOARDS_ARM_CXD56XX_SPRESENSE_INCLUDE_CXD56_BMP280_H
/****************************************************************************
* Included Files
@ -83,4 +83,4 @@ int board_bmp280_initialize(int bus);
#endif
#endif /* __ASSEMBLY__ */
#endif /* __BOARDS_ARM_CX56XX_SPRESENSE_INCLUDE_CXD56_BMP280_H */
#endif /* __BOARDS_ARM_CXD56XX_SPRESENSE_INCLUDE_CXD56_BMP280_H */

6
boards/arm/cxd56xx/spresense/include/cxd56_gs2200m.h
View file

@ -34,8 +34,8 @@
*
****************************************************************************/
#ifndef __BOARDS_ARM_SPRESENSE_INCLUDE_CXD56_GS2200M_H
#define __BOARDS_ARM_SPRESENSE_INCLUDE_CXD56_GS2200M_H
#ifndef __BOARDS_ARM_CXD56XX_SPRESENSE_INCLUDE_CXD56_GS2200M_H
#define __BOARDS_ARM_CXD56XX_SPRESENSE_INCLUDE_CXD56_GS2200M_H
/****************************************************************************
* Included Files
@ -82,4 +82,4 @@ int board_gs2200m_initialize(FAR const char *devpath, int bus);
#endif
#endif /* __ASSEMBLY__ */
#endif /* __BOARDS_ARM_SPRESENSE_INCLUDE_CXD56_GS2200M_H */
#endif /* __BOARDS_ARM_CXD56XX_SPRESENSE_INCLUDE_CXD56_GS2200M_H */

8
boards/arm/cxd56xx/spresense/include/cxd56_imageproc.h
View file

@ -1,5 +1,5 @@
/***************************************************************************
* boards/arm/cxd56xx/include/cxd56_imageproc.h
* boards/arm/cxd56xx/spresense/include/cxd56_imageproc.h
*
* Copyright 2018 Sony Semiconductor Solutions Corporation
*
@ -32,8 +32,8 @@
*
****************************************************************************/
#ifndef __BOARDS_ARM_CXD56XX_INCLUDE_CXD56_IMAGEPROC_H__
#define __BOARDS_ARM_CXD56XX_INCLUDE_CXD56_IMAGEPROC_H__
#ifndef __BOARDS_ARM_CXD56XX_SPRESENSE_INCLUDE_CXD56_IMAGEPROC_H
#define __BOARDS_ARM_CXD56XX_SPRESENSE_INCLUDE_CXD56_IMAGEPROC_H
#include <stdint.h>
@ -148,4 +148,4 @@ extern "C"
}
#endif
#endif /* __BOARDS_ARM_CXD56XX_INCLUDE_CXD56_IMAGEPROC_H__ */
#endif /* __BOARDS_ARM_CXD56XX_SPRESENSE_INCLUDE_CXD56_IMAGEPROC_H */

2
boards/arm/cxd56xx/spresense/include/cxd56_kx022.h
View file

@ -83,4 +83,4 @@ int board_kx022_initialize(FAR const char *devpath, int bus);
#endif
#endif /* __ASSEMBLY__ */
#endif /* __BOARDS_ARM_CXD56XX_SENSORS_INCLUDE_CXD56_KX022_H */
#endif /* __BOARDS_ARM_CXD56XX_SPRESENSE_INCLUDE_CXD56_KX022_H */

6
boards/arm/cxd56xx/spresense/include/cxd56_lt1pa01.h
View file

@ -33,8 +33,8 @@
*
****************************************************************************/
#ifndef __BOARDS_ARM_CXD56XX_SPESENSE_INCLUDE_CXD56_LT1PA01_H
#define __BOARDS_ARM_CXD56XX_SPESENSE_INCLUDE_CXD56_LT1PA01_H
#ifndef __BOARDS_ARM_CXD56XX_SPRESENSE_INCLUDE_CXD56_LT1PA01_H
#define __BOARDS_ARM_CXD56XX_SPRESENSE_INCLUDE_CXD56_LT1PA01_H
/****************************************************************************
* Included Files
@ -83,4 +83,4 @@ int board_lt1pa01_initialize(int bus);
#endif
#endif /* __ASSEMBLY__ */
#endif /* __BOARDS_ARM_CXD56XX_SPESENSE_INCLUDE_CXD56_LT1PA01_H */
#endif /* __BOARDS_ARM_CXD56XX_SPRESENSE_INCLUDE_CXD56_LT1PA01_H */

2
boards/arm/cxd56xx/spresense/scripts/Make.defs
View file

@ -1,5 +1,5 @@
############################################################################
# boards/arm/cxd56xx/spresense/nsh/Make.defs
# boards/arm/cxd56xx/spresense/scripts/Make.defs
#
# Copyright (C) 2014 Gregory Nutt. All rights reserved.
# Author: Gregory Nutt <gnutt@nuttx.org>

1
boards/arm/cxd56xx/spresense/src/cxd56_sdcard.c
View file

@ -171,6 +171,7 @@ static void board_sdcard_enable(FAR void *arg)
else
{
_err("ERROR: Failed to mount the SDCARD. %d\n", errno);
goto release_frequency_lock;
}
}
}