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esp32/[ble/wifi]: Update the wireless drivers

Browse source 
This commit updates the Wi-Fi and the BLE driver of ESP32. Most of
the changes rely on using the common sources and header files for
xtensa-based Espressif's SoCs.

The new Wi-Fi driver supports WPA3-SAE for both Station and SoftAP
mode. BLE's coexistence mode was enhanced according to the latest
libraries.

Please note that other sources required minor changes in order to
be compatible with the common sources.
This commit is contained in:
Tiago Medicci Serrano 2024-03-11 10:51:06 -03:00 committed by Xiang Xiao
parent d16bb11b93
commit 09464ff9bc
26 changed files with 3688 additions and 3947 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

85
arch/xtensa/src/common/espressif/utils/memory_reserve.h Normal file
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@ -0,0 +1,85 @@
/****************************************************************************
* arch/xtensa/src/common/espressif/utils/memory_reserve.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#pragma once
/****************************************************************************
* Included Files
****************************************************************************/
#include <stdlib.h>
#include <stdint.h>
#include <stdbool.h>
#include "sdkconfig.h"
#ifdef __cplusplus
extern "C"
{
#endif
/****************************************************************************
* Public Types
****************************************************************************/
/* Region descriptor holds a description for a particular region of
* memory reserved on this SoC for a particular use (ie not available
* for stack/heap usage.)
*/
typedef struct
{
intptr_t start;
intptr_t end;
} soc_reserved_region_t;
/****************************************************************************
* Helper Macros/Inline Functions
****************************************************************************/
/****************************************************************************
* Name: SOC_RESERVE_MEMORY_REGION
*
* Description:
* Macro to reserve a fixed region of RAM (hardcoded addresses) for a
* particular purpose. Usually used to mark out memory addresses needed
* for hardware or ROM code purposes. Not intended for user code which
* can use normal C static allocation instead.
*
* Input Parameters:
* START - Start address to be reserved.
* END - One memory address after the address of the last byte to be
* reserved.
* (ie length of the reserved region is (END - START) in bytes.)
* NAME - Name for the reserved region. Must be a valid variable name,
* unique to this source file.
*
* Returned Value:
* None
*
****************************************************************************/
#define SOC_RESERVE_MEMORY_REGION(START, END, NAME) \
__attribute__((section(".reserved_memory_address"))) \
__attribute__((used)) \
static soc_reserved_region_t reserved_region_##NAME = { START, END };
#ifdef __cplusplus
}
#endif

6
arch/xtensa/src/esp32/Kconfig
View file

@ -99,6 +99,10 @@ config ARCH_CHIP_ESP32PICOD4
endchoice # ESP32 Chip Selection
config ESPRESSIF_CHIP_SERIES
string
default "esp32"
config ESP32_SINGLE_CPU
bool
default n
@ -791,8 +795,10 @@ endmenu # ESP32 Peripheral Selection
config ESP32_WIFI_BT_COEXIST
bool "Wi-Fi and BT coexist"
default y if ESP32_WIFI && ESP32_BLE
default n
depends on ESP32_WIFI && ESP32_BLE
select ESP32_WIFI_STA_DISCONNECT_PM
menu "Interrupt Configuration"

85
arch/xtensa/src/esp32/Make.defs
View file

@ -117,7 +117,6 @@ endif
CHIP_CSRCS += esp32_efuse.c
ifeq ($(CONFIG_ESP32_EFUSE),y)
CHIP_CSRCS += esp32_efuse_table.c
CHIP_CSRCS += esp32_efuse_lowerhalf.c
endif
@ -201,60 +200,6 @@ CHIP_CSRCS += esp32_rtc_lowerhalf.c
endif
endif
ifeq ($(CONFIG_ESP32_WIRELESS),y)
WIRELESS_DRV_UNPACK = esp-wireless-drivers-3rdparty
WIRELESS_DRV_ID = 45701c0
WIRELESS_DRV_ZIP = $(WIRELESS_DRV_ID).zip
WIRELESS_DRV_URL = https://github.com/espressif/esp-wireless-drivers-3rdparty/archive
$(WIRELESS_DRV_ZIP):
$(call DOWNLOAD,$(WIRELESS_DRV_URL),$(WIRELESS_DRV_ZIP),chip/$(WIRELESS_DRV_ZIP))
chip/$(WIRELESS_DRV_UNPACK): $(WIRELESS_DRV_ZIP)
$(Q) echo "Unpacking: ESP Wireless Drivers"
$(Q) unzip -oqq chip/$(WIRELESS_DRV_ZIP) -d chip/
$(Q) mv chip/$(WIRELESS_DRV_UNPACK)-$(WIRELESS_DRV_ID)* chip/$(WIRELESS_DRV_UNPACK)
$(Q) touch chip/$(WIRELESS_DRV_UNPACK)
ifeq ($(wildcard chip/$(WIRELESS_DRV_UNPACK)/.git),)
context:: chip/$(WIRELESS_DRV_UNPACK)
distclean::
$(call DELFILE, chip/$(WIRELESS_DRV_ZIP))
$(call DELDIR, chip/$(WIRELESS_DRV_UNPACK))
endif
INCLUDES += ${INCDIR_PREFIX}$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)esp-wireless-drivers-3rdparty$(DELIM)include
INCLUDES += ${INCDIR_PREFIX}$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)esp-wireless-drivers-3rdparty$(DELIM)include$(DELIM)esp32
EXTRA_LIBPATHS += -L $(ARCH_SRCDIR)$(DELIM)chip$(DELIM)esp-wireless-drivers-3rdparty$(DELIM)libs$(DELIM)esp32
EXTRA_LIBS += -lphy -lrtc
# Wireless interfaces.
CHIP_CSRCS += esp32_wireless.c
endif
ifeq ($(CONFIG_ESP32_WIFI),y)
CHIP_CSRCS += esp32_wlan.c esp32_wifi_utils.c esp32_wifi_adapter.c
EXTRA_LIBS += -lcore -lnet80211 -lpp -lsmartconfig -lespnow -lwpa_supplicant
ifeq ($(GCCVER),)
export GCCVER := $(shell $(CC) --version | grep gcc | sed -E 's/.* ([0-9]+\.[0-9]+).*/\1/' | cut -d'.' -f1)
endif
ifeq ($(GCCVER),12)
chip/esp32_wifi_adapter.c_CFLAGS += -Wno-maybe-uninitialized
endif
endif
ifeq ($(CONFIG_ESP32_BLE),y)
CHIP_CSRCS += esp32_ble_adapter.c esp32_ble.c
EXTRA_LIBS += -lbtdm_app
ifeq ($(CONFIG_ESP32_WIFI_BT_COEXIST),y)
EXTRA_LIBS += -lcoexist
endif
endif
ifeq ($(CONFIG_ESP32_OPENETH),y)
CHIP_CSRCS += esp32_openeth.c
endif
@ -267,11 +212,11 @@ endif
ESP_HAL_3RDPARTY_REPO = esp-hal-3rdparty
ifndef ESP_HAL_3RDPARTY_VERSION
ESP_HAL_3RDPARTY_VERSION = 2fbc8a025275d68833cdfef490377048538de57a
ESP_HAL_3RDPARTY_VERSION = 966f1bbf7d80d3fac9a43f414e864985cbcfd680
endif
ifndef ESP_HAL_3RDPARTY_URL
ESP_HAL_3RDPARTY_URL = https://github.com/espressif/esp-hal-3rdparty.git
ESP_HAL_3RDPARTY_URL = https://github.com/espressif/esp-hal-3rdparty.git
endif
chip/$(ESP_HAL_3RDPARTY_REPO):
@ -284,7 +229,33 @@ chip/$(ESP_HAL_3RDPARTY_REPO):
CFLAGS += -Wno-undef -Wno-unused-variable
# Files that require the HAL recipe
CHIP_SERIES = $(patsubst "%",%,$(CONFIG_ESPRESSIF_CHIP_SERIES))
include chip/Bootloader.mk
include chip/hal.mk
include common/espressif/Make.defs
context:: chip/$(ESP_HAL_3RDPARTY_REPO)
ifeq ($(CONFIG_ESP32_WIRELESS),y)
$(Q) echo "Espressif HAL for 3rd Party Platforms: initializing submodules..."
$(Q) git -C chip/$(ESP_HAL_3RDPARTY_REPO) submodule --quiet update --init --depth=1 components/mbedtls/mbedtls components/esp_phy/lib components/esp_wifi/lib components/bt/controller/lib_esp32 components/esp_coex/lib
$(Q) git -C chip/$(ESP_HAL_3RDPARTY_REPO)/components/mbedtls/mbedtls reset --quiet --hard
$(Q) echo "Applying patches..."
$(Q) cd chip/$(ESP_HAL_3RDPARTY_REPO)/components/mbedtls/mbedtls && git apply ../../../nuttx/patches/components/mbedtls/mbedtls/*.patch
endif
distclean::
$(call DELDIR, chip/$(ESP_HAL_3RDPARTY_REPO))
ifeq ($(CONFIG_ESP32_WIRELESS),y)
include chip/Wireless.mk
endif
distclean::
$(call DELDIR,chip/$(ESP_HAL_3RDPARTY_REPO))
INCLUDES += ${INCDIR_PREFIX}$(ARCH_SRCDIR)$(DELIM)common$(DELIM)espressif

253
arch/xtensa/src/esp32/Wireless.mk Normal file
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@ -0,0 +1,253 @@
############################################################################
# arch/xtensa/src/esp32/Wireless.mk
#
# Licensed to the Apache Software Foundation (ASF) under one or more
# contributor license agreements. See the NOTICE file distributed with
# this work for additional information regarding copyright ownership. The
# ASF licenses this file to you under the Apache License, Version 2.0 (the
# "License"); you may not use this file except in compliance with the
# License. You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
# License for the specific language governing permissions and limitations
# under the License.
#
############################################################################
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bt$(DELIM)include$(DELIM)$(CHIP_SERIES)$(DELIM)include
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_coex$(DELIM)include
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)nuttx$(DELIM)$(CHIP_SERIES)$(DELIM)include
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)nuttx$(DELIM)include$(DELIM)esp_wifi
EXTRA_LIBPATHS += -L $(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bt$(DELIM)controller$(DELIM)lib_esp32$(DELIM)$(CHIP_SERIES)
EXTRA_LIBPATHS += -L $(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_coex$(DELIM)lib$(DELIM)$(CHIP_SERIES)
EXTRA_LIBPATHS += -L $(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_phy$(DELIM)lib$(DELIM)$(CHIP_SERIES)
EXTRA_LIBPATHS += -L $(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_wifi$(DELIM)lib$(DELIM)$(CHIP_SERIES)
EXTRA_LIBS += -lrtc -lphy -lcoexist
# Wireless interfaces.
CHIP_CSRCS += esp32_wireless.c
ifeq ($(CONFIG_ESP32_BLE),y)
CHIP_CSRCS += esp32_ble_adapter.c esp32_ble.c
EXTRA_LIBS += -lbtdm_app
endif
ifeq ($(CONFIG_ESP32_WIFI),y)
CHIP_CSRCS += esp32_wlan.c esp32_wifi_utils.c esp32_wifi_adapter.c
EXTRA_LIBS += -lcore -lnet80211 -lpp
ifeq ($(CONFIG_WPA_WAPI_PSK),y)
EXTRA_LIBS += -lwapi
endif
## ESP-IDF's mbedTLS
VPATH += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)mbedtls$(DELIM)mbedtls$(DELIM)library
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)mbedtls$(DELIM)mbedtls$(DELIM)include
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)mbedtls$(DELIM)mbedtls$(DELIM)library
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)mbedtls$(DELIM)port$(DELIM)include
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)nuttx$(DELIM)include$(DELIM)mbedtls
### Define Espressif's configs for mbedTLS
CFLAGS += $(DEFINE_PREFIX)MBEDTLS_CONFIG_FILE="<mbedtls/esp_config.h>"
CHIP_CSRCS += aes.c
CHIP_CSRCS += aria.c
CHIP_CSRCS += bignum_core.c
CHIP_CSRCS += bignum.c
CHIP_CSRCS += ccm.c
CHIP_CSRCS += cipher_wrap.c
CHIP_CSRCS += cipher.c
CHIP_CSRCS += cmac.c
CHIP_CSRCS += constant_time.c
CHIP_CSRCS += ctr_drbg.c
CHIP_CSRCS += ecp_curves.c
CHIP_CSRCS += ecp.c
CHIP_CSRCS += entropy.c
CHIP_CSRCS += gcm.c
CHIP_CSRCS += md.c
CHIP_CSRCS += pkcs5.c
CHIP_CSRCS += platform_util.c
CHIP_CSRCS += platform.c
CHIP_CSRCS += sha1.c
CHIP_CSRCS += sha256.c
CHIP_CSRCS += sha512.c
CHIP_CSRCS += pk.c
CHIP_CSRCS += pk_wrap.c
CHIP_CSRCS += pkparse.c
CHIP_CSRCS += ecdsa.c
CHIP_CSRCS += asn1parse.c
CHIP_CSRCS += asn1write.c
CHIP_CSRCS += rsa.c
CHIP_CSRCS += md5.c
CHIP_CSRCS += oid.c
CHIP_CSRCS += pem.c
CHIP_CSRCS += hmac_drbg.c
CHIP_CSRCS += hash_info.c
CHIP_CSRCS += rsa_alt_helpers.c
CHIP_CSRCS += ecdh.c
VPATH += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)mbedtls$(DELIM)port
CHIP_CSRCS += esp_hardware.c
CHIP_CSRCS += esp_mem.c
CHIP_CSRCS += esp_timing.c
VPATH += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)mbedtls$(DELIM)port$(DELIM)md
CHIP_CSRCS += esp_md.c
## WPA Supplicant
WIFI_WPA_SUPPLICANT = chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)wpa_supplicant
CFLAGS += $(DEFINE_PREFIX)__ets__
CFLAGS += $(DEFINE_PREFIX)CONFIG_CRYPTO_MBEDTLS
CFLAGS += $(DEFINE_PREFIX)CONFIG_ECC
CFLAGS += $(DEFINE_PREFIX)CONFIG_IEEE80211W
CFLAGS += $(DEFINE_PREFIX)CONFIG_WPA3_SAE
CFLAGS += $(DEFINE_PREFIX)EAP_PEER_METHOD
CFLAGS += $(DEFINE_PREFIX)ESP_PLATFORM=1
CFLAGS += $(DEFINE_PREFIX)ESP_SUPPLICANT
CFLAGS += $(DEFINE_PREFIX)ESPRESSIF_USE
CFLAGS += $(DEFINE_PREFIX)IEEE8021X_EAPOL
CFLAGS += $(DEFINE_PREFIX)USE_WPA2_TASK
CFLAGS += $(DEFINE_PREFIX)CONFIG_SHA256
CFLAGS += $(DEFINE_PREFIX)CONFIG_SAE
ifeq ($(CONFIG_ESP_WIFI_ENABLE_SAE_PK),y)
CFLAGS += $(DEFINE_PREFIX)CONFIG_SAE_PK
endif
ifeq ($(CONFIG_ESP_WIFI_ENABLE_WPA3_OWE_STA),y)
CFLAGS += $(DEFINE_PREFIX)CONFIG_OWE_STA
endif
ifeq ($(CONFIG_ESP_WIFI_GCMP_SUPPORT),y)
CFLAGS += $(DEFINE_PREFIX)CONFIG_GCMP
endif
ifeq ($(CONFIG_ESP_WIFI_GMAC_SUPPORT),y)
CFLAGS += $(DEFINE_PREFIX)CONFIG_GMAC
endif
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)$(WIFI_WPA_SUPPLICANT)$(DELIM)include
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)$(WIFI_WPA_SUPPLICANT)$(DELIM)src
VPATH += $(WIFI_WPA_SUPPLICANT)$(DELIM)src$(DELIM)ap
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)$(WIFI_WPA_SUPPLICANT)$(DELIM)src$(DELIM)ap
CHIP_CSRCS += ap_config.c
CHIP_CSRCS += ieee802_11.c
CHIP_CSRCS += comeback_token.c
CHIP_CSRCS += pmksa_cache_auth.c
CHIP_CSRCS += sta_info.c
CHIP_CSRCS += wpa_auth_ie.c
CHIP_CSRCS += wpa_auth.c
VPATH += $(WIFI_WPA_SUPPLICANT)$(DELIM)src$(DELIM)common
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)$(WIFI_WPA_SUPPLICANT)$(DELIM)src$(DELIM)common
CHIP_CSRCS += dragonfly.c
CHIP_CSRCS += sae.c
CHIP_CSRCS += wpa_common.c
CHIP_CSRCS += sae_pk.c
CHIP_CSRCS += bss.c
CHIP_CSRCS += scan.c
CHIP_CSRCS += ieee802_11_common.c
VPATH += $(WIFI_WPA_SUPPLICANT)$(DELIM)src$(DELIM)crypto
CHIP_CSRCS += aes-ccm.c
CHIP_CSRCS += aes-gcm.c
CHIP_CSRCS += aes-omac1.c
CHIP_CSRCS += aes-unwrap.c
CHIP_CSRCS += aes-wrap.c
CHIP_CSRCS += ccmp.c
CHIP_CSRCS += crypto_ops.c
CHIP_CSRCS += des-internal.c
CHIP_CSRCS += dh_groups.c
CHIP_CSRCS += rc4.c
CHIP_CSRCS += sha1-prf.c
CHIP_CSRCS += sha256-kdf.c
CHIP_CSRCS += sha256-prf.c
VPATH += $(WIFI_WPA_SUPPLICANT)$(DELIM)src$(DELIM)eap_peer
CHIP_CSRCS += chap.c
CHIP_CSRCS += eap_common.c
CHIP_CSRCS += eap_mschapv2.c
CHIP_CSRCS += eap_peap_common.c
CHIP_CSRCS += eap_peap.c
CHIP_CSRCS += eap_tls_common.c
CHIP_CSRCS += eap_tls.c
CHIP_CSRCS += eap_ttls.c
CHIP_CSRCS += eap.c
CHIP_CSRCS += mschapv2.c
VPATH += $(WIFI_WPA_SUPPLICANT)$(DELIM)src$(DELIM)rsn_supp
CHIP_CSRCS += pmksa_cache.c
CHIP_CSRCS += wpa_ie.c
CHIP_CSRCS += wpa.c
VPATH += $(WIFI_WPA_SUPPLICANT)$(DELIM)src$(DELIM)utils
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)$(WIFI_WPA_SUPPLICANT)$(DELIM)src$(DELIM)utils
CHIP_CSRCS += base64.c
CHIP_CSRCS += bitfield.c
CHIP_CSRCS += common.c
CHIP_CSRCS += ext_password.c
CHIP_CSRCS += json.c
CHIP_CSRCS += uuid.c
CHIP_CSRCS += wpa_debug.c
CHIP_CSRCS += wpabuf.c
VPATH += $(WIFI_WPA_SUPPLICANT)$(DELIM)port
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)$(WIFI_WPA_SUPPLICANT)$(DELIM)port$(DELIM)include
CHIP_CSRCS += eloop.c
CHIP_CSRCS += os_xtensa.c
## ESP Supplicant (Espressif's WPA supplicant extension)
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)$(WIFI_WPA_SUPPLICANT)$(DELIM)esp_supplicant$(DELIM)include
VPATH += $(WIFI_WPA_SUPPLICANT)$(DELIM)esp_supplicant$(DELIM)src
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)$(WIFI_WPA_SUPPLICANT)$(DELIM)esp_supplicant$(DELIM)src
CHIP_CSRCS += esp_common.c
CHIP_CSRCS += esp_hostap.c
CHIP_CSRCS += esp_wpa_main.c
CHIP_CSRCS += esp_wpa2.c
CHIP_CSRCS += esp_wpa3.c
CHIP_CSRCS += esp_wpas_glue.c
CHIP_CSRCS += esp_owe.c
CHIP_CSRCS += esp_scan.c
VPATH += $(WIFI_WPA_SUPPLICANT)$(DELIM)esp_supplicant$(DELIM)src$(DELIM)crypto
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)$(WIFI_WPA_SUPPLICANT)$(DELIM)src$(DELIM)crypto
CHIP_CSRCS += crypto_mbedtls-bignum.c
CHIP_CSRCS += crypto_mbedtls-ec.c
CHIP_CSRCS += crypto_mbedtls-rsa.c
CHIP_CSRCS += crypto_mbedtls.c
CHIP_CSRCS += tls_mbedtls.c
CHIP_CSRCS += aes-siv.c
endif

3963
arch/xtensa/src/esp32/esp32_ble_adapter.c
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File diff suppressed because it is too large Load diff

39
arch/xtensa/src/esp32/esp32_ble_adapter.h
View file

@ -31,45 +31,6 @@
#include "esp_bt.h"
/* Bluetooth system and controller config */
#define BTDM_CFG_BT_DATA_RELEASE (1 << 0)
#define BTDM_CFG_HCI_UART (1 << 1)
#define BTDM_CFG_CONTROLLER_RUN_APP_CPU (1 << 2)
#define BTDM_CFG_SCAN_DUPLICATE_OPTIONS (1 << 3)
#define BTDM_CFG_SEND_ADV_RESERVED_SIZE (1 << 4)
#define BTDM_CFG_BLE_FULL_SCAN_SUPPORTED (1 << 5)
/* Bluetooth memory regions */
#define SOC_MEM_BT_DATA_START 0x3ffae6e0
#define SOC_MEM_BT_DATA_END 0x3ffaff10
#define SOC_MEM_BT_EM_START 0x3ffb0000
#define SOC_MEM_BT_EM_END 0x3ffb7cd8
#define SOC_MEM_BT_EM_BTDM0_START 0x3ffb0000
#define SOC_MEM_BT_EM_BTDM0_END 0x3ffb09a8
#define SOC_MEM_BT_EM_BLE_START 0x3ffb09a8
#define SOC_MEM_BT_EM_BLE_END 0x3ffb1ddc
#define SOC_MEM_BT_EM_BTDM1_START 0x3ffb1ddc
#define SOC_MEM_BT_EM_BTDM1_END 0x3ffb2730
#define SOC_MEM_BT_EM_BREDR_START 0x3ffb2730
#define SOC_MEM_BT_EM_BREDR_NO_SYNC_END 0x3ffb6388 /* Not calculate with synchronize connection support */
#define SOC_MEM_BT_EM_BREDR_END 0x3ffb7cd8 /* Calculate with synchronize connection support */
#define SOC_MEM_BT_EM_SYNC0_START 0x3ffb6388
#define SOC_MEM_BT_EM_SYNC0_END 0x3ffb6bf8
#define SOC_MEM_BT_EM_SYNC1_START 0x3ffb6bf8
#define SOC_MEM_BT_EM_SYNC1_END 0x3ffb7468
#define SOC_MEM_BT_EM_SYNC2_START 0x3ffb7468
#define SOC_MEM_BT_EM_SYNC2_END 0x3ffb7cd8
#define SOC_MEM_BT_BSS_START 0x3ffb8000
#define SOC_MEM_BT_BSS_END 0x3ffb9a20
#define SOC_MEM_BT_MISC_START 0x3ffbdb28
#define SOC_MEM_BT_MISC_END 0x3ffbdb5c
#define SOC_MEM_BT_EM_PER_SYNC_SIZE 0x870
#define SOC_MEM_BT_EM_BREDR_REAL_END (SOC_MEM_BT_EM_BREDR_NO_SYNC_END + CONFIG_BTDM_CTRL_BR_EDR_MAX_SYNC_CONN_EFF * SOC_MEM_BT_EM_PER_SYNC_SIZE)
/****************************************************************************
* Public Function Prototypes
****************************************************************************/

1
arch/xtensa/src/esp32/esp32_dac.c
View file

@ -31,6 +31,7 @@
#include "esp32_rtc_gpio.h"
#include "hardware/esp32_rtc_io.h"
#include "hardware/esp32_dport.h"
#include "hardware/esp32_sens.h"
/****************************************************************************
* Pre-processor Definitions

2
arch/xtensa/src/esp32/esp32_dac.h
View file

@ -27,8 +27,6 @@
#include <nuttx/config.h>
#include <nuttx/analog/dac.h>
#include "hardware/esp32_sens.h"
#include "hardware/esp32_rtc_io.h"
/****************************************************************************
* Pre-processor definitions

641
arch/xtensa/src/esp32/esp32_efuse_table.c
View file

@ -1,641 +0,0 @@
/****************************************************************************
* arch/xtensa/src/esp32/esp32_efuse_table.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <stdint.h>
#include <stddef.h>
#include <nuttx/efuse/efuse.h>
#include "esp32_efuse.h"
#define MAX_BLK_LEN 256
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* The last free bit in the block is counted over the entire file */
#define LAST_FREE_BIT_BLK1 MAX_BLK_LEN
#define LAST_FREE_BIT_BLK2 MAX_BLK_LEN
#define LAST_FREE_BIT_BLK3 192
/****************************************************************************
* Private Types
****************************************************************************/
static const efuse_desc_t MAC_FACTORY[] =
{
{
72, 8 /* Factory MAC addr [0], */
},
{
64, 8 /* Factory MAC addr [1], */
},
{
56, 8 /* Factory MAC addr [2], */
},
{
48, 8 /* Factory MAC addr [3], */
},
{
40, 8 /* Factory MAC addr [4], */
},
{
32, 8 /* Factory MAC addr [5], */
},
};
static const efuse_desc_t MAC_FACTORY_CRC[] =
{
{
80, 8 /* CRC8 for factory MAC address */
},
};
static const efuse_desc_t MAC_CUSTOM_CRC[] =
{
{
768, 8 /* CRC8 for custom MAC address */
},
};
static const efuse_desc_t MAC_CUSTOM[] =
{
{
776, 48 /* Custom MAC */
},
};
static const efuse_desc_t MAC_CUSTOM_VER[] =
{
{
952, 8 /* Custom MAC version */
},
};
static const efuse_desc_t SECURE_BOOT_KEY[] =
{
{
512, MAX_BLK_LEN /* Security boot key */
},
};
static const efuse_desc_t ABS_DONE_0[] =
{
{
196, 1 /* Secure boot is enabled for bootloader image.
* EFUSE_RD_ABS_DONE_0
*/
},
};
static const efuse_desc_t ENCRYPT_FLASH_KEY[] =
{
{
256, MAX_BLK_LEN /* Flash encrypt key */
},
};
static const efuse_desc_t ENCRYPT_CONFIG[] =
{
{
188, 4 /* Flash encrypt. EFUSE_FLASH_CRYPT_CONFIG_M */
},
};
static const efuse_desc_t DISABLE_DL_ENCRYPT[] =
{
{
199, 1 /* Flash encrypt. Disable UART bootloader
* encryption. EFUSE_DISABLE_DL_ENCRYPT
*/
},
};
static const efuse_desc_t DISABLE_DL_DECRYPT[] =
{
{
200, 1 /* Flash encrypt. Disable UART bootloader
* decryption. EFUSE_DISABLE_DL_DECRYPT
*/
},
};
static const efuse_desc_t DISABLE_DL_CACHE[] =
{
{
201, 1 /* Flash encrypt. Disable UART bootloader MMU
* cache. EFUSE_DISABLE_DL_CACHE
*/
},
};
static const efuse_desc_t FLASH_CRYPT_CNT[] =
{
{
20, 7 /* Flash encrypt. Flash encryption is enabled
* if this field has an odd number of bits set.
* EFUSE_FLASH_CRYPT_CNT
*/
},
};
static const efuse_desc_t DISABLE_JTAG[] =
{
{
198, 1 /* Disable JTAG. EFUSE_RD_DISABLE_JTAG */
},
};
static const efuse_desc_t CONSOLE_DEBUG_DISABLE[] =
{
{
194, 1 /* Disable ROM BASIC interpreter fallback.
* EFUSE_RD_CONSOLE_DEBUG_DISABLE
*/
},
};
static const efuse_desc_t UART_DOWNLOAD_DIS[] =
{
{
27, 1 /* Disable UART download mode.
* Valid for ESP32 V3 and newer
*/
},
};
static const efuse_desc_t WR_DIS_FLASH_CRYPT_CNT[] =
{
{
2, 1 /* Flash encrypt. Write protection
* FLASH_CRYPT_CNT
*/
},
};
static const efuse_desc_t WR_DIS_BLK1[] =
{
{
7, 1 /* Flash encrypt. Write protection encryption key.
* EFUSE_WR_DIS_BLK1
*/
},
};
static const efuse_desc_t WR_DIS_BLK2[] =
{
{
8, 1 /* Security boot. Write protection security key.
* EFUSE_WR_DIS_BLK2
*/
},
};
static const efuse_desc_t WR_DIS_BLK3[] =
{
{
9, 1 /* Write protection for EFUSE_BLK3.
* EFUSE_WR_DIS_BLK3
*/
},
};
static const efuse_desc_t RD_DIS_BLK1[] =
{
{
16, 1 /* Flash encrypt. efuse_key_read_protected.
* EFUSE_RD_DIS_BLK1
*/
},
};
static const efuse_desc_t RD_DIS_BLK2[] =
{
{
17, 1 /* Security boot. efuse_key_read_protected.
* EFUSE_RD_DIS_BLK2
*/
},
};
static const efuse_desc_t RD_DIS_BLK3[] =
{
{
18, 1 /* Read protection for EFUSE_BLK3.
* EFUSE_RD_DIS_BLK3
*/
},
};
static const efuse_desc_t CHIP_VER_DIS_APP_CPU[] =
{
{
96, 1 /* EFUSE_RD_CHIP_VER_DIS_APP_CPU */
},
};
static const efuse_desc_t CHIP_VER_DIS_BT[] =
{
{
97, 1 /* EFUSE_RD_CHIP_VER_DIS_BT */
},
};
static const efuse_desc_t CHIP_VER_PKG[] =
{
{
105, 3 /* EFUSE_RD_CHIP_VER_PKG */
},
};
static const efuse_desc_t CHIP_CPU_FREQ_LOW[] =
{
{
108, 1 /* EFUSE_RD_CHIP_CPU_FREQ_LOW */
},
};
static const efuse_desc_t CHIP_CPU_FREQ_RATED[] =
{
{
109, 1 /* EFUSE_RD_CHIP_CPU_FREQ_RATED */
},
};
static const efuse_desc_t CHIP_VER_REV1[] =
{
{
111, 1 /* EFUSE_RD_CHIP_VER_REV1 */
},
};
static const efuse_desc_t CHIP_VER_REV2[] =
{
{
180, 1 /* EFUSE_RD_CHIP_VER_REV2 */
},
};
static const efuse_desc_t XPD_SDIO_REG[] =
{
{
142, 1 /* EFUSE_RD_XPD_SDIO_REG */
},
};
static const efuse_desc_t SDIO_TIEH[] =
{
{
143, 1 /* EFUSE_RD_SDIO_TIEH */
},
};
static const efuse_desc_t SDIO_FORCE[] =
{
{
144, 1 /* EFUSE_RD_XPD_SDIO_FORCE */
},
};
static const efuse_desc_t ADC_VREF_AND_SDIO_DREF[] =
{
{
136, 6 /* EFUSE_RD_ADC_VREF[0..4] or SDIO_DREFH[0 1] */
},
};
static const efuse_desc_t ADC1_TP_LOW[] =
{
{
864, 7 /* TP_REG EFUSE_RD_ADC1_TP_LOW */
},
};
static const efuse_desc_t ADC2_TP_LOW[] =
{
{
880, 7 /* TP_REG EFUSE_RD_ADC2_TP_LOW */
},
};
static const efuse_desc_t ADC1_TP_HIGH[] =
{
{
871, 9 /* TP_REG EFUSE_RD_ADC1_TP_HIGH */
},
};
static const efuse_desc_t ADC2_TP_HIGH[] =
{
{
887, 9 /* TP_REG EFUSE_RD_ADC2_TP_HIGH */
},
};
static const efuse_desc_t SECURE_VERSION[] =
{
{
896, 32 /* Secure version for anti-rollback */
},
};
/* */
const efuse_desc_t *ESP_EFUSE_MAC_FACTORY[] =
{
&MAC_FACTORY[0], /* Factory MAC addr [0] */
&MAC_FACTORY[1], /* Factory MAC addr [1] */
&MAC_FACTORY[2], /* Factory MAC addr [2] */
&MAC_FACTORY[3], /* Factory MAC addr [3] */
&MAC_FACTORY[4], /* Factory MAC addr [4] */
&MAC_FACTORY[5], /* Factory MAC addr [5] */
NULL
};
const efuse_desc_t *ESP_EFUSE_MAC_FACTORY_CRC[] =
{
&MAC_FACTORY_CRC[0], /* CRC8 for factory MAC address */
NULL
};
const efuse_desc_t *ESP_EFUSE_MAC_CUSTOM_CRC[] =
{
&MAC_CUSTOM_CRC[0], /* CRC8 for custom MAC address. */
NULL
};
const efuse_desc_t *ESP_EFUSE_MAC_CUSTOM[] =
{
&MAC_CUSTOM[0], /* Custom MAC */
NULL
};
const efuse_desc_t *ESP_EFUSE_MAC_CUSTOM_VER[] =
{
&MAC_CUSTOM_VER[0], /* Custom MAC version */
NULL
};
const efuse_desc_t *ESP_EFUSE_SECURE_BOOT_KEY[] =
{
&SECURE_BOOT_KEY[0], /* Security boot. Key.
* (length = "None" - 256.
* "3/4" - 192. "REPEAT" - 128)
*/
NULL
};
const efuse_desc_t *ESP_EFUSE_ABS_DONE_0[] =
{
&ABS_DONE_0[0], /* Secure boot is enabled for bootloader image.
* EFUSE_RD_ABS_DONE_0
*/
NULL
};
const efuse_desc_t *ESP_EFUSE_ENCRYPT_FLASH_KEY[] =
{
&ENCRYPT_FLASH_KEY[0], /* Flash encrypt. Key.
* (length = "None" - 256.
* "3/4" - 192. "REPEAT" - 128)
*/
NULL
};
const efuse_desc_t *ESP_EFUSE_ENCRYPT_CONFIG[] =
{
&ENCRYPT_CONFIG[0], /* Flash encrypt. EFUSE_FLASH_CRYPT_CONFIG_M */
NULL
};
const efuse_desc_t *ESP_EFUSE_DISABLE_DL_ENCRYPT[] =
{
&DISABLE_DL_ENCRYPT[0], /* Flash encrypt. Disable UART bootloader
* encryption. EFUSE_DISABLE_DL_ENCRYPT.
*/
NULL
};
const efuse_desc_t *ESP_EFUSE_DISABLE_DL_DECRYPT[] =
{
&DISABLE_DL_DECRYPT[0], /* Flash encrypt. Disable UART bootloader
* decryption. EFUSE_DISABLE_DL_DECRYPT.
*/
NULL
};
const efuse_desc_t *ESP_EFUSE_DISABLE_DL_CACHE[] =
{
&DISABLE_DL_CACHE[0], /* Flash encrypt. Disable UART bootloader
* MMU cache. EFUSE_DISABLE_DL_CACHE.
*/
NULL
};
const efuse_desc_t *ESP_EFUSE_FLASH_CRYPT_CNT[] =
{
&FLASH_CRYPT_CNT[0], /* Flash encrypt. Flash encryption is enabled
* if this field has an odd number of bits set.
* EFUSE_FLASH_CRYPT_CNT.
*/
NULL
};
const efuse_desc_t *ESP_EFUSE_DISABLE_JTAG[] =
{
&DISABLE_JTAG[0], /* Disable JTAG. EFUSE_RD_DISABLE_JTAG. */
NULL
};
const efuse_desc_t *ESP_EFUSE_CONSOLE_DEBUG_DISABLE[] =
{
&CONSOLE_DEBUG_DISABLE[0], /* Disable ROM BASIC interpreter fallback.
* EFUSE_RD_CONSOLE_DEBUG_DISABLE.
*/
NULL
};
const efuse_desc_t *ESP_EFUSE_UART_DOWNLOAD_DIS[] =
{
&UART_DOWNLOAD_DIS[0], /* Disable UART download mode. Valid for
* ESP32 V3 and newer
*/
NULL
};
const efuse_desc_t *ESP_EFUSE_WR_DIS_FLASH_CRYPT_CNT[] =
{
&WR_DIS_FLASH_CRYPT_CNT[0], /* Flash encrypt. Write protection
* FLASH_CRYPT_CNT
*/
NULL
};
const efuse_desc_t *ESP_EFUSE_WR_DIS_BLK1[] =
{
&WR_DIS_BLK1[0], /* Flash encrypt. Write protection
* encryption key. EFUSE_WR_DIS_BLK1 */
NULL
};
const efuse_desc_t *ESP_EFUSE_WR_DIS_BLK2[] =
{
&WR_DIS_BLK2[0], /* Security boot. Write protection security
* key. EFUSE_WR_DIS_BLK2 */
NULL
};
const efuse_desc_t *ESP_EFUSE_WR_DIS_BLK3[] =
{
&WR_DIS_BLK3[0], /* Write protection for EFUSE_BLK3.
* EFUSE_WR_DIS_BLK3
*/
NULL
};
const efuse_desc_t *ESP_EFUSE_RD_DIS_BLK1[] =
{
&RD_DIS_BLK1[0], /* Flash encrypt. efuse_key_read_protected.
* EFUSE_RD_DIS_BLK1
*/
NULL
};
const efuse_desc_t *ESP_EFUSE_RD_DIS_BLK2[] =
{
&RD_DIS_BLK2[0], /* Security boot. efuse_key_read_protected.
* EFUSE_RD_DIS_BLK2
*/
NULL
};
const efuse_desc_t *ESP_EFUSE_RD_DIS_BLK3[] =
{
&RD_DIS_BLK3[0], /* Read protection for EFUSE_BLK3.
* EFUSE_RD_DIS_BLK3
*/
NULL
};
const efuse_desc_t *ESP_EFUSE_CHIP_VER_DIS_APP_CPU[] =
{
&CHIP_VER_DIS_APP_CPU[0], /* EFUSE_RD_CHIP_VER_DIS_APP_CPU */
NULL
};
const efuse_desc_t *ESP_EFUSE_CHIP_VER_DIS_BT[] =
{
&CHIP_VER_DIS_BT[0], /* EFUSE_RD_CHIP_VER_DIS_BT */
NULL
};
const efuse_desc_t *ESP_EFUSE_CHIP_VER_PKG[] =
{
&CHIP_VER_PKG[0], /* EFUSE_RD_CHIP_VER_PKG */
NULL
};
const efuse_desc_t *ESP_EFUSE_CHIP_CPU_FREQ_LOW[] =
{
&CHIP_CPU_FREQ_LOW[0], /* EFUSE_RD_CHIP_CPU_FREQ_LOW */
NULL
};
const efuse_desc_t *ESP_EFUSE_CHIP_CPU_FREQ_RATED[] =
{
&CHIP_CPU_FREQ_RATED[0], /* EFUSE_RD_CHIP_CPU_FREQ_RATED */
NULL
};
const efuse_desc_t *ESP_EFUSE_CHIP_VER_REV1[] =
{
&CHIP_VER_REV1[0], /* EFUSE_RD_CHIP_VER_REV1 */
NULL
};
const efuse_desc_t *ESP_EFUSE_CHIP_VER_REV2[] =
{
&CHIP_VER_REV2[0], /* EFUSE_RD_CHIP_VER_REV2 */
NULL
};
const efuse_desc_t *ESP_EFUSE_XPD_SDIO_REG[] =
{
&XPD_SDIO_REG[0], /* EFUSE_RD_XPD_SDIO_REG */
NULL
};
const efuse_desc_t *ESP_EFUSE_SDIO_TIEH[] =
{
&SDIO_TIEH[0], /* EFUSE_RD_SDIO_TIEH */
NULL
};
const efuse_desc_t *ESP_EFUSE_SDIO_FORCE[] =
{
&SDIO_FORCE[0], /* EFUSE_RD_SDIO_FORCE */
NULL
};
const efuse_desc_t *ESP_EFUSE_ADC_VREF_AND_SDIO_DREF[] =
{
&ADC_VREF_AND_SDIO_DREF[0], /* EFUSE_RD_ADC_VREF[0..4] or
* SDIO_DREFH[0 1]
*/
NULL
};
const efuse_desc_t *ESP_EFUSE_ADC1_TP_LOW[] =
{
&ADC1_TP_LOW[0], /* TP_REG EFUSE_RD_ADC1_TP_LOW */
NULL
};
const efuse_desc_t *ESP_EFUSE_ADC2_TP_LOW[] =
{
&ADC2_TP_LOW[0], /* TP_REG EFUSE_RD_ADC2_TP_LOW */
NULL
};
const efuse_desc_t *ESP_EFUSE_ADC1_TP_HIGH[] =
{
&ADC1_TP_HIGH[0], /* TP_REG EFUSE_RD_ADC1_TP_HIGH */
NULL
};
const efuse_desc_t *ESP_EFUSE_ADC2_TP_HIGH[] =
{
&ADC2_TP_HIGH[0], /* TP_REG EFUSE_RD_ADC2_TP_HIGH */
NULL
};
const efuse_desc_t *ESP_EFUSE_SECURE_VERSION[] =
{
&SECURE_VERSION[0], /* Secure version for anti-rollback */
NULL
};
/****************************************************************************
* Private Functions
****************************************************************************/

16
arch/xtensa/src/esp32/esp32_irq.c
View file

@ -178,8 +178,9 @@ static bool g_non_iram_int_disabled_flag[CONFIG_SMP_NCPUS];
*/
static uint32_t g_cpu0_freeints = ESP32_CPUINT_PERIPHSET &
(~ESP32_WIFI_RESERVE_INT &
~ESP32_BLE_RESERVE_INT);
~(ESP32_WIFI_RESERVE_INT |
ESP32_BLE_RESERVE_INT);
#ifdef CONFIG_SMP
static uint32_t g_cpu1_freeints = ESP32_CPUINT_PERIPHSET;
#endif
@ -517,6 +518,8 @@ void up_irqinitialize(void)
/* Hard code special cases. */
g_irqmap[XTENSA_IRQ_TIMER0] = IRQ_MKMAP(0, ESP32_CPUINT_TIMER0);
g_irqmap[XTENSA_IRQ_SWINT] = IRQ_MKMAP(0, ESP32_CPUINT_SOFTWARE1);
g_irqmap[XTENSA_IRQ_SWINT] = IRQ_MKMAP(1, ESP32_CPUINT_SOFTWARE1);
#ifdef CONFIG_ESP32_WIFI
g_irqmap[ESP32_IRQ_MAC] = IRQ_MKMAP(0, ESP32_CPUINT_MAC);
@ -528,9 +531,6 @@ void up_irqinitialize(void)
g_irqmap[ESP32_IRQ_RWBLE_IRQ] = IRQ_MKMAP(0, ESP32_PERIPH_RWBLE_IRQ);
#endif
g_irqmap[XTENSA_IRQ_SWINT] = IRQ_MKMAP(0, ESP32_CPUINT_SOFTWARE1);
g_irqmap[XTENSA_IRQ_SWINT] = IRQ_MKMAP(1, ESP32_CPUINT_SOFTWARE1);
/* Initialize CPU interrupts */
esp32_cpuint_initialize();
@ -681,7 +681,7 @@ void up_enable_irq(int irq)
/* Enable the CPU interrupt now for internal CPU. */
xtensa_enable_cpuint(&g_intenable[cpu], 1ul << cpuint);
xtensa_enable_cpuint(&g_intenable[cpu], (1ul << cpuint));
}
else
{
@ -711,8 +711,8 @@ void up_enable_irq(int irq)
DEBUGASSERT(cpu >= 0 && cpu < CONFIG_SMP_NCPUS);
/* Attach the interrupt to the peripheral; the CPU interrupt was
* already enabled when allocated.
/* For peripheral interrupts, attach the interrupt to the peripheral;
* the CPU interrupt was already enabled when allocated.
*/
int periph = ESP32_IRQ2PERIPH(irq);

38
arch/xtensa/src/esp32/esp32_rng.c
View file

@ -44,6 +44,8 @@
#include "hardware/wdev_reg.h"
#include "esp32_clockconfig.h"
#include "esp_random.h"
#if defined(CONFIG_ESP32_RNG)
#if defined(CONFIG_DEV_RANDOM) || defined(CONFIG_DEV_URANDOM_ARCH)
@ -81,42 +83,6 @@ static const struct file_operations g_rngops =
* Private functions
****************************************************************************/
/****************************************************************************
* Name: esp32_random
****************************************************************************/
uint32_t IRAM_ATTR esp_random(void)
{
/* The PRNG which implements WDEV_RANDOM register gets 2 bits
* of extra entropy from a hardware randomness source every APB clock cycle
* (provided Wi-Fi or BT are enabled). To make sure entropy is not drained
* faster than it is added, this function needs to wait for at least 16 APB
* clock cycles after reading previous word. This implementation may
* actually wait a bit longer due to extra time spent in arithmetic and
* branch statements.
*
* As a (probably unnecessary) precaution to avoid returning the
* RNG state as-is, the result is XORed with additional
* WDEV_RND_REG reads while waiting.
*/
uint32_t cpu_to_apb_freq_ratio = esp_clk_cpu_freq() / esp_clk_apb_freq();
static uint32_t last_ccount = 0;
uint32_t ccount;
uint32_t result = 0;
do
{
ccount = XTHAL_GET_CCOUNT();
result ^= getreg32(WDEV_RND_REG);
}
while (ccount - last_ccount < cpu_to_apb_freq_ratio * 16);
last_ccount = ccount;
return result ^ getreg32(WDEV_RND_REG);
}
/****************************************************************************
* Name: esp32_rng_read
****************************************************************************/

2
arch/xtensa/src/esp32/esp32_touch.h
View file

@ -29,7 +29,7 @@
#include <stdint.h>
#include <stdbool.h>
#include "esp32_touch_lowerhalf.h"
#include "hardware/esp32_touch.h"
/****************************************************************************
* Pre-processor Definitions

3
arch/xtensa/src/esp32/esp32_twai.c
View file

@ -48,6 +48,9 @@
#include "hardware/esp32_dport.h"
#include "hardware/esp32_gpio_sigmap.h"
#include "hardware/esp32_twai.h"
#include "soc/soc.h"
#if defined(CONFIG_ESP32_TWAI)

1
arch/xtensa/src/esp32/esp32_twai.h
View file

@ -26,7 +26,6 @@
****************************************************************************/
#include <nuttx/config.h>
#include "hardware/esp32_twai.h"
/****************************************************************************
* Pre-processor Definitions

1278
arch/xtensa/src/esp32/esp32_wifi_adapter.c
View file

File diff suppressed because it is too large Load diff

3
arch/xtensa/src/esp32/esp32_wifi_adapter.h
View file

@ -61,7 +61,8 @@ extern "C"
# define ESP32_WLAN_DEVS 2
#endif
/* Needed to fix coex_adapter_funcs_t definition */
#define SSID_MAX_LEN (32)
#define PWD_MAX_LEN (64)
#define CONFIG_IDF_TARGET_ESP32 1

58
arch/xtensa/src/esp32/esp32_wifi_utils.c
View file

@ -35,7 +35,15 @@
#include "esp32_wifi_adapter.h"
#include "esp32_wifi_utils.h"
#include "esp32_wireless.h"
#include "espidf_wifi.h"
#include "esp_log.h"
#include "esp_mac.h"
#include "esp_private/phy.h"
#include "esp_private/wifi.h"
#include "esp_random.h"
#include "esp_timer.h"
#include "rom/ets_sys.h"
#include "soc/soc_caps.h"
/****************************************************************************
* Pre-processor Definitions
@ -53,7 +61,6 @@
#endif
#define SCAN_TIME_SEC (5)
#define SSID_LEN (33)
/* Maximum number of channels for Wi-Fi 2.4Ghz */
@ -114,13 +121,13 @@ int esp_wifi_start_scan(struct iwreq *iwr)
{
struct wifi_scan_result *priv = &g_scan_priv;
wifi_scan_config_t *config = NULL;
uint8_t target_ssid[SSID_LEN];
struct iw_scan_req *req;
int ret = 0;
int i;
uint8_t target_mac[MAC_LEN];
uint8_t target_ssid[SSID_MAX_LEN + 1];
memset(target_ssid, 0x0, sizeof(SSID_MAX_LEN + 1));
memset(target_ssid, 0x0, sizeof(SSID_LEN));
if (iwr == NULL)
{
wlerr("ERROR: Invalid ioctl cmd.\n");
@ -132,7 +139,7 @@ int esp_wifi_start_scan(struct iwreq *iwr)
return OK;
}
config = kmm_malloc(sizeof(wifi_scan_config_t));
config = kmm_calloc(1, sizeof(wifi_scan_config_t));
if (config == NULL)
{
wlerr("ERROR: Cannot allocate result buffer\n");
@ -141,7 +148,7 @@ int esp_wifi_start_scan(struct iwreq *iwr)
g_channel_num = 0;
memset(g_channel_list, 0x0, CHANNEL_MAX_NUM);
memset(config, 0x0, sizeof(wifi_scan_config_t));
if (iwr->u.data.pointer &&
iwr->u.data.length >= sizeof(struct iw_scan_req))
{
@ -153,6 +160,8 @@ int esp_wifi_start_scan(struct iwreq *iwr)
{
/* Scan specific ESSID */
config->show_hidden = true;
config->bssid = NULL;
memcpy(&target_ssid[0], req->essid, req->essid_len);
config->ssid = &target_ssid[0];
config->ssid[req->essid_len] = '\0';
@ -196,8 +205,6 @@ int esp_wifi_start_scan(struct iwreq *iwr)
}
esp_wifi_start();
esp_wifi_scan_stop();
ret = esp_wifi_scan_start(config, false);
if (ret != OK)
{
@ -257,18 +264,25 @@ int esp_wifi_get_scan_results(struct iwreq *iwr)
if (g_scan_priv.scan_status == ESP_SCAN_RUN)
{
irqstate_t irqstate = enter_critical_section();
if (scan_block == false)
{
scan_block = true;
leave_critical_section(irqstate);
nxsem_tickwait(&priv->scan_signal, SEC2TICK(SCAN_TIME_SEC));
scan_block = false;
}
else
{
leave_critical_section(irqstate);
ret = -EINVAL;
goto exit_failed;
}
}
else if (g_scan_priv.scan_status == ESP_SCAN_DISABLED)
{
return -EINVAL;
}
if ((iwr == NULL) || (g_scan_priv.scan_status != ESP_SCAN_DONE))
{
@ -276,7 +290,7 @@ int esp_wifi_get_scan_results(struct iwreq *iwr)
goto exit_failed;
}
if (!priv->scan_result)
if (priv->scan_result == NULL)
{
/* Result have already been requested */
@ -352,19 +366,26 @@ void esp_wifi_scan_event_parse(void)
uint8_t bss_count = 0;
bool parse_done = false;
if (priv->scan_status != ESP_SCAN_RUN)
{
return;
}
esp_wifi_scan_get_ap_num(&bss_total);
if (bss_total == 0)
{
priv->scan_status = ESP_SCAN_DONE;
wlinfo("INFO: None AP is scanned\n");
nxsem_post(&priv->scan_signal);
return;
}
ap_list_buffer = kmm_zalloc(bss_total * sizeof(wifi_ap_record_t));
ap_list_buffer = kmm_calloc(bss_total, sizeof(wifi_ap_record_t));
if (ap_list_buffer == NULL)
{
priv->scan_status = ESP_SCAN_DONE;
wlerr("ERROR: Failed to malloc buffer to print scan results");
wlerr("ERROR: Failed to calloc buffer to print scan results");
nxsem_post(&priv->scan_signal);
return;
}
@ -377,6 +398,7 @@ void esp_wifi_scan_event_parse(void)
size_t essid_len_aligned;
bool is_target_channel = true;
int i;
for (bss_count = 0; bss_count < bss_total; bss_count++)
{
if (g_channel_num > 1)
@ -421,16 +443,16 @@ void esp_wifi_scan_event_parse(void)
/* Copy ESSID */
essid_len = MIN(strlen((const char *)
ap_list_buffer[bss_count].ssid), 32);
ap_list_buffer[bss_count].ssid), SSID_MAX_LEN);
essid_len_aligned = (essid_len + 3) & -4;
if (result_size < ESP_IW_EVENT_SIZE(essid)+essid_len_aligned)
if (result_size < ESP_IW_EVENT_SIZE(essid) + essid_len_aligned)
{
goto scan_result_full;
}
iwe = (struct iw_event *)
&priv->scan_result[priv->scan_result_size];
iwe->len = ESP_IW_EVENT_SIZE(essid)+essid_len_aligned;
iwe->len = ESP_IW_EVENT_SIZE(essid) + essid_len_aligned;
iwe->cmd = SIOCGIWESSID;
iwe->u.essid.flags = 0;
iwe->u.essid.length = essid_len;
@ -442,10 +464,12 @@ void esp_wifi_scan_event_parse(void)
iwe->u.essid.pointer = (void *)sizeof(iwe->u.essid);
memcpy(&iwe->u.essid + 1,
ap_list_buffer[bss_count].ssid, essid_len);
wlinfo("INFO: ssid %s\n", ap_list_buffer[bss_count].ssid);
priv->scan_result_size +=
ESP_IW_EVENT_SIZE(essid)+essid_len_aligned;
result_size -= ESP_IW_EVENT_SIZE(essid)+essid_len_aligned;
ESP_IW_EVENT_SIZE(essid) + essid_len_aligned;
result_size -= ESP_IW_EVENT_SIZE(essid) + essid_len_aligned;
/* Copy link quality info */
@ -459,7 +483,9 @@ void esp_wifi_scan_event_parse(void)
iwe->len = ESP_IW_EVENT_SIZE(qual);
iwe->cmd = IWEVQUAL;
iwe->u.qual.qual = 0x00;
wlinfo("INFO: signal %d\n", ap_list_buffer[bss_count].rssi);
iwe->u.qual.level = ap_list_buffer[bss_count].rssi;
iwe->u.qual.noise = 0x00;
iwe->u.qual.updated = IW_QUAL_DBM | IW_QUAL_ALL_UPDATED;

530
arch/xtensa/src/esp32/esp32_wireless.c
View file

@ -26,10 +26,10 @@
#include <nuttx/kmalloc.h>
#include <nuttx/mqueue.h>
#include <netinet/in.h>
#include <sys/param.h>
#include <debug.h>
#include <assert.h>
#include <netinet/in.h>
#include <sys/param.h>
#include "xtensa.h"
#include "hardware/esp32_dport.h"
@ -38,6 +38,13 @@
#include "esp32_irq.h"
#include "esp32_partition.h"
#include "esp_private/phy.h"
#ifdef CONFIG_ESP32_WIFI
# include "esp_private/wifi.h"
# include "esp_wpa.h"
#endif
#include "esp_coexist_internal.h"
#include "periph_ctrl.h"
#include "esp_phy_init.h"
#include "phy_init_data.h"
@ -47,12 +54,6 @@
* Pre-processor Definitions
****************************************************************************/
#ifdef CONFIG_ESP32_UNIVERSAL_MAC_ADDRESSES_FOUR
# define MAC_ADDR_UNIVERSE_BT_OFFSET 2
#else
# define MAC_ADDR_UNIVERSE_BT_OFFSET 1
#endif
/* Software Interrupt */
#define SWI_IRQ ESP32_IRQ_CPU_CPU2
@ -81,13 +82,16 @@ struct esp_wireless_priv_s
static inline void phy_digital_regs_store(void);
static inline void phy_digital_regs_load(void);
static int esp_swi_irq(int irq, void *context, void *arg);
#ifdef CONFIG_ESP32_WIFI
static void esp_wifi_set_log_level(void);
#endif
/****************************************************************************
* Extern Functions declaration
****************************************************************************/
extern uint8_t esp_crc8(const uint8_t *p, uint32_t len);
extern void coex_bt_high_prio(void);
extern void phy_wakeup_init(void);
extern void phy_close_rf(void);
extern uint8_t phy_dig_reg_backup(bool init, uint32_t *regs);
@ -116,6 +120,10 @@ static uint32_t *g_phy_digital_regs_mem = NULL;
static bool g_is_phy_calibrated = false;
/* Private data of the wireless common interface */
static struct esp_wireless_priv_s g_esp_wireless_priv;
#ifdef CONFIG_ESP32_PHY_INIT_DATA_IN_PARTITION
static const char *phy_partion_label = "phy_init";
#endif
@ -144,6 +152,7 @@ static const char *g_phy_type[ESP_PHY_INIT_DATA_TYPE_NUMBER] =
static phy_country_to_bin_type_t g_country_code_map_type_table[] =
{
{"01", ESP_PHY_INIT_DATA_TYPE_DEFAULT},
{"AT", ESP_PHY_INIT_DATA_TYPE_CE},
{"AU", ESP_PHY_INIT_DATA_TYPE_ACMA},
{"BE", ESP_PHY_INIT_DATA_TYPE_CE},
@ -192,9 +201,13 @@ static phy_country_to_bin_type_t g_country_code_map_type_table[] =
#endif
/* Private data of the wireless common interface */
/****************************************************************************
* Public Data
****************************************************************************/
static struct esp_wireless_priv_s g_esp_wireless_priv;
/* Callback function to update WiFi MAC time */
wifi_mac_time_update_cb_t g_wifi_mac_time_update_cb = NULL;
/****************************************************************************
* Private Functions
@ -299,6 +312,41 @@ static int esp_swi_irq(int irq, void *context, void *arg)
return OK;
}
#ifdef CONFIG_ESP32_WIFI
/****************************************************************************
* Name: esp_wifi_set_log_level
*
* Description:
* Sets the log level for the ESP32 WiFi module based on preprocessor
* definitions. The log level can be verbose, warning, or error.
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
static void esp_wifi_set_log_level(void)
{
wifi_log_level_t wifi_log_level = WIFI_LOG_NONE;
/* set WiFi log level */
#if defined(CONFIG_DEBUG_WIRELESS_INFO)
wifi_log_level = WIFI_LOG_VERBOSE;
#elif defined(CONFIG_DEBUG_WIRELESS_WARN)
wifi_log_level = WIFI_LOG_WARNING;
#elif defined(CONFIG_LOG_MAXIMUM_LEVEL)
wifi_log_level = WIFI_LOG_ERROR;
#endif
esp_wifi_internal_set_log_level(wifi_log_level);
}
#endif /* CONFIG_ESP32_WIFI */
/****************************************************************************
* Public Functions
****************************************************************************/
@ -326,48 +374,6 @@ uint32_t IRAM_ATTR esp_dport_access_reg_read(uint32_t reg)
return getreg32(reg);
}
/****************************************************************************
* Name: phy_enter_critical
*
* Description:
* Enter critical state
*
* Input Parameters:
* None
*
* Returned Value:
* CPU PS value
*
****************************************************************************/
uint32_t IRAM_ATTR phy_enter_critical(void)
{
irqstate_t flags;
flags = enter_critical_section();
return flags;
}
/****************************************************************************
* Name: phy_exit_critical
*
* Description:
* Exit from critical state
*
* Input Parameters:
* level - CPU PS value
*
* Returned Value:
* None
*
****************************************************************************/
void IRAM_ATTR phy_exit_critical(uint32_t level)
{
leave_critical_section(level);
}
/****************************************************************************
* Name: phy_printf
*
@ -395,71 +401,6 @@ int phy_printf(const char *format, ...)
return 0;
}
/****************************************************************************
* Name: esp32_phy_enable_clock
*
* Description:
* Enable PHY hardware clock
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
void esp32_phy_enable_clock(void)
{
irqstate_t flags;
flags = enter_critical_section();
if (g_phy_clk_en_cnt == 0)
{
modifyreg32(DPORT_WIFI_CLK_EN_REG, 0,
DPORT_WIFI_CLK_WIFI_BT_COMMON_M);
}
g_phy_clk_en_cnt++;
leave_critical_section(flags);
}
/****************************************************************************
* Name: esp32_phy_disable_clock
*
* Description:
* Disable PHY hardware clock
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
void esp32_phy_disable_clock(void)
{
irqstate_t flags;
flags = enter_critical_section();
if (g_phy_clk_en_cnt > 0)
{
g_phy_clk_en_cnt--;
if (g_phy_clk_en_cnt == 0)
{
modifyreg32(DPORT_WIFI_CLK_EN_REG,
DPORT_WIFI_CLK_WIFI_BT_COMMON_M,
0);
}
}
leave_critical_section(flags);
}
#ifdef CONFIG_ESP32_SUPPORT_MULTIPLE_PHY_INIT_DATA
/****************************************************************************
@ -515,7 +456,7 @@ static uint8_t phy_find_bin_type_according_country(const char *country)
for (i = 0; i < num; i++)
{
if (memcmp(country, g_country_code_map_type_table[i].cc,
PHY_COUNTRY_CODE_LEN) == 0)
sizeof(g_phy_current_country)) == 0)
{
phy_init_data_type = g_country_code_map_type_table[i].type;
wlinfo("Current country is %c%c, PHY init data type is %s\n",
@ -606,8 +547,10 @@ static int phy_get_multiple_init_data(uint8_t *data, size_t length,
return -ENOMEM;
}
int ret = esp32_partition_read(phy_partion_label, length,
control_info, sizeof(phy_control_info_data_t));
int ret = esp32_partition_read(phy_partion_label,
length,
control_info,
sizeof(phy_control_info_data_t));
if (ret != OK)
{
kmm_free(control_info);
@ -618,8 +561,9 @@ static int phy_get_multiple_init_data(uint8_t *data, size_t length,
if ((control_info->check_algorithm) == PHY_CRC_ALGORITHM)
{
ret = phy_crc_check(control_info->multiple_bin_checksum,
control_info->control_info_checksum, sizeof(phy_control_info_data_t) -
sizeof(control_info->control_info_checksum));
control_info->control_info_checksum,
sizeof(phy_control_info_data_t) -
sizeof(control_info->control_info_checksum));
if (ret != OK)
{
kmm_free(control_info);
@ -762,7 +706,7 @@ static int phy_update_init_data(phy_init_data_type_t init_data_type)
if (g_current_apply_phy_init_data != g_phy_init_data_type)
{
ret = esp_phy_apply_phy_init_data(init_data_store +
sizeof(phy_init_magic_pre));
sizeof(phy_init_magic_pre));
if (ret != OK)
{
wlerr("ERROR: PHY init data failed to load\n");
@ -802,7 +746,7 @@ const esp_phy_init_data_t *esp_phy_get_init_data(void)
{
int ret;
size_t length = sizeof(phy_init_magic_pre) +
sizeof(esp_phy_init_data_t) + sizeof(phy_init_magic_post);
sizeof(esp_phy_init_data_t) + sizeof(phy_init_magic_post);
uint8_t *init_data_store = kmm_malloc(length);
if (init_data_store == NULL)
{
@ -867,6 +811,7 @@ const esp_phy_init_data_t *esp_phy_get_init_data(void)
}
#endif
wlinfo("PHY data partition validated\n");
return (const esp_phy_init_data_t *)
(init_data_store + sizeof(phy_init_magic_pre));
}
@ -931,84 +876,6 @@ void esp_phy_release_init_data(const esp_phy_init_data_t *init_data)
}
#endif
/****************************************************************************
* Name: esp_read_mac
*
* Description:
* Read MAC address from efuse
*
* Input Parameters:
* mac - MAC address buffer pointer
* type - MAC address type
*
* Returned Value:
* 0 if success or -1 if fail
*
****************************************************************************/
int32_t esp_read_mac(uint8_t *mac, esp_mac_type_t type)
{
uint32_t regval[2];
uint8_t *data = (uint8_t *)regval;
uint8_t crc;
int i;
if (type > ESP_MAC_BT)
{
wlerr("Input type is error=%d\n", type);
return -1;
}
regval[0] = getreg32(MAC_ADDR0_REG);
regval[1] = getreg32(MAC_ADDR1_REG);
crc = data[6];
for (i = 0; i < MAC_LEN; i++)
{
mac[i] = data[5 - i];
}
if (crc != esp_crc8(mac, MAC_LEN))
{
wlerr("Failed to check MAC address CRC\n");
return -1;
}
if (type == ESP_MAC_WIFI_SOFTAP)
{
#ifdef CONFIG_ESP_MAC_ADDR_UNIVERSE_WIFI_AP
mac[5] += 1;
#else
uint8_t tmp = mac[0];
for (i = 0; i < 64; i++)
{
mac[0] = tmp | 0x02;
mac[0] ^= i << 2;
if (mac[0] != tmp)
{
break;
}
}
if (i >= 64)
{
wlerr("Failed to generate SoftAP MAC\n");
return -1;
}
#endif
}
if (type == ESP_MAC_BT)
{
#ifdef CONFIG_ESP_MAC_ADDR_UNIVERSE_BT
mac[5] += MAC_ADDR_UNIVERSE_BT_OFFSET;
#endif
}
return 0;
}
/****************************************************************************
* Name: esp32_phy_update_country_info
*
@ -1058,107 +925,134 @@ int esp32_phy_update_country_info(const char *country)
}
/****************************************************************************
* Name: esp32_phy_disable
* Name: esp_timer_create
*
* Description:
* Deinitialize PHY hardware
* Create timer with given arguments
*
* Input Parameters:
* None
* create_args - Timer arguments data pointer
* out_handle - Timer handle pointer
*
* Returned Value:
* None
* 0 if success or -1 if fail
*
****************************************************************************/
void esp32_phy_disable(void)
int32_t esp_timer_create(const esp_timer_create_args_t *create_args,
esp_timer_handle_t *out_handle)
{
irqstate_t flags;
flags = enter_critical_section();
int ret;
struct rt_timer_args_s rt_timer_args;
struct rt_timer_s *rt_timer;
g_phy_access_ref--;
rt_timer_args.arg = create_args->arg;
rt_timer_args.callback = create_args->callback;
if (g_phy_access_ref == 0)
ret = rt_timer_create(&rt_timer_args, &rt_timer);
if (ret)
{
/* Disable PHY and RF. */
phy_close_rf();
/* Disable Wi-Fi/BT common peripheral clock.
* Do not disable clock for hardware RNG.
*/
esp32_phy_disable_clock();
wlerr("Failed to create rt_timer error=%d\n", ret);
return ret;
}
leave_critical_section(flags);
*out_handle = (esp_timer_handle_t)rt_timer;
return 0;
}
/****************************************************************************
* Name: esp32_phy_enable
* Name: esp_timer_start_once
*
* Description:
* Initialize PHY hardware
* Start timer with one shot mode
*
* Input Parameters:
* None
* timer - Timer handle pointer
* timeout_us - Timeout value by micro second
*
* Returned Value:
* None
* 0 if success or -1 if fail
*
****************************************************************************/
void esp32_phy_enable(void)
int32_t esp_timer_start_once(esp_timer_handle_t timer, uint64_t timeout_us)
{
static bool debug = false;
irqstate_t flags;
esp_phy_calibration_data_t *cal_data;
if (debug == false)
{
char *phy_version = get_phy_version_str();
wlinfo("phy_version %s\n", phy_version);
debug = true;
}
struct rt_timer_s *rt_timer = (struct rt_timer_s *)timer;
cal_data = kmm_zalloc(sizeof(esp_phy_calibration_data_t));
if (!cal_data)
{
wlerr("ERROR: Failed to allocate PHY calibration data buffer.");
abort();
}
rt_timer_start(rt_timer, timeout_us, false);
flags = enter_critical_section();
return 0;
}
if (g_phy_access_ref == 0)
{
esp32_phy_enable_clock();
if (g_is_phy_calibrated == false)
{
const esp_phy_init_data_t *init_data = esp_phy_get_init_data();
if (init_data == NULL)
{
wlerr("ERROR: Failed to obtain PHY init data");
abort();
}
/****************************************************************************
* Name: esp_timer_start_periodic
*
* Description:
* Start timer with periodic mode
*
* Input Parameters:
* timer - Timer handle pointer
* period - Timeout value by micro second
*
* Returned Value:
* 0 if success or -1 if fail
*
****************************************************************************/
register_chipv7_phy(init_data, cal_data, PHY_RF_CAL_FULL);
esp_phy_release_init_data(init_data);
g_is_phy_calibrated = true;
}
else
{
phy_wakeup_init();
phy_digital_regs_load();
}
int32_t esp_timer_start_periodic(esp_timer_handle_t timer, uint64_t period)
{
struct rt_timer_s *rt_timer = (struct rt_timer_s *)timer;
#ifdef CONFIG_ESP32_BLE
coex_bt_high_prio();
#endif
}
rt_timer_start(rt_timer, period, true);
g_phy_access_ref++;
leave_critical_section(flags);
kmm_free(cal_data);
return 0;
}
/****************************************************************************
* Name: esp_timer_stop
*
* Description:
* Stop timer
*
* Input Parameters:
* timer - Timer handle pointer
*
* Returned Value:
* 0 if success or -1 if fail
*
****************************************************************************/
int32_t esp_timer_stop(esp_timer_handle_t timer)
{
struct rt_timer_s *rt_timer = (struct rt_timer_s *)timer;
rt_timer_stop(rt_timer);
return 0;
}
/****************************************************************************
* Name: esp_timer_delete
*
* Description:
* Delete timer and free resource
*
* Input Parameters:
* timer - Timer handle pointer
*
* Returned Value:
* 0 if success or -1 if fail
*
****************************************************************************/
int32_t esp_timer_delete(esp_timer_handle_t timer)
{
struct rt_timer_s *rt_timer = (struct rt_timer_s *)timer;
rt_timer_delete(rt_timer);
return 0;
}
/****************************************************************************
@ -1397,3 +1291,99 @@ int esp_wireless_deinit(void)
return OK;
}
#ifdef CONFIG_ESP32_WIFI
/****************************************************************************
* Name: esp_wifi_init
*
* Description:
* Initialize Wi-Fi
*
* Input Parameters:
* config - Initialization config parameters
*
* Returned Value:
* 0 if success or others if fail
*
****************************************************************************/
int32_t esp_wifi_init(const wifi_init_config_t *config)
{
int32_t ret;
esp_wifi_power_domain_on();
#ifdef CONFIG_ESP32_WIFI_BT_COEXIST
ret = coex_init();
if (ret)
{
wlerr("ERROR: Failed to initialize coex error=%d\n", ret);
return ret;
}
#endif /* CONFIG_ESP32_WIFI_BT_COEXIST */
esp_wifi_set_log_level();
ret = esp_wifi_init_internal(config);
if (ret)
{
wlerr("Failed to initialize Wi-Fi error=%d\n", ret);
return ret;
}
#if CONFIG_MAC_BB_PD
esp_mac_bb_pd_mem_init();
esp_wifi_internal_set_mac_sleep(true);
#endif
esp_phy_modem_init();
g_wifi_mac_time_update_cb = esp_wifi_internal_update_mac_time;
ret = esp_supplicant_init();
if (ret)
{
wlerr("Failed to initialize WPA supplicant error=%d\n", ret);
esp_wifi_deinit_internal();
return ret;
}
return 0;
}
/****************************************************************************
* Name: esp_wifi_deinit
*
* Description:
* Deinitialize Wi-Fi and free resource
*
* Input Parameters:
* None
*
* Returned Value:
* 0 if success or others if fail
*
****************************************************************************/
int32_t esp_wifi_deinit(void)
{
int ret;
ret = esp_supplicant_deinit();
if (ret)
{
wlerr("Failed to deinitialize supplicant\n");
return ret;
}
ret = esp_wifi_deinit_internal();
if (ret != 0)
{
wlerr("Failed to deinitialize Wi-Fi\n");
return ret;
}
return ret;
}
#endif /* CONFIG_ESP32_WIFI */

207
arch/xtensa/src/esp32/esp32_wireless.h
View file

@ -32,8 +32,16 @@
#include <nuttx/list.h>
#include "xtensa_attr.h"
#include "esp32_rt_timer.h"
#include "espidf_wifi.h"
#include "esp_log.h"
#include "esp_mac.h"
#include "esp_private/phy.h"
#include "esp_private/wifi.h"
#include "esp_random.h"
#include "esp_timer.h"
#include "rom/ets_sys.h"
#include "soc/soc_caps.h"
/****************************************************************************
* Pre-processor Definitions
@ -81,87 +89,6 @@ struct esp_queuecache_s
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: esp_read_mac
*
* Description:
* Read MAC address from efuse
*
* Input Parameters:
* mac - MAC address buffer pointer
* type - MAC address type
*
* Returned Value:
* 0 if success or -1 if fail
*
****************************************************************************/
int32_t esp_read_mac(uint8_t *mac, esp_mac_type_t type);
/****************************************************************************
* Name: esp32_phy_enable
*
* Description:
* Initialize PHY hardware
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
void esp32_phy_enable(void);
/****************************************************************************
* Name: esp32_phy_disable
*
* Description:
* Deinitialize PHY hardware
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
void esp32_phy_disable(void);
/****************************************************************************
* Name: esp32_phy_enable_clock
*
* Description:
* Enable PHY clock
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
void esp32_phy_enable_clock(void);
/****************************************************************************
* Name: esp32_phy_disable_clock
*
* Description:
* Disable PHY clock
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
void esp32_phy_disable_clock(void);
/****************************************************************************
* Functions needed by libphy.a
****************************************************************************/
@ -182,38 +109,6 @@ void esp32_phy_disable_clock(void);
uint32_t IRAM_ATTR esp_dport_access_reg_read(uint32_t reg);
/****************************************************************************
* Name: phy_enter_critical
*
* Description:
* Enter critical state
*
* Input Parameters:
* None
*
* Returned Value:
* CPU PS value
*
****************************************************************************/
uint32_t IRAM_ATTR phy_enter_critical(void);
/****************************************************************************
* Name: phy_exit_critical
*
* Description:
* Exit from critical state
*
* Input Parameters:
* level - CPU PS value
*
* Returned Value:
* None
*
****************************************************************************/
void IRAM_ATTR phy_exit_critical(uint32_t level);
/****************************************************************************
* Name: phy_printf
*
@ -230,6 +125,90 @@ void IRAM_ATTR phy_exit_critical(uint32_t level);
int phy_printf(const char *format, ...) printf_like(1, 2);
/****************************************************************************
* Name: esp_timer_create
*
* Description:
* Create timer with given arguments
*
* Input Parameters:
* create_args - Timer arguments data pointer
* out_handle - Timer handle pointer
*
* Returned Value:
* 0 if success or -1 if fail
*
****************************************************************************/
int32_t esp_timer_create(const esp_timer_create_args_t *create_args,
esp_timer_handle_t *out_handle);
/****************************************************************************
* Name: esp_timer_start_once
*
* Description:
* Start timer with one shot mode
*
* Input Parameters:
* timer - Timer handle pointer
* timeout_us - Timeout value by micro second
*
* Returned Value:
* 0 if success or -1 if fail
*
****************************************************************************/
int32_t esp_timer_start_once(esp_timer_handle_t timer, uint64_t timeout_us);
/****************************************************************************
* Name: esp_timer_start_periodic
*
* Description:
* Start timer with periodic mode
*
* Input Parameters:
* timer - Timer handle pointer
* period - Timeout value by micro second
*
* Returned Value:
* 0 if success or -1 if fail
*
****************************************************************************/
int32_t esp_timer_start_periodic(esp_timer_handle_t timer, uint64_t period);
/****************************************************************************
* Name: esp_timer_stop
*
* Description:
* Stop timer
*
* Input Parameters:
* timer - Timer handle pointer
*
* Returned Value:
* 0 if success or -1 if fail
*
****************************************************************************/
int32_t esp_timer_stop(esp_timer_handle_t timer);
/****************************************************************************
* Name: esp_timer_delete
*
* Description:
* Delete timer and free resource
*
* Input Parameters:
* timer - Timer handle pointer
*
* Returned Value:
* 0 if success or -1 if fail
*
****************************************************************************/
int32_t esp_timer_delete(esp_timer_handle_t timer);
/****************************************************************************
* Name: esp32_phy_update_country_info
*

110
arch/xtensa/src/esp32/hal.mk Normal file
View file

@ -0,0 +1,110 @@
############################################################################
# arch/xtensa/src/esp32/hal.mk
#
# Licensed to the Apache Software Foundation (ASF) under one or more
# contributor license agreements. See the NOTICE file distributed with
# this work for additional information regarding copyright ownership. The
# ASF licenses this file to you under the Apache License, Version 2.0 (the
# "License"); you may not use this file except in compliance with the
# License. You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
# License for the specific language governing permissions and limitations
# under the License.
#
############################################################################
# Include header paths
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)$(DELIM)include
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)efuse$(DELIM)include
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)efuse$(DELIM)private_include
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)efuse$(DELIM)$(CHIP_SERIES)$(DELIM)include
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)efuse$(DELIM)$(CHIP_SERIES)$(DELIM)private_include
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_common$(DELIM)include
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_event$(DELIM)include
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)include
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)include$(DELIM)esp_private
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)include$(DELIM)soc
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)private_include
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)include
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_phy$(DELIM)$(CHIP_SERIES)$(DELIM)include
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_phy$(DELIM)include
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)$(CHIP_SERIES)
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)include
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)include$(DELIM)$(CHIP_SERIES)
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_system$(DELIM)include
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_system$(DELIM)port$(DELIM)include
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_system$(DELIM)port$(DELIM)include$(DELIM)private
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_system$(DELIM)port$(DELIM)public_compat
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_timer$(DELIM)include
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_wifi$(DELIM)include
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)$(CHIP_SERIES)$(DELIM)include
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)include
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)platform_port$(DELIM)include
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)log
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)log$(DELIM)include
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)include
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)include
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)xtensa$(DELIM)$(CHIP_SERIES)$(DELIM)include
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)xtensa$(DELIM)include
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)nuttx$(DELIM)$(CHIP_SERIES)$(DELIM)include
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)nuttx$(DELIM)include
# Linker scripts
ARCHSCRIPT += $(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)$(CHIP_SERIES)$(DELIM)ld$(DELIM)$(CHIP_SERIES).rom.api.ld
ARCHSCRIPT += $(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)$(CHIP_SERIES)$(DELIM)ld$(DELIM)$(CHIP_SERIES).rom.ld
ARCHSCRIPT += $(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)ld$(DELIM)$(CHIP_SERIES).peripherals.ld
# Source files
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)efuse$(DELIM)src$(DELIM)esp_efuse_api.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)efuse$(DELIM)src$(DELIM)esp_efuse_utility.c
# Please note that the following source file depends on `CONFIG_SOC_EFUSE_KEY_PURPOSE_FIELD` and `CONFIG_SOC_EFUSE_CONSISTS_OF_ONE_KEY_BLOCK`
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)efuse$(DELIM)src$(DELIM)efuse_controller$(DELIM)keys$(DELIM)without_key_purposes$(DELIM)three_key_blocks$(DELIM)esp_efuse_api_key.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)efuse$(DELIM)$(CHIP_SERIES)$(DELIM)esp_efuse_fields.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)efuse$(DELIM)$(CHIP_SERIES)$(DELIM)esp_efuse_table.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)efuse$(DELIM)$(CHIP_SERIES)$(DELIM)esp_efuse_utility.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)clk_ctrl_os.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)cpu.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)esp_clk.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)hw_random.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)mac_addr.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)periph_ctrl.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)cpu_region_protect.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)esp_clk_tree.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)rtc_clk.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)rtc_time.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)esp_clk_tree_common.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)regi2c_ctrl.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_phy$(DELIM)src$(DELIM)phy_init.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)patches$(DELIM)esp_rom_wdt.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_system$(DELIM)port$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)clk.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_system$(DELIM)port$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)system_internal.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)$(CHIP_SERIES)$(DELIM)clk_tree_hal.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)$(CHIP_SERIES)$(DELIM)efuse_hal.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)brownout_hal.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)efuse_hal.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)gpio_hal.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)ledc_hal_iram.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)ledc_hal.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)rmt_hal.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)timer_hal_iram.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)timer_hal.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)uart_hal_iram.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)uart_hal.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)log$(DELIM)log_noos.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)log$(DELIM)log.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)gpio_periph.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)ledc_periph.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)rmt_periph.c
CFLAGS += ${DEFINE_PREFIX}ESP_PLATFORM=1

2
arch/xtensa/src/esp32/hardware/esp32_aes.h
View file

@ -23,8 +23,6 @@
/* AES acceleration registers */
#define DR_REG_AES_BASE (0x3ff01000)
#define AES_START_REG ((DR_REG_AES_BASE) + 0x00)
#define AES_IDLE_REG ((DR_REG_AES_BASE) + 0x04)
#define AES_MODE_REG ((DR_REG_AES_BASE) + 0x08)

261
arch/xtensa/src/esp32/hardware/esp32_soc.h
View file

@ -33,6 +33,8 @@
#include <nuttx/bits.h>
#include "soc/soc.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
@ -77,113 +79,6 @@
/* Registers Operation */
#define ETS_UNCACHED_ADDR(addr) (addr)
#define ETS_CACHED_ADDR(addr) (addr)
/* Write value to register */
#define REG_WRITE(_r, _v) (*(volatile uint32_t *)(_r)) = (_v)
/* Read value from register */
#define REG_READ(_r) (*(volatile uint32_t *)(_r))
/* Get bit or get bits from register */
#define REG_GET_BIT(_r, _b) (*(volatile uint32_t*)(_r) & (_b))
/* Set bit or set bits to register */
#define REG_SET_BIT(_r, _b) (*(volatile uint32_t*)(_r) |= (_b))
/* Clear bit or clear bits of register */
#define REG_CLR_BIT(_r, _b) (*(volatile uint32_t*)(_r) &= ~(_b))
/* Set bits of register controlled by mask */
#define REG_SET_BITS(_r, _b, _m) (*(volatile uint32_t*)(_r) = (*(volatile uint32_t*)(_r) & ~(_m)) | ((_b) & (_m)))
/* Get field from register,
* used when _f is not left shifted by _f##_S
*/
#define REG_GET_FIELD(addr, field) ((getreg32(addr) >> (field##_S)) & (field##_V))
/* Set field to register,
* used when _f is not left shifted by _f##_S
*/
#define REG_SET_FIELD(addr, field, val) (modifyreg32((addr), (field##_M), (((uint32_t) val) & (field##_V)) << (field##_S)))
/* Set field value from a variable,
* used when _f is not left shifted by _f##_S
*/
#define VALUE_GET_FIELD(_r, _f) (((_r) >> (_f##_S)) & (_f))
/* Get field value from a variable,
* used when _f is left shifted by _f##_S
*/
#define VALUE_GET_FIELD2(_r, _f) (((_r) & (_f))>> (_f##_S))
/* Set field value to a variable,
* used when _f is not left shifted by _f##_S
*/
#define VALUE_SET_FIELD(_r, _f, _v) ((_r)=(((_r) & ~((_f) << (_f##_S)))|((_v)<<(_f##_S))))
/* Set field value to a variable,
* used when _f is left shifted by _f##_S
*/
#define VALUE_SET_FIELD2(_r, _f, _v) ((_r)=(((_r) & ~(_f))|((_v)<<(_f##_S))))
/* Generate a value from a field value,
* used when _f is not left shifted by _f##_S
*/
#define FIELD_TO_VALUE(_f, _v) (((_v)&(_f))<<_f##_S)
/* Generate a value from a field value,
* used when _f is left shifted by _f##_S
*/
#define FIELD_TO_VALUE2(_f, _v) (((_v)<<_f##_S) & (_f))
/* Read value from register */
#define READ_PERI_REG(addr) (*((volatile uint32_t *)ETS_UNCACHED_ADDR(addr)))
/* Write value to register */
#define WRITE_PERI_REG(addr, val) (*((volatile uint32_t *)ETS_UNCACHED_ADDR(addr))) = (uint32_t)(val)
/* Clear bits of register controlled by mask */
#define CLEAR_PERI_REG_MASK(reg, mask) WRITE_PERI_REG((reg), (READ_PERI_REG(reg)&(~(mask))))
/* Set bits of register controlled by mask */
#define SET_PERI_REG_MASK(reg, mask) WRITE_PERI_REG((reg), (READ_PERI_REG(reg)|(mask)))
/* Get bits of register controlled by mask */
#define GET_PERI_REG_MASK(reg, mask) (READ_PERI_REG(reg) & (mask))
/* Get bits of register controlled by highest bit and lowest bit */
#define GET_PERI_REG_BITS(reg, hipos,lowpos) ((READ_PERI_REG(reg)>>(lowpos))&((1<<((hipos)-(lowpos)+1))-1))
/* Set bits of register controlled by mask and shift */
#define SET_PERI_REG_BITS(reg,bit_map,value,shift) (WRITE_PERI_REG((reg),(READ_PERI_REG(reg)&(~((bit_map)<<(shift))))|(((value) & bit_map)<<(shift)) ))
/* Get field of register */
#define GET_PERI_REG_BITS2(reg, mask,shift) ((READ_PERI_REG(reg)>>(shift))&(mask))
/* Extract the field from the register and shift it to avoid wrong reading */
#define REG_MASK(_reg, _field) (((_reg) & (_field##_M)) >> (_field##_S))
@ -194,65 +89,15 @@
/* Periheral Clock */
#define APB_CLK_FREQ_ROM 26 * 1000000
#define CPU_CLK_FREQ_ROM APB_CLK_FREQ_ROM
#define CPU_CLK_FREQ APB_CLK_FREQ
#define APB_CLK_FREQ 80 * 1000000 /* Unit: Hz */
#define REF_CLK_FREQ (1000000)
#define UART_CLK_FREQ APB_CLK_FREQ
#define MWDT_CLK_FREQ APB_CLK_FREQ
#define TIMER_CLK_FREQ (80000000 >> 4) /* 80MHz divided by 16 */
#define SPI_CLK_DIV 4
#define TICKS_PER_US_ROM 26 /* CPU is 80MHz */
#define DR_REG_DPORT_BASE 0x3ff00000
#define DR_REG_UART_BASE 0x3ff40000
#define DR_REG_SPI1_BASE 0x3ff42000
#define DR_REG_SPI0_BASE 0x3ff43000
#define DR_REG_GPIO_BASE 0x3ff44000
#define DR_REG_GPIO_SD_BASE 0x3ff44f00
#define DR_REG_FE2_BASE 0x3ff45000
#define DR_REG_FE_BASE 0x3ff46000
#define DR_REG_FRC_TIMER_BASE 0x3ff47000
#define DR_REG_RTCCNTL_BASE 0x3ff48000
#define DR_REG_RTCIO_BASE 0x3ff48400
#define DR_REG_SENS_BASE 0x3ff48800
#define DR_REG_IO_MUX_BASE 0x3ff49000
#define DR_REG_EFUSE_BASE 0x3ff5a000
#define DR_REG_RTCMEM0_BASE 0x3ff61000
#define DR_REG_RTCMEM1_BASE 0x3ff62000
#define DR_REG_RTCMEM2_BASE 0x3ff63000
#define DR_REG_HINF_BASE 0x3ff4b000
#define DR_REG_UHCI1_BASE 0x3ff4c000
#define DR_REG_I2S_BASE 0x3ff4f000
#define DR_REG_UART1_BASE 0x3ff50000
#define DR_REG_BT_BASE 0x3ff51000
#define DR_REG_I2C_EXT_BASE 0x3ff53000
#define DR_REG_UHCI0_BASE 0x3ff54000
#define DR_REG_SLCHOST_BASE 0x3ff55000
#define DR_REG_RMT_BASE 0x3ff56000
#define DR_REG_PCNT_BASE 0x3ff57000
#define DR_REG_SLC_BASE 0x3ff58000
#define DR_REG_LEDC_BASE 0x3ff59000
#define DR_REG_EFUSE_BASE 0x3ff5a000
#define DR_REG_SPI_ENCRYPT_BASE 0x3ff5b000
#define DR_REG_NRX_BASE 0x3ff5cc00
#define DR_REG_BB_BASE 0x3ff5d000
#define DR_REG_PWM_BASE 0x3ff5e000
#define DR_REG_TIMERGROUP0_BASE 0x3ff5f000
#define DR_REG_TIMERGROUP1_BASE 0x3ff60000
#define DR_REG_SPI2_BASE 0x3ff64000
#define DR_REG_SPI3_BASE 0x3ff65000
#define DR_REG_I2C1_EXT_BASE 0x3ff67000
#define DR_REG_SDMMC_BASE 0x3ff68000
#define DR_REG_EMAC_BASE 0x3ff69000
#define DR_REG_TWAI_BASE 0x3ff6b000
#define DR_REG_CAN_BASE DR_REG_TWAI_BASE
#define DR_REG_PWM1_BASE 0x3ff6c000
#define DR_REG_I2S1_BASE 0x3ff6d000
#define DR_REG_UART2_BASE 0x3ff6e000
#define DR_REG_PWM2_BASE 0x3ff6f000
#define DR_REG_PWM3_BASE 0x3ff70000
#define DR_REG_TWAI_BASE DR_REG_CAN_BASE
#define PERIPHS_SPI_ENCRYPT_BASEADDR DR_REG_SPI_ENCRYPT_BASE
/* Some AHB addresses can be used instead of DPORT addresses
@ -266,108 +111,14 @@
/* Overall memory map */
#define SOC_DROM_LOW 0x3f400000
#define SOC_DROM_HIGH 0x3f800000
#define SOC_DRAM_LOW 0x3ffae000
#define SOC_DRAM_HIGH 0x40000000
#define SOC_IROM_LOW 0x400d0000
#define SOC_IROM_HIGH 0x40400000
#define SOC_IROM_MASK_LOW 0x40000000
#define SOC_IROM_MASK_HIGH 0x40064f00
#define SOC_CACHE_PRO_LOW 0x40070000
#define SOC_CACHE_PRO_HIGH 0x40078000
#define SOC_CACHE_APP_LOW 0x40078000
#define SOC_CACHE_APP_HIGH 0x40080000
#define SOC_IRAM_LOW 0x40080000
#define SOC_IRAM_HIGH 0x400a0000
#define SOC_RTC_IRAM_LOW 0x400c0000
#define SOC_RTC_IRAM_HIGH 0x400c2000
#define SOC_RTC_DRAM_LOW 0x3ff80000
#define SOC_RTC_DRAM_HIGH 0x3ff82000
#define SOC_RTC_SLOW_LOW 0x50000000
#define SOC_RTC_SLOW_HIGH 0x50002000
#define SOC_EXTRAM_DATA_LOW 0x3f800000
#define SOC_EXTRAM_DATA_HIGH 0x3fc00000
#define SOC_RTC_SLOW_LOW SOC_RTC_DATA_LOW
#define SOC_RTC_SLOW_HIGH SOC_RTC_DATA_HIGH
/* Virtual address 0 */
#define VADDR0_START_ADDR SOC_DROM_LOW
#define VADDR0_END_ADDR (SOC_DROM_HIGH - 1)
/* Interrupt hardware source table
* This table is decided by hardware, don't touch this.
*/
#define ETS_WIFI_MAC_INTR_SOURCE 0 /* Interrupt of Wi-Fi MAC, level */
#define ETS_WIFI_MAC_NMI_SOURCE 1 /* Interrupt of Wi-Fi MAC, NMI, use if MAC have bug to fix in NMI */
#define ETS_WIFI_BB_INTR_SOURCE 2 /* Interrupt of Wi-Fi BB, level, we can do some calibartion */
#define ETS_BT_MAC_INTR_SOURCE 3 /* will be cancelled */
#define ETS_BT_BB_INTR_SOURCE 4 /* Interrupt of BT BB, level */
#define ETS_BT_BB_NMI_SOURCE 5 /* Interrupt of BT BB, NMI, use if BB have bug to fix in NMI */
#define ETS_RWBT_INTR_SOURCE 6 /* Interrupt of RWBT, level */
#define ETS_RWBLE_INTR_SOURCE 7 /* Interrupt of RWBLE, level */
#define ETS_RWBT_NMI_SOURCE 8 /* Interrupt of RWBT, NMI, use if RWBT have bug to fix in NMI */
#define ETS_RWBLE_NMI_SOURCE 9 /* Interrupt of RWBLE, NMI, use if RWBT have bug to fix in NMI */
#define ETS_SLC0_INTR_SOURCE 10 /* Interrupt of SLC0, level */
#define ETS_SLC1_INTR_SOURCE 11 /* Interrupt of SLC1, level */
#define ETS_UHCI0_INTR_SOURCE 12 /* Interrupt of UHCI0, level */
#define ETS_UHCI1_INTR_SOURCE 13 /* Interrupt of UHCI1, level */
#define ETS_TG0_T0_LEVEL_INTR_SOURCE 14 /* Interrupt of TIMER_GROUP0, TIMER0, level, we would like use EDGE for timer if permission */
#define ETS_TG0_T1_LEVEL_INTR_SOURCE 15 /* Interrupt of TIMER_GROUP0, TIMER1, level, we would like use EDGE for timer if permission */
#define ETS_TG0_WDT_LEVEL_INTR_SOURCE 16 /* Interrupt of TIMER_GROUP0, WATCHDOG, level */
#define ETS_TG0_LACT_LEVEL_INTR_SOURCE 17 /* Interrupt of TIMER_GROUP0, LACT, level */
#define ETS_TG1_T0_LEVEL_INTR_SOURCE 18 /* Interrupt of TIMER_GROUP1, TIMER0, level, we would like use EDGE for timer if permission */
#define ETS_TG1_T1_LEVEL_INTR_SOURCE 19 /* Interrupt of TIMER_GROUP1, TIMER1, level, we would like use EDGE for timer if permission */
#define ETS_TG1_WDT_LEVEL_INTR_SOURCE 20 /* Interrupt of TIMER_GROUP1, WATCHDOG, level */
#define ETS_TG1_LACT_LEVEL_INTR_SOURCE 21 /* Interrupt of TIMER_GROUP1, LACT, level */
#define ETS_GPIO_INTR_SOURCE 22 /* Interrupt of GPIO, level */
#define ETS_GPIO_NMI_SOURCE 23 /* Interrupt of GPIO, NMI */
#define ETS_FROM_CPU_INTR0_SOURCE 24 /* Interrupt0 generated from a CPU, level */
#define ETS_FROM_CPU_INTR1_SOURCE 25 /* Interrupt1 generated from a CPU, level */
#define ETS_FROM_CPU_INTR2_SOURCE 26 /* Interrupt2 generated from a CPU, level */
#define ETS_FROM_CPU_INTR3_SOURCE 27 /* Interrupt3 generated from a CPU, level */
#define ETS_SPI0_INTR_SOURCE 28 /* Interrupt of SPI0, level, SPI0 is for Cache Access, do not use this */
#define ETS_SPI1_INTR_SOURCE 29 /* Interrupt of SPI1, level, SPI1 is for flash read/write, do not use this */
#define ETS_SPI2_INTR_SOURCE 30 /* Interrupt of SPI2, level */
#define ETS_SPI3_INTR_SOURCE 31 /* Interrupt of SPI3, level */
#define ETS_I2S0_INTR_SOURCE 32 /* Interrupt of I2S0, level */
#define ETS_I2S1_INTR_SOURCE 33 /* Interrupt of I2S1, level */
#define ETS_UART0_INTR_SOURCE 34 /* Interrupt of UART0, level */
#define ETS_UART1_INTR_SOURCE 35 /* Interrupt of UART1, level */
#define ETS_UART2_INTR_SOURCE 36 /* Interrupt of UART2, level */
#define ETS_SDIO_HOST_INTR_SOURCE 37 /* Interrupt of SD/SDIO/MMC HOST, level */
#define ETS_ETH_MAC_INTR_SOURCE 38 /* Interrupt of ethernet mac, level */
#define ETS_PWM0_INTR_SOURCE 39 /* Interrupt of PWM0, level, Reserved */
#define ETS_PWM1_INTR_SOURCE 40 /* Interrupt of PWM1, level, Reserved */
#define ETS_PWM2_INTR_SOURCE 41 /* Interrupt of PWM2, level */
#define ETS_PWM3_INTR_SOURCE 42 /* Interruot of PWM3, level */
#define ETS_LEDC_INTR_SOURCE 43 /* Interrupt of LED PWM, level */
#define ETS_EFUSE_INTR_SOURCE 44 /* Interrupt of efuse, level, not likely to use */
#define ETS_CAN_INTR_SOURCE 45 /* Interrupt of can, level */
#define ETS_RTC_CORE_INTR_SOURCE 46 /* Interrupt of rtc core, level, include rtc watchdog */
#define ETS_RMT_INTR_SOURCE 47 /* Interrupt of remote controller, level */
#define ETS_PCNT_INTR_SOURCE 48 /* Interrupt of pulse count, level */
#define ETS_I2C_EXT0_INTR_SOURCE 49 /* Interrupt of I2C controller1, level */
#define ETS_I2C_EXT1_INTR_SOURCE 50 /* Interrupt of I2C controller0, level */
#define ETS_RSA_INTR_SOURCE 51 /* Interrupt of RSA accelerator, level */
#define ETS_SPI1_DMA_INTR_SOURCE 52 /* Interrupt of SPI1 DMA, SPI1 is for flash read/write, do not use this */
#define ETS_SPI2_DMA_INTR_SOURCE 53 /* Interrupt of SPI2 DMA, level */
#define ETS_SPI3_DMA_INTR_SOURCE 54 /* Interrupt of SPI3 DMA, level */
#define ETS_WDT_INTR_SOURCE 55 /* will be cancelled */
#define ETS_TIMER1_INTR_SOURCE 56 /* will be cancelled */
#define ETS_TIMER2_INTR_SOURCE 57 /* will be cancelled */
#define ETS_TG0_T0_EDGE_INTR_SOURCE 58 /* Interrupt of TIMER_GROUP0, TIMER0, EDGE */
#define ETS_TG0_T1_EDGE_INTR_SOURCE 59 /* Interrupt of TIMER_GROUP0, TIMER1, EDGE */
#define ETS_TG0_WDT_EDGE_INTR_SOURCE 60 /* Interrupt of TIMER_GROUP0, WATCH DOG, EDGE */
#define ETS_TG0_LACT_EDGE_INTR_SOURCE 61 /* Interrupt of TIMER_GROUP0, LACT, EDGE */
#define ETS_TG1_T0_EDGE_INTR_SOURCE 62 /* Interrupt of TIMER_GROUP1, TIMER0, EDGE */
#define ETS_TG1_T1_EDGE_INTR_SOURCE 63 /* Interrupt of TIMER_GROUP1, TIMER1, EDGE */
#define ETS_TG1_WDT_EDGE_INTR_SOURCE 64 /* Interrupt of TIMER_GROUP1, WATCHDOG, EDGE */
#define ETS_TG1_LACT_EDGE_INTR_SOURCE 65 /* Interrupt of TIMER_GROUP0, LACT, EDGE */
#define ETS_MMU_IA_INTR_SOURCE 66 /* Interrupt of MMU Invalid Access, LEVEL */
#define ETS_MPU_IA_INTR_SOURCE 67 /* Interrupt of MPU Invalid Access, LEVEL */
#define ETS_CACHE_IA_INTR_SOURCE 68 /* Interrupt of Cache Invalied Access, LEVEL */
#define GPIO_STRAP_REG (DR_REG_GPIO_BASE + 0x0038)
/* Interrupt cpu using table */

47
boards/xtensa/esp32/common/scripts/legacy_sections.ld
View file

@ -112,6 +112,7 @@ SECTIONS
*(.wifirxiram .wifirxiram.*)
*(.wifi0iram .wifi0iram.*)
*(.wifiorslpiram .wifiorslpiram.*)
*(.wifislpiram .wifislpiram.*)
*(.wifislprxiram .wifislprxiram.*)
*(.phyiram .phyiram.*)
@ -132,15 +133,39 @@ SECTIONS
. = ALIGN (8);
_sbss = ABSOLUTE(.);
_bss_start = ABSOLUTE(.);
*(EXCLUDE_FILE(*libble_app.a *libbt.a *libbtdm_app.a *libnimble.a) .bss EXCLUDE_FILE(*libble_app.a *libbt.a *libbtdm_app.a *libnimble.a) .bss.*)
*(.ext_ram.bss*)
*(EXCLUDE_FILE(*libble_app.a *libbt.a *libbtdm_app.a *libnimble.a) COMMON)
. = ALIGN(4);
_bt_controller_bss_start = ABSOLUTE(.);
*libble_app.a:(.bss .bss.*)
. = ALIGN(4);
_bt_controller_bss_end = ABSOLUTE(.);
. = ALIGN(4);
_bt_controller_common_start = ABSOLUTE(.);
*libble_app.a:(COMMON)
. = ALIGN(4);
_bt_controller_common_end = ABSOLUTE(.);
. = ALIGN(4);
_bt_bss_start = ABSOLUTE(.);
*libbt.a:(.bss .bss.* COMMON)
. = ALIGN (4);
*libbt.a:(.bss .bss.*)
. = ALIGN(4);
_bt_bss_end = ABSOLUTE(.);
. = ALIGN(4);
_bt_common_start = ABSOLUTE(.);
*libbt.a:(COMMON)
. = ALIGN(4);
_bt_common_end = ABSOLUTE(.);
. = ALIGN(4);
_btdm_bss_start = ABSOLUTE(.);
*libbtdm_app.a:(.bss .bss.* COMMON)
. = ALIGN (4);
*libbtdm_app.a:(.bss .bss.*)
. = ALIGN(4);
_btdm_bss_end = ABSOLUTE(.);
. = ALIGN(4);
_btdm_common_start = ABSOLUTE(.);
*libbtdm_app.a:(COMMON)
. = ALIGN(4);
_btdm_common_end = ABSOLUTE(.);
. = ALIGN (8);
*(.dynsbss)
*(.sbss)
@ -253,6 +278,13 @@ SECTIONS
_srodata = ABSOLUTE(.);
*(.rodata)
*(.rodata.*)
#ifdef CONFIG_ESP32_WIRELESS
*(.rodata_wlog_verbose.*)
*(.rodata_wlog_debug.*)
*(.rodata_wlog_info.*)
*(.rodata_wlog_warning.*)
*(.rodata_wlog_error.*)
#endif
*(.irom1.text) /* catch stray ICACHE_RODATA_ATTR */
*(.gnu.linkonce.r.*)
*(.rodata1)
@ -288,6 +320,13 @@ SECTIONS
*(.xt_except_desc_end)
*(.dynamic)
*(.gnu.version_d)
/* Addresses of memory regions reserved via SOC_RESERVE_MEMORY_REGION() */
soc_reserved_memory_region_start = ABSOLUTE(.);
KEEP (*(.reserved_memory_address))
soc_reserved_memory_region_end = ABSOLUTE(.);
_erodata = ABSOLUTE(.);
/* Literals are also RO data. */
_lit4_start = ABSOLUTE(.);

1
boards/xtensa/esp32/esp32-devkitc/configs/blewifi/defconfig
View file

@ -38,7 +38,6 @@ CONFIG_ESP32_SPIFLASH_SPIFFS=y
CONFIG_ESP32_STORAGE_MTD_SIZE=0x80000
CONFIG_ESP32_UART0=y
CONFIG_ESP32_WIFI=y
CONFIG_ESP32_WIFI_BT_COEXIST=y
CONFIG_ESP32_WIFI_STATION_SOFTAP=y
CONFIG_EXAMPLES_DHCPD=y
CONFIG_EXAMPLE_POWER_SAVE_MIN_MODEM=y

1
boards/xtensa/esp32/esp32-devkitc/src/esp32_ledc.c
View file

@ -33,7 +33,6 @@
#include <arch/board/board.h>
#include "chip.h"
#include "esp32_ledc.h"
/****************************************************************************

2
boards/xtensa/esp32/esp32-devkitc/src/esp32_twai.c
View file

@ -30,8 +30,6 @@
#include <nuttx/can/can.h>
#include <arch/board/board.h>
#include "chip.h"
#include "esp32_twai.h"
#include "esp32-devkitc.h"