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mmcsd:Stuck in 1-bit mode, Removed CONFIG_ARCH_HAVE_SDIO_DELAYED_INVLDT
mmcsd:Remove CONFIG_ARCH_HAVE_SDIO_DELAYED_INVLDT stm32h7:sdmmc remove CONFIG_ARCH_HAVE_SDIO_DELAYED_INVLDT stm32f7:sdmmc remove CONFIG_ARCH_HAVE_SDIO_DELAYED_INVLDT stm32f7:sdmmc WRITE COMPLETE prevent false triggers stm32h7:sdmmc WRITE COMPLETE prevent false triggers While testing PR #2989 on the H7 I noticed that the cards were staying in 1-bit mode. The root cause was that the scr read path was using DMA without an invlidate. This was caused by CONFIG_ARCH_HAVE_SDIO_DELAYED_INVLDT, but the sdmmc driver, did not use the delayed invalidate nor would it work on 8 bytes. The driver fully supported dcache mgt on runt buffers, but the #ifdef CONFIG_ARCH_HAVE_SDIO_DELAYED_INVLDT blocked it. Reviewing the PR that added CONFIG_ARCH_HAVE_SDIO_DELAYED_INVLDT it may have been valid at the time. But after the dcache operations we fixed. It is not necessary and offers no benefit.
This commit is contained in:
David Sidrane
Alan Carvalho de Assis
parent
6061981e37
commit
0c57351f78
7 changed files with 47 additions and 200 deletions
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@ -661,7 +661,6 @@ config STM32F7_STM32F722XX
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default n
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select STM32F7_STM32F72XX
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select ARCH_HAVE_FPU
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select ARCH_HAVE_SDIO_DELAYED_INVLDT
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select ARMV7M_HAVE_ICACHE
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select ARMV7M_HAVE_DCACHE
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select ARMV7M_HAVE_ITCM
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@ -679,7 +678,6 @@ config STM32F7_STM32F723XX
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default n
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select STM32F7_STM32F72XX
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select ARCH_HAVE_FPU
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select ARCH_HAVE_SDIO_DELAYED_INVLDT
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select ARMV7M_HAVE_ICACHE
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select ARMV7M_HAVE_DCACHE
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select ARMV7M_HAVE_ITCM
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@ -696,7 +694,6 @@ config STM32F7_STM32F745XX
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default n
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select STM32F7_STM32F74XX
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select ARCH_HAVE_FPU
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select ARCH_HAVE_SDIO_DELAYED_INVLDT
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select ARMV7M_HAVE_ICACHE
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select ARMV7M_HAVE_DCACHE
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select ARMV7M_HAVE_ITCM
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@ -716,7 +713,6 @@ config STM32F7_STM32F746XX
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default n
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select STM32F7_STM32F74XX
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select ARCH_HAVE_FPU
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select ARCH_HAVE_SDIO_DELAYED_INVLDT
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select ARMV7M_HAVE_ICACHE
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select ARMV7M_HAVE_DCACHE
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select ARMV7M_HAVE_ITCM
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@ -762,7 +758,6 @@ config STM32F7_STM32F765XX
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select STM32F7_STM32F76XX
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select ARCH_HAVE_FPU
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select ARCH_HAVE_DPFPU
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select ARCH_HAVE_SDIO_DELAYED_INVLDT
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select ARMV7M_HAVE_ICACHE
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select ARMV7M_HAVE_DCACHE
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select ARMV7M_HAVE_ITCM
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@ -812,7 +807,6 @@ config STM32F7_STM32F768XX # Revisit When parts released
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select STM32F7_STM32F76XX
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select ARCH_HAVE_FPU
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select ARCH_HAVE_DPFPU
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select ARCH_HAVE_SDIO_DELAYED_INVLDT
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select ARMV7M_HAVE_ICACHE
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select ARMV7M_HAVE_DCACHE
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select ARMV7M_HAVE_ITCM
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@ -839,7 +833,6 @@ config STM32F7_STM32F768AX # Revisit When parts released
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select STM32F7_STM32F76XX
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select ARCH_HAVE_FPU
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select ARCH_HAVE_DPFPU
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select ARCH_HAVE_SDIO_DELAYED_INVLDT
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select ARMV7M_HAVE_ICACHE
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select ARMV7M_HAVE_DCACHE
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select ARMV7M_HAVE_ITCM
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@ -865,7 +858,6 @@ config STM32F7_STM32F769XX
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select STM32F7_STM32F76XX
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select ARCH_HAVE_FPU
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select ARCH_HAVE_DPFPU
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select ARCH_HAVE_SDIO_DELAYED_INVLDT
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select ARMV7M_HAVE_ICACHE
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select ARMV7M_HAVE_DCACHE
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select ARMV7M_HAVE_ITCM
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@ -892,7 +884,6 @@ config STM32F7_STM32F769AX # Revisit When parts released
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select STM32F7_STM32F76XX
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select ARCH_HAVE_FPU
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select ARCH_HAVE_DPFPU
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select ARCH_HAVE_SDIO_DELAYED_INVLDT
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select ARMV7M_HAVE_ICACHE
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select ARMV7M_HAVE_DCACHE
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select ARMV7M_HAVE_ITCM
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@ -918,7 +909,6 @@ config STM32F7_STM32F777XX
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select STM32F7_STM32F77XX
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select ARCH_HAVE_FPU
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select ARCH_HAVE_DPFPU
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select ARCH_HAVE_SDIO_DELAYED_INVLDT
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select ARMV7M_HAVE_ICACHE
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select ARMV7M_HAVE_DCACHE
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select ARMV7M_HAVE_ITCM
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@ -947,7 +937,6 @@ config STM32F7_STM32F778XX # Revisit when parts released
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select STM32F7_STM32F77XX
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select ARCH_HAVE_FPU
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select ARCH_HAVE_DPFPU
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select ARCH_HAVE_SDIO_DELAYED_INVLDT
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select ARMV7M_HAVE_ICACHE
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select ARMV7M_HAVE_DCACHE
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select ARMV7M_HAVE_ITCM
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@ -976,7 +965,6 @@ config STM32F7_STM32F778AX
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select STM32F7_STM32F77XX
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select ARCH_HAVE_FPU
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select ARCH_HAVE_DPFPU
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select ARCH_HAVE_SDIO_DELAYED_INVLDT
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select ARMV7M_HAVE_ICACHE
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select ARMV7M_HAVE_DCACHE
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select ARMV7M_HAVE_ITCM
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@ -1004,7 +992,6 @@ config STM32F7_STM32F779XX
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select STM32F7_STM32F77XX
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select ARCH_HAVE_FPU
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select ARCH_HAVE_DPFPU
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select ARCH_HAVE_SDIO_DELAYED_INVLDT
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select ARMV7M_HAVE_ICACHE
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select ARMV7M_HAVE_DCACHE
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select ARMV7M_HAVE_ITCM
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@ -1033,7 +1020,6 @@ config STM32F7_STM32F779AX
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select STM32F7_STM32F77XX
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select ARCH_HAVE_FPU
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select ARCH_HAVE_DPFPU
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select ARCH_HAVE_SDIO_DELAYED_INVLDT
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select ARMV7M_HAVE_ICACHE
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select ARMV7M_HAVE_DCACHE
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select ARMV7M_HAVE_ITCM
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@ -583,10 +583,6 @@ static int stm32_dmarecvsetup(FAR struct sdio_dev_s *dev,
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FAR uint8_t *buffer, size_t buflen);
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static int stm32_dmasendsetup(FAR struct sdio_dev_s *dev,
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FAR const uint8_t *buffer, size_t buflen);
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#ifdef CONFIG_ARCH_HAVE_SDIO_DELAYED_INVLDT
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static int stm32_dmadelydinvldt(FAR struct sdio_dev_s *dev,
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FAR const uint8_t *buffer, size_t buflen);
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#endif
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#endif /* CONFIG_STM32F7_SDMMC_DMA */
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/* Initialization/uninitialization/reset ************************************/
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@ -636,9 +632,6 @@ struct stm32_dev_s g_sdmmcdev1 =
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#endif
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.dmarecvsetup = stm32_dmarecvsetup,
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.dmasendsetup = stm32_dmasendsetup,
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#ifdef CONFIG_ARCH_HAVE_SDIO_DELAYED_INVLDT
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.dmadelydinvldt = stm32_dmadelydinvldt,
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#endif
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#else
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#ifdef CONFIG_ARCH_HAVE_SDIO_PREFLIGHT
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.dmapreflight = NULL,
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@ -705,9 +698,6 @@ struct stm32_dev_s g_sdmmcdev2 =
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#endif
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.dmarecvsetup = stm32_dmarecvsetup,
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.dmasendsetup = stm32_dmasendsetup,
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#ifdef CONFIG_ARCH_HAVE_SDIO_DELAYED_INVLDT
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.dmadelydinvldt = stm32_dmadelydinvldt,
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#endif
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#endif
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},
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.base = STM32_SDMMC2_BASE,
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@ -1600,7 +1590,14 @@ static void stm32_endtransfer(struct stm32_dev_s *priv,
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static int stm32_sdmmc_rdyinterrupt(int irq, void *context, void *arg)
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{
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struct stm32_dev_s *priv = (struct stm32_dev_s *)arg;
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stm32_endwait(priv, SDIOWAIT_WRCOMPLETE);
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/* Avoid noise, check the state */
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if (stm32_gpioread(priv->d0_gpio))
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{
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stm32_endwait(priv, SDIOWAIT_WRCOMPLETE);
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}
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return OK;
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}
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#endif
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@ -3102,9 +3099,7 @@ static int stm32_dmarecvsetup(FAR struct sdio_dev_s *dev,
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if ((uintptr_t)buffer < DTCM_START ||
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(uintptr_t)buffer + buflen > DTCM_END)
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{
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#if !defined(CONFIG_ARCH_HAVE_SDIO_DELAYED_INVLDT)
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up_invalidate_dcache((uintptr_t)buffer, (uintptr_t)buffer + buflen);
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#endif
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}
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/* Start the DMA */
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@ -3177,11 +3172,7 @@ static int stm32_dmasendsetup(FAR struct sdio_dev_s *dev,
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if ((uintptr_t)buffer < DTCM_START ||
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(uintptr_t)buffer + buflen > DTCM_END)
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{
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#ifdef CONFIG_ARMV7M_DCACHE_WRITETHROUGH
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up_invalidate_dcache((uintptr_t)buffer, (uintptr_t)buffer + buflen);
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#else
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up_flush_dcache((uintptr_t)buffer, (uintptr_t)buffer + buflen);
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#endif
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up_clean_dcache((uintptr_t)buffer, (uintptr_t)buffer + buflen);
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}
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/* Save the source buffer information for use by the interrupt handler */
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@ -3220,44 +3211,6 @@ static int stm32_dmasendsetup(FAR struct sdio_dev_s *dev,
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}
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#endif
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/****************************************************************************
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* Name: stm32_dmadelydinvldt
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*
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* Description:
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* Delayed D-cache invalidation.
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* This function should be called after receive DMA completion to perform
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* D-cache invalidation. This eliminates the need for cache aligned DMA
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* buffers when the D-cache is in store-through mode.
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*
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* Input Parameters:
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* dev - An instance of the SDIO device interface
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* buffer - The memory to DMA into
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* buflen - The size of the DMA transfer in bytes
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*
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* Returned Value:
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* OK on success; a negated errno on failure
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*
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****************************************************************************/
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#if defined(CONFIG_ARCH_HAVE_SDIO_DELAYED_INVLDT) && \
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defined(CONFIG_STM32F7_SDMMC_DMA)
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static int stm32_dmadelydinvldt(FAR struct sdio_dev_s *dev,
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FAR const uint8_t *buffer, size_t buflen)
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{
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/* Invaliate cache to physical memory when not in DTCM memory. */
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if ((uintptr_t)buffer < DTCM_START ||
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(uintptr_t)buffer + buflen > DTCM_END)
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{
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up_invalidate_dcache((uintptr_t)buffer,
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(uintptr_t)buffer + buflen);
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}
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return OK;
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}
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#endif
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/****************************************************************************
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* Name: stm32_callback
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*
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@ -215,7 +215,6 @@ config STM32H7_STM32H7X3XX
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default n
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select ARCH_HAVE_FPU
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select ARCH_HAVE_DPFPU
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select ARCH_HAVE_SDIO_DELAYED_INVLDT
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select ARMV7M_HAVE_ICACHE
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select ARMV7M_HAVE_DCACHE
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select ARMV7M_HAVE_ITCM
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@ -233,7 +232,6 @@ config STM32H7_STM32H7X7XX
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default n
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select ARCH_HAVE_FPU
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select ARCH_HAVE_DPFPU
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select ARCH_HAVE_SDIO_DELAYED_INVLDT
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select ARMV7M_HAVE_ICACHE
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select ARMV7M_HAVE_DCACHE
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select ARMV7M_HAVE_ITCM
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@ -375,8 +375,7 @@ struct stm32_dev_s
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#endif
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uint8_t rxfifo[FIFO_SIZE_IN_BYTES] /* To offload with IDMA */
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__attribute__((aligned(ARMV7M_DCACHE_LINESIZE)));
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#if defined(CONFIG_ARMV7M_DCACHE) && defined(CONFIG_STM32H7_SDMMC_IDMA) && \
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!defined(CONFIG_ARCH_HAVE_SDIO_DELAYED_INVLDT)
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#if defined(CONFIG_ARMV7M_DCACHE) && defined(CONFIG_STM32H7_SDMMC_IDMA)
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bool unaligned_rx; /* read buffer is not cache-line aligned */
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#endif
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};
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@ -448,8 +447,7 @@ static void stm32_datadisable(struct stm32_dev_s *priv);
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#ifndef CONFIG_STM32H7_SDMMC_IDMA
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static void stm32_sendfifo(struct stm32_dev_s *priv);
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static void stm32_recvfifo(struct stm32_dev_s *priv);
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#elif defined(CONFIG_ARMV7M_DCACHE) && \
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!defined(CONFIG_ARCH_HAVE_SDIO_DELAYED_INVLDT)
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#elif defined(CONFIG_ARMV7M_DCACHE)
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static void stm32_recvdma(struct stm32_dev_s *priv);
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#endif
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static void stm32_eventtimeout(wdparm_t arg);
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@ -527,10 +525,6 @@ static int stm32_dmarecvsetup(FAR struct sdio_dev_s *dev,
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FAR uint8_t *buffer, size_t buflen);
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static int stm32_dmasendsetup(FAR struct sdio_dev_s *dev,
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FAR const uint8_t *buffer, size_t buflen);
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# if defined(CONFIG_ARCH_HAVE_SDIO_DELAYED_INVLDT)
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static int stm32_dmadelydinvldt(FAR struct sdio_dev_s *dev,
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FAR const uint8_t *buffer, size_t buflen);
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# endif
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#endif
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/* Initialization/uninitialization/reset ************************************/
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@ -583,9 +577,6 @@ struct stm32_dev_s g_sdmmcdev1 =
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# endif
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.dmarecvsetup = stm32_dmarecvsetup,
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.dmasendsetup = stm32_dmasendsetup,
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# if defined(CONFIG_ARCH_HAVE_SDIO_DELAYED_INVLDT)
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.dmadelydinvldt = stm32_dmadelydinvldt,
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# endif
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#endif
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},
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.base = STM32_SDMMC1_BASE,
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@ -640,9 +631,6 @@ struct stm32_dev_s g_sdmmcdev2 =
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# endif
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.dmarecvsetup = stm32_dmarecvsetup,
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.dmasendsetup = stm32_dmasendsetup,
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# if defined(CONFIG_ARCH_HAVE_SDIO_DELAYED_INVLDT)
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.dmadelydinvldt = stm32_dmadelydinvldt,
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# endif
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#endif
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},
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.base = STM32_SDMMC2_BASE,
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@ -662,8 +650,7 @@ static struct stm32_sampleregs_s g_sampleregs[DEBUG_NSAMPLES];
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#endif
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/* Input dma buffer for unaligned transfers */
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#if defined(CONFIG_ARMV7M_DCACHE) && defined(CONFIG_STM32H7_SDMMC_IDMA) && \
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!defined(CONFIG_ARCH_HAVE_SDIO_DELAYED_INVLDT)
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#if defined(CONFIG_ARMV7M_DCACHE) && defined(CONFIG_STM32H7_SDMMC_IDMA)
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static uint8_t sdmmc_rxbuffer[SDMMC_MAX_BLOCK_SIZE]
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__attribute__((aligned(ARMV7M_DCACHE_LINESIZE)));
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#endif
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@ -1145,8 +1132,7 @@ static void stm32_dataconfig(struct stm32_dev_s *priv, uint32_t timeout,
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{
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DEBUGASSERT((dlen % priv->blocksize) == 0);
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#if defined(CONFIG_STM32H7_SDMMC_IDMA) && defined(CONFIG_ARMV7M_DCACHE) && \
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!defined(CONFIG_ARCH_HAVE_SDIO_DELAYED_INVLDT)
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#if defined(CONFIG_STM32H7_SDMMC_IDMA) && defined(CONFIG_ARMV7M_DCACHE)
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/* If cache is enabled, and this is an unaligned receive,
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* receive one block at a time to the internal buffer
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*/
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@ -1348,8 +1334,7 @@ static void stm32_recvfifo(struct stm32_dev_s *priv)
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*
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****************************************************************************/
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#if defined (CONFIG_STM32H7_SDMMC_IDMA) && defined(CONFIG_ARMV7M_DCACHE) && \
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!defined(CONFIG_ARCH_HAVE_SDIO_DELAYED_INVLDT)
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#if defined (CONFIG_STM32H7_SDMMC_IDMA) && defined(CONFIG_ARMV7M_DCACHE)
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static void stm32_recvdma(struct stm32_dev_s *priv)
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{
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uint32_t dctrl;
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@ -1606,7 +1591,14 @@ static void stm32_sdmmc_fifo_monitor(FAR void *arg)
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static int stm32_sdmmc_rdyinterrupt(int irq, void *context, void *arg)
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{
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struct stm32_dev_s *priv = (struct stm32_dev_s *)arg;
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stm32_endwait(priv, SDIOWAIT_WRCOMPLETE);
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/* Avoid noise, check the state */
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if (stm32_gpioread(priv->d0_gpio))
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{
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stm32_endwait(priv, SDIOWAIT_WRCOMPLETE);
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}
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return OK;
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}
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#endif
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@ -1709,8 +1701,7 @@ static int stm32_sdmmc_interrupt(int irq, void *context, void *arg)
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memcpy(priv->buffer, priv->rxfifo, priv->remaining);
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}
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#else
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# if defined(CONFIG_ARMV7M_DCACHE) && \
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!defined(CONFIG_ARCH_HAVE_SDIO_DELAYED_INVLDT)
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# if defined(CONFIG_ARMV7M_DCACHE)
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if (priv->receivecnt)
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{
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/* Invalidate dcache, and copy the received data into
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@ -3056,8 +3047,9 @@ static int stm32_registercallback(FAR struct sdio_dev_s *dev,
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static int stm32_dmapreflight(FAR struct sdio_dev_s *dev,
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FAR const uint8_t *buffer, size_t buflen)
|
||||
{
|
||||
#if defined(CONFIG_ARMV7M_DCACHE) && !defined(CONFIG_ARMV7M_DCACHE_WRITETHROUGH)
|
||||
struct stm32_dev_s *priv = (struct stm32_dev_s *)dev;
|
||||
|
||||
#endif
|
||||
DEBUGASSERT(priv != NULL && buffer != NULL && buflen > 0);
|
||||
|
||||
/* IDMA must be possible to the buffer */
|
||||
|
|
@ -3080,7 +3072,7 @@ static int stm32_dmapreflight(FAR struct sdio_dev_s *dev,
|
|||
}
|
||||
#endif
|
||||
|
||||
# if defined(CONFIG_ARMV7M_DCACHE) && !defined(CONFIG_ARMV7M_DCACHE_WRITETHROUGH)
|
||||
#if defined(CONFIG_ARMV7M_DCACHE) && !defined(CONFIG_ARMV7M_DCACHE_WRITETHROUGH)
|
||||
/* buffer alignment is required for DMA transfers with dcache in buffered
|
||||
* mode (not write-through) because a) arch_invalidate_dcache could lose
|
||||
* buffered writes and b) arch_flush_dcache could corrupt adjacent memory
|
||||
|
|
@ -3097,7 +3089,7 @@ static int stm32_dmapreflight(FAR struct sdio_dev_s *dev,
|
|||
buffer, buffer + buflen - 1);
|
||||
return -EFAULT;
|
||||
}
|
||||
# endif
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -3129,11 +3121,11 @@ static int stm32_dmarecvsetup(FAR struct sdio_dev_s *dev,
|
|||
struct stm32_dev_s *priv = (struct stm32_dev_s *)dev;
|
||||
|
||||
DEBUGASSERT(priv != NULL && buffer != NULL && buflen > 0);
|
||||
# if defined(CONFIG_ARCH_HAVE_SDIO_PREFLIGHT)
|
||||
#if defined(CONFIG_ARCH_HAVE_SDIO_PREFLIGHT)
|
||||
DEBUGASSERT(stm32_dmapreflight(dev, buffer, buflen) == 0);
|
||||
# else
|
||||
# if defined(CONFIG_ARMV7M_DCACHE) && \
|
||||
!defined(CONFIG_ARCH_HAVE_SDIO_DELAYED_INVLDT)
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_ARMV7M_DCACHE)
|
||||
if (((uintptr_t)buffer & (ARMV7M_DCACHE_LINESIZE - 1)) != 0 ||
|
||||
(buflen & (ARMV7M_DCACHE_LINESIZE - 1)) != 0)
|
||||
{
|
||||
|
|
@ -3153,8 +3145,7 @@ static int stm32_dmarecvsetup(FAR struct sdio_dev_s *dev,
|
|||
|
||||
priv->unaligned_rx = false;
|
||||
}
|
||||
# endif
|
||||
# endif
|
||||
#endif
|
||||
|
||||
/* Reset the DPSM configuration */
|
||||
|
||||
|
|
@ -3180,15 +3171,14 @@ static int stm32_dmarecvsetup(FAR struct sdio_dev_s *dev,
|
|||
|
||||
/* Configure the RX DMA */
|
||||
|
||||
# if defined(CONFIG_ARMV7M_DCACHE) && \
|
||||
!defined(CONFIG_ARCH_HAVE_SDIO_DELAYED_INVLDT)
|
||||
#if defined(CONFIG_ARMV7M_DCACHE)
|
||||
if (priv->unaligned_rx)
|
||||
{
|
||||
sdmmc_putreg32(priv, (uintptr_t)sdmmc_rxbuffer,
|
||||
STM32_SDMMC_IDMABASE0R_OFFSET);
|
||||
}
|
||||
else
|
||||
# endif
|
||||
#endif
|
||||
{
|
||||
sdmmc_putreg32(priv, (uintptr_t)priv->buffer,
|
||||
STM32_SDMMC_IDMABASE0R_OFFSET);
|
||||
|
|
@ -3232,14 +3222,13 @@ static int stm32_dmasendsetup(FAR struct sdio_dev_s *dev,
|
|||
struct stm32_dev_s *priv = (struct stm32_dev_s *)dev;
|
||||
|
||||
DEBUGASSERT(priv != NULL && buffer != NULL && buflen > 0);
|
||||
# if defined(CONFIG_ARCH_HAVE_SDIO_PREFLIGHT)
|
||||
#if defined(CONFIG_ARCH_HAVE_SDIO_PREFLIGHT)
|
||||
DEBUGASSERT(stm32_dmapreflight(dev, buffer, buflen) == 0);
|
||||
# endif
|
||||
#endif
|
||||
|
||||
# if defined(CONFIG_ARMV7M_DCACHE) && \
|
||||
!defined(CONFIG_ARCH_HAVE_SDIO_DELAYED_INVLDT)
|
||||
#if defined(CONFIG_ARMV7M_DCACHE)
|
||||
priv->unaligned_rx = false;
|
||||
# endif
|
||||
#endif
|
||||
|
||||
/* Reset the DPSM configuration */
|
||||
|
||||
|
|
@ -3252,14 +3241,14 @@ static int stm32_dmasendsetup(FAR struct sdio_dev_s *dev,
|
|||
|
||||
/* Flush cache to physical memory when not in DTCM memory */
|
||||
|
||||
# if defined(CONFIG_ARMV7M_DCACHE) && \
|
||||
#if defined(CONFIG_ARMV7M_DCACHE) && \
|
||||
!defined(CONFIG_ARMV7M_DCACHE_WRITETHROUGH)
|
||||
if ((uintptr_t)buffer < DTCM_START ||
|
||||
(uintptr_t)buffer + buflen > DTCM_END)
|
||||
{
|
||||
up_clean_dcache((uintptr_t)buffer, (uintptr_t)buffer + buflen);
|
||||
}
|
||||
# endif
|
||||
#endif
|
||||
|
||||
/* Save the source buffer information for use by the interrupt handler */
|
||||
|
||||
|
|
@ -3288,43 +3277,6 @@ static int stm32_dmasendsetup(FAR struct sdio_dev_s *dev,
|
|||
}
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_dmadelydinvldt
|
||||
*
|
||||
* Description:
|
||||
* Delayed D-cache invalidation.
|
||||
* This function should be called after receive DMA completion to perform
|
||||
* D-cache invalidation. This eliminates the need for cache aligned DMA
|
||||
* buffers when the D-cache is in store-through mode.
|
||||
*
|
||||
* Input Parameters:
|
||||
* dev - An instance of the SDIO device interface
|
||||
* buffer - The memory to DMA into
|
||||
* buflen - The size of the DMA transfer in bytes
|
||||
*
|
||||
* Returned Value:
|
||||
* OK on success; a negated errno on failure
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#if defined(CONFIG_STM32H7_SDMMC_IDMA) && \
|
||||
defined(CONFIG_ARCH_HAVE_SDIO_DELAYED_INVLDT)
|
||||
static int stm32_dmadelydinvldt(FAR struct sdio_dev_s *dev,
|
||||
FAR const uint8_t *buffer, size_t buflen)
|
||||
{
|
||||
/* Invalidate cache to physical memory when not in DTCM memory. */
|
||||
|
||||
if ((uintptr_t)buffer < DTCM_START ||
|
||||
(uintptr_t)buffer + buflen > DTCM_END)
|
||||
{
|
||||
up_invalidate_dcache((uintptr_t)buffer,
|
||||
(uintptr_t)buffer + buflen);
|
||||
}
|
||||
|
||||
return OK;
|
||||
}
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_callback
|
||||
*
|
||||
|
|
@ -3457,11 +3409,11 @@ FAR struct sdio_dev_s *sdio_initialize(int slotno)
|
|||
|
||||
priv = &g_sdmmcdev1;
|
||||
|
||||
# if defined(CONFIG_SDMMC1_WIDTH_D1_ONLY)
|
||||
#if defined(CONFIG_SDMMC1_WIDTH_D1_ONLY)
|
||||
priv->onebit = true;
|
||||
# else
|
||||
#else
|
||||
priv->onebit = false;
|
||||
# endif
|
||||
#endif
|
||||
|
||||
/* Configure GPIOs for 4-bit, wide-bus operation (the chip is capable
|
||||
* of 8-bit wide bus operation but D4-D7 are not configured).
|
||||
|
|
@ -3470,16 +3422,16 @@ FAR struct sdio_dev_s *sdio_initialize(int slotno)
|
|||
* utility in the scope of the board support package.
|
||||
*/
|
||||
|
||||
# ifndef CONFIG_SDIO_MUXBUS
|
||||
#ifndef CONFIG_SDIO_MUXBUS
|
||||
stm32_configgpio(SDMMC1_SDIO_PULL(GPIO_SDMMC1_D0));
|
||||
# ifndef CONFIG_SDMMC1_WIDTH_D1_ONLY
|
||||
# ifndef CONFIG_SDMMC1_WIDTH_D1_ONLY
|
||||
stm32_configgpio(SDMMC1_SDIO_PULL(GPIO_SDMMC1_D1));
|
||||
stm32_configgpio(SDMMC1_SDIO_PULL(GPIO_SDMMC1_D2));
|
||||
stm32_configgpio(SDMMC1_SDIO_PULL(GPIO_SDMMC1_D3));
|
||||
# endif
|
||||
# endif
|
||||
stm32_configgpio(GPIO_SDMMC1_CK);
|
||||
stm32_configgpio(SDMMC1_SDIO_PULL(GPIO_SDMMC1_CMD));
|
||||
# endif
|
||||
#endif
|
||||
}
|
||||
else
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -17,10 +17,6 @@ config ARCH_HAVE_SDIO_PREFLIGHT
|
|||
bool
|
||||
default n
|
||||
|
||||
config ARCH_HAVE_SDIO_DELAYED_INVLDT
|
||||
bool
|
||||
default n
|
||||
|
||||
menuconfig MMCSD
|
||||
bool "MMC/SD Driver Support"
|
||||
default n
|
||||
|
|
|
|||
|
|
@ -1477,9 +1477,6 @@ static ssize_t mmcsd_readsingle(FAR struct mmcsd_state_s *priv,
|
|||
|
||||
ret = mmcsd_eventwait(priv, SDIOWAIT_TIMEOUT | SDIOWAIT_ERROR,
|
||||
MMCSD_BLOCK_RDATADELAY);
|
||||
#ifdef CONFIG_SDIO_DMA
|
||||
SDIO_DMADELYDINVLDT(priv->dev, buffer, priv->blocksize);
|
||||
#endif
|
||||
if (ret != OK)
|
||||
{
|
||||
ferr("ERROR: CMD17 transfer failed: %d\n", ret);
|
||||
|
|
@ -1623,9 +1620,6 @@ static ssize_t mmcsd_readmultiple(FAR struct mmcsd_state_s *priv,
|
|||
/* Send STOP_TRANSMISSION */
|
||||
|
||||
ret = mmcsd_stoptransmission(priv);
|
||||
#ifdef CONFIG_SDIO_DMA
|
||||
SDIO_DMADELYDINVLDT(priv->dev, buffer, priv->blocksize * nblocks);
|
||||
#endif
|
||||
|
||||
if (ret != OK)
|
||||
{
|
||||
|
|
@ -2886,9 +2880,6 @@ static int mmcsd_read_csd(FAR struct mmcsd_state_s *priv)
|
|||
|
||||
ret = mmcsd_eventwait(priv, SDIOWAIT_TIMEOUT | SDIOWAIT_ERROR,
|
||||
MMCSD_BLOCK_RDATADELAY);
|
||||
#ifdef CONFIG_SDIO_DMA
|
||||
SDIO_DMADELYDINVLDT(priv->dev, buffer, 512);
|
||||
#endif
|
||||
if (ret != OK)
|
||||
{
|
||||
ferr("ERROR: CMD17 transfer failed: %d\n", ret);
|
||||
|
|
|
|||
|
|
@ -809,31 +809,6 @@
|
|||
# define SDIO_DMARECVSETUP(dev,buffer,len) (-ENOSYS)
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Name: SDIO_DMADELYDINVLDT
|
||||
*
|
||||
* Description:
|
||||
* Delayed D-cache invalidation.
|
||||
* This function should be called after receive DMA completion to perform
|
||||
* D-cache invalidation. This eliminates the need for cache aligned DMA
|
||||
* buffers when the D-cache is in store-through mode.
|
||||
*
|
||||
* Input Parameters:
|
||||
* dev - An instance of the SDIO device interface
|
||||
* buffer - The memory to DMA from
|
||||
* buflen - The size of the DMA transfer in bytes
|
||||
*
|
||||
* Returned Value:
|
||||
* OK on success; a negated errno on failure
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#if defined(CONFIG_SDIO_DMA) && defined(CONFIG_ARCH_HAVE_SDIO_DELAYED_INVLDT)
|
||||
# define SDIO_DMADELYDINVLDT(dev,buffer,len) ((dev)->dmadelydinvldt(dev,buffer,len))
|
||||
#else
|
||||
# define SDIO_DMADELYDINVLDT(dev,buffer,len) (OK)
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Name: SDIO_DMASENDSETUP
|
||||
*
|
||||
|
|
@ -969,10 +944,6 @@ struct sdio_dev_s
|
|||
size_t buflen);
|
||||
int (*dmasendsetup)(FAR struct sdio_dev_s *dev,
|
||||
FAR const uint8_t *buffer, size_t buflen);
|
||||
#ifdef CONFIG_ARCH_HAVE_SDIO_DELAYED_INVLDT
|
||||
int (*dmadelydinvldt)(FAR struct sdio_dev_s *dev,
|
||||
FAR const uint8_t *buffer, size_t buflen);
|
||||
#endif
|
||||
#endif /* CONFIG_SDIO_DMA */
|
||||
};
|
||||
|
||||
|
|
|
|||
Loading…
Reference in a new issue