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mmcsd:Stuck in 1-bit mode, Removed CONFIG_ARCH_HAVE_SDIO_DELAYED_INVLDT

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mmcsd:Remove CONFIG_ARCH_HAVE_SDIO_DELAYED_INVLDT
   stm32h7:sdmmc remove CONFIG_ARCH_HAVE_SDIO_DELAYED_INVLDT
   stm32f7:sdmmc remove CONFIG_ARCH_HAVE_SDIO_DELAYED_INVLDT
   stm32f7:sdmmc WRITE COMPLETE prevent false triggers
   stm32h7:sdmmc WRITE COMPLETE prevent false triggers

   While testing PR #2989 on the H7 I noticed that the cards
   were staying in 1-bit mode. The root cause was that the
   scr read path was using DMA without an invlidate.

   This was caused by CONFIG_ARCH_HAVE_SDIO_DELAYED_INVLDT,
   but the sdmmc driver, did not use the delayed invalidate
   nor would it work on 8 bytes.

   The driver fully supported dcache mgt on runt buffers, but
   the #ifdef CONFIG_ARCH_HAVE_SDIO_DELAYED_INVLDT blocked it.

   Reviewing the PR that added CONFIG_ARCH_HAVE_SDIO_DELAYED_INVLDT
   it may have been valid at the time. But after the dcache operations
   we fixed. It is not necessary and offers no benefit.
This commit is contained in:
David Sidrane 2021-03-12 04:42:04 -08:00 committed by Alan Carvalho de Assis
parent 6061981e37
commit 0c57351f78
7 changed files with 47 additions and 200 deletions
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14
arch/arm/src/stm32f7/Kconfig
View file

@ -661,7 +661,6 @@ config STM32F7_STM32F722XX
default n default n
select STM32F7_STM32F72XX select STM32F7_STM32F72XX
select ARCH_HAVE_FPU select ARCH_HAVE_FPU
select ARCH_HAVE_SDIO_DELAYED_INVLDT
select ARMV7M_HAVE_ICACHE select ARMV7M_HAVE_ICACHE
select ARMV7M_HAVE_DCACHE select ARMV7M_HAVE_DCACHE
select ARMV7M_HAVE_ITCM select ARMV7M_HAVE_ITCM
@ -679,7 +678,6 @@ config STM32F7_STM32F723XX
default n default n
select STM32F7_STM32F72XX select STM32F7_STM32F72XX
select ARCH_HAVE_FPU select ARCH_HAVE_FPU
select ARCH_HAVE_SDIO_DELAYED_INVLDT
select ARMV7M_HAVE_ICACHE select ARMV7M_HAVE_ICACHE
select ARMV7M_HAVE_DCACHE select ARMV7M_HAVE_DCACHE
select ARMV7M_HAVE_ITCM select ARMV7M_HAVE_ITCM
@ -696,7 +694,6 @@ config STM32F7_STM32F745XX
default n default n
select STM32F7_STM32F74XX select STM32F7_STM32F74XX
select ARCH_HAVE_FPU select ARCH_HAVE_FPU
select ARCH_HAVE_SDIO_DELAYED_INVLDT
select ARMV7M_HAVE_ICACHE select ARMV7M_HAVE_ICACHE
select ARMV7M_HAVE_DCACHE select ARMV7M_HAVE_DCACHE
select ARMV7M_HAVE_ITCM select ARMV7M_HAVE_ITCM
@ -716,7 +713,6 @@ config STM32F7_STM32F746XX
default n default n
select STM32F7_STM32F74XX select STM32F7_STM32F74XX
select ARCH_HAVE_FPU select ARCH_HAVE_FPU
select ARCH_HAVE_SDIO_DELAYED_INVLDT
select ARMV7M_HAVE_ICACHE select ARMV7M_HAVE_ICACHE
select ARMV7M_HAVE_DCACHE select ARMV7M_HAVE_DCACHE
select ARMV7M_HAVE_ITCM select ARMV7M_HAVE_ITCM
@ -762,7 +758,6 @@ config STM32F7_STM32F765XX
select STM32F7_STM32F76XX select STM32F7_STM32F76XX
select ARCH_HAVE_FPU select ARCH_HAVE_FPU
select ARCH_HAVE_DPFPU select ARCH_HAVE_DPFPU
select ARCH_HAVE_SDIO_DELAYED_INVLDT
select ARMV7M_HAVE_ICACHE select ARMV7M_HAVE_ICACHE
select ARMV7M_HAVE_DCACHE select ARMV7M_HAVE_DCACHE
select ARMV7M_HAVE_ITCM select ARMV7M_HAVE_ITCM
@ -812,7 +807,6 @@ config STM32F7_STM32F768XX # Revisit When parts released
select STM32F7_STM32F76XX select STM32F7_STM32F76XX
select ARCH_HAVE_FPU select ARCH_HAVE_FPU
select ARCH_HAVE_DPFPU select ARCH_HAVE_DPFPU
select ARCH_HAVE_SDIO_DELAYED_INVLDT
select ARMV7M_HAVE_ICACHE select ARMV7M_HAVE_ICACHE
select ARMV7M_HAVE_DCACHE select ARMV7M_HAVE_DCACHE
select ARMV7M_HAVE_ITCM select ARMV7M_HAVE_ITCM
@ -839,7 +833,6 @@ config STM32F7_STM32F768AX # Revisit When parts released
select STM32F7_STM32F76XX select STM32F7_STM32F76XX
select ARCH_HAVE_FPU select ARCH_HAVE_FPU
select ARCH_HAVE_DPFPU select ARCH_HAVE_DPFPU
select ARCH_HAVE_SDIO_DELAYED_INVLDT
select ARMV7M_HAVE_ICACHE select ARMV7M_HAVE_ICACHE
select ARMV7M_HAVE_DCACHE select ARMV7M_HAVE_DCACHE
select ARMV7M_HAVE_ITCM select ARMV7M_HAVE_ITCM
@ -865,7 +858,6 @@ config STM32F7_STM32F769XX
select STM32F7_STM32F76XX select STM32F7_STM32F76XX
select ARCH_HAVE_FPU select ARCH_HAVE_FPU
select ARCH_HAVE_DPFPU select ARCH_HAVE_DPFPU
select ARCH_HAVE_SDIO_DELAYED_INVLDT
select ARMV7M_HAVE_ICACHE select ARMV7M_HAVE_ICACHE
select ARMV7M_HAVE_DCACHE select ARMV7M_HAVE_DCACHE
select ARMV7M_HAVE_ITCM select ARMV7M_HAVE_ITCM
@ -892,7 +884,6 @@ config STM32F7_STM32F769AX # Revisit When parts released
select STM32F7_STM32F76XX select STM32F7_STM32F76XX
select ARCH_HAVE_FPU select ARCH_HAVE_FPU
select ARCH_HAVE_DPFPU select ARCH_HAVE_DPFPU
select ARCH_HAVE_SDIO_DELAYED_INVLDT
select ARMV7M_HAVE_ICACHE select ARMV7M_HAVE_ICACHE
select ARMV7M_HAVE_DCACHE select ARMV7M_HAVE_DCACHE
select ARMV7M_HAVE_ITCM select ARMV7M_HAVE_ITCM
@ -918,7 +909,6 @@ config STM32F7_STM32F777XX
select STM32F7_STM32F77XX select STM32F7_STM32F77XX
select ARCH_HAVE_FPU select ARCH_HAVE_FPU
select ARCH_HAVE_DPFPU select ARCH_HAVE_DPFPU
select ARCH_HAVE_SDIO_DELAYED_INVLDT
select ARMV7M_HAVE_ICACHE select ARMV7M_HAVE_ICACHE
select ARMV7M_HAVE_DCACHE select ARMV7M_HAVE_DCACHE
select ARMV7M_HAVE_ITCM select ARMV7M_HAVE_ITCM
@ -947,7 +937,6 @@ config STM32F7_STM32F778XX # Revisit when parts released
select STM32F7_STM32F77XX select STM32F7_STM32F77XX
select ARCH_HAVE_FPU select ARCH_HAVE_FPU
select ARCH_HAVE_DPFPU select ARCH_HAVE_DPFPU
select ARCH_HAVE_SDIO_DELAYED_INVLDT
select ARMV7M_HAVE_ICACHE select ARMV7M_HAVE_ICACHE
select ARMV7M_HAVE_DCACHE select ARMV7M_HAVE_DCACHE
select ARMV7M_HAVE_ITCM select ARMV7M_HAVE_ITCM
@ -976,7 +965,6 @@ config STM32F7_STM32F778AX
select STM32F7_STM32F77XX select STM32F7_STM32F77XX
select ARCH_HAVE_FPU select ARCH_HAVE_FPU
select ARCH_HAVE_DPFPU select ARCH_HAVE_DPFPU
select ARCH_HAVE_SDIO_DELAYED_INVLDT
select ARMV7M_HAVE_ICACHE select ARMV7M_HAVE_ICACHE
select ARMV7M_HAVE_DCACHE select ARMV7M_HAVE_DCACHE
select ARMV7M_HAVE_ITCM select ARMV7M_HAVE_ITCM
@ -1004,7 +992,6 @@ config STM32F7_STM32F779XX
select STM32F7_STM32F77XX select STM32F7_STM32F77XX
select ARCH_HAVE_FPU select ARCH_HAVE_FPU
select ARCH_HAVE_DPFPU select ARCH_HAVE_DPFPU
select ARCH_HAVE_SDIO_DELAYED_INVLDT
select ARMV7M_HAVE_ICACHE select ARMV7M_HAVE_ICACHE
select ARMV7M_HAVE_DCACHE select ARMV7M_HAVE_DCACHE
select ARMV7M_HAVE_ITCM select ARMV7M_HAVE_ITCM
@ -1033,7 +1020,6 @@ config STM32F7_STM32F779AX
select STM32F7_STM32F77XX select STM32F7_STM32F77XX
select ARCH_HAVE_FPU select ARCH_HAVE_FPU
select ARCH_HAVE_DPFPU select ARCH_HAVE_DPFPU
select ARCH_HAVE_SDIO_DELAYED_INVLDT
select ARMV7M_HAVE_ICACHE select ARMV7M_HAVE_ICACHE
select ARMV7M_HAVE_DCACHE select ARMV7M_HAVE_DCACHE
select ARMV7M_HAVE_ITCM select ARMV7M_HAVE_ITCM

65
arch/arm/src/stm32f7/stm32_sdmmc.c
View file

@ -583,10 +583,6 @@ static int stm32_dmarecvsetup(FAR struct sdio_dev_s *dev,
FAR uint8_t *buffer, size_t buflen); FAR uint8_t *buffer, size_t buflen);
static int stm32_dmasendsetup(FAR struct sdio_dev_s *dev, static int stm32_dmasendsetup(FAR struct sdio_dev_s *dev,
FAR const uint8_t *buffer, size_t buflen); FAR const uint8_t *buffer, size_t buflen);
#ifdef CONFIG_ARCH_HAVE_SDIO_DELAYED_INVLDT
static int stm32_dmadelydinvldt(FAR struct sdio_dev_s *dev,
FAR const uint8_t *buffer, size_t buflen);
#endif
#endif /* CONFIG_STM32F7_SDMMC_DMA */ #endif /* CONFIG_STM32F7_SDMMC_DMA */
/* Initialization/uninitialization/reset ************************************/ /* Initialization/uninitialization/reset ************************************/
@ -636,9 +632,6 @@ struct stm32_dev_s g_sdmmcdev1 =
#endif #endif
.dmarecvsetup = stm32_dmarecvsetup, .dmarecvsetup = stm32_dmarecvsetup,
.dmasendsetup = stm32_dmasendsetup, .dmasendsetup = stm32_dmasendsetup,
#ifdef CONFIG_ARCH_HAVE_SDIO_DELAYED_INVLDT
.dmadelydinvldt = stm32_dmadelydinvldt,
#endif
#else #else
#ifdef CONFIG_ARCH_HAVE_SDIO_PREFLIGHT #ifdef CONFIG_ARCH_HAVE_SDIO_PREFLIGHT
.dmapreflight = NULL, .dmapreflight = NULL,
@ -705,9 +698,6 @@ struct stm32_dev_s g_sdmmcdev2 =
#endif #endif
.dmarecvsetup = stm32_dmarecvsetup, .dmarecvsetup = stm32_dmarecvsetup,
.dmasendsetup = stm32_dmasendsetup, .dmasendsetup = stm32_dmasendsetup,
#ifdef CONFIG_ARCH_HAVE_SDIO_DELAYED_INVLDT
.dmadelydinvldt = stm32_dmadelydinvldt,
#endif
#endif #endif
}, },
.base = STM32_SDMMC2_BASE, .base = STM32_SDMMC2_BASE,
@ -1600,7 +1590,14 @@ static void stm32_endtransfer(struct stm32_dev_s *priv,
static int stm32_sdmmc_rdyinterrupt(int irq, void *context, void *arg) static int stm32_sdmmc_rdyinterrupt(int irq, void *context, void *arg)
{ {
struct stm32_dev_s *priv = (struct stm32_dev_s *)arg; struct stm32_dev_s *priv = (struct stm32_dev_s *)arg;
stm32_endwait(priv, SDIOWAIT_WRCOMPLETE);
/* Avoid noise, check the state */
if (stm32_gpioread(priv->d0_gpio))
{
stm32_endwait(priv, SDIOWAIT_WRCOMPLETE);
}
return OK; return OK;
} }
#endif #endif
@ -3102,9 +3099,7 @@ static int stm32_dmarecvsetup(FAR struct sdio_dev_s *dev,
if ((uintptr_t)buffer < DTCM_START || if ((uintptr_t)buffer < DTCM_START ||
(uintptr_t)buffer + buflen > DTCM_END) (uintptr_t)buffer + buflen > DTCM_END)
{ {
#if !defined(CONFIG_ARCH_HAVE_SDIO_DELAYED_INVLDT)
up_invalidate_dcache((uintptr_t)buffer, (uintptr_t)buffer + buflen); up_invalidate_dcache((uintptr_t)buffer, (uintptr_t)buffer + buflen);
#endif
} }
/* Start the DMA */ /* Start the DMA */
@ -3177,11 +3172,7 @@ static int stm32_dmasendsetup(FAR struct sdio_dev_s *dev,
if ((uintptr_t)buffer < DTCM_START || if ((uintptr_t)buffer < DTCM_START ||
(uintptr_t)buffer + buflen > DTCM_END) (uintptr_t)buffer + buflen > DTCM_END)
{ {
#ifdef CONFIG_ARMV7M_DCACHE_WRITETHROUGH up_clean_dcache((uintptr_t)buffer, (uintptr_t)buffer + buflen);
up_invalidate_dcache((uintptr_t)buffer, (uintptr_t)buffer + buflen);
#else
up_flush_dcache((uintptr_t)buffer, (uintptr_t)buffer + buflen);
#endif
} }
/* Save the source buffer information for use by the interrupt handler */ /* Save the source buffer information for use by the interrupt handler */
@ -3220,44 +3211,6 @@ static int stm32_dmasendsetup(FAR struct sdio_dev_s *dev,
} }
#endif #endif
/****************************************************************************
* Name: stm32_dmadelydinvldt
*
* Description:
* Delayed D-cache invalidation.
* This function should be called after receive DMA completion to perform
* D-cache invalidation. This eliminates the need for cache aligned DMA
* buffers when the D-cache is in store-through mode.
*
* Input Parameters:
* dev - An instance of the SDIO device interface
* buffer - The memory to DMA into
* buflen - The size of the DMA transfer in bytes
*
* Returned Value:
* OK on success; a negated errno on failure
*
****************************************************************************/
#if defined(CONFIG_ARCH_HAVE_SDIO_DELAYED_INVLDT) && \
defined(CONFIG_STM32F7_SDMMC_DMA)
static int stm32_dmadelydinvldt(FAR struct sdio_dev_s *dev,
FAR const uint8_t *buffer, size_t buflen)
{
/* Invaliate cache to physical memory when not in DTCM memory. */
if ((uintptr_t)buffer < DTCM_START ||
(uintptr_t)buffer + buflen > DTCM_END)
{
up_invalidate_dcache((uintptr_t)buffer,
(uintptr_t)buffer + buflen);
}
return OK;
}
#endif
/**************************************************************************** /****************************************************************************
* Name: stm32_callback * Name: stm32_callback
* *

2
arch/arm/src/stm32h7/Kconfig
View file

@ -215,7 +215,6 @@ config STM32H7_STM32H7X3XX
default n default n
select ARCH_HAVE_FPU select ARCH_HAVE_FPU
select ARCH_HAVE_DPFPU select ARCH_HAVE_DPFPU
select ARCH_HAVE_SDIO_DELAYED_INVLDT
select ARMV7M_HAVE_ICACHE select ARMV7M_HAVE_ICACHE
select ARMV7M_HAVE_DCACHE select ARMV7M_HAVE_DCACHE
select ARMV7M_HAVE_ITCM select ARMV7M_HAVE_ITCM
@ -233,7 +232,6 @@ config STM32H7_STM32H7X7XX
default n default n
select ARCH_HAVE_FPU select ARCH_HAVE_FPU
select ARCH_HAVE_DPFPU select ARCH_HAVE_DPFPU
select ARCH_HAVE_SDIO_DELAYED_INVLDT
select ARMV7M_HAVE_ICACHE select ARMV7M_HAVE_ICACHE
select ARMV7M_HAVE_DCACHE select ARMV7M_HAVE_DCACHE
select ARMV7M_HAVE_ITCM select ARMV7M_HAVE_ITCM

124
arch/arm/src/stm32h7/stm32_sdmmc.c
View file

@ -375,8 +375,7 @@ struct stm32_dev_s
#endif #endif
uint8_t rxfifo[FIFO_SIZE_IN_BYTES] /* To offload with IDMA */ uint8_t rxfifo[FIFO_SIZE_IN_BYTES] /* To offload with IDMA */
__attribute__((aligned(ARMV7M_DCACHE_LINESIZE))); __attribute__((aligned(ARMV7M_DCACHE_LINESIZE)));
#if defined(CONFIG_ARMV7M_DCACHE) && defined(CONFIG_STM32H7_SDMMC_IDMA) && \ #if defined(CONFIG_ARMV7M_DCACHE) && defined(CONFIG_STM32H7_SDMMC_IDMA)
!defined(CONFIG_ARCH_HAVE_SDIO_DELAYED_INVLDT)
bool unaligned_rx; /* read buffer is not cache-line aligned */ bool unaligned_rx; /* read buffer is not cache-line aligned */
#endif #endif
}; };
@ -448,8 +447,7 @@ static void stm32_datadisable(struct stm32_dev_s *priv);
#ifndef CONFIG_STM32H7_SDMMC_IDMA #ifndef CONFIG_STM32H7_SDMMC_IDMA
static void stm32_sendfifo(struct stm32_dev_s *priv); static void stm32_sendfifo(struct stm32_dev_s *priv);
static void stm32_recvfifo(struct stm32_dev_s *priv); static void stm32_recvfifo(struct stm32_dev_s *priv);
#elif defined(CONFIG_ARMV7M_DCACHE) && \ #elif defined(CONFIG_ARMV7M_DCACHE)
!defined(CONFIG_ARCH_HAVE_SDIO_DELAYED_INVLDT)
static void stm32_recvdma(struct stm32_dev_s *priv); static void stm32_recvdma(struct stm32_dev_s *priv);
#endif #endif
static void stm32_eventtimeout(wdparm_t arg); static void stm32_eventtimeout(wdparm_t arg);
@ -527,10 +525,6 @@ static int stm32_dmarecvsetup(FAR struct sdio_dev_s *dev,
FAR uint8_t *buffer, size_t buflen); FAR uint8_t *buffer, size_t buflen);
static int stm32_dmasendsetup(FAR struct sdio_dev_s *dev, static int stm32_dmasendsetup(FAR struct sdio_dev_s *dev,
FAR const uint8_t *buffer, size_t buflen); FAR const uint8_t *buffer, size_t buflen);
# if defined(CONFIG_ARCH_HAVE_SDIO_DELAYED_INVLDT)
static int stm32_dmadelydinvldt(FAR struct sdio_dev_s *dev,
FAR const uint8_t *buffer, size_t buflen);
# endif
#endif #endif
/* Initialization/uninitialization/reset ************************************/ /* Initialization/uninitialization/reset ************************************/
@ -583,9 +577,6 @@ struct stm32_dev_s g_sdmmcdev1 =
# endif # endif
.dmarecvsetup = stm32_dmarecvsetup, .dmarecvsetup = stm32_dmarecvsetup,
.dmasendsetup = stm32_dmasendsetup, .dmasendsetup = stm32_dmasendsetup,
# if defined(CONFIG_ARCH_HAVE_SDIO_DELAYED_INVLDT)
.dmadelydinvldt = stm32_dmadelydinvldt,
# endif
#endif #endif
}, },
.base = STM32_SDMMC1_BASE, .base = STM32_SDMMC1_BASE,
@ -640,9 +631,6 @@ struct stm32_dev_s g_sdmmcdev2 =
# endif # endif
.dmarecvsetup = stm32_dmarecvsetup, .dmarecvsetup = stm32_dmarecvsetup,
.dmasendsetup = stm32_dmasendsetup, .dmasendsetup = stm32_dmasendsetup,
# if defined(CONFIG_ARCH_HAVE_SDIO_DELAYED_INVLDT)
.dmadelydinvldt = stm32_dmadelydinvldt,
# endif
#endif #endif
}, },
.base = STM32_SDMMC2_BASE, .base = STM32_SDMMC2_BASE,
@ -662,8 +650,7 @@ static struct stm32_sampleregs_s g_sampleregs[DEBUG_NSAMPLES];
#endif #endif
/* Input dma buffer for unaligned transfers */ /* Input dma buffer for unaligned transfers */
#if defined(CONFIG_ARMV7M_DCACHE) && defined(CONFIG_STM32H7_SDMMC_IDMA) && \ #if defined(CONFIG_ARMV7M_DCACHE) && defined(CONFIG_STM32H7_SDMMC_IDMA)
!defined(CONFIG_ARCH_HAVE_SDIO_DELAYED_INVLDT)
static uint8_t sdmmc_rxbuffer[SDMMC_MAX_BLOCK_SIZE] static uint8_t sdmmc_rxbuffer[SDMMC_MAX_BLOCK_SIZE]
__attribute__((aligned(ARMV7M_DCACHE_LINESIZE))); __attribute__((aligned(ARMV7M_DCACHE_LINESIZE)));
#endif #endif
@ -1145,8 +1132,7 @@ static void stm32_dataconfig(struct stm32_dev_s *priv, uint32_t timeout,
{ {
DEBUGASSERT((dlen % priv->blocksize) == 0); DEBUGASSERT((dlen % priv->blocksize) == 0);
#if defined(CONFIG_STM32H7_SDMMC_IDMA) && defined(CONFIG_ARMV7M_DCACHE) && \ #if defined(CONFIG_STM32H7_SDMMC_IDMA) && defined(CONFIG_ARMV7M_DCACHE)
!defined(CONFIG_ARCH_HAVE_SDIO_DELAYED_INVLDT)
/* If cache is enabled, and this is an unaligned receive, /* If cache is enabled, and this is an unaligned receive,
* receive one block at a time to the internal buffer * receive one block at a time to the internal buffer
*/ */
@ -1348,8 +1334,7 @@ static void stm32_recvfifo(struct stm32_dev_s *priv)
* *
****************************************************************************/ ****************************************************************************/
#if defined (CONFIG_STM32H7_SDMMC_IDMA) && defined(CONFIG_ARMV7M_DCACHE) && \ #if defined (CONFIG_STM32H7_SDMMC_IDMA) && defined(CONFIG_ARMV7M_DCACHE)
!defined(CONFIG_ARCH_HAVE_SDIO_DELAYED_INVLDT)
static void stm32_recvdma(struct stm32_dev_s *priv) static void stm32_recvdma(struct stm32_dev_s *priv)
{ {
uint32_t dctrl; uint32_t dctrl;
@ -1606,7 +1591,14 @@ static void stm32_sdmmc_fifo_monitor(FAR void *arg)
static int stm32_sdmmc_rdyinterrupt(int irq, void *context, void *arg) static int stm32_sdmmc_rdyinterrupt(int irq, void *context, void *arg)
{ {
struct stm32_dev_s *priv = (struct stm32_dev_s *)arg; struct stm32_dev_s *priv = (struct stm32_dev_s *)arg;
stm32_endwait(priv, SDIOWAIT_WRCOMPLETE);
/* Avoid noise, check the state */
if (stm32_gpioread(priv->d0_gpio))
{
stm32_endwait(priv, SDIOWAIT_WRCOMPLETE);
}
return OK; return OK;
} }
#endif #endif
@ -1709,8 +1701,7 @@ static int stm32_sdmmc_interrupt(int irq, void *context, void *arg)
memcpy(priv->buffer, priv->rxfifo, priv->remaining); memcpy(priv->buffer, priv->rxfifo, priv->remaining);
} }
#else #else
# if defined(CONFIG_ARMV7M_DCACHE) && \ # if defined(CONFIG_ARMV7M_DCACHE)
!defined(CONFIG_ARCH_HAVE_SDIO_DELAYED_INVLDT)
if (priv->receivecnt) if (priv->receivecnt)
{ {
/* Invalidate dcache, and copy the received data into /* Invalidate dcache, and copy the received data into
@ -3056,8 +3047,9 @@ static int stm32_registercallback(FAR struct sdio_dev_s *dev,
static int stm32_dmapreflight(FAR struct sdio_dev_s *dev, static int stm32_dmapreflight(FAR struct sdio_dev_s *dev,
FAR const uint8_t *buffer, size_t buflen) FAR const uint8_t *buffer, size_t buflen)
{ {
#if defined(CONFIG_ARMV7M_DCACHE) && !defined(CONFIG_ARMV7M_DCACHE_WRITETHROUGH)
struct stm32_dev_s *priv = (struct stm32_dev_s *)dev; struct stm32_dev_s *priv = (struct stm32_dev_s *)dev;
#endif
DEBUGASSERT(priv != NULL && buffer != NULL && buflen > 0); DEBUGASSERT(priv != NULL && buffer != NULL && buflen > 0);
/* IDMA must be possible to the buffer */ /* IDMA must be possible to the buffer */
@ -3080,7 +3072,7 @@ static int stm32_dmapreflight(FAR struct sdio_dev_s *dev,
} }
#endif #endif
# if defined(CONFIG_ARMV7M_DCACHE) && !defined(CONFIG_ARMV7M_DCACHE_WRITETHROUGH) #if defined(CONFIG_ARMV7M_DCACHE) && !defined(CONFIG_ARMV7M_DCACHE_WRITETHROUGH)
/* buffer alignment is required for DMA transfers with dcache in buffered /* buffer alignment is required for DMA transfers with dcache in buffered
* mode (not write-through) because a) arch_invalidate_dcache could lose * mode (not write-through) because a) arch_invalidate_dcache could lose
* buffered writes and b) arch_flush_dcache could corrupt adjacent memory * buffered writes and b) arch_flush_dcache could corrupt adjacent memory
@ -3097,7 +3089,7 @@ static int stm32_dmapreflight(FAR struct sdio_dev_s *dev,
buffer, buffer + buflen - 1); buffer, buffer + buflen - 1);
return -EFAULT; return -EFAULT;
} }
# endif #endif
return 0; return 0;
} }
@ -3129,11 +3121,11 @@ static int stm32_dmarecvsetup(FAR struct sdio_dev_s *dev,
struct stm32_dev_s *priv = (struct stm32_dev_s *)dev; struct stm32_dev_s *priv = (struct stm32_dev_s *)dev;
DEBUGASSERT(priv != NULL && buffer != NULL && buflen > 0); DEBUGASSERT(priv != NULL && buffer != NULL && buflen > 0);
# if defined(CONFIG_ARCH_HAVE_SDIO_PREFLIGHT) #if defined(CONFIG_ARCH_HAVE_SDIO_PREFLIGHT)
DEBUGASSERT(stm32_dmapreflight(dev, buffer, buflen) == 0); DEBUGASSERT(stm32_dmapreflight(dev, buffer, buflen) == 0);
# else #endif
# if defined(CONFIG_ARMV7M_DCACHE) && \
!defined(CONFIG_ARCH_HAVE_SDIO_DELAYED_INVLDT) #if defined(CONFIG_ARMV7M_DCACHE)
if (((uintptr_t)buffer & (ARMV7M_DCACHE_LINESIZE - 1)) != 0 || if (((uintptr_t)buffer & (ARMV7M_DCACHE_LINESIZE - 1)) != 0 ||
(buflen & (ARMV7M_DCACHE_LINESIZE - 1)) != 0) (buflen & (ARMV7M_DCACHE_LINESIZE - 1)) != 0)
{ {
@ -3153,8 +3145,7 @@ static int stm32_dmarecvsetup(FAR struct sdio_dev_s *dev,
priv->unaligned_rx = false; priv->unaligned_rx = false;
} }
# endif #endif
# endif
/* Reset the DPSM configuration */ /* Reset the DPSM configuration */
@ -3180,15 +3171,14 @@ static int stm32_dmarecvsetup(FAR struct sdio_dev_s *dev,
/* Configure the RX DMA */ /* Configure the RX DMA */
# if defined(CONFIG_ARMV7M_DCACHE) && \ #if defined(CONFIG_ARMV7M_DCACHE)
!defined(CONFIG_ARCH_HAVE_SDIO_DELAYED_INVLDT)
if (priv->unaligned_rx) if (priv->unaligned_rx)
{ {
sdmmc_putreg32(priv, (uintptr_t)sdmmc_rxbuffer, sdmmc_putreg32(priv, (uintptr_t)sdmmc_rxbuffer,
STM32_SDMMC_IDMABASE0R_OFFSET); STM32_SDMMC_IDMABASE0R_OFFSET);
} }
else else
# endif #endif
{ {
sdmmc_putreg32(priv, (uintptr_t)priv->buffer, sdmmc_putreg32(priv, (uintptr_t)priv->buffer,
STM32_SDMMC_IDMABASE0R_OFFSET); STM32_SDMMC_IDMABASE0R_OFFSET);
@ -3232,14 +3222,13 @@ static int stm32_dmasendsetup(FAR struct sdio_dev_s *dev,
struct stm32_dev_s *priv = (struct stm32_dev_s *)dev; struct stm32_dev_s *priv = (struct stm32_dev_s *)dev;
DEBUGASSERT(priv != NULL && buffer != NULL && buflen > 0); DEBUGASSERT(priv != NULL && buffer != NULL && buflen > 0);
# if defined(CONFIG_ARCH_HAVE_SDIO_PREFLIGHT) #if defined(CONFIG_ARCH_HAVE_SDIO_PREFLIGHT)
DEBUGASSERT(stm32_dmapreflight(dev, buffer, buflen) == 0); DEBUGASSERT(stm32_dmapreflight(dev, buffer, buflen) == 0);
# endif #endif
# if defined(CONFIG_ARMV7M_DCACHE) && \ #if defined(CONFIG_ARMV7M_DCACHE)
!defined(CONFIG_ARCH_HAVE_SDIO_DELAYED_INVLDT)
priv->unaligned_rx = false; priv->unaligned_rx = false;
# endif #endif
/* Reset the DPSM configuration */ /* Reset the DPSM configuration */
@ -3252,14 +3241,14 @@ static int stm32_dmasendsetup(FAR struct sdio_dev_s *dev,
/* Flush cache to physical memory when not in DTCM memory */ /* Flush cache to physical memory when not in DTCM memory */
# if defined(CONFIG_ARMV7M_DCACHE) && \ #if defined(CONFIG_ARMV7M_DCACHE) && \
!defined(CONFIG_ARMV7M_DCACHE_WRITETHROUGH) !defined(CONFIG_ARMV7M_DCACHE_WRITETHROUGH)
if ((uintptr_t)buffer < DTCM_START || if ((uintptr_t)buffer < DTCM_START ||
(uintptr_t)buffer + buflen > DTCM_END) (uintptr_t)buffer + buflen > DTCM_END)
{ {
up_clean_dcache((uintptr_t)buffer, (uintptr_t)buffer + buflen); up_clean_dcache((uintptr_t)buffer, (uintptr_t)buffer + buflen);
} }
# endif #endif
/* Save the source buffer information for use by the interrupt handler */ /* Save the source buffer information for use by the interrupt handler */
@ -3288,43 +3277,6 @@ static int stm32_dmasendsetup(FAR struct sdio_dev_s *dev,
} }
#endif #endif
/****************************************************************************
* Name: stm32_dmadelydinvldt
*
* Description:
* Delayed D-cache invalidation.
* This function should be called after receive DMA completion to perform
* D-cache invalidation. This eliminates the need for cache aligned DMA
* buffers when the D-cache is in store-through mode.
*
* Input Parameters:
* dev - An instance of the SDIO device interface
* buffer - The memory to DMA into
* buflen - The size of the DMA transfer in bytes
*
* Returned Value:
* OK on success; a negated errno on failure
*
****************************************************************************/
#if defined(CONFIG_STM32H7_SDMMC_IDMA) && \
defined(CONFIG_ARCH_HAVE_SDIO_DELAYED_INVLDT)
static int stm32_dmadelydinvldt(FAR struct sdio_dev_s *dev,
FAR const uint8_t *buffer, size_t buflen)
{
/* Invalidate cache to physical memory when not in DTCM memory. */
if ((uintptr_t)buffer < DTCM_START ||
(uintptr_t)buffer + buflen > DTCM_END)
{
up_invalidate_dcache((uintptr_t)buffer,
(uintptr_t)buffer + buflen);
}
return OK;
}
#endif
/**************************************************************************** /****************************************************************************
* Name: stm32_callback * Name: stm32_callback
* *
@ -3457,11 +3409,11 @@ FAR struct sdio_dev_s *sdio_initialize(int slotno)
priv = &g_sdmmcdev1; priv = &g_sdmmcdev1;
# if defined(CONFIG_SDMMC1_WIDTH_D1_ONLY) #if defined(CONFIG_SDMMC1_WIDTH_D1_ONLY)
priv->onebit = true; priv->onebit = true;
# else #else
priv->onebit = false; priv->onebit = false;
# endif #endif
/* Configure GPIOs for 4-bit, wide-bus operation (the chip is capable /* Configure GPIOs for 4-bit, wide-bus operation (the chip is capable
* of 8-bit wide bus operation but D4-D7 are not configured). * of 8-bit wide bus operation but D4-D7 are not configured).
@ -3470,16 +3422,16 @@ FAR struct sdio_dev_s *sdio_initialize(int slotno)
* utility in the scope of the board support package. * utility in the scope of the board support package.
*/ */
# ifndef CONFIG_SDIO_MUXBUS #ifndef CONFIG_SDIO_MUXBUS
stm32_configgpio(SDMMC1_SDIO_PULL(GPIO_SDMMC1_D0)); stm32_configgpio(SDMMC1_SDIO_PULL(GPIO_SDMMC1_D0));
# ifndef CONFIG_SDMMC1_WIDTH_D1_ONLY # ifndef CONFIG_SDMMC1_WIDTH_D1_ONLY
stm32_configgpio(SDMMC1_SDIO_PULL(GPIO_SDMMC1_D1)); stm32_configgpio(SDMMC1_SDIO_PULL(GPIO_SDMMC1_D1));
stm32_configgpio(SDMMC1_SDIO_PULL(GPIO_SDMMC1_D2)); stm32_configgpio(SDMMC1_SDIO_PULL(GPIO_SDMMC1_D2));
stm32_configgpio(SDMMC1_SDIO_PULL(GPIO_SDMMC1_D3)); stm32_configgpio(SDMMC1_SDIO_PULL(GPIO_SDMMC1_D3));
# endif # endif
stm32_configgpio(GPIO_SDMMC1_CK); stm32_configgpio(GPIO_SDMMC1_CK);
stm32_configgpio(SDMMC1_SDIO_PULL(GPIO_SDMMC1_CMD)); stm32_configgpio(SDMMC1_SDIO_PULL(GPIO_SDMMC1_CMD));
# endif #endif
} }
else else
#endif #endif

4
drivers/mmcsd/Kconfig
View file

@ -17,10 +17,6 @@ config ARCH_HAVE_SDIO_PREFLIGHT
bool bool
default n default n
config ARCH_HAVE_SDIO_DELAYED_INVLDT
bool
default n
menuconfig MMCSD menuconfig MMCSD
bool "MMC/SD Driver Support" bool "MMC/SD Driver Support"
default n default n

9
drivers/mmcsd/mmcsd_sdio.c
View file

@ -1477,9 +1477,6 @@ static ssize_t mmcsd_readsingle(FAR struct mmcsd_state_s *priv,
ret = mmcsd_eventwait(priv, SDIOWAIT_TIMEOUT | SDIOWAIT_ERROR, ret = mmcsd_eventwait(priv, SDIOWAIT_TIMEOUT | SDIOWAIT_ERROR,
MMCSD_BLOCK_RDATADELAY); MMCSD_BLOCK_RDATADELAY);
#ifdef CONFIG_SDIO_DMA
SDIO_DMADELYDINVLDT(priv->dev, buffer, priv->blocksize);
#endif
if (ret != OK) if (ret != OK)
{ {
ferr("ERROR: CMD17 transfer failed: %d\n", ret); ferr("ERROR: CMD17 transfer failed: %d\n", ret);
@ -1623,9 +1620,6 @@ static ssize_t mmcsd_readmultiple(FAR struct mmcsd_state_s *priv,
/* Send STOP_TRANSMISSION */ /* Send STOP_TRANSMISSION */
ret = mmcsd_stoptransmission(priv); ret = mmcsd_stoptransmission(priv);
#ifdef CONFIG_SDIO_DMA
SDIO_DMADELYDINVLDT(priv->dev, buffer, priv->blocksize * nblocks);
#endif
if (ret != OK) if (ret != OK)
{ {
@ -2886,9 +2880,6 @@ static int mmcsd_read_csd(FAR struct mmcsd_state_s *priv)
ret = mmcsd_eventwait(priv, SDIOWAIT_TIMEOUT | SDIOWAIT_ERROR, ret = mmcsd_eventwait(priv, SDIOWAIT_TIMEOUT | SDIOWAIT_ERROR,
MMCSD_BLOCK_RDATADELAY); MMCSD_BLOCK_RDATADELAY);
#ifdef CONFIG_SDIO_DMA
SDIO_DMADELYDINVLDT(priv->dev, buffer, 512);
#endif
if (ret != OK) if (ret != OK)
{ {
ferr("ERROR: CMD17 transfer failed: %d\n", ret); ferr("ERROR: CMD17 transfer failed: %d\n", ret);

29
include/nuttx/sdio.h
View file

@ -809,31 +809,6 @@
# define SDIO_DMARECVSETUP(dev,buffer,len) (-ENOSYS) # define SDIO_DMARECVSETUP(dev,buffer,len) (-ENOSYS)
#endif #endif
/****************************************************************************
* Name: SDIO_DMADELYDINVLDT
*
* Description:
* Delayed D-cache invalidation.
* This function should be called after receive DMA completion to perform
* D-cache invalidation. This eliminates the need for cache aligned DMA
* buffers when the D-cache is in store-through mode.
*
* Input Parameters:
* dev - An instance of the SDIO device interface
* buffer - The memory to DMA from
* buflen - The size of the DMA transfer in bytes
*
* Returned Value:
* OK on success; a negated errno on failure
*
****************************************************************************/
#if defined(CONFIG_SDIO_DMA) && defined(CONFIG_ARCH_HAVE_SDIO_DELAYED_INVLDT)
# define SDIO_DMADELYDINVLDT(dev,buffer,len) ((dev)->dmadelydinvldt(dev,buffer,len))
#else
# define SDIO_DMADELYDINVLDT(dev,buffer,len) (OK)
#endif
/**************************************************************************** /****************************************************************************
* Name: SDIO_DMASENDSETUP * Name: SDIO_DMASENDSETUP
* *
@ -969,10 +944,6 @@ struct sdio_dev_s
size_t buflen); size_t buflen);
int (*dmasendsetup)(FAR struct sdio_dev_s *dev, int (*dmasendsetup)(FAR struct sdio_dev_s *dev,
FAR const uint8_t *buffer, size_t buflen); FAR const uint8_t *buffer, size_t buflen);
#ifdef CONFIG_ARCH_HAVE_SDIO_DELAYED_INVLDT
int (*dmadelydinvldt)(FAR struct sdio_dev_s *dev,
FAR const uint8_t *buffer, size_t buflen);
#endif
#endif /* CONFIG_SDIO_DMA */ #endif /* CONFIG_SDIO_DMA */
}; };