nuttx/nuttx-mirror
1
2
Fork 0
mirror of https://github.com/apache/nuttx.git synced 2025-01-13 01:38:36 +08:00
Code Issues Projects Releases Packages Wiki Activity Actions

Merge 0945bc0fb8 into 39780fdae1

Browse source
This commit is contained in:
nuttxs 2025-01-12 00:17:46 +08:00 committed by GitHub
commit 0ed79fe857
No known key found for this signature in database
GPG key ID: B5690EEEBB952194
2 changed files with 12 additions and 0 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

6
arch/xtensa/src/esp32s3/esp32s3_tim.c
View file

@ -39,6 +39,7 @@
#include "soc/periph_defs.h"
#include "esp_private/periph_ctrl.h"
#include "hardware/esp32s3_system.h"
/****************************************************************************
* Private Types
@ -937,6 +938,8 @@ struct esp32s3_tim_dev_s *esp32s3_tim_init(int timer)
case ESP32S3_TIMER0:
{
tim = &g_esp32s3_tim0_priv;
modifyreg32(SYSTEM_PERIP_CLK_EN0_REG, 0, SYSTEM_TIMERGROUP_CLK_EN);
modifyreg32(SYSTEM_PERIP_RST_EN0_REG, SYSTEM_TIMERGROUP_RST_M, 0);
break;
}
#endif
@ -945,6 +948,9 @@ struct esp32s3_tim_dev_s *esp32s3_tim_init(int timer)
case ESP32S3_TIMER1:
{
tim = &g_esp32s3_tim1_priv;
modifyreg32(SYSTEM_PERIP_CLK_EN0_REG, 0,
SYSTEM_TIMERGROUP1_CLK_EN);
modifyreg32(SYSTEM_PERIP_RST_EN0_REG, SYSTEM_TIMERGROUP1_RST_M, 0);
break;
}
#endif

6
arch/xtensa/src/esp32s3/esp32s3_wdt.c
View file

@ -33,6 +33,7 @@
#include "hardware/esp32s3_rtccntl.h"
#include "hardware/esp32s3_tim.h"
#include "hardware/esp32s3_efuse.h"
#include "hardware/esp32s3_system.h"
#include "esp32s3_irq.h"
#include "esp32s3_rtc_gpio.h"
@ -991,6 +992,8 @@ struct esp32s3_wdt_dev_s *esp32s3_wdt_init(enum esp32s3_wdt_inst_e wdt_id)
case ESP32S3_WDT_MWDT0:
{
wdt = &g_esp32s3_mwdt0_priv;
modifyreg32(SYSTEM_PERIP_CLK_EN0_REG, 0, SYSTEM_TIMERGROUP_CLK_EN);
modifyreg32(SYSTEM_PERIP_RST_EN0_REG, SYSTEM_TIMERGROUP_RST_M, 0);
break;
}
@ -1000,6 +1003,9 @@ struct esp32s3_wdt_dev_s *esp32s3_wdt_init(enum esp32s3_wdt_inst_e wdt_id)
case ESP32S3_WDT_MWDT1:
{
wdt = &g_esp32s3_mwdt1_priv;
modifyreg32(SYSTEM_PERIP_CLK_EN0_REG, 0,
SYSTEM_TIMERGROUP1_CLK_EN);
modifyreg32(SYSTEM_PERIP_RST_EN0_REG, SYSTEM_TIMERGROUP1_RST_M, 0);
break;
}
#endif