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Merge remote-tracking branch 'origin/master' into composite

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This commit is contained in:
Gregory Nutt 2017-07-07 20:26:53 -06:00
commit 0f9ad16e18
259 changed files with 4356 additions and 2308 deletions
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136
arch/arm/include/stm32/chip.h
View file

@ -92,7 +92,7 @@
# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */
# undef CONFIG_STM32_STM32F33XX /* STM32F33xxx family */
# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */
# undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx families */
# undef CONFIG_STM32_STM32F4XXX /* STM32F4xxxx family */
# define STM32_NFSMC 0 /* No FSMC */
# define STM32_NATIM 0 /* No advanced timers */
# define STM32_NGTIM 3 /* 16-bit general up/down timers TIM2-4 with DMA */
@ -133,7 +133,7 @@
# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */
# undef CONFIG_STM32_STM32F33XX /* STM32F33xxx family */
# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */
# undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx families */
# undef CONFIG_STM32_STM32F4XXX /* STM32F4xxxx family */
# define STM32_NFSMC 0 /* No FSMC */
# define STM32_NATIM 0 /* No advanced timers */
# define STM32_NGTIM 3 /* 16-bit general up/down timers TIM2-4 with DMA */
@ -174,7 +174,7 @@
# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */
# undef CONFIG_STM32_STM32F33XX /* STM32F33xxx family */
# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */
# undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx families */
# undef CONFIG_STM32_STM32F4XXX /* STM32F4xxxx family */
# define STM32_NFSMC 0 /* No FSMC */
# define STM32_NATIM 0 /* No advanced timers */
# define STM32_NGTIM 3 /* 16-bit general up/down timers TIM2-4 with DMA */
@ -215,7 +215,7 @@
# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */
# undef CONFIG_STM32_STM32F33XX /* STM32F33xxx family */
# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */
# undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx families */
# undef CONFIG_STM32_STM32F4XXX /* STM32F4xxxx family */
# define STM32_NFSMC 0 /* No FSMC */
# define STM32_NATIM 0 /* No advanced timers */
# define STM32_NGTIM 3 /* 16-bit general up/down timers TIM2-4 with DMA */
@ -256,7 +256,7 @@
# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */
# undef CONFIG_STM32_STM32F33XX /* STM32F33xxx family */
# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */
# undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx families */
# undef CONFIG_STM32_STM32F4XXX /* STM32F4xxxx family */
# define STM32_NFSMC 0 /* No FSMC */
# define STM32_NATIM 0 /* No advanced timers */
# define STM32_NGTIM 3 /* 16-bit general up/down timers TIM2-4 with DMA */
@ -297,7 +297,7 @@
# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */
# undef CONFIG_STM32_STM32F33XX /* STM32F33xxx family */
# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */
# undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx families */
# undef CONFIG_STM32_STM32F4XXX /* STM32F4xxxx family */
# define STM32_NFSMC 0 /* No FSMC */
# define STM32_NATIM 0 /* No advanced timers */
# define STM32_NGTIM 3 /* 16-bit general up/down timers TIM2-4 with DMA */
@ -337,7 +337,7 @@
# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */
# undef CONFIG_STM32_STM32F33XX /* STM32F33xxx family */
# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */
# undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx families */
# undef CONFIG_STM32_STM32F4XXX /* STM32F4xxxx family */
# define STM32_NFSMC 0 /* No FSMC */
# define STM32_NATIM 0 /* No advanced timers */
# define STM32_NGTIM 3 /* 16-bit general up/down timers TIM2-4 with DMA */
@ -377,7 +377,7 @@
# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */
# undef CONFIG_STM32_STM32F33XX /* STM32F33xxx family */
# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */
# undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx families */
# undef CONFIG_STM32_STM32F4XXX /* STM32F4xxxx family */
# define STM32_NFSMC 0 /* No FSMC */
# define STM32_NATIM 0 /* No advanced timers */
# define STM32_NGTIM 3 /* 16-bit general up/down timers TIM2-4 with DMA */
@ -417,7 +417,7 @@
# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */
# undef CONFIG_STM32_STM32F33XX /* STM32F33xxx family */
# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */
# undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx families */
# undef CONFIG_STM32_STM32F4XXX /* STM32F4xxxx family */
# define STM32_NFSMC 0 /* No FSMC */
# define STM32_NATIM 0 /* No advanced timers */
# define STM32_NGTIM 3 /* 16-bit general up/down timers TIM2-4 with DMA */
@ -457,7 +457,7 @@
# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */
# undef CONFIG_STM32_STM32F33XX /* STM32F33xxx family */
# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */
# undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx families */
# undef CONFIG_STM32_STM32F4XXX /* STM32F4xxxx family */
# define STM32_NFSMC 1 /* FSMC */
# define STM32_NATIM 0 /* No advanced timers */
# define STM32_NGTIM 4 /* 16-bit general timers TIM2-4 with DMA
@ -498,7 +498,7 @@
# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */
# undef CONFIG_STM32_STM32F33XX /* STM32F33xxx family */
# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */
# undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx families */
# undef CONFIG_STM32_STM32F4XXX /* STM32F4xxxx family */
# define STM32_NFSMC 0 /* No FSMC */
# define STM32_NATIM 0 /* No advanced timers */
# define STM32_NGTIM 4 /* 16-bit general timers TIM2-4 with DMA
@ -543,7 +543,7 @@
# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */
# undef CONFIG_STM32_STM32F33XX /* STM32F33xxx family */
# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */
# undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx families */
# undef CONFIG_STM32_STM32F4XXX /* STM32F4xxxx family */
# define STM32_NFSMC 0 /* No FSMC */
# define STM32_NATIM 1 /* One advanced timer TIM1 */
# define STM32_NGTIM 3 /* 16-bit general timers TIM2-4 with DMA */
@ -582,7 +582,7 @@
# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */
# undef CONFIG_STM32_STM32F33XX /* STM32F33xxx family */
# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */
# undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx families */
# undef CONFIG_STM32_STM32F4XXX /* STM32F4xxxx family */
# define STM32_NFSMC 0 /* FSMC */
# define STM32_NATIM 1 /* One advanced timer TIM1 */
# define STM32_NGTIM 3 /* 16-bit general timers TIM2-4 with DMA */
@ -624,7 +624,7 @@
# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */
# undef CONFIG_STM32_STM32F33XX /* STM32F33xxx family */
# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */
# undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx families */
# undef CONFIG_STM32_STM32F4XXX /* STM32F4xxxx family */
# define STM32_NFSMC 0 /* FSMC */
# define STM32_NATIM 1 /* One advanced timer TIM1 */
# define STM32_NGTIM 4 /* 16-bit general timers TIM2-5 with DMA */
@ -664,7 +664,7 @@
# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */
# undef CONFIG_STM32_STM32F33XX /* STM32F33xxx family */
# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */
# undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx families */
# undef CONFIG_STM32_STM32F4XXX /* STM32F4xxxx family */
# define STM32_NFSMC 1 /* FSMC */
# define STM32_NATIM 1 /* One advanced timer TIM1 */
# define STM32_NGTIM 4 /* 16-bit general timers TIM2-5 with DMA */
@ -703,7 +703,7 @@
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */
# undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx families */
# undef CONFIG_STM32_STM32F4XXX /* STM32F4xxxx family */
# define STM32_NFSMC 1 /* FSMC */
# define STM32_NATIM 0 /* No advanced timer TIM1 */
# define STM32_NGTIM 3 /* 16-bit general timers TIM2-4 */
@ -743,7 +743,7 @@
# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */
# undef CONFIG_STM32_STM32F33XX /* STM32F33xxx family */
# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */
# undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx families */
# undef CONFIG_STM32_STM32F4XXX /* STM32F4xxxx family */
# define STM32_NFSMC 0 /* FSMC */
# define STM32_NATIM 1 /* One advanced timer TIM1 */
# define STM32_NGTIM 2 /* General timers TIM2,3 */
@ -782,7 +782,7 @@
# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */
# undef CONFIG_STM32_STM32F33XX /* STM32F33xxx family */
# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */
# undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx families */
# undef CONFIG_STM32_STM32F4XXX /* STM32F4xxxx family */
# define STM32_NFSMC 0 /* No FSMC */
# define STM32_NATIM 1 /* One advanced timer TIM1 */
# define STM32_NGTIM 3 /* General timers TIM2-4 */
@ -821,7 +821,7 @@
# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */
# undef CONFIG_STM32_STM32F33XX /* STM32F33xxx family */
# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */
# undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx families */
# undef CONFIG_STM32_STM32F4XXX /* STM32F4xxxx family */
# define STM32_NFSMC 0 /* No FSMC */
# define STM32_NATIM 1 /* One advanced timer TIM1 */
# define STM32_NGTIM 3 /* General timers TIM2-4 */
@ -860,7 +860,7 @@
# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */
# undef CONFIG_STM32_STM32F33XX /* STM32F33xxx family */
# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */
# undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx families */
# undef CONFIG_STM32_STM32F4XXX /* STM32F4xxxx family */
# define STM32_NFSMC 0 /* No FSMC */
# define STM32_NATIM 1 /* One advanced timer TIM1 */
# define STM32_NGTIM 3 /* General timers TIM2-4 */
@ -904,7 +904,7 @@
# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */
# undef CONFIG_STM32_STM32F33XX /* STM32F33xxx family */
# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */
# undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx */
# undef CONFIG_STM32_STM32F4XXX /* STM32F4xxxx family */
# define STM32_NFSMC 1 /* FSMC */
# define STM32_NATIM 2 /* Two advanced timers TIM1 and TIM8 */
# define STM32_NGTIM 4 /* 16-bit general timers TIM2-5 with DMA */
@ -946,7 +946,7 @@
# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */
# undef CONFIG_STM32_STM32F33XX /* STM32F33xxx family */
# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */
# undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx families */
# undef CONFIG_STM32_STM32F4XXX /* STM32F4xxxx family */
# define STM32_NFSMC 1 /* FSMC */
# define STM32_NATIM 2 /* Two advanced timers TIM1 and TIM8 */
# define STM32_NGTIM 4 /* General timers TIM2-5 */
@ -988,7 +988,7 @@
# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */
# undef CONFIG_STM32_STM32F33XX /* STM32F33xxx family */
# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */
# undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx families */
# undef CONFIG_STM32_STM32F4XXX /* STM32F4xxxx family */
# define STM32_NFSMC 1 /* FSMC */
# define STM32_NATIM 1 /* One advanced timer TIM1 */
# define STM32_NGTIM 4 /* 16-bit general timers TIM2-5 with DMA */
@ -1028,7 +1028,7 @@
# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */
# undef CONFIG_STM32_STM32F33XX /* STM32F33xxx family */
# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */
# undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx */
# undef CONFIG_STM32_STM32F4XXX /* STM32F4xxxx family */
# define STM32_NFSMC 1 /* FSMC */
# define STM32_NATIM 1 /* One advanced timers TIM1 */
# define STM32_NGTIM 4 /* 16-bit general timers TIM2-5 with DMA */
@ -1066,7 +1066,7 @@
# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */
# undef CONFIG_STM32_STM32F33XX /* STM32F33xxx family */
# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */
# undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx */
# undef CONFIG_STM32_STM32F4XXX /* STM32F4xxxx family */
# define STM32_NFSMC 1 /* FSMC */
# define STM32_NATIM 1 /* One advanced timers TIM1 */
# define STM32_NGTIM 4 /* 16-bit general timers TIM2-5 with DMA */
@ -1104,7 +1104,7 @@
# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */
# undef CONFIG_STM32_STM32F33XX /* STM32F33xxx family */
# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */
# undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx */
# undef CONFIG_STM32_STM32F4XXX /* STM32F4xxxx family */
# define STM32_NFSMC 1 /* FSMC */
# define STM32_NATIM 1 /* One advanced timers TIM1 */
# define STM32_NGTIM 4 /* 16-bit general timers TIM2-5 with DMA */
@ -1144,7 +1144,7 @@
# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */
# undef CONFIG_STM32_STM32F33XX /* STM32F33xxx family */
# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */
# undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx */
# undef CONFIG_STM32_STM32F4XXX /* STM32F4xxxx family */
# define STM32_NFSMC 0 /* No FSMC */
# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */
# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA
@ -1183,7 +1183,7 @@
# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */
# undef CONFIG_STM32_STM32F33XX /* STM32F33xxx family */
# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */
# undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx */
# undef CONFIG_STM32_STM32F4XXX /* STM32F4xxxx family */
# define STM32_NFSMC 1 /* FSMC */
# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */
# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA
@ -1222,7 +1222,7 @@
# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */
# undef CONFIG_STM32_STM32F33XX /* STM32F33xxx family */
# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */
# undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx */
# undef CONFIG_STM32_STM32F4XXX /* STM32F4xxxx family */
# define STM32_NFSMC 1 /* FSMC */
# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */
# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA
@ -1269,7 +1269,7 @@
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
# define CONFIG_STM32_STM32F30XX 1 /* STM32F30xxx family */
# undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx */
# undef CONFIG_STM32_STM32F4XXX /* STM32F4xxxx family */
# define STM32_NFSMC 0 /* No FSMC */
# define STM32_NATIM 1 /* (1) Advanced 16-bit timers with DMA: TIM1 (no TIM8) */
# define STM32_NGTIM 6 /* (2) 16-bit general timers with DMA: TIM3 and TIM4
@ -1310,7 +1310,7 @@
# define CONFIG_STM32_STM32F30XX 1 /* STM32F30xxx family */
# undef CONFIG_STM32_STM32F33XX /* STM32F33xxx family */
# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */
# undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx */
# undef CONFIG_STM32_STM32F4XXX /* STM32F4xxxx family */
# define STM32_NFSMC 0 /* No FSMC */
# define STM32_NATIM 1 /* (1) Advanced 16-bit timers with DMA: TIM1 (no TIM8) */
# define STM32_NGTIM 6 /* (2) 16-bit general timers with DMA: TIM3 and TIM4
@ -1351,7 +1351,7 @@
# define CONFIG_STM32_STM32F30XX 1 /* STM32F30xxx family */
# undef CONFIG_STM32_STM32F33XX /* STM32F33xxx family */
# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */
# undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx */
# undef CONFIG_STM32_STM32F4XXX /* STM32F4xxxx family */
# define STM32_NFSMC 0 /* No FSMC */
# define STM32_NATIM 1 /* (1) Advanced 16-bit timers with DMA: TIM1 (no TIM8) */
# define STM32_NGTIM 6 /* (2) 16-bit general timers with DMA: TIM3 and TIM4
@ -1392,7 +1392,7 @@
# define CONFIG_STM32_STM32F30XX 1 /* STM32F30xxx family */
# undef CONFIG_STM32_STM32F33XX /* STM32F33xxx family */
# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */
# undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx */
# undef CONFIG_STM32_STM32F4XXX /* STM32F4xxxx family */
# define STM32_NFSMC 0 /* No FSMC */
# define STM32_NATIM 1 /* (1) Advanced 16-bit timers with DMA: TIM1 (no TIM8) */
# define STM32_NGTIM 6 /* (2) 16-bit general timers with DMA: TIM3 and TIM4
@ -1433,7 +1433,7 @@
# define CONFIG_STM32_STM32F30XX 1 /* STM32F30xxx family */
# undef CONFIG_STM32_STM32F33XX /* STM32F33xxx family */
# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */
# undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx */
# undef CONFIG_STM32_STM32F4XXX /* STM32F4xxxx family */
# define STM32_NFSMC 0 /* No FSMC */
# define STM32_NATIM 1 /* (1) Advanced 16-bit timers with DMA: TIM1 */
@ -1474,7 +1474,7 @@
# define CONFIG_STM32_STM32F30XX 1 /* STM32F30xxx family */
# undef CONFIG_STM32_STM32F33XX /* STM32F33xxx family */
# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */
# undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx */
# undef CONFIG_STM32_STM32F4XXX /* STM32F4xxxx family */
# define STM32_NFSMC 0 /* No FSMC */
# define STM32_NATIM 1 /* (1) Advanced 16-bit timers with DMA: TIM1 */
@ -1515,7 +1515,7 @@
# define CONFIG_STM32_STM32F30XX 1 /* STM32F30xxx family */
# undef CONFIG_STM32_STM32F33XX /* STM32F33xxx family */
# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */
# undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx */
# undef CONFIG_STM32_STM32F4XXX /* STM32F4xxxx family */
# define STM32_NFSMC 0 /* No FSMC */
# define STM32_NATIM 2 /* (2) Advanced 16-bit timers with DMA: TIM1 and TIM8 */
@ -1556,7 +1556,7 @@
# define CONFIG_STM32_STM32F30XX 1 /* STM32F30xxx family */
# undef CONFIG_STM32_STM32F33XX /* STM32F33xxx family */
# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */
# undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx */
# undef CONFIG_STM32_STM32F4XXX /* STM32F4xxxx family */
# define STM32_NFSMC 0 /* No FSMC */
# define STM32_NATIM 2 /* (2) Advanced 16-bit timers with DMA: TIM1 and TIM8 */
@ -1597,7 +1597,7 @@
# define CONFIG_STM32_STM32F30XX 1 /* STM32F30xxx family */
# undef CONFIG_STM32_STM32F33XX /* STM32F33xxx family */
# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */
# undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx */
# undef CONFIG_STM32_STM32F4XXX /* STM32F4xxxx family */
# define STM32_NFSMC 0 /* No FSMC */
# define STM32_NATIM 2 /* (2) Advanced 16-bit timers with DMA: TIM1 and TIM8 */
@ -1638,7 +1638,7 @@
# define CONFIG_STM32_STM32F30XX 1 /* STM32F30xxx family */
# undef CONFIG_STM32_STM32F33XX /* STM32F33xxx family */
# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */
# undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx */
# undef CONFIG_STM32_STM32F4XXX /* STM32F4xxxx family */
# define STM32_NFSMC 0 /* No FSMC */
# define STM32_NATIM 2 /* (2) Advanced 16-bit timers with DMA: TIM1 and TIM8 */
@ -1679,7 +1679,7 @@
# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */
# define CONFIG_STM32_STM32F33XX 1 /* STM32F33xxx family */
# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */
# undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx */
# undef CONFIG_STM32_STM32F4XXX /* STM32F4xxxx family */
# define STM32_NFSMC 0 /* No FSMC */
# define STM32_HRTIM 1 /* (1) High-resolution timer 16-bit, 10 channels: HRTIM1 */
@ -1723,7 +1723,7 @@
# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */
# define CONFIG_STM32_STM32F33XX 1 /* STM32F33xxx family */
# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */
# undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx */
# undef CONFIG_STM32_STM32F4XXX /* STM32F4xxxx family */
# define STM32_NFSMC 0 /* No FSMC */
# define STM32_HRTIM 1 /* (1) High-resolution timer 16-bit, 10 channels: HRTIM1 */
@ -1767,7 +1767,7 @@
# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */
# define CONFIG_STM32_STM32F33XX 1 /* STM32F33xxx family */
# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */
# undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx */
# undef CONFIG_STM32_STM32F4XXX /* STM32F4xxxx family */
# define STM32_NFSMC 0 /* No FSMC */
# define STM32_HRTIM 1 /* (1) High-resolution timer 16-bit, 10 channels: HRTIM1 */
@ -1810,7 +1810,7 @@
# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */
# undef CONFIG_STM32_STM32F33XX /* STM32F33xxx family */
# define CONFIG_STM32_STM32F37XX 1 /* STM32F37xxx family */
# undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx */
# undef CONFIG_STM32_STM32F4XXX /* STM32F4xxxx family */
# define STM32_NFSMC 0 /* No FSMC */
# define STM32_NATIM 0 /* (0) Advanced 16-bit timers with DMA: */
@ -1856,7 +1856,7 @@
# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */
# undef CONFIG_STM32_STM32F33XX /* STM32F33xxx family */
# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */
# define CONFIG_STM32_STM32F40XX 1 /* STM32F405xx and STM32407xx */
# define CONFIG_STM32_STM32F4XXX 1 /* STM32F4xxxx family */
# define STM32_NFSMC 0 /* No FSMC */
# define STM32_NATIM 1 /* One advanced timers TIM1 */
# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA
@ -1894,7 +1894,7 @@
# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */
# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */
# define CONFIG_STM32_STM32F40XX 1 /* STM32F405xx and STM32407xx */
# define CONFIG_STM32_STM32F4XXX 1 /* STM32F4xxxx family */
# define STM32_NFSMC 0 /* No FSMC */
# define STM32_NATIM 1 /* One advanced timers TIM1 */
# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA
@ -1933,7 +1933,7 @@
# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */
# undef CONFIG_STM32_STM32F33XX /* STM32F33xxx family */
# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */
# define CONFIG_STM32_STM32F40XX 1 /* STM32F405xx and STM32407xx */
# define CONFIG_STM32_STM32F4XXX 1 /* STM32F4xxxx family */
# define STM32_NFSMC 0 /* No FSMC */
# define STM32_NATIM 1 /* One advanced timers TIM1 */
# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA
@ -1972,7 +1972,7 @@
# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */
# undef CONFIG_STM32_STM32F33XX /* STM32F33xxx family */
# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */
# define CONFIG_STM32_STM32F40XX 1 /* STM32F405xx and STM32407xx */
# define CONFIG_STM32_STM32F4XXX 1 /* STM32F4xxxx family */
# define STM32_NFSMC 0 /* No FSMC */
# define STM32_NATIM 1 /* One advanced timers TIM1 */
# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA
@ -2011,7 +2011,7 @@
# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */
# undef CONFIG_STM32_STM32F33XX /* STM32F33xxx family */
# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */
# define CONFIG_STM32_STM32F40XX 1 /* STM32F405xx and STM32407xx */
# define CONFIG_STM32_STM32F4XXX 1 /* STM32F4xxxx family */
# define STM32_NFSMC 0 /* No FSMC */
# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */
# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA
@ -2050,7 +2050,7 @@
# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */
# undef CONFIG_STM32_STM32F33XX /* STM32F33xxx family */
# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */
# define CONFIG_STM32_STM32F40XX 1 /* STM32F405xx and STM32407xx */
# define CONFIG_STM32_STM32F4XXX 1 /* STM32F4xxxx family */
# define STM32_NFSMC 1 /* FSMC */
# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */
# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA
@ -2089,7 +2089,7 @@
# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */
# undef CONFIG_STM32_STM32F33XX /* STM32F33xxx family */
# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */
# define CONFIG_STM32_STM32F40XX 1 /* STM32F405xx and STM32407xx */
# define CONFIG_STM32_STM32F4XXX 1 /* STM32F4xxxx family */
# define STM32_NFSMC 1 /* FSMC */
# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */
# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA
@ -2128,7 +2128,7 @@
# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */
# undef CONFIG_STM32_STM32F33XX /* STM32F33xxx family */
# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */
# define CONFIG_STM32_STM32F40XX 1 /* STM32F405xx and STM32407xx */
# define CONFIG_STM32_STM32F4XXX 1 /* STM32F4xxxx family */
# define STM32_NFSMC 1 /* FSMC */
# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */
# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA
@ -2167,7 +2167,7 @@
# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */
# undef CONFIG_STM32_STM32F33XX /* STM32F33xxx family */
# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */
# define CONFIG_STM32_STM32F40XX 1 /* STM32F405xx and STM32407xx */
# define CONFIG_STM32_STM32F4XXX 1 /* STM32F4xxxx family */
# define STM32_NFSMC 1 /* FSMC */
# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */
# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA
@ -2206,7 +2206,7 @@
# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */
# undef CONFIG_STM32_STM32F33XX /* STM32F33xxx family */
# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */
# define CONFIG_STM32_STM32F40XX 1 /* STM32F405xx and STM32407xx */
# define CONFIG_STM32_STM32F4XXX 1 /* STM32F4xxxx family */
# define STM32_NFSMC 1 /* FSMC */
# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */
# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA
@ -2245,7 +2245,7 @@
# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */
# undef CONFIG_STM32_STM32F33XX /* STM32F33xxx family */
# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */
# define CONFIG_STM32_STM32F40XX 1 /* STM32F405xx and STM32407xx */
# define CONFIG_STM32_STM32F4XXX 1 /* STM32F4xxxx family */
# define STM32_NFSMC 1 /* FSMC */
# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */
# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA
@ -2284,7 +2284,7 @@
# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */
# undef CONFIG_STM32_STM32F33XX /* STM32F33xxx family */
# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */
# define CONFIG_STM32_STM32F40XX 1 /* STM32F405xx and STM32407xx */
# define CONFIG_STM32_STM32F4XXX 1 /* STM32F4xxxx family */
# define STM32_NFSMC 1 /* FSMC */
# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */
# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA
@ -2323,7 +2323,7 @@
# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */
# undef CONFIG_STM32_STM32F33XX /* STM32F33xxx family */
# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */
# define CONFIG_STM32_STM32F40XX 1 /* STM32F405xx and STM32407xx */
# define CONFIG_STM32_STM32F4XXX 1 /* STM32F4xxxx family */
# define STM32_NFSMC 1 /* FSMC */
# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */
# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA
@ -2362,7 +2362,7 @@
# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */
# undef CONFIG_STM32_STM32F33XX /* STM32F33xxx family */
# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */
# define CONFIG_STM32_STM32F40XX 1 /* STM32F405xx, STM32407xx and STM32F427/437 */
# define CONFIG_STM32_STM32F4XXX 1 /* STM32F4xxxx family */
# define STM32_NFSMC 1 /* FSMC */
# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */
# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA
@ -2401,7 +2401,7 @@
# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */
# undef CONFIG_STM32_STM32F33XX /* STM32F33xxx family */
# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */
# define CONFIG_STM32_STM32F40XX 1 /* STM32F405xx, STM32407xx and STM32F427/437 */
# define CONFIG_STM32_STM32F4XXX 1 /* STM32F4xxxx family */
# define STM32_NFSMC 1 /* FSMC */
# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */
# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA
@ -2440,7 +2440,7 @@
# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */
# undef CONFIG_STM32_STM32F33XX /* STM32F33xxx family */
# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */
# define CONFIG_STM32_STM32F40XX 1 /* STM32F405xx, STM32407xx and STM32F427/437 */
# define CONFIG_STM32_STM32F4XXX 1 /* STM32F4xxxx family */
# define STM32_NFSMC 1 /* FSMC */
# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */
# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA
@ -2479,7 +2479,7 @@
# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */
# undef CONFIG_STM32_STM32F33XX /* STM32F33xxx family */
# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */
# define CONFIG_STM32_STM32F40XX 1 /* STM32F405xx, STM32407xx and STM32F427/437 */
# define CONFIG_STM32_STM32F4XXX 1 /* STM32F4xxxx family */
# define STM32_NFSMC 1 /* FSMC */
# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */
# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA
@ -2518,7 +2518,7 @@
# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */
# undef CONFIG_STM32_STM32F33XX /* STM32F33xxx family */
# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */
# define CONFIG_STM32_STM32F40XX 1 /* STM32F405xx, STM32407xx and STM32F427/437/429/439 */
# define CONFIG_STM32_STM32F4XXX 1 /* STM32F4xxxx family */
# define STM32_NFSMC 1 /* FSMC */
# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */
# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA
@ -2557,7 +2557,7 @@
# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */
# undef CONFIG_STM32_STM32F33XX /* STM32F33xxx family */
# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */
# define CONFIG_STM32_STM32F40XX 1 /* STM32F405xx, STM32407xx and STM32F427/437 */
# define CONFIG_STM32_STM32F4XXX 1 /* STM32F4xxxx family */
# define STM32_NFSMC 1 /* FSMC */
# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */
# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA
@ -2596,7 +2596,7 @@
# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */
# undef CONFIG_STM32_STM32F33XX /* STM32F33xxx family */
# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */
# define CONFIG_STM32_STM32F40XX 1 /* STM32F405xx, STM32407xx and STM32F427/437 STM32F466 */
# define CONFIG_STM32_STM32F4XXX 1 /* STM32F4xxxx family */
# define STM32_NFSMC 0 /* FSMC */
# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */
# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA
@ -2635,7 +2635,7 @@
# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */
# undef CONFIG_STM32_STM32F33XX /* STM32F33xxx family */
# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */
# define CONFIG_STM32_STM32F40XX 1 /* STM32F405xx, STM32407xx and STM32F427/437 STM32F466 */
# define CONFIG_STM32_STM32F4XXX 1 /* STM32F4xxxx family */
# define STM32_NFSMC 0 /* FSMC */
# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */
# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA
@ -2674,7 +2674,7 @@
# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */
# undef CONFIG_STM32_STM32F33XX /* STM32F33xxx family */
# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */
# define CONFIG_STM32_STM32F40XX 1 /* STM32F405xx, STM32407xx and STM32F427/437 STM32F466 */
# define CONFIG_STM32_STM32F4XXX 1 /* STM32F4xxxx family */
# define STM32_NFSMC 1 /* FSMC */
# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */
# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA
@ -2713,7 +2713,7 @@
# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */
# undef CONFIG_STM32_STM32F33XX /* STM32F33xxx family */
# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */
# define CONFIG_STM32_STM32F40XX 1 /* STM32F405xx, STM32407xx and STM32F427/437 STM32F466 */
# define CONFIG_STM32_STM32F4XXX 1 /* STM32F4xxxx family */
# define STM32_NFSMC 1 /* FSMC */
# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */
# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA
@ -2752,7 +2752,7 @@
# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */
# undef CONFIG_STM32_STM32F33XX /* STM32F33xxx family */
# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */
# define CONFIG_STM32_STM32F40XX 1 /* STM32F405xx, STM32407xx and STM32F427/437 */
# define CONFIG_STM32_STM32F4XXX 1 /* STM32F4xxxx family */
# define STM32_NFSMC 1 /* FSMC */
# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */
# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA
@ -2794,7 +2794,7 @@
# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */
# undef CONFIG_STM32_STM32F33XX /* STM32F33xxx family */
# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */
# define CONFIG_STM32_STM32F40XX 1 /* STM32F405xx, STM32407xx and STM32F427/437 */
# define CONFIG_STM32_STM32F4XXX 1 /* STM32F4xxxx family */
# define STM32_NFSMC 1 /* FSMC */
# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */
# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA

2
arch/arm/include/stm32/irq.h
View file

@ -89,7 +89,7 @@
# include <arch/stm32/stm32f33xxx_irq.h>
#elif defined(CONFIG_STM32_STM32F37XX)
# include <arch/stm32/stm32f37xxx_irq.h>
#elif defined(CONFIG_STM32_STM32F40XX)
#elif defined(CONFIG_STM32_STM32F4XXX)
# include <arch/stm32/stm32f40xxx_irq.h>
#else
# error "Unsupported STM32 chip"

146
arch/arm/src/stm32/Kconfig
View file

@ -968,189 +968,189 @@ config ARCH_CHIP_STM32F373VC
config ARCH_CHIP_STM32F401RE
bool "STM32F401RE"
select ARCH_CORTEXM4
select STM32_STM32F40XX
select STM32_STM32F4XXX
select STM32_STM32F401
select ARCH_HAVE_FPU
config ARCH_CHIP_STM32F410RB
bool "STM32F410RB"
select ARCH_CORTEXM4
select STM32_STM32F40XX
select STM32_STM32F4XXX
select STM32_STM32F410
select ARCH_HAVE_FPU
config ARCH_CHIP_STM32F411RE
bool "STM32F411RE"
select ARCH_CORTEXM4
select STM32_STM32F40XX
select STM32_STM32F4XXX
select STM32_STM32F411
select ARCH_HAVE_FPU
config ARCH_CHIP_STM32F411VE
bool "STM32F411VE"
select ARCH_CORTEXM4
select STM32_STM32F40XX
select STM32_STM32F4XXX
select STM32_STM32F411
select ARCH_HAVE_FPU
config ARCH_CHIP_STM32F405RG
bool "STM32F405RG"
select ARCH_CORTEXM4
select STM32_STM32F40XX
select STM32_STM32F4XXX
select STM32_STM32F405
select ARCH_HAVE_FPU
config ARCH_CHIP_STM32F405VG
bool "STM32F405VG"
select ARCH_CORTEXM4
select STM32_STM32F40XX
select STM32_STM32F4XXX
select STM32_STM32F405
select ARCH_HAVE_FPU
config ARCH_CHIP_STM32F405ZG
bool "STM32F405ZG"
select ARCH_CORTEXM4
select STM32_STM32F40XX
select STM32_STM32F4XXX
select STM32_STM32F405
select ARCH_HAVE_FPU
config ARCH_CHIP_STM32F407VE
bool "STM32F407VE"
select ARCH_CORTEXM4
select STM32_STM32F40XX
select STM32_STM32F4XXX
select STM32_STM32F407
select ARCH_HAVE_FPU
config ARCH_CHIP_STM32F407VG
bool "STM32F407VG"
select ARCH_CORTEXM4
select STM32_STM32F40XX
select STM32_STM32F4XXX
select STM32_STM32F407
select ARCH_HAVE_FPU
config ARCH_CHIP_STM32F407ZE
bool "STM32F407ZE"
select ARCH_CORTEXM4
select STM32_STM32F40XX
select STM32_STM32F4XXX
select STM32_STM32F407
select ARCH_HAVE_FPU
config ARCH_CHIP_STM32F407ZG
bool "STM32F407ZG"
select ARCH_CORTEXM4
select STM32_STM32F40XX
select STM32_STM32F4XXX
select STM32_STM32F407
select ARCH_HAVE_FPU
config ARCH_CHIP_STM32F407IE
bool "STM32F407IE"
select ARCH_CORTEXM4
select STM32_STM32F40XX
select STM32_STM32F4XXX
select STM32_STM32F407
select ARCH_HAVE_FPU
config ARCH_CHIP_STM32F407IG
bool "STM32F407IG"
select ARCH_CORTEXM4
select STM32_STM32F40XX
select STM32_STM32F4XXX
select STM32_STM32F407
select ARCH_HAVE_FPU
config ARCH_CHIP_STM32F427V
bool "STM32F427V"
select ARCH_CORTEXM4
select STM32_STM32F40XX
select STM32_STM32F4XXX
select STM32_STM32F427
select ARCH_HAVE_FPU
config ARCH_CHIP_STM32F427Z
bool "STM32F427Z"
select ARCH_CORTEXM4
select STM32_STM32F40XX
select STM32_STM32F4XXX
select STM32_STM32F427
select ARCH_HAVE_FPU
config ARCH_CHIP_STM32F427I
bool "STM32F427I"
select ARCH_CORTEXM4
select STM32_STM32F40XX
select STM32_STM32F4XXX
select STM32_STM32F427
select ARCH_HAVE_FPU
config ARCH_CHIP_STM32F429V
bool "STM32F429V"
select ARCH_CORTEXM4
select STM32_STM32F40XX
select STM32_STM32F4XXX
select STM32_STM32F429
select ARCH_HAVE_FPU
config ARCH_CHIP_STM32F429Z
bool "STM32F429Z"
select ARCH_CORTEXM4
select STM32_STM32F40XX
select STM32_STM32F4XXX
select STM32_STM32F429
select ARCH_HAVE_FPU
config ARCH_CHIP_STM32F429I
bool "STM32F429I"
select ARCH_CORTEXM4
select STM32_STM32F40XX
select STM32_STM32F4XXX
select STM32_STM32F429
select ARCH_HAVE_FPU
config ARCH_CHIP_STM32F429B
bool "STM32F429B"
select ARCH_CORTEXM4
select STM32_STM32F40XX
select STM32_STM32F4XXX
select STM32_STM32F429
select ARCH_HAVE_FPU
config ARCH_CHIP_STM32F429N
bool "STM32F429N"
select ARCH_CORTEXM4
select STM32_STM32F40XX
select STM32_STM32F4XXX
select STM32_STM32F429
select ARCH_HAVE_FPU
config ARCH_CHIP_STM32F446M
bool "STM32F446M"
select ARCH_CORTEXM4
select STM32_STM32F40XX
select STM32_STM32F4XXX
select STM32_STM32F446
select ARCH_HAVE_FPU
config ARCH_CHIP_STM32F446R
bool "STM32F446R"
select ARCH_CORTEXM4
select STM32_STM32F40XX
select STM32_STM32F4XXX
select STM32_STM32F446
select ARCH_HAVE_FPU
config ARCH_CHIP_STM32F446V
bool "STM32F446V"
select ARCH_CORTEXM4
select STM32_STM32F40XX
select STM32_STM32F4XXX
select STM32_STM32F446
select ARCH_HAVE_FPU
config ARCH_CHIP_STM32F446Z
bool "STM32F446Z"
select ARCH_CORTEXM4
select STM32_STM32F40XX
select STM32_STM32F4XXX
select STM32_STM32F446
select ARCH_HAVE_FPU
config ARCH_CHIP_STM32F469A
bool "STM32F469A"
select ARCH_CORTEXM4
select STM32_STM32F40XX
select STM32_STM32F4XXX
select STM32_STM32F469
select ARCH_HAVE_FPU
config ARCH_CHIP_STM32F469I
bool "STM32F469I"
select ARCH_CORTEXM4
select STM32_STM32F40XX
select STM32_STM32F4XXX
select STM32_STM32F469
select ARCH_HAVE_FPU
select STM32_HAVE_ETHMAC
@ -1158,7 +1158,7 @@ config ARCH_CHIP_STM32F469I
config ARCH_CHIP_STM32F469B
bool "STM32F469B"
select ARCH_CORTEXM4
select STM32_STM32F40XX
select STM32_STM32F4XXX
select STM32_STM32F469
select ARCH_HAVE_FPU
select STM32_HAVE_ETHMAC
@ -1166,7 +1166,7 @@ config ARCH_CHIP_STM32F469B
config ARCH_CHIP_STM32F469N
bool "STM32F469N"
select ARCH_CORTEXM4
select STM32_STM32F40XX
select STM32_STM32F4XXX
select STM32_STM32F469
select ARCH_HAVE_FPU
select STM32_HAVE_ETHMAC
@ -1522,23 +1522,19 @@ config STM32_STM32F37XX
select STM32_HAVE_SPI3
select STM32_HAVE_USART3
config STM32_STM32F40XX
config STM32_STM32F4XXX
bool
default n
select STM32_HAVE_OTGFS
select STM32_HAVE_TIM3
select STM32_HAVE_TIM4
select STM32_HAVE_SPI2
select STM32_HAVE_SPI3
select STM32_HAVE_I2S3
select STM32_HAVE_I2C2
select STM32_HAVE_I2C3
config STM32_STM32F401
bool
default n
select STM32_HAVE_USART6
select STM32_HAVE_TIM1
select STM32_HAVE_TIM3
select STM32_HAVE_TIM4
select STM32_HAVE_TIM5
select STM32_HAVE_TIM9
select STM32_HAVE_TIM10
@ -1546,6 +1542,8 @@ config STM32_STM32F401
select STM32_HAVE_SPI2
select STM32_HAVE_SPI3
select STM32_HAVE_I2S3
select STM32_HAVE_I2C3
select STM32_HAVE_OTGFS
config STM32_STM32F410
bool
@ -1557,21 +1555,26 @@ config STM32_STM32F410
select STM32_HAVE_TIM9
select STM32_HAVE_TIM11
select STM32_HAVE_SPI5
select STM32_HAVE_DAC1
config STM32_STM32F411
bool
default n
select STM32_HAVE_USART6
select STM32_HAVE_TIM1
select STM32_HAVE_TIM3
select STM32_HAVE_TIM4
select STM32_HAVE_TIM5
select STM32_HAVE_TIM9
select STM32_HAVE_TIM10
select STM32_HAVE_TIM11
select STM32_HAVE_SPI2
select STM32_HAVE_SPI3
select STM32_HAVE_I2S3
select STM32_HAVE_SPI4
select STM32_HAVE_SPI5
select STM32_HAVE_I2S3
select STM32_HAVE_I2C3
select STM32_HAVE_OTGFS
config STM32_STM32F405
bool
@ -1583,6 +1586,8 @@ config STM32_STM32F405
select STM32_HAVE_UART5
select STM32_HAVE_USART6
select STM32_HAVE_TIM1
select STM32_HAVE_TIM3
select STM32_HAVE_TIM4
select STM32_HAVE_TIM5
select STM32_HAVE_TIM6
select STM32_HAVE_TIM7
@ -1599,7 +1604,11 @@ config STM32_STM32F405
select STM32_HAVE_CAN2
select STM32_HAVE_DAC1
select STM32_HAVE_DAC2
select STM32_HAVE_SPI3
select STM32_HAVE_I2S3
select STM32_HAVE_I2C3
select STM32_HAVE_RNG
select STM32_HAVE_OTGFS
config STM32_STM32F407
bool
@ -1612,6 +1621,8 @@ config STM32_STM32F407
select STM32_HAVE_USART6
select STM32_HAVE_TIM1
select STM32_HAVE_TIM2
select STM32_HAVE_TIM3
select STM32_HAVE_TIM4
select STM32_HAVE_TIM5
select STM32_HAVE_TIM6
select STM32_HAVE_TIM7
@ -1628,10 +1639,15 @@ config STM32_STM32F407
select STM32_HAVE_CAN2
select STM32_HAVE_DAC1
select STM32_HAVE_DAC2
select STM32_HAVE_SPI3
select STM32_HAVE_I2S3
select STM32_HAVE_I2C3
select STM32_HAVE_RNG
select STM32_HAVE_ETHMAC
select STM32_HAVE_OTGFS
# This is really 427/437, but we treat the two the same.
config STM32_STM32F427
bool
default n
@ -1644,6 +1660,8 @@ config STM32_STM32F427
select STM32_HAVE_UART7
select STM32_HAVE_UART8
select STM32_HAVE_TIM1
select STM32_HAVE_TIM3
select STM32_HAVE_TIM4
select STM32_HAVE_TIM5
select STM32_HAVE_TIM6
select STM32_HAVE_TIM7
@ -1664,12 +1682,15 @@ config STM32_STM32F427
select STM32_HAVE_ETHMAC
select STM32_HAVE_SPI2
select STM32_HAVE_SPI3
select STM32_HAVE_I2S3
select STM32_HAVE_SPI4
select STM32_HAVE_SPI5
select STM32_HAVE_I2S3
select STM32_HAVE_I2C3
select STM32_HAVE_OTGFS
select STM32_HAVE_SPI6
# This is really 429/439, but we treat the two the same.
config STM32_STM32F429
bool
default n
@ -1683,6 +1704,8 @@ config STM32_STM32F429
select STM32_HAVE_UART7
select STM32_HAVE_UART8
select STM32_HAVE_TIM1
select STM32_HAVE_TIM3
select STM32_HAVE_TIM4
select STM32_HAVE_TIM5
select STM32_HAVE_TIM6
select STM32_HAVE_TIM7
@ -1707,6 +1730,9 @@ config STM32_STM32F429
select STM32_HAVE_SPI4
select STM32_HAVE_SPI5
select STM32_HAVE_SPI6
select STM32_HAVE_I2S3
select STM32_HAVE_I2C3
select STM32_HAVE_OTGFS
config STM32_STM32F446
bool
@ -1735,11 +1761,16 @@ config STM32_STM32F446
select STM32_HAVE_CAN2
select STM32_HAVE_DAC1
select STM32_HAVE_DAC2
select STM32_HAVE_SPI3
select STM32_HAVE_SPI4
select STM32_HAVE_I2S3
select STM32_HAVE_I2C3
select STM32_HAVE_OTGFS
select STM32_HAVE_SAIPLL
select STM32_HAVE_I2SPLL
# This is really 469/479, but we treat the two the same.
config STM32_STM32F469
bool
default n
@ -1773,12 +1804,15 @@ config STM32_STM32F469
select STM32_HAVE_DAC1
select STM32_HAVE_DAC2
select STM32_HAVE_RNG
select STM32_HAVE_SPI3
select STM32_HAVE_SPI4
select STM32_HAVE_SPI5
select STM32_HAVE_SPI6
select STM32_HAVE_OTGFS
select STM32_HAVE_SAIPLL
select STM32_HAVE_I2SPLL
select STM32_HAVE_I2S3
select STM32_HAVE_I2C3
config STM32_DFU
bool "DFU bootloader"
@ -2169,7 +2203,7 @@ config STM32_BKP
config STM32_BKPSRAM
bool "Enable BKP RAM Domain"
default n
depends on STM32_STM32F207 || STM32_STM32F40XX
depends on STM32_STM32F207 || STM32_STM32F4XXX
config STM32_CAN1
bool "CAN1"
@ -2188,7 +2222,7 @@ config STM32_CAN2
config STM32_CCMDATARAM
bool "CMD/DATA RAM"
default n
depends on STM32_STM32F40XX
depends on STM32_STM32F4XXX
config STM32_AES
bool "128-bit AES"
@ -2209,7 +2243,7 @@ config STM32_CRC
config STM32_CRYP
bool "CRYP"
default n
depends on STM32_STM32F207 || STM32_STM32F40XX
depends on STM32_STM32F207 || STM32_STM32F4XXX
config STM32_DMA1
bool "DMA1"
@ -2237,7 +2271,7 @@ config STM32_DAC2
config STM32_DCMI
bool "DCMI"
default n
depends on STM32_STM32F207 || STM32_STM32F40XX
depends on STM32_STM32F207 || STM32_STM32F4XXX
config STM32_ETHMAC
bool "Ethernet MAC"
@ -2254,7 +2288,7 @@ config STM32_FSMC
config STM32_HASH
bool "HASH"
default n
depends on STM32_STM32F207 || STM32_STM32F40XX
depends on STM32_STM32F207 || STM32_STM32F4XXX
config STM32_HRTIM1
bool "HRTIM1"
@ -2329,7 +2363,7 @@ config STM32_OTGFS
config STM32_OTGHS
bool "OTG HS"
default n
depends on STM32_STM32F205 || STM32_STM32F207 || STM32_STM32F40XX || STM32_STM32F429
depends on STM32_STM32F205 || STM32_STM32F207 || STM32_STM32F4XXX || STM32_STM32F429
select USBHOST_HAVE_ASYNCH if USBHOST
config STM32_PWR
@ -2401,7 +2435,7 @@ config STM32_SPI6
config STM32_SYSCFG
bool "SYSCFG"
default y
depends on STM32_STM32L15XX || STM32_STM32F30XX || STM32_STM32F37XX || STM32_STM32F207 || STM32_STM32F40XX || STM32_CONNECTIVITYLINE
depends on STM32_STM32L15XX || STM32_STM32F30XX || STM32_STM32F37XX || STM32_STM32F207 || STM32_STM32F4XXX || STM32_CONNECTIVITYLINE
config STM32_TIM1
bool "TIM1"
@ -2770,7 +2804,7 @@ endmenu
config STM32_FLASH_PREFETCH
bool "Enable FLASH Pre-fetch"
depends on STM32_STM32F207 || STM32_STM32F40XX
depends on STM32_STM32F207 || STM32_STM32F4XXX
default y if STM32_STM32F427 || STM32_STM32F429 || STM32_STM32F446
default n
---help---
@ -2868,8 +2902,8 @@ config STM32_CCM_PROCFS
config STM32_DMACAPABLE
bool "Workaround non-DMA capable memory"
depends on ARCH_DMA
default y if STM32_STM32F40XX && !STM32_CCMEXCLUDE
default n if !STM32_STM32F40XX || STM32_CCMEXCLUDE
default y if STM32_STM32F4XXX && !STM32_CCMEXCLUDE
default n if !STM32_STM32F4XXX || STM32_CCMEXCLUDE
---help---
This option enables the DMA interface stm32_dmacapable that can be
used to check if it is possible to do DMA from the selected address.
@ -6412,7 +6446,7 @@ config STM32_I2C_DUTY16_9
config STM32_I2C_DMA
bool "I2C DMA Support"
default n
depends on STM32_I2C && STM32_STM32F40XX && STM32_DMA1 && !I2C_POLLED
depends on STM32_I2C && STM32_STM32F4XXX && STM32_DMA1 && !I2C_POLLED
---help---
This option enables the DMA for I2C transfers.
Note: The user can define CONFIG_I2C_DMAPRIO: a custom priority value for the
@ -6551,7 +6585,7 @@ config STM32_MII
choice
prompt "MII clock configuration"
default STM32_MII_MCO if STM32_STM32F10XX
default STM32_MII_MCO1 if STM32_STM32F207 || STM32_STM32F40XX
default STM32_MII_MCO1 if STM32_STM32F207 || STM32_STM32F4XXX
depends on STM32_MII
config STM32_MII_MCO
@ -6562,13 +6596,13 @@ config STM32_MII_MCO
config STM32_MII_MCO1
bool "Use MC01 as MII clock"
depends on (STM32_STM32F207 || STM32_STM32F40XX)
depends on (STM32_STM32F207 || STM32_STM32F4XXX)
---help---
Use MCO1 to clock the MII interface. Default: Use MC01
config STM32_MII_MCO2
bool "Use MC02 as MII clock"
depends on (STM32_STM32F207 || STM32_STM32F40XX)
depends on (STM32_STM32F207 || STM32_STM32F4XXX)
---help---
Use MCO2 to clock the MII interface. Default: Use MC01
@ -6699,7 +6733,7 @@ config STM32_RMII
choice
prompt "RMII clock configuration"
default STM32_RMII_MCO if STM32_STM32F10XX
default STM32_RMII_MCO1 if STM32_STM32F207 || STM32_STM32F40XX
default STM32_RMII_MCO1 if STM32_STM32F207 || STM32_STM32F4XXX
depends on STM32_RMII
config STM32_RMII_MCO
@ -6710,13 +6744,13 @@ config STM32_RMII_MCO
config STM32_RMII_MCO1
bool "Use MC01 as RMII clock"
depends on (STM32_STM32F207 || STM32_STM32F40XX)
depends on (STM32_STM32F207 || STM32_STM32F4XXX)
---help---
Use MCO1 to clock the RMII interface. Default: Use MC01
config STM32_RMII_MCO2
bool "Use MC02 as RMII clock"
depends on (STM32_STM32F207 || STM32_STM32F40XX)
depends on (STM32_STM32F207 || STM32_STM32F4XXX)
---help---
Use MCO2 to clock the RMII interface. Default: Use MC01

2
arch/arm/src/stm32/Make.defs
View file

@ -140,7 +140,7 @@ else ifeq ($(CONFIG_STM32_STM32F30XX),y)
CHIP_CSRCS += stm32f30xxx_i2c.c
else ifeq ($(CONFIG_STM32_STM32F37XX),y)
CHIP_CSRCS += stm32f30xxx_i2c.c
else ifeq ($(CONFIG_STM32_STM32F40XX),y)
else ifeq ($(CONFIG_STM32_STM32F4XXX),y)
CHIP_CSRCS += stm32f40xxx_i2c.c
else
CHIP_CSRCS += stm32_i2c.c

4
arch/arm/src/stm32/chip.h
View file

@ -134,7 +134,7 @@
/* STM32 F4 Family ******************************************************************/
#elif defined(CONFIG_STM32_STM32F40XX)
#elif defined(CONFIG_STM32_STM32F4XXX)
# include "chip/stm32f40xxx_pinmap.h"
#else
# error "No pinmap file for this STM32 chip"
@ -157,7 +157,7 @@
# include "chip/stm32f33xxx_vectors.h"
# elif defined(CONFIG_STM32_STM32F37XX)
# include "chip/stm32f37xxx_vectors.h"
# elif defined(CONFIG_STM32_STM32F40XX)
# elif defined(CONFIG_STM32_STM32F4XXX)
# include "chip/stm32f40xxx_vectors.h"
# else
# error "No vector file for this STM32 family"

22
arch/arm/src/stm32/chip/stm32_adc.h
View file

@ -93,7 +93,7 @@
# define STM32_ADC_SMPR0_OFFSET 0X005c /* ADC sample time register 3 (32-bit) */
#endif
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX) || defined(CONFIG_STM32_STM32L15XX)
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) || defined(CONFIG_STM32_STM32L15XX)
# define STM32_ADC_CSR_OFFSET 0x0000 /* Common status register */
# define STM32_ADC_CCR_OFFSET 0x0004 /* Common control register */
# ifndef CONFIG_STM32_STM32L15XX
@ -186,7 +186,7 @@
# define STM32_ADC3_DR (STM32_ADC3_BASE+STM32_ADC_DR_OFFSET)
#endif
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX) || defined(CONFIG_STM32_STM32L15XX)
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) || defined(CONFIG_STM32_STM32L15XX)
# define STM32_ADC_CSR (STM32_ADCCMN_BASE+STM32_ADC_CSR_OFFSET)
# define STM32_ADC_CCR (STM32_ADCCMN_BASE+STM32_ADC_CCR_OFFSET)
# ifndef CONFIG_STM32_STM32L15XX
@ -203,7 +203,7 @@
#define ADC_SR_JEOC (1 << 2) /* Bit 2 : Injected channel end of conversion */
#define ADC_SR_JSTRT (1 << 3) /* Bit 3 : Injected channel Start flag */
#define ADC_SR_STRT (1 << 4) /* Bit 4 : Regular channel Start flag */
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX) || defined(CONFIG_STM32_STM32L15XX)
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) || defined(CONFIG_STM32_STM32L15XX)
# define ADC_SR_OVR (1 << 5) /* Bit 5 : Overrun */
#endif
#if defined(CONFIG_STM32_STM32L15XX)
@ -253,7 +253,7 @@
#define ADC_CR1_JAWDEN (1 << 22) /* Bit 22: Analog watchdog enable on injected channels */
#define ADC_CR1_AWDEN (1 << 23) /* Bit 23: Analog watchdog enable on regular channels */
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX) || defined(CONFIG_STM32_STM32L15XX)
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) || defined(CONFIG_STM32_STM32L15XX)
# define ADC_CR1_RES_SHIFT (24) /* Bits 24-25: Resolution */
# define ADC_CR1_RES_MASK (3 << ADC_CR1_RES_SHIFT)
# define ADC_CR1_RES_12BIT (0 << ADC_CR1_RES_SHIFT) /* 15 ADCCLK cycles. For STM32L15XX: 12 ADCCLK cycles */
@ -298,14 +298,14 @@
#define ADC_CR2_DMA (1 << 8) /* Bit 8: Direct Memory access mode */
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX) || defined(CONFIG_STM32_STM32L15XX)
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) || defined(CONFIG_STM32_STM32L15XX)
# define ADC_CR2_DDS (1 << 9) /* Bit 9: DMA disable selection (for single ADC mode) */
# define ADC_CR2_EOCS (1 << 10) /* Bit 10: End of conversion selection */
#endif
#define ADC_CR2_ALIGN (1 << 11) /* Bit 11: Data Alignment */
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX) || defined(CONFIG_STM32_STM32L15XX)
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) || defined(CONFIG_STM32_STM32L15XX)
/* Bits 12-15: Reserved */
# define ADC_CR2_JEXTSEL_SHIFT (16) /* Bits 16-19: External event select for injected group */
# define ADC_CR2_JEXTSEL_MASK (0x0F << ADC_CR2_JEXTSEL_SHIFT)
@ -425,7 +425,7 @@
/* ADC sample time register 1 */
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX)
# define ADC_SMPR_3 0 /* 000: 3 cycles */
# define ADC_SMPR_15 1 /* 001: 15 cycles */
@ -436,7 +436,7 @@
# define ADC_SMPR_144 6 /* 110: 144 cycles */
# define ADC_SMPR_480 7 /* 111: 480 cycles */
#elif !defined(CONFIG_STM32_STM32L15XX) && !defined(CONFIG_STM32_STM32F20XX) && !defined(CONFIG_STM32_STM32F40XX)
#elif !defined(CONFIG_STM32_STM32L15XX) && !defined(CONFIG_STM32_STM32F20XX) && !defined(CONFIG_STM32_STM32F4XXX)
# define ADC_SMPR_1p5 0 /* 000: 1.5 cycles */
# define ADC_SMPR_7p5 1 /* 001: 7.5 cycles */
@ -477,7 +477,7 @@
# define ADC_SMPR1_SMP16_MASK (7 << ADC_SMPR1_SMP16_SHIFT)
# define ADC_SMPR1_SMP17_SHIFT (21) /* Bits 21-23: Channel 17 Sample time selection */
# define ADC_SMPR1_SMP17_MASK (7 << ADC_SMPR1_SMP17_SHIFT)
# if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
# if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX)
# define ADC_SMPR1_SMP18_SHIFT (24) /* Bits 24-26: Channel 18 Sample time selection */
# define ADC_SMPR1_SMP18_MASK (7 << ADC_SMPR1_SMP17_SHIFT)
# endif
@ -784,7 +784,7 @@
/* Common status register */
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX) || defined(CONFIG_STM32_STM32L15XX)
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) || defined(CONFIG_STM32_STM32L15XX)
#
# define ADC_CSR_AWD1 (1 << 0) /* Bit 0: Analog watchdog flag of ADC1 (copy of AWD in ADC1_SR) */
# define ADC_CSR_EOC1 (1 << 1) /* Bit 1: End of conversion of ADC1 (copy of EOC in ADC1_SR) */
@ -818,7 +818,7 @@
/* Common control register */
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX)
# define ADC_CCR_MULTI_SHIFT (0) /* Bits 0-4: Multi ADC mode selection */
# define ADC_CCR_MULTI_MASK (31 << ADC_CCR_MULTI_SHIFT)
# define ADC_CCR_MULTI_NONE (0 << ADC_CCR_MULTI_SHIFT) /* 00000: Independent mode */

12
arch/arm/src/stm32/chip/stm32_can.h
View file

@ -62,7 +62,7 @@
/* Number of filters depends on silicon */
#if defined(CONFIG_STM32_CONNECTIVITYLINE) || defined(CONFIG_STM32_STM32F20XX) || \
defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F40XX)
defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F4XXX)
# define CAN_NFILTERS 28
#else
# define CAN_NFILTERS 14
@ -449,14 +449,14 @@
/* CAN filter master register */
#define CAN_FMR_FINIT (1 << 0) /* Bit 0: Filter Init Mode */
#if defined(CONFIG_STM32_CONNECTIVITYLINE) || defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
#if defined(CONFIG_STM32_CONNECTIVITYLINE) || defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX)
# define CAN_FMR_CAN2SB_SHIFT (8) /* Bits 13-8: CAN2 start bank */
# define CAN_FMR_CAN2SB_MASK (0x3f << CAN_FMR_CAN2SB_SHIFT)
#endif
/* CAN filter mode register */
#if defined(CONFIG_STM32_CONNECTIVITYLINE) || defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
#if defined(CONFIG_STM32_CONNECTIVITYLINE) || defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX)
# define CAN_FM1R_FBM_SHIFT (0) /* Bits 13:0: Filter Mode */
# define CAN_FM1R_FBM_MASK (0x3fff << CAN_FM1R_FBM_SHIFT)
#else
@ -466,7 +466,7 @@
/* CAN filter scale register */
#if defined(CONFIG_STM32_CONNECTIVITYLINE) || defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
#if defined(CONFIG_STM32_CONNECTIVITYLINE) || defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX)
# define CAN_FS1R_FSC_SHIFT (0) /* Bits 13:0: Filter Scale Configuration */
# define CAN_FS1R_FSC_MASK (0x3fff << CAN_FS1R_FSC_SHIFT)
#else
@ -476,7 +476,7 @@
/* CAN filter FIFO assignment register */
#if defined(CONFIG_STM32_CONNECTIVITYLINE) || defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
#if defined(CONFIG_STM32_CONNECTIVITYLINE) || defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX)
# define CAN_FFA1R_FFA_SHIFT (0) /* Bits 13:0: Filter FIFO Assignment */
# define CAN_FFA1R_FFA_MASK (0x3fff << CAN_FFA1R_FFA_SHIFT)
#else
@ -486,7 +486,7 @@
/* CAN filter activation register */
#if defined(CONFIG_STM32_CONNECTIVITYLINE) || defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
#if defined(CONFIG_STM32_CONNECTIVITYLINE) || defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX)
# define CAN_FA1R_FACT_SHIFT (0) /* Bits 13:0: Filter Active */
# define CAN_FA1R_FACT_MASK (0x3fff << CAN_FA1R_FACT_SHIFT)
#else

6
arch/arm/src/stm32/chip/stm32_dbgmcu.h
View file

@ -53,7 +53,7 @@
#define STM32_DBGMCU_IDCODE 0xe0042000 /* MCU identifier */
#define STM32_DBGMCU_CR 0xe0042004 /* MCU debug */
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F30XX) || \
defined(CONFIG_STM32_STM32F33XX) || defined(CONFIG_STM32_STM32F40XX) || \
defined(CONFIG_STM32_STM32F33XX) || defined(CONFIG_STM32_STM32F4XXX) || \
defined(CONFIG_STM32_STM32L15XX)
# define STM32_DBGMCU_APB1_FZ 0xe0042008 /* Debug MCU APB1 freeze register */
# define STM32_DBGMCU_APB2_FZ 0xe004200c /* Debug MCU APB2 freeze register */
@ -101,7 +101,7 @@
/* Debug MCU APB1 freeze register */
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX)
# define DBGMCU_APB1_TIM2STOP (1 << 0) /* Bit 0: TIM2 stopped when core is halted */
# define DBGMCU_APB1_TIM3STOP (1 << 1) /* Bit 1: TIM3 stopped when core is halted */
# define DBGMCU_APB1_TIM4STOP (1 << 2) /* Bit 2: TIM4 stopped when core is halted */
@ -138,7 +138,7 @@
/* Debug MCU APB2 freeze register */
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX)
# define DBGMCU_APB2_TIM1STOP (1 << 0) /* Bit 0: TIM1 stopped when core is halted */
# define DBGMCU_APB2_TIM8STOP (1 << 1) /* Bit 1: TIM8 stopped when core is halted */
# define DBGMCU_APB2_TIM9STOP (1 << 16) /* Bit 16: TIM9 stopped when core is halted */

16
arch/arm/src/stm32/chip/stm32_eth.h
View file

@ -62,7 +62,7 @@
#define STM32_ETH_MACVLANTR_OFFSET 0x001c /* Ethernet MAC VLAN tag register */
#define STM32_ETH_MACRWUFFR_OFFSET 0x0028 /* Ethernet MAC remote wakeup frame filter reg */
#define STM32_ETH_MACPMTCSR_OFFSET 0x002c /* Ethernet MAC PMT control and status register */
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX)
# define STM32_ETH_MACDBGR_OFFSET 0x0034 /* Ethernet MAC debug register */
#endif
#define STM32_ETH_MACSR_OFFSET 0x0038 /* Ethernet MAC interrupt status register */
@ -134,7 +134,7 @@
#define STM32_ETH_MACVLANTR (STM32_ETHERNET_BASE+STM32_ETH_MACVLANTR_OFFSET)
#define STM32_ETH_MACRWUFFR (STM32_ETHERNET_BASE+STM32_ETH_MACRWUFFR_OFFSET)
#define STM32_ETH_MACPMTCSR (STM32_ETHERNET_BASE+STM32_ETH_MACPMTCSR_OFFSET)
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX)
# define STM32_ETH_MACDBGR (STM32_ETHERNET_BASE+STM32_ETH_MACDBGR_OFFSET)
#endif
#define STM32_ETH_MACSR (STM32_ETHERNET_BASE+STM32_ETH_MACSR_OFFSET)
@ -220,7 +220,7 @@
# define ETH_MACCR_IFG(n) ((12-((n) >> 3)) << ETH_MACCR_IFG_SHIFT) /* n bit times, n=40,48,..96 */
#define ETH_MACCR_JD (1 << 22) /* Bit 22: Jabber disable */
#define ETH_MACCR_WD (1 << 23) /* Bit 23: Watchdog disable */
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX)
# define ETH_MACCR_CSTF (1 << 25) /* Bits 25: CRC stripping for Type frames */
#endif
@ -309,7 +309,7 @@
/* Ethernet MAC debug register */
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX)
#define ETH_MACDBGR_MMRPEA (1 << 0) /* Bit 0: MAC MII receive protocol engine active */
#define ETH_MACDBGR_MSFRWCS_SHIFT (1) /* Bits 1-2: MAC small FIFO read / write controllers status */
@ -429,7 +429,7 @@
#define ETH_MMCCR_ROR (1 << 2) /* Bit 2: Reset on read */
#define ETH_MMCCR_MCF (1 << 3) /* Bit 3: MMC counter freeze */
#define ETH_MMCCR_MCP (1 << 4) /* Bit 4: MMC counter preset */
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX)
# define ETH_MMCCR_MCFHP (1 << 5) /* Bit 5: MMC counter Full-Half preset */
#endif
@ -466,7 +466,7 @@
#define ETH_PTPTSCR_TSITE (1 << 4) /* Bit 4: Time stamp interrupt trigger enable */
#define ETH_PTPTSCR_TSARU (1 << 5) /* Bit 5: Time stamp addend register update */
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX)
#define ETH_PTPTSCR_TSSARFE (1 << 8) /* Bit 8: Time stamp snapshot for all received frames enable */
#define ETH_PTPTSCR_TSSSR (1 << 9) /* Bit 9: Time stamp subsecond rollover: digital or binary rollover control */
#define ETH_PTPTSCR_TSPTPPSV2E (1 << 10) /* Bit 10: Time stamp PTP packet snooping for version2 format enable */
@ -558,7 +558,7 @@
#define ETH_DMABMR_USP (1 << 23) /* Bit 23: Use separate PBL */
#define ETH_DMABMR_FPM (1 << 24) /* Bit 24: 4xPBL mode */
#define ETH_DMABMR_AAB (1 << 25) /* Bit 25: Address-aligned beats */
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX)
# define ETH_DMABMR_MB (1 << 26) /* Bit 26: Mixed burst */
#endif
@ -711,7 +711,7 @@
/* RDES0: Receive descriptor Word0 */
#define ETH_RDES0_PCE (1 << 0) /* Bit 0: Payload checksum error */
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX)
# define ETH_RDES0_ESA (1 << 0) /* Bit 0: Extended status available */
#endif
#define ETH_RDES0_CE (1 << 1) /* Bit 1: CRC error */

4
arch/arm/src/stm32/chip/stm32_exti.h
View file

@ -60,7 +60,7 @@
# define STM32_EXTI1_MASK 0xffffffff
# define STM32_NEXTI2 4
# define STM32_EXTI2_MASK 0x0000000f
#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX)
# define STM32_NEXTI 23
# define STM32_EXTI_MASK 0x007fffff
#endif
@ -137,7 +137,7 @@
# define EXTI_RTC_CMP1 (1 << 21) /* EXTI line 21 is connected to the Comparator 1 wakeup event */
# define EXTI_RTC_CMP2 (1 << 22) /* EXTI line 22 is connected to the Comparator 2 wakeup event */
# define EXTI_RTC_ACQUIRE (1 << 23) /* EXTI line 23 is connected to the channel acquisition interrupt */
#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX)
# define EXTI_PVD_LINE (1 << 16) /* EXTI line 16 is connected to the PVD output */
# define EXTI_RTC_ALARM (1 << 17) /* EXTI line 17 is connected to the RTC Alarm event */
# define EXTI_OTGFS_WAKEUP (1 << 18) /* EXTI line 18 is connected to the USB OTG FS Wakeup event */

22
arch/arm/src/stm32/chip/stm32_flash.h
View file

@ -115,7 +115,7 @@
# define STM32_FLASH_NPAGES 128
# define STM32_FLASH_PAGESIZE 2048
# elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
# elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX)
# define STM32_FLASH_NPAGES 8
# define STM32_FLASH_SIZE _K((4 * 16) + (1 * 64) + (3 * 128))
# define STM32_FLASH_SIZES {_K(16), _K(16), _K(16), _K(16), \
@ -133,7 +133,7 @@
/* Define the Valid Configuration the F2 and F4 */
# if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
# if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX)
# if defined(CONFIG_STM32_FLASH_CONFIG_B)
# define STM32_FLASH_NPAGES 5
@ -147,7 +147,7 @@
# define STM32_FLASH_SIZES {_K(16), _K(16), _K(16), _K(16), \
_K(64), _K(128)}
# elif defined(CONFIG_STM32_FLASH_CONFIG_D) && defined(CONFIG_STM32_STM32F40XX)
# elif defined(CONFIG_STM32_FLASH_CONFIG_D) && defined(CONFIG_STM32_STM32F4XXX)
# define STM32_FLASH_NPAGES 7
# define STM32_FLASH_SIZE _K((4 * 16) + (1 * 64) + (2 * 128))
# define STM32_FLASH_SIZES {_K(16), _K(16), _K(16), _K(16), \
@ -173,7 +173,7 @@
_K(64), _K(128), _K(128), _K(128), \
_K(128), _K(128), _K(128), _K(128)}
# elif defined(CONFIG_STM32_FLASH_CONFIG_I) && defined(CONFIG_STM32_STM32F40XX)
# elif defined(CONFIG_STM32_FLASH_CONFIG_I) && defined(CONFIG_STM32_STM32F4XXX)
# define STM32_FLASH_NPAGES 24
# define STM32_FLASH_SIZE _K((4 * 16) + (1 * 64) + (7 * 128)) + \
_K((4 * 16) + (1 * 64) + (7 * 128))
@ -249,7 +249,7 @@
# define STM32_FLASH_AR_OFFSET 0x0014
# define STM32_FLASH_OBR_OFFSET 0x001c
# define STM32_FLASH_WRPR_OFFSET 0x0020
# elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
# elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX)
# define STM32_FLASH_OPTCR_OFFSET 0x0014
# endif
#endif
@ -285,7 +285,7 @@
# define STM32_FLASH_AR (STM32_FLASHIF_BASE+STM32_FLASH_AR_OFFSET)
# define STM32_FLASH_OBR (STM32_FLASHIF_BASE+STM32_FLASH_OBR_OFFSET)
# define STM32_FLASH_WRPR (STM32_FLASHIF_BASE+STM32_FLASH_WRPR_OFFSET)
# elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
# elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX)
# define STM32_FLASH_OPTCR (STM32_FLASHIF_BASE+STM32_FLASH_OPTCR_OFFSET)
# endif
# if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429) || \
@ -324,7 +324,7 @@
defined(CONFIG_STM32_STM32F37XX)
# define FLASH_ACR_PRFTBS (1 << 5) /* Bit 5: FLASH prefetch buffer status */
# endif
# elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
# elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX)
# define FLASH_ACR_PRFTEN (1 << 8) /* FLASH prefetch enable */
# define FLASH_ACR_ICEN (1 << 9) /* Bit 9: Instruction cache enable */
# define FLASH_ACR_DCEN (1 << 10) /* Bit 10: Data cache enable */
@ -341,7 +341,7 @@
# define FLASH_SR_PGERR (1 << 2) /* Programming Error */
# define FLASH_SR_WRPRT_ERR (1 << 4) /* Write Protection Error */
# define FLASH_SR_EOP (1 << 5) /* End of Operation */
#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX)
# define FLASH_SR_EOP (1 << 0) /* Bit 0: End of operation */
# define FLASH_SR_OPERR (1 << 1) /* Bit 1: Operation error */
# define FLASH_SR_WRPERR (1 << 4) /* Bit 4: Write protection error */
@ -397,7 +397,7 @@
defined(CONFIG_STM32_STM32F37XX)
# define FLASH_CR_OBL_LAUNCH (1 << 13) /* Bit 13: Force option byte loading */
# endif
#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX)
# define FLASH_CR_PG (1 << 0) /* Bit 0: Programming */
# define FLASH_CR_SER (1 << 1) /* Bit 1: Sector Erase */
# define FLASH_CR_MER (1 << 2) /* Bit 2: Mass Erase sectors 0..11 */
@ -426,7 +426,7 @@
/* Flash Option Control Register (OPTCR) */
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX)
# define FLASH_OPTCR_OPTLOCK (1 << 0) /* Bit 0: Option lock */
# define FLASH_OPTCR_OPTSTRT (1 << 1) /* Bit 1: Option start */
# define FLASH_OPTCR_BORLEV_SHIFT (2) /* Bits 2-3: BOR reset Level */
@ -468,7 +468,7 @@
void stm32_flash_lock(void);
void stm32_flash_unlock(void);
#ifdef CONFIG_STM32_STM32F40XX
#ifdef CONFIG_STM32_STM32F4XXX
int stm32_flash_writeprotect(size_t page, bool enabled);
#endif

2
arch/arm/src/stm32/chip/stm32_memorymap.h
View file

@ -55,7 +55,7 @@
# include "chip/stm32f33xxx_memorymap.h"
#elif defined(CONFIG_STM32_STM32F37XX)
# include "chip/stm32f37xxx_memorymap.h"
#elif defined(CONFIG_STM32_STM32F40XX)
#elif defined(CONFIG_STM32_STM32F4XXX)
# include "chip/stm32f40xxx_memorymap.h"
#else
# error "Unsupported STM32 memory map"

6
arch/arm/src/stm32/chip/stm32_pwr.h
View file

@ -90,7 +90,7 @@
# endif
#define PWR_CR_DBP (1 << 8) /* Bit 8: Disable Backup Domain write protection */
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX)
# define PWR_CR_FPDS (1 << 9) /* Bit 9: Flash power down in Stop mode */
# if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429) || \
defined(CONFIG_STM32_STM32F446) || defined(CONFIG_STM32_STM32F469)
@ -139,7 +139,7 @@
#define PWR_CSR_PVDO (1 << 2) /* Bit 2: PVD Output */
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F37XX) || \
defined(CONFIG_STM32_STM32F40XX)
defined(CONFIG_STM32_STM32F4XXX)
# define PWR_CSR_BRR (1 << 3) /* Bit 3: Backup regulator ready */
#elif defined(CONFIG_STM32_STM32L15XX)
# define PWR_CSR_VREFINTRDYF (1 << 3) /* Bit 3: Internal voltage reference (VREFINT) ready flag */
@ -159,7 +159,7 @@
# define PWR_CSR_EWUP (1 << 8) /* Bit 8: Enable WKUP pin */
#endif
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX)
# define PWR_CSR_BRE (1 << 9) /* Bit 9: Backup regulator enable */
# define PWR_CSR_VOSRDY (1 << 14) /* Bit 14: Regulator voltage scaling output selection ready bite */
#endif

18
arch/arm/src/stm32/chip/stm32_spi.h
View file

@ -49,7 +49,7 @@
/* Maximum allowed speed as per specifications for all SPIs */
#if defined(CONFIG_STM32_STM32F40XX)
#if defined(CONFIG_STM32_STM32F4XXX)
# define STM32_SPI_CLK_MAX 37500000UL
#else
# define STM32_SPI_CLK_MAX 18000000UL
@ -66,7 +66,7 @@
#define STM32_SPI_TXCRCR_OFFSET 0x0018 /* SPI Tx CRC register (16-bit) */
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F30XX) || \
defined(CONFIG_STM32_STM32F37XX) || defined(CONFIG_STM32_STM32F40XX)
defined(CONFIG_STM32_STM32F37XX) || defined(CONFIG_STM32_STM32F4XXX)
# define STM32_SPI_I2SCFGR_OFFSET 0x001c /* I2S configuration register */
# define STM32_SPI_I2SPR_OFFSET 0x0020 /* I2S prescaler register */
#endif
@ -92,7 +92,7 @@
# define STM32_SPI2_RXCRCR (STM32_SPI2_BASE+STM32_SPI_RXCRCR_OFFSET)
# define STM32_SPI2_TXCRCR (STM32_SPI2_BASE+STM32_SPI_TXCRCR_OFFSET)
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F30XX) || \
defined(CONFIG_STM32_STM32F37XX) || defined(CONFIG_STM32_STM32F40XX)
defined(CONFIG_STM32_STM32F37XX) || defined(CONFIG_STM32_STM32F4XXX)
# define STM32_SPI2_I2SCFGR (STM32_SPI2_BASE+STM32_SPI_I2SCFGR_OFFSET)
# define STM32_SPI2_I2SPR (STM32_SPI2_BASE+STM32_SPI_I2SPR_OFFSET)
# endif
@ -107,7 +107,7 @@
# define STM32_SPI3_RXCRCR (STM32_SPI3_BASE+STM32_SPI_RXCRCR_OFFSET)
# define STM32_SPI3_TXCRCR (STM32_SPI3_BASE+STM32_SPI_TXCRCR_OFFSET)
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F30XX) || \
defined(CONFIG_STM32_STM32F37XX) || defined(CONFIG_STM32_STM32F40XX)
defined(CONFIG_STM32_STM32F37XX) || defined(CONFIG_STM32_STM32F4XXX)
# define STM32_SPI3_I2SCFGR (STM32_SPI3_BASE+STM32_SPI_I2SCFGR_OFFSET)
# define STM32_SPI3_I2SPR (STM32_SPI3_BASE+STM32_SPI_I2SPR_OFFSET)
# endif
@ -152,7 +152,7 @@
#define SPI_CR2_SSOE (1 << 2) /* Bit 2: SS Output Enable */
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F30XX) || \
defined(CONFIG_STM32_STM32F37XX) || defined(CONFIG_STM32_STM32F40XX)
defined(CONFIG_STM32_STM32F37XX) || defined(CONFIG_STM32_STM32F4XXX)
# define SPI_CR2_FRF (1 << 4) /* Bit 4: Frame format */
#endif
@ -188,7 +188,7 @@
#define SPI_SR_TXE (1 << 1) /* Bit 1: Transmit buffer empty */
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F30XX) || \
defined(CONFIG_STM32_STM32F37XX) || defined(CONFIG_STM32_STM32F40XX)
defined(CONFIG_STM32_STM32F37XX) || defined(CONFIG_STM32_STM32F4XXX)
# define SPI_SR_CHSIDE (1 << 2) /* Bit 2: Channel side */
# define SPI_SR_UDR (1 << 3) /* Bit 3: Underrun flag */
#endif
@ -199,7 +199,7 @@
#define SPI_SR_BSY (1 << 7) /* Bit 7: Busy flag */
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F30XX) || \
defined(CONFIG_STM32_STM32F37XX) || defined(CONFIG_STM32_STM32F40XX)
defined(CONFIG_STM32_STM32F37XX) || defined(CONFIG_STM32_STM32F4XXX)
# define SPI_SR_FRE (1 << 8) /* Bit 8: TI frame format error */
#endif
@ -221,7 +221,7 @@
/* I2S configuration register */
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F30XX) || \
defined(CONFIG_STM32_STM32F37XX) || defined(CONFIG_STM32_STM32F40XX)
defined(CONFIG_STM32_STM32F37XX) || defined(CONFIG_STM32_STM32F4XXX)
# define SPI_I2SCFGR_CHLEN (1 << 0) /* Bit 0: Channel length (number of bits per audio channel) */
# define SPI_I2SCFGR_DATLEN_SHIFT (1) /* Bit 1-2: Data length to be transferred */
# define SPI_I2SCFGR_DATLEN_MASK (3 << SPI_I2SCFGR_DATLEN_SHIFT)
@ -249,7 +249,7 @@
/* I2S prescaler register */
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F30XX) || \
defined(CONFIG_STM32_STM32F37XX) || defined(CONFIG_STM32_STM32F40XX)
defined(CONFIG_STM32_STM32F37XX) || defined(CONFIG_STM32_STM32F4XXX)
# define SPI_I2SPR_I2SDIV_SHIFT (0) /* Bit 0-7: I2S Linear prescaler */
# define SPI_I2SPR_I2SDIV_MASK (0xff << SPI_I2SPR_I2SDIV_SHIFT)
# define SPI_I2SPR_ODD (1 << 8) /* Bit 8: Odd factor for the prescaler */

8
arch/arm/src/stm32/chip/stm32_tim.h
View file

@ -214,7 +214,7 @@
# define STM32_TIM2_CCR4 (STM32_TIM2_BASE+STM32_GTIM_CCR4_OFFSET)
# define STM32_TIM2_DCR (STM32_TIM2_BASE+STM32_GTIM_DCR_OFFSET)
# define STM32_TIM2_DMAR (STM32_TIM2_BASE+STM32_GTIM_DMAR_OFFSET)
# if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
# if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX)
# define STM32_TIM2_OR (STM32_TIM2_BASE+STM32_GTIM_OR_OFFSET)
# endif
#endif
@ -280,7 +280,7 @@
# define STM32_TIM5_CCR4 (STM32_TIM5_BASE+STM32_GTIM_CCR4_OFFSET)
# define STM32_TIM5_DCR (STM32_TIM5_BASE+STM32_GTIM_DCR_OFFSET)
# define STM32_TIM5_DMAR (STM32_TIM5_BASE+STM32_GTIM_DMAR_OFFSET)
# if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
# if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX)
# define STM32_TIM5_OR (STM32_TIM5_BASE+STM32_GTIM_OR_OFFSET)
# endif
#endif
@ -829,7 +829,7 @@
#define ATIM_CCER_CC4P (1 << 13) /* Bit 13: Capture/Compare 4 output Polarity */
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F30XX) || \
defined(CONFIG_STM32_STM32F37XX) || defined(CONFIG_STM32_STM32F40XX) || \
defined(CONFIG_STM32_STM32F37XX) || defined(CONFIG_STM32_STM32F4XXX) || \
defined(CONFIG_STM32_STM32L15XX)
# define ATIM_CCER_CC4NP (1 << 15) /* Bit 15: Capture/Compare 4 Complementary output polarity */
#elif defined(CONFIG_STM32_STM32F30XX)
@ -1283,7 +1283,7 @@
/* Timer 2/5 option register */
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX)
# define TIM2_OR_ITR1_RMP_SHIFT (10) /* Bits 10-11: Internal trigger 1 remap */
# define TIM2_OR_ITR1_RMP_MASK (3 << TIM2_OR_ITR1_RMP_SHIFT)
# define TIM2_OR_ITR1_TIM8_TRGOUT (0 << TIM2_OR_ITR1_RMP_SHIFT) /* 00: TIM2_ITR1 input connected to TIM8_TRGOUT */

4
arch/arm/src/stm32/chip/stm32f40xxx_syscfg.h
View file

@ -46,7 +46,7 @@
#include <nuttx/config.h>
#include "chip.h"
#ifdef CONFIG_STM32_STM32F40XX
#ifdef CONFIG_STM32_STM32F4XXX
/****************************************************************************************************
* Pre-processor Definitions
@ -198,5 +198,5 @@
# define SYSCFG_CFGR_FMPI2C1_SDA (1 << 1) /* Bit 8: Forces FM+ drive capability on SDA */
#endif
#endif /* CONFIG_STM32_STM32F40XX */
#endif /* CONFIG_STM32_STM32F4XXX */
#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32F40XXX_SYSCFG_H */

4
arch/arm/src/stm32/gnu/stm32_vectors.S
View file

@ -181,7 +181,7 @@ _vectors:
# include "chip/stm32f33xxx_vectors.h"
#elif defined(CONFIG_STM32_STM32F37XX)
# include "chip/stm32f37xxx_vectors.h"
#elif defined(CONFIG_STM32_STM32F40XX)
#elif defined(CONFIG_STM32_STM32F4XXX)
# include "chip/stm32f40xxx_vectors.h"
#else
# error "No vectors for STM32 chip"
@ -228,7 +228,7 @@ handlers:
# include "chip/stm32f33xxx_vectors.h"
#elif defined(CONFIG_STM32_STM32F37XX)
# include "chip/stm32f37xxx_vectors.h"
#elif defined(CONFIG_STM32_STM32F40XX)
#elif defined(CONFIG_STM32_STM32F4XXX)
# include "chip/stm32f40xxx_vectors.h"
#else
# error "No handlers for STM32 chip"

4
arch/arm/src/stm32/iar/stm32_vectors.S
View file

@ -469,7 +469,7 @@ __vector_table:
# include "chip/stm32f42xxx_vectors.h"
#elif defined(CONFIG_STM32_STM32F446)
# include "chip/stm32f44xxx_vectors.h"
#elif defined(CONFIG_STM32_STM32F40XX)
#elif defined(CONFIG_STM32_STM32F4XXX)
# include "chip/stm32f40xxx_vectors.h"
#else
# error "No vectors for STM32 chip"
@ -788,7 +788,7 @@ handlers:
# include "chip/stm32f42xxx_vectors.h"
#elif defined(CONFIG_STM32_STM32F446)
# include "chip/stm32f44xxx_vectors.h"
#elif defined(CONFIG_STM32_STM32F40XX)
#elif defined(CONFIG_STM32_STM32F4XXX)
# include "chip/stm32f40xxx_vectors.h"
#else
# error "No handlers for STM32 chip"

24
arch/arm/src/stm32/stm32_adc.c
View file

@ -82,7 +82,7 @@
#if defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32F20XX) || \
defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) || \
defined(CONFIG_STM32_STM32F37XX) || defined(CONFIG_STM32_STM32F40XX) || \
defined(CONFIG_STM32_STM32F37XX) || defined(CONFIG_STM32_STM32F4XXX) || \
defined(CONFIG_STM32_STM32L15XX)
/* At the moment there is no proper implementation for timers external
@ -125,7 +125,7 @@
#elif defined(CONFIG_STM32_STM32F37XX)
# define STM32_RCC_RSTR STM32_RCC_APB2RSTR
# define RCC_RSTR_ADC1RST RCC_APB2RSTR_ADCRST
#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX)
# define STM32_RCC_RSTR STM32_RCC_APB2RSTR
# define RCC_RSTR_ADC1RST RCC_APB2RSTR_ADCRST
# define RCC_RSTR_ADC2RST RCC_APB2RSTR_ADCRST
@ -205,7 +205,7 @@
# endif
#endif
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX)
# define ADC_DMA_CONTROL_WORD (DMA_SCR_MSIZE_16BITS | \
DMA_SCR_PSIZE_16BITS | \
DMA_SCR_MINC | \
@ -266,7 +266,7 @@
(ADC_SMPR_DEFAULT << ADC_SMPR2_SMP17_SHIFT) | \
(ADC_SMPR_DEFAULT << ADC_SMPR2_SMP18_SHIFT))
#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F37XX) || \
defined(CONFIG_STM32_STM32F40XX)
defined(CONFIG_STM32_STM32F4XXX)
# if defined(CONFIG_STM32_STM32F37XX)
# define ADC_SMPR_DEFAULT ADC_SMPR_239p5 /* TODO choose 1p5? */
# else
@ -353,7 +353,7 @@ struct stm32_dev_s
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F30XX) || \
defined(CONFIG_STM32_STM32F33XX) || defined(CONFIG_STM32_STM32F37XX) || \
defined(CONFIG_STM32_STM32F40XX) || defined(CONFIG_STM32_STM32L15XX)
defined(CONFIG_STM32_STM32F4XXX) || defined(CONFIG_STM32_STM32L15XX)
static void stm32_modifyreg32(unsigned int addr, uint32_t clrbits,
uint32_t setbits);
#endif
@ -621,7 +621,7 @@ static struct adc_dev_s g_adcdev4 =
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F30XX) || \
defined(CONFIG_STM32_STM32F33XX) || defined(CONFIG_STM32_STM32F37XX) || \
defined(CONFIG_STM32_STM32F40XX) || defined(CONFIG_STM32_STM32L15XX)
defined(CONFIG_STM32_STM32F4XXX) || defined(CONFIG_STM32_STM32L15XX)
static void stm32_modifyreg32(unsigned int addr, uint32_t clrbits,
uint32_t setbits)
{
@ -1154,7 +1154,7 @@ static int adc_timinit(FAR struct stm32_dev_s *priv)
# if defined(CONFIG_STM32_STM32F20XX) || \
defined(CONFIG_STM32_STM32F30XX) || \
defined(CONFIG_STM32_STM32F40XX)
defined(CONFIG_STM32_STM32F4XXX)
ccer &= ~(ATIM_CCER_CC1NE | ATIM_CCER_CC1NP |
ATIM_CCER_CC2NE | ATIM_CCER_CC2NP |
ATIM_CCER_CC3NE | ATIM_CCER_CC3NP |
@ -1174,7 +1174,7 @@ static int adc_timinit(FAR struct stm32_dev_s *priv)
}
# if defined(CONFIG_STM32_STM32F20XX) || \
defined(CONFIG_STM32_STM32F30XX) || \
defined(CONFIG_STM32_STM32F40XX)
defined(CONFIG_STM32_STM32F4XXX)
else
{
ccer &= ~(GTIM_CCER_CC1NP | GTIM_CCER_CC2NP | GTIM_CCER_CC3NP);
@ -2000,12 +2000,12 @@ static void adc_reset(FAR struct adc_dev_s *dev)
}
#endif
#elif defined(CONFIG_STM32_STM32F20XX) || \
defined(CONFIG_STM32_STM32F40XX) || \
defined(CONFIG_STM32_STM32F4XXX) || \
defined(CONFIG_STM32_STM32L15XX)
clrbits = ADC_CCR_ADCPRE_MASK | ADC_CCR_TSVREFE;
setbits = ADC_CCR_ADCPRE_DIV2;
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX)
clrbits |= ADC_CCR_MULTI_MASK | ADC_CCR_DELAY_MASK | ADC_CCR_DDS |
ADC_CCR_DMA_MASK | ADC_CCR_VBATE;
setbits |= ADC_CCR_MULTI_NONE | ADC_CCR_DMA_DISABLED;
@ -2103,7 +2103,7 @@ static void adc_reset(FAR struct adc_dev_s *dev)
}
#endif
#elif defined(CONFIG_STM32_STM32F20XX) || \
defined(CONFIG_STM32_STM32F40XX) || \
defined(CONFIG_STM32_STM32F4XXX) || \
defined(CONFIG_STM32_STM32L15XX)
ainfo("CCR: 0x%08x\n", getreg32(STM32_ADC_CCR));
#endif
@ -3104,7 +3104,7 @@ struct adc_dev_s *stm32_adcinitialize(int intf, FAR const uint8_t *chanlist,
#endif /* CONFIG_STM32_STM32F10XX || CONFIG_STM32_STM32F20XX ||
* CONFIG_STM32_STM32F30XX || CONFIG_STM32_STM32F33XX ||
* CONFIG_STM32_STM32F47XX || CONFIG_STM32_STM32F40XX ||
* CONFIG_STM32_STM32F47XX || CONFIG_STM32_STM32F4XXX ||
* CONFIG_STM32_STM32L15XX
*/
#endif /* CONFIG_STM32_ADC1 || CONFIG_STM32_ADC2 ||

4
arch/arm/src/stm32/stm32_adc.h
View file

@ -112,7 +112,7 @@
# undef CONFIG_STM32_TIM4_ADC4
#endif
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX)
# ifndef CONFIG_STM32_TIM5
# undef CONFIG_STM32_TIM5_ADC
# undef CONFIG_STM32_TIM5_ADC1
@ -129,7 +129,7 @@
#endif
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F30XX) || \
defined(CONFIG_STM32_STM32F40XX)
defined(CONFIG_STM32_STM32F4XXX)
# ifndef CONFIG_STM32_TIM8
# undef CONFIG_STM32_TIM8_ADC
# undef CONFIG_STM32_TIM8_ADC1

2
arch/arm/src/stm32/stm32_allocateheap.c
View file

@ -348,7 +348,7 @@
* In addition, external FSMC SRAM may be available.
*/
#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX)
/* The STM32 F2 and the STM32 F401/F411 have no CCM SRAM */

2
arch/arm/src/stm32/stm32_bbsram.h
View file

@ -59,7 +59,7 @@
* Pre-processor Definitions
****************************************************************************/
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX)
# define STM32_BBSRAM_SIZE 4096
#else
# error No backup SRAM on this STM32

2
arch/arm/src/stm32/stm32_can.c
View file

@ -1952,7 +1952,7 @@ static int stm32can_filterinit(FAR struct stm32_can_s *priv)
#if defined(CONFIG_STM32_CONNECTIVITYLINE) || \
defined(CONFIG_STM32_STM32F20XX) || \
defined(CONFIG_STM32_STM32F40XX)
defined(CONFIG_STM32_STM32F4XXX)
regval = stm32can_getfreg(priv, STM32_CAN_FMR_OFFSET);
regval &= CAN_FMR_CAN2SB_MASK;
regval |= (CAN_NFILTERS / 2) << CAN_FMR_CAN2SB_SHIFT;

2
arch/arm/src/stm32/stm32_ccm.h
View file

@ -58,7 +58,7 @@
#if defined(CONFIG_STM32_STM32F30XX)
# define CCM_START 0x10000000
# define CCM_END 0x10002000
#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX) || \
#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) || \
defined(CONFIG_STM32_STM32F33XX)
# define CCM_START 0x10000000
# define CCM_END 0x10010000

10
arch/arm/src/stm32/stm32_dac.c
View file

@ -100,7 +100,7 @@
# undef CONFIG_STM32_DAC1_DMA
# undef CONFIG_STM32_DAC2_DMA
# endif
# elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
# elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX)
# ifndef CONFIG_STM32_DMA1
# warning "STM32 F4 DAC DMA support requires CONFIG_STM32_DMA1"
# undef CONFIG_STM32_DAC1_DMA
@ -153,7 +153,7 @@
# define DAC_DMA 2
# define DAC1_DMA_CHAN DMACHAN_DAC_CHAN1
# define DAC2_DMA_CHAN DMACHAN_DAC_CHAN2
# elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX) || \
# elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) || \
defined(CONFIG_STM32_STM32F33XX)
# define HAVE_DMA 1
# define DAC_DMA 1
@ -320,7 +320,7 @@
/* DMA stream/channel configuration */
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX)
# define DAC_DMA_CONTROL_WORD (DMA_SCR_MSIZE_16BITS | \
DMA_SCR_PSIZE_16BITS | \
DMA_SCR_MINC | \
@ -381,7 +381,7 @@ static void tim_putreg(FAR struct stm32_chan_s *chan, int offset,
/* Interrupt handler */
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX)
static int dac_interrupt(int irq, FAR void *context, FAR void *arg);
#endif
@ -620,7 +620,7 @@ static void tim_modifyreg(FAR struct stm32_chan_s *chan, int offset,
*
****************************************************************************/
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX)
static int dac_interrupt(int irq, FAR void *context, FAR void *arg)
{
#warning "Missing logic"

2
arch/arm/src/stm32/stm32_dma.c
View file

@ -62,6 +62,6 @@
# include "stm32f33xxx_dma.c"
#elif defined(CONFIG_STM32_STM32F20XX)
# include "stm32f20xxx_dma.c"
#elif defined(CONFIG_STM32_STM32F40XX)
#elif defined(CONFIG_STM32_STM32F4XXX)
# include "stm32f40xxx_dma.c"
#endif

6
arch/arm/src/stm32/stm32_dma.h
View file

@ -54,7 +54,7 @@
# include "chip/stm32f33xxx_dma.h"
#elif defined(CONFIG_STM32_STM32F20XX)
# include "chip/stm32f20xxx_dma.h"
#elif defined(CONFIG_STM32_STM32F40XX)
#elif defined(CONFIG_STM32_STM32F4XXX)
# include "chip/stm32f40xxx_dma.h"
#else
# error "Unknown STM32 DMA"
@ -72,7 +72,7 @@
# define DMA_STATUS_TEIF DMA_CHAN_TEIF_BIT /* Channel Transfer Error */
# define DMA_STATUS_HTIF DMA_CHAN_HTIF_BIT /* Channel Half Transfer */
# define DMA_STATUS_TCIF DMA_CHAN_TCIF_BIT /* Channel Transfer Complete */
#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX)
# define DMA_STATUS_FEIF 0 /* Stream FIFO error (ignored) */
# define DMA_STATUS_DMEIF DMA_STREAM_DMEIF_BIT /* Stream direct mode error */
# define DMA_STATUS_TEIF DMA_STREAM_TEIF_BIT /* Stream Transfer Error */
@ -119,7 +119,7 @@ struct stm32_dmaregs_s
uint32_t cpar;
uint32_t cmar;
};
#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX)
struct stm32_dmaregs_s
{
uint32_t lisr;

2
arch/arm/src/stm32/stm32_dumpgpio.c
View file

@ -196,7 +196,7 @@ int stm32_dumpgpio(uint32_t pinset, const char *msg)
getreg32(base + STM32_GPIO_AFRL_OFFSET),
getreg32(base + STM32_GPIO_BRR_OFFSET));
#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX)
DEBUGASSERT(port < STM32_NGPIO_PORTS);
_info("GPIO%c pinset: %08x base: %08x -- %s\n",

8
arch/arm/src/stm32/stm32_eth.c
View file

@ -125,7 +125,7 @@
#endif
#ifdef CONFIG_STM32_MII
# if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
# if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX)
# if !defined(CONFIG_STM32_MII_MCO1) && !defined(CONFIG_STM32_MII_MCO2) && !defined(CONFIG_STM32_MII_EXTCLK)
# warning "Neither CONFIG_STM32_MII_MCO1, CONFIG_STM32_MII_MCO2, nor CONFIG_STM32_MII_EXTCLK defined"
# endif
@ -140,7 +140,7 @@
#endif
#ifdef CONFIG_STM32_RMII
# if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
# if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX)
# if !defined(CONFIG_STM32_RMII_MCO1) && !defined(CONFIG_STM32_RMII_MCO2) && !defined(CONFIG_STM32_RMII_EXTCLK)
# warning "Neither CONFIG_STM32_RMII_MCO1, CONFIG_STM32_RMII_MCO2, nor CONFIG_STM32_RMII_EXTCLK defined"
# endif
@ -344,7 +344,7 @@
* ETH_MACCR_CSTF Bits 25: CRC stripping for Type frames (F2/F4 only)
*/
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX)
#define MACCR_CLEAR_BITS \
(ETH_MACCR_RE | ETH_MACCR_TE | ETH_MACCR_DC | ETH_MACCR_BL_MASK | \
ETH_MACCR_APCS | ETH_MACCR_RD | ETH_MACCR_IPCO | ETH_MACCR_DM | \
@ -531,7 +531,7 @@
* ETH_DMABMR_MB Bit 26: Mixed burst (F2/F4 only)
*/
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX)
#define DMABMR_CLEAR_MASK \
(ETH_DMABMR_SR | ETH_DMABMR_DA | ETH_DMABMR_DSL_MASK | ETH_DMABMR_EDFE | \
ETH_DMABMR_PBL_MASK | ETH_DMABMR_RTPR_MASK | ETH_DMABMR_FB | ETH_DMABMR_RDP_MASK | \

26
arch/arm/src/stm32/stm32_flash.c
View file

@ -62,10 +62,10 @@
/* Only for the STM32F[1|3|4]0xx family and STM32L15xx (EEPROM only) for now */
#if defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32F30XX) || \
defined (CONFIG_STM32_STM32F40XX) || defined(CONFIG_STM32_STM32L15XX)
defined (CONFIG_STM32_STM32F4XXX) || defined(CONFIG_STM32_STM32L15XX)
#if defined(CONFIG_STM32_FLASH_CONFIG_DEFAULT) && \
(defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX))
(defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX))
# warning "Default Flash Configuration Used - See Override Flash Size Designator"
#endif
@ -86,7 +86,7 @@
#if defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32F30XX)
# define FLASH_CR_PAGE_ERASE FLASH_CR_PER
# define FLASH_SR_WRITE_PROTECTION_ERROR FLASH_SR_WRPRT_ERR
#elif defined(CONFIG_STM32_STM32F40XX)
#elif defined(CONFIG_STM32_STM32F4XXX)
# define FLASH_CR_PAGE_ERASE FLASH_CR_SER
# define FLASH_SR_WRITE_PROTECTION_ERROR FLASH_SR_WRPERR
#endif
@ -394,13 +394,13 @@ ssize_t stm32_eeprom_erase(size_t addr, size_t eraselen)
*
************************************************************************************/
#ifdef CONFIG_STM32_STM32F40XX
#ifdef CONFIG_STM32_STM32F4XXX
int stm32_flash_writeprotect(size_t page, bool enabled)
{
uint32_t reg;
uint32_t val;
#ifdef CONFIG_STM32_STM32F40XX
#ifdef CONFIG_STM32_STM32F4XXX
if (page >= STM32_FLASH_NPAGES)
{
return -EFAULT;
@ -415,7 +415,7 @@ int stm32_flash_writeprotect(size_t page, bool enabled)
{
reg = STM32_FLASH_OPTCR;
}
#if defined(CONFIG_STM32_FLASH_CONFIG_I) && defined(CONFIG_STM32_STM32F40XX)
#if defined(CONFIG_STM32_FLASH_CONFIG_I) && defined(CONFIG_STM32_STM32F4XXX)
else
{
reg = STM32_FLASH_OPTCR1;
@ -500,7 +500,7 @@ size_t up_progmem_getaddress(size_t page)
#endif /* defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32F30XX) */
#ifdef CONFIG_STM32_STM32F40XX
#ifdef CONFIG_STM32_STM32F4XXX
size_t up_progmem_pagesize(size_t page)
{
@ -561,7 +561,7 @@ size_t up_progmem_getaddress(size_t page)
return base_address;
}
#endif /* def CONFIG_STM32_STM32F40XX */
#endif /* def CONFIG_STM32_STM32F4XXX */
#if !defined(CONFIG_STM32_STM32L15XX)
@ -592,7 +592,7 @@ ssize_t up_progmem_erasepage(size_t page)
sem_lock();
#if !defined(CONFIG_STM32_STM32F40XX)
#if !defined(CONFIG_STM32_STM32F4XXX)
if (!(getreg32(STM32_RCC_CR) & RCC_CR_HSION))
{
sem_unlock();
@ -612,7 +612,7 @@ ssize_t up_progmem_erasepage(size_t page)
page_address = up_progmem_getaddress(page);
putreg32(page_address, STM32_FLASH_AR);
#elif defined(CONFIG_STM32_STM32F40XX)
#elif defined(CONFIG_STM32_STM32F4XXX)
modifyreg32(STM32_FLASH_CR, FLASH_CR_SNB_MASK, FLASH_CR_SNB(page));
#endif
@ -685,7 +685,7 @@ ssize_t up_progmem_write(size_t addr, const void *buf, size_t count)
sem_lock();
#if !defined(CONFIG_STM32_STM32F40XX)
#if !defined(CONFIG_STM32_STM32F4XXX)
if (!(getreg32(STM32_RCC_CR) & RCC_CR_HSION))
{
sem_unlock();
@ -703,7 +703,7 @@ ssize_t up_progmem_write(size_t addr, const void *buf, size_t count)
modifyreg32(STM32_FLASH_CR, 0, FLASH_CR_PG);
#if defined(CONFIG_STM32_STM32F40XX)
#if defined(CONFIG_STM32_STM32F4XXX)
/* TODO: implement up_progmem_write() to support other sizes than 16-bits */
modifyreg32(STM32_FLASH_CR, FLASH_CR_PSIZE_MASK, FLASH_CR_PSIZE_X16);
#endif
@ -746,4 +746,4 @@ ssize_t up_progmem_write(size_t addr, const void *buf, size_t count)
#endif /* !defined(CONFIG_STM32_STM32L15XX) */
#endif /* defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32F30XX) || \
defined(CONFIG_STM32_STM32F40XX) || defined(CONFIG_STM32_STM32L15XX) */
defined(CONFIG_STM32_STM32F4XXX) || defined(CONFIG_STM32_STM32L15XX) */

2
arch/arm/src/stm32/stm32_fsmc.h
View file

@ -187,7 +187,7 @@
#define FSMC_BCR_WREN (1 << 12) /* Write enable bit */
#define FSMC_BCR_WAITEN (1 << 13) /* Wait enable bit */
#define FSMC_BCR_EXTMOD (1 << 14) /* Extended mode enable */
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX)
# define FSMC_BCR_ASYNCWAIT (1 << 15) /* Wait signal during asynchronous transfers */
#endif
#define FSMC_BCR_CBURSTRW (1 << 19) /* Write burst enable */

10
arch/arm/src/stm32/stm32_gpio.c
View file

@ -56,7 +56,7 @@
#if defined(CONFIG_STM32_STM32L15XX) || defined(CONFIG_STM32_STM32F20XX) || \
defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) || \
defined(CONFIG_STM32_STM32F37XX) || defined(CONFIG_STM32_STM32F40XX)
defined(CONFIG_STM32_STM32F37XX) || defined(CONFIG_STM32_STM32F4XXX)
# include "chip/stm32_syscfg.h"
#endif
@ -428,7 +428,7 @@ int stm32_configgpio(uint32_t cfgset)
#if defined(CONFIG_STM32_STM32L15XX) || defined(CONFIG_STM32_STM32F20XX) || \
defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) || \
defined(CONFIG_STM32_STM32F37XX) || defined(CONFIG_STM32_STM32F40XX)
defined(CONFIG_STM32_STM32F37XX) || defined(CONFIG_STM32_STM32F4XXX)
int stm32_configgpio(uint32_t cfgset)
{
uintptr_t base;
@ -683,7 +683,7 @@ int stm32_unconfiggpio(uint32_t cfgset)
cfgset |= GPIO_INPUT | GPIO_CNF_INFLOAT | GPIO_MODE_INPUT;
#elif defined(CONFIG_STM32_STM32L15XX) || defined(CONFIG_STM32_STM32F20XX) || \
defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) || \
defined(CONFIG_STM32_STM32F37XX) || defined(CONFIG_STM32_STM32F40XX)
defined(CONFIG_STM32_STM32F37XX) || defined(CONFIG_STM32_STM32F4XXX)
cfgset |= GPIO_INPUT | GPIO_FLOAT;
#else
# error "Unsupported STM32 chip"
@ -709,7 +709,7 @@ void stm32_gpiowrite(uint32_t pinset, bool value)
uint32_t offset;
#elif defined(CONFIG_STM32_STM32L15XX) || defined(CONFIG_STM32_STM32F20XX) || \
defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) || \
defined(CONFIG_STM32_STM32F37XX) || defined(CONFIG_STM32_STM32F40XX)
defined(CONFIG_STM32_STM32F37XX) || defined(CONFIG_STM32_STM32F4XXX)
uint32_t bit;
#endif
unsigned int port;
@ -743,7 +743,7 @@ void stm32_gpiowrite(uint32_t pinset, bool value)
#elif defined(CONFIG_STM32_STM32L15XX) || defined(CONFIG_STM32_STM32F20XX) || \
defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) || \
defined(CONFIG_STM32_STM32F37XX) || defined(CONFIG_STM32_STM32F40XX)
defined(CONFIG_STM32_STM32F37XX) || defined(CONFIG_STM32_STM32F4XXX)
if (value)
{

4
arch/arm/src/stm32/stm32_gpio.h
View file

@ -62,7 +62,7 @@
#elif defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) || \
defined(CONFIG_STM32_STM32F37XX)
# include "chip/stm32f30xxx_gpio.h"
#elif defined(CONFIG_STM32_STM32F40XX)
#elif defined(CONFIG_STM32_STM32F4XXX)
# include "chip/stm32f40xxx_gpio.h"
#else
# error "Unrecognized STM32 chip"
@ -203,7 +203,7 @@
#elif defined(CONFIG_STM32_STM32L15XX) || defined(CONFIG_STM32_STM32F20XX) || \
defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) || \
defined(CONFIG_STM32_STM32F37XX) || defined(CONFIG_STM32_STM32F40XX)
defined(CONFIG_STM32_STM32F37XX) || defined(CONFIG_STM32_STM32F4XXX)
/* Each port bit of the general-purpose I/O (GPIO) ports can be individually configured
* by software in several modes:

8
arch/arm/src/stm32/stm32_i2c.c
View file

@ -105,7 +105,7 @@
/* Experimentally enabled for STM32L15XX */
#if defined(CONFIG_STM32_STM32L15XX) || defined(CONFIG_STM32_STM32F10XX) || \
defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX)
/************************************************************************************
* Pre-processor Definitions
@ -155,7 +155,7 @@
#elif defined(CONFIG_STM32_STM32F10XX)
# define I2C_OUTPUT (GPIO_OUTPUT | GPIO_OUTPUT_SET | GPIO_CNF_OUTOD | \
GPIO_MODE_50MHz)
#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX)
# define I2C_OUTPUT (GPIO_OUTPUT | GPIO_FLOAT | GPIO_OPENDRAIN |\
GPIO_SPEED_50MHz | GPIO_OUTPUT_SET)
#endif
@ -1345,7 +1345,7 @@ static int stm32_i2c_isr_process(struct stm32_i2c_priv_s *priv)
* the F1 in that BTF is not set after data is received (only RXNE).
*/
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX) || \
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) || \
defined(CONFIG_STM32_STM32L15XX)
if (priv->dcnt <= 0 && (status & (I2C_SR1_BTF | I2C_SR1_RXNE)) != 0)
#else
@ -2003,5 +2003,5 @@ int stm32_i2cbus_uninitialize(FAR struct i2c_master_s *dev)
return OK;
}
#endif /* CONFIG_STM32_STM32F10XX || CONFIG_STM32_STM32F20XX || CONFIG_STM32_STM32F40XX */
#endif /* CONFIG_STM32_STM32F10XX || CONFIG_STM32_STM32F20XX || CONFIG_STM32_STM32F4XXX */
#endif /* CONFIG_STM32_I2C1 || CONFIG_STM32_I2C2 || CONFIG_STM32_I2C3 */

6
arch/arm/src/stm32/stm32_i2c_alt.c
View file

@ -112,7 +112,7 @@
/* Experimentally enabled for STM32L15XX */
#if defined(CONFIG_STM32_STM32L15XX) || defined(CONFIG_STM32_STM32F10XX) || \
defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX)
/************************************************************************************
* Pre-processor Definitions
@ -162,7 +162,7 @@
#elif defined(CONFIG_STM32_STM32F10XX)
# define I2C_OUTPUT (GPIO_OUTPUT | GPIO_OUTPUT_SET | GPIO_CNF_OUTOD | \
GPIO_MODE_50MHz)
#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX)
# define I2C_OUTPUT (GPIO_OUTPUT | GPIO_FLOAT | GPIO_OPENDRAIN |\
GPIO_SPEED_50MHz | GPIO_OUTPUT_SET)
#endif
@ -2451,5 +2451,5 @@ int stm32_i2cbus_uninitialize(FAR struct i2c_master_s *dev)
return OK;
}
#endif /* CONFIG_STM32_STM32F10XX || CONFIG_STM32_STM32F20XX || CONFIG_STM32_STM32F40XX */
#endif /* CONFIG_STM32_STM32F10XX || CONFIG_STM32_STM32F20XX || CONFIG_STM32_STM32F4XXX */
#endif /* CONFIG_STM32_I2C1 || CONFIG_STM32_I2C2 || CONFIG_STM32_I2C3 */

6
arch/arm/src/stm32/stm32_i2s.c
View file

@ -153,7 +153,7 @@
# define SPI_DMA_PRIO CONFIG_SPI_DMAPRIO
# elif defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32L15XX)
# define SPI_DMA_PRIO DMA_CCR_PRIMED
# elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
# elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX)
# define SPI_DMA_PRIO DMA_SCR_PRIMED
# else
# error "Unknown STM32 DMA"
@ -163,7 +163,7 @@
# if (SPI_DMA_PRIO & ~DMA_CCR_PL_MASK) != 0
# error "Illegal value for CONFIG_SPI_DMAPRIO"
# endif
# elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
# elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX)
# if (SPI_DMA_PRIO & ~DMA_SCR_PL_MASK) != 0
# error "Illegal value for CONFIG_SPI_DMAPRIO"
# endif
@ -185,7 +185,7 @@
# define SPI_TXDMA8_CONFIG (SPI_DMA_PRIO|DMA_CCR_MSIZE_8BITS |DMA_CCR_PSIZE_8BITS |DMA_CCR_MINC|DMA_CCR_DIR)
# define SPI_TXDMA16NULL_CONFIG (SPI_DMA_PRIO|DMA_CCR_MSIZE_8BITS |DMA_CCR_PSIZE_16BITS |DMA_CCR_DIR)
# define SPI_TXDMA8NULL_CONFIG (SPI_DMA_PRIO|DMA_CCR_MSIZE_8BITS |DMA_CCR_PSIZE_8BITS |DMA_CCR_DIR)
#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX)
# define SPI_RXDMA16_CONFIG (SPI_DMA_PRIO|DMA_SCR_MSIZE_16BITS|DMA_SCR_PSIZE_16BITS|DMA_SCR_MINC|DMA_SCR_DIR_P2M)
# define SPI_RXDMA8_CONFIG (SPI_DMA_PRIO|DMA_SCR_MSIZE_8BITS |DMA_SCR_PSIZE_8BITS |DMA_SCR_MINC|DMA_SCR_DIR_P2M)
# define SPI_RXDMA16NULL_CONFIG (SPI_DMA_PRIO|DMA_SCR_MSIZE_8BITS |DMA_SCR_PSIZE_16BITS |DMA_SCR_DIR_P2M)

2
arch/arm/src/stm32/stm32_iwdg.c
View file

@ -691,7 +691,7 @@ void stm32_iwdginitialize(FAR const char *devpath, uint32_t lsifreq)
defined(CONFIG_STM32_JTAG_SW_ENABLE)
{
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F30XX) || \
defined(CONFIG_STM32_STM32F40XX) || defined(CONFIG_STM32_STM32L15XX)
defined(CONFIG_STM32_STM32F4XXX) || defined(CONFIG_STM32_STM32L15XX)
uint32_t cr = getreg32(STM32_DBGMCU_APB1_FZ);
cr |= DBGMCU_APB1_IWDGSTOP;
putreg32(cr, STM32_DBGMCU_APB1_FZ);

2
arch/arm/src/stm32/stm32_lowputc.c
View file

@ -572,7 +572,7 @@ void stm32_lowsetup(void)
#elif defined(CONFIG_STM32_STM32L15XX) || defined(CONFIG_STM32_STM32F20XX) || \
defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) || \
defined(CONFIG_STM32_STM32F37XX) || defined(CONFIG_STM32_STM32F40XX)
defined(CONFIG_STM32_STM32F37XX) || defined(CONFIG_STM32_STM32F4XXX)
void stm32_lowsetup(void)
{

10
arch/arm/src/stm32/stm32_pwm.c
View file

@ -89,7 +89,7 @@
#else
# define TIMTYPE_TIM2 TIMTYPE_GENERAL32
#endif
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX)
# define TIMTYPE_TIM3 TIMTYPE_GENERAL32
# define TIMTYPE_TIM4 TIMTYPE_GENERAL32
#else
@ -1719,7 +1719,7 @@ static int pwm_timer(FAR struct stm32_pwmtimer_s *priv,
*/
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F30XX) || \
defined(CONFIG_STM32_STM32F37XX) || defined(CONFIG_STM32_STM32F40XX)
defined(CONFIG_STM32_STM32F37XX) || defined(CONFIG_STM32_STM32F4XXX)
ccer &= ~(ATIM_CCER_CC1NE | ATIM_CCER_CC1NP | ATIM_CCER_CC2NE | ATIM_CCER_CC2NP |
ATIM_CCER_CC3NE | ATIM_CCER_CC3NP | ATIM_CCER_CC4NP);
#else
@ -1742,12 +1742,12 @@ static int pwm_timer(FAR struct stm32_pwmtimer_s *priv,
pwm_putreg(priv, STM32_ATIM_BDTR_OFFSET, bdtr);
}
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F30XX) || \
defined(CONFIG_STM32_STM32F37XX) || defined(CONFIG_STM32_STM32F40XX)
defined(CONFIG_STM32_STM32F37XX) || defined(CONFIG_STM32_STM32F4XXX)
else
#endif
#endif
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F30XX) || \
defined(CONFIG_STM32_STM32F37XX) || defined(CONFIG_STM32_STM32F40XX)
defined(CONFIG_STM32_STM32F37XX) || defined(CONFIG_STM32_STM32F4XXX)
{
/* CCxNP must be cleared in any case */
@ -2284,7 +2284,7 @@ static int pwm_shutdown(FAR struct pwm_lowerhalf_s *dev)
#elif defined(CONFIG_STM32_STM32F20XX) || \
defined(CONFIG_STM32_STM32F30XX) || \
defined(CONFIG_STM32_STM32F37XX) || \
defined(CONFIG_STM32_STM32F40XX) || \
defined(CONFIG_STM32_STM32F4XXX) || \
defined(CONFIG_STM32_STM32L15XX)
pincfg |= GPIO_INPUT | GPIO_FLOAT;
#else

2
arch/arm/src/stm32/stm32_pwr.c
View file

@ -248,7 +248,7 @@ void stm32_pwr_enablebkp(bool writable)
*
************************************************************************************/
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX)
void stm32_pwr_enablebreg(bool regon)
{
uint16_t regval;

2
arch/arm/src/stm32/stm32_pwr.h
View file

@ -146,7 +146,7 @@ void stm32_pwr_enablebkp(bool writable);
*
************************************************************************************/
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX)
void stm32_pwr_enablebreg(bool regon);
#else
# define stm32_pwr_enablebreg(regon)

4
arch/arm/src/stm32/stm32_qencoder.c
View file

@ -115,7 +115,7 @@
/* On the F4 series, TIM2 and TIM5 are 32-bit. All of the rest are 16-bit */
#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX)
/* If TIM2 or TIM5 are enabled, then we have 32-bit timers */
@ -212,7 +212,7 @@
GPIO_MODE_INPUT)
#elif defined(CONFIG_STM32_STM32F20XX) || \
defined(CONFIG_STM32_STM32F30XX) || \
defined(CONFIG_STM32_STM32F40XX)
defined(CONFIG_STM32_STM32F4XXX)
# define STM32_GPIO_INPUT_FLOAT (GPIO_INPUT | GPIO_FLOAT)
#else
# error "Unrecognized STM32 chip"

2
arch/arm/src/stm32/stm32_rcc.c
View file

@ -86,7 +86,7 @@
# include "stm32f33xxx_rcc.c"
#elif defined(CONFIG_STM32_STM32F37XX)
# include "stm32f37xxx_rcc.c"
#elif defined(CONFIG_STM32_STM32F40XX)
#elif defined(CONFIG_STM32_STM32F4XXX)
# include "stm32f40xxx_rcc.c"
#else
# error "Unsupported STM32 chip"

6
arch/arm/src/stm32/stm32_rcc.h
View file

@ -57,7 +57,7 @@
# include "chip/stm32f33xxx_rcc.h"
#elif defined(CONFIG_STM32_STM32F37XX)
# include "chip/stm32f37xxx_rcc.h"
#elif defined(CONFIG_STM32_STM32F40XX)
#elif defined(CONFIG_STM32_STM32F4XXX)
# include "chip/stm32f40xxx_rcc.h"
#endif
@ -113,7 +113,7 @@ extern uint32_t _vectors[]; /* See stm32_vectors.S */
*
************************************************************************************/
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX)
static inline void stm32_mco1config(uint32_t source, uint32_t div)
{
uint32_t regval;
@ -214,7 +214,7 @@ static inline void stm32_mcodivconfig(uint32_t source, uint32_t divider)
*
************************************************************************************/
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX)
static inline void stm32_mco2config(uint32_t source, uint32_t div)
{
uint32_t regval;

2
arch/arm/src/stm32/stm32_rtc.c
View file

@ -66,6 +66,6 @@
#elif defined(CONFIG_STM32_STM32L15XX) || defined(CONFIG_STM32_STM32F20XX) || \
defined(CONFIG_STM32_STM32F30XX)
# include "stm32_rtcc.c"
#elif defined(CONFIG_STM32_STM32F40XX)
#elif defined(CONFIG_STM32_STM32F4XXX)
# include "stm32f40xxx_rtcc.c"
#endif

4
arch/arm/src/stm32/stm32_rtc.h
View file

@ -60,13 +60,13 @@
*/
#elif defined(CONFIG_STM32_STM32L15XX) || defined(CONFIG_STM32_STM32F20XX) || \
defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F40XX)
defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F4XXX)
# include "chip/stm32_rtcc.h"
#endif
/* Alarm function differs from part to part */
#ifdef CONFIG_STM32_STM32F40XX
#ifdef CONFIG_STM32_STM32F4XXX
# include "stm32f40xxx_alarm.h"
#else
# include "stm32_alarm.h"

14
arch/arm/src/stm32/stm32_rtc_lowerhalf.c
View file

@ -60,7 +60,7 @@
* Pre-processor Definitions
****************************************************************************/
#ifdef CONFIG_STM32_STM32F40XX
#ifdef CONFIG_STM32_STM32F4XXX
# define STM32_NALARMS 2
#else
# define STM32_NALARMS 1
@ -75,7 +75,7 @@ struct stm32_cbinfo_s
{
volatile rtc_alarm_callback_t cb; /* Callback when the alarm expires */
volatile FAR void *priv; /* Private argurment to accompany callback */
#ifdef CONFIG_STM32_STM32F40XX
#ifdef CONFIG_STM32_STM32F4XXX
uint8_t id; /* Identifies the alarm */
#endif
};
@ -174,7 +174,7 @@ static struct stm32_lowerhalf_s g_rtc_lowerhalf =
****************************************************************************/
#ifdef CONFIG_RTC_ALARM
#ifdef CONFIG_STM32_STM32F40XX
#ifdef CONFIG_STM32_STM32F4XXX
static void stm32_alarm_callback(FAR void *arg, unsigned int alarmid)
{
FAR struct stm32_lowerhalf_s *lower;
@ -229,7 +229,7 @@ static void stm32_alarm_callback(void)
}
}
#endif /* CONFIG_STM32_STM32F40XX */
#endif /* CONFIG_STM32_STM32F4XXX */
#endif /* CONFIG_RTC_ALARM */
/****************************************************************************
@ -393,7 +393,7 @@ static bool stm32_havesettime(FAR struct rtc_lowerhalf_s *lower)
static int stm32_setalarm(FAR struct rtc_lowerhalf_s *lower,
FAR const struct lower_setalarm_s *alarminfo)
{
#ifdef CONFIG_STM32_STM32F40XX
#ifdef CONFIG_STM32_STM32F4XXX
FAR struct stm32_lowerhalf_s *priv;
FAR struct stm32_cbinfo_s *cbinfo;
struct alm_setalarm_s lowerinfo;
@ -492,7 +492,7 @@ static int stm32_setalarm(FAR struct rtc_lowerhalf_s *lower,
static int stm32_setrelative(FAR struct rtc_lowerhalf_s *lower,
FAR const struct lower_setrelative_s *alarminfo)
{
#ifdef CONFIG_STM32_STM32F40XX
#ifdef CONFIG_STM32_STM32F4XXX
struct lower_setalarm_s setalarm;
struct tm time;
time_t seconds;
@ -643,7 +643,7 @@ static int stm32_setrelative(FAR struct rtc_lowerhalf_s *lower,
#ifdef CONFIG_RTC_ALARM
static int stm32_cancelalarm(FAR struct rtc_lowerhalf_s *lower, int alarmid)
{
#ifdef CONFIG_STM32_STM32F40XX
#ifdef CONFIG_STM32_STM32F4XXX
FAR struct stm32_lowerhalf_s *priv;
FAR struct stm32_cbinfo_s *cbinfo;
int ret = -EINVAL;

10
arch/arm/src/stm32/stm32_sdio.c
View file

@ -126,7 +126,7 @@
# ifndef CONFIG_STM32_SDIO_DMAPRIO
# if defined(CONFIG_STM32_STM32F10XX)
# define CONFIG_STM32_SDIO_DMAPRIO DMA_CCR_PRIMED
# elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
# elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX)
# define CONFIG_STM32_SDIO_DMAPRIO DMA_SCR_PRIVERYHI
# else
# error "Unknown STM32 DMA"
@ -136,7 +136,7 @@
# if (CONFIG_STM32_SDIO_DMAPRIO & ~DMA_CCR_PL_MASK) != 0
# error "Illegal value for CONFIG_STM32_SDIO_DMAPRIO"
# endif
# elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
# elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX)
# if (CONFIG_STM32_SDIO_DMAPRIO & ~DMA_SCR_PL_MASK) != 0
# error "Illegal value for CONFIG_STM32_SDIO_DMAPRIO"
# endif
@ -207,7 +207,7 @@
/* STM32 F4 stream configuration register (SCR) settings. */
#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX)
# define SDIO_RXDMA32_CONFIG (DMA_SCR_PFCTRL | DMA_SCR_DIR_P2M|DMA_SCR_MINC | \
DMA_SCR_PSIZE_32BITS | DMA_SCR_MSIZE_32BITS | \
CONFIG_STM32_SDIO_DMAPRIO | DMA_SCR_PBURST_INCR4 | \
@ -227,7 +227,7 @@
#if defined(CONFIG_STM32_STM32F10XX)
# define SDIO_DMACHAN DMACHAN_SDIO
#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX)
# define SDIO_DMACHAN DMAMAP_SDIO
#else
# error "Unknown STM32 DMA"
@ -2649,7 +2649,7 @@ static int stm32_registercallback(FAR struct sdio_dev_s *dev,
static int stm32_dmapreflight(FAR struct sdio_dev_s *dev,
FAR const uint8_t *buffer, size_t buflen)
{
#if !defined(CONFIG_STM32_STM32F40XX)
#if !defined(CONFIG_STM32_STM32F4XXX)
struct stm32_dev_s *priv = (struct stm32_dev_s *)dev;
DEBUGASSERT(priv != NULL && buffer != NULL && buflen > 0);

10
arch/arm/src/stm32/stm32_serial.c
View file

@ -80,7 +80,7 @@
#ifdef SERIAL_HAVE_DMA
# if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
# if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX)
/* Verify that DMA has been enabled and the DMA channel has been defined.
*/
@ -198,7 +198,7 @@
defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) || \
defined(CONFIG_STM32_STM32F37XX)
# define CONFIG_USART_DMAPRIO DMA_CCR_PRIMED
# elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
# elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX)
# define CONFIG_USART_DMAPRIO DMA_SCR_PRIMED
# else
# error "Unknown STM32 DMA"
@ -210,7 +210,7 @@
# if (CONFIG_USART_DMAPRIO & ~DMA_CCR_PL_MASK) != 0
# error "Illegal value for CONFIG_USART_DMAPRIO"
# endif
# elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
# elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX)
# if (CONFIG_USART_DMAPRIO & ~DMA_SCR_PL_MASK) != 0
# error "Illegal value for CONFIG_USART_DMAPRIO"
# endif
@ -220,7 +220,7 @@
/* DMA control word */
# if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
# if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX)
# define SERIAL_DMA_CONTROL_WORD \
(DMA_SCR_DIR_P2M | \
DMA_SCR_CIRC | \
@ -1265,7 +1265,7 @@ static void up_set_format(struct uart_dev_s *dev)
fraction = (usartdiv32 - (mantissa << 5) + 1) >> 1;
#if defined(CONFIG_STM32_STM32F40XX)
#if defined(CONFIG_STM32_STM32F4XXX)
/* The F4 supports 8 X in oversampling additional to the
* standard oversampling by 16.
*

6
arch/arm/src/stm32/stm32_spi.c
View file

@ -111,7 +111,7 @@
# define SPI_DMA_PRIO CONFIG_SPI_DMAPRIO
# elif defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32L15XX)
# define SPI_DMA_PRIO DMA_CCR_PRIMED
# elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
# elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX)
# define SPI_DMA_PRIO DMA_SCR_PRIMED
# else
# error "Unknown STM32 DMA"
@ -121,7 +121,7 @@
# if (SPI_DMA_PRIO & ~DMA_CCR_PL_MASK) != 0
# error "Illegal value for CONFIG_SPI_DMAPRIO"
# endif
# elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
# elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX)
# if (SPI_DMA_PRIO & ~DMA_SCR_PL_MASK) != 0
# error "Illegal value for CONFIG_SPI_DMAPRIO"
# endif
@ -143,7 +143,7 @@
# define SPI_TXDMA8_CONFIG (SPI_DMA_PRIO|DMA_CCR_MSIZE_8BITS |DMA_CCR_PSIZE_8BITS |DMA_CCR_MINC|DMA_CCR_DIR)
# define SPI_TXDMA16NULL_CONFIG (SPI_DMA_PRIO|DMA_CCR_MSIZE_8BITS |DMA_CCR_PSIZE_16BITS |DMA_CCR_DIR)
# define SPI_TXDMA8NULL_CONFIG (SPI_DMA_PRIO|DMA_CCR_MSIZE_8BITS |DMA_CCR_PSIZE_8BITS |DMA_CCR_DIR)
#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX)
# define SPI_RXDMA16_CONFIG (SPI_DMA_PRIO|DMA_SCR_MSIZE_16BITS|DMA_SCR_PSIZE_16BITS|DMA_SCR_MINC|DMA_SCR_DIR_P2M)
# define SPI_RXDMA8_CONFIG (SPI_DMA_PRIO|DMA_SCR_MSIZE_8BITS |DMA_SCR_PSIZE_8BITS |DMA_SCR_MINC|DMA_SCR_DIR_P2M)
# define SPI_RXDMA16NULL_CONFIG (SPI_DMA_PRIO|DMA_SCR_MSIZE_8BITS |DMA_SCR_PSIZE_16BITS |DMA_SCR_DIR_P2M)

2
arch/arm/src/stm32/stm32_syscfg.h
View file

@ -53,7 +53,7 @@
# include "chip/stm32f33xxx_syscfg.h"
#elif defined(CONFIG_STM32_STM32F37XX)
# include "chip/stm32f37xxx_syscfg.h"
#elif defined(CONFIG_STM32_STM32F40XX)
#elif defined(CONFIG_STM32_STM32F4XXX)
# include "chip/stm32f40xxx_syscfg.h"
#endif

2
arch/arm/src/stm32/stm32_tim_lowerhalf.c
View file

@ -73,7 +73,7 @@
#else
# define STM32_TIM2_RES 32
#endif
#if defined(CONFIG_STM32_STM32L20XX) || defined(CONFIG_STM32_STM32F40XX)
#if defined(CONFIG_STM32_STM32L20XX) || defined(CONFIG_STM32_STM32F4XXX)
# define STM32_TIM3_RES 32
# define STM32_TIM4_RES 32
#else

2
arch/arm/src/stm32/stm32_uart.h
View file

@ -53,7 +53,7 @@
#elif defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) || \
defined(CONFIG_STM32_STM32F37XX)
# include "chip/stm32f30xxx_uart.h"
#elif defined(CONFIG_STM32_STM32F40XX)
#elif defined(CONFIG_STM32_STM32F4XXX)
# include "chip/stm32f40xxx_uart.h"
#else
# error "Unsupported STM32 UART"

2
arch/arm/src/stm32/stm32_wwdg.c
View file

@ -790,7 +790,7 @@ void stm32_wwdginitialize(FAR const char *devpath)
defined(CONFIG_STM32_JTAG_SW_ENABLE)
{
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F30XX) || \
defined(CONFIG_STM32_STM32F40XX) || defined(CONFIG_STM32_STM32L15XX)
defined(CONFIG_STM32_STM32F4XXX) || defined(CONFIG_STM32_STM32L15XX)
uint32_t cr = getreg32(STM32_DBGMCU_APB1_FZ);
cr |= DBGMCU_APB1_WWDGSTOP;
putreg32(cr, STM32_DBGMCU_APB1_FZ);

4
arch/arm/src/stm32/stm32f40xxx_dma.c
View file

@ -59,7 +59,7 @@
* as well?)
*/
#if defined(CONFIG_STM32_STM32F40XX)
#if defined(CONFIG_STM32_STM32F4XXX)
/****************************************************************************
* Pre-processor Definitions
@ -1050,4 +1050,4 @@ void stm32_dmadump(DMA_HANDLE handle, const struct stm32_dmaregs_s *regs,
}
#endif
#endif /* CONFIG_STM32_STM32F40XX */
#endif /* CONFIG_STM32_STM32F4XXX */

6
arch/arm/src/stm32/stm32f40xxx_i2c.c
View file

@ -105,7 +105,7 @@
/* Experimentally enabled for STM32L15XX */
#if defined(CONFIG_STM32_STM32L15XX) || defined(CONFIG_STM32_STM32F10XX) || \
defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX)
/************************************************************************************
* Pre-processor Definitions
@ -155,7 +155,7 @@
#elif defined(CONFIG_STM32_STM32F10XX)
# define I2C_OUTPUT (GPIO_OUTPUT | GPIO_OUTPUT_SET | GPIO_CNF_OUTOD | \
GPIO_MODE_50MHz)
#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX)
# define I2C_OUTPUT (GPIO_OUTPUT | GPIO_FLOAT | GPIO_OPENDRAIN |\
GPIO_SPEED_50MHz | GPIO_OUTPUT_SET)
#endif
@ -2747,5 +2747,5 @@ int stm32_i2cbus_uninitialize(FAR struct i2c_master_s *dev)
return OK;
}
#endif /* CONFIG_STM32_STM32F10XX || CONFIG_STM32_STM32F20XX || CONFIG_STM32_STM32F40XX */
#endif /* CONFIG_STM32_STM32F10XX || CONFIG_STM32_STM32F20XX || CONFIG_STM32_STM32F4XXX */
#endif /* CONFIG_STM32_I2C1 || CONFIG_STM32_I2C2 || CONFIG_STM32_I2C3 */

13
configs/Board.mk
View file

@ -50,6 +50,9 @@ OBJS = $(AOBJS) $(COBJS)
SCHEDSRCDIR = $(TOPDIR)$(DELIM)sched
ARCHSRCDIR = $(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src
ifneq ($(CONFIG_ARCH_FAMILY),)
ARCH_FAMILY = $(patsubst "%",%,$(CONFIG_ARCH_FAMILY))
endif
ifneq ($(ZDSVERSION),)
ifeq ($(WINTOOL),y)
@ -67,8 +70,8 @@ ifeq ($(CONFIG_ARCH_SIM),y)
else
CFLAGS += -I "${shell cygpath -w $(ARCHSRCDIR)$(DELIM)chip}"
CFLAGS += -I "${shell cygpath -w $(ARCHSRCDIR)$(DELIM)common}"
ifneq ($(CONFIG_ARCH_FAMILY),)
CFLAGS += -I "${shell cygpath -w $(ARCHSRCDIR)$(DELIM)$(CONFIG_ARCH_FAMILY)}"
ifneq ($(ARCH_FAMILY),)
CFLAGS += -I "${shell cygpath -w $(ARCHSRCDIR)$(DELIM)$(ARCH_FAMILY)}"
endif
endif
else
@ -78,8 +81,8 @@ ifeq ($(CONFIG_ARCH_SIM),y)
else
CFLAGS += -I$(ARCHSRCDIR)$(DELIM)chip
CFLAGS += -I$(ARCHSRCDIR)$(DELIM)common
ifneq ($(CONFIG_ARCH_FAMILY),)
CFLAGS += -I$(ARCHSRCDIR)$(DELIM)$(CONFIG_ARCH_FAMILY)
ifneq ($(ARCH_FAMILY),)
CFLAGS += -I$(ARCHSRCDIR)$(DELIM)$(ARCH_FAMILY)
endif
endif
endif
@ -113,7 +116,7 @@ $(CXXOBJS) $(LINKOBJS): %$(OBJEXT): %.cxx
$(call COMPILEXX, $<, $@)
libboard$(LIBEXT): $(OBJS) $(CXXOBJS)
$(Q) $(AR) $@ # Create an empty archive
$(Q) $(AR) $@
ifneq ($(OBJS),)
$(call ARCHIVE, $@, $(OBJS) $(CXXOBJS))
endif

2
configs/clicker2-stm32/knsh/defconfig
View file

@ -326,7 +326,7 @@ CONFIG_STM32_FLASH_CONFIG_DEFAULT=y
# CONFIG_STM32_STM32F303 is not set
# CONFIG_STM32_STM32F33XX is not set
# CONFIG_STM32_STM32F37XX is not set
CONFIG_STM32_STM32F40XX=y
CONFIG_STM32_STM32F4XXX=y
# CONFIG_STM32_STM32F401 is not set
# CONFIG_STM32_STM32F410 is not set
# CONFIG_STM32_STM32F411 is not set

2
configs/clicker2-stm32/mrf24j40-6lowpan/defconfig
View file

@ -318,7 +318,7 @@ CONFIG_STM32_FLASH_CONFIG_DEFAULT=y
# CONFIG_STM32_STM32F303 is not set
# CONFIG_STM32_STM32F33XX is not set
# CONFIG_STM32_STM32F37XX is not set
CONFIG_STM32_STM32F40XX=y
CONFIG_STM32_STM32F4XXX=y
# CONFIG_STM32_STM32F401 is not set
# CONFIG_STM32_STM32F410 is not set
# CONFIG_STM32_STM32F411 is not set

2
configs/clicker2-stm32/mrf24j40-mac/defconfig
View file

@ -319,7 +319,7 @@ CONFIG_STM32_FLASH_CONFIG_DEFAULT=y
# CONFIG_STM32_STM32F303 is not set
# CONFIG_STM32_STM32F33XX is not set
# CONFIG_STM32_STM32F37XX is not set
CONFIG_STM32_STM32F40XX=y
CONFIG_STM32_STM32F4XXX=y
# CONFIG_STM32_STM32F401 is not set
# CONFIG_STM32_STM32F410 is not set
# CONFIG_STM32_STM32F411 is not set

2
configs/clicker2-stm32/mrf24j40-starhub/defconfig
View file

@ -318,7 +318,7 @@ CONFIG_STM32_FLASH_CONFIG_DEFAULT=y
# CONFIG_STM32_STM32F303 is not set
# CONFIG_STM32_STM32F33XX is not set
# CONFIG_STM32_STM32F37XX is not set
CONFIG_STM32_STM32F40XX=y
CONFIG_STM32_STM32F4XXX=y
# CONFIG_STM32_STM32F401 is not set
# CONFIG_STM32_STM32F410 is not set
# CONFIG_STM32_STM32F411 is not set

2
configs/clicker2-stm32/mrf24j40-starpoint/defconfig
View file

@ -318,7 +318,7 @@ CONFIG_STM32_FLASH_CONFIG_DEFAULT=y
# CONFIG_STM32_STM32F303 is not set
# CONFIG_STM32_STM32F33XX is not set
# CONFIG_STM32_STM32F37XX is not set
CONFIG_STM32_STM32F40XX=y
CONFIG_STM32_STM32F4XXX=y
# CONFIG_STM32_STM32F401 is not set
# CONFIG_STM32_STM32F410 is not set
# CONFIG_STM32_STM32F411 is not set

2
configs/clicker2-stm32/nsh/defconfig
View file

@ -319,7 +319,7 @@ CONFIG_STM32_FLASH_CONFIG_DEFAULT=y
# CONFIG_STM32_STM32F303 is not set
# CONFIG_STM32_STM32F33XX is not set
# CONFIG_STM32_STM32F37XX is not set
CONFIG_STM32_STM32F40XX=y
CONFIG_STM32_STM32F4XXX=y
# CONFIG_STM32_STM32F401 is not set
# CONFIG_STM32_STM32F410 is not set
# CONFIG_STM32_STM32F411 is not set

2
configs/clicker2-stm32/usbnsh/defconfig
View file

@ -319,7 +319,7 @@ CONFIG_STM32_FLASH_CONFIG_DEFAULT=y
# CONFIG_STM32_STM32F303 is not set
# CONFIG_STM32_STM32F33XX is not set
# CONFIG_STM32_STM32F37XX is not set
CONFIG_STM32_STM32F40XX=y
CONFIG_STM32_STM32F4XXX=y
# CONFIG_STM32_STM32F401 is not set
# CONFIG_STM32_STM32F410 is not set
# CONFIG_STM32_STM32F411 is not set

2
configs/cloudctrl/nsh/defconfig
View file

@ -328,7 +328,7 @@ CONFIG_STM32_CONNECTIVITYLINE=y
# CONFIG_STM32_STM32F303 is not set
# CONFIG_STM32_STM32F33XX is not set
# CONFIG_STM32_STM32F37XX is not set
# CONFIG_STM32_STM32F40XX is not set
# CONFIG_STM32_STM32F4XXX is not set
# CONFIG_STM32_STM32F401 is not set
# CONFIG_STM32_STM32F411 is not set
# CONFIG_STM32_STM32F405 is not set

12
configs/dk-tm4c129x/README.txt
View file

@ -757,7 +757,8 @@ Where <subdir> is one of the following:
configuration other than using IPv6. So all of the notes above
regarding the nsh configuration apply.
Telnet does not work with IPv6.
Telnet does work with IPv6 but is not enabled in this
configuration (but could be).
2. This configuration can be modified to that both IPv4 and IPv6
are support. Here is a summary of the additional configuration
@ -788,9 +789,14 @@ Where <subdir> is one of the following:
ping6 fc00::2 (Linux)
ping -6 fc00::2 (Windows cmd)
and Telnet again works from the host:
and Telnet is now enabled and works from the host... but only using
IPv6 addressing:
telnet 10.0.0.2
telnet fc00::2
That is because the Telnet daemon will default to IPv6 and there is
no Telnet option to let you select which if both IPv4 and IPv6 are
enabled.
3. You can enable IPv6 autonomous address configuration with the
following changes to the configuration:

2
configs/fire-stm32v2/nsh/defconfig
View file

@ -328,7 +328,7 @@ CONFIG_STM32_HIGHDENSITY=y
# CONFIG_STM32_STM32F303 is not set
# CONFIG_STM32_STM32F33XX is not set
# CONFIG_STM32_STM32F37XX is not set
# CONFIG_STM32_STM32F40XX is not set
# CONFIG_STM32_STM32F4XXX is not set
# CONFIG_STM32_STM32F401 is not set
# CONFIG_STM32_STM32F411 is not set
# CONFIG_STM32_STM32F405 is not set

2
configs/hymini-stm32v/nsh/defconfig
View file

@ -313,7 +313,7 @@ CONFIG_STM32_HIGHDENSITY=y
# CONFIG_STM32_STM32F303 is not set
# CONFIG_STM32_STM32F33XX is not set
# CONFIG_STM32_STM32F37XX is not set
# CONFIG_STM32_STM32F40XX is not set
# CONFIG_STM32_STM32F4XXX is not set
# CONFIG_STM32_STM32F401 is not set
# CONFIG_STM32_STM32F411 is not set
# CONFIG_STM32_STM32F405 is not set

2
configs/hymini-stm32v/nsh2/defconfig
View file

@ -313,7 +313,7 @@ CONFIG_STM32_HIGHDENSITY=y
# CONFIG_STM32_STM32F303 is not set
# CONFIG_STM32_STM32F33XX is not set
# CONFIG_STM32_STM32F37XX is not set
# CONFIG_STM32_STM32F40XX is not set
# CONFIG_STM32_STM32F4XXX is not set
# CONFIG_STM32_STM32F401 is not set
# CONFIG_STM32_STM32F411 is not set
# CONFIG_STM32_STM32F405 is not set

2
configs/hymini-stm32v/usbmsc/defconfig
View file

@ -313,7 +313,7 @@ CONFIG_STM32_HIGHDENSITY=y
# CONFIG_STM32_STM32F303 is not set
# CONFIG_STM32_STM32F33XX is not set
# CONFIG_STM32_STM32F37XX is not set
# CONFIG_STM32_STM32F40XX is not set
# CONFIG_STM32_STM32F4XXX is not set
# CONFIG_STM32_STM32F401 is not set
# CONFIG_STM32_STM32F411 is not set
# CONFIG_STM32_STM32F405 is not set

2
configs/hymini-stm32v/usbnsh/defconfig
View file

@ -313,7 +313,7 @@ CONFIG_STM32_HIGHDENSITY=y
# CONFIG_STM32_STM32F303 is not set
# CONFIG_STM32_STM32F33XX is not set
# CONFIG_STM32_STM32F37XX is not set
# CONFIG_STM32_STM32F40XX is not set
# CONFIG_STM32_STM32F4XXX is not set
# CONFIG_STM32_STM32F401 is not set
# CONFIG_STM32_STM32F411 is not set
# CONFIG_STM32_STM32F405 is not set

2
configs/hymini-stm32v/usbserial/defconfig
View file

@ -313,7 +313,7 @@ CONFIG_STM32_HIGHDENSITY=y
# CONFIG_STM32_STM32F303 is not set
# CONFIG_STM32_STM32F33XX is not set
# CONFIG_STM32_STM32F37XX is not set
# CONFIG_STM32_STM32F40XX is not set
# CONFIG_STM32_STM32F4XXX is not set
# CONFIG_STM32_STM32F401 is not set
# CONFIG_STM32_STM32F411 is not set
# CONFIG_STM32_STM32F405 is not set

2
configs/maple/nsh/defconfig
View file

@ -313,7 +313,7 @@ CONFIG_STM32_MEDIUMDENSITY=y
# CONFIG_STM32_STM32F303 is not set
# CONFIG_STM32_STM32F33XX is not set
# CONFIG_STM32_STM32F37XX is not set
# CONFIG_STM32_STM32F40XX is not set
# CONFIG_STM32_STM32F4XXX is not set
# CONFIG_STM32_STM32F401 is not set
# CONFIG_STM32_STM32F411 is not set
# CONFIG_STM32_STM32F405 is not set

2
configs/maple/nx/defconfig
View file

@ -313,7 +313,7 @@ CONFIG_STM32_MEDIUMDENSITY=y
# CONFIG_STM32_STM32F303 is not set
# CONFIG_STM32_STM32F33XX is not set
# CONFIG_STM32_STM32F37XX is not set
# CONFIG_STM32_STM32F40XX is not set
# CONFIG_STM32_STM32F4XXX is not set
# CONFIG_STM32_STM32F401 is not set
# CONFIG_STM32_STM32F411 is not set
# CONFIG_STM32_STM32F405 is not set

2
configs/maple/usbnsh/defconfig
View file

@ -313,7 +313,7 @@ CONFIG_STM32_MEDIUMDENSITY=y
# CONFIG_STM32_STM32F303 is not set
# CONFIG_STM32_STM32F33XX is not set
# CONFIG_STM32_STM32F37XX is not set
# CONFIG_STM32_STM32F40XX is not set
# CONFIG_STM32_STM32F4XXX is not set
# CONFIG_STM32_STM32F401 is not set
# CONFIG_STM32_STM32F411 is not set
# CONFIG_STM32_STM32F405 is not set

2
configs/mikroe-stm32f4/fulldemo/defconfig
View file

@ -320,7 +320,7 @@ CONFIG_STM32_FLASH_CONFIG_DEFAULT=y
# CONFIG_STM32_STM32F303 is not set
# CONFIG_STM32_STM32F33XX is not set
# CONFIG_STM32_STM32F37XX is not set
CONFIG_STM32_STM32F40XX=y
CONFIG_STM32_STM32F4XXX=y
# CONFIG_STM32_STM32F401 is not set
# CONFIG_STM32_STM32F410 is not set
# CONFIG_STM32_STM32F411 is not set

2
configs/mikroe-stm32f4/kostest/defconfig
View file

@ -326,7 +326,7 @@ CONFIG_STM32_FLASH_CONFIG_DEFAULT=y
# CONFIG_STM32_STM32F303 is not set
# CONFIG_STM32_STM32F33XX is not set
# CONFIG_STM32_STM32F37XX is not set
CONFIG_STM32_STM32F40XX=y
CONFIG_STM32_STM32F4XXX=y
# CONFIG_STM32_STM32F401 is not set
# CONFIG_STM32_STM32F410 is not set
# CONFIG_STM32_STM32F411 is not set

2
configs/mikroe-stm32f4/nsh/defconfig
View file

@ -320,7 +320,7 @@ CONFIG_STM32_FLASH_CONFIG_DEFAULT=y
# CONFIG_STM32_STM32F303 is not set
# CONFIG_STM32_STM32F33XX is not set
# CONFIG_STM32_STM32F37XX is not set
CONFIG_STM32_STM32F40XX=y
CONFIG_STM32_STM32F4XXX=y
# CONFIG_STM32_STM32F401 is not set
# CONFIG_STM32_STM32F410 is not set
# CONFIG_STM32_STM32F411 is not set

2
configs/mikroe-stm32f4/nx/defconfig
View file

@ -319,7 +319,7 @@ CONFIG_STM32_FLASH_CONFIG_DEFAULT=y
# CONFIG_STM32_STM32F303 is not set
# CONFIG_STM32_STM32F33XX is not set
# CONFIG_STM32_STM32F37XX is not set
CONFIG_STM32_STM32F40XX=y
CONFIG_STM32_STM32F4XXX=y
# CONFIG_STM32_STM32F401 is not set
# CONFIG_STM32_STM32F410 is not set
# CONFIG_STM32_STM32F411 is not set

2
configs/mikroe-stm32f4/nxlines/defconfig
View file

@ -319,7 +319,7 @@ CONFIG_STM32_FLASH_CONFIG_DEFAULT=y
# CONFIG_STM32_STM32F303 is not set
# CONFIG_STM32_STM32F33XX is not set
# CONFIG_STM32_STM32F37XX is not set
CONFIG_STM32_STM32F40XX=y
CONFIG_STM32_STM32F4XXX=y
# CONFIG_STM32_STM32F401 is not set
# CONFIG_STM32_STM32F410 is not set
# CONFIG_STM32_STM32F411 is not set

2
configs/mikroe-stm32f4/nxtext/defconfig
View file

@ -319,7 +319,7 @@ CONFIG_STM32_FLASH_CONFIG_DEFAULT=y
# CONFIG_STM32_STM32F303 is not set
# CONFIG_STM32_STM32F33XX is not set
# CONFIG_STM32_STM32F37XX is not set
CONFIG_STM32_STM32F40XX=y
CONFIG_STM32_STM32F4XXX=y
# CONFIG_STM32_STM32F401 is not set
# CONFIG_STM32_STM32F410 is not set
# CONFIG_STM32_STM32F411 is not set

2
configs/mikroe-stm32f4/usbnsh/defconfig
View file

@ -320,7 +320,7 @@ CONFIG_STM32_FLASH_CONFIG_DEFAULT=y
# CONFIG_STM32_STM32F303 is not set
# CONFIG_STM32_STM32F33XX is not set
# CONFIG_STM32_STM32F37XX is not set
CONFIG_STM32_STM32F40XX=y
CONFIG_STM32_STM32F4XXX=y
# CONFIG_STM32_STM32F401 is not set
# CONFIG_STM32_STM32F410 is not set
# CONFIG_STM32_STM32F411 is not set

2
configs/nucleo-f303re/adc/defconfig
View file

@ -315,7 +315,7 @@ CONFIG_STM32_STM32F30XX=y
CONFIG_STM32_STM32F303=y
# CONFIG_STM32_STM32F33XX is not set
# CONFIG_STM32_STM32F37XX is not set
# CONFIG_STM32_STM32F40XX is not set
# CONFIG_STM32_STM32F4XXX is not set
# CONFIG_STM32_STM32F401 is not set
# CONFIG_STM32_STM32F411 is not set
# CONFIG_STM32_STM32F405 is not set

2
configs/nucleo-f303re/can/defconfig
View file

@ -318,7 +318,7 @@ CONFIG_STM32_STM32F30XX=y
CONFIG_STM32_STM32F303=y
# CONFIG_STM32_STM32F33XX is not set
# CONFIG_STM32_STM32F37XX is not set
# CONFIG_STM32_STM32F40XX is not set
# CONFIG_STM32_STM32F4XXX is not set
# CONFIG_STM32_STM32F401 is not set
# CONFIG_STM32_STM32F411 is not set
# CONFIG_STM32_STM32F405 is not set

2
configs/nucleo-f303re/hello/defconfig
View file

@ -314,7 +314,7 @@ CONFIG_STM32_STM32F30XX=y
CONFIG_STM32_STM32F303=y
# CONFIG_STM32_STM32F33XX is not set
# CONFIG_STM32_STM32F37XX is not set
# CONFIG_STM32_STM32F40XX is not set
# CONFIG_STM32_STM32F4XXX is not set
# CONFIG_STM32_STM32F401 is not set
# CONFIG_STM32_STM32F411 is not set
# CONFIG_STM32_STM32F405 is not set

2
configs/nucleo-f303re/nxlines/defconfig
View file

@ -315,7 +315,7 @@ CONFIG_STM32_STM32F30XX=y
CONFIG_STM32_STM32F303=y
# CONFIG_STM32_STM32F33XX is not set
# CONFIG_STM32_STM32F37XX is not set
# CONFIG_STM32_STM32F40XX is not set
# CONFIG_STM32_STM32F4XXX is not set
# CONFIG_STM32_STM32F401 is not set
# CONFIG_STM32_STM32F411 is not set
# CONFIG_STM32_STM32F405 is not set

2
configs/nucleo-f303re/pwm/defconfig
View file

@ -313,7 +313,7 @@ CONFIG_STM32_STM32F30XX=y
CONFIG_STM32_STM32F303=y
# CONFIG_STM32_STM32F33XX is not set
# CONFIG_STM32_STM32F37XX is not set
# CONFIG_STM32_STM32F40XX is not set
# CONFIG_STM32_STM32F4XXX is not set
# CONFIG_STM32_STM32F401 is not set
# CONFIG_STM32_STM32F411 is not set
# CONFIG_STM32_STM32F405 is not set

2
configs/nucleo-f303re/serialrx/defconfig
View file

@ -316,7 +316,7 @@ CONFIG_STM32_STM32F30XX=y
CONFIG_STM32_STM32F303=y
# CONFIG_STM32_STM32F33XX is not set
# CONFIG_STM32_STM32F37XX is not set
# CONFIG_STM32_STM32F40XX is not set
# CONFIG_STM32_STM32F4XXX is not set
# CONFIG_STM32_STM32F401 is not set
# CONFIG_STM32_STM32F411 is not set
# CONFIG_STM32_STM32F405 is not set

2
configs/nucleo-f303re/uavcan/defconfig
View file

@ -319,7 +319,7 @@ CONFIG_STM32_STM32F30XX=y
CONFIG_STM32_STM32F303=y
# CONFIG_STM32_STM32F33XX is not set
# CONFIG_STM32_STM32F37XX is not set
# CONFIG_STM32_STM32F40XX is not set
# CONFIG_STM32_STM32F4XXX is not set
# CONFIG_STM32_STM32F401 is not set
# CONFIG_STM32_STM32F410 is not set
# CONFIG_STM32_STM32F411 is not set

2
configs/nucleo-f334r8/adc/defconfig
View file

@ -346,7 +346,7 @@ CONFIG_STM32_FLASH_CONFIG_DEFAULT=y
# CONFIG_STM32_STM32F303 is not set
CONFIG_STM32_STM32F33XX=y
# CONFIG_STM32_STM32F37XX is not set
# CONFIG_STM32_STM32F40XX is not set
# CONFIG_STM32_STM32F4XXX is not set
# CONFIG_STM32_STM32F401 is not set
# CONFIG_STM32_STM32F411 is not set
# CONFIG_STM32_STM32F405 is not set

2
configs/nucleo-f334r8/nsh/defconfig
View file

@ -344,7 +344,7 @@ CONFIG_STM32_FLASH_CONFIG_DEFAULT=y
# CONFIG_STM32_STM32F303 is not set
CONFIG_STM32_STM32F33XX=y
# CONFIG_STM32_STM32F37XX is not set
# CONFIG_STM32_STM32F40XX is not set
# CONFIG_STM32_STM32F4XXX is not set
# CONFIG_STM32_STM32F401 is not set
# CONFIG_STM32_STM32F411 is not set
# CONFIG_STM32_STM32F405 is not set

2
configs/nucleo-f4x1re/f401-nsh-clang/defconfig
View file

@ -320,7 +320,7 @@ CONFIG_STM32_FLASH_CONFIG_DEFAULT=y
# CONFIG_STM32_STM32F303 is not set
# CONFIG_STM32_STM32F33XX is not set
# CONFIG_STM32_STM32F37XX is not set
CONFIG_STM32_STM32F40XX=y
CONFIG_STM32_STM32F4XXX=y
CONFIG_STM32_STM32F401=y
# CONFIG_STM32_STM32F410 is not set
# CONFIG_STM32_STM32F411 is not set

2
configs/nucleo-f4x1re/f401-nsh/defconfig
View file

@ -320,7 +320,7 @@ CONFIG_STM32_FLASH_CONFIG_DEFAULT=y
# CONFIG_STM32_STM32F303 is not set
# CONFIG_STM32_STM32F33XX is not set
# CONFIG_STM32_STM32F37XX is not set
CONFIG_STM32_STM32F40XX=y
CONFIG_STM32_STM32F4XXX=y
CONFIG_STM32_STM32F401=y
# CONFIG_STM32_STM32F410 is not set
# CONFIG_STM32_STM32F411 is not set

2
configs/nucleo-f4x1re/f411-nsh/defconfig
View file

@ -320,7 +320,7 @@ CONFIG_STM32_FLASH_CONFIG_DEFAULT=y
# CONFIG_STM32_STM32F303 is not set
# CONFIG_STM32_STM32F33XX is not set
# CONFIG_STM32_STM32F37XX is not set
CONFIG_STM32_STM32F40XX=y
CONFIG_STM32_STM32F4XXX=y
# CONFIG_STM32_STM32F401 is not set
# CONFIG_STM32_STM32F410 is not set
CONFIG_STM32_STM32F411=y

2
configs/olimex-stm32-e407/discover/defconfig
View file

@ -321,7 +321,7 @@ CONFIG_STM32_FLASH_CONFIG_DEFAULT=y
# CONFIG_STM32_STM32F303 is not set
# CONFIG_STM32_STM32F33XX is not set
# CONFIG_STM32_STM32F37XX is not set
CONFIG_STM32_STM32F40XX=y
CONFIG_STM32_STM32F4XXX=y
# CONFIG_STM32_STM32F401 is not set
# CONFIG_STM32_STM32F410 is not set
# CONFIG_STM32_STM32F411 is not set

2
configs/olimex-stm32-e407/netnsh/defconfig
View file

@ -321,7 +321,7 @@ CONFIG_STM32_FLASH_CONFIG_DEFAULT=y
# CONFIG_STM32_STM32F303 is not set
# CONFIG_STM32_STM32F33XX is not set
# CONFIG_STM32_STM32F37XX is not set
CONFIG_STM32_STM32F40XX=y
CONFIG_STM32_STM32F4XXX=y
# CONFIG_STM32_STM32F401 is not set
# CONFIG_STM32_STM32F410 is not set
# CONFIG_STM32_STM32F411 is not set

2
configs/olimex-stm32-e407/nsh/defconfig
View file

@ -320,7 +320,7 @@ CONFIG_STM32_FLASH_CONFIG_DEFAULT=y
# CONFIG_STM32_STM32F303 is not set
# CONFIG_STM32_STM32F33XX is not set
# CONFIG_STM32_STM32F37XX is not set
CONFIG_STM32_STM32F40XX=y
CONFIG_STM32_STM32F4XXX=y
# CONFIG_STM32_STM32F401 is not set
# CONFIG_STM32_STM32F410 is not set
# CONFIG_STM32_STM32F411 is not set

2
configs/olimex-stm32-e407/telnetd/defconfig
View file

@ -321,7 +321,7 @@ CONFIG_STM32_FLASH_CONFIG_DEFAULT=y
# CONFIG_STM32_STM32F303 is not set
# CONFIG_STM32_STM32F33XX is not set
# CONFIG_STM32_STM32F37XX is not set
CONFIG_STM32_STM32F40XX=y
CONFIG_STM32_STM32F4XXX=y
# CONFIG_STM32_STM32F401 is not set
# CONFIG_STM32_STM32F410 is not set
# CONFIG_STM32_STM32F411 is not set

2
configs/olimex-stm32-e407/usbnsh/defconfig
View file

@ -320,7 +320,7 @@ CONFIG_STM32_FLASH_CONFIG_DEFAULT=y
# CONFIG_STM32_STM32F303 is not set
# CONFIG_STM32_STM32F33XX is not set
# CONFIG_STM32_STM32F37XX is not set
CONFIG_STM32_STM32F40XX=y
CONFIG_STM32_STM32F4XXX=y
# CONFIG_STM32_STM32F401 is not set
# CONFIG_STM32_STM32F410 is not set
# CONFIG_STM32_STM32F411 is not set

2
configs/olimex-stm32-e407/webserver/defconfig
View file

@ -321,7 +321,7 @@ CONFIG_STM32_FLASH_CONFIG_DEFAULT=y
# CONFIG_STM32_STM32F303 is not set
# CONFIG_STM32_STM32F33XX is not set
# CONFIG_STM32_STM32F37XX is not set
CONFIG_STM32_STM32F40XX=y
CONFIG_STM32_STM32F4XXX=y
# CONFIG_STM32_STM32F401 is not set
# CONFIG_STM32_STM32F410 is not set
# CONFIG_STM32_STM32F411 is not set

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