diff --git a/arch/arm/src/at32/at32_gpio.h b/arch/arm/src/at32/at32_gpio.h index 1b6a1b3851..3e877750a6 100644 --- a/arch/arm/src/at32/at32_gpio.h +++ b/arch/arm/src/at32/at32_gpio.h @@ -50,7 +50,7 @@ /* Bit-encoded input to at32_configgpio() */ -#if defined(CONFIG_AT32_AT32F43XX) +#if defined(CONFIG_AT32_AT32F43XX) /* Each port bit of the general-purpose I/O (GPIO) ports can be * individually configured by software in several modes: * diff --git a/arch/arm/src/at32/at32_tim.c b/arch/arm/src/at32/at32_tim.c index e2a6e2ea51..7573d8505c 100644 --- a/arch/arm/src/at32/at32_tim.c +++ b/arch/arm/src/at32/at32_tim.c @@ -263,7 +263,7 @@ defined(CONFIG_AT32_TIM9) || defined(CONFIG_AT32_TIM10) || \ defined(CONFIG_AT32_TIM11) || defined(CONFIG_AT32_TIM12) || \ defined(CONFIG_AT32_TIM13) || defined(CONFIG_AT32_TIM14) || \ - defined(CONFIG_AT32_TIM20) + defined(CONFIG_AT32_TIM20) /**************************************************************************** * Private Types diff --git a/arch/arm/src/at32/at32_uid.c b/arch/arm/src/at32/at32_uid.c index 5aaa31c407..25f8acf8f7 100644 --- a/arch/arm/src/at32/at32_uid.c +++ b/arch/arm/src/at32/at32_uid.c @@ -29,7 +29,7 @@ #include "hardware/at32_memorymap.h" #include "at32_uid.h" -#ifdef AT32_SYSMEM_UID +#ifdef AT32_SYSMEM_UID /**************************************************************************** * Public Functions diff --git a/arch/arm/src/at32/hardware/at32_adc_v1.h b/arch/arm/src/at32/hardware/at32_adc_v1.h index 03b27df0fa..713a092962 100644 --- a/arch/arm/src/at32/hardware/at32_adc_v1.h +++ b/arch/arm/src/at32/hardware/at32_adc_v1.h @@ -612,7 +612,7 @@ /* Calibration value register */ -#define ADC_CALVAL_SHIFT (0) +#define ADC_CALVAL_SHIFT (0) #define ADC_CALVAL_MASK (0x7f << ADC_CALVAL_SHIFT) # define ADC_CALVAL(n) (n << ADC_CALVAL_SHIFT) diff --git a/arch/arm/src/at32/hardware/at32_can.h b/arch/arm/src/at32/hardware/at32_can.h index bc727e0232..34bf9dfc26 100644 --- a/arch/arm/src/at32/hardware/at32_can.h +++ b/arch/arm/src/at32/hardware/at32_can.h @@ -307,7 +307,7 @@ #define CAN_ESTS_BOF (1 << 0) /* Bus-off flag */ #define CAN_ESTS_ETR_SHIFT (4) /* Error type record */ -#define CAN_ESTS_ETR_MASK (7 << CAN_ESTS_ETR_SHIFT) +#define CAN_ESTS_ETR_MASK (7 << CAN_ESTS_ETR_SHIFT) #define CAN_ESTS_ETR_NONE (0 << CAN_ESTS_ETR_SHIFT) /* No error */ #define CAN_ESTS_ETR_STUFF (1 << CAN_ESTS_ETR_SHIFT) /* Stuff error */ #define CAN_ESTS_ETR_FORM (2 << CAN_ESTS_ETR_SHIFT) /* Form error */ @@ -318,7 +318,7 @@ #define CAN_ESTS_ETR_SOFT (7 << CAN_ESTS_ETR_SHIFT) /* Set by soft */ #define CAN_ESTS_TEC_SHIFT (16) /* Transmit error counter */ -#define CAN_ESTS_TEC_MASK (0xff << CAN_ESTS_TEC_SHIFT) +#define CAN_ESTS_TEC_MASK (0xff << CAN_ESTS_TEC_SHIFT) #define CAN_ESTS_REC_SHIFT (24) /* Receive error counter */ #define CAN_ESTS_REC_MASK (0xff << CAN_ESTS_REC_SHIFT) diff --git a/arch/arm/src/at32/hardware/at32f43xxx_rcc.h b/arch/arm/src/at32/hardware/at32f43xxx_rcc.h index 90bf1e391a..46de4253e4 100644 --- a/arch/arm/src/at32/hardware/at32f43xxx_rcc.h +++ b/arch/arm/src/at32/hardware/at32f43xxx_rcc.h @@ -97,11 +97,11 @@ /* PLL configuration register */ #define CRM_PLL_CFG_PLL_MS_SHIFT (0) /* PLL pre-division, range: 1~15 */ -#define CRM_PLL_CFG_PLL_MS_MASK (15 << CRM_PLL_CFG_PLL_MS_SHIFT) +#define CRM_PLL_CFG_PLL_MS_MASK (15 << CRM_PLL_CFG_PLL_MS_SHIFT) # define CRM_PLL_CFG_PLL_MS(n) ((n) << CRM_PLL_CFG_PLL_MS_SHIFT) /* n = 1..15 */ #define CRM_PLL_CFG_PLL_NS_SHIFT (6) /* PLL Multiplication Factor,range: 31~500 */ -#define CRM_PLL_CFG_PLL_NS_MASK (0x1FF << CRM_PLL_CFG_PLL_NS_SHIFT) +#define CRM_PLL_CFG_PLL_NS_MASK (0x1FF << CRM_PLL_CFG_PLL_NS_SHIFT) # define CRM_PLL_CFG_PLL_NS(n) ((n) << CRM_PLL_CFG_PLL_NS_SHIFT) /* n = 31..500 */ #define CRM_PLL_CFG_PLL_FR_SHIFT (16) /* PLL post-division */ @@ -510,7 +510,7 @@ #define CRM_MISC1_HICK_TO_SCLK (1 << 14) /* HICK as system clock frequency select */ #define CRM_MISC1_CLKOUT2_SEL2_SHIFT (16) /* Clock output2 sel2 */ -#define CRM_MISC1_CLKOUT2_SEL2_MASK (15 << CRM_MISC1_CLKOUT2_SEL2_SHIFT) +#define CRM_MISC1_CLKOUT2_SEL2_MASK (15 << CRM_MISC1_CLKOUT2_SEL2_SHIFT) # define CRM_MISC1_CLKOUT2_SEL2_USB (0 << CRM_MISC1_CLKOUT2_SEL2_SHIFT) /* Select USB output */ # define CRM_MISC1_CLKOUT2_SEL2_ADC (1 << CRM_MISC1_CLKOUT2_SEL2_SHIFT) /* Select ADC output */ # define CRM_MISC1_CLKOUT2_SEL2_HICK (2 << CRM_MISC1_CLKOUT2_SEL2_SHIFT) /* Select HICK output */ diff --git a/arch/arm/src/at32/hardware/at32f43xxx_syscfg.h b/arch/arm/src/at32/hardware/at32f43xxx_syscfg.h index 65710ea3bc..580be58529 100644 --- a/arch/arm/src/at32/hardware/at32f43xxx_syscfg.h +++ b/arch/arm/src/at32/hardware/at32f43xxx_syscfg.h @@ -71,13 +71,13 @@ #define SCFG_CFG1_IR_POL (1 << 5) /* Infrared output polarity selection */ #define SCFG_CFG1_IR_SRC_SEL_SHIFT (6) /* Infrared modulation envelope signal source selection */ -#define SCFG_CFG1_IR_SRC_SEL_MASK (3 << SCFG_CFG1_IR_SRC_SEL_SHIFT) +#define SCFG_CFG1_IR_SRC_SEL_MASK (3 << SCFG_CFG1_IR_SRC_SEL_SHIFT) # define SCFG_CFG1_IR_SRC_SEL_TMR10 (0 << SCFG_CFG1_IR_SRC_SEL_SHIFT) /* Source use TRM10 */ # define SCFG_CFG1_IR_SRC_SEL_USART1 (1 << SCFG_CFG1_IR_SRC_SEL_SHIFT) /* Source use USART1 */ # define SCFG_CFG1_IR_SRC_SEL_USART2 (2 << SCFG_CFG1_IR_SRC_SEL_SHIFT) /* Source use USART2 */ #define SCFG_CFG1_SWAP_XMC_SHIFT (6) /* Infrared modulation envelope signal source selection */ -#define SCFG_CFG1_SWAP_XMC_MASK (3 << SCFG_CFG1_SWAP_XMC_SHIFT) +#define SCFG_CFG1_SWAP_XMC_MASK (3 << SCFG_CFG1_SWAP_XMC_SHIFT) # define SCFG_CFG1_SWAP_XMC_NONE (0 << SCFG_CFG1_SWAP_XMC_SHIFT) /* No swap */ # define SCFG_CFG1_SWAP_XMC_SDRAM1 (1 << SCFG_CFG1_SWAP_XMC_SHIFT) /* SDRAM swap1 */ # define SCFG_CFG1_SWAP_XMC_QSPI2 (2 << SCFG_CFG1_SWAP_XMC_SHIFT) /* QSPI2 swap */ diff --git a/arch/arm/src/at32/hardware/at32f43xxx_uart.h b/arch/arm/src/at32/hardware/at32f43xxx_uart.h index d4285e6920..234948540c 100644 --- a/arch/arm/src/at32/hardware/at32f43xxx_uart.h +++ b/arch/arm/src/at32/hardware/at32f43xxx_uart.h @@ -176,7 +176,7 @@ #define USART_CTRL1_TCDT_MASK (31 << USART_CTRL1_TCDT_SHIFT) #define USART_CTRL1_TCDT(X) ((X) << USART_CTRL1_TCDT_SHIFT) #define USART_CTRL1_TSDT_SHIFT (21) /* transmit start delay time */ -#define USART_CTRL1_TSDT_MASK (31 << USART_CTRL1_TSDT_SHIFT) +#define USART_CTRL1_TSDT_MASK (31 << USART_CTRL1_TSDT_SHIFT) #define USART_CTRL1_TSDT(X) ((X) << USART_CTRL1_TSDT_SHIFT) #define USART_CTRL1_DBN1 (1 << 28) /* Data bit num */ diff --git a/arch/arm/src/gd32f4/gd32f4xx_progmem.c b/arch/arm/src/gd32f4/gd32f4xx_progmem.c index 3f8b35c5db..e1ceed1767 100644 --- a/arch/arm/src/gd32f4/gd32f4xx_progmem.c +++ b/arch/arm/src/gd32f4/gd32f4xx_progmem.c @@ -74,12 +74,12 @@ # define FMC_PROGMEM_SECTOR_EADDR (0x0810FFFF) # elif defined(CONFIG_GD32F4_FLASH_CONFIG_K) -#if defined(CONFIG_GD32F4_GD32F450) +#if defined(CONFIG_GD32F4_GD32F450) # define FMC_PROGMEM_SECTOR_SIZES {_K(16), _K(16), _K(16), _K(16)} # define FMC_PROGMEM_SECTOR_NUM (4) # define FMC_PROGMEM_SECTOR_SADDR (0x08100000) # define FMC_PROGMEM_SECTOR_EADDR (0x0810FFFF) -#elif defined(CONFIG_GD32F4_GD32F470) +#elif defined(CONFIG_GD32F4_GD32F470) # define FMC_PROGMEM_SECTOR_SIZES {_K(256), _K(256), _K(256), _K(256)} # define FMC_PROGMEM_SECTOR_NUM (256) # define FMC_PROGMEM_SECTOR_SADDR (0x08200000) diff --git a/arch/arm/src/imxrt/hardware/imxrt_flexio.h b/arch/arm/src/imxrt/hardware/imxrt_flexio.h index eec91affbf..099bb94592 100644 --- a/arch/arm/src/imxrt/hardware/imxrt_flexio.h +++ b/arch/arm/src/imxrt/hardware/imxrt_flexio.h @@ -41,7 +41,7 @@ #define IMXRT_FLEXIO_SHIFTSTAT_OFFSET 0x0010 /* Shifter Status Register, offset: 0x10 */ #define IMXRT_FLEXIO_SHIFTERR_OFFSET 0x0014 /* Shifter Error Register, offset: 0x14 */ #define IMXRT_FLEXIO_TIMSTAT_OFFSET 0x0018 /* Timer Status Register, offset: 0x18 */ -#define IMXRT_FLEXIO_SHIFTSIEN_OFFSET 0x0020 /* Shift Enable, offset: 0x20 */ +#define IMXRT_FLEXIO_SHIFTSIEN_OFFSET 0x0020 /* Shift Enable, offset: 0x20 */ #define IMXRT_FLEXIO_SHIFTEIEN_OFFSET 0x0024 /* Shifter Error Interrupt Enable, offset: 0x24 */ #define IMXRT_FLEXIO_TIMIEN_OFFSET 0x0028 /* Timer Interrupt Enable Register, offset: 0x28 */ #define IMXRT_FLEXIO_SHIFTSDEN_OFFSET 0x0030 /* Shifter Status DMA Enable, offset: 0x30 */ diff --git a/arch/arm/src/imxrt/hardware/rt117x/imxrt117x_pmu.h b/arch/arm/src/imxrt/hardware/rt117x/imxrt117x_pmu.h index 51563f75f1..de394dd026 100644 --- a/arch/arm/src/imxrt/hardware/rt117x/imxrt117x_pmu.h +++ b/arch/arm/src/imxrt/hardware/rt117x/imxrt117x_pmu.h @@ -120,7 +120,7 @@ #define ANADIG_PMU_PMU_BIAS_CTRL_WB_CFG_1P8(n) (((n) << ANADIG_PMU_PMU_BIAS_CTRL_WB_CFG_1P8_SHIFT) & ANADIG_PMU_PMU_BIAS_CTRL_WB_CFG_1P8_MASK) #define ANADIG_PMU_PMU_BIAS_CTRL_WB_VDD_SEL_1P8 (1 << 14) /* Bit 14: wb_vdd_sel_1p8 */ -#define ANADIG_PMU_PMU_BIAS_CTRL_WB_CFG_1P8_WELL_SELECT (0x1) /* Bit 0: WELL Select */ +#define ANADIG_PMU_PMU_BIAS_CTRL_WB_CFG_1P8_WELL_SELECT (0x1) /* Bit 0: WELL Select */ #define ANADIG_PMU_PMU_BIAS_CTRL_WB_CFG_1P8_VOLTAGE_THRESHOLD_SHIFT (1) #define ANADIG_PMU_PMU_BIAS_CTRL_WB_CFG_1P8_VOLTAGE_THRESHOLD_MASK (0x1 << ANADIG_PMU_PMU_BIAS_CTRL_WB_CFG_1P8_VOLTAGE_THRESHOLD_SHIFT) @@ -130,7 +130,7 @@ #define ANADIG_PMU_PMU_BIAS_CTRL_WB_CFG_1P8_DRIVE_STRENGTH_MASK (0x7 << ANADIG_PMU_PMU_BIAS_CTRL_WB_CFG_1P8_DRIVE_STRENGTH_SHIFT) #define ANADIG_PMU_PMU_BIAS_CTRL_WB_CFG_1P8_DRIVE_STRENGTH(n) ((n) << ANADIG_PMU_PMU_BIAS_CTRL_WB_CFG_1P8_DRIVE_STRENGTH_SHIFT) & ANADIG_PMU_PMU_BIAS_CTRL_WB_CFG_1P8_DRIVE_STRENGTH_MASK) -#define ANADIG_PMU_PMU_BIAS_CTRL_WB_CFG_1P8_OSCILLATOR_FREQ_SHIFT (5) /* Bits 5:8: Oscillator settings */ +#define ANADIG_PMU_PMU_BIAS_CTRL_WB_CFG_1P8_OSCILLATOR_FREQ_SHIFT (5) /* Bits 5:8: Oscillator settings */ #define ANADIG_PMU_PMU_BIAS_CTRL_WB_CFG_1P8_OSCILLATOR_FREQ_MASK (0xf << ANADIG_PMU_PMU_BIAS_CTRL_WB_CFG_1P8_OSCILLATOR_FREQ_SHIFT) #define ANADIG_PMU_PMU_BIAS_CTRL_WB_CFG_1P8_OSCILLATOR_FREQ(n) ((n) << ANADIG_PMU_PMU_BIAS_CTRL_WB_CFG_1P8_OSCILLATOR_FREQ_SHIFT) & ANADIG_PMU_PMU_BIAS_CTRL_WB_CFG_1P8_OSCILLATOR_FREQ_MASK) diff --git a/arch/arm/src/stm32/hardware/stm32_flash.h b/arch/arm/src/stm32/hardware/stm32_flash.h index 44feb59756..2da3181508 100644 --- a/arch/arm/src/stm32/hardware/stm32_flash.h +++ b/arch/arm/src/stm32/hardware/stm32_flash.h @@ -203,7 +203,7 @@ # elif defined(CONFIG_STM32_FLASH_CONFIG_E) # define STM32_FLASH_SIZE 128 * 4096 # endif -# elif defined(CONFIG_STM32_STM32G49XX) +# elif defined(CONFIG_STM32_STM32G49XX) # elif defined(CONFIG_STM32_FLASH_CONFIG_C) # define STM32_FLASH_NPAGES 128 # define STM32_FLASH_PAGESIZE 2048 diff --git a/arch/arm/src/stm32/stm32_lowputc.c b/arch/arm/src/stm32/stm32_lowputc.c index 44f65ae662..ff9659c971 100644 --- a/arch/arm/src/stm32/stm32_lowputc.c +++ b/arch/arm/src/stm32/stm32_lowputc.c @@ -308,9 +308,9 @@ # define STM32_BRR_VALUE \ (((STM32_APBCLOCK & 0xf0000000) / STM32_CONSOLE_BAUD) << 4) + \ (((STM32_APBCLOCK & 0x0fffffff) << 4) / STM32_CONSOLE_BAUD) -# define STM32_PRESC_VALUE 0x7 +# define STM32_PRESC_VALUE 0x7 -# else +# else # if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) || \ defined(CONFIG_STM32_STM32F37XX) || defined(CONFIG_STM32_STM32G4XXX) @@ -668,7 +668,7 @@ void stm32_lowsetup(void) #if CONSOLE_LPUART > 0 && defined(CONFIG_STM32_STM32G4XXX) putreg32(STM32_PRESC_VALUE, STM32_CONSOLE_BASE + STM32_USART_PRESC_OFFSET); -#endif +#endif putreg32(STM32_BRR_VALUE, STM32_CONSOLE_BASE + STM32_USART_BRR_OFFSET); diff --git a/arch/arm/src/stm32h5/hardware/stm32_adc.h b/arch/arm/src/stm32h5/hardware/stm32_adc.h index 35dc2668c2..9c19701126 100644 --- a/arch/arm/src/stm32h5/hardware/stm32_adc.h +++ b/arch/arm/src/stm32h5/hardware/stm32_adc.h @@ -511,13 +511,13 @@ /* ADC analog watchdog 2 configuration register */ #define ADC_AWD2CR_CH_SHIFT (0) -#define ADC_AWD2CR_CH_MASK (0xfffff << ADC_AWD2CR_CH_SHIFT) +#define ADC_AWD2CR_CH_MASK (0xfffff << ADC_AWD2CR_CH_SHIFT) # define ADC_AWD2CR_CH(n) (1 << (n)) /* Channel n=0..19*/ /* ADC analog watchdog 3 configuration register */ #define ADC_AWD3CR_CH_SHIFT (0) -#define ADC_AWD3CR_CH_MASK (0xfffff << ADC_AWD3CR_CH_SHIFT) +#define ADC_AWD3CR_CH_MASK (0xfffff << ADC_AWD3CR_CH_SHIFT) # define ADC_AWD3CR_CH(n) (1 << (n)) /* Channel n=0..19*/ /* ADC differential mode selection register */ diff --git a/arch/arm/src/stm32h5/stm32_lowputc.c b/arch/arm/src/stm32h5/stm32_lowputc.c index 4ad64eb4c9..7de76e7300 100644 --- a/arch/arm/src/stm32h5/stm32_lowputc.c +++ b/arch/arm/src/stm32h5/stm32_lowputc.c @@ -49,7 +49,7 @@ # define STM32H5_CONSOLE_BASE STM32_LPUART1_BASE # define STM32H5_APBCLOCK STM32_PCLK1_FREQUENCY # define STM32H5_CONSOLE_APBREG STM32_RCC_APB3ENR -# define STM32H5_CONSOLE_APBEN RCC_APB3ENR_LPUART1EN +# define STM32H5_CONSOLE_APBEN RCC_APB3ENR_LPUART1EN # define STM32H5_CONSOLE_BAUD CONFIG_LPUART1_BAUD # define STM32H5_CONSOLE_BITS CONFIG_LPUART1_BITS # define STM32H5_CONSOLE_PARITY CONFIG_LPUART1_PARITY @@ -67,8 +67,8 @@ # elif defined(CONFIG_USART1_SERIAL_CONSOLE) # define STM32H5_CONSOLE_BASE STM32_USART1_BASE # define STM32H5_APBCLOCK STM32_PCLK2_FREQUENCY -# define STM32H5_CONSOLE_APBREG STM32_RCC_APB2ENR -# define STM32H5_CONSOLE_APBEN RCC_APB2ENR_USART1EN +# define STM32H5_CONSOLE_APBREG STM32_RCC_APB2ENR +# define STM32H5_CONSOLE_APBEN RCC_APB2ENR_USART1EN # define STM32H5_CONSOLE_BAUD CONFIG_USART1_BAUD # define STM32H5_CONSOLE_BITS CONFIG_USART1_BITS # define STM32H5_CONSOLE_PARITY CONFIG_USART1_PARITY @@ -372,9 +372,9 @@ # define STM32_BRR_VALUE \ (((STM32_APBCLOCK & 0xf0000000) / STM32_CONSOLE_BAUD) << 4) + \ (((STM32_APBCLOCK & 0x0fffffff) << 4) / STM32_CONSOLE_BAUD) -# define STM32_PRESC_VALUE 0x7 +# define STM32_PRESC_VALUE 0x7 -# else +# else /* Baud rate for standard USART (SPI mode included): * diff --git a/arch/arm/src/stm32u5/hardware/stm32u5xx_spi.h b/arch/arm/src/stm32u5/hardware/stm32u5xx_spi.h index 7b00c1bcc2..e7d98a97ae 100644 --- a/arch/arm/src/stm32u5/hardware/stm32u5xx_spi.h +++ b/arch/arm/src/stm32u5/hardware/stm32u5xx_spi.h @@ -32,7 +32,7 @@ #if defined(CONFIG_STM32U5_STM32U535XX) || defined(CONFIG_STM32U5_STM32U545XX) || \ defined(CONFIG_STM32U5_STM32U575XX) || defined(CONFIG_STM32U5_STM32U585XX) || \ defined(CONFIG_STM32U5_STM32U59XX) || defined(CONFIG_STM32U5_STM32U59AXX) || \ - defined(CONFIG_STM32U5_STM32U5A5XX) || defined(CONFIG_STM32U5_STM32U5A9XX) + defined(CONFIG_STM32U5_STM32U5A5XX) || defined(CONFIG_STM32U5_STM32U5A9XX) /**************************************************************************** * Pre-processor Definitions diff --git a/arch/arm/src/stm32u5/hardware/stm32u5xx_syscfg.h b/arch/arm/src/stm32u5/hardware/stm32u5xx_syscfg.h index f47743b2fa..56fc25f062 100644 --- a/arch/arm/src/stm32u5/hardware/stm32u5xx_syscfg.h +++ b/arch/arm/src/stm32u5/hardware/stm32u5xx_syscfg.h @@ -33,7 +33,7 @@ #if defined(CONFIG_STM32U5_STM32U535XX) || defined(CONFIG_STM32U5_STM32U545XX) || \ defined(CONFIG_STM32U5_STM32U575XX) || defined(CONFIG_STM32U5_STM32U585XX) || \ defined(CONFIG_STM32U5_STM32U59XX) || defined(CONFIG_STM32U5_STM32U59AXX) || \ - defined(CONFIG_STM32U5_STM32U5A5XX) || defined(CONFIG_STM32U5_STM32U5A9XX) + defined(CONFIG_STM32U5_STM32U5A5XX) || defined(CONFIG_STM32U5_STM32U5A9XX) /**************************************************************************** * Pre-processor Definitions diff --git a/arch/arm/src/xmc4/xmc4_lowputc.c b/arch/arm/src/xmc4/xmc4_lowputc.c index b2f701dd03..dd53a2b655 100644 --- a/arch/arm/src/xmc4/xmc4_lowputc.c +++ b/arch/arm/src/xmc4/xmc4_lowputc.c @@ -112,30 +112,30 @@ #define UART_OVERSAMPLING 16 -#if defined(CONFIG_XMC4_USIC0_CHAN0_ISUART) -#if CONFIG_XMC4_USIC0_CHAN0_TX_BUFFER_SIZE < 2 \ +#if defined(CONFIG_XMC4_USIC0_CHAN0_ISUART) +#if CONFIG_XMC4_USIC0_CHAN0_TX_BUFFER_SIZE < 2 \ || CONFIG_XMC4_USIC0_CHAN0_TX_BUFFER_SIZE > 64 \ || !IS_POWER_OF_2(CONFIG_XMC4_USIC0_CHAN0_TX_BUFFER_SIZE) # error Tx Buffer Size should be a power of 2 between 2 and 64 #endif -#if CONFIG_XMC4_USIC0_CHAN0_RX_BUFFER_SIZE < 2 \ - || CONFIG_XMC4_USIC0_CHAN0_RX_BUFFER_SIZE > 64 \ +#if CONFIG_XMC4_USIC0_CHAN0_RX_BUFFER_SIZE < 2 \ + || CONFIG_XMC4_USIC0_CHAN0_RX_BUFFER_SIZE > 64 \ || !IS_POWER_OF_2(CONFIG_XMC4_USIC0_CHAN0_RX_BUFFER_SIZE) # error Rx Buffer Size should be a power of 2 between 2 and 64 #endif #endif -#if defined(CONFIG_XMC4_USIC0_CHAN1_ISUART) -#if CONFIG_XMC4_USIC0_CHAN1_TX_BUFFER_SIZE < 2 \ +#if defined(CONFIG_XMC4_USIC0_CHAN1_ISUART) +#if CONFIG_XMC4_USIC0_CHAN1_TX_BUFFER_SIZE < 2 \ || CONFIG_XMC4_USIC0_CHAN1_TX_BUFFER_SIZE > 64 \ || !IS_POWER_OF_2(CONFIG_XMC4_USIC0_CHAN1_TX_BUFFER_SIZE) # error Tx Buffer Size should be a power of 2 between 2 and 64 #endif -#if CONFIG_XMC4_USIC0_CHAN1_RX_BUFFER_SIZE < 2 \ - || CONFIG_XMC4_USIC0_CHAN1_RX_BUFFER_SIZE > 64 \ +#if CONFIG_XMC4_USIC0_CHAN1_RX_BUFFER_SIZE < 2 \ + || CONFIG_XMC4_USIC0_CHAN1_RX_BUFFER_SIZE > 64 \ || !IS_POWER_OF_2(CONFIG_XMC4_USIC0_CHAN1_RX_BUFFER_SIZE) # error Rx Buffer Size should be a power of 2 between 2 and 64 #endif @@ -144,43 +144,43 @@ #if defined(CONFIG_XMC4_USIC0_CHAN0_ISUART) && defined(CONFIG_XMC4_USIC0_CHAN1_ISUART) #if CONFIG_XMC4_USIC0_CHAN0_TX_BUFFER_SIZE + CONFIG_XMC4_USIC0_CHAN0_RX_BUFFER_SIZE + \ - CONFIG_XMC4_USIC0_CHAN1_TX_BUFFER_SIZE + CONFIG_XMC4_USIC0_CHAN1_RX_BUFFER_SIZE > 64 + CONFIG_XMC4_USIC0_CHAN1_TX_BUFFER_SIZE + CONFIG_XMC4_USIC0_CHAN1_RX_BUFFER_SIZE > 64 # error The sum of Rx and Tx Buffers sizes should be inferior to 64 #endif #endif -#if defined(CONFIG_XMC4_USIC1_CHAN0_ISUART) -#if CONFIG_XMC4_USIC1_CHAN0_TX_BUFFER_SIZE < 2 \ +#if defined(CONFIG_XMC4_USIC1_CHAN0_ISUART) +#if CONFIG_XMC4_USIC1_CHAN0_TX_BUFFER_SIZE < 2 \ || CONFIG_XMC4_USIC1_CHAN0_TX_BUFFER_SIZE > 64 \ || !IS_POWER_OF_2(CONFIG_XMC4_USIC1_CHAN0_TX_BUFFER_SIZE) # error Tx Buffer Size should be a power of 2 between 2 and 64 #endif -#if CONFIG_XMC4_USIC1_CHAN0_RX_BUFFER_SIZE < 2 \ - || CONFIG_XMC4_USIC1_CHAN0_RX_BUFFER_SIZE > 64 \ +#if CONFIG_XMC4_USIC1_CHAN0_RX_BUFFER_SIZE < 2 \ + || CONFIG_XMC4_USIC1_CHAN0_RX_BUFFER_SIZE > 64 \ || !IS_POWER_OF_2(CONFIG_XMC4_USIC1_CHAN0_RX_BUFFER_SIZE) # error Rx Buffer Size should be a power of 2 between 2 and 64 #endif -#if CONFIG_XMC4_USIC1_CHAN0_TX_BUFFER_SIZE + CONFIG_XMC4_USIC1_CHAN0_RX_BUFFER_SIZE > 64 +#if CONFIG_XMC4_USIC1_CHAN0_TX_BUFFER_SIZE + CONFIG_XMC4_USIC1_CHAN0_RX_BUFFER_SIZE > 64 # error The sum of Rx and Tx Buffer sizes should be inferior to 64 #endif #endif -#if defined(CONFIG_XMC4_USIC1_CHAN1_ISUART) -#if CONFIG_XMC4_USIC1_CHAN1_TX_BUFFER_SIZE < 2 \ +#if defined(CONFIG_XMC4_USIC1_CHAN1_ISUART) +#if CONFIG_XMC4_USIC1_CHAN1_TX_BUFFER_SIZE < 2 \ || CONFIG_XMC4_USIC1_CHAN1_TX_BUFFER_SIZE > 64 \ || !IS_POWER_OF_2(CONFIG_XMC4_USIC1_CHAN1_TX_BUFFER_SIZE) # error Tx Buffer Size should be a power of 2 between 2 and 64 #endif -#if CONFIG_XMC4_USIC1_CHAN1_RX_BUFFER_SIZE < 2 \ - || CONFIG_XMC4_USIC1_CHAN1_RX_BUFFER_SIZE > 64 \ +#if CONFIG_XMC4_USIC1_CHAN1_RX_BUFFER_SIZE < 2 \ + || CONFIG_XMC4_USIC1_CHAN1_RX_BUFFER_SIZE > 64 \ || !IS_POWER_OF_2(CONFIG_XMC4_USIC1_CHAN1_RX_BUFFER_SIZE) # error Rx Buffer Size should be a power of 2 between 2 and 64 #endif -#if CONFIG_XMC4_USIC1_CHAN1_TX_BUFFER_SIZE + CONFIG_XMC4_USIC1_CHAN1_RX_BUFFER_SIZE > 64 +#if CONFIG_XMC4_USIC1_CHAN1_TX_BUFFER_SIZE + CONFIG_XMC4_USIC1_CHAN1_RX_BUFFER_SIZE > 64 # error The sum of Rx and Tx Buffer sizes should be inferior to 64 #endif #endif @@ -192,38 +192,38 @@ #endif #endif -#if defined(CONFIG_XMC4_USIC2_CHAN0_ISUART) -#if CONFIG_XMC4_USIC2_CHAN0_TX_BUFFER_SIZE < 2 \ +#if defined(CONFIG_XMC4_USIC2_CHAN0_ISUART) +#if CONFIG_XMC4_USIC2_CHAN0_TX_BUFFER_SIZE < 2 \ || CONFIG_XMC4_USIC2_CHAN0_TX_BUFFER_SIZE > 64 \ || !IS_POWER_OF_2(CONFIG_XMC4_USIC2_CHAN0_TX_BUFFER_SIZE) # error Tx Buffer Size should be a power of 2 between 2 and 64 #endif -#if CONFIG_XMC4_USIC2_CHAN0_RX_BUFFER_SIZE < 2 \ - || CONFIG_XMC4_USIC2_CHAN0_RX_BUFFER_SIZE > 64 \ +#if CONFIG_XMC4_USIC2_CHAN0_RX_BUFFER_SIZE < 2 \ + || CONFIG_XMC4_USIC2_CHAN0_RX_BUFFER_SIZE > 64 \ || !IS_POWER_OF_2(CONFIG_XMC4_USIC2_CHAN0_RX_BUFFER_SIZE) # error Rx Buffer Size should be a power of 2 between 2 and 64 #endif -#if CONFIG_XMC4_USIC2_CHAN0_TX_BUFFER_SIZE + CONFIG_XMC4_USIC2_CHAN0_RX_BUFFER_SIZE > 64 +#if CONFIG_XMC4_USIC2_CHAN0_TX_BUFFER_SIZE + CONFIG_XMC4_USIC2_CHAN0_RX_BUFFER_SIZE > 64 # error The sum of Rx and Tx Buffer sizes should be inferior to 64 #endif #endif -#if defined(CONFIG_XMC4_USIC2_CHAN1_ISUART) -#if CONFIG_XMC4_USIC2_CHAN1_TX_BUFFER_SIZE < 2 \ +#if defined(CONFIG_XMC4_USIC2_CHAN1_ISUART) +#if CONFIG_XMC4_USIC2_CHAN1_TX_BUFFER_SIZE < 2 \ || CONFIG_XMC4_USIC2_CHAN1_TX_BUFFER_SIZE > 64 \ || !IS_POWER_OF_2(CONFIG_XMC4_USIC2_CHAN1_TX_BUFFER_SIZE) # error Tx Buffer Size should be a power of 2 between 2 and 64 #endif -#if CONFIG_XMC4_USIC2_CHAN1_RX_BUFFER_SIZE < 2 \ - || CONFIG_XMC4_USIC2_CHAN1_RX_BUFFER_SIZE > 64 \ +#if CONFIG_XMC4_USIC2_CHAN1_RX_BUFFER_SIZE < 2 \ + || CONFIG_XMC4_USIC2_CHAN1_RX_BUFFER_SIZE > 64 \ || !IS_POWER_OF_2(CONFIG_XMC4_USIC2_CHAN1_RX_BUFFER_SIZE) # error Rx Buffer Size should be a power of 2 between 2 and 64 #endif -#if CONFIG_XMC4_USIC2_CHAN1_TX_BUFFER_SIZE + CONFIG_XMC4_USIC2_CHAN1_RX_BUFFER_SIZE > 64 +#if CONFIG_XMC4_USIC2_CHAN1_TX_BUFFER_SIZE + CONFIG_XMC4_USIC2_CHAN1_RX_BUFFER_SIZE > 64 # error The sum of Rx and Tx Buffer sizes should be inferior to 64 #endif #endif diff --git a/arch/arm64/include/rk3399/chip.h b/arch/arm64/include/rk3399/chip.h index 26530b6f38..b04d2b8ea6 100644 --- a/arch/arm64/include/rk3399/chip.h +++ b/arch/arm64/include/rk3399/chip.h @@ -42,7 +42,7 @@ /* Rockchip A64 Generic Interrupt Controller v2: Distributor and Redist */ #define CONFIG_GICD_BASE 0xfee00000 -#define CONFIG_GICR_BASE 0xfef00000 +#define CONFIG_GICR_BASE 0xfef00000 #define CONFIG_GICR_OFFSET 0x20000 /* Rockchip RK3399 Memory Map: RAM and Device I/O */ diff --git a/arch/arm64/include/zynq-mpsoc/chip.h b/arch/arm64/include/zynq-mpsoc/chip.h index 7305d7f909..f8dedb16aa 100644 --- a/arch/arm64/include/zynq-mpsoc/chip.h +++ b/arch/arm64/include/zynq-mpsoc/chip.h @@ -42,7 +42,7 @@ /* XilinX ZYNQ_MPSOC Generic Interrupt Controller v2: Distributor & Redist */ #define CONFIG_GICD_BASE 0xf9010000 -#define CONFIG_GICR_BASE 0xf9020000 +#define CONFIG_GICR_BASE 0xf9020000 #define CONFIG_GICR_OFFSET 0x20000 /* XilinX ZYNQ_MPSOC Memory Map: RAM and Device I/O */ diff --git a/arch/arm64/src/imx9/hardware/imx9_enet.h b/arch/arm64/src/imx9/hardware/imx9_enet.h index 10613cc7ae..4f7050527a 100644 --- a/arch/arm64/src/imx9/hardware/imx9_enet.h +++ b/arch/arm64/src/imx9/hardware/imx9_enet.h @@ -160,7 +160,7 @@ #define ENET_RXB2 (1 << 4) /* Receive buffer interrupt, class 2 */ #define ENET_RXF2 (1 << 5) /* Receive frame interrupt, class 2 */ #define ENET_TXB2 (1 << 6) /* Transmit buffer interrupt, class 2 */ -#define ENET_TXF2 (1 << 7) /* Transmit frame interrupt, class 2 */ +#define ENET_TXF2 (1 << 7) /* Transmit frame interrupt, class 2 */ #define ENET_RXFLUSH_0 (1 << 12) /* RX DMA Ring 0 flush indication */ #define ENET_RXFLUSH_1 (1 << 13) /* RX DMA Ring 1 flush indication */ #define ENET_RXFLUSH_2 (1 << 14) /* RX DMA Ring 2 flush indication */ diff --git a/arch/risc-v/src/hpm6000/hardware/hpm6300/hpm6300_sysctl.h b/arch/risc-v/src/hpm6000/hardware/hpm6300/hpm6300_sysctl.h index 3b9c46d6cd..7003d4f35e 100644 --- a/arch/risc-v/src/hpm6000/hardware/hpm6300/hpm6300_sysctl.h +++ b/arch/risc-v/src/hpm6000/hardware/hpm6300/hpm6300_sysctl.h @@ -286,7 +286,7 @@ #define SYSCTL_RETENTION_LINK_MASK (0xffU << SYSCTL_RETENTION_LINK_SHIFT) # define SYSCTL_RETENTION_LINK_SOC_RAM (0 << SYSCTL_RETENTION_LINK_SHIFT) # define SYSCTL_RETENTION_LINK_PERIPH_REG (1 << SYSCTL_RETENTION_LINK_SHIFT) -# define SYSCTL_RETENTION_LINK_CPU0_RAM (2 << SYSCTL_RETENTION_LINK_SHIFT) +# define SYSCTL_RETENTION_LINK_CPU0_RAM (2 << SYSCTL_RETENTION_LINK_SHIFT) # define SYSCTL_RETENTION_LINK_CPU0_REG (3 << SYSCTL_RETENTION_LINK_SHIFT) # define SYSCTL_RETENTION_LINK_XTAL (4 << SYSCTL_RETENTION_LINK_SHIFT) # define SYSCTL_RETENTION_LINK_PLL0 (5 << SYSCTL_RETENTION_LINK_SHIFT) diff --git a/boards/arm/at32/at32f437-mini/src/at32_at24.c b/boards/arm/at32/at32f437-mini/src/at32_at24.c index ada3ce12d7..fab6b34d2d 100644 --- a/boards/arm/at32/at32f437-mini/src/at32_at24.c +++ b/boards/arm/at32/at32f437-mini/src/at32_at24.c @@ -107,7 +107,7 @@ int at32_at24_automount(int minor) ferr("ERROR: Failed to mount the NXFFS volume: %d\n", ret); return ret; } -#else +#else /* And use the FTL layer to wrap the MTD driver as a block driver */ finfo("Initialize the FTL layer to create /dev/mtdblock%d\n", diff --git a/boards/arm/stm32/nucleo-f429zi/src/stm32_appinitialize.c b/boards/arm/stm32/nucleo-f429zi/src/stm32_appinitialize.c index aa33e7355a..d697b6083b 100644 --- a/boards/arm/stm32/nucleo-f429zi/src/stm32_appinitialize.c +++ b/boards/arm/stm32/nucleo-f429zi/src/stm32_appinitialize.c @@ -43,7 +43,7 @@ #if defined(CONFIG_I2C) && defined(CONFIG_SYSTEM_I2CTOOL) # include "stm32_i2c.h" -#endif +#endif /**************************************************************************** * Private Functions diff --git a/boards/arm/stm32h5/nucleo-h563zi/include/board.h b/boards/arm/stm32h5/nucleo-h563zi/include/board.h index e9e1805065..e077dec0eb 100644 --- a/boards/arm/stm32h5/nucleo-h563zi/include/board.h +++ b/boards/arm/stm32h5/nucleo-h563zi/include/board.h @@ -152,7 +152,7 @@ #if defined(CONFIG_STM32H5_USBFS) || defined(CONFIG_STM32H5_RNG) # define STM32H5_USE_CLK48 1 -# define STM32H5_CLKUSB_SEL RCC_CCIPR4_USBSEL_HSI48KERCK +# define STM32H5_CLKUSB_SEL RCC_CCIPR4_USBSEL_HSI48KERCK # define STM32H5_HSI48_SYNCSRC SYNCSRC_NONE #endif diff --git a/boards/xtensa/esp32s3/esp32s3-devkit/include/board.h b/boards/xtensa/esp32s3/esp32s3-devkit/include/board.h index b00dc167fa..f28c134287 100644 --- a/boards/xtensa/esp32s3/esp32s3-devkit/include/board.h +++ b/boards/xtensa/esp32s3/esp32s3-devkit/include/board.h @@ -55,7 +55,7 @@ #ifdef CONFIG_NET_LAN9250 -# define LAN9250_SPI 2 +# define LAN9250_SPI 2 /* LAN9250 IRQ pin */ diff --git a/fs/mnemofs/mnemofs_ctz.c b/fs/mnemofs/mnemofs_ctz.c index 2c6f7bdceb..ec16bd748f 100644 --- a/fs/mnemofs/mnemofs_ctz.c +++ b/fs/mnemofs/mnemofs_ctz.c @@ -99,7 +99,7 @@ #include #include #include -#include +#include #include #include diff --git a/include/nuttx/lin.h b/include/nuttx/lin.h index ffe4a5df43..51bd3be173 100644 --- a/include/nuttx/lin.h +++ b/include/nuttx/lin.h @@ -113,7 +113,7 @@ #define LIN_ERR_TX_UNSPEC 0x00 /* Unspecified error */ #define LIN_ERR_TX_BREAK_TMO (1 << 0) /* Bit 0: Master send break field, but detect break event timeout */ -#define LIN_ERR_TX_SYNC_TMO (1 << 1) /* Bit 1: Master send sync timeout (receive back timeout) */ +#define LIN_ERR_TX_SYNC_TMO (1 << 1) /* Bit 1: Master send sync timeout (receive back timeout) */ #define LIN_ERR_TX_PID_TMO (1 << 2) /* Bit 2: Master send pid timeout (receive back timeout) */ #define LIN_ERR_TX_DATA_TMO (1 << 3) /* Bit 3: Master/slave send data timeout (receive back timeout) */ #define LIN_ERR_TX_CHECKSUM_TMO (1 << 4) /* Bit 4: Master/slave send checksum timeout(receive back timeout) */ diff --git a/include/nuttx/timers/pwm.h b/include/nuttx/timers/pwm.h index 76cbc3a659..7a124c655c 100644 --- a/include/nuttx/timers/pwm.h +++ b/include/nuttx/timers/pwm.h @@ -136,7 +136,7 @@ * the disabled channel's output state. */ -#define PWM_DCPOL_NDEF 0 /* Not defined, the default output state is arch dependant */ +#define PWM_DCPOL_NDEF 0 /* Not defined, the default output state is arch dependant */ #define PWM_DCPOL_LOW 1 /* Logical zero */ #define PWM_DCPOL_HIGH 2 /* Logical one */