mirror of
https://github.com/apache/nuttx.git
synced 2025-01-12 22:08:35 +08:00
arm/stm32h753bi: Add support to lvgl
Signed-off-by: Jorge Guzman <jorge.gzm@gmail.com>
This commit is contained in:
Jorge Guzman
parent
bbd6931d61
commit
155fbd7ccf
9 changed files with 253 additions and 94 deletions
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@ -813,3 +813,57 @@ Configures the board to use the SPI4 and enables RFID driver with MFRC522::
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MOSI PE6
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CS PE4
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======== =====
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lvgl
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----
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Configures the board to use display of 7 inch with lvgl example.
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To verify if the display is functioning correctly, use the **fb** command. You should see the display change colors.::
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nsh> fb
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VideoInfo:
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fmt: 11
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xres: 1024
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yres: 600
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nplanes: 1
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noverlays: 1
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OverlayInfo (overlay 0):
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fbmem: 0xc0000000
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fblen: 1228800
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stride: 2048
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overlay: 0
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bpp: 16
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blank: 0
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chromakey: 0x00000000
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color: 0x00000000
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transp: 0xff
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mode: 0
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area: (0,0) => (1024,600)
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accl: 1
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PlaneInfo (plane 0):
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fbmem: 0xc0000000
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fblen: 1228800
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stride: 2048
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display: 0
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bpp: 16
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Mapped FB: 0xc0000000
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0: ( 0, 0) (1024,600)
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1: ( 93, 54) (838,492)
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2: (186,108) (652,384)
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3: (279,162) (466,276)
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4: (372,216) (280,168)
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5: (465,270) ( 94, 60)
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Test finished
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Once the **fd** command work, run the lvgl exemple. ::
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nsh> lvgldemo
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**WARNING:** This example at the moment is not working correctly yet and have a bug fix to be done.
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In the lvgl file **./apps/graphics/lvgl/lvgl/src/drivers/nuttx/lv_nuttx_fbdev.c**
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search the function **lv_nuttx_fbdev_set_file** and modify line 156 as follows:
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dsc->mem_off_screen = malloc(data_size);
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to
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dsc->mem_off_screen = (void*)0xC00000000;
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@ -2623,7 +2623,7 @@ static int stm32_setchromakey(struct fb_vtable_s *vtable,
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struct stm32_ltdcdev_s *priv = (struct stm32_ltdcdev_s *)vtable;
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DEBUGASSERT(vtable != NULL && priv == &g_vtable && oinfo != NULL);
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lcdinfo("vtable=%p, overlay=%d, chromakey=%08x\n", vtable,
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lcdinfo("vtable=%p, overlay=%d, chromakey=%08" PRIx32 "\n", vtable,
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oinfo->overlay, oinfo->chromakey);
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if (oinfo->overlay < LTDC_NLAYERS)
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@ -2689,7 +2689,8 @@ static int stm32_setcolor(struct fb_vtable_s *vtable,
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const struct fb_overlayinfo_s *oinfo)
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{
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DEBUGASSERT(vtable != NULL && vtable == &g_vtable.vtable && oinfo != NULL);
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lcdinfo("vtable=%p, overlay=%d, color=%08x\n", vtable, oinfo->color);
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lcdinfo("vtable=%p, overlay=%d, color=%08" PRIx32 "\n",
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vtable, oinfo->overlay, oinfo->color);
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if (oinfo->overlay < LTDC_NOVERLAYS)
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{
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@ -2737,7 +2738,8 @@ static int stm32_setblank(struct fb_vtable_s *vtable,
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struct stm32_ltdcdev_s *priv = (struct stm32_ltdcdev_s *)vtable;
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DEBUGASSERT(vtable != NULL && priv == &g_vtable && oinfo != NULL);
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lcdinfo("vtable=%p, overlay=%d, blank=%02x\n", vtable, oinfo->blank);
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lcdinfo("vtable=%p, overlay=%d, blank=%02x\n",
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vtable, oinfo->overlay, oinfo->blank);
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if (oinfo->overlay < LTDC_NLAYERS)
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{
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@ -2626,7 +2626,7 @@ static int stm32_setchromakey(struct fb_vtable_s *vtable,
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struct stm32_ltdcdev_s *priv = (struct stm32_ltdcdev_s *)vtable;
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DEBUGASSERT(vtable != NULL && priv == &g_vtable && oinfo != NULL);
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lcdinfo("vtable=%p, overlay=%d, chromakey=%08x\n", vtable,
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lcdinfo("vtable=%p, overlay=%d, chromakey=%08" PRIx32 "\n", vtable,
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oinfo->overlay, oinfo->chromakey);
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if (oinfo->overlay < LTDC_NLAYERS)
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@ -2692,7 +2692,8 @@ static int stm32_setcolor(struct fb_vtable_s *vtable,
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const struct fb_overlayinfo_s *oinfo)
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{
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DEBUGASSERT(vtable != NULL && vtable == &g_vtable.vtable && oinfo != NULL);
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lcdinfo("vtable=%p, overlay=%d, color=%08x\n", vtable, oinfo->color);
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lcdinfo("vtable=%p, overlay=%d, color=%08" PRIx32 "\n",
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vtable, oinfo->overlay, oinfo->color);
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if (oinfo->overlay < LTDC_NOVERLAYS)
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{
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@ -2739,7 +2740,8 @@ static int stm32_setblank(struct fb_vtable_s *vtable,
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struct stm32_ltdcdev_s *priv = (struct stm32_ltdcdev_s *)vtable;
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DEBUGASSERT(vtable != NULL && priv == &g_vtable && oinfo != NULL);
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lcdinfo("vtable=%p, overlay=%d, blank=%02x\n", vtable, oinfo->blank);
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lcdinfo("vtable=%p, overlay=%d, blank=%02x\n",
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vtable, oinfo->overlay, oinfo->blank);
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if (oinfo->overlay < LTDC_NLAYERS)
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{
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74
boards/arm/stm32h7/linum-stm32h753bi/configs/lvgl/defconfig
Normal file
74
boards/arm/stm32h7/linum-stm32h753bi/configs/lvgl/defconfig
Normal file
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@ -0,0 +1,74 @@
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#
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# This file is autogenerated: PLEASE DO NOT EDIT IT.
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#
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# You can use "make menuconfig" to make any modifications to the installed .config file.
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# You can then do "make savedefconfig" to generate a new defconfig file that includes your
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# modifications.
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#
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# CONFIG_STANDARD_SERIAL is not set
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# CONFIG_STM32H7_FB_CMAP is not set
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# CONFIG_STM32H7_LTDC_L1_CHROMAKEYEN is not set
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# CONFIG_STM32H7_LTDC_L2 is not set
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# CONFIG_STM32H7_USE_LEGACY_PINMAP is not set
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CONFIG_ARCH="arm"
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CONFIG_ARCH_BOARD="linum-stm32h753bi"
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CONFIG_ARCH_BOARD_LINUM_STM32H753BI=y
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CONFIG_ARCH_CHIP="stm32h7"
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CONFIG_ARCH_CHIP_STM32H753BI=y
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CONFIG_ARCH_CHIP_STM32H7=y
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CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y
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CONFIG_ARCH_STACKDUMP=y
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CONFIG_ARMV7M_DCACHE=y
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CONFIG_ARMV7M_DCACHE_WRITETHROUGH=y
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CONFIG_ARMV7M_DTCM=y
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CONFIG_ARMV7M_ICACHE=y
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CONFIG_BOARD_LOOPSPERMSEC=43103
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CONFIG_BUILTIN=y
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CONFIG_DEBUG_FEATURES=y
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CONFIG_DEBUG_SYMBOLS=y
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CONFIG_DRIVERS_VIDEO=y
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CONFIG_EXAMPLES_ALARM=y
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CONFIG_EXAMPLES_FB=y
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CONFIG_EXAMPLES_LVGLDEMO=y
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CONFIG_FB_OVERLAY=y
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CONFIG_FS_PROCFS=y
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CONFIG_GRAPHICS_LVGL=y
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CONFIG_INIT_ENTRYPOINT="nsh_main"
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CONFIG_INTELHEX_BINARY=y
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CONFIG_LIBM=y
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CONFIG_LV_USE_CLIB_MALLOC=y
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CONFIG_LV_USE_CLIB_SPRINTF=y
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CONFIG_LV_USE_CLIB_STRING=y
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CONFIG_LV_USE_DEMO_WIDGETS=y
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CONFIG_LV_USE_NUTTX=y
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CONFIG_MM_REGIONS=5
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CONFIG_NSH_ARCHINIT=y
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CONFIG_NSH_BUILTIN_APPS=y
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CONFIG_NSH_DISABLE_IFUPDOWN=y
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CONFIG_NSH_FILEIOSIZE=512
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CONFIG_NSH_LINELEN=64
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CONFIG_NSH_READLINE=y
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CONFIG_PREALLOC_TIMERS=4
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CONFIG_RAM_SIZE=245760
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CONFIG_RAM_START=0x20010000
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CONFIG_RAW_BINARY=y
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CONFIG_RR_INTERVAL=200
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CONFIG_RTC_ALARM=y
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CONFIG_RTC_DATETIME=y
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CONFIG_RTC_DRIVER=y
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CONFIG_SCHED_WAITPID=y
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CONFIG_START_DAY=6
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CONFIG_START_MONTH=12
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CONFIG_START_YEAR=2011
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CONFIG_STM32H7_FMC=y
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CONFIG_STM32H7_LTDC=y
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CONFIG_STM32H7_LTDC_FB_BASE=0xC0000000
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CONFIG_STM32H7_LTDC_FB_SIZE=1228800
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CONFIG_STM32H7_PWR=y
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CONFIG_STM32H7_RTC=y
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CONFIG_STM32H7_USART1=y
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CONFIG_SYSTEM_NSH=y
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CONFIG_TASK_NAME_SIZE=0
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CONFIG_TESTING_RAMTEST=y
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CONFIG_USART1_SERIAL_CONSOLE=y
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CONFIG_VIDEO_FB=y
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@ -88,13 +88,13 @@
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#define STM32_PLLCFG_PLLSRC RCC_PLLCKSELR_PLLSRC_HSE
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/* PLL1, wide 4 - 8 MHz input, enable DIVP, DIVQ, DIVR
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/* PLL1 - 25 MHz input, enable DIVP, DIVQ, DIVR
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*
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* PLL1_VCO = (25 MHz / 5) * 192 = 960 MHz
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*
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* PLL1P = PLL1_VCO/2 = 800 MHz / 2 = 480 MHz
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* PLL1Q = PLL1_VCO/4 = 800 MHz / 4 = 240 MHz
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* PLL1R = PLL1_VCO/8 = 800 MHz / 4 = 240 MHz
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* PLL1R = PLL1_VCO/4 = 800 MHz / 4 = 240 MHz
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*/
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#define STM32_PLLCFG_PLL1CFG (RCC_PLLCFGR_PLL1VCOSEL_WIDE| \
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@ -103,24 +103,24 @@
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RCC_PLLCFGR_DIVQ1EN| \
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RCC_PLLCFGR_DIVR1EN)
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#define STM32_VCO1_FREQUENCY ((STM32_HSE_FREQUENCY / 5) * 192)
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#define STM32_PLL1P_FREQUENCY (STM32_VCO1_FREQUENCY / 2)
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#define STM32_PLL1Q_FREQUENCY (STM32_VCO1_FREQUENCY / 4)
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#define STM32_PLL1R_FREQUENCY (STM32_VCO1_FREQUENCY / 4)
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#define STM32_PLLCFG_PLL1M RCC_PLLCKSELR_DIVM1(5)
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#define STM32_PLLCFG_PLL1N RCC_PLL1DIVR_N1(192)
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#define STM32_PLLCFG_PLL1P RCC_PLL1DIVR_P1(2)
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#define STM32_PLLCFG_PLL1Q RCC_PLL1DIVR_Q1(4)
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#define STM32_PLLCFG_PLL1R RCC_PLL1DIVR_R1(4)
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/* PLL2, wide 4 - 8 MHz input, enable DIVP, DIVQ, DIVR
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#define STM32_VCO1_FREQUENCY ((STM32_HSE_FREQUENCY / 5) * 192)
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#define STM32_PLL1P_FREQUENCY (STM32_VCO1_FREQUENCY / 2)
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#define STM32_PLL1Q_FREQUENCY (STM32_VCO1_FREQUENCY / 4)
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#define STM32_PLL1R_FREQUENCY (STM32_VCO1_FREQUENCY / 4)
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/* PLL2 - 25 MHz input, enable DIVP, DIVQ, DIVR
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*
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* PLL1_VCO = (25 MHz / 2) * 48 = 600 MHz
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* PLL2_VCO = (25 MHz / 2) * 48 = 600 MHz
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*
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* PLL2P = PLL2_VCO/2 = 600 MHz / 8 = 75 MHz
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* PLL2Q = PLL2_VCO/4 = 600 MHz / 40 = 15 MHz
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* PLL2R = PLL2_VCO/8 = 600 MHz / 3 = 200 MHz
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* PLL2P = PLL2_VCO/8 = 600 MHz / 8 = 75 MHz
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* PLL2Q = PLL2_VCO/40 = 600 MHz / 40 = 15 MHz
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* PLL2R = PLL2_VCO/3 = 600 MHz / 3 = 200 MHz
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*/
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#define STM32_PLLCFG_PLL2CFG (RCC_PLLCFGR_PLL2VCOSEL_WIDE| \
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RCC_PLLCFGR_PLL2RGE_4_8_MHZ| \
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@ -128,30 +128,41 @@
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RCC_PLLCFGR_DIVQ2EN| \
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RCC_PLLCFGR_DIVR2EN)
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#define STM32_VCO2_FREQUENCY ((STM32_HSE_FREQUENCY / 2) * 48)
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#define STM32_PLL2P_FREQUENCY (STM32_VCO2_FREQUENCY / 8)
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#define STM32_PLL2Q_FREQUENCY (STM32_VCO2_FREQUENCY / 40)
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#define STM32_PLL2R_FREQUENCY (STM32_VCO2_FREQUENCY / 3)
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#define STM32_PLLCFG_PLL2M RCC_PLLCKSELR_DIVM2(2)
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#define STM32_PLLCFG_PLL2N RCC_PLL2DIVR_N2(48)
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#define STM32_PLLCFG_PLL2P RCC_PLL2DIVR_P2(8)
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#define STM32_PLLCFG_PLL2Q RCC_PLL2DIVR_Q2(40)
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#define STM32_PLLCFG_PLL2R RCC_PLL2DIVR_R2(3)
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/* PLL3 */
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#define STM32_VCO2_FREQUENCY ((STM32_HSE_FREQUENCY / 2) * 48)
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#define STM32_PLL2P_FREQUENCY (STM32_VCO2_FREQUENCY / 8)
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#define STM32_PLL2Q_FREQUENCY (STM32_VCO2_FREQUENCY / 40)
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#define STM32_PLL2R_FREQUENCY (STM32_VCO2_FREQUENCY / 3)
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#define STM32_PLLCFG_PLL3CFG 0
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#define STM32_PLLCFG_PLL3M 0
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#define STM32_PLLCFG_PLL3N 0
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#define STM32_PLLCFG_PLL3P 0
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#define STM32_PLLCFG_PLL3Q 0
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#define STM32_PLLCFG_PLL3R 0
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/* PLL3 - 25 MHz input, enable DIVP, DIVQ, DIVR
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*
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* PLL3_VCO = (25 MHz / 1) * 35 = 875 MHz
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*
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* PLL3P = PLL3_VCO/2 = 875 MHz / 2 = 437.7 MHz
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* PLL3Q = PLL3_VCO/1 = 875 MHz / 1 = 875 MHz
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* PLL3R = PLL3_VCO/20 = 875 MHz / 20 = 43.75 MHz
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*/
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#define STM32_PLLCFG_PLL3CFG (RCC_PLLCFGR_PLL3VCOSEL_WIDE| \
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RCC_PLLCFGR_PLL3RGE_8_16_MHZ| \
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RCC_PLLCFGR_DIVP3EN| \
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RCC_PLLCFGR_DIVQ3EN| \
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RCC_PLLCFGR_DIVR3EN)
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#define STM32_VCO3_FREQUENCY
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#define STM32_PLL3P_FREQUENCY
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#define STM32_PLL3Q_FREQUENCY
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#define STM32_PLL3R_FREQUENCY
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#define STM32_PLLCFG_PLL3M RCC_PLLCKSELR_DIVM3(1)
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#define STM32_PLLCFG_PLL3N RCC_PLL3DIVR_N3(35)
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#define STM32_PLLCFG_PLL3P RCC_PLL3DIVR_P3(2)
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#define STM32_PLLCFG_PLL3Q RCC_PLL3DIVR_Q3(1)
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#define STM32_PLLCFG_PLL3R RCC_PLL3DIVR_R3(20)
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#define STM32_VCO3_FREQUENCY ((STM32_HSE_FREQUENCY / 1) * 35)
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#define STM32_PLL3P_FREQUENCY (STM32_VCO3_FREQUENCY / 2)
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#define STM32_PLL3Q_FREQUENCY (STM32_VCO3_FREQUENCY / 1)
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#define STM32_PLL3R_FREQUENCY (STM32_VCO3_FREQUENCY / 20)
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/* SYSCLK = PLL1P = 480 MHz
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* CPUCLK = SYSCLK / 1 = 480 MHz
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@ -163,7 +174,7 @@
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/* Configure Clock Assignments */
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/* AHB clock (HCLK) is SYSCLK/2 (480 MHz max)
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/* AHB clock (HCLK) is SYSCLK/2 (240 MHz max)
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* HCLK1 = HCLK2 = HCLK3 = HCLK4
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*/
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@ -173,22 +184,22 @@
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/* APB1 clock (PCLK1) is HCLK/2 (120 MHz) */
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#define STM32_RCC_D2CFGR_D2PPRE1 RCC_D2CFGR_D2PPRE1_HCLKd2 /* PCLK1 = HCLK / 2 */
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#define STM32_RCC_D2CFGR_D2PPRE1 RCC_D2CFGR_D2PPRE1_HCLKd2 /* PCLK1 = HCLK / 2 */
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#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/2)
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/* APB2 clock (PCLK2) is HCLK/2 (120 MHz) */
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#define STM32_RCC_D2CFGR_D2PPRE2 RCC_D2CFGR_D2PPRE2_HCLKd2 /* PCLK2 = HCLK / 2 */
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#define STM32_RCC_D2CFGR_D2PPRE2 RCC_D2CFGR_D2PPRE2_HCLKd2 /* PCLK2 = HCLK / 2 */
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#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/2)
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/* APB3 clock (PCLK3) is HCLK/2 (120 MHz) */
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#define STM32_RCC_D1CFGR_D1PPRE RCC_D1CFGR_D1PPRE_HCLKd2 /* PCLK3 = HCLK / 2 */
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#define STM32_RCC_D1CFGR_D1PPRE RCC_D1CFGR_D1PPRE_HCLKd2 /* PCLK3 = HCLK / 2 */
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#define STM32_PCLK3_FREQUENCY (STM32_HCLK_FREQUENCY/2)
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/* APB4 clock (PCLK4) is HCLK/2 (120 MHz) */
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#define STM32_RCC_D3CFGR_D3PPRE RCC_D3CFGR_D3PPRE_HCLKd2 /* PCLK4 = HCLK / 2 */
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#define STM32_RCC_D3CFGR_D3PPRE RCC_D3CFGR_D3PPRE_HCLKd2 /* PCLK4 = HCLK / 2 */
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#define STM32_PCLK4_FREQUENCY (STM32_HCLK_FREQUENCY/2)
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/* Timer clock frequencies */
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@ -246,6 +257,17 @@
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#define STM32_RCC_D3CCIPR_ADCSRC RCC_D3CCIPR_ADCSEL_PLL2
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/* FDCAN 1 2 clock source, use STM32_HSE_FREQUENCY */
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#define STM32_RCC_D2CCIP1R_FDCANSEL RCC_D2CCIP1R_FDCANSEL_HSE
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/* SDMMC 1 2 clock source, use STM32_PLL1Q_FREQUENCY */
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#define STM32_RCC_D1CCIPR_SDMMCSEL RCC_D1CCIPR_SDMMC_PLL1
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/* FMC clock source, use STM32_PLL1Q_FREQUENCY */
|
||||
#define BOARD_FMC_CLK RCC_D1CCIPR_FMCSEL_HCLK
|
||||
|
||||
/* FLASH wait states
|
||||
*
|
||||
* ------------ ---------- -----------
|
||||
|
|
@ -268,21 +290,6 @@
|
|||
|
||||
#define BOARD_FLASH_WAITSTATES 4
|
||||
|
||||
/* SDMMC definitions ********************************************************/
|
||||
|
||||
/* Init 400 kHz, PLL1Q/(2*300) = 240 MHz / (2*300) = 400 Khz */
|
||||
|
||||
#define STM32_SDMMC_INIT_CLKDIV (300 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT)
|
||||
|
||||
/* Just set these to 24 MHz for now,
|
||||
* PLL1Q/(2*5) = 240 MHz / (2*5) = 24 MHz
|
||||
*/
|
||||
|
||||
#define STM32_SDMMC_MMCXFR_CLKDIV (5 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT)
|
||||
#define STM32_SDMMC_SDXFR_CLKDIV (5 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT)
|
||||
|
||||
#define STM32_SDMMC_CLKCR_EDGE STM32_SDMMC_CLKCR_NEGEDGE
|
||||
|
||||
/* LED definitions **********************************************************/
|
||||
|
||||
/* The board has 1 user LED RGB that could be used this diagnostic LED too.
|
||||
|
|
@ -386,6 +393,18 @@
|
|||
|
||||
/* SDMMC1 - Used SD Card memory */
|
||||
|
||||
/* Init 400 kHz, PLL1Q/(2*300) = 240 MHz / (2*300) = 400 Khz */
|
||||
|
||||
#define STM32_SDMMC_INIT_CLKDIV (300 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT)
|
||||
|
||||
/* Just set these to 24 MHz for now,
|
||||
* PLL1Q/(2*5) = 240 MHz / (2*5) = 24 MHz
|
||||
*/
|
||||
|
||||
#define STM32_SDMMC_MMCXFR_CLKDIV (5 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT)
|
||||
#define STM32_SDMMC_SDXFR_CLKDIV (5 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT)
|
||||
#define STM32_SDMMC_CLKCR_EDGE STM32_SDMMC_CLKCR_NEGEDGE
|
||||
|
||||
#define GPIO_SDMMC1_CK (GPIO_SDMMC1_CK_0|GPIO_SPEED_100MHz) /* PC12 */
|
||||
#define GPIO_SDMMC1_CMD (GPIO_SDMMC1_CMD_0|GPIO_SPEED_100MHz) /* PD2 */
|
||||
#define GPIO_SDMMC1_D0 (GPIO_SDMMC1_D0_0|GPIO_SPEED_100MHz) /* PC8 */
|
||||
|
|
@ -450,15 +469,13 @@
|
|||
|
||||
/* SDRAM FMC definitions ****************************************************/
|
||||
|
||||
/* The following settings correspond to W9864G6KH-6 SDRAM
|
||||
* part-number ("-6" speed grades ) and FMC_SDCLK frequency of 166 MHz
|
||||
* (period is ~ 6.25 ns).
|
||||
/* The following settings correspond to IS42S16400J SDRAM
|
||||
* part-number and FMC_SDCLK frequency of 120 MHz
|
||||
*/
|
||||
|
||||
/* Though W9864G6KH-6 SDRAM itself provides 16-bit data bus,
|
||||
/* Though IS42S16400J SDRAM itself provides 16-bit data bus,
|
||||
* linum board routes only DQ[15:0] bits.
|
||||
*/
|
||||
#define BOARD_FMC_CLK RCC_D1CCIPR_FMCSEL_HCLK
|
||||
|
||||
#if CONFIG_STM32H7_FMC
|
||||
# define FMC_SDCLK_FREQUENCY (STM32_HCLK_FREQUENCY / 2)
|
||||
|
|
@ -559,37 +576,37 @@
|
|||
|
||||
/* LTDC */
|
||||
|
||||
#define GPIO_LTDC_R0 (GPIO_LTDC_R0_3|GPIO_SPEED_100MHz)
|
||||
#define GPIO_LTDC_R1 (GPIO_LTDC_R1_3|GPIO_SPEED_100MHz)
|
||||
#define GPIO_LTDC_R2 (GPIO_LTDC_R2_4|GPIO_SPEED_100MHz)
|
||||
#define GPIO_LTDC_R3 (GPIO_LTDC_R3_3|GPIO_SPEED_100MHz)
|
||||
#define GPIO_LTDC_R4 (GPIO_LTDC_R4_4|GPIO_SPEED_100MHz)
|
||||
#define GPIO_LTDC_R5 (GPIO_LTDC_R5_4|GPIO_SPEED_100MHz)
|
||||
#define GPIO_LTDC_R6 (GPIO_LTDC_R6_4|GPIO_SPEED_100MHz)
|
||||
#define GPIO_LTDC_R7 (GPIO_LTDC_R7_3|GPIO_SPEED_100MHz)
|
||||
#define GPIO_LTDC_R0 (GPIO_LTDC_R0_3|GPIO_SPEED_100MHz) /* PI15 */
|
||||
#define GPIO_LTDC_R1 (GPIO_LTDC_R1_3|GPIO_SPEED_100MHz) /* PJ0 */
|
||||
#define GPIO_LTDC_R2 (GPIO_LTDC_R2_4|GPIO_SPEED_100MHz) /* PJ1 */
|
||||
#define GPIO_LTDC_R3 (GPIO_LTDC_R3_2|GPIO_SPEED_100MHz) /* PJ2 */
|
||||
#define GPIO_LTDC_R4 (GPIO_LTDC_R4_4|GPIO_SPEED_100MHz) /* PJ3 */
|
||||
#define GPIO_LTDC_R5 (GPIO_LTDC_R5_5|GPIO_SPEED_100MHz) /* PJ4 */
|
||||
#define GPIO_LTDC_R6 (GPIO_LTDC_R6_3|GPIO_SPEED_100MHz) /* PJ5 */
|
||||
#define GPIO_LTDC_R7 (GPIO_LTDC_R7_3|GPIO_SPEED_100MHz) /* PJ6 */
|
||||
|
||||
#define GPIO_LTDC_G0 (GPIO_LTDC_G0_2|GPIO_SPEED_100MHz)
|
||||
#define GPIO_LTDC_G1 (GPIO_LTDC_G1_2|GPIO_SPEED_100MHz)
|
||||
#define GPIO_LTDC_G2 (GPIO_LTDC_G2_3|GPIO_SPEED_100MHz)
|
||||
#define GPIO_LTDC_G3 (GPIO_LTDC_G3_4|GPIO_SPEED_100MHz)
|
||||
#define GPIO_LTDC_G4 (GPIO_LTDC_G4_3|GPIO_SPEED_100MHz)
|
||||
#define GPIO_LTDC_G5 (GPIO_LTDC_G5_3|GPIO_SPEED_100MHz)
|
||||
#define GPIO_LTDC_G6 (GPIO_LTDC_G6_3|GPIO_SPEED_100MHz)
|
||||
#define GPIO_LTDC_G7 (GPIO_LTDC_G7_3|GPIO_SPEED_100MHz)
|
||||
#define GPIO_LTDC_G0 (GPIO_LTDC_G0_3|GPIO_SPEED_100MHz) /* PJ7 */
|
||||
#define GPIO_LTDC_G1 (GPIO_LTDC_G1_3|GPIO_SPEED_100MHz) /* PJ8 */
|
||||
#define GPIO_LTDC_G2 (GPIO_LTDC_G2_3|GPIO_SPEED_100MHz) /* PJ9 */
|
||||
#define GPIO_LTDC_G3 (GPIO_LTDC_G3_4|GPIO_SPEED_100MHz) /* PJ10 */
|
||||
#define GPIO_LTDC_G4 (GPIO_LTDC_G4_4|GPIO_SPEED_100MHz) /* PJ11 */
|
||||
#define GPIO_LTDC_G5 (GPIO_LTDC_G5_3|GPIO_SPEED_100MHz) /* PK0 */
|
||||
#define GPIO_LTDC_G6 (GPIO_LTDC_G6_3|GPIO_SPEED_100MHz) /* PK1 */
|
||||
#define GPIO_LTDC_G7 (GPIO_LTDC_G7_4|GPIO_SPEED_100MHz) /* PK2 */
|
||||
|
||||
#define GPIO_LTDC_B0 (GPIO_LTDC_B0_3|GPIO_SPEED_100MHz)
|
||||
#define GPIO_LTDC_B1 (GPIO_LTDC_B1_2|GPIO_SPEED_100MHz)
|
||||
#define GPIO_LTDC_B2 (GPIO_LTDC_B2_3|GPIO_SPEED_100MHz)
|
||||
#define GPIO_LTDC_B3 (GPIO_LTDC_B3_3|GPIO_SPEED_100MHz)
|
||||
#define GPIO_LTDC_B4 (GPIO_LTDC_B4_3|GPIO_SPEED_100MHz)
|
||||
#define GPIO_LTDC_B5 (GPIO_LTDC_B5_3|GPIO_SPEED_100MHz)
|
||||
#define GPIO_LTDC_B6 (GPIO_LTDC_B6_3|GPIO_SPEED_100MHz)
|
||||
#define GPIO_LTDC_B7 (GPIO_LTDC_B7_3|GPIO_SPEED_100MHz)
|
||||
#define GPIO_LTDC_B0 (GPIO_LTDC_B0_3|GPIO_SPEED_100MHz) /* PJ12 */
|
||||
#define GPIO_LTDC_B1 (GPIO_LTDC_B1_3|GPIO_SPEED_100MHz) /* PJ13 */
|
||||
#define GPIO_LTDC_B2 (GPIO_LTDC_B2_4|GPIO_SPEED_100MHz) /* PJ14 */
|
||||
#define GPIO_LTDC_B3 (GPIO_LTDC_B3_4|GPIO_SPEED_100MHz) /* PJ15 */
|
||||
#define GPIO_LTDC_B4 (GPIO_LTDC_B4_4|GPIO_SPEED_100MHz) /* PK3 */
|
||||
#define GPIO_LTDC_B5 (GPIO_LTDC_B5_3|GPIO_SPEED_100MHz) /* PK4 */
|
||||
#define GPIO_LTDC_B6 (GPIO_LTDC_B6_3|GPIO_SPEED_100MHz) /* PK5 */
|
||||
#define GPIO_LTDC_B7 (GPIO_LTDC_B7_3|GPIO_SPEED_100MHz) /* PK6 */
|
||||
|
||||
#define GPIO_LTDC_VSYNC (GPIO_LTDC_VSYNC_2|GPIO_SPEED_100MHz)
|
||||
#define GPIO_LTDC_HSYNC (GPIO_LTDC_HSYNC_2|GPIO_SPEED_100MHz)
|
||||
#define GPIO_LTDC_DE (GPIO_LTDC_DE_3|GPIO_SPEED_100MHz)
|
||||
#define GPIO_LTDC_CLK (GPIO_LTDC_CLK_3|GPIO_SPEED_100MHz)
|
||||
#define GPIO_LTDC_DE (GPIO_LTDC_DE_3|GPIO_SPEED_100MHz) /* PK7 */
|
||||
#define GPIO_LTDC_CLK (GPIO_LTDC_CLK_3|GPIO_SPEED_100MHz) /* PI14 */
|
||||
#define GPIO_LTDC_VSYNC (GPIO_LTDC_VSYNC_3|GPIO_SPEED_100MHz) /* PI9 */
|
||||
#define GPIO_LTDC_HSYNC (GPIO_LTDC_HSYNC_2|GPIO_SPEED_100MHz) /* PI10 */
|
||||
|
||||
/* LCD definitions **********************************************************/
|
||||
|
||||
|
|
@ -598,14 +615,12 @@
|
|||
|
||||
#define BOARD_LTDC_OUTPUT_BPP 16
|
||||
#define BOARD_LTDC_HFP 160
|
||||
#define BOARD_LTDC_HBP 160
|
||||
#define BOARD_LTDC_HBP 160 /* AccumulatedHBP */
|
||||
#define BOARD_LTDC_VFP 1
|
||||
#define BOARD_LTDC_VBP 23
|
||||
#define BOARD_LTDC_HSYNC 0
|
||||
#define BOARD_LTDC_VSYNC 0
|
||||
#define BOARD_LTDC_VBP 23 /* AccumulatedVBP */
|
||||
|
||||
#define BOARD_LTDC_PLLSAIN 192
|
||||
#define BOARD_LTDC_PLLSAIR 5
|
||||
#define BOARD_LTDC_HSYNC 1 /* HorizontalSync */
|
||||
#define BOARD_LTDC_VSYNC 1 /* VerticalSync */
|
||||
|
||||
/* Pixel Clock Polarity */
|
||||
|
||||
|
|
|
|||
|
|
@ -70,6 +70,10 @@ if(CONFIG_CL_MFRC522)
|
|||
list(APPEND SRCS stm32_mfrc522.c)
|
||||
endif()
|
||||
|
||||
if(CONFIG_STM32H7_LTDC)
|
||||
list(APPEND SRCS stm32_lcd.c)
|
||||
endif()
|
||||
|
||||
target_sources(board PRIVATE ${SRCS})
|
||||
|
||||
set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/flash.ld")
|
||||
|
|
|
|||
|
|
@ -72,4 +72,8 @@ ifeq ($(CONFIG_BOARDCTL),y)
|
|||
CSRCS += stm32_appinitialize.c
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_STM32H7_LTDC),y)
|
||||
CSRCS += stm32_lcd.c
|
||||
endif
|
||||
|
||||
include $(TOPDIR)/boards/Board.mk
|
||||
|
|
|
|||
|
|
@ -120,11 +120,13 @@
|
|||
|
||||
#define LINUMSTM32H753BI_QETIMER 5
|
||||
|
||||
/* LCD */
|
||||
/* DISP_RESET */
|
||||
|
||||
#define GPIO_LCD_DISP (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz|\
|
||||
GPIO_OUTPUT_SET|GPIO_PORTI|GPIO_PIN7)
|
||||
|
||||
/* DISP_PWM */
|
||||
|
||||
#define GPIO_LCD_BL (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz|\
|
||||
GPIO_OUTPUT_SET|GPIO_PORTH|GPIO_PIN6)
|
||||
|
||||
|
|
|
|||
|
|
@ -75,10 +75,12 @@ static void convert_lcd_rgb565(void)
|
|||
stm32_gpiowrite(GPIO_LTDC_R1, 0);
|
||||
stm32_configgpio(GPIO_LTDC_R2);
|
||||
stm32_gpiowrite(GPIO_LTDC_R2, 0);
|
||||
|
||||
stm32_configgpio(GPIO_LTDC_G0);
|
||||
stm32_gpiowrite(GPIO_LTDC_G0, 0);
|
||||
stm32_configgpio(GPIO_LTDC_G1);
|
||||
stm32_gpiowrite(GPIO_LTDC_G1, 0);
|
||||
|
||||
stm32_configgpio(GPIO_LTDC_B0);
|
||||
stm32_gpiowrite(GPIO_LTDC_B0, 0);
|
||||
stm32_configgpio(GPIO_LTDC_B1);
|
||||
|
|
|
|||
Loading…
Reference in a new issue