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arm64: fix tpidr maybe null

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Before the MPU initialization, the up_update_task(this_cpu()) function is called at a time when hardware cache coherency is not yet enabled.
In certain critical scenarios, Core 1 reads a zero value for tcb from the global variable g_assignedtask and stores this zero value into the tpidr
register. This results in subsequent interrupt handlers reading a zero tcb, causing an exception.

Signed-off-by: hujun5 <hujun5@xiaomi.com>
This commit is contained in:
hujun5 2024-12-25 16:51:33 +08:00 committed by Xiang Xiao
parent d4acd6949f
commit 2886fddc0f
1 changed files with 8 additions and 6 deletions
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14
arch/arm64/src/common/arm64_cpustart.c
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@ -217,12 +217,6 @@ int up_cpu_start(int cpu)
void arm64_boot_secondary_c_routine(void)
{
struct tcb_s *tcb = current_task(this_cpu());
/* Init idle task to percpu reg */
up_update_task(tcb);
#ifdef CONFIG_ARCH_HAVE_MPU
arm64_mpu_init(false);
#endif
@ -231,6 +225,14 @@ void arm64_boot_secondary_c_routine(void)
arm64_mmu_init(false);
#endif
/* We need to confirm that current_task has been initialized. */
while (!current_task(this_cpu()));
/* Init idle task to percpu reg */
up_update_task(current_task(this_cpu()));
arm64_gic_secondary_init();
arm64_smp_init_top();