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This commit is contained in:
Yoshinori Sugino 2020-10-24 10:40:33 +09:00 committed by Abdelatif Guettouche
parent ea5ec14995
commit 3ac90fca79
28 changed files with 64 additions and 64 deletions
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2
arch/arm/src/eoss3/hardware/eoss3_clock.h
View file

@ -168,6 +168,6 @@
/* MISC_LOCK_KEY_CTRL Register */
#define MISC_LOCK_KEY_CTRL_UNLOCK (0x1acce551)
#define MISC_LOCK_KEY_CTRL_LOCK (0x00000000)
#define MISC_LOCK_KEY_CTRL_LOCK (0x00000000)
#endif /* __ARCH_ARM_SRC_EOSS3_HARDWARE_EOSS3_CLOCK_H */

2
arch/arm/src/imxrt/hardware/rt106x/imxrt106x_ccm.h
View file

@ -784,7 +784,7 @@
#define CCM_CMEOR_MOD_EN_OV_PIT (1 << 6) /* Bit 6: Override clock enable signal from PIT */
#define CCM_CMEOR_MOD_EN_OV_USDHC (1 << 7) /* Bit 7: Override clock enable signal from USDHC */
#define CCM_CMEOR_MOD_EN_OV_TRNG (1 << 9) /* Bit 9: Override clock enable signal from TRNG */
#define CCM_CMEOR_MOD_EN_OV_CANFD_CPI (1 << 10) /* Bit 10: Override clock enable signal from CAN3 */
#define CCM_CMEOR_MOD_EN_OV_CANFD_CPI (1 << 10) /* Bit 10: Override clock enable signal from CAN3 */
/* Bits 11-27: Reserved */
#define CCM_CMEOR_MOD_EN_OV_CAN2_CPI (1 << 28) /* Bit 28: Override clock enable signal from CAN2 */
#define CCM_CMEOR_MOD_EN_OV_CAN1_CPI (1 << 30) /* Bit 30: Override clock enable signal from CAN1 */

8
arch/arm/src/samd5e5/hardware/sam_tc.h
View file

@ -343,17 +343,17 @@
#define TC_CTRLA_CAPTEN0_SHIFT (16) /* (TC_CTRLA) Capture Channel 0 Enable */
#define TC_CTRLA_CAPTEN0 (1 << TC_CTRLA_CAPTEN0_SHIFT)
#define TC_CTRLA_CAPTEN1_SHIFT (17) /* (TC_CTRLA) Capture Channel 1 Enable */
#define TC_CTRLA_CAPTEN1 (1 << TC_CTRLA_CAPTEN1_SHIFT)
#define TC_CTRLA_CAPTEN1 (1 << TC_CTRLA_CAPTEN1_SHIFT)
#define TC_CTRLA_COPEN0_SHIFT (20) /* (TC_CTRLA) Capture On Pin 0 Enable */
#define TC_CTRLA_COPEN0 (1 << TC_CTRLA_COPEN1_SHIFT)
#define TC_CTRLA_COPEN1_SHIFT (21) /* (TC_CTRLA) Capture On Pin 1 Enable */
#define TC_CTRLA_COPEN1 (1 << TC_CTRLA_CAPTEN1_SHIFT)
#define TC_CTRLA_CAPTMODE0_SHIFT (24) /* (TC_CTRLA) Capture Mode Channel 0 */
#define TC_CTRLA_COPEN1 (1 << TC_CTRLA_CAPTEN1_SHIFT)
#define TC_CTRLA_CAPTMODE0_SHIFT (24) /* (TC_CTRLA) Capture Mode Channel 0 */
#define TC_CTRLA_CAPTMODE0_MASK (3 << TC_CTRLA_CAPTMODE0_SHIFT)
#define TC_CTRLA_CAPTMODE0_CAPTD (0 << TC_CTRLA_CAPTMODE0_SHIFT) /* (TC_CTRLA) Default capture */
#define TC_CTRLA_CAPTMODE0_CAPTMIN (1 << TC_CTRLA_CAPTMODE0_SHIFT) /* (TC_CTRLA) Minimum capture */
#define TC_CTRLA_CAPTMODE0_CAPTMAX (2 << TC_CTRLA_CAPTMODE0_SHIFT) /* (TC_CTRLA) Maximum capture */
#define TC_CTRLA_CAPTMODE1_SHIFT (27) /* (TC_CTRLA) Capture Mode Channel 0 */
#define TC_CTRLA_CAPTMODE1_SHIFT (27) /* (TC_CTRLA) Capture Mode Channel 0 */
#define TC_CTRLA_CAPTMODE1_MASK (3 << TC_CTRLA_CAPTMODE1_SHIFT)
#define TC_CTRLA_CAPTMODE1_CAPTD (0 << TC_CTRLA_CAPTMODE1_SHIFT) /* (TC_CTRLA) Default capture */
#define TC_CTRLA_CAPTMODE1_CAPTMIN (1 << TC_CTRLA_CAPTMODE1_SHIFT) /* (TC_CTRLA) Minimum capture */

2
arch/arm/src/samd5e5/sam_usb.c
View file

@ -853,7 +853,7 @@ static void sam_sw_shutdown(struct sam_usbdev_s *priv);
#ifdef CONFIG_USBHOST
#undef CONFIG_SAM_USBHOST_PKTDUMP
#undef CONFIG_SAM_USBHOST_PKTDUMP
#ifdef CONFIG_SAM_USBHOST_PKTDUMP
# define sam_pktdump(m,b,n) lib_dumpbuffer(m,b,n)
#else

2
arch/arm/src/samd5e5/sam_wdt.c
View file

@ -60,7 +60,7 @@
/** N clock cycles */
#define WDT_CLK_8CYCLE 8
#define WDT_CLK_8CYCLE 8
#define WDT_CLK_16CYCLE 16
#define WDT_CLK_32CYCLE 32
#define WDT_CLK_64CYCLE 64

2
arch/renesas/src/rx65n/rx65n_definitions.h
View file

@ -1030,7 +1030,7 @@
#define USB0_CFIFO16 (USB0.CFIFO.WORD)
#define USB0_D0FIFO16 (USB0.D0FIFO.WORD)
#define USB0_D1FIFO16 (USB0.D1FIFO.WORD)
#define USB_WRITEEND (0x0000u)
#define USB_WRITEEND (0x0000u)
#define USB_CTRL_END (0u)
#define USB_BREQUEST (0xFF00u)
#define USB_BRDY0 (0x0001u) /* b1: PIPE0 */

22
arch/renesas/src/rx65n/rx65n_dtc.c
View file

@ -104,7 +104,7 @@
#define DTC_VECTOR_TABLE_SIZE_BYTES (DTC_VECTOR_ADDRESS_ALIGN + DTC_VECTOR_TABLE_SIZE)
#endif
#endif
/* DTC register mask and value */
@ -170,7 +170,7 @@ struct st_dtc_mrb_bit
uint8_t DISEL:1; /* DTC Interrupt Select */
uint8_t CHNS :1; /* DTC Chain Transfer Select */
uint8_t CHNE :1; /* b7: DTC Chain Transfer Enable */
#else
#else
uint8_t CHNE :1; /* b7: DTC Chain Transfer Enable */
uint8_t CHNS :1; /* DTC Chain Transfer Select */
uint8_t DISEL:1; /* DTC Interrupt Select */
@ -269,10 +269,10 @@ struct st_second_word
#ifdef __RX_LITTLE_ENDIAN__
uint8_t SAR[3];
dtc_mrb_t MRB;
#else
#else
dtc_mrb_t MRB;
uint8_t DAR[3];
#endif
#endif
};
struct st_third_word
@ -280,10 +280,10 @@ struct st_third_word
#ifdef __RX_LITTLE_ENDIAN__
dtc_crb_t CRB;
dtc_cra_t CRA;
#else
#else
dtc_cra_t CRA;
dtc_crb_t CRB;
#endif
#endif
};
typedef union lword1
@ -331,9 +331,9 @@ struct st_first_lword
#else
dtc_mrc_t MRC;
uint8_t reserver; /* reserve area */
#endif
#endif
#endif
#endif
};
struct st_fourth_lword
@ -396,7 +396,7 @@ struct rx65n_dtc_s
uint8_t * vectortable; /* Vector table pointer */
#if defined (CONFIG_RX65N_DTC_SEQUENCE_TRANSFER_MODE)
uint8_t * indextable; /* Index table pointer for sequence transfer */
#endif
#endif
uint8_t addmode; /* Address mode */
@ -1775,7 +1775,7 @@ void rx65n_dtc_initialize(void)
#if defined(CONFIG_RX65N_DTC_SHORT_ADDRESS_MODE) /* Short-address mode */
DTC.DTCADMOD.BIT.SHORT = 1;
dtchandle->addmode = 1;
#else
#else
/* Full-address mode */
DTC.DTCADMOD.BIT.SHORT = 0;
@ -1805,4 +1805,4 @@ void rx65n_dtc_initialize(void)
rx65n_dtc_start(dtchandle);
}
}
#endif /* End of CONFIG_RX65N_DTC*/
#endif /* End of CONFIG_RX65N_DTC*/

2
arch/renesas/src/rx65n/rx65n_riic.c
View file

@ -864,7 +864,7 @@ static void rx65n_riic_init(FAR struct rx65n_i2c_priv_s *priv)
}
rx65n_putreg(regval, RX65N_RIIC0_ICMR2);
#endif
#endif
rx65n_riic_irq_init(priv);

4
arch/renesas/src/rx65n/rx65n_riic.h
View file

@ -50,7 +50,7 @@
#define RIIC_ERR_AL 3 /* Arbitration lost error */
#define RIIC_ERR_TMO 4 /* Time Out error */
#define RIIC_ERR_NACK 5 /* NACK reception */
#define RIIC_ERR_OTHER 6 /* Other error */
#define RIIC_ERR_OTHER 6 /* Other error */
/****************************************************************************
* Public Function Prototypes
@ -92,4 +92,4 @@ FAR struct i2c_master_s *rx65n_i2cbus_initialize(int channel);
int rx65n_i2cbus_uninitialize(FAR struct i2c_master_s *dev);
#endif /* __ARCH_RENESAS_SRC_RX65N_RX65N_RIIC_H */
#endif /* __ARCH_RENESAS_SRC_RX65N_RX65N_RIIC_H */

4
arch/renesas/src/rx65n/rx65n_rspi.c
View file

@ -492,7 +492,7 @@ dtc_static_transfer_data_cfg_t rx_cfg =
.source_addr = (uint32_t)NULL, /* Set data register address */
.dest_addr = (uint32_t)NULL, /* This will set dynamically */
.transfer_count = 0, /* This will set dynamically */
#if CONFIG_RX65N_RSPI_BUF_SIZE > 1
#if CONFIG_RX65N_RSPI_BUF_SIZE > 1
.block_size = CONFIG_RX65N_RSPI_BUF_SIZE, /* Looks like tx fifo size */
#else
.block_size = 0,
@ -2309,7 +2309,7 @@ static void rspi_bus_initialize(FAR struct rx65n_rspidev_s *priv)
#else
regval8 |= (RSPI_SPDCR_SPFC0 | RSPI_SPDCR_SPFC1); /* 4 frames */
priv->bufsize = BUFSIZE_4FRAME;
#endif
#endif
regval8 |= (RSPI_SPDCR_SPBYT);
priv->nbits = 8;
rspi_putreg8(priv, RX65N_RSPI_SPDCR_OFFSET, regval8);

2
arch/renesas/src/rx65n/rx65n_rspi_sw.c
View file

@ -1905,7 +1905,7 @@ static void rspi_bus_initialize(FAR struct rx65n_rspidev_s *priv)
#else
regval8 |= (RSPI_SPDCR_SPFC0 | RSPI_SPDCR_SPFC1); /* 4 frames */
priv->bufsize = BUFSIZE_4FRAME;
#endif
#endif
regval8 |= (RSPI_SPDCR_SPBYT);
priv->nbits = 8;
rspi_putreg8(priv, RX65N_RSPI_SPDCR_OFFSET, regval8);

2
arch/xtensa/src/esp32/esp32_emac.c
View file

@ -145,7 +145,7 @@
/* SMI interface pins */
#define EMAC_MDC_PIN (CONFIG_ESP32_ETH_MDCPIN)
#define EMAC_MDC_PIN (CONFIG_ESP32_ETH_MDCPIN)
#define EMAC_MDIO_PIN (CONFIG_ESP32_ETH_MDIOPIN)
/* Reset PHY chip pins */

2
arch/xtensa/src/esp32/esp32_rtc.c
View file

@ -87,7 +87,7 @@
/* Disable logging from the ROM code. */
#define RTC_DISABLE_ROM_LOG ((1 << 0) | (1 << 16))
#define RTC_DISABLE_ROM_LOG ((1 << 0) | (1 << 16))
#define EXT_OSC_FLAG BIT(3)
/* Default initializer for esp32_rtc_sleep_config_t

4
arch/xtensa/src/esp32/esp32_tim.c
View file

@ -34,7 +34,7 @@
#include "xtensa.h"
#include "hardware/esp32_tim.h"
#include "hardware/esp32_tim.h"
#include "esp32_tim.h"
#include "esp32_cpuint.h"
@ -130,7 +130,7 @@ struct esp32_tim_ops_s esp32_tim_ops =
.ackint = esp32_tim_ackint
};
#ifdef CONFIG_ESP32_TIMER0
#ifdef CONFIG_ESP32_TIMER0
/* TIMER0 */
struct esp32_tim_priv_s g_esp32_tim0_priv =

2
arch/xtensa/src/esp32/esp32_tim_lowerhalf.c
View file

@ -45,7 +45,7 @@
/* TIMER configuration */
/* Lowest divider, Highest Frequency Best Resolution */
#define ESP32_TIMER_PRESCALER 2
#define ESP32_TIMER_PRESCALER 2
/* Number of cycles to complete 1 microsecond */
#define ESP32_1USECOND ((TB_CLK_FREQ/ESP32_TIMER_PRESCALER)/1000000)
#define ESP32_INIT_CNTR_VALUE 0 /* Initial counter value */

2
arch/xtensa/src/esp32/esp32_wlan.c
View file

@ -55,7 +55,7 @@
* Pre-processor Definitions
****************************************************************************/
#define STA_DEVNO 0
#define STA_DEVNO 0
/* TX poll delay = 1 seconds.
* CLK_TCK is the number of clock ticks per second

2
boards/arm/s32k1xx/s32k144evb/include/board.h
View file

@ -158,7 +158,7 @@
/* I2C selections ***********************************************************/
#define PIN_LPI2C0_SCL PIN_LPI2C0_SCL_2 /* PTA3 */
#define PIN_LPI2C0_SCL PIN_LPI2C0_SCL_2 /* PTA3 */
#define PIN_LPI2C0_SDA PIN_LPI2C0_SDA_2 /* PTA2 */
#endif /* __BOARDS_ARM_S32K144EVB_INCLUDE_BOARD_H */

2
boards/arm/s32k1xx/s32k146evb/include/board.h
View file

@ -158,7 +158,7 @@
/* I2C selections ***********************************************************/
#define PIN_LPI2C0_SCL PIN_LPI2C0_SCL_2 /* PTA3 */
#define PIN_LPI2C0_SCL PIN_LPI2C0_SCL_2 /* PTA3 */
#define PIN_LPI2C0_SDA PIN_LPI2C0_SDA_2 /* PTA2 */
#endif /* __BOARDS_ARM_S32K146EVB_INCLUDE_BOARD_H */

16
boards/arm/samd5e5/metro-m4/include/board.h
View file

@ -482,17 +482,17 @@
/* Tickless */
#define BOARD_TC0_PINMAP_CC0 0 /* CC0: (not used) */
#define BOARD_TC0_PINMAP_CC1 0 /* CC1: (not used) */
#define BOARD_TC0_GCLKGEN 3
#define BOARD_TC0_PINMAP_CC0 0 /* CC0: (not used) */
#define BOARD_TC0_PINMAP_CC1 0 /* CC1: (not used) */
#define BOARD_TC0_GCLKGEN 3
#define BOARD_TC0_FREQUENCY BOARD_GCLK3_FREQUENCY
#define BOARD_TC2_PINMAP_CC0 0 /* CC0: (not used) */
#define BOARD_TC2_PINMAP_CC1 0 /* CC1: (not used) */
#define BOARD_TC2_PINMAP_CC0 0 /* CC0: (not used) */
#define BOARD_TC2_PINMAP_CC1 0 /* CC1: (not used) */
#define BOARD_TC2_GCLKGEN 3
#define BOARD_TC2_FREQUENCY BOARD_GCLK3_FREQUENCY
#define BOARD_TC4_PINMAP_CC0 0 /* CC0: (not used) */
#define BOARD_TC4_PINMAP_CC1 0 /* CC1: (not used) */
#define BOARD_TC4_GCLKGEN 3
#define BOARD_TC4_PINMAP_CC0 0 /* CC0: (not used) */
#define BOARD_TC4_PINMAP_CC1 0 /* CC1: (not used) */
#define BOARD_TC4_GCLKGEN 3
#define BOARD_TC4_FREQUENCY BOARD_GCLK3_FREQUENCY
/* USB */

2
boards/arm/samd5e5/metro-m4/src/sam_bringup.c
View file

@ -116,7 +116,7 @@ int sam_bringup(void)
/* Initialize I2C bus */
ret = metro_m4_i2cdev_initialize();
#endif
#endif
#ifdef CONFIG_USBHOST
/* Initialize USB host operation. samd_usbhost_initialize() starts a

2
boards/renesas/rx65n/rx65n-grrose/include/rx65n_gpio.h
View file

@ -32,7 +32,7 @@
#define PHY_STS_REG_LINK (1 << 0)
#define PHY_STS_READ_REG PHY_STS_REG
#define PHY_STS_BIT_MASK (0x1)
#define PHY_STS_SHIFT_COUNT (0x0)
#define PHY_STS_SHIFT_COUNT (0x0)
#endif
#if defined(CONFIG_ARCH_RX65N_GRROSE)

4
boards/renesas/rx65n/rx65n-rsk1mb/src/rx65n_gpio.c
View file

@ -99,7 +99,7 @@ void r_ether_pheriperal_enable(void)
{
/* TODO */
}
#endif
#endif
/****************************************************************************
* Name: sci2_init_port
@ -123,5 +123,5 @@ inline void sci2_init_port(void)
PORT5.PDR.BIT.BT0 = 1u;
PORT5.PMR.BIT.BT0 = 1u;
}
#endif
#endif
#endif /* CONFIG_ARCH_BOARD_RX65N_RSK1MB*/

6
boards/renesas/rx65n/rx65n-rsk2mb/src/rx65n_gpio.c
View file

@ -38,7 +38,7 @@
* LED Port Initialization for RX65N RSK2MB Board
****************************************************************************/
#if defined (CONFIG_ARCH_BOARD_RX65N_RSK2MB)
#if defined (CONFIG_ARCH_BOARD_RX65N_RSK2MB)
void led_port_create(void)
{
/* LED Port initialization of RX65N RSK2MB */
@ -460,7 +460,7 @@ void rspi_pinconfig(int bus)
break;
}
}
#endif
#endif
/****************************************************************************
* Name: riic0_init_port
@ -527,4 +527,4 @@ inline void riic2_init_port(void)
PORT1.PMR.BIT.B7 = 1u;
}
#endif
#endif /* CONFIG_ARCH_BOARD_RX65N_RSK2MB */
#endif /* CONFIG_ARCH_BOARD_RX65N_RSK2MB */

6
drivers/sensors/hdc1008.c
View file

@ -87,9 +87,9 @@
#define HDC1008_CONFIGURATION_BTST (1 << 11) /* Bit 11: Battery status */
#define HDC1008_CONFIGURATION_MODE (1 << 12) /* Bit 12: Mode of aquisition */
#define HDC1008_CONFIGURATION_HEAT_SHIFT (13) /* Bit 13: Heater */
#define HDC1008_CONFIGURATION_HEAT_MASK (0x01 << HDC1008_CONFIGURATION_HEAT_SHIFT)
# define HDC1008_CONFIGURATION_HEAT_DISABLE (0x00 << HDC1008_CONFIGURATION_HEAT_SHIFT)
# define HDC1008_CONFIGURATION_HEAT_ENABLE (0x01 << HDC1008_CONFIGURATION_HEAT_SHIFT)
#define HDC1008_CONFIGURATION_HEAT_MASK (0x01 << HDC1008_CONFIGURATION_HEAT_SHIFT)
# define HDC1008_CONFIGURATION_HEAT_DISABLE (0x00 << HDC1008_CONFIGURATION_HEAT_SHIFT)
# define HDC1008_CONFIGURATION_HEAT_ENABLE (0x01 << HDC1008_CONFIGURATION_HEAT_SHIFT)
/* Bit 14: Reserved */
#define HDC1008_CONFIGURATION_RST (1 << 15) /* Bit 15: Software reset bit */

12
include/netpacket/can.h
View file

@ -67,17 +67,17 @@
/* CAN_RAW socket options */
#define CAN_RAW_FILTER (__SO_PROTOCOL + 0)
#define CAN_RAW_FILTER (__SO_PROTOCOL + 0)
/* set 0 .. n can_filter(s) */
#define CAN_RAW_ERR_FILTER (__SO_PROTOCOL + 1)
#define CAN_RAW_ERR_FILTER (__SO_PROTOCOL + 1)
/* set filter for error frames */
#define CAN_RAW_LOOPBACK (__SO_PROTOCOL + 2)
#define CAN_RAW_LOOPBACK (__SO_PROTOCOL + 2)
/* local loopback (default:on) */
#define CAN_RAW_RECV_OWN_MSGS (__SO_PROTOCOL + 3)
#define CAN_RAW_RECV_OWN_MSGS (__SO_PROTOCOL + 3)
/* receive my own msgs (default:off) */
#define CAN_RAW_FD_FRAMES (__SO_PROTOCOL + 4)
#define CAN_RAW_FD_FRAMES (__SO_PROTOCOL + 4)
/* allow CAN FD frames (default:off) */
#define CAN_RAW_JOIN_FILTERS (__SO_PROTOCOL + 5)
#define CAN_RAW_JOIN_FILTERS (__SO_PROTOCOL + 5)
/* all filters must match to trigger */
#define CAN_RAW_TX_DEADLINE (__SO_PROTOCOL + 6)
/* Abort frame when deadline passed */

8
include/nuttx/power/bq27426.h
View file

@ -201,10 +201,10 @@
#define BQ27426_OPCONFIG_BATLOWEN (1 << 2)
#define BQ27426_OPCONFIG_TEMPS (1 << 0)
#define BQ27426_ACCESS_SUB_CLASS_80 0x50
#define BQ27426_ACCESS_SUB_CLASS_81 0x51
#define BQ27426_ACCESS_SUB_CLASS_80 0x50
#define BQ27426_ACCESS_SUB_CLASS_81 0x51
#define BQ27426_ACCESS_SUB_CLASS_82 0x52
#define BQ27426_ACCESS_SUB_CLASS_89 0x59
#define BQ27426_ACCESS_SUB_CLASS_64 0x40
#define BQ27426_ACCESS_SUB_CLASS_89 0x59
#define BQ27426_ACCESS_SUB_CLASS_64 0x40
#endif /* __DRIVERS_POWER_BQ27426_H */

2
include/nuttx/sched_note.h
View file

@ -329,7 +329,7 @@ struct note_filter_mode_s
unsigned int flag; /* Filter mode flag */
#ifdef CONFIG_SMP
unsigned int cpuset; /* The set of monitored CPUs */
#endif
#endif
};
/* This is the type of the argument passed to the NOTECTL_GETSYSCALLFILTER

2
net/netdev/netdev_ioctl.c
View file

@ -1088,7 +1088,7 @@ static int netdev_ifr_ioctl(FAR struct socket *psock, int cmd,
}
}
break;
#endif
#endif
#if defined(CONFIG_NETDEV_IOCTL) && defined(CONFIG_NETDEV_CAN_BITRATE_IOCTL)
case SIOCGCANBITRATE: /* Get bitrate from a CAN controller */