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arch: inline up_interrupt_context()

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inline the up_interrupt_context() to avoid unnecessary stack pushes

Signed-off-by: chao.an <anchao@xiaomi.com>
This commit is contained in:
chao.an 2022-05-17 12:16:29 +08:00 committed by Xiang Xiao
parent d4b0fc9eb4
commit 3f65b562bb
81 changed files with 970 additions and 1093 deletions
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92
arch/arm/include/irq.h
View file

@ -29,6 +29,11 @@
* Included Files
****************************************************************************/
#include <sys/types.h>
#ifndef __ASSEMBLY__
# include <stdbool.h>
#endif
/* Include NuttX-specific IRQ definitions */
#include <nuttx/irq.h>
@ -55,4 +60,91 @@
# include <arch/arm/irq.h>
#endif
#ifndef __ASSEMBLY__
#ifdef __cplusplus
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Public Data
****************************************************************************/
/* g_current_regs[] holds a references to the current interrupt level
* register storage structure. If is non-NULL only during interrupt
* processing. Access to g_current_regs[] must be through the macro
* CURRENT_REGS for portability.
*/
/* For the case of architectures with multiple CPUs, then there must be one
* such value for each processor that can receive an interrupt.
*/
EXTERN volatile uint32_t *g_current_regs[CONFIG_SMP_NCPUS];
#define CURRENT_REGS (g_current_regs[up_cpu_index()])
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: up_cpu_index
*
* Description:
* Return an index in the range of 0 through (CONFIG_SMP_NCPUS-1) that
* corresponds to the currently executing CPU.
*
* Input Parameters:
* None
*
* Returned Value:
* An integer index in the range of 0 through (CONFIG_SMP_NCPUS-1) that
* corresponds to the currently executing CPU.
*
****************************************************************************/
#ifdef CONFIG_SMP
int up_cpu_index(void);
#else
# define up_cpu_index() (0)
#endif
/****************************************************************************
* Inline functions
****************************************************************************/
/****************************************************************************
* Name: up_interrupt_context
*
* Description:
* Return true is we are currently executing in the interrupt
* handler context.
*
****************************************************************************/
static inline bool up_interrupt_context(void)
{
#ifdef CONFIG_SMP
irqstate_t flags = up_irq_save();
#endif
bool ret = CURRENT_REGS != NULL;
#ifdef CONFIG_SMP
up_irq_restore(flags);
#endif
return ret;
}
#endif /* __ASSEMBLY__ */
#undef EXTERN
#ifdef __cplusplus
}
#endif
#endif /* __ARCH_ARM_INCLUDE_IRQ_H */

2
arch/arm/src/common/Make.defs
View file

@ -22,7 +22,7 @@
CMN_CSRCS += arm_allocateheap.c arm_assert.c arm_blocktask.c
CMN_CSRCS += arm_createstack.c arm_exit.c arm_fullcontextrestore.c
CMN_CSRCS += arm_initialize.c arm_interruptcontext.c arm_lowputs.c
CMN_CSRCS += arm_initialize.c arm_lowputs.c
CMN_CSRCS += arm_modifyreg16.c arm_modifyreg32.c
CMN_CSRCS += arm_modifyreg8.c arm_puts.c arm_releasepending.c
CMN_CSRCS += arm_releasestack.c arm_reprioritizertr.c arm_saveusercontext.c

13
arch/arm/src/common/arm_internal.h
View file

@ -160,19 +160,6 @@ extern "C"
#define EXTERN extern
#endif
/* g_current_regs[] holds a references to the current interrupt level
* register storage structure. If is non-NULL only during interrupt
* processing. Access to g_current_regs[] must be through the macro
* CURRENT_REGS for portability.
*/
/* For the case of architectures with multiple CPUs, then there must be one
* such value for each processor that can receive an interrupt.
*/
EXTERN volatile uint32_t *g_current_regs[CONFIG_SMP_NCPUS];
#define CURRENT_REGS (g_current_regs[up_cpu_index()])
/* This is the beginning of heap as provided from arm_head.S.
* This is the first address in DRAM after the loaded
* program+bss+idle stack. The end of the heap is

58
arch/arm/src/common/arm_interruptcontext.c
View file

@ -1,58 +0,0 @@
/****************************************************************************
* arch/arm/src/common/arm_interruptcontext.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdbool.h>
#include <nuttx/arch.h>
#include <nuttx/irq.h>
#include "arm_internal.h"
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: up_interrupt_context
*
* Description: Return true is we are currently executing in
* the interrupt handler context.
*
****************************************************************************/
bool up_interrupt_context(void)
{
#ifdef CONFIG_SMP
irqstate_t flags = up_irq_save();
#endif
bool ret = CURRENT_REGS != NULL;
#ifdef CONFIG_SMP
up_irq_restore(flags);
#endif
return ret;
}

70
arch/avr/include/irq.h
View file

@ -29,6 +29,11 @@
* Included Files
****************************************************************************/
#include <sys/types.h>
#ifndef __ASSEMBLY__
# include <stdbool.h>
#endif
/* Include NuttX-specific IRQ definitions */
#include <nuttx/irq.h>
@ -55,19 +60,6 @@
* Public Types
****************************************************************************/
/****************************************************************************
* Inline functions
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
#ifndef __ASSEMBLY__
#ifdef __cplusplus
#define EXTERN extern "C"
extern "C"
@ -76,6 +68,58 @@ extern "C"
#define EXTERN extern
#endif
/****************************************************************************
* Public Data
****************************************************************************/
#ifndef __ASSEMBLY__
/* This holds a references to the current interrupt level register storage
* structure. If is non-NULL only during interrupt processing.
*/
#ifdef CONFIG_ARCH_FAMILY_AVR32
EXTERN volatile uint32_t *g_current_regs;
#else
EXTERN volatile uint8_t *g_current_regs;
#endif
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: up_cpu_index
*
* Description:
* Return an index in the range of 0 through (CONFIG_SMP_NCPUS-1) that
* corresponds to the currently executing CPU.
*
* Input Parameters:
* None
*
* Returned Value:
* An integer index in the range of 0 through (CONFIG_SMP_NCPUS-1) that
* corresponds to the currently executing CPU.
*
****************************************************************************/
#define up_cpu_index() (0)
/****************************************************************************
* Inline functions
****************************************************************************/
/****************************************************************************
* Name: up_interrupt_context
*
* Description:
* Return true is we are currently executing in the interrupt
* handler context.
*
****************************************************************************/
#define up_interrupt_context() (g_current_regs != NULL)
#undef EXTERN
#ifdef __cplusplus
}

2
arch/avr/src/at32uc3/Make.defs
View file

@ -27,7 +27,7 @@ HEAD_ASRC = up_nommuhead.S
CMN_ASRCS = up_exceptions.S up_fullcontextrestore.S up_switchcontext.S
CMN_CSRCS = up_assert.c up_allocateheap.c up_blocktask.c up_copystate.c
CMN_CSRCS += up_createstack.c up_mdelay.c up_udelay.c up_exit.c up_idle.c
CMN_CSRCS += up_initialize.c up_initialstate.c up_interruptcontext.c
CMN_CSRCS += up_initialize.c up_initialstate.c
CMN_CSRCS += up_modifyreg8.c up_modifyreg16.c up_modifyreg32.c
CMN_CSRCS += up_releasepending.c up_releasestack.c up_reprioritizertr.c
CMN_CSRCS += up_schedulesigaction.c up_sigdeliver.c up_stackframe.c

2
arch/avr/src/at90usb/Make.defs
View file

@ -27,7 +27,7 @@ HEAD_ASRC = at90usb_head.S
CMN_ASRCS = up_switchcontext.S
CMN_CSRCS = up_allocateheap.c up_assert.c up_blocktask.c up_copystate.c
CMN_CSRCS += up_createstack.c up_doirq.c up_exit.c up_idle.c up_initialize.c
CMN_CSRCS += up_initialstate.c up_interruptcontext.c up_irq.c up_lowputs.c
CMN_CSRCS += up_initialstate.c up_irq.c up_lowputs.c
CMN_CSRCS += up_mdelay.c up_modifyreg8.c up_modifyreg16.c up_modifyreg32.c
CMN_CSRCS += up_puts.c up_releasepending.c up_releasestack.c
CMN_CSRCS += up_reprioritizertr.c up_schedulesigaction.c up_sigdeliver.c

2
arch/avr/src/atmega/Make.defs
View file

@ -27,7 +27,7 @@ HEAD_ASRC = atmega_head.S
CMN_ASRCS = up_switchcontext.S
CMN_CSRCS = up_allocateheap.c up_assert.c up_blocktask.c up_copystate.c
CMN_CSRCS += up_createstack.c up_doirq.c up_exit.c up_idle.c up_initialize.c
CMN_CSRCS += up_initialstate.c up_interruptcontext.c up_irq.c up_lowputs.c
CMN_CSRCS += up_initialstate.c up_irq.c up_lowputs.c
CMN_CSRCS += up_mdelay.c up_modifyreg8.c up_modifyreg16.c up_modifyreg32.c
CMN_CSRCS += up_puts.c up_releasepending.c up_releasestack.c
CMN_CSRCS += up_reprioritizertr.c up_schedulesigaction.c up_sigdeliver.c

6
arch/avr/src/avr/avr.h
View file

@ -55,12 +55,6 @@
****************************************************************************/
#ifndef __ASSEMBLY__
/* This holds a references to the current interrupt level register storage
* structure. If is non-NULL only during interrupt processing.
*/
extern volatile uint8_t *g_current_regs;
/* This is the beginning of heap as provided from up_head.S. This is the
* first address in DRAM after the loaded program+bss+idle stack. The end
* of the heap is CONFIG_RAM_END

6
arch/avr/src/avr32/avr32.h
View file

@ -65,12 +65,6 @@
****************************************************************************/
#ifndef __ASSEMBLY__
/* This holds a references to the current interrupt level register storage
* structure. If is non-NULL only during interrupt processing.
*/
extern volatile uint32_t *g_current_regs;
/* This is the beginning of heap as provided from up_head.S. This is the
* first address in DRAM after the loaded program+bss+idle stack.
* The end of the heap is CONFIG_RAM_END

2
arch/avr/src/common/up_internal.h
View file

@ -29,6 +29,8 @@
#ifndef __ASSEMBLY__
# include <stdint.h>
# include <nuttx/arch.h>
# include <nuttx/irq.h>
#endif
#ifdef CONFIG_ARCH_FAMILY_AVR32

55
arch/avr/src/common/up_interruptcontext.c
View file

@ -1,55 +0,0 @@
/****************************************************************************
* arch/avr/src/common/up_interruptcontext.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdbool.h>
#include <nuttx/arch.h>
#include <nuttx/irq.h>
#include "up_internal.h"
/****************************************************************************
* Private Types
****************************************************************************/
/****************************************************************************
* Private Function Prototypes
****************************************************************************/
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: up_interrupt_context
*
* Description: Return true is we are currently executing in
* the interrupt handler context.
****************************************************************************/
bool up_interrupt_context(void)
{
return g_current_regs != NULL;
}

90
arch/ceva/include/irq.h
View file

@ -29,6 +29,11 @@
* Included Files
****************************************************************************/
#include <sys/types.h>
#ifndef __ASSEMBLY__
# include <stdbool.h>
#endif
/* Include chip-specific IRQ definitions (including IRQ numbers) */
#include <arch/chip/irq.h>
@ -75,4 +80,89 @@
#define IRQ_VINT25 (IRQ_VINT_FIRST + 25)
#define IRQ_VINT26 (IRQ_VINT_FIRST + 26)
/****************************************************************************
* Public Data
****************************************************************************/
#ifndef __ASSEMBLY__
#ifdef __cplusplus
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/* g_current_regs[] holds a references to the current interrupt level
* register storage structure. If is non-NULL only during interrupt
* processing. Access to g_current_regs[] must be through the macro
* CURRENT_REGS for portability.
*/
/* For the case of architectures with multiple CPUs, then there must be one
* such value for each processor that can receive an interrupt.
*/
EXTERN uint32_t *volatile g_current_regs[CONFIG_SMP_NCPUS];
#define CURRENT_REGS (g_current_regs[up_cpu_index()])
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: up_cpu_index
*
* Description:
* Return an index in the range of 0 through (CONFIG_SMP_NCPUS-1) that
* corresponds to the currently executing CPU.
*
* Input Parameters:
* None
*
* Returned Value:
* An integer index in the range of 0 through (CONFIG_SMP_NCPUS-1) that
* corresponds to the currently executing CPU.
*
****************************************************************************/
#ifdef CONFIG_SMP
int up_cpu_index(void);
#else
# define up_cpu_index() (0)
#endif
/****************************************************************************
* Inline functions
****************************************************************************/
/****************************************************************************
* Name: up_interrupt_context
*
* Description:
* Return true is we are currently executing in the interrupt
* handler context.
*
****************************************************************************/
static inline bool up_interrupt_context(void)
{
#ifdef CONFIG_SMP
irqstate_t flags = up_irq_save();
#endif
bool ret = CURRENT_REGS != NULL;
#ifdef CONFIG_SMP
up_irq_restore(flags);
#endif
return ret;
}
#undef EXTERN
#ifdef __cplusplus
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_CEVA_INCLUDE_IRQ_H */

13
arch/ceva/src/common/up_internal.h
View file

@ -118,19 +118,6 @@ extern "C"
#define EXTERN extern
#endif
/* g_current_regs[] holds a references to the current interrupt level
* register storage structure. If is non-NULL only during interrupt
* processing. Access to g_current_regs[] must be through the macro
* CURRENT_REGS for portability.
*/
/* For the case of architectures with multiple CPUs, then there must be one
* such value for each processor that can receive an interrupt.
*/
EXTERN uint32_t *volatile g_current_regs[CONFIG_SMP_NCPUS];
#define CURRENT_REGS (g_current_regs[up_cpu_index()])
/* This is the beginning of heap as provided from up_head.S.
* This is the first address in DRAM after the loaded
* program+bss+idle stack. The end of the heap is

45
arch/ceva/src/common/up_interruptcontext.c
View file

@ -1,45 +0,0 @@
/****************************************************************************
* arch/ceva/src/common/up_interruptcontext.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <nuttx/arch.h>
#include "up_internal.h"
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: up_interrupt_context
*
* Description: Return true is we are currently executing in
* the interrupt handler context.
****************************************************************************/
bool up_interrupt_context(void)
{
return CURRENT_REGS != NULL;
}

68
arch/hc/include/irq.h
View file

@ -29,6 +29,11 @@
* Included Files
****************************************************************************/
#include <sys/types.h>
#ifndef __ASSEMBLY__
# include <stdbool.h>
#endif
/* Include NuttX-specific IRQ definitions */
#include <nuttx/irq.h>
@ -55,18 +60,6 @@
* Public Types
****************************************************************************/
/****************************************************************************
* Inline functions
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
#ifndef __ASSEMBLY__
#ifdef __cplusplus
#define EXTERN extern "C"
@ -76,6 +69,57 @@ extern "C"
#define EXTERN extern
#endif
/****************************************************************************
* Public Data
****************************************************************************/
/* This holds a references to the current interrupt level register storage
* structure. If is non-NULL only during interrupt processing.
*/
EXTERN volatile uint8_t *g_current_regs;
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: up_cpu_index
*
* Description:
* Return an index in the range of 0 through (CONFIG_SMP_NCPUS-1) that
* corresponds to the currently executing CPU.
*
* Input Parameters:
* None
*
* Returned Value:
* An integer index in the range of 0 through (CONFIG_SMP_NCPUS-1) that
* corresponds to the currently executing CPU.
*
****************************************************************************/
#define up_cpu_index() (0)
/****************************************************************************
* Inline functions
****************************************************************************/
/****************************************************************************
* Name: up_interrupt_context
*
* Description:
* Return true is we are currently executing in the interrupt
* handler context.
*
****************************************************************************/
#define up_interrupt_context() (g_current_regs != NULL)
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
#undef EXTERN
#ifdef __cplusplus
}

7
arch/hc/src/common/up_internal.h
View file

@ -29,6 +29,7 @@
#ifndef __ASSEMBLY__
# include <nuttx/compiler.h>
# include <nuttx/irq.h>
# include <stdint.h>
#endif
@ -110,12 +111,6 @@ typedef void (*up_vector_t)(void);
****************************************************************************/
#ifndef __ASSEMBLY__
/* This holds a references to the current interrupt level register storage
* structure. If is non-NULL only during interrupt processing.
*/
extern volatile uint8_t *g_current_regs;
/* This is the beginning of heap as provided from processor-specific logic.
* This is the first address in RAM after the loaded program+bss+idle stack.
* The end of the heap is CONFIG_RAM_END

56
arch/hc/src/common/up_interruptcontext.c
View file

@ -1,56 +0,0 @@
/****************************************************************************
* arch/hc/src/common/up_interruptcontext.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdbool.h>
#include <nuttx/arch.h>
#include <nuttx/irq.h>
#include "up_internal.h"
/****************************************************************************
* Private Types
****************************************************************************/
/****************************************************************************
* Private Function Prototypes
****************************************************************************/
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: up_interrupt_context
*
* Description: Return true is we are currently executing in the interrupt
* handler context.
*
****************************************************************************/
bool up_interrupt_context(void)
{
return g_current_regs != NULL;
}

2
arch/hc/src/m9s12/Make.defs
View file

@ -21,7 +21,7 @@
HEAD_ASRC = m9s12_vectors.S
CMN_CSRCS = up_allocateheap.c up_blocktask.c up_copystate.c up_createstack.c
CMN_CSRCS += up_doirq.c up_exit.c up_idle.c up_initialize.c up_interruptcontext.c
CMN_CSRCS += up_doirq.c up_exit.c up_idle.c up_initialize.c
CMN_CSRCS += up_mdelay.c up_modifyreg16.c up_modifyreg32.c up_modifyreg8.c
CMN_CSRCS += up_puts.c up_releasepending.c up_releasestack.c up_reprioritizertr.c
CMN_CSRCS += up_stackframe.c up_udelay.c up_unblocktask.c up_usestack.c

72
arch/mips/include/irq.h
View file

@ -29,6 +29,11 @@
* Included Files
****************************************************************************/
#include <sys/types.h>
#ifndef __ASSEMBLY__
# include <stdbool.h>
#endif
/* Include NuttX-specific IRQ definitions */
#include <nuttx/irq.h>
@ -54,19 +59,6 @@
****************************************************************************/
#ifndef __ASSEMBLY__
/****************************************************************************
* Inline functions
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
#ifdef __cplusplus
#define EXTERN extern "C"
extern "C"
@ -75,6 +67,60 @@ extern "C"
#define EXTERN extern
#endif
/****************************************************************************
* Public Data
****************************************************************************/
/* g_current_regs holds a references to the current interrupt level
* register storage structure. It is non-NULL only during interrupt
* processing. Access to g_current_regs must be through the macro
* CURRENT_REGS for portability.
*/
/* For the case of architectures with multiple CPUs, then there must be one
* such value for each processor that can receive an interrupt.
*/
EXTERN volatile uint32_t *g_current_regs;
#define CURRENT_REGS g_current_regs
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: up_cpu_index
*
* Description:
* Return an index in the range of 0 through (CONFIG_SMP_NCPUS-1) that
* corresponds to the currently executing CPU.
*
* Input Parameters:
* None
*
* Returned Value:
* An integer index in the range of 0 through (CONFIG_SMP_NCPUS-1) that
* corresponds to the currently executing CPU.
*
****************************************************************************/
#define up_cpu_index() (0)
/****************************************************************************
* Inline functions
****************************************************************************/
/****************************************************************************
* Name: up_interrupt_context
*
* Description:
* Return true is we are currently executing in the interrupt
* handler context.
*
****************************************************************************/
#define up_interrupt_context() (g_current_regs != NULL)
#undef EXTERN
#ifdef __cplusplus
}

13
arch/mips/src/common/mips_internal.h
View file

@ -112,19 +112,6 @@ typedef void (*up_vector_t)(void);
****************************************************************************/
#ifndef __ASSEMBLY__
/* g_current_regs holds a references to the current interrupt level
* register storage structure. It is non-NULL only during interrupt
* processing. Access to g_current_regs must be through the macro
* CURRENT_REGS for portability.
*/
/* For the case of architectures with multiple CPUs, then there must be one
* such value for each processor that can receive an interrupt.
*/
extern volatile uint32_t *g_current_regs[CONFIG_SMP_NCPUS];
#define CURRENT_REGS (g_current_regs[up_cpu_index()])
/* This is the beginning of heap as provided from up_head.S. This is the
* first address in DRAM after the loaded program+bss+idle stack. The end
* of the heap is CONFIG_RAM_END

55
arch/mips/src/common/mips_interruptcontext.c
View file

@ -1,55 +0,0 @@
/****************************************************************************
* arch/mips/src/common/mips_interruptcontext.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdbool.h>
#include <nuttx/arch.h>
#include <nuttx/irq.h>
#include "mips_internal.h"
/****************************************************************************
* Private Types
****************************************************************************/
/****************************************************************************
* Private Function Prototypes
****************************************************************************/
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: up_interrupt_context
*
* Description: Return true is we are currently executing in
* the interrupt handler context.
****************************************************************************/
bool up_interrupt_context(void)
{
return CURRENT_REGS != NULL;
}

2
arch/mips/src/pic32mx/Make.defs
View file

@ -27,7 +27,7 @@ HEAD_ASRC = pic32mx_head.S
CMN_ASRCS = mips_syscall0.S vfork.S
CMN_CSRCS = mips_allocateheap.c mips_assert.c mips_blocktask.c mips_copystate.c
CMN_CSRCS += mips_createstack.c mips_doirq.c mips_exit.c mips_initialize.c
CMN_CSRCS += mips_initialstate.c mips_interruptcontext.c mips_irq.c mips_lowputs.c
CMN_CSRCS += mips_initialstate.c mips_irq.c mips_lowputs.c
CMN_CSRCS += mips_mdelay.c mips_modifyreg8.c mips_modifyreg16.c mips_modifyreg32.c
CMN_CSRCS += mips_puts.c mips_releasepending.c mips_releasestack.c
CMN_CSRCS += mips_reprioritizertr.c mips_schedulesigaction.c mips_sigdeliver.c

2
arch/mips/src/pic32mx/pic32mx_irq.c
View file

@ -53,7 +53,7 @@
* Public Data
****************************************************************************/
volatile uint32_t *g_current_regs[1];
volatile uint32_t *g_current_regs;
/****************************************************************************
* Private Data

2
arch/mips/src/pic32mz/Make.defs
View file

@ -27,7 +27,7 @@ HEAD_ASRC = pic32mz_head.S
CMN_ASRCS = mips_syscall0.S vfork.S mips_cache.S
CMN_CSRCS = mips_allocateheap.c mips_assert.c mips_blocktask.c mips_copystate.c
CMN_CSRCS += mips_createstack.c mips_doirq.c mips_exit.c mips_initialize.c
CMN_CSRCS += mips_initialstate.c mips_interruptcontext.c mips_irq.c mips_lowputs.c
CMN_CSRCS += mips_initialstate.c mips_irq.c mips_lowputs.c
CMN_CSRCS += mips_mdelay.c mips_modifyreg8.c mips_modifyreg16.c mips_modifyreg32.c
CMN_CSRCS += mips_puts.c mips_releasepending.c mips_releasestack.c
CMN_CSRCS += mips_reprioritizertr.c mips_schedulesigaction.c mips_sigdeliver.c

2
arch/mips/src/pic32mz/pic32mz_irq.c
View file

@ -65,7 +65,7 @@
* CURRENT_REGS for portability.
*/
volatile uint32_t *g_current_regs[1];
volatile uint32_t *g_current_regs;
/****************************************************************************
* Private Data

60
arch/misoc/include/irq.h
View file

@ -29,6 +29,11 @@
* Included Files
****************************************************************************/
#include <sys/types.h>
#ifndef __ASSEMBLY__
# include <stdbool.h>
#endif
#include <nuttx/irq.h>
#include <arch/chip/irq.h>
@ -43,10 +48,6 @@
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
#ifndef __ASSEMBLY__
#ifdef __cplusplus
#define EXTERN extern "C"
@ -56,6 +57,57 @@ extern "C"
#define EXTERN extern
#endif
/****************************************************************************
* Public Data
****************************************************************************/
/* This holds a references to the current interrupt level register storage
* structure. If is non-NULL only during interrupt processing.
*/
EXTERN volatile uint32_t *g_current_regs;
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: up_cpu_index
*
* Description:
* Return an index in the range of 0 through (CONFIG_SMP_NCPUS-1) that
* corresponds to the currently executing CPU.
*
* Input Parameters:
* None
*
* Returned Value:
* An integer index in the range of 0 through (CONFIG_SMP_NCPUS-1) that
* corresponds to the currently executing CPU.
*
****************************************************************************/
#define up_cpu_index() (0)
/****************************************************************************
* Inline functions
****************************************************************************/
/****************************************************************************
* Name: up_interrupt_context
*
* Description:
* Return true is we are currently executing in the interrupt
* handler context.
*
****************************************************************************/
#define up_interrupt_context() (g_current_regs != NULL)
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
irqstate_t up_irq_save(void);
irqstate_t up_irq_enable(void);
void up_irq_restore(irqstate_t flags);

2
arch/misoc/src/lm32/Make.defs
View file

@ -30,7 +30,7 @@ CHIP_ASRCS = lm32_syscall.S
CHIP_CSRCS = lm32_allocateheap.c lm32_assert.c lm32_blocktask.c
CHIP_CSRCS += lm32_copystate.c lm32_createstack.c lm32_decodeirq.c
CHIP_CSRCS += lm32_doirq.c lm32_dumpstate.c lm32_exit.c lm32_idle.c
CHIP_CSRCS += lm32_initialize.c lm32_initialstate.c lm32_interruptcontext.c
CHIP_CSRCS += lm32_initialize.c lm32_initialstate.c
CHIP_CSRCS += lm32_irq.c lm32_releasepending.c lm32_releasestack.c
CHIP_CSRCS += lm32_stackframe.c lm32_swint.c lm32_unblocktask.c
CHIP_CSRCS += lm32_reprioritizertr.c lm32_schedulesigaction.c lm32_sigdeliver.c

2
arch/misoc/src/lm32/lm32.h
View file

@ -29,6 +29,7 @@
#ifndef __ASSEMBLY__
# include <nuttx/compiler.h>
# include <nuttx/irq.h>
# include <sys/types.h>
# include <stdint.h>
#endif
@ -89,7 +90,6 @@
#ifndef __ASSEMBLY__
extern volatile uint32_t *g_current_regs;
extern uint32_t g_idle_topstack;
/****************************************************************************

46
arch/misoc/src/lm32/lm32_interruptcontext.c
View file

@ -1,46 +0,0 @@
/****************************************************************************
* arch/misoc/src/lm32/lm32_interruptcontext.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdbool.h>
#include <nuttx/arch.h>
#include "lm32.h"
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: up_interrupt_context
*
* Description: Return true is we are currently executing in
* the interrupt handler context.
****************************************************************************/
bool up_interrupt_context(void)
{
return g_current_regs != NULL;
}

2
arch/misoc/src/minerva/Make.defs
View file

@ -30,7 +30,7 @@ CHIP_ASRCS = minerva_syscall.S
CHIP_CSRCS = minerva_allocateheap.c minerva_assert.c minerva_blocktask.c
CHIP_CSRCS += minerva_copystate.c minerva_createstack.c minerva_decodeirq.c
CHIP_CSRCS += minerva_doirq.c minerva_dumpstate.c minerva_exit.c minerva_idle.c
CHIP_CSRCS += minerva_initialize.c minerva_initialstate.c minerva_interruptcontext.c
CHIP_CSRCS += minerva_initialize.c minerva_initialstate.c
CHIP_CSRCS += minerva_irq.c minerva_releasepending.c minerva_releasestack.c
CHIP_CSRCS += minerva_stackframe.c minerva_swint.c minerva_unblocktask.c
CHIP_CSRCS += minerva_reprioritizertr.c minerva_schedulesigaction.c minerva_sigdeliver.c

1
arch/misoc/src/minerva/minerva.h
View file

@ -89,7 +89,6 @@
#ifndef __ASSEMBLY__
extern volatile uint32_t *g_current_regs;
extern uint32_t g_idle_topstack;
/****************************************************************************

46
arch/misoc/src/minerva/minerva_interruptcontext.c
View file

@ -1,46 +0,0 @@
/****************************************************************************
* arch/misoc/src/minerva/minerva_interruptcontext.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdbool.h>
#include <nuttx/arch.h>
#include "minerva.h"
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: up_interrupt_context
*
* Description: Return true is we are currently executing in
* the interrupt handler context.
****************************************************************************/
bool up_interrupt_context(void)
{
return g_current_regs != NULL;
}

91
arch/or1k/include/irq.h
View file

@ -29,6 +29,11 @@
* Included Files
****************************************************************************/
#include <sys/types.h>
#ifndef __ASSEMBLY__
# include <stdbool.h>
#endif
/* Include NuttX-specific IRQ definitions */
#include <nuttx/irq.h>
@ -37,4 +42,90 @@
#include <arch/chip/irq.h>
/****************************************************************************
* Public Data
****************************************************************************/
#ifndef __ASSEMBLY__
#ifdef __cplusplus
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/* g_current_regs[] holds a references to the current interrupt level
* register storage structure. If is non-NULL only during interrupt
* processing. Access to g_current_regs[] must be through the macro
* CURRENT_REGS for portability.
*/
/* For the case of architectures with multiple CPUs, then there must be one
* such value for each processor that can receive an interrupt.
*/
EXTERN volatile uint32_t *g_current_regs[CONFIG_SMP_NCPUS];
#define CURRENT_REGS (g_current_regs[up_cpu_index()])
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: up_cpu_index
*
* Description:
* Return an index in the range of 0 through (CONFIG_SMP_NCPUS-1) that
* corresponds to the currently executing CPU.
*
* Input Parameters:
* None
*
* Returned Value:
* An integer index in the range of 0 through (CONFIG_SMP_NCPUS-1) that
* corresponds to the currently executing CPU.
*
****************************************************************************/
#ifdef CONFIG_SMP
int up_cpu_index(void);
#else
# define up_cpu_index() (0)
#endif
/****************************************************************************
* Inline functions
****************************************************************************/
/****************************************************************************
* Name: up_interrupt_context
*
* Description:
* Return true is we are currently executing in the interrupt
* handler context.
*
****************************************************************************/
static inline bool up_interrupt_context(void)
{
#ifdef CONFIG_SMP
irqstate_t flags = up_irq_save();
#endif
bool ret = CURRENT_REGS != NULL;
#ifdef CONFIG_SMP
up_irq_restore(flags);
#endif
return ret;
}
#undef EXTERN
#ifdef __cplusplus
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_OR1K_INCLUDE_IRQ_H */

13
arch/or1k/src/common/up_internal.h
View file

@ -131,19 +131,6 @@ extern "C"
#define EXTERN extern
#endif
/* g_current_regs[] holds a references to the current interrupt level
* register storage structure. If is non-NULL only during interrupt
* processing. Access to g_current_regs[] must be through the macro
* CURRENT_REGS for portability.
*/
/* For the case of architectures with multiple CPUs, then there must be one
* such value for each processor that can receive an interrupt.
*/
EXTERN volatile uint32_t *g_current_regs[CONFIG_SMP_NCPUS];
#define CURRENT_REGS (g_current_regs[up_cpu_index()])
/* This is the beginning of heap as provided from up_head.S.
* This is the first address in DRAM after the loaded
* program+bss+idle stack. The end of the heap is

47
arch/or1k/src/common/up_interruptcontext.c
View file

@ -1,47 +0,0 @@
/****************************************************************************
* arch/or1k/src/common/up_interruptcontext.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdbool.h>
#include <nuttx/arch.h>
#include <nuttx/irq.h>
#include "up_internal.h"
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: up_interrupt_context
*
* Description: Return true is we are currently executing in
* the interrupt handler context.
****************************************************************************/
bool up_interrupt_context(void)
{
return CURRENT_REGS != NULL;
}

1
arch/or1k/src/mor1kx/Make.defs
View file

@ -23,7 +23,6 @@ CMN_ASRCS = up_vectortab.S \
up_fullcontextrestore.S
CMN_CSRCS = up_initialize.c \
up_interruptcontext.c \
up_allocateheap.c \
up_createstack.c \
up_usestack.c \

65
arch/renesas/include/irq.h
View file

@ -29,6 +29,11 @@
* Included Files
****************************************************************************/
#include <sys/types.h>
#ifndef __ASSEMBLY__
# include <stdbool.h>
#endif
#include <nuttx/irq.h>
#include <arch/chip/irq.h>
@ -40,18 +45,6 @@
* Public Types
****************************************************************************/
/****************************************************************************
* Inline functions
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
#ifndef __ASSEMBLY__
#ifdef __cplusplus
#define EXTERN extern "C"
@ -61,6 +54,54 @@ extern "C"
#define EXTERN extern
#endif
/****************************************************************************
* Public Data
****************************************************************************/
/* This holds a references to the current interrupt level
* register storage structure. If is non-NULL only during
* interrupt processing.
*/
EXTERN volatile uint32_t *g_current_regs;
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: up_cpu_index
*
* Description:
* Return an index in the range of 0 through (CONFIG_SMP_NCPUS-1) that
* corresponds to the currently executing CPU.
*
* Input Parameters:
* None
*
* Returned Value:
* An integer index in the range of 0 through (CONFIG_SMP_NCPUS-1) that
* corresponds to the currently executing CPU.
*
****************************************************************************/
#define up_cpu_index() (0)
/****************************************************************************
* Inline functions
****************************************************************************/
/****************************************************************************
* Name: up_interrupt_context
*
* Description:
* Return true is we are currently executing in the interrupt
* handler context.
*
****************************************************************************/
#define up_interrupt_context() (g_current_regs != NULL)
#undef EXTERN
#ifdef __cplusplus
}

7
arch/renesas/src/common/up_internal.h
View file

@ -109,13 +109,6 @@ typedef void (*up_vector_t)(void);
****************************************************************************/
#ifndef __ASSEMBLY__
/* This holds a references to the current interrupt level
* register storage structure. If is non-NULL only during
* interrupt processing.
*/
extern volatile uint32_t *g_current_regs;
/* This is the beginning of heap as provided from up_head.S.
* This is the first address in DRAM after the loaded
* program+bss+idle stack. The end of the heap is

55
arch/renesas/src/common/up_interruptcontext.c
View file

@ -1,55 +0,0 @@
/****************************************************************************
* arch/renesas/src/common/up_interruptcontext.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdbool.h>
#include <nuttx/arch.h>
#include <nuttx/irq.h>
#include "up_internal.h"
/****************************************************************************
* Private Types
****************************************************************************/
/****************************************************************************
* Private Function Prototypes
****************************************************************************/
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: up_interrupt_context
*
* Description: Return true is we are currently executing in
* the interrupt handler context.
****************************************************************************/
bool up_interrupt_context(void)
{
return g_current_regs != NULL;
}

2
arch/renesas/src/m16c/Make.defs
View file

@ -22,7 +22,7 @@ HEAD_ASRC = m16c_head.S
CMN_CSRCS = up_allocateheap.c up_assert.c up_blocktask.c
CMN_CSRCS += up_createstack.c up_doirq.c up_exit.c up_idle.c up_initialize.c
CMN_CSRCS += up_interruptcontext.c up_lowputs.c up_mdelay.c up_puts.c
CMN_CSRCS += up_lowputs.c up_mdelay.c up_puts.c
CMN_CSRCS += up_releasepending.c up_releasestack.c up_reprioritizertr.c
CMN_CSRCS += up_stackframe.c up_udelay.c up_unblocktask.c up_usestack.c

4
arch/renesas/src/rx65n/Make.defs
View file

@ -22,7 +22,7 @@ HEAD_ASRC = rx65n_head.S
CMN_CSRCS = up_allocateheap.c up_assert.c up_blocktask.c
CMN_CSRCS += up_createstack.c up_doirq.c up_exit.c up_idle.c up_initialize.c
CMN_CSRCS += up_interruptcontext.c up_lowputs.c up_mdelay.c up_puts.c
CMN_CSRCS += up_lowputs.c up_mdelay.c up_puts.c
CMN_CSRCS += up_releasepending.c up_releasestack.c up_reprioritizertr.c
CMN_CSRCS += up_stackframe.c up_udelay.c up_unblocktask.c up_usestack.c
@ -62,4 +62,4 @@ endif
ifeq ($(CONFIG_RX65N_DTC),y)
CHIP_CSRCS += rx65n_dtc.c
endif
endif

2
arch/renesas/src/sh1/Make.defs
View file

@ -22,7 +22,7 @@ HEAD_ASRC = sh1_head.S
CMN_CSRCS = up_allocateheap.c up_assert.c up_blocktask.c
CMN_CSRCS += up_createstack.c up_doirq.c up_exit.c up_idle.c up_initialize.c
CMN_CSRCS += up_initialstate.c up_interruptcontext.c up_lowputs.c
CMN_CSRCS += up_initialstate.c up_lowputs.c
CMN_CSRCS += up_mdelay.c up_puts.c up_releasepending.c up_releasestack.c
CMN_CSRCS += up_reprioritizertr.c up_stackframe.c up_udelay.c
CMN_CSRCS += sh1_schedulesigaction.c sh1_sigdeliver.c

73
arch/risc-v/include/irq.h
View file

@ -581,6 +581,55 @@ extern "C"
#define EXTERN extern
#endif
/* g_current_regs[] holds a references to the current interrupt level
* register storage structure. If is non-NULL only during interrupt
* processing. Access to g_current_regs[] must be through the macro
* CURRENT_REGS for portability.
*/
/* For the case of architectures with multiple CPUs, then there must be one
* such value for each processor that can receive an interrupt.
*/
EXTERN volatile uintptr_t *g_current_regs[CONFIG_SMP_NCPUS];
#define CURRENT_REGS (g_current_regs[up_cpu_index()])
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: up_irq_enable
*
* Description:
* Return the current interrupt state and enable interrupts
*
****************************************************************************/
irqstate_t up_irq_enable(void);
/****************************************************************************
* Name: up_cpu_index
*
* Description:
* Return an index in the range of 0 through (CONFIG_SMP_NCPUS-1) that
* corresponds to the currently executing CPU.
*
* Input Parameters:
* None
*
* Returned Value:
* An integer index in the range of 0 through (CONFIG_SMP_NCPUS-1) that
* corresponds to the currently executing CPU.
*
****************************************************************************/
#ifdef CONFIG_SMP
int up_cpu_index(void);
#else
# define up_cpu_index() (0)
#endif
/****************************************************************************
* Inline Functions
****************************************************************************/
@ -634,18 +683,28 @@ static inline void up_irq_restore(irqstate_t flags)
}
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: up_irq_enable
* Name: up_interrupt_context
*
* Description:
* Return the current interrupt state and enable interrupts
* Return true is we are currently executing in the interrupt
* handler context.
*
****************************************************************************/
EXTERN irqstate_t up_irq_enable(void);
static inline bool up_interrupt_context(void)
{
#ifdef CONFIG_SMP
irqstate_t flags = up_irq_save();
#endif
bool ret = CURRENT_REGS != NULL;
#ifdef CONFIG_SMP
up_irq_restore(flags);
#endif
return ret;
}
#undef EXTERN
#if defined(__cplusplus)

2
arch/risc-v/src/bl602/Make.defs
View file

@ -29,7 +29,7 @@ CMN_ASRCS += riscv_vectors.S riscv_testset.S riscv_exception_common.S
CMN_CSRCS += riscv_initialize.c riscv_swint.c
CMN_CSRCS += riscv_createstack.c riscv_exit.c
CMN_CSRCS += riscv_assert.c riscv_blocktask.c riscv_copystate.c riscv_initialstate.c
CMN_CSRCS += riscv_interruptcontext.c riscv_modifyreg32.c riscv_puts.c riscv_mdelay.c
CMN_CSRCS += riscv_modifyreg32.c riscv_puts.c riscv_mdelay.c
CMN_CSRCS += riscv_releasepending.c riscv_reprioritizertr.c
CMN_CSRCS += riscv_releasestack.c riscv_stackframe.c riscv_schedulesigaction.c
CMN_CSRCS += riscv_sigdeliver.c riscv_udelay.c riscv_unblocktask.c riscv_usestack.c

2
arch/risc-v/src/c906/Make.defs
View file

@ -29,7 +29,7 @@ CMN_ASRCS += riscv_vectors.S riscv_testset.S riscv_exception_common.S
CMN_CSRCS += riscv_initialize.c riscv_swint.c
CMN_CSRCS += riscv_createstack.c riscv_exit.c riscv_exception.c
CMN_CSRCS += riscv_assert.c riscv_blocktask.c riscv_copystate.c riscv_initialstate.c
CMN_CSRCS += riscv_interruptcontext.c riscv_modifyreg32.c riscv_puts.c
CMN_CSRCS += riscv_modifyreg32.c riscv_puts.c
CMN_CSRCS += riscv_releasepending.c riscv_reprioritizertr.c
CMN_CSRCS += riscv_releasestack.c riscv_stackframe.c riscv_schedulesigaction.c
CMN_CSRCS += riscv_sigdeliver.c riscv_unblocktask.c riscv_usestack.c

2
arch/risc-v/src/common/riscv_internal.h
View file

@ -165,8 +165,6 @@ extern "C"
#endif
#ifndef __ASSEMBLY__
EXTERN volatile uintptr_t *g_current_regs[CONFIG_SMP_NCPUS];
#define CURRENT_REGS (g_current_regs[up_cpu_index()])
EXTERN uintptr_t g_idle_topstack;
/* Address of per-cpu idle stack base */

69
arch/risc-v/src/common/riscv_interruptcontext.c
View file

@ -1,69 +0,0 @@
/****************************************************************************
* arch/risc-v/src/common/riscv_interruptcontext.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdbool.h>
#include <nuttx/arch.h>
#include <nuttx/irq.h>
#include "riscv_internal.h"
/****************************************************************************
* Private Types
****************************************************************************/
/****************************************************************************
* Private Function Prototypes
****************************************************************************/
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: up_interrupt_context
*
* Description: Return true is we are currently executing in
* the interrupt handler context.
****************************************************************************/
bool up_interrupt_context(void)
{
#ifdef CONFIG_ARCH_RV64
#ifdef CONFIG_SMP
irqstate_t flags = up_irq_save();
#endif
bool ret = CURRENT_REGS != NULL;
#ifdef CONFIG_SMP
up_irq_restore(flags);
#endif
return ret;
#else
return CURRENT_REGS != NULL;
#endif
}

2
arch/risc-v/src/esp32c3/Make.defs
View file

@ -36,7 +36,7 @@ CMN_ASRCS = riscv_exception_common.S
CMN_CSRCS += riscv_initialize.c riscv_swint.c
CMN_CSRCS += riscv_allocateheap.c riscv_createstack.c riscv_exit.c riscv_exception.c
CMN_CSRCS += riscv_assert.c riscv_blocktask.c riscv_copystate.c riscv_initialstate.c
CMN_CSRCS += riscv_interruptcontext.c riscv_modifyreg32.c riscv_puts.c riscv_mdelay.c
CMN_CSRCS += riscv_modifyreg32.c riscv_puts.c riscv_mdelay.c
CMN_CSRCS += riscv_releasepending.c riscv_reprioritizertr.c
CMN_CSRCS += riscv_releasestack.c riscv_stackframe.c riscv_schedulesigaction.c
CMN_CSRCS += riscv_sigdeliver.c riscv_udelay.c riscv_unblocktask.c riscv_usestack.c

2
arch/risc-v/src/fe310/Make.defs
View file

@ -29,7 +29,7 @@ CMN_ASRCS += riscv_vectors.S riscv_testset.S riscv_exception_common.S
CMN_CSRCS += riscv_initialize.c riscv_swint.c riscv_exception.c riscv_mtimer.c
CMN_CSRCS += riscv_allocateheap.c riscv_createstack.c riscv_exit.c
CMN_CSRCS += riscv_assert.c riscv_blocktask.c riscv_copystate.c riscv_initialstate.c
CMN_CSRCS += riscv_interruptcontext.c riscv_modifyreg32.c riscv_puts.c riscv_mdelay.c
CMN_CSRCS += riscv_modifyreg32.c riscv_puts.c riscv_mdelay.c
CMN_CSRCS += riscv_releasepending.c riscv_reprioritizertr.c
CMN_CSRCS += riscv_releasestack.c riscv_stackframe.c riscv_schedulesigaction.c
CMN_CSRCS += riscv_sigdeliver.c riscv_udelay.c riscv_unblocktask.c riscv_usestack.c

2
arch/risc-v/src/k210/Make.defs
View file

@ -29,7 +29,7 @@ CMN_ASRCS += riscv_vectors.S riscv_testset.S riscv_exception_common.S
CMN_CSRCS += riscv_initialize.c riscv_swint.c riscv_mtimer.c
CMN_CSRCS += riscv_createstack.c riscv_exit.c riscv_exception.c
CMN_CSRCS += riscv_assert.c riscv_blocktask.c riscv_copystate.c riscv_initialstate.c
CMN_CSRCS += riscv_interruptcontext.c riscv_modifyreg32.c riscv_puts.c
CMN_CSRCS += riscv_modifyreg32.c riscv_puts.c
CMN_CSRCS += riscv_releasepending.c riscv_reprioritizertr.c
CMN_CSRCS += riscv_releasestack.c riscv_stackframe.c riscv_schedulesigaction.c
CMN_CSRCS += riscv_sigdeliver.c riscv_unblocktask.c riscv_usestack.c

2
arch/risc-v/src/litex/Make.defs
View file

@ -29,7 +29,7 @@ CMN_ASRCS += riscv_vectors.S riscv_testset.S riscv_exception_common.S
CMN_CSRCS += riscv_initialize.c riscv_swint.c riscv_doirq.c riscv_exception.c
CMN_CSRCS += riscv_allocateheap.c riscv_createstack.c riscv_exit.c
CMN_CSRCS += riscv_assert.c riscv_blocktask.c riscv_copystate.c riscv_initialstate.c
CMN_CSRCS += riscv_interruptcontext.c riscv_modifyreg32.c riscv_puts.c riscv_mdelay.c
CMN_CSRCS += riscv_modifyreg32.c riscv_puts.c riscv_mdelay.c
CMN_CSRCS += riscv_releasepending.c riscv_reprioritizertr.c
CMN_CSRCS += riscv_releasestack.c riscv_stackframe.c riscv_schedulesigaction.c
CMN_CSRCS += riscv_sigdeliver.c riscv_udelay.c riscv_unblocktask.c riscv_usestack.c

2
arch/risc-v/src/mpfs/Make.defs
View file

@ -36,7 +36,7 @@ endif
CMN_CSRCS += riscv_initialize.c riscv_swint.c
CMN_CSRCS += riscv_createstack.c riscv_exit.c riscv_exception.c
CMN_CSRCS += riscv_assert.c riscv_blocktask.c riscv_copystate.c riscv_initialstate.c
CMN_CSRCS += riscv_interruptcontext.c riscv_modifyreg32.c riscv_puts.c
CMN_CSRCS += riscv_modifyreg32.c riscv_puts.c
CMN_CSRCS += riscv_releasepending.c riscv_reprioritizertr.c
CMN_CSRCS += riscv_releasestack.c riscv_stackframe.c riscv_schedulesigaction.c
CMN_CSRCS += riscv_sigdeliver.c riscv_unblocktask.c riscv_usestack.c

2
arch/risc-v/src/qemu-rv/Make.defs
View file

@ -33,7 +33,7 @@ CMN_ASRCS += riscv_vectors.S riscv_exception_common.S
CMN_CSRCS += riscv_initialize.c riscv_swint.c riscv_mtimer.c
CMN_CSRCS += riscv_allocateheap.c riscv_createstack.c riscv_exit.c
CMN_CSRCS += riscv_assert.c riscv_blocktask.c riscv_copystate.c riscv_initialstate.c
CMN_CSRCS += riscv_interruptcontext.c riscv_modifyreg32.c riscv_puts.c
CMN_CSRCS += riscv_modifyreg32.c riscv_puts.c
CMN_CSRCS += riscv_releasepending.c riscv_reprioritizertr.c
CMN_CSRCS += riscv_releasestack.c riscv_stackframe.c riscv_schedulesigaction.c
CMN_CSRCS += riscv_sigdeliver.c riscv_unblocktask.c riscv_usestack.c

2
arch/risc-v/src/rv32m1/Make.defs
View file

@ -29,7 +29,7 @@ CMN_ASRCS = riscv_vectors.S
CMN_CSRCS += riscv_initialize.c riscv_swint.c riscv_doirq.c riscv_exception.c
CMN_CSRCS += riscv_allocateheap.c riscv_createstack.c riscv_exit.c
CMN_CSRCS += riscv_assert.c riscv_blocktask.c riscv_copystate.c riscv_initialstate.c
CMN_CSRCS += riscv_interruptcontext.c riscv_modifyreg32.c riscv_puts.c
CMN_CSRCS += riscv_modifyreg32.c riscv_puts.c
CMN_CSRCS += riscv_releasepending.c riscv_reprioritizertr.c
CMN_CSRCS += riscv_releasestack.c riscv_stackframe.c riscv_schedulesigaction.c
CMN_CSRCS += riscv_sigdeliver.c riscv_unblocktask.c riscv_usestack.c

36
arch/sim/include/irq.h
View file

@ -30,6 +30,9 @@
****************************************************************************/
#include <arch/setjmp.h>
#ifndef __ASSEMBLY__
# include <stdbool.h>
#endif
/****************************************************************************
* Pre-processor Definitions
@ -66,6 +69,28 @@ extern "C"
#define EXTERN extern
#endif
/****************************************************************************
* Name: up_cpu_index
*
* Description:
* Return an index in the range of 0 through (CONFIG_SMP_NCPUS-1) that
* corresponds to the currently executing CPU.
*
* Input Parameters:
* None
*
* Returned Value:
* An integer index in the range of 0 through (CONFIG_SMP_NCPUS-1) that
* corresponds to the currently executing CPU.
*
****************************************************************************/
#ifdef CONFIG_SMP
int up_cpu_index(void);
#else
# define up_cpu_index() (0)
#endif
/* Name: up_irq_save, up_irq_restore, and friends.
*
* NOTE: These functions should never be called from application code and,
@ -78,6 +103,17 @@ extern "C"
irqstate_t up_irq_save(void);
void up_irq_restore(irqstate_t flags);
/****************************************************************************
* Name: up_interrupt_context
*
* Description:
* Return true is we are currently executing in the interrupt
* handler context.
*
****************************************************************************/
bool up_interrupt_context(void);
#undef EXTERN
#ifdef __cplusplus
}

68
arch/sparc/include/irq.h
View file

@ -29,6 +29,11 @@
* Included Files
****************************************************************************/
#include <sys/types.h>
#ifndef __ASSEMBLY__
# include <stdbool.h>
#endif
/* Include NuttX-specific IRQ definitions */
#include <nuttx/irq.h>
@ -55,18 +60,6 @@
#ifndef __ASSEMBLY__
/****************************************************************************
* Inline functions
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
#ifdef __cplusplus
#define EXTERN extern "C"
extern "C"
@ -75,6 +68,57 @@ extern "C"
#define EXTERN extern
#endif
/****************************************************************************
* Public Data
****************************************************************************/
/* This holds a references to the current interrupt level register storage
* structure. If is non-NULL only during interrupt processing.
*/
EXTERN volatile uint32_t *g_current_regs;
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: up_cpu_index
*
* Description:
* Return an index in the range of 0 through (CONFIG_SMP_NCPUS-1) that
* corresponds to the currently executing CPU.
*
* Input Parameters:
* None
*
* Returned Value:
* An integer index in the range of 0 through (CONFIG_SMP_NCPUS-1) that
* corresponds to the currently executing CPU.
*
****************************************************************************/
#define up_cpu_index() (0)
/****************************************************************************
* Inline functions
****************************************************************************/
/****************************************************************************
* Name: up_interrupt_context
*
* Description:
* Return true is we are currently executing in the interrupt
* handler context.
*
****************************************************************************/
#define up_interrupt_context() (g_current_regs != NULL)
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
#undef EXTERN
#ifdef __cplusplus
}

2
arch/sparc/src/bm3803/Make.defs
View file

@ -27,7 +27,7 @@ HEAD_ASRC = bm3803_head.S
CMN_ASRCS = up_syscall.S
CMN_CSRCS = up_allocateheap.c up_assert.c up_blocktask.c up_copystate.c up_systemreset.c
CMN_CSRCS += up_createstack.c up_doirq.c up_exit.c up_idle.c up_initialize.c
CMN_CSRCS += up_initialstate.c up_interruptcontext.c up_irq.c up_lowputs.c
CMN_CSRCS += up_initialstate.c up_irq.c up_lowputs.c
CMN_CSRCS += up_mdelay.c up_modifyreg8.c up_modifyreg16.c up_modifyreg32.c
CMN_CSRCS += up_puts.c up_releasepending.c up_releasestack.c
CMN_CSRCS += up_reprioritizertr.c up_schedulesigaction.c up_sigdeliver.c

2
arch/sparc/src/bm3823/Make.defs
View file

@ -27,7 +27,7 @@ HEAD_ASRC = bm3823_head.S
CMN_ASRCS = up_syscall.S
CMN_CSRCS = up_allocateheap.c up_assert.c up_blocktask.c up_copystate.c
CMN_CSRCS += up_createstack.c up_doirq.c up_exit.c up_idle.c up_initialize.c
CMN_CSRCS += up_initialstate.c up_interruptcontext.c up_irq.c up_lowputs.c
CMN_CSRCS += up_initialstate.c up_irq.c up_lowputs.c
CMN_CSRCS += up_mdelay.c up_modifyreg8.c up_modifyreg16.c up_modifyreg32.c
CMN_CSRCS += up_puts.c up_releasepending.c up_releasestack.c
CMN_CSRCS += up_reprioritizertr.c up_schedulesigaction.c up_sigdeliver.c

6
arch/sparc/src/common/up_internal.h
View file

@ -120,12 +120,6 @@ typedef void (*up_vector_t)(void);
****************************************************************************/
#ifndef __ASSEMBLY__
/* This holds a references to the current interrupt level register storage
* structure. If is non-NULL only during interrupt processing.
*/
extern volatile uint32_t *g_current_regs;
/* This is the beginning of heap as provided from up_head.S. This is the
* first address in DRAM after the loaded program+bss+idle stack. The end
* of the heap is CONFIG_RAM_END

55
arch/sparc/src/common/up_interruptcontext.c
View file

@ -1,55 +0,0 @@
/****************************************************************************
* arch/sparc/src/common/up_interruptcontext.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdbool.h>
#include <nuttx/arch.h>
#include <nuttx/irq.h>
#include "up_internal.h"
/****************************************************************************
* Private Types
****************************************************************************/
/****************************************************************************
* Private Function Prototypes
****************************************************************************/
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: up_interrupt_context
*
* Description: Return true is we are currently executing in
* the interrupt handler context.
****************************************************************************/
bool up_interrupt_context(void)
{
return g_current_regs != NULL;
}

6
arch/sparc/src/sparc_v8/sparc_v8.h
View file

@ -54,12 +54,6 @@
****************************************************************************/
#ifndef __ASSEMBLY__
/* This holds a references to the current interrupt level register storage
* structure. If is non-NULL only during interrupt processing.
*/
extern volatile uint32_t *g_current_regs;
/* This is the beginning of heap as provided from up_head.S.This is the first
* address in DRAM after the loaded program+bss+idle stack. The end of the
* heap is CONFIG_RAM_END

63
arch/x86/include/irq.h
View file

@ -29,6 +29,10 @@
* Included Files
****************************************************************************/
#ifndef __ASSEMBLY__
# include <stddef.h>
#endif
/* Include NuttX-specific IRQ definitions */
#include <nuttx/irq.h>
@ -42,7 +46,7 @@
*/
#ifdef CONFIG_ARCH_I486
# include <arch/i486/irq.h>
# include <arch/i486/irq.h>
#endif
/****************************************************************************
@ -53,14 +57,6 @@
* Public Types
****************************************************************************/
/****************************************************************************
* Inline functions
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
@ -74,6 +70,55 @@ extern "C"
#define EXTERN extern
#endif
/****************************************************************************
* Public Data
****************************************************************************/
#ifndef __ASSEMBLY__
/* This holds a references to the current interrupt level register storage
* structure. If is non-NULL only during interrupt processing.
*/
EXTERN volatile uint32_t *g_current_regs;
#endif
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: up_cpu_index
*
* Description:
* Return an index in the range of 0 through (CONFIG_SMP_NCPUS-1) that
* corresponds to the currently executing CPU.
*
* Input Parameters:
* None
*
* Returned Value:
* An integer index in the range of 0 through (CONFIG_SMP_NCPUS-1) that
* corresponds to the currently executing CPU.
*
****************************************************************************/
#define up_cpu_index() (0)
/****************************************************************************
* Inline functions
****************************************************************************/
/****************************************************************************
* Name: up_interrupt_context
*
* Description:
* Return true is we are currently executing in the interrupt handler
* context.
*
****************************************************************************/
#define up_interrupt_context() (g_current_regs != NULL)
#undef EXTERN
#ifdef __cplusplus
}

6
arch/x86/src/common/up_internal.h
View file

@ -111,12 +111,6 @@ typedef void (*up_vector_t)(void);
****************************************************************************/
#ifndef __ASSEMBLY__
/* This holds a references to the current interrupt level register storage
* structure. If is non-NULL only during interrupt processing.
*/
extern volatile uint32_t *g_current_regs;
/* This is the beginning of heap as provided from up_head.S. This is the
* first address in DRAM after the loaded program+bss+idle stack. The end
* of the heap is CONFIG_RAM_END

57
arch/x86/src/common/up_interruptcontext.c
View file

@ -1,57 +0,0 @@
/****************************************************************************
* arch/x86/src/common/up_interruptcontext.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdbool.h>
#include <nuttx/arch.h>
#include <nuttx/irq.h>
#include "up_internal.h"
/****************************************************************************
* Private Types
****************************************************************************/
/****************************************************************************
* Private Function Prototypes
****************************************************************************/
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: up_interrupt_context
*
* Description:
* Return true is we are currently executing in the interrupt handler
* context.
*
****************************************************************************/
bool up_interrupt_context(void)
{
return g_current_regs != NULL;
}

2
arch/x86/src/qemu/Make.defs
View file

@ -27,7 +27,7 @@ HEAD_ASRC = qemu_head.S
CMN_ASRCS = i486_utils.S up_syscall6.S
CMN_CSRCS += up_allocateheap.c up_assert.c up_blocktask.c up_copystate.c
CMN_CSRCS += up_createstack.c up_mdelay.c up_udelay.c up_exit.c
CMN_CSRCS += up_initialize.c up_initialstate.c up_interruptcontext.c
CMN_CSRCS += up_initialize.c up_initialstate.c
CMN_CSRCS += up_irq.c up_modifyreg8.c up_modifyreg16.c up_modifyreg32.c
CMN_CSRCS += up_regdump.c up_releasepending.c up_releasestack.c
CMN_CSRCS += up_reprioritizertr.c up_savestate.c up_sigdeliver.c

45
arch/x86_64/include/irq.h
View file

@ -53,14 +53,18 @@
* Public Types
****************************************************************************/
/****************************************************************************
* Inline functions
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
#ifndef __ASSEMBLY__
/* This holds a references to the current interrupt level register storage
* structure. If is non-NULL only during interrupt processing.
*/
extern volatile uint64_t *g_current_regs;
#endif
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
@ -74,6 +78,39 @@ extern "C"
#define EXTERN extern
#endif
/****************************************************************************
* Name: up_cpu_index
*
* Description:
* Return an index in the range of 0 through (CONFIG_SMP_NCPUS-1) that
* corresponds to the currently executing CPU.
*
* Input Parameters:
* None
*
* Returned Value:
* An integer index in the range of 0 through (CONFIG_SMP_NCPUS-1) that
* corresponds to the currently executing CPU.
*
****************************************************************************/
#define up_cpu_index() (0)
/****************************************************************************
* Inline functions
****************************************************************************/
/****************************************************************************
* Name: up_interrupt_context
*
* Description:
* Return true is we are currently executing in the interrupt handler
* context.
*
****************************************************************************/
#define up_interrupt_context() (g_current_regs != NULL)
#undef EXTERN
#ifdef __cplusplus
}

5
arch/x86_64/src/common/up_internal.h
View file

@ -130,11 +130,6 @@ typedef void (*up_vector_t)(void);
****************************************************************************/
#ifndef __ASSEMBLY__
/* This holds a references to the current interrupt level register storage
* structure. If is non-NULL only during interrupt processing.
*/
extern volatile uint64_t *g_current_regs;
/* This is the beginning of heap as provided from up_head.S. This is the
* first address in DRAM after the loaded program+bss+idle stack. The

57
arch/x86_64/src/common/up_interruptcontext.c
View file

@ -1,57 +0,0 @@
/****************************************************************************
* arch/x86_64/src/common/up_interruptcontext.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdbool.h>
#include <nuttx/arch.h>
#include <nuttx/irq.h>
#include "up_internal.h"
/****************************************************************************
* Private Types
****************************************************************************/
/****************************************************************************
* Private Function Prototypes
****************************************************************************/
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: up_interrupt_context
*
* Description:
* Return true is we are currently executing in the interrupt handler
* context.
*
****************************************************************************/
bool up_interrupt_context(void)
{
return g_current_regs != NULL;
}

2
arch/x86_64/src/intel64/Make.defs
View file

@ -22,7 +22,7 @@
CMN_CSRCS += up_allocateheap.c up_assert.c up_blocktask.c up_copystate.c up_restore_auxstate.c
CMN_CSRCS += up_createstack.c up_mdelay.c up_udelay.c up_exit.c
CMN_CSRCS += up_initialize.c up_initialstate.c up_interruptcontext.c
CMN_CSRCS += up_initialize.c up_initialstate.c
CMN_CSRCS += up_irq.c up_modifyreg8.c up_modifyreg16.c up_modifyreg32.c
CMN_CSRCS += up_regdump.c up_releasepending.c up_releasestack.c
CMN_CSRCS += up_reprioritizertr.c up_savestate.c up_sigdeliver.c

76
arch/xtensa/include/irq.h
View file

@ -34,6 +34,11 @@
#include <nuttx/config.h>
#include <nuttx/irq.h>
#include <sys/types.h>
#ifndef __ASSEMBLY__
# include <stdbool.h>
#endif
#include <arch/types.h>
#include <arch/chip/tie.h>
#include <arch/chip/core-isa.h>
@ -317,10 +322,6 @@ static inline void xtensa_intclear(uint32_t mask)
);
}
/****************************************************************************
* Public Data
****************************************************************************/
#ifdef __cplusplus
#define EXTERN extern "C"
extern "C"
@ -329,6 +330,25 @@ extern "C"
#define EXTERN extern
#endif
/****************************************************************************
* Public Data
****************************************************************************/
#ifndef __ASSEMBLY__
/* g_current_regs[] holds a references to the current interrupt level
* register storage structure. If is non-NULL only during interrupt
* processing. Access to g_current_regs[] must be through the macro
* CURRENT_REGS for portability.
*/
/* For the case of architectures with multiple CPUs, then there must be one
* such value for each processor that can receive an interrupt.
*/
EXTERN volatile uint32_t *g_current_regs[CONFIG_SMP_NCPUS];
#define CURRENT_REGS (g_current_regs[up_cpu_index()])
#endif
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
@ -357,6 +377,54 @@ irqstate_t xtensa_enable_interrupts(irqstate_t mask);
irqstate_t xtensa_disable_interrupts(irqstate_t mask);
/****************************************************************************
* Name: up_cpu_index
*
* Description:
* Return an index in the range of 0 through (CONFIG_SMP_NCPUS-1) that
* corresponds to the currently executing CPU.
*
* Input Parameters:
* None
*
* Returned Value:
* An integer index in the range of 0 through (CONFIG_SMP_NCPUS-1) that
* corresponds to the currently executing CPU.
*
****************************************************************************/
#ifdef CONFIG_SMP
int up_cpu_index(void);
#else
# define up_cpu_index() (0)
#endif
/****************************************************************************
* Name: up_interrupt_context
*
* Description:
* Return true is we are currently executing in the interrupt
* handler context.
*
****************************************************************************/
#ifndef __ASSEMBLY__
static inline bool up_interrupt_context(void)
{
#ifdef CONFIG_SMP
irqstate_t flags = up_irq_save();
#endif
bool ret = CURRENT_REGS != NULL;
#ifdef CONFIG_SMP
up_irq_restore(flags);
#endif
return ret;
}
#endif
#undef EXTERN
#ifdef __cplusplus
}

13
arch/xtensa/src/common/xtensa.h
View file

@ -162,19 +162,6 @@
****************************************************************************/
#ifndef __ASSEMBLY__
/* g_current_regs[] holds a references to the current interrupt level
* register storage structure. If is non-NULL only during interrupt
* processing. Access to g_current_regs[] must be through the macro
* CURRENT_REGS for portability.
*/
/* For the case of architectures with multiple CPUs, then there must be one
* such value for each processor that can receive an interrupt.
*/
extern volatile uint32_t *g_current_regs[CONFIG_SMP_NCPUS];
#define CURRENT_REGS (g_current_regs[up_cpu_index()])
#if !defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 15
/* The (optional) interrupt stack */

58
arch/xtensa/src/common/xtensa_interruptcontext.c
View file

@ -1,58 +0,0 @@
/****************************************************************************
* arch/xtensa/src/common/xtensa_interruptcontext.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdbool.h>
#include <nuttx/arch.h>
#include <nuttx/irq.h>
#include "xtensa.h"
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: up_interrupt_context
*
* Description: Return true is we are currently executing in
* the interrupt handler context on this CPU.
*
****************************************************************************/
bool up_interrupt_context(void)
{
#ifdef CONFIG_SMP
irqstate_t flags = up_irq_save();
#endif
bool ret = CURRENT_REGS != NULL;
#ifdef CONFIG_SMP
up_irq_restore(flags);
#endif
return ret;
}

2
arch/xtensa/src/esp32/Make.defs
View file

@ -33,7 +33,7 @@ CMN_ASRCS += xtensa_sigtramp.S
CMN_CSRCS = xtensa_assert.c xtensa_blocktask.c
CMN_CSRCS += xtensa_cpenable.c xtensa_createstack.c xtensa_exit.c
CMN_CSRCS += xtensa_initialize.c xtensa_initialstate.c xtensa_interruptcontext.c
CMN_CSRCS += xtensa_initialize.c xtensa_initialstate.c
CMN_CSRCS += xtensa_irqdispatch.c xtensa_lowputs.c xtensa_mdelay.c
CMN_CSRCS += xtensa_modifyreg8.c xtensa_modifyreg16.c xtensa_modifyreg32.c
CMN_CSRCS += xtensa_puts.c xtensa_releasepending.c xtensa_releasestack.c

2
arch/xtensa/src/esp32s2/Make.defs
View file

@ -33,7 +33,7 @@ CMN_ASRCS += xtensa_sigtramp.S
CMN_CSRCS = xtensa_assert.c xtensa_blocktask.c
CMN_CSRCS += xtensa_cpenable.c xtensa_createstack.c xtensa_exit.c
CMN_CSRCS += xtensa_initialize.c xtensa_initialstate.c xtensa_interruptcontext.c
CMN_CSRCS += xtensa_initialize.c xtensa_initialstate.c
CMN_CSRCS += xtensa_irqdispatch.c xtensa_lowputs.c xtensa_mdelay.c
CMN_CSRCS += xtensa_modifyreg8.c xtensa_modifyreg16.c xtensa_modifyreg32.c
CMN_CSRCS += xtensa_puts.c xtensa_releasepending.c xtensa_releasestack.c

2
arch/xtensa/src/esp32s3/Make.defs
View file

@ -33,7 +33,7 @@ CMN_ASRCS += xtensa_sigtramp.S
CMN_CSRCS = xtensa_assert.c xtensa_blocktask.c
CMN_CSRCS += xtensa_cpenable.c xtensa_createstack.c xtensa_exit.c
CMN_CSRCS += xtensa_initialize.c xtensa_initialstate.c xtensa_interruptcontext.c
CMN_CSRCS += xtensa_initialize.c xtensa_initialstate.c
CMN_CSRCS += xtensa_irqdispatch.c xtensa_lowputs.c xtensa_mdelay.c
CMN_CSRCS += xtensa_modifyreg8.c xtensa_modifyreg16.c xtensa_modifyreg32.c
CMN_CSRCS += xtensa_puts.c xtensa_releasepending.c xtensa_releasestack.c

55
arch/z16/include/irq.h
View file

@ -29,6 +29,11 @@
* Included Files
****************************************************************************/
#include <sys/types.h>
#ifndef __ASSEMBLY__
# include <stdbool.h>
#endif
#include <nuttx/irq.h>
#include <arch/chip/irq.h>
@ -57,6 +62,56 @@ extern "C"
#define EXTERN extern
#endif
/****************************************************************************
* Public Data
****************************************************************************/
#ifndef __ASSEMBLY__
/* This holds a references to the current interrupt level
* register storage structure. If is non-NULL only during
* interrupt processing.
*/
EXTERN volatile FAR chipreg_t *g_current_regs;
#endif
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: up_cpu_index
*
* Description:
* Return an index in the range of 0 through (CONFIG_SMP_NCPUS-1) that
* corresponds to the currently executing CPU.
*
* Input Parameters:
* None
*
* Returned Value:
* An integer index in the range of 0 through (CONFIG_SMP_NCPUS-1) that
* corresponds to the currently executing CPU.
*
****************************************************************************/
#define up_cpu_index() (0)
/****************************************************************************
* Inline functions
****************************************************************************/
/****************************************************************************
* Name: up_interrupt_context
*
* Description:
* Return true is we are currently executing in the interrupt
* handler context.
*
****************************************************************************/
#define up_interrupt_context() (g_current_regs != NULL)
#undef EXTERN
#ifdef __cplusplus
}

13
arch/z16/src/common/z16_internal.h
View file

@ -108,19 +108,6 @@
typedef void (*up_vector_t)(void);
#endif
/****************************************************************************
* Public Data
****************************************************************************/
#ifndef __ASSEMBLY__
/* This holds a references to the current interrupt level
* register storage structure. If is non-NULL only during
* interrupt processing.
*/
extern volatile FAR chipreg_t *g_current_regs;
#endif
/****************************************************************************
* Public Function Prototypes
****************************************************************************/

48
arch/z16/src/common/z16_interruptcontext.c
View file

@ -1,48 +0,0 @@
/****************************************************************************
* arch/z16/src/common/z16_interruptcontext.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <nuttx/arch.h>
#include <nuttx/irq.h>
#include "z16_internal.h"
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: up_interrupt_context
*
* Description: Return true is we are currently executing in
* the interrupt handler context.
****************************************************************************/
bool up_interrupt_context(void)
{
return g_current_regs != NULL;
}

2
arch/z16/src/z16f/Make.defs
View file

@ -22,7 +22,7 @@ HEAD_SSRC = z16f_head.S
CMN_CSRCS = z16_allocateheap.c z16_initialize.c z16_schedulesigaction.c
CMN_CSRCS += z16_assert.c z16_initialstate.c z16_sigdeliver.c z16_blocktask.c
CMN_CSRCS += z16_interruptcontext.c z16_stackdump.c z16_copystate.c
CMN_CSRCS += z16_stackdump.c z16_copystate.c
CMN_CSRCS += z16_mdelay.c z16_udelay.c z16_createstack.c z16_registerdump.c
CMN_CSRCS += z16_unblocktask.c z16_doirq.c z16_releasepending.c z16_usestack.c
CMN_CSRCS += z16_exit.c z16_releasestack.c z16_stackframe.c z16_idle.c

33
include/nuttx/arch.h
View file

@ -1449,17 +1449,6 @@ int up_shmdt(uintptr_t vaddr, unsigned int npages);
void up_irqinitialize(void);
/****************************************************************************
* Name: up_interrupt_context
*
* Description:
* Return true is we are currently executing in
* the interrupt handler context.
*
****************************************************************************/
bool up_interrupt_context(void);
/****************************************************************************
* Name: up_enable_irq
*
@ -1951,28 +1940,6 @@ int16_t up_fetchsub16(FAR volatile int16_t *addr, int16_t value);
int8_t up_fetchsub8(FAR volatile int8_t *addr, int8_t value);
#endif
/****************************************************************************
* Name: up_cpu_index
*
* Description:
* Return an index in the range of 0 through (CONFIG_SMP_NCPUS-1) that
* corresponds to the currently executing CPU.
*
* Input Parameters:
* None
*
* Returned Value:
* An integer index in the range of 0 through (CONFIG_SMP_NCPUS-1) that
* corresponds to the currently executing CPU.
*
****************************************************************************/
#ifdef CONFIG_SMP
int up_cpu_index(void);
#else
# define up_cpu_index() (0)
#endif
/****************************************************************************
* Name: up_cpu_idlestack
*