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use small lock in:
arch/arm/src/imxrt/imxrt_wdog.c arch/arm/src/kinetis/kinetis_edma.c arch/arm/src/lc823450/lc823450_dvfs2.c arch/arm/src/lc823450/lc823450_timer.c arch/arm/src/lpc54xx/lpc54_lowputc.c Signed-off-by: hujun5 <hujun5@xiaomi.com>
This commit is contained in:
hujun5
Xiang Xiao
parent
b3813bd450
commit
46c2d46a6b
6 changed files with 80 additions and 63 deletions
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@ -73,6 +73,7 @@ struct imxrt_wdog_lower
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const struct watchdog_ops_s *ops; /* Lower half operations */
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uint32_t timeout;
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uint32_t enabled;
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spinlock_t lock;
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};
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/****************************************************************************
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@ -239,12 +240,14 @@ static int imxrt_wdog_stop(struct watchdog_lowerhalf_s *lower)
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static int imxrt_wdog_keepalive(struct watchdog_lowerhalf_s *lower)
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{
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irqstate_t flags = spin_lock_irqsave(NULL);
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struct imxrt_wdog_lower *priv = (struct imxrt_wdog_lower *)lower;
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irqstate_t flags = spin_lock_irqsave(&priv->lock);
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putreg16(WDOG_KEEP_ALIVE_KEY1, IMXRT_WDOG1_WSR);
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putreg16(WDOG_KEEP_ALIVE_KEY2, IMXRT_WDOG1_WSR);
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spin_unlock_irqrestore(NULL, flags);
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spin_unlock_irqrestore(&priv->lock, flags);
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return OK;
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}
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@ -314,7 +317,7 @@ static int imxrt_wdog_settimeout(struct watchdog_lowerhalf_s *lower,
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priv->timeout = timeout;
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irqstate_t flags = spin_lock_irqsave(NULL);
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irqstate_t flags = spin_lock_irqsave(&priv->lock);
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/* write timer value to WCR WT register */
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@ -328,7 +331,7 @@ static int imxrt_wdog_settimeout(struct watchdog_lowerhalf_s *lower,
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putreg16(WDOG_KEEP_ALIVE_KEY1, IMXRT_WDOG1_WSR);
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putreg16(WDOG_KEEP_ALIVE_KEY2, IMXRT_WDOG1_WSR);
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spin_unlock_irqrestore(NULL, flags);
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spin_unlock_irqrestore(&priv->lock, flags);
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return OK;
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}
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@ -360,14 +363,14 @@ void imxrt_wdog_initialize(void)
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priv->ops = &g_wdgops;
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priv->timeout = WDOG_MIN;
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spin_lock_init(&g_wdgdev.lock);
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/* Register the watchdog driver at the path */
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wdinfo("Entry: devpath=%s\n", DEVPATH);
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watchdog_register(DEVPATH, (struct watchdog_lowerhalf_s *)priv);
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}
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#endif /* CONFIG_WATCHDOG && CONFIG_IMXRT_WDOG */
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/****************************************************************************
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* Name: imxrt_wdog_disable
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*
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@ -395,9 +398,11 @@ void imxrt_wdog_disable_all(void)
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putreg16(reg, IMXRT_WDOG2_WCR);
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}
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flags = enter_critical_section();
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flags = spin_lock_irqsave(&g_wdgdev.lock);
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putreg32(RTWDOG_UPDATE_KEY, IMXRT_RTWDOG_CNT);
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putreg32(0xffff, IMXRT_RTWDOG_TOVAL);
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modifyreg32(IMXRT_RTWDOG_CS, RTWDOG_CS_EN, RTWDOG_CS_UPDATE);
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leave_critical_section(flags);
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spin_unlock_irqrestore(&g_wdgdev.lock, flags);
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}
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#endif /* CONFIG_WATCHDOG && CONFIG_IMXRT_WDOG */
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@ -155,6 +155,7 @@ struct kinetis_edma_s
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static struct kinetis_edma_s g_edma =
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{
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.chlock = NXMUTEX_INITIALIZER,
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.lock = SP_UNLOCKED,
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#if CONFIG_KINETIS_EDMA_NTCD > 0
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.dsem = SEM_INITIALIZER(CONFIG_KINETIS_EDMA_NTCD),
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#endif
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@ -197,15 +198,16 @@ static struct kinetis_edmatcd_s *kinetis_tcd_alloc(void)
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* waiting.
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*/
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flags = enter_critical_section();
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nxsem_wait_uninterruptible(&g_edma.dsem);
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flags = spin_lock_irqsave(&g_edma.lock);
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/* Now there should be a TCD in the free list reserved just for us */
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tcd = (struct kinetis_edmatcd_s *)sq_remfirst(&g_tcd_free);
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DEBUGASSERT(tcd != NULL);
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leave_critical_section(flags);
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spin_unlock_irqrestore(&g_edma.lock, flags);
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return tcd;
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}
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#endif
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@ -219,6 +221,19 @@ static struct kinetis_edmatcd_s *kinetis_tcd_alloc(void)
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****************************************************************************/
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#if CONFIG_KINETIS_EDMA_NTCD > 0
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static void kinetis_tcd_free_nolock(struct kinetis_edmatcd_s *tcd)
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{
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irqstate_t flags;
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/* Add the the TCD to the end of the free list and post the 'dsem',
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* possibly waking up another thread that might be waiting for
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* a TCD.
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*/
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sq_addlast((sq_entry_t *)tcd, &g_tcd_free);
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nxsem_post(&g_edma.dsem);
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}
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static void kinetis_tcd_free(struct kinetis_edmatcd_s *tcd)
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{
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irqstate_t flags;
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@ -228,10 +243,11 @@ static void kinetis_tcd_free(struct kinetis_edmatcd_s *tcd)
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* a TCD.
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*/
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flags = spin_lock_irqsave(NULL);
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sq_addlast((sq_entry_t *)tcd, &g_tcd_free);
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nxsem_post(&g_edma.dsem);
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spin_unlock_irqrestore(NULL, flags);
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flags = spin_lock_irqsave(&g_edma.lock);
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sched_lock();
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kinetis_tcd_free_nolock(tcd);
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spin_unlock_irqrestore(&g_edma.lock, flags);
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sched_unlock();
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}
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#endif
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@ -435,9 +451,13 @@ static void kinetis_dmaterminate(struct kinetis_dmach_s *dmach, int result)
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struct kinetis_edmatcd_s *next;
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#endif
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uintptr_t regaddr;
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irqstate_t flags;
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uint8_t regval8;
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uint8_t chan;
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flags = spin_lock_irqsave(&g_edma.lock);
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sched_lock();
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/* Disable channel ERROR interrupts */
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chan = dmach->chan;
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@ -469,7 +489,7 @@ static void kinetis_dmaterminate(struct kinetis_dmach_s *dmach, int result)
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next = dmach->flags & EDMA_CONFIG_LOOPDEST ?
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NULL : (struct kinetis_edmatcd_s *)tcd->dlastsga;
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kinetis_tcd_free(tcd);
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kinetis_tcd_free_nolock(tcd);
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}
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dmach->head = NULL;
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@ -486,6 +506,9 @@ static void kinetis_dmaterminate(struct kinetis_dmach_s *dmach, int result)
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dmach->callback = NULL;
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dmach->arg = NULL;
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dmach->state = KINETIS_DMA_IDLE;
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spin_unlock_irqrestore(&g_edma.lock, flags);
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sched_unlock();
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}
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/****************************************************************************
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@ -1114,7 +1137,7 @@ int kinetis_dmach_start(DMACH_HANDLE handle, edma_callback_t callback,
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/* Save the callback info. This will be invoked when the DMA completes */
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flags = spin_lock_irqsave(NULL);
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flags = spin_lock_irqsave(&g_edma.lock);
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dmach->callback = callback;
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dmach->arg = arg;
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@ -1139,7 +1162,7 @@ int kinetis_dmach_start(DMACH_HANDLE handle, edma_callback_t callback,
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putreg8(regval8, KINETIS_EDMA_SERQ);
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}
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spin_unlock_irqrestore(NULL, flags);
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spin_unlock_irqrestore(&g_edma.lock, flags);
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return OK;
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}
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@ -1162,14 +1185,11 @@ int kinetis_dmach_start(DMACH_HANDLE handle, edma_callback_t callback,
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void kinetis_dmach_stop(DMACH_HANDLE handle)
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{
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struct kinetis_dmach_s *dmach = (struct kinetis_dmach_s *)handle;
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irqstate_t flags;
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dmainfo("dmach: %p\n", dmach);
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DEBUGASSERT(dmach != NULL);
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flags = spin_lock_irqsave(NULL);
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kinetis_dmaterminate(dmach, -EINTR);
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spin_unlock_irqrestore(NULL, flags);
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}
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/****************************************************************************
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@ -1267,7 +1287,7 @@ void kinetis_dmasample(DMACH_HANDLE handle, struct kinetis_dmaregs_s *regs)
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/* eDMA Global Registers */
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flags = spin_lock_irqsave(NULL);
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flags = spin_lock_irqsave(&g_edma.lock);
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regs->cr = getreg32(KINETIS_EDMA_CR); /* Control */
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regs->es = getreg32(KINETIS_EDMA_ES); /* Error Status */
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@ -1302,7 +1322,7 @@ void kinetis_dmasample(DMACH_HANDLE handle, struct kinetis_dmaregs_s *regs)
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regaddr = KINETIS_DMAMUX_CHCFG(chan);
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regs->dmamux = getreg32(regaddr); /* Channel configuration */
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spin_unlock_irqrestore(NULL, flags);
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spin_unlock_irqrestore(&g_edma.lock, flags);
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}
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#endif /* CONFIG_DEBUG_DMA */
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@ -68,6 +68,8 @@
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* Private Data
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****************************************************************************/
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static spinlock_t g_dvfs_lock = SP_UNLOCKED;
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typedef struct freq_entry
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{
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uint16_t freq;
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@ -428,7 +430,7 @@ static void lc823450_dvfs_do_auto(uint32_t idle[])
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void lc823450_dvfs_get_idletime(uint64_t idletime[])
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{
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irqstate_t flags = spin_lock_irqsave(NULL);
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irqstate_t flags = spin_lock_irqsave(&g_dvfs_lock);
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/* First, copy g_idle_totaltime to the caller */
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@ -448,7 +450,7 @@ void lc823450_dvfs_get_idletime(uint64_t idletime[])
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}
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#endif
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spin_unlock_irqrestore(NULL, flags);
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spin_unlock_irqrestore(&g_dvfs_lock, flags);
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}
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/****************************************************************************
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@ -504,7 +506,7 @@ void lc823450_dvfs_tick_callback(void)
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void lc823450_dvfs_enter_idle(void)
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{
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irqstate_t flags = spin_lock_irqsave(NULL);
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irqstate_t flags = spin_lock_irqsave(&g_dvfs_lock);
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int me = this_cpu();
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@ -544,7 +546,7 @@ void lc823450_dvfs_enter_idle(void)
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lc823450_dvfs_set_div(_dvfs_cur_idx, 1);
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exit_with_error:
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spin_unlock_irqrestore(NULL, flags);
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spin_unlock_irqrestore(&g_dvfs_lock, flags);
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}
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/****************************************************************************
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@ -554,7 +556,7 @@ exit_with_error:
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void lc823450_dvfs_exit_idle(int irq)
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{
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irqstate_t flags = spin_lock_irqsave(NULL);
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irqstate_t flags = spin_lock_irqsave(&g_dvfs_lock);
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int me = this_cpu();
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uint64_t d;
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@ -596,7 +598,7 @@ exit_with_error:
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_dvfs_cpu_is_active[me] = 1;
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spin_unlock_irqrestore(NULL, flags);
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spin_unlock_irqrestore(&g_dvfs_lock, flags);
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}
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/****************************************************************************
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@ -628,7 +630,7 @@ int lc823450_dvfs_set_freq(int freq)
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return -1;
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}
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flags = spin_lock_irqsave(NULL);
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flags = spin_lock_irqsave(&g_dvfs_lock);
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switch (freq)
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{
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@ -656,6 +658,6 @@ int lc823450_dvfs_set_freq(int freq)
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lc823450_dvfs_set_div(idx, 0);
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}
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spin_unlock_irqrestore(NULL, flags);
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spin_unlock_irqrestore(&g_dvfs_lock, flags);
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return ret;
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}
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@ -148,6 +148,8 @@ static void hrt_usleep_add(struct hrt_s *phrt);
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* Private Data
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****************************************************************************/
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static spinlock_t g_hrt_timer_queue_lock = SP_UNLOCKED;
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#ifdef CHECK_INTERVAL
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static bool _timer_val = true;
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#endif
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@ -185,7 +187,7 @@ static void hrt_queue_refresh(void)
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struct hrt_s *tmp;
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irqstate_t flags;
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flags = spin_lock_irqsave(NULL);
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flags = spin_lock_irqsave(&g_hrt_timer_queue_lock);
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elapsed = (uint64_t)getreg32(MT20CNT) * (1000 * 1000) * 10 / XT1OSC_CLK;
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for (pent = hrt_timer_queue.head; pent; pent = dq_next(pent))
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@ -204,9 +206,9 @@ cont:
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if (tmp->usec <= 0)
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{
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dq_rem(pent, &hrt_timer_queue);
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spin_unlock_irqrestore(NULL, flags);
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spin_unlock_irqrestore(&g_hrt_timer_queue_lock, flags);
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nxsem_post(&tmp->sem);
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flags = spin_lock_irqsave(NULL);
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flags = spin_lock_irqsave(&g_hrt_timer_queue_lock);
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goto cont;
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}
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else
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@ -215,7 +217,7 @@ cont:
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}
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}
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spin_unlock_irqrestore(NULL, flags);
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spin_unlock_irqrestore(&g_hrt_timer_queue_lock, flags);
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}
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#endif
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@ -230,7 +232,7 @@ static void hrt_usleep_setup(void)
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struct hrt_s *head;
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irqstate_t flags;
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flags = spin_lock_irqsave(NULL);
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flags = spin_lock_irqsave(&g_hrt_timer_queue_lock);
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head = container_of(hrt_timer_queue.head, struct hrt_s, ent);
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if (head == NULL)
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{
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@ -238,7 +240,7 @@ static void hrt_usleep_setup(void)
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modifyreg32(MCLKCNTEXT1, MCLKCNTEXT1_MTM2C_CLKEN, 0x0);
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modifyreg32(MCLKCNTEXT1, MCLKCNTEXT1_MTM2_CLKEN, 0x0);
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spin_unlock_irqrestore(NULL, flags);
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spin_unlock_irqrestore(&g_hrt_timer_queue_lock, flags);
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return;
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}
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@ -260,7 +262,7 @@ static void hrt_usleep_setup(void)
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/* Enable MTM2-Ch0 */
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putreg32(1, MT2OPR);
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spin_unlock_irqrestore(NULL, flags);
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spin_unlock_irqrestore(&g_hrt_timer_queue_lock, flags);
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}
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#endif
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@ -299,7 +301,7 @@ static void hrt_usleep_add(struct hrt_s *phrt)
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hrt_queue_refresh();
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flags = spin_lock_irqsave(NULL);
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flags = spin_lock_irqsave(&g_hrt_timer_queue_lock);
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/* add phrt to hrt_timer_queue */
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@ -321,7 +323,7 @@ static void hrt_usleep_add(struct hrt_s *phrt)
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dq_addlast(&phrt->ent, &hrt_timer_queue);
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}
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spin_unlock_irqrestore(NULL, flags);
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spin_unlock_irqrestore(&g_hrt_timer_queue_lock, flags);
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hrt_usleep_setup();
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}
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@ -699,7 +701,7 @@ int up_rtc_gettime(struct timespec *tp)
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irqstate_t flags;
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uint64_t f;
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flags = spin_lock_irqsave(NULL);
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flags = spin_lock_irqsave(&g_hrt_timer_queue_lock);
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/* Get the elapsed time */
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@ -710,7 +712,7 @@ int up_rtc_gettime(struct timespec *tp)
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f = up_get_timer_fraction();
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elapsed += f;
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spin_unlock_irqrestore(NULL, flags);
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spin_unlock_irqrestore(&g_hrt_timer_queue_lock, flags);
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tmrinfo("elapsed = %lld\n", elapsed);
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@ -244,6 +244,8 @@
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****************************************************************************/
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#ifdef HAVE_USART_CONSOLE
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static spinlock_t g_console_lock = SP_UNLOCKED;
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/* USART console configuration */
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static const struct uart_config_s g_console_config =
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@ -784,31 +786,17 @@ void arm_lowputc(char ch)
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#ifdef HAVE_USART_CONSOLE
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irqstate_t flags;
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for (; ; )
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{
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/* Wait for the transmit FIFO to be not full */
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/* Wait for the transmit FIFO to be not full */
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while ((getreg32(CONSOLE_BASE + LPC54_USART_FIFOSTAT_OFFSET) &
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USART_FIFOSTAT_TXNOTFULL) == 0)
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{
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}
|
||||
flags = spin_lock_irqsave(&g_console_lock);
|
||||
while ((getreg32(CONSOLE_BASE + LPC54_USART_FIFOSTAT_OFFSET) &
|
||||
USART_FIFOSTAT_TXNOTFULL) == 0);
|
||||
|
||||
/* Disable interrupts so that the fest test and the transmission are
|
||||
* atomic.
|
||||
*/
|
||||
/* Send the character */
|
||||
|
||||
flags = spin_lock_irqsave(NULL);
|
||||
if ((getreg32(CONSOLE_BASE + LPC54_USART_FIFOSTAT_OFFSET) &
|
||||
USART_FIFOSTAT_TXNOTFULL) != 0)
|
||||
{
|
||||
/* Send the character */
|
||||
putreg32((uint32_t)ch, CONSOLE_BASE + LPC54_USART_FIFOWR_OFFSET);
|
||||
|
||||
putreg32((uint32_t)ch, CONSOLE_BASE + LPC54_USART_FIFOWR_OFFSET);
|
||||
spin_unlock_irqrestore(NULL, flags);
|
||||
return;
|
||||
}
|
||||
spin_unlock_irqrestore(&g_console_lock, flags);
|
||||
|
||||
spin_unlock_irqrestore(NULL, flags);
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
|
|
|||
|
|
@ -119,7 +119,7 @@ static void gs2200m_irq_enable(void)
|
|||
{
|
||||
/* Check if irq has been asserted */
|
||||
|
||||
dready = gs2200m_dready(&g_gs2200m_lock);
|
||||
dready = gs2200m_dready(NULL);
|
||||
|
||||
/* NOTE: stm32 does not support level-triggered irq */
|
||||
|
||||
|
|
|
|||
Loading…
Reference in a new issue