nuttx/nuttx-mirror
1
2
Fork 0
mirror of https://github.com/apache/nuttx.git synced 2025-01-13 13:18:50 +08:00
Code Issues Projects Releases Packages Wiki Activity Actions

Merge remote-tracking branch 'origin/master' into composite

Browse source
This commit is contained in:
Gregory Nutt 2017-06-14 09:17:49 -06:00
commit 49cd279fc6
122 changed files with 10341 additions and 1336 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

4
ChangeLog
View file

@ -7917,7 +7917,7 @@
command line NxPlayer (2014-7-31).
* audio/audio.c: More debug output (2014-7-31).
* configs/sama5d3x-ek/README.txt: REAME update (2014-7-31).
* drivers/audio/wm8904.c: Was not saving i2s interface instance
* drivers/audio/wm8904.c: Was not saving I2S interface instance
(2014-7-31).
* sched/sem_wait.c: Use set_errno() and get_errno(). Direct access
inside the OS may not be supported in the future (2014-7-31).
@ -15307,7 +15307,7 @@
change the link state. From Sebastien Lorquet (2017-05-19).
* drivers/wireless/ieee80211: Add support for AP scanning. From Simon
Piriou (2017-05-21).
* drivers/audio: Add cs43l22 audio driver STM32F4: Add i2s driver.
* drivers/audio: Add cs43l22 audio driver STM32F4: Add I2S driver.
From Taras Drozdovsky (2017-05-21).
* This is based on a patch by Taras Drozdovsky. Basically, the delay
that was added during the integration of the CDC/ACM host driver was

223
Documentation/NuttShell.html
View file

@ -8,7 +8,7 @@
<tr align="center" bgcolor="#e4e4e4">
<td>
<h1><big><font color="#3c34ec"><i>NuttShell (NSH)</i></font></big></h1>
<p>Last Updated: April 5, 2017</p>
<p>Last Updated: June 13, 2017</p>
</td>
</tr>
</table>
@ -305,7 +305,7 @@
<tr>
<td><br></td>
<td>
<a href="#cmdmkfatfs">2.37 Create a FAT Filesystem (mkfatfs)</a>
<a href="#cmdmkfatfs">2.37 Create a FAT File System (mkfatfs)</a>
</td>
</tr>
<tr>
@ -335,7 +335,7 @@
<tr>
<td><br></td>
<td>
<a href="#cmdnfsmount">2.42 Mount an NFS file system (nfsmount)</a>
<a href="#cmdnfsmount">2.42 Mount an NFS File System (nfsmount)</a>
</td>
</tr>
<tr>
@ -619,9 +619,35 @@
NuttShell (NSH)
nsh&gt;
</pre></ul>
The greating may also include NuttX versioning information if you are using a versioned copy of NuttX.
The greeting may also include NuttX versioning information if you are using a versioned copy of NuttX.
<code>nsh&gt;</code> is the NSH prompt and indicates that you may enter a command from the console.
</p>
<p>
<a name="usbstartup"><b>USB console startup</b></a>.
When using a USB console, the start-up sequence differs a little: In this case, you are required to press <i>ENTER</i> three times. Then NSH prompt will appear as described above.
This is required for the following reasons:
</p>
<ol>
<li>
This assures that the USB connection is stable.
The USB connection may be made, broken, and re-established a few times if the USB cable is not yet fully seated.
Waiting for <i>ENTER</i> to be pressed three times assures that the connection is stable.
</li>
<li>
The establishment of the connection is two step process: First, the USB serial connection is made with the host PC. Then the application that uses the serial interface is started on the host.
When the serial connection is established on the host, the host operating system may send several <i>AT</i> modem commands to the host depending upon how the host serial port is configured.
By waiting for <i>ENTER</i> to be pressed three consecutive times, all of these modem commands will go to the bit-bucket and will not be interpreted as NSH command input.
</li>
<li>
Similarly, in the second step when the applications is started, there may be additional <i>AT</i> modem commands sent out the serial port.
Most serial terminal programs will do this unless they are specifically configured to suppress the modem command output.
Waiting for the <i>ENTER</i> input eliminates the invalid command errors from both (2) and (3).
</li>
<li>
Finally, if NSH did not wait for some positive indication that the serial terminal program is up and running, then the output of the NSH greeting and initial NSH prompt would be lost.
</li>
</ol>
<p>
<a name="cle"><b>Extended Command Line Editing</b></a>.
By default, NuttX uses a simple command line editor that allows command entry after the <code>nsh&gt;</code> and supports only the <i>backspace</i> key for editing.
@ -752,7 +778,7 @@ nsh&gt;
<td><code>&lt;file&gt;</code></td>
<td>
is the full or relative path to any writable object
in the filesystem name space (file or character driver).
in the file system name space (file or character driver).
Such objects will be referred to simply as files throughout
this document.
</td>
@ -779,7 +805,7 @@ nsh&gt;
<p>
<b>Optional Syntax Extensions</b>
Because these features commit significant resources, it is disabled by default.
Because these features commit significant resources, they are disabled by default.
</p>
<ul>
<li>
@ -804,7 +830,7 @@ set BAR 123
set FOOBAR ABC_${FOO}_${BAR}
</pre></ul>
would set the environment variable <code>FOO</code> to <code>XYZ</code>, <code>BAR</code> to <code>123</code> and <code>FOOBAR</code> to <code>ABC_XYZ_123</code>.
If <code>CONFIG_NSH_ARGCAT</code> is not selected, then a slightly small FLASH footprint results but then also only simple environment variables like <code>$FOO</code> can be used on the command line.
If <code>CONFIG_NSH_ARGCAT</code> is not selected, then a slightly smaller FLASH footprint results but then also only simple environment variables like <code>$FOO</code> can be used on the command line.
</li>
</ul>
@ -820,7 +846,7 @@ set FOOBAR ABC_${FOO}_${BAR}
An <code>if-then[-else]-fi</code> construct is also supported in order to
support conditional execution of commands. This works from the
command line but is primarily intended for use within NSH scripts
(see the <a href="#cmdsh"><code>sh</code></a> commnd). The syntax is as follows:
(see the <a href="#cmdsh"><code>sh</code></a> command). The syntax is as follows:
</p>
<ul><pre>
if &lt;cmd&gt;
@ -968,7 +994,7 @@ done
<ul>
<li>
NSH will create a read-only RAM disk (a ROM disk), containing a tiny
ROMFS filesystem containing the following:
ROMFS file system containing the following:
<ul><pre>
`--init.d/
`-- rcS
@ -976,7 +1002,7 @@ done
Where rcS is the NSH start-up script.
</li>
<li>
NSH will then mount the ROMFS filesystem at <code>/etc</code>, resulting in:
NSH will then mount the ROMFS file system at <code>/etc</code>, resulting in:
<ul><pre>
|--dev/
| `-- ram0
@ -1058,7 +1084,7 @@ mount -t vfat /dev/ram1 /tmp
All of the startup-behavior is contained in <code>rcS.template</code>. The
role of <code>mkromfsimg.sh</code> is to (1) apply the specific configuration
settings to <code>rcS.template</code> to create the final <code>rcS</code>, and (2) to
generate the header file <code>nsh_romfsimg.h</code> containg the ROMFS
generate the header file <code>nsh_romfsimg.h</code> containing the ROMFS
file system image.
</p>
@ -1139,7 +1165,7 @@ addroute &lt;target&gt; &lt;netmask&gt; &lt;router&gt;
<p>
<b>Synopsis</b>.
This command adds an entry in the routing table.
The new entry will map the IP address of a router on a local network(&lt;router&gt;) to an external network characterized by the &lt;target&gt; IP address and a network mask &lt;netmask&gt;
The new entry will map the IP address of a router on a local network (&lt;router&gt;) to an external network characterized by the &lt;target&gt; IP address and a network mask &lt;netmask&gt;
</p>
<p>
<b>Example:</b>
@ -1274,7 +1300,7 @@ cat <code>&lt;path&gt;</code> [<code>&lt;path&gt;</code> [<code>&lt;path&gt;</co
</pre></ul>
<p>
<b>Synopsis</b>.
This command copies and concatentates all of the files at <code>&lt;path&gt;</code>
This command copies and concatenates all of the files at <code>&lt;path&gt;</code>
to the console (or to another file if the output is redirected).
</p>
@ -1352,7 +1378,7 @@ cp &lt;source-path&gt; &lt;dest-path&gt;
<p>
<b>Synopsis</b>.
Copy of the contents of the file at <code>&lt;source-path&gt;</code> to the location
in the filesystem indicated by <code>&lt;dest-path&gt;</code>.
in the file system indicated by <code>&lt;dest-path&gt;</code>.
</p>
<table width ="100%">
@ -1425,7 +1451,7 @@ nsh&gt; dd if=/dev/zero of=/dev/ram0
</pre></ul>
</li>
<li>
Read from a block devic, write to a character device. This
Read from a block device, write to a character device. This
will read the entire block device and dump the contents in
the bit bucket.
</li>
@ -1564,7 +1590,7 @@ exit
<b>Synopsis</b>.
Exit NSH. Only useful for the serial front end if you have started some other tasks (perhaps
using the <code><a href="#cmdexec">exec</a></code> command) and you would like to have NSH out of the
way. For the telnet front-end, <code>exit</code> terminates the telenet session.
way. For the telnet front-end, <code>exit</code> terminates the telnet session.
</p>
<table width ="100%">
@ -1638,7 +1664,7 @@ get [-b|-n] [-f &lt;local-path&gt;] -h &lt;ip-address&gt; &lt;remote-path&gt;
<tr>
<td><b><code>-b|-n</code></b></td>
<td>
Selects either binary (&quot;octet&quot;) or test (&quot;netascii&quot;) transfer
Selects either binary (&quot;octet&quot;) or text (&quot;netascii&quot;) transfer
mode. Default: text.
</td>
</tr>
@ -1686,12 +1712,25 @@ help [-v] [&lt;cmd&gt;]
<p><b>Command Syntax:</b></p>
<ul><pre>
hexdump &lt;file or device&gt;
hexdump &lt;file or device&gt; [skip=&lt;bytes&gt;] [count=&lt;bytes&gt;]
</pre></ul>
<p>
<b>Synopsis</b>.
Dump data in hexadecimal format from a file or character device.
</p>
<ul><table>
<tr>
<td><b><code>skip=&lt;bytes&gt;</code></b></td>
<td>Will skip <code>&lt;bytes&gt;</code> number of bytes from the beginning.
</tr>
<tr>
<td><b><code>count=&lt;bytes&gt;</code></b></td>
<td>Will stop after dumping <code>&lt;bytes&gt;</code> number of bytes.
</tr>
</table></ul>
<p>
The <code>skip</code> and <code>count</code> options are only available if <code>CONFIG_NSH_CMDOPT_HEXDUMP</code> is defined in the NuttX configuration.
</p>
<table width ="100%">
<tr bgcolor="#e4e4e4">
@ -1707,13 +1746,13 @@ ifconfig [nic_name [&lt;ip-address&gt;|dhcp]] [dr|gw|gateway &lt;dr-address&gt;]
</pre></ul>
<p>
<b>Synopsis</b>.
Multiple forms of the <code>ifconfig</code>command are supported:
Multiple forms of the <code>ifconfig</code> command are supported:
</p>
<ol>
<li>
<p>
With one or no arguments, <code>ifconfig</code> will shows the
current configuration of the network and, perhaps, the status of ethernet
current configuration of the network and, perhaps, the status of Ethernet
device:
</p>
<ul><pre>
@ -1736,7 +1775,7 @@ eth0 HWaddr 00:18:11:80:10:06
<li>
<p>
If both the network interface name and an IP address are supplied as arguments,
then <code>ifconfig</code> will set the address of the ethernet device:
then <code>ifconfig</code> will set the address of the Ethernet device:
</p>
<ul><pre>
ifconfig nic_name ip_address
@ -1880,7 +1919,7 @@ nsh&gt;
<p><small>
<b>NOTE</b>:
NuttX does not support a FULL POSIX signalling system.
Standard signals like SIGCHLD, SIGINTR, SIGKILL, etc. do not exist in NuttX and sending those signal may not have the result that you expect.
Standard signals like SIGCHLD, SIGINTR, SIGKILL, etc. do not exist in NuttX and sending those signals may not have the result that you expect.
Rather, NuttX supports only what are referred to as POSIX real-time signals.
These signals may be used to communicate with running tasks, may be use to waiting waiting tasks, etc.
But, as an example, <code>kill -9</code> (SIGKILL) will not terminate a task.
@ -1942,22 +1981,22 @@ losetup d &lt;dev-path&gt;
<table width ="100%">
<tr bgcolor="#e4e4e4">
<td>
<a name="cmdln"><h2>2.30 List to a File or Directory (ln)</h2></a>
<a name="cmdln"><h2>2.30 Link to a File or Directory (ln)</h2></a>
</td>
</tr>
</table>
<p><b>Command Syntax:</b></p>
<ul><pre>
link [-s] &lt;target&gt; &lt;link&gt;
ln [-s] &lt;target&gt; &lt;link&gt;
</pre></ul>
<p>
<b>Synopsis</b>.
The <code>link</code> command will create a new symbolic link at &lt;link&gt; for the existing file or directory, &lt;target&gt;.
This implementation is simplied for use with NuttX in these ways:
The <code>ln</code> command will create a new symbolic link at &lt;link&gt; for the existing file or directory, &lt;target&gt;.
This implementation is simplified for use with NuttX in these ways:
</p>
<ul>
<li>Links may be created only within the NuttX top-level, pseudo file system.
<li>Links may be created only within the NuttX top-level, <a href="NuttxUserGuide.html#FileSystemOverview"><i>pseudo</i> file system</a>.
No file system currently supported by NuttX provides symbolic links.</li>
<li>For the same reason, only soft links are implemented.</li>
<li>File privileges are ignored.</li>
@ -1979,7 +2018,7 @@ ls [-lRs] &lt;dir-path&gt;
<p>
<b>Synopsis</b>.
Show the contents of the directory at <code>&lt;dir-path&gt;</code>. NOTE:
<code>&lt;dir-path&gt;</code> must refer to a directory and no other filesystem
<code>&lt;dir-path&gt;</code> must refer to a directory and no other file system
object.
</p>
<p><b>Options:</b></p>
@ -2073,20 +2112,19 @@ mw &lt;hex-address&gt;[=&lt;hex-value&gt;][ &lt;hex-byte-count&gt;]
</p>
<ul><table>
<tr>
<td><code>&lt;hex-address&gt;</code>.</td>
<td><code>&lt;hex-address&gt;</code></td>
<td>Specifies the address to be accessed. The current
value at that address will always be read and displayed.
</tr>
<tr>
<td><code>&lt;hex-address&gt;=&lt;hex-value&gt;</code>.</td>
<td><code>&lt;hex-address&gt;=&lt;hex-value&gt;</code></td>
<td>Read the value, then write <code>&lt;hex-value&gt;</code>
to the location.
</tr>
<tr>
<td><code>&lt;hex-byte-count&gt;</code>.</td>
<td><code>&lt;hex-byte-count&gt;</code></td>
<td>Perform the mb, mh, or mw operation on a total
of <code>&lt;hex-byte-count&gt;</code> bytes, increment the <code>&lt;hex-address&gt;</code> appropriately
after each access
of <code>&lt;hex-byte-count&gt;</code> bytes, increment the <code>&lt;hex-address&gt;</code> appropriately after each access.
</tr>
</table></ul>
<p><b>Example:</b><p>
@ -2160,10 +2198,10 @@ mkdir &lt;path&gt;
</p>
<p>
<b>Limited to Mounted File Systems</b>.
Recall that NuttX uses a <a href="NuttxUserGuide.html#FileSystemOverview"><i>pseudo</i> filesystem</a> for its root file
Recall that NuttX uses a <a href="NuttxUserGuide.html#FileSystemOverview"><i>pseudo</i> file system</a> for its root file
system.
The <code>mkdir</code> command can only be used to create directories in volumes set up with the
<a href="#cmdmount"><code>mount</code></a> command; it cannot be used to create directories in the <i>pseudo</i> filesystem.
<a href="#cmdmount"><code>mount</code></a> command; it cannot be used to create directories in the <i>pseudo</i> file system.
</p>
<p><b>Example:</b></p>
<ul><pre>
@ -2178,7 +2216,7 @@ nsh&gt;
<table width ="100%">
<tr bgcolor="#e4e4e4">
<td>
<a name="cmdmkfatfs"><h2>2.37 Create a FAT Filesystem (mkfatfs)</h2></a>
<a name="cmdmkfatfs"><h2>2.37 Create a FAT File System (mkfatfs)</h2></a>
</td>
</tr>
</table>
@ -2196,7 +2234,7 @@ mkfatfs [-F &lt;fatsize&gt;] &lt;block-driver&gt;
</p>
<p>
NSH provides this command to access the <a href="mkfatfs"><code>mkfatfs()</code></a> NuttX API.
This block device must reside in the NuttX <a href="NuttxUserGuide.html#FileSystemOverview"><i>pseudo</i> filesystem</a> and
This block device must reside in the NuttX <a href="NuttxUserGuide.html#FileSystemOverview"><i>pseudo</i> file system</a> and
must have been created by some call to <code>register_blockdriver()</code> (see <code>include/nuttx/fs/fs.h</code>).
</p>
@ -2307,26 +2345,26 @@ mount -t &lt;fstype&gt; [-o &lt;options&gt;] &lt;block-device&gt; <code>&lt;dir-
If no parameters are provided on the command line after the <code>mount</code> command, then the <code>mount</code> command will enumerate all of the current mountpoints on the console.
</p>
<p>
If the mount parameters are provied on the command after the <code>mount</code> command, then the <code>mount</code> command will mount a file system in the NuttX pseudo-file system.
<code>mount</code>' performs a three way association, binding:
If the mount parameters are provided on the command after the <code>mount</code> command, then the <code>mount</code> command will mount a file system in the NuttX pseudo-file system.
<code>mount</code> performs a three way association, binding:
</p>
<ol>
<li><b>File system.</b>
<li><b>File System.</b>
The '-t <code>&lt;fstype&gt;</code>' option identifies the type of
file system that has been formatted on the <code>&lt;block-device&gt;</code>.
As of this writing, <code>vfat</code> is the only supported value for <code>&lt;fstype&gt;</code>
</li>
<li><b>Block Device.</b>
The <code>&lt;block-device&gt;</code> argument is the full or relative
path to a block driver inode in the <a href="NuttxUserGuide.html#FileSystemOverview"><i>pseudo</i> filesystem</a>.
path to a block driver inode in the <a href="NuttxUserGuide.html#FileSystemOverview"><i>pseudo</i> file system</a>.
By convention, this is a name under the <code>/dev</code> sub-directory.
This <code>&lt;block-device&gt;</code> must have been previously formatted with the same file system
type as specified by <code>&lt;fstype&gt;</code>
</li>
<li><b>Mount Point.</b>
The mount point, <code>&lt;dir-path&gt;</code>, is the location in the
<a href="NuttxUserGuide.html#FileSystemOverview"><i>pseudo</i> filesystem</a> where the mounted volume will appear.
This mount point can only reside in the NuttX <a href="NuttxUserGuide.html#FileSystemOverview"><i>pseudo</i> filesystem</a>.
<a href="NuttxUserGuide.html#FileSystemOverview"><i>pseudo</i> file system</a> where the mounted volume will appear.
This mount point can only reside in the NuttX <a href="NuttxUserGuide.html#FileSystemOverview"><i>pseudo</i> file system</a>.
By convention, this mount point is a subdirectory under <code>/mnt</code>.
The mount command will create whatever pseudo directories that may be needed to complete the
full path but the full path must not already exist.
@ -2334,8 +2372,8 @@ mount -t &lt;fstype&gt; [-o &lt;options&gt;] &lt;block-device&gt; <code>&lt;dir-
</ol>
<p>
After the volume has been mounted in the NuttX
<a href="NuttxUserGuide.html#FileSystemOverview"><i>pseudo</i> filesystem</a>,
it may be access in the same way as other objects in thefile system.
<a href="NuttxUserGuide.html#FileSystemOverview"><i>pseudo</i> file system</a>,
it may be access in the same way as other objects in the file system.
</p>
<p><b>Examples</b>:</p>
<p>Using <code>mount</code> to mount a file system:</p>
@ -2383,7 +2421,7 @@ mv &lt;old-path&gt; &lt;new-path&gt;
<p>
<b>Synopsis</b>.
Rename the file object at <code>&lt;old-path&gt;</code> to <code>&lt;new-path&gt;</code>.
Both paths must reside in the same mounted filesystem.
Both paths must reside in the same mounted file system.
</p>
<table width ="100%">
@ -2527,7 +2565,7 @@ put [-b|-n] [-f &lt;remote-path&gt;] -h &lt;ip-address&gt; &lt;local-path&gt;
<tr>
<td><b><code>-b|-n</code></b></td>
<td>
Selects either binary (&quot;octet&quot;) or test (&quot;netascii&quot;) transfer
Selects either binary (&quot;octet&quot;) or text (&quot;netascii&quot;) transfer
mode. Default: text.
</td>
</tr>
@ -2616,11 +2654,11 @@ rm &lt;file-path&gt;
<p>
<b>Synopsis</b>.
Remove the specified <code>&lt;file-path&gt;</code> name from the mounted file system.
Recall that NuttX uses a <a href="NuttxUserGuide.html#FileSystemOverview"><i>pseudo</i> filesystem</a> for its root file
Recall that NuttX uses a <a href="NuttxUserGuide.html#FileSystemOverview"><i>pseudo</i> file system</a> for its root file
system.
The <code>rm</code> command can only be used to remove (unlink) files in volumes set up with the
<a href="#cmdmount"><code>mount</code></a> command;
it cannot be used to remove names in the <i>pseudo</i> filesystem.
it cannot be used to remove names in the <i>pseudo</i> file system.
</p>
<p><b>Example:</b></p>
<ul><pre>
@ -2650,11 +2688,11 @@ rmdir &lt;dir-path&gt;
<p>
<b>Synopsis</b>.
Remove the specified <code>&lt;dir-path&gt;</code> directory from the mounted file system.
Recall that NuttX uses a <a href="NuttxUserGuide.html#FileSystemOverview"><i>pseudo</i> filesystem</a> for its root file
Recall that NuttX uses a <a href="NuttxUserGuide.html#FileSystemOverview"><i>pseudo</i> file system</a> for its root file
system.
The <code>rmdir</code> command can only be used to remove directories from volumes set up with the
<a href="#cmdmount"><code>mount</code></a> command;
it cannot be used to remove directories from the <i>pseudo</i> filesystem.
it cannot be used to remove directories from the <i>pseudo</i> file system.
</p>
<p><b>Example:</b></p>
<ul><pre>
@ -2712,10 +2750,7 @@ set [{+|-}{e|x|xe|ex}] [&lt;name&gt; &lt;value&gt;]
</pre></ul>
<p>
<b>Synopsis</b>.
Set the environment variable <code>&lt;name&gt;</code> to the string <code>&lt;value&gt;</code> and or set NSH
parser control options. For example,
For example,
Set the environment variable <code>&lt;name&gt;</code> to the string <code>&lt;value&gt;</code> and or set NSH parser control options. For example,
</p>
<ul><pre>
nsh&gt; echo $foobar
@ -2728,7 +2763,7 @@ nsh&gt;
<p>
Set the 'exit on error control' and/or 'print a trace' of commands when parsing
scripts in NSH. The settinngs are in effect from the point of exection, until
scripts in NSH. The settings are in effect from the point of execution, until
they are changed again, or in the case of the init script, the settings are
returned to the default settings when it exits. Included child scripts will run
with the parents settings and changes made in the child script will effect the
@ -2740,9 +2775,8 @@ nsh&gt;
</p>
<p>
Use 'set -x' to enable and 'set +x' to disable (silence) printing a trace of the script
commands as they are ececuted.
The default is +x. No printing of a trace of script commands as they are executed.
commands as they are executed.
The default is +x: no printing of a trace of script commands as they are executed.
</p>
Example 1 - no exit on command not found
@ -2757,16 +2791,16 @@ nsh&gt;
notacommand
</pre></ul>
Example 3 - will exit on command not found, and print a trace of the script commmands
Example 3 - will exit on command not found, and print a trace of the script commands
<ul><pre>
set -ex
</pre></ul>
Example 4 - will exit on command not found, and print a trace of the script commmands
Example 4 - will exit on command not found, and print a trace of the script commands
and set foobar to foovalue.
<ul><pre>
set -ex foobar foovalue
nsh> echo $foobar
nsh&gt; echo $foobar
foovalue
</pre></ul>
@ -2855,8 +2889,7 @@ nsh&gt; time "sleep 2"
nsh&gt;
</pre></ul>
<p>
The additional 10 millseconds in this example is due to the way that the sleep command works: It always waits one system clock tick longer than requested and this test setup used a 10 millisecond periodic system
timer.
The additional 10 milliseconds in this example is due to the way that the sleep command works: It always waits one system clock tick longer than requested and this test setup used a 10 millisecond periodic system timer.
Sources of error could include various quantization errors, competing CPU usage, and the additional overhead of the time command execution itself which is included in the total.
</p>
<p>
@ -2949,7 +2982,7 @@ uname [-a | -imnoprsv]
<tr>
<td><code>-n</code></td>
<td>
Print the network node hostname (only availabel if <code>CONFIG_NET=y</code>)
Print the network node hostname (only available if <code>CONFIG_NET=y</code>)
</td>
</tr>
<tr>
@ -3167,7 +3200,7 @@ nsh&gt;
</p>
<p>
Note that in addition to general NuttX configuation settings, each NSH command can be
Note that in addition to general NuttX configuration settings, each NSH command can be
individually disabled via the settings in the rightmost column.
All of these settings make the configuration of NSH potentially complex but also allow it to
squeeze into very small memory footprints.
@ -3336,13 +3369,13 @@ nsh&gt;
</tr>
<tr>
<td><b><code>ln</code></b></td>
<td><code>CONFIG_NFILE_DESCRIPTORS</code> &gt; 0</td>
<td><code>CONFIG_NSH_DISABLE_LL</code></td>
<td><code>CONFIG_NFILE_DESCRIPTORS</code> &gt; 0 &amp;&amp; <code>CONFIG_PSEUDOFS_SOFTLINKS</code></td>
<td><code>CONFIG_NSH_DISABLE_LN</code></td>
</tr>
<tr>
<td><b><code>ls</code></b></td>
<td><code>CONFIG_NFILE_DESCRIPTORS</code> &gt; 0</td>
<td><code>CONFIG_NSH_DISABLE_LS</code> &amp;&amp; <code>CONFIG_PSEUDOFS_SOFTLINKS</code></td>
<td><code>CONFIG_NSH_DISABLE_LS</code></td>
</tr>
<tr>
<td><b><code>lsmod</code></b></td>
@ -3441,6 +3474,11 @@ nsh&gt;
<td>!<code>CONFIG_DISABLE_ENVIRON</code> &amp;&amp; <code>CONFIG_NFILE_DESCRIPTORS</code> &gt; 0</td>
<td><code>CONFIG_NSH_DISABLE_PWD</code></td>
</tr>
<tr>
<td><b><code>readlink</code></b></td>
<td><code>CONFIG_NFILE_DESCRIPTORS</code> &gt; 0 &amp;&amp; <code>CONFIG_PSEUDOFS_SOFTLINKS</code></td>
<td><code>CONFIG_NSH_DISABLE_READLINK</code></td>
</tr>
<tr>
<td><b><code>reboot</code></b></td>
<td><code>CONFIG_BOARD_RESET</code></td>
@ -3488,7 +3526,7 @@ nsh&gt;
</tr>
<tr>
<td><b><code>time</code></b></td>
<td>&nbsp</td>
<td>&nbsp;</td>
<td><code>CONFIG_NSH_DISABLE_TIME</code></td>
</tr>
<tr>
@ -3498,7 +3536,7 @@ nsh&gt;
</tr>
<tr>
<td><b><code>uname</code></b></td>
<td>br</td>
<td>&nbsp;</td>
<td><code>CONFIG_NSH_DISABLE_UNAME</code></td>
</tr>
<tr>
@ -3547,15 +3585,15 @@ nsh&gt;
<p><sup>1</sup><small>
Because of hardware padding, the actual required packet size may be larger</small><br>
<sup>2</sup><small>
Special TFTP server start-up optionss will probably be required to permit
Special TFTP server start-up options will probably be required to permit
creation of files for the correct operation of the <code>put</code> command.</small><br>
<sup>3</sup><small>
<code>CONFIG_FS_READABLE</code> is not a user configuration but is set automatically
if any readable filesystem is selected. At present, this is either <code>CONFIG_FS_FAT</code>
if any readable file system is selected. At present, this is either <code>CONFIG_FS_FAT</code>
or <code>CONFIG_FS_ROMFS</code>.</small><br>
<sup>4</sup><small>
<code>CONFIG_FS_WRITABLE</code> is not a user configuration but is set automatically
if any writable filesystem is selected. At present, this is only <code>CONFIG_FS_FAT</code>.</small><br>
if any writable file system is selected. At present, this is only <code>CONFIG_FS_FAT</code>.</small><br>
<sup>5</sup><small>
Verbose help output can be suppressed by defining <code>CONFIG_NSH_HELP_TERSE</code>.
In that case, the help command is still available but will be slightly smaller.
@ -3613,7 +3651,7 @@ nsh&gt;
<td valign="top"><b><code>CONFIG_NSH_FILEIOSIZE</code></b></td>
<td>
Size of a static I/O buffer used for file access (ignored if
there is no filesystem). Default is 1024.
there is no file system). Default is 1024.
</td>
</tr>
<tr>
@ -3686,7 +3724,7 @@ set FOOBAR ABC_${FOO}_${BAR}
<td valign="top"><b><code>CONFIG_NSH_NESTDEPTH</code></b></td>
<td>
The maximum number of nested <a href="#conditional"><code>if-then[-else]-fi</code></a> sequences that
are permissable. Default: 3
are permissible. Default: 3
</td>
</tr>
<tr>
@ -3734,7 +3772,7 @@ set FOOBAR ABC_${FOO}_${BAR}
<tr>
<td valign="top"><b><code>CONFIG_NSH_ROMFSETC</code></b></td>
<td>
Mount a ROMFS filesystem at <code>/etc</code> and provide a startup script
Mount a ROMFS file system at <code>/etc</code> and provide a startup script
at <code>/etc/init.d/rcS</code>. The default startup script will mount
a FAT FS RAMDISK at <code>/tmp</code> but the logic is
<a href="#startupscript">easily extensible</a>.
@ -3837,7 +3875,7 @@ set FOOBAR ABC_${FOO}_${BAR}
<tr>
<td valign="top"><b><code>CONFIG_NSH_TELNET</code></b></td>
<td>
If <code>CONFIG_NSH_TELNET</code> is set to <i>y</i>, then a TELENET
If <code>CONFIG_NSH_TELNET</code> is set to <i>y</i>, then a TELNET
server front-end is selected. When this option is provided,
you may log into NuttX remotely using telnet in order to
access NSH.
@ -3932,7 +3970,7 @@ set FOOBAR ABC_${FOO}_${BAR}
<td valign="top"><b><code>CONFIG_NSH_IOBUFFER_SIZE</code></b></td>
<td>
Determines the size of the I/O buffer to use for sending/
receiving TELNET commands/reponses
receiving TELNET commands/responses
</td>
</tr>
<tr>
@ -3963,7 +4001,7 @@ set FOOBAR ABC_${FOO}_${BAR}
<tr>
<td valign="top"><b><code>CONFIG_NSH_NOMAC</code></b></td>
<td>
Set if your ethernet hardware has no built-in MAC address.
Set if your Ethernet hardware has no built-in MAC address.
If set, a bogus MAC will be assigned.
</td>
</tr>
@ -4236,7 +4274,7 @@ mount -t vfat /dev/ram1 /tmp
</p>
<li>
<p>
Mount the FAT filesystem at a configured mountpoint, <code>/tmp</code>.
Mount the FAT file system at a configured mountpoint, <code>/tmp</code>.
</p>
</ul>
<p>
@ -4364,7 +4402,7 @@ struct cmdmap_s
That last string is what is printed when enter &quot;<code>nsh&gt help</code>&quot;.
</p>
<p>
So, for you sample commnd, you would add the following the to the <code>g_cmdmap[]</code> table:
So, for you sample command, you would add the following the to the <code>g_cmdmap[]</code> table:
</p>
<ul><pre>
{ &quot;mycmd&quot;, cmd_mycmd, 1, 1, NULL },
@ -4525,7 +4563,7 @@ int hello_main(int argc, char *argv[])
</p>
<li>
<p>
And finally, the <code>apps/examples/Makefile</code> will execute the <i>context</i> target in all configured <code>example</code>sub-directores, getting us finally to <code>apps/examples/Makefile</code> which is covered below.</p>
And finally, the <code>apps/examples/Makefile</code> will execute the <i>context</i> target in all configured <code>example</code>sub-directories, getting us finally to <code>apps/examples/Makefile</code> which is covered below.</p>
</ol>
<p>
@ -4654,7 +4692,7 @@ CONFIG_SCHED_WAITPID=y
<p>
You replace the sample code at <code>apps/examples/nsh/nsh_main.c</code> with whatever start-up logic that you want.
NSH is a library at <code>apps/nshlib</code>.
<code>apps.examplex/nsh</code> is just a tiny, example start-up function (<code>CONFIG_USER_ENTRYPOINT</code>()) that that runs immediately and illustrates how to start NSH
<code>apps.examples/nsh</code> is just a tiny, example start-up function (<code>CONFIG_USER_ENTRYPOINT</code>()) that that runs immediately and illustrates how to start NSH
If you want something else to run immediately then you can write your write your own custom <code>CONFIG_USER_ENTRYPOINT</code>() function and then start other tasks from your custom <code>CONFIG_USER_ENTRYPOINT</code>().
</p>
<li>
@ -4711,7 +4749,7 @@ CONFIG_SCHED_WAITPID=y
<ul>
<li>
<p>
NSH will create a read-only RAM disk (a ROM disk), containing a tiny ROMFS filesystem containing the following:
NSH will create a read-only RAM disk (a ROM disk), containing a tiny ROMFS file system containing the following:
</p>
<ul><pre>
`--init.d/
@ -4722,7 +4760,7 @@ CONFIG_SCHED_WAITPID=y
</p>
<li>
<p>
NSH will then mount the ROMFS filesystem at <code>/etc</code>, resulting in:
NSH will then mount the ROMFS file system at <code>/etc</code>, resulting in:
</p>
<ul><pre>
|--dev/
@ -4829,7 +4867,7 @@ mount -t vfat /dev/ram1 /tmp
</p>
<p>
To generate a custom <code>rcS</code> file a copy of <code>rcS.template</code> needs to be placed at <code>tools/</code> and changed according to the desired start-up behaviour.
Running <code>tools/mkromfsimg.h</code> creates <code>nsh_romfsimg.h</code> which needs to be copied to <code>apps/nhslib</code> OR if <code>CONFIG_NSH_ARCHROMFS</code> is defined to <code>configs/&lt;board&gt;/include</code>.
Running <code>tools/mkromfsimg.h</code> creates <code>nsh_romfsimg.h</code> which needs to be copied to <code>apps/nshlib</code> OR if <code>CONFIG_NSH_ARCHROMFS</code> is defined to <code>configs/&lt;board&gt;/include</code>.
</p>
</ol>
@ -4845,7 +4883,7 @@ mount -t vfat /dev/ram1 /tmp
<p>
All of the startup-behavior is contained in <code>rcS.template</code>.
The role of <code>mkromfsimg.sh</code> script is to (1) apply the specific configuration settings to <code>rcS.template</code> to create the final <code>rcS</code>, and (2) to generate the header file <code>nsh_romfsimg.h</code> containg the ROMFS file system image.
The role of <code>mkromfsimg.sh</code> script is to (1) apply the specific configuration settings to <code>rcS.template</code> to create the final <code>rcS</code>, and (2) to generate the header file <code>nsh_romfsimg.h</code> containing the ROMFS file system image.
To do this, <code>mkromfsimg.sh</code> uses two tools that must be installed in your system:
</p>
<ol>
@ -5316,13 +5354,13 @@ xxd -i romfs_img >nsh_romfsimg.h
<li><a href="#cmdinsmod"><code>insmod</code></a></li>
<li><a href="#cmdkill"><code>kill</code></a></li>
<li><a href="#cmdlosetup"><code>losetup</code></a></li>
<li><a href="#cmdln">ln</code></a></li>
<li><a href="#cmdls">ls</code></a></li>
<li><a href="#cmdln"><code>ln</code></a></li>
<li><a href="#cmdls"><code>ls</code></a></li>
<li><a href="#cmdmbhw"><code>mb</code></a></li>
<li><a href="#nshlogin">Login</a></li>
<li><a href="#verifymethods">Login, Credentials</a></li>
<li><a href="#cmdlsmod"><code>lsmod</code></a></li>
<li><a href="#cmdmd5">md5</a></li>
<li><a href="#cmdmd5"><code>md5</code></a></li>
<li><a href="#cmdmbhw"><code>mh</code></a></li>
<li><a href="#cmdmbhw"><code>mw</code></a></li>
<li><a href="#cmdmkdir"><code>mkdir</code></a></li>
@ -5331,10 +5369,10 @@ xxd -i romfs_img >nsh_romfsimg.h
<li><a href="#cmdmkrd"><code>mkrd</code></a></li>
<li><a href="#custinit"><code>mkromfsimg.sh</code></a></li>
<li><a href="#cmdmount"><code>mount</code></a></li>
<li><a href="#cmdmv"><code>mv</code></a></li>
</ul></td>
<td width="34%" valign="top">
<ul>
<li><a href="#cmdmv"><code>mv</code></a></li>
<li><a href="#cmdnfsmount"><code>nfsmount</code></a></li>
<li><a href="#cmdoverview"><code>nice</code></a></li>
<li><a href="#custonshlib">NSH library (<code>nshlib</code>)</a></li>
@ -5391,6 +5429,7 @@ xxd -i romfs_img >nsh_romfsimg.h
<li><a href="#custonshlib"><code>up_cxxinitialize()</code></a></li>
<li><a href="#cmdurldec"><code>urldecode</code></a></li>
<li><a href="#cmdurlencode"><code>urlencode</code></a></li>
<li><a href="#usbstartup">USB console startup</a></li>
<li><a href="#cmduseradd"><code>useradd</code></a></li>
<li><a href="#cmduserdel"><code>userdel</code></a></li>
<li><a href="#cmdusleep"><code>usleep</code></a></li>

39
Documentation/NuttX.html
View file

@ -1624,8 +1624,8 @@
<li>STMicroelectronics
<ul>
<li><a href="#str71x">STMicro STR71x</a> <small>(ARM7TDMI)</small></li>
<li><a href="#stm32l152">STMicro STM32L152</a> <small>(STM32 L &quot;EnergyLite&quot; Line, ARM Cortex-M3)</small></li>
<li><a href="#stm32l162">STMicro STM32L162</a> <small>(STM32 L &quot;EnergyLite&quot; Medium+ Density, ARM Cortex-M3)</small></li>
<li><a href="#stm32l152">STMicro STM32L152</a> <small>(STM32 L1 &quot;EnergyLite&quot; Line, ARM Cortex-M3)</small></li>
<li><a href="#stm32l162">STMicro STM32L162</a> <small>(STM32 L1 &quot;EnergyLite&quot; Medium+ Density, ARM Cortex-M3)</small></li>
<li><a href="#stm32f0xx">STMicro STM32F0xx</a> <small>(STM32 F0, ARM Cortex-M0)</small></li>
<li><a href="#stm32f100x">STMicro STM32F100x</a> <small>(STM32 F1 &quot;Value Line&quot;Family, ARM Cortex-M3)</small></li>
<li><a href="#stm32f102x">STMicro STM32F102x</a> <small>(STM32 F1 Family, ARM Cortex-M3)</small></li>
@ -1651,9 +1651,9 @@
<li><a href="#stm32f429x">STMicro STM32 F429</a> <small>(STM32 F4 family, ARM Cortex-M4)</small></li>
<li><a href="#stm32f446x">STMicro STM32 F446</a> <small>(STM32 F4 family, ARM Cortex-M4)</small></li>
<li><a href="#stm32f46xxx">STMicro STM32 F46xx</a> <small>(STM32 F4 family, ARM Cortex-M4)</small></li>
<li><a href="#stm32l4x2">STMicro STM32 L4x2</a> <small>(STM32 F4 family, ARM Cortex-M4)</small></li>
<li><a href="#stm32l476">STMicro STM32 L476</a> <small>(STM32 F4 family, ARM Cortex-M4)</small></li>
<li><a href="#stm32l496">STMicro STM32 L496</a> <small>(STM32 F4 family, ARM Cortex-M4)</small></li>
<li><a href="#stm32l4x2">STMicro STM32 L4x2</a> <small>(STM32 L4 family, ARM Cortex-M4)</small></li>
<li><a href="#stm32l476">STMicro STM32 L476</a> <small>(STM32 L4 family, ARM Cortex-M4)</small></li>
<li><a href="#stm32l496">STMicro STM32 L496</a> <small>(STM32 L4 family, ARM Cortex-M4)</small></li>
<li><a href="#stm32f74x">STMicro STM32 F745/F746</a> <small>(STM32 F7 family, ARM Cortex-M7)</small></li>
<li><a href="#stm32f75x">STMicro STM32 F756</a> <small>(STM32 F7 family, ARM Cortex-M7)</small></li>
<li><a href="#stm32f76xx77xx">STMicro STM32 F76xx/F77xx</a> <small>(STM32 F7 family, ARM Cortex-M7)</small></li>
@ -2871,7 +2871,7 @@ Mem: 14096 3928 10168 10168
nsh>
</pre></ul>
<p>
You can see that 9.9KB (62%) of SRAM heap is staill available for further application development while NSH is running.
You can see that 9.9KB (62%) of SRAM heap is still available for further application development while NSH is running.
</p>
</td>
</tr>
@ -2883,9 +2883,9 @@ nsh>
<td><br></td>
<td>
<p>
<a name="stm32l162"><b>STMicro STM32F152x/162x(STM32 F1 &quot;EnergyLite&quot; Medium+ Density Family)</b>.</a>
Support for the STM32152 and STM32162 Medium+ density parts from Jussi Kivilinna and Sami Pelkonen was included in NuttX-7.3, extending the basic STM32F152x support.
This is <i>architecture-only</i> support, meaning that support for the boards with these chips is available, but not support for any publicly available boards is included.
<a name="stm32l162"><b>STMicro STM32L152x/162x (STM32 L1 &quot;EnergyLite&quot; Medium+ Density Family)</b>.</a>
Support for the STM32L152 and STM32L162 Medium+ density parts from Jussi Kivilinna and Sami Pelkonen was included in NuttX-7.3, extending the basic STM32L152x support.
This is <i>architecture-only</i> support, meaning that support for the boards with these chips is available, but no support for any publicly available boards is included.
</p>
</td>
</tr>
@ -2995,7 +2995,7 @@ nsh>
</li>
<li>
<p>
The other port is for a generic minimual STM32F103CBT6 &quot;blue&quot; board contributed by Alan Carvalho de Assis.
The other port is for a generic minimal STM32F103CBT6 &quot;blue&quot; board contributed by Alan Carvalho de Assis.
Alan added support for numerous sensors, tone generators, user LEDs, and LCD support in NuttX 7.18.
</p>
</li>
@ -3170,7 +3170,7 @@ nsh>
<td>
<p>
<a name="stm32f107x"><b>STMicro STM32F107x (STM32 F1 &quot;Connectivity Line&quot; family)</b>.</a>
Chip support for the STM32 F1 &quot;Connectivity Line&quot; family has been present in NuttX for some time and users have reported that they have successful brought up NuttX on theor proprietary boards using this logic.
Chip support for the STM32 F1 &quot;Connectivity Line&quot; family has been present in NuttX for some time and users have reported that they have successful brought up NuttX on their proprietary boards using this logic.
</p>
<ul>
<li>
@ -3259,7 +3259,7 @@ nsh>
</p>
<ul>
<b>STATUS:</b>
In addition to the above-mention WiFI support, the Photon board support includes buttons, LEDS, IWDG, USB OTG HS, and procfs support. Configurations available for nsh, usbnsh, and wlan configurations. See the Photon https://bitbucket.org/nuttx/nuttx/src/master/configs/photon/README.txt" target="_blank">README</a> file for additional information.
In addition to the above-mention WiFI support, the Photon board support includes buttons, LEDS, IWDG, USB OTG HS, and procfs support. Configurations available for nsh, usbnsh, and wlan configurations. See the Photon <a href="https://bitbucket.org/nuttx/nuttx/src/master/configs/photon/README.txt" target="_blank">README</a> file for additional information.
</td>
</tr>
<tr>
@ -3783,7 +3783,7 @@ nsh>
</ul>
<p>
<b>STMicro ST Nucleo F303RE board.</b>.
<b>STMicro ST Nucleo F303RE board</b>.
Contributed by Paul Alexander Patience.
</p>
<ul>
@ -4047,7 +4047,7 @@ nsh>
</p>
<ul>
<li>
The intial release included support from either OTG FS or OTG HS in FS mode.
The initial release included support from either OTG FS or OTG HS in FS mode.
</li>
<li>
The F429 port adds support for the STM32F439 LCD and OTG HS (in FS mode).
@ -4176,10 +4176,17 @@ nsh>
</p>
<ul>
<li>Serial Audio Interface (SAI).</li>
<li>Power Managmement.</li>
<li>Power Management.</li>
<li>LPTIM.</li>
<li>Comparator (COMP).</li>
</ul>
<p>
<b>NuttX-7.21</b>.
Additional drivers were added:
</p>
<ul>
<li>Internal Watchdog (IWDG).</li>
</ul>
</td>
</tr>
@ -4481,7 +4488,7 @@ nsh>
<li>
This board supports included two configurations for the NuttShell (<a href="http://www.nuttx.org/Documentation/NuttShell.html">NSH</a>).
Both are networked enabled: One configured to support IPv4 and one configured to supported IPv6.
Instructions are included in the board <a href="https://bitbucket.org/nuttx/nuttx/src/master/configs/dk-tm4c129x/README.txt" target="_blank">README</a> file for configuring both IPv4 and IPv6 simultaneously..
Instructions are included in the board <a href="https://bitbucket.org/nuttx/nuttx/src/master/configs/dk-tm4c129x/README.txt" target="_blank">README</a> file for configuring both IPv4 and IPv6 simultaneously.
</li>
<li>
Tiva PWM and Quadrature Encoder drivers were contributed to NuttX in 7.18 by Young.

121
Documentation/NuttXCCodingStandard.html
View file

@ -12,7 +12,7 @@
<h1><big><font color="#3c34ec">
<i>NuttX C Coding Standard</i>
</font></big></h1>
<p>Last Updated: May 6, 2017</p>
<p>Last Updated: June 11, 2017</p>
</td>
</tr>
</table>
@ -736,12 +736,25 @@ void some_function(void)
<ul>
<li>
<b>Always on Separate Lines</b>.
Braces always appear on a separate line containing nothing else other that white space.
Braces always appear on a separate line containing nothing else other than white space.
</li>
<li>
<b>Never Comments on Braces</b>.
Do not put comments on the same line as braces.
</li>
<li>
<b>Compound Statements</b>.
Within this document, an opening left brace followed by a sequence of statments, and ending with a closing right brace is refered to as a <i>compound statement</i>.
</li>
<li>
<b>Nested Compound Statements</b>.
In the case where there are nested compound statements that end with several consecutive right braces, each closing right brace must lie on a separate line and must be indented to match the corresponding opening brace.
</li>
<li>
<b>Final brace followed by a single blank line</b>.
The <i>final</i> right brace must be followed by a blank line as per standard rules.
In the case where there are nested several consecutive right braces, no blank lines should be inserted except for after the <i>final</i> right brace.
</li>
<li>
<b>Special Indentation Rules</b>.
Special <a href="#indentation">indentation rules</a> apply to braces.
@ -763,6 +776,19 @@ while (true)
...
} /* not valid */
} /* end forever */
if (a < b) {
if (a < 0) {
c = -a;
} else {
c = a;
}
} else {
if (b < 0) {
c = -b;
} else {
c = b;
}
}
</ul></pre></font>
</td></tr>
<tr><td bgcolor="white">
@ -779,12 +805,36 @@ while (true)
...
}
}
if (a < b)
{
if (a < 0)
{
c = -a;
}
else
{
c = a;
}
}
else
{
if (b < 0)
{
c = -b;
}
else
{
c = b;
}
}
</ul></pre></font>
</td></tr>
</table></center>
<p>
<b>Exceptions</b>.
<b>Exception to Indentation Rule for Braces</b>.
The exception is braces that following structure, enumeration, union, and function declarations.
There is no additional indentation for those braces;
those braces align with the beginning of the definition
@ -854,6 +904,7 @@ int animals(int animal)
{
...
}
</ul></pre></font>
</td></tr>
</table></center>
@ -2099,12 +2150,24 @@ x++;
</td></tr>
</table></center>
<p>
<b>Forbidden Multicharacter Forms</b>.
Many operators are expressed as a character in combination with <code>=</code> such as <code>+=</code>, <code>>=</code>, <code>>>=</code>, etc.
Some compilers will accept the <code>=</code> at the beginning or the end of the sequence.
This standard, however, requires that the <code>=</code> always appear last in order to avoid amiguities that may arise if the <code>=</code> were to appear first. For example, <code>a =++ b;</code> could also be interpreted as <code>a =+ +b;</code> or <code>a = ++b</code> all of which are very different.
</p>
<p>
<h2>4.4 <a name="ifthenelse"></a><code>if then else</code> Statement</h2>
<p><b>Coding Standard:</b></p>
<ul>
<li>
<b><code>if</code> separated from <code>&lt;condition&gt;</code></b>.
The <code>if</code> keyword and the <code>&lt;condition&gt;</code> must appear on the same line.
The <code>if</code> keyword and the <code>&lt;condition&gt;</code> must be separated by a single space.
</li>
</li>
<b>Keywords on separate lines</b>.
<code>if &lt;condition&gt;</code> and <code>else</code> must lie on separate lines with nothing else present on the line.
</li>
@ -2118,16 +2181,24 @@ x++;
</li>
<li>
<b>Statement(s) always enclosed in braces</b>.
Statement(s) following the <code>if &lt;condition&gt;</code> and <code>else</code> lines must always be enclosed in braces.
Braces must follow the <code>if &lt;condition&gt;</code> and <code>else</code> lines even in the case where these is no contained statement!
Statement(s) following the <code>if &lt;condition&gt;</code> and <code>else</code> keywords must always be enclosed in braces.
Braces must follow the <code>if &lt;condition&gt;</code> and <code>else</code> lines even in the cases where (a) there is no contained statement or (b) there is only a single statement!
</li>
<li>
<b>Braces and indentation</b>.
The placement of braces and statements must follow the standard rules for braces and indentation.
The placement of braces and statements must follow the standard rules for <a href="#braces">braces and indentation</a>.
</li>
<li>
<b>Followed by a single blank line</b>.
The final right brace must be followed by a blank line.
<b>Final brace followed by a single blank line</b>.
The <i>final</i> right brace of the <code>if</code>-<code>else</code> must be followed by a blank line in most cases (the exception given below).
This may be the final brace of the <code>if</code> compound statement if the <code>else</code> keyword is not present.
Or it may be the the final brace of the <code>else</code> compound statement if present.
A blank line never follows the right brace closing the <code>if</code> compound statement if the <code>else</code> keyword is present.
Use of braces must follow all other standard rules for <a href="#braces">braces and spacing</a>.
</li>
<li>
<b>Exception</b>.
That blank line must also be omitted for certain cases where the <code>if &lt;condition&gt;</code>-<code>else</code> statement is nested within another compound statement; there should be no blank lines between consecutive right braces as discussed in the standard rules for use of <a href="#braces">braces</a>.
</li>
</ul>
<p>
@ -2221,6 +2292,11 @@ x++;
<p><b>Coding Standard:</b></p>
<ul>
<li>
<b><code>switch</code> separated from <code>&lt;value&gt;</code></b>.
The <code>switch</code> keyword and the switch <code>&lt;value&gt;</code> must appear on the same line.
The <code>if</code> keyword and the <code>&lt;value&gt;</code> must be separated by a single space.
</li>
<li>
<b>Falling through</b>.
Falling through a case statement into the next case statement is be permitted as long as a comment is included.
@ -2239,6 +2315,14 @@ x++;
<code>break</code> statements are normally indented by two spaces.
When used conditionally with case logic, the placement of the break statement follows normal indentation rules.
</li>
<li>
<b>Followed by a single blank line</b>.
The final right brace that closes the <code>switch &lt;value&gt;</code> statement must be followed by a single blank line.
</li>
<li>
<b>Exception</b>.
That blank line must be omitted for certain cases where the <code>switch &lt;value&gt;</code> statement is nested within another compound statement; there should be no blank lines between consecutive right braces as discussed in the standard rules for use of <a href="#braces">braces</a>.
</li>
</ul>
<p>
<b>Other Applicable Coding Standards</b>.
@ -2274,6 +2358,11 @@ x++;
<h2>4.6 <a name="while"><code>while</code> Statement</a></h2>
<p><b>Coding Standard:</b></p>
<ul>
<li>
<b><code>while</code> separated from <code>&lt;condition&gt;</code></b>.
The <code>while</code> keyword and the <code>&lt;condition&gt;</code> must appear on the same line.
The <code>while</code> keyword and the <code>&lt;condition&gt;</code> must be separated by a single space.
</li>
<li>
<b>Keywords on separate lines</b>.
<code>while &lt;condition&gt;</code> must lie on a separate line with nothing else present on the line.
@ -2297,7 +2386,11 @@ x++;
</li>
<li>
<b>Followed by a single blank line</b>.
The final right brace must be followed by a blank line.
The final right brace that closes the <code>while &lt;condition&gt;</code> statment must be followed by a single blank line.
</li>
<li>
<b>Exception</b>.
That blank line must be omitted for certain cases where the <code>while &lt;condition&gt;</code> statement is nested within another compound statement; there should be no blank lines between consecutive right braces as discussed in the standard rules for use of <a href="#braces">braces</a>.
</li>
</ul>
<p>
@ -2345,15 +2438,20 @@ x++;
</li>
<li>
<b>Statements enclosed in braces</b>
Statement(s) following the <code>do</code> must always be enclosed in braces, even if only a single statement follows.
Statement(s) following the <code>do</code> must always be enclosed in braces, even if only a single statement (or no statement) follows.
</li>
<li>
<b>Braces and indentation</b>.
The placement of braces and statements must follow the standard rules for braces and indentation.
</li>
<li>
<b><code>while</code> separated from <code>&lt;condition&gt;</code></b>.
The <code>while</code> keyword and the <code>&lt;condition&gt;</code> must appear on the same line.
The <code>while</code> keyword and the <code>&lt;condition&gt;</code> must be separated by a single space.
</li>
<li>
<b>Followed by a single blank line</b>.
The final right brace must be followed by a blank line.
The concluding <code>while &lt;condition&gt;</code> must be followed by a single blank line.
</li>
</ul>
<p>
@ -2388,6 +2486,7 @@ x++;
ptr++;
}
while (*ptr != '\0');
</ul></pre></font>
</td></tr>
</table></center>

9
Documentation/NuttxUserGuide.html
View file

@ -5769,15 +5769,6 @@ be sent.
<li><code>pthread_mutex_timedlock</code>. lock a mutex.</li>
<li><code>pthread_mutexattr_getprioceiling</code>. get and set the prioceiling attribute of the mutex attributes object.</li>
<li><code>pthread_mutexattr_setprioceiling</code>. get and set the prioceiling attribute of the mutex attributes object.</li>
<li><code>pthread_rwlock_destroy</code>. destroy and initialize a read-write lock object.</li>
<li><code>pthread_rwlock_init</code>. destroy and initialize a read-write lock object.</li>
<li><code>pthread_rwlock_rdlock</code>. lock a read-write lock object for reading.</li>
<li><code>pthread_rwlock_timedrdlock</code>. lock a read-write lock for reading.</li>
<li><code>pthread_rwlock_timedwrlock</code>. lock a read-write lock for writing.</li>
<li><code>pthread_rwlock_tryrdlock</code>. lock a read-write lock object for reading.</li>
<li><code>pthread_rwlock_trywrlock</code>. lock a read-write lock object for writing.</li>
<li><code>pthread_rwlock_unlock</code>. unlock a read-write lock object.</li>
<li><code>pthread_rwlock_wrlock</code>. lock a read-write lock object for writing.</li>
<li><code>pthread_rwlockattr_destroy</code>. destroy and initialize the read-write lock attributes object.</li>
<li><code>pthread_rwlockattr_getpshared</code>. get and set the process-shared attribute of the read-write lock attributes object.</li>
<li><code>pthread_rwlockattr_init</code>. destroy and initialize the read-write lock attributes object.</li>

4
Documentation/README.html
View file

@ -8,7 +8,7 @@
<tr align="center" bgcolor="#e4e4e4">
<td>
<h1><big><font color="#3c34ec"><i>NuttX README Files</i></font></big></h1>
<p>Last Updated: May 9, 2017</p>
<p>Last Updated: June 10, 2017</p>
</td>
</tr>
</table>
@ -62,6 +62,8 @@ nuttx/
| | `- <a href="https://bitbucket.org/nuttx/nuttx/src/master/configs/arduino-due/README.txt" target="_blank"><b><i>README.txt</i></b></a>
| |- avr32dev1/
| | `- <a href="https://bitbucket.org/nuttx/nuttx/src/master/configs/avr32dev1/README.txt" target="_blank"><b><i>README.txt</i></b></a>
| |- b-l475e-iot01a/
| | `- <a href="https://bitbucket.org/nuttx/nuttx/src/master/configs/b-l475e-iot01a/README.txt" target="_blank"><b><i>README.txt</i></b></a>
| |- bambino-200e/
| | `- <a href="https://bitbucket.org/nuttx/nuttx/src/master/configs/bambino-200e/README.txt" target="_blank"><b><i>README.txt</i></b></a>
| |- c5471evm/

73
Documentation/acronyms.txt
View file

@ -1,57 +1,112 @@
AIC Advanced Interrupt Controller (Atmel SAM)
6loWPAN IPv6 over Low power Wireless Personal Area Networks
ACM Abstract Control Model (USB)
ADC Analog to Digital Conversion
AIC Advanced Interrupt Controller (Atmel SAM)
ARP Address Resolution Protocol (networking)
BCH Block to Character
BINFMT Binary Format (Dynamic Loader)
BPP Bits Per Pixel
CAN Controller Area Network
CDC Communication Device Class (USB)
CP15 Coprocessor 15 (ARM)
CPU Central Processing Unit
DEVIF Device Interface (networking)
DAC Digital to Analog Conversion
DCD Device Controller Driver (USB)
DCMI Digital Camera Interface
DEV Device
DHCP Dynamic Host Configuration Protocol
DHCPC DHCP Client
DHCPD DHCP Daemon (server)
DMA Direct Memory Access (hardware)
DMAC DMA Controller (hardware)
DNS Domain Name Service (or System or Server) (networking)
DRAM Dynamic RAM
EABI Embedded-Application Binary Interface
EEPROM Electrically Erasable Programmable Read-Only Memory
EMAC Ethernet Media Access Controller (networking)
EPROM Erasable Programmable Read-Only Memory
FAT File Allocation Table (file systems)
FB Frame Buffer (video interface)
FSMC Flexible Static Memory Controller (STM32)
FTL FLASH Translation Layer (MTD)
GPIO General Purpose Input/Output
GMAC Gigabit Media Access Controller (networking)
HCD Host Controller Driver (USB)
HSMCI High Speed Memory Card Interface (Atmel)
I/O Input/Output
IOCTL Input/Output Control
IoT Internet of Things (marketing BS)
IP Internet Protocol (version 4?) (networking)
IPv4 Internet Protocol Version 4 (networking)
IPv6 Internet Protocol Version 6 (networking)
IRQ Interrupt Request
I2C Inter-Integrated Circuit
I2S Inter IC Sound
IRQ Interrupt Request (hardware)
I2C Inter-Integrated Circuit (serial interface)
I2S Inter IC Sound (serial interface)
ICMP Internet Control Message Protocol (networking)
ICMPv6 Internet Control Message Protocol for IPv6 (networking)
IGMP Internet Group Multicast Protocol (networking)
IOB I/O Buffer (networking)
LAN Local Area Network (networking)
LCD Liquid Crystal Display
LIBC The "C" Library
LIBM The "C" Math Library
MAC Media Access Control (networking, OSI model)
MCI Memory Card Interface
MCU Microcontroller Unit
MM Memory Management/Manager
MMAP Memory Map
MMC Multi-Media Card
MMCSD See MMC and SD
MMU Memory Management Unit
MPU Memory Protection Unit
MTD Memory Technology Device
NFS Network File System
NETDB Network Data Base (networking)
NETDEV Network Device (networking)
NSH NuttShell
NVM Non-Volatile Memory
NTP Network Time Protocol (networking)
NX NuttX, the NuttX Graphics server (graphics)
NXFFS NuttX Flash File System
NXWM The NuttX Window Manager (graphics)
PID Peripheral ID (Atmel SAM)
PID Process ID (operating systems)
Peripheral ID (Atmel SAM)
PROM Programmable Read-Only Memory
OS Operating System
OTG On-The-Go (USB)
OTP One-Time Programmable
PWM Pulse Width Modulation
PKT "Raw" Packet socket (networking)
PRNG Pseudo-Random Number Generator
RAM Random Access Memory
RNG Random Number Generator
ROM Read-Only Memory
RTC Real Time Clock
RTCC Real Time Clock/Calendar
RTOS Real Time Operating System
SAIC Secure Advanced Interrupt Controller (Atmel SAM)
SD Secure Digital
SD Secure Digital (flash memory)
SDHC Secure Digital High Capacity (flash memory),
Secure Digital Host Controller (hardware)
SDIO Secure Digital I/O
SDRAM Synchronous Dynamic Random Access Memory
SLCD Segment Liquid Crystal Display
SMC Static Memory Controller (hardware)
SPI Serial Periperhal Interface
SPRNG Scalable Parallel Random Number Generator
SRAM Static RAM
SYSLOG System Log
TCP Transmission Control Protocol (networking)
TSC Touchscreen Controller
TWI Two-Wire Interface
TUN network TUNnel
TWI Two-Wire Interface (serial interface)
UDP User Datagram Protocol (networking)
UART Universal Asynchronous Receiver/Transmitter
USB Universal Serial Bus
USB Universal Serial Bus (serial interface)
USART Universal Synchronous/Asynchronous Receiver/Transmitter
WDT Watchdog Timer
WAN Wide Area Network (networking)
WLAN Wireless Local Area Network (networking)
WPAN Wireless Personal Area Network (networking)
WDT Watchdog Timer (hardware)
XDMAC Extended DMA Controller (Atmel)

2
README.txt
View file

@ -1462,6 +1462,8 @@ nuttx/
| | `- README.txt
| |- avr32dev1/
| | `- README.txt
| |- b-l475e-iot01a/
| | `- README.txt
| |- bambino-200e/
| | `- README.txt
| |- c5471evm/

2
ReleaseNotes
View file

@ -13839,7 +13839,7 @@ Additional new features and extended functionality:
Juha Niskanen.
- STM32 Ethernet: Add support for KSZ8081 PHY interrupts. From
Sebastien Lorquet.
- STM32 F4: Add i2s driver. From Taras Drozdovsky.
- STM32 F4: Add I2S driver. From Taras Drozdovsky.
- STM32 L4: Add IWDG peripheral. This is the same as for STM32
except that prescale and reload can be changed after watchdog has
been started, as this seems to work on L4. From Juha Niskanen.

29
TODO
View file

@ -1,4 +1,4 @@
NuttX TODO List (Last updated May 31, 2017)
NuttX TODO List (Last updated June 14, 2017)
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
This file summarizes known NuttX bugs, limitations, inconsistencies with
@ -234,6 +234,33 @@ o Task/Scheduler (sched/)
could be improved and made a little more efficient with this
change.
Title: INAPPROPRIATE USE OF sched_lock() BY pthreads
Description: In implementation of standard pthread functions, the non-
standard, NuttX function sched_lock() is used. This is very
strong sense it disables pre-emption for all threads in all
task groups. I believe it is only really necessary in most
cases to lock threads in the task group with a new non-
standard interface, say pthread_lock().
This is because the OS resources used by a thread such as
mutexes, condition variable, barriers, etc. are only
meaningful from within the task group. So, in order to
performance exclusive operations on these resources, it is
only necessary to block other threads executing within the
task group.
This is an easy change: pthread_lock() and pthread_unlock()
would simply operate on a semaphore retained in the task
group structure. I am, however, hesitant to make this change:
I the flat build model, there is nothing that prevents people
from accessing the inter-thread controls from threads in
differnt task groups. Making this change, while correct,
might introduce subtle bugs in code by people who are not
using NuttX correctly.
Status: Open
Priority: Low. This change would improve real-time performance of the
OS but is not otherwise required.
o SMP
^^^

47
arch/arm/include/stm32l4/chip.h
View file

@ -1,8 +1,10 @@
/************************************************************************************
* arch/arm/include/stm32l4/chip.h
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
* Copyright (C) 2016 Sebastien Lorquet. All rights reserved.
* Author: Sebastien Lorquet <sebastien@lorquet.fr>
* Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@ -45,9 +47,11 @@
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* STM32L476, STM32L486, STM32L496, STM32L4A6
/* STM32L475, STM32L476, STM32L486, STM32L496, STM32L4A6
*
* Differences between family members:
* - L475 has no TSC, no LCD, no AES, no I2C4, no CAN2, No Hash/CRS, no DCMI,
* no DMA2D
* - L486 has AES
* - L496, L4A6 has 320 Kib SRAM, 2xCAN and CameraIF. Most (all?) of these have I2C4.
* - L4A6 has AES and HASH
@ -55,6 +59,8 @@
* ----------- ---------------- ----- ------ ------ ---- ---- -----
* PART PACKAGE GPIOs LCD Tamper FSMC CapS AdcCh
* ----------- ---------------- ----- ------ ------ ---- ---- -----
* STM32L475Rx LQFP100 82 3 Yes 21 16
* STM32L475Vx LQFP64 51 2 No 12 16
* STM32L4x6Jx WLCSP72L 57 8x28 2 No 12 16
* STM32L476Mx WLCSP81L 65 ? ? ? ? ?
* STM32L4x6Qx UFBGA132L 109 8x40 3 Yes 24 16
@ -75,7 +81,8 @@
#if defined(CONFIG_STM32L4_STM32L496XX)
# define STM32L4_SRAM1_SIZE (256*1024) /* 256Kb SRAM1 on AHB bus Matrix */
# define STM32L4_SRAM2_SIZE (64*1024) /* 64Kb SRAM2 on AHB bus Matrix */
#elif defined(CONFIG_STM32L4_STM32L476XX) || defined(CONFIG_STM32L4_STM32L486XX)
#elif defined(CONFIG_STM32L4_STM32L475XX) || defined(CONFIG_STM32L4_STM32L476XX) || \
defined(CONFIG_STM32L4_STM32L486XX)
# define STM32L4_SRAM1_SIZE (96*1024) /* 96Kb SRAM1 on AHB bus Matrix */
# define STM32L4_SRAM2_SIZE (32*1024) /* 32Kb SRAM2 on AHB bus Matrix */
#elif defined(CONFIG_STM32L4_STM32L451XX) || defined(CONFIG_STM32L4_STM32L452XX) || \
@ -89,6 +96,36 @@
# error "Unsupported STM32L4 chip"
#endif
#if defined(CONFIG_STM32L4_STM32L4X5)
# define STM32L4_NFSMC 1 /* Have FSMC memory controller */
# define STM32L4_NATIM 2 /* Two advanced timers TIM1 and 8 */
# define STM32L4_NGTIM32 2 /* 32-bit general timers TIM2 and 5 with DMA */
# define STM32L4_NGTIM16 2 /* 16-bit general timers TIM3 and 4 with DMA */
# define STM32L4_NGTIMNDMA 3 /* 16-bit general timers TIM15-17 without DMA */
# define STM32L4_NBTIM 2 /* Two basic timers, TIM6-7 */
# define STM32L4_NLPTIM 2 /* Two low-power timers, LPTIM1-2 */
# define STM32L4_NRNG 1 /* Random number generator (RNG) */
# define STM32L4_NUART 2 /* UART 4-5 */
# define STM32L4_NUSART 3 /* USART 1-3 */
# define STM32L4_NLPUART 1 /* LPUART 1 */
# define STM32L4_QSPI 1 /* QuadSPI1 */
# define STM32L4_NSPI 3 /* SPI1-3 */
# define STM32L4_NI2C 3 /* I2C1-3 */
# define STM32L4_NSWPMI 1 /* SWPMI1 */
# define STM32L4_NUSBOTGFS 1 /* USB OTG FS */
# define STM32L4_NUSBFS 0 /* No USB FS */
# define STM32L4_NCAN 1 /* CAN1 */
# define STM32L4_NSAI 2 /* SAI1-2 */
# define STM32L4_NSDMMC 1 /* SDMMC interface */
# define STM32L4_NDMA 2 /* DMA1-2 */
# define STM32L4_NPORTS 8 /* 8 GPIO ports, GPIOA-H */
# define STM32L4_NADC 3 /* 12-bit ADC1-3, 16 channels */
# define STM32L4_NDAC 2 /* 12-bit DAC1-2 */
# define STM32L4_NCRC 1 /* CRC */
# define STM32L4_NCOMP 2 /* Comparators */
# define STM32L4_NOPAMP 2 /* Operational Amplifiers */
#endif /* CONFIG_STM32L4_STM32L4X5 */
#if defined(CONFIG_STM32L4_STM32L4X6)
# define STM32L4_NFSMC 1 /* Have FSMC memory controller */
# define STM32L4_NATIM 2 /* Two advanced timers TIM1 and 8 */
@ -101,12 +138,14 @@
# define STM32L4_NUART 2 /* UART 4-5 */
# define STM32L4_NUSART 3 /* USART 1-3 */
# define STM32L4_NLPUART 1 /* LPUART 1 */
# define STM32L4_QSPI 1 /* QuadSPI1 */
# define STM32L4_NSPI 3 /* SPI1-3 */
#if defined(CONFIG_STM32L4_STM32L496XX)
# define STM32L4_NI2C 4 /* I2C1-4 */
#else
# define STM32L4_NI2C 3 /* I2C1-3 */
#endif
# define STM32L4_NSWPMI 1 /* SWPMI1 */
# define STM32L4_NUSBOTGFS 1 /* USB OTG FS */
# define STM32L4_NUSBFS 0 /* No USB FS */
#if defined(CONFIG_STM32L4_STM32L496XX)
@ -142,8 +181,10 @@
# define STM32L4_NUART 1 /* UART 4 */
# define STM32L4_NUSART 3 /* USART 1-3 */
# define STM32L4_NLPUART 1 /* LPUART 1 */
# define STM32L4_QSPI 1 /* QuadSPI1 */
# define STM32L4_NSPI 3 /* SPI1-3 */
# define STM32L4_NI2C 4 /* I2C1-4 */
# define STM32L4_NSWPMI 1 /* SWPMI1 */
# define STM32L4_NUSBOTGFS 0 /* No USB OTG FS */
#if defined(CONFIG_STM32L4_STM32L451XX)
# define STM32L4_NUSBFS 0 /* No USB FS */
@ -178,8 +219,10 @@
# define STM32L4_NUART 0 /* No UART */
# define STM32L4_NUSART 2 /* USART 1-2 */
# define STM32L4_NLPUART 1 /* LPUART 1 */
# define STM32L4_QSPI 1 /* QuadSPI1 */
# define STM32L4_NSPI 2 /* SPI1, SPI3 */
# define STM32L4_NI2C 2 /* I2C1, I2C3 */
# define STM32L4_NSWPMI 1 /* SWPMI1 */
# define STM32L4_NUSBOTGFS 0 /* No USB OTG FS */
# define STM32L4_NUSBFS 1 /* USB FS */
# define STM32L4_NCAN 1 /* CAN1 */

8
arch/arm/include/stm32l4/irq.h
View file

@ -76,10 +76,12 @@
#define STM32L4_IRQ_FIRST (16) /* Vector number of the first external interrupt */
#if defined(CONFIG_STM32L4_STM32L4X6)
# include <arch/stm32l4/stm32l4x6xx_irq.h>
#elif defined(CONFIG_STM32L4_STM32L4X3)
#if defined(CONFIG_STM32L4_STM32L4X3)
# include <arch/stm32l4/stm32l4x3xx_irq.h>
#elif defined(CONFIG_STM32L4_STM32L4X5)
# include <arch/stm32l4/stm32l4x5xx_irq.h>
#elif defined(CONFIG_STM32L4_STM32L4X6)
# include <arch/stm32l4/stm32l4x6xx_irq.h>
#else
# error "Unsupported STM32 L4 chip"
#endif

185
arch/arm/include/stm32l4/stm32l4x5xx_irq.h Normal file
View file

@ -0,0 +1,185 @@
/****************************************************************************************************
* arch/arm/include/stm32l4/stm32l4x5xx_irq.h
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
* Copyright (C) 2015 Sebastien Lorquet. All rights reserved.
* Author: Sebastien Lorquet <sebastien@lorquet.fr>
* Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************************************/
/* This file should never be included directed but, rather, only indirectly through arch/irq.h */
#ifndef __ARCH_ARM_INCLUDE_STM32L4_STM32L4X5XX_IRQ_H
#define __ARCH_ARM_INCLUDE_STM32L4_STM32L4X5XX_IRQ_H
/****************************************************************************************************
* Included Files
****************************************************************************************************/
#include <nuttx/config.h>
/****************************************************************************************************
* Pre-processor Definitions
****************************************************************************************************/
/* IRQ numbers. The IRQ number corresponds vector number and hence map directly to bits in the
* NVIC. This does, however, waste several words of memory in the IRQ to handle mapping tables.
*
* Processor Exceptions (vectors 0-15). These common definitions can be found in the file
* nuttx/arch/arm/include/stm32f7/irq.h which includes this file
*
* External interrupts (vectors >= 16)
*/
#define STM32L4_IRQ_WWDG (STM32L4_IRQ_FIRST+0) /* 0: Window Watchdog interrupt */
#define STM32L4_IRQ_PVD (STM32L4_IRQ_FIRST+1) /* 1: PVD through EXTI Line detection interrupt */
#define STM32L4_IRQ_TAMPER (STM32L4_IRQ_FIRST+2) /* 2: Tamper and time stamp interrupts */
#define STM32L4_IRQ_TIMESTAMP (STM32L4_IRQ_FIRST+2) /* 2: Tamper and time stamp interrupts */
#define STM32L4_IRQ_RTC_WKUP (STM32L4_IRQ_FIRST+3) /* 3: RTC global interrupt */
#define STM32L4_IRQ_FLASH (STM32L4_IRQ_FIRST+4) /* 4: Flash global interrupt */
#define STM32L4_IRQ_RCC (STM32L4_IRQ_FIRST+5) /* 5: RCC global interrupt */
#define STM32L4_IRQ_EXTI0 (STM32L4_IRQ_FIRST+6) /* 6: EXTI Line 0 interrupt */
#define STM32L4_IRQ_EXTI1 (STM32L4_IRQ_FIRST+7) /* 7: EXTI Line 1 interrupt */
#define STM32L4_IRQ_EXTI2 (STM32L4_IRQ_FIRST+8) /* 8: EXTI Line 2 interrupt */
#define STM32L4_IRQ_EXTI3 (STM32L4_IRQ_FIRST+9) /* 9: EXTI Line 3 interrupt */
#define STM32L4_IRQ_EXTI4 (STM32L4_IRQ_FIRST+10) /* 10: EXTI Line 4 interrupt */
#define STM32L4_IRQ_DMA1CH1 (STM32L4_IRQ_FIRST+11) /* 11: DMA1 Channel 1 global interrupt */
#define STM32L4_IRQ_DMA1CH2 (STM32L4_IRQ_FIRST+12) /* 12: DMA1 Channel 2 global interrupt */
#define STM32L4_IRQ_DMA1CH3 (STM32L4_IRQ_FIRST+13) /* 13: DMA1 Channel 3 global interrupt */
#define STM32L4_IRQ_DMA1CH4 (STM32L4_IRQ_FIRST+14) /* 14: DMA1 Channel 4 global interrupt */
#define STM32L4_IRQ_DMA1CH5 (STM32L4_IRQ_FIRST+15) /* 15: DMA1 Channel 5 global interrupt */
#define STM32L4_IRQ_DMA1CH6 (STM32L4_IRQ_FIRST+16) /* 16: DMA1 Channel 6 global interrupt */
#define STM32L4_IRQ_DMA1CH7 (STM32L4_IRQ_FIRST+17) /* 17: DMA1 Channel 7 global interrupt */
#define STM32L4_IRQ_ADC12 (STM32L4_IRQ_FIRST+18) /* 18: ADC1 and ADC2 global interrupt */
#define STM32L4_IRQ_CAN1TX (STM32L4_IRQ_FIRST+19) /* 19: CAN1 TX interrupts */
#define STM32L4_IRQ_CAN1RX0 (STM32L4_IRQ_FIRST+20) /* 20: CAN1 RX0 interrupts */
#define STM32L4_IRQ_CAN1RX1 (STM32L4_IRQ_FIRST+21) /* 21: CAN1 RX1 interrupt */
#define STM32L4_IRQ_CAN1SCE (STM32L4_IRQ_FIRST+22) /* 22: CAN1 SCE interrupt */
#define STM32L4_IRQ_EXTI95 (STM32L4_IRQ_FIRST+23) /* 23: EXTI Line[9:5] interrupts */
#define STM32L4_IRQ_TIM1BRK (STM32L4_IRQ_FIRST+24) /* 24: TIM1 Break interrupt */
#define STM32L4_IRQ_TIM15 (STM32L4_IRQ_FIRST+24) /* 24: TIM15 global interrupt */
#define STM32L4_IRQ_TIM1UP (STM32L4_IRQ_FIRST+25) /* 25: TIM1 Update interrupt */
#define STM32L4_IRQ_TIM16 (STM32L4_IRQ_FIRST+25) /* 25: TIM16 global interrupt */
#define STM32L4_IRQ_TIM1TRGCOM (STM32L4_IRQ_FIRST+26) /* 26: TIM1 Trigger and Commutation interrupts */
#define STM32L4_IRQ_TIM17 (STM32L4_IRQ_FIRST+26) /* 26: TIM17 global interrupt */
#define STM32L4_IRQ_TIM1CC (STM32L4_IRQ_FIRST+27) /* 27: TIM1 Capture Compare interrupt */
#define STM32L4_IRQ_TIM2 (STM32L4_IRQ_FIRST+28) /* 28: TIM2 global interrupt */
#define STM32L4_IRQ_TIM3 (STM32L4_IRQ_FIRST+29) /* 29: TIM3 global interrupt */
#define STM32L4_IRQ_TIM4 (STM32L4_IRQ_FIRST+30) /* 30: TIM4 global interrupt */
#define STM32L4_IRQ_I2C1EV (STM32L4_IRQ_FIRST+31) /* 31: I2C1 event interrupt */
#define STM32L4_IRQ_I2C1ER (STM32L4_IRQ_FIRST+32) /* 32: I2C1 error interrupt */
#define STM32L4_IRQ_I2C2EV (STM32L4_IRQ_FIRST+33) /* 33: I2C2 event interrupt */
#define STM32L4_IRQ_I2C2ER (STM32L4_IRQ_FIRST+34) /* 34: I2C2 error interrupt */
#define STM32L4_IRQ_SPI1 (STM32L4_IRQ_FIRST+35) /* 35: SPI1 global interrupt */
#define STM32L4_IRQ_SPI2 (STM32L4_IRQ_FIRST+36) /* 36: SPI2 global interrupt */
#define STM32L4_IRQ_USART1 (STM32L4_IRQ_FIRST+37) /* 37: USART1 global interrupt */
#define STM32L4_IRQ_USART2 (STM32L4_IRQ_FIRST+38) /* 38: USART2 global interrupt */
#define STM32L4_IRQ_USART3 (STM32L4_IRQ_FIRST+39) /* 39: USART3 global interrupt */
#define STM32L4_IRQ_EXTI1510 (STM32L4_IRQ_FIRST+40) /* 40: EXTI Line[15:10] interrupts */
#define STM32L4_IRQ_RTCALRM (STM32L4_IRQ_FIRST+41) /* 41: RTC alarm through EXTI line interrupt */
#define STM32L4_IRQ_DFSDM3 (STM32L4_IRQ_FIRST+42) /* 42: Digital Filter / Sigma Delta Modulator interrupt */
#define STM32L4_IRQ_TIM8BRK (STM32L4_IRQ_FIRST+43) /* 43: TIM8 Break interrupt */
#define STM32L4_IRQ_TIM8UP (STM32L4_IRQ_FIRST+44) /* 44: TIM8 Update interrupt */
#define STM32L4_IRQ_TIM8TRGCOM (STM32L4_IRQ_FIRST+45) /* 45: TIM8 Trigger and Commutation interrupts */
#define STM32L4_IRQ_TIM8CC (STM32L4_IRQ_FIRST+46) /* 46: TIM8 Capture Compare interrupt */
#define STM32L4_IRQ_ADC3 (STM32L4_IRQ_FIRST+47) /* 47: ADC3 global interrupt */
#define STM32L4_IRQ_FSMC (STM32L4_IRQ_FIRST+48) /* 48: FSMC global interrupt */
#define STM32L4_IRQ_SDMMC1 (STM32L4_IRQ_FIRST+49) /* 49: SDMMC1 global interrupt */
#define STM32L4_IRQ_TIM5 (STM32L4_IRQ_FIRST+50) /* 50: TIM5 global interrupt */
#define STM32L4_IRQ_SPI3 (STM32L4_IRQ_FIRST+51) /* 51: SPI3 global interrupt */
#define STM32L4_IRQ_UART4 (STM32L4_IRQ_FIRST+52) /* 52: UART4 global interrupt */
#define STM32L4_IRQ_UART5 (STM32L4_IRQ_FIRST+53) /* 53: UART5 global interrupt */
#define STM32L4_IRQ_TIM6 (STM32L4_IRQ_FIRST+54) /* 54: TIM6 global interrupt */
#define STM32L4_IRQ_DAC (STM32L4_IRQ_FIRST+54) /* 54: DAC1 and DAC2 underrun error interrupts */
#define STM32L4_IRQ_TIM7 (STM32L4_IRQ_FIRST+55) /* 55: TIM7 global interrupt */
#define STM32L4_IRQ_DMA2CH1 (STM32L4_IRQ_FIRST+56) /* 56: DMA2 Channel 1 global interrupt */
#define STM32L4_IRQ_DMA2CH2 (STM32L4_IRQ_FIRST+57) /* 57: DMA2 Channel 2 global interrupt */
#define STM32L4_IRQ_DMA2CH3 (STM32L4_IRQ_FIRST+58) /* 58: DMA2 Channel 3 global interrupt */
#define STM32L4_IRQ_DMA2CH4 (STM32L4_IRQ_FIRST+59) /* 59: DMA2 Channel 4 global interrupt */
#define STM32L4_IRQ_DMA2CH5 (STM32L4_IRQ_FIRST+60) /* 60: DMA2 Channel 5 global interrupt */
#define STM32L4_IRQ_DFSDM0 (STM32L4_IRQ_FIRST+61) /* 61: DFSDM0 global interrupt */
#define STM32L4_IRQ_DFSDM1 (STM32L4_IRQ_FIRST+62) /* 62: DFSDM1 global interrupt*/
#define STM32L4_IRQ_DFSDM2 (STM32L4_IRQ_FIRST+63) /* 63: DFSDM2 global interrupt */
#define STM32L4_IRQ_COMP (STM32L4_IRQ_FIRST+64) /* 64: COMP1/COMP2 interrupts */
#define STM32L4_IRQ_LPTIM1 (STM32L4_IRQ_FIRST+65) /* 65: LPTIM1 global interrupt */
#define STM32L4_IRQ_LPTIM2 (STM32L4_IRQ_FIRST+66) /* 66: LPTIM2 global interrupt */
#define STM32L4_IRQ_OTGFS (STM32L4_IRQ_FIRST+67) /* 67: USB On The Go FS global interrupt */
#define STM32L4_IRQ_DMA2CH6 (STM32L4_IRQ_FIRST+68) /* 68: DMA2 Channel 6 global interrupt */
#define STM32L4_IRQ_DMA2CH7 (STM32L4_IRQ_FIRST+69) /* 69: DMA2 Channel 7 global interrupt */
#define STM32L4_IRQ_LPUART1 (STM32L4_IRQ_FIRST+70) /* 70: Low power UART 1 global interrupt */
#define STM32L4_IRQ_QUADSPI (STM32L4_IRQ_FIRST+71) /* 71: QUADSPI global interrupt */
#define STM32L4_IRQ_I2C3EV (STM32L4_IRQ_FIRST+72) /* 72: I2C3 event interrupt */
#define STM32L4_IRQ_I2C3ER (STM32L4_IRQ_FIRST+73) /* 73: I2C3 error interrupt */
#define STM32L4_IRQ_SAI1 (STM32L4_IRQ_FIRST+74) /* 74: SAI1 global interrupt */
#define STM32L4_IRQ_SAI2 (STM32L4_IRQ_FIRST+75) /* 75: SAI2 global interrupt */
#define STM32L4_IRQ_SWPMI1 (STM32L4_IRQ_FIRST+76) /* 76: SWPMI1 global interrupt */
#define STM32L4_IRQ_TSC (STM32L4_IRQ_FIRST+77) /* 77: TSC global interrupt */
#define STM32_IRQ_RESERVED78 (STM32L4_IRQ_FIRST+78) /* 78: Reserved */
#define STM32_IRQ_RESERVED79 (STM32L4_IRQ_FIRST+79) /* 79: Reserved */
#define STM32L4_IRQ_RNG (STM32L4_IRQ_FIRST+80) /* 80: RNG global interrupt */
#define STM32L4_IRQ_FPU (STM32L4_IRQ_FIRST+81) /* 81: FPU global interrupt */
#define NR_INTERRUPTS 82
#define NR_VECTORS (STM32L4_IRQ_FIRST+NR_INTERRUPTS)
/* EXTI interrupts (Do not use IRQ numbers) */
#define NR_IRQS NR_VECTORS
/****************************************************************************************************
* Public Types
****************************************************************************************************/
/****************************************************************************************************
* Public Data
****************************************************************************************************/
#ifndef __ASSEMBLY__
#ifdef __cplusplus
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************************************
* Public Functions
****************************************************************************************************/
#undef EXTERN
#ifdef __cplusplus
}
#endif
#endif
#endif /* __ARCH_ARM_INCLUDE_STM32L4_STM32L4X5XX_IRQ_H */

12
arch/arm/include/stm32l4/stm32l4x6xx_irq.h
View file

@ -70,12 +70,12 @@
#define STM32L4_IRQ_EXTI2 (STM32L4_IRQ_FIRST+8) /* 8: EXTI Line 2 interrupt */
#define STM32L4_IRQ_EXTI3 (STM32L4_IRQ_FIRST+9) /* 9: EXTI Line 3 interrupt */
#define STM32L4_IRQ_EXTI4 (STM32L4_IRQ_FIRST+10) /* 10: EXTI Line 4 interrupt */
#define STM32L4_IRQ_DMA1CH1 (STM32L4_IRQ_FIRST+11) /* 12: DMA1 Channel 1 global interrupt */
#define STM32L4_IRQ_DMA1CH2 (STM32L4_IRQ_FIRST+12) /* 13: DMA1 Channel 2 global interrupt */
#define STM32L4_IRQ_DMA1CH3 (STM32L4_IRQ_FIRST+13) /* 14: DMA1 Channel 3 global interrupt */
#define STM32L4_IRQ_DMA1CH4 (STM32L4_IRQ_FIRST+14) /* 15: DMA1 Channel 4 global interrupt */
#define STM32L4_IRQ_DMA1CH5 (STM32L4_IRQ_FIRST+15) /* 16: DMA1 Channel 5 global interrupt */
#define STM32L4_IRQ_DMA1CH6 (STM32L4_IRQ_FIRST+16) /* 17: DMA1 Channel 6 global interrupt */
#define STM32L4_IRQ_DMA1CH1 (STM32L4_IRQ_FIRST+11) /* 11: DMA1 Channel 1 global interrupt */
#define STM32L4_IRQ_DMA1CH2 (STM32L4_IRQ_FIRST+12) /* 12: DMA1 Channel 2 global interrupt */
#define STM32L4_IRQ_DMA1CH3 (STM32L4_IRQ_FIRST+13) /* 13: DMA1 Channel 3 global interrupt */
#define STM32L4_IRQ_DMA1CH4 (STM32L4_IRQ_FIRST+14) /* 14: DMA1 Channel 4 global interrupt */
#define STM32L4_IRQ_DMA1CH5 (STM32L4_IRQ_FIRST+15) /* 15: DMA1 Channel 5 global interrupt */
#define STM32L4_IRQ_DMA1CH6 (STM32L4_IRQ_FIRST+16) /* 16: DMA1 Channel 6 global interrupt */
#define STM32L4_IRQ_DMA1CH7 (STM32L4_IRQ_FIRST+17) /* 17: DMA1 Channel 7 global interrupt */
#define STM32L4_IRQ_ADC12 (STM32L4_IRQ_FIRST+18) /* 18: ADC1 and ADC2 global interrupt */
#define STM32L4_IRQ_CAN1TX (STM32L4_IRQ_FIRST+19) /* 19: CAN1 TX interrupts */

6
arch/arm/src/a1x/a1x_serial.c
View file

@ -1,7 +1,7 @@
/****************************************************************************
* arch/arm/src/a1x/a1x_serial.c
*
* Copyright (C) 2013-2014 Gregory Nutt. All rights reserved.
* Copyright (C) 2013-2014, 2017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
@ -1035,7 +1035,7 @@ static int up_attach(struct uart_dev_s *dev)
/* Attach and enable the IRQ */
ret = irq_attach(priv->irq, uart_interrupt, priv);
ret = irq_attach(priv->irq, uart_interrupt, dev);
if (ret == OK)
{
/* Enable the interrupt (RX and TX interrupts are still disabled
@ -1080,7 +1080,7 @@ static void up_detach(struct uart_dev_s *dev)
static int uart_interrupt(int irq, void *context, void *arg)
{
struct uart_dev_s *dev = (struct uart_dev_s *)arg;
struct up_dev_s *priv = (struct up_dev_s *)arg;
struct up_dev_s *priv;
uint32_t status;
int passes;

72
arch/arm/src/imx1/imx_serial.c
View file

@ -1,8 +1,7 @@
/****************************************************************************
* arch/arm/src/imx1/imx_serial.c
* arch/arm/src/chip/imx_serial.c
*
* Copyright (C) 2009, 2012-2013 Gregory Nutt. All rights reserved.
* Copyright (C) 2009, 2012-2013, 2017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
@ -111,7 +110,6 @@ static int up_setup(struct uart_dev_s *dev);
static void up_shutdown(struct uart_dev_s *dev);
static int up_attach(struct uart_dev_s *dev);
static void up_detach(struct uart_dev_s *dev);
static inline struct uart_dev_s *up_mapirq(int irq);
static int up_interrupt(int irq, void *context, FAR void *arg);
static int up_ioctl(struct file *filep, int cmd, unsigned long arg);
static int up_receive(struct uart_dev_s *dev, uint32_t *status);
@ -753,13 +751,13 @@ static int up_attach(struct uart_dev_s *dev)
/* Attach and enable the IRQ */
#if defined(CONFIG_ARCH_CHIP_IMX1) || defined(CONFIG_ARCH_CHIP_IMXL)
ret = irq_attach(priv->rxirq, up_interrupt, NULL);
ret = irq_attach(priv->rxirq, up_interrupt, dev);
if (ret < 0)
{
return ret;
}
ret = irq_attach(priv->txirq, up_interrupt, NULL);
ret = irq_attach(priv->txirq, up_interrupt, dev);
if (ret < 0)
{
irq_detach(priv->rxirq);
@ -772,7 +770,7 @@ static int up_attach(struct uart_dev_s *dev)
up_enable_irq(priv->txirq);
#else
ret = irq_attach(priv->irq, up_interrupt, NULL);
ret = irq_attach(priv->irq, up_interrupt, dev);
if (ret == OK)
{
/* Enable the interrupt (RX and TX interrupts are still disabled
@ -810,60 +808,6 @@ static void up_detach(struct uart_dev_s *dev)
#endif
}
/****************************************************************************
* Name: up_mapirq
*
* Description:
* Map an IRQ number to internal UART state structure
*
****************************************************************************/
static inline struct uart_dev_s *up_mapirq(int irq)
{
struct uart_dev_s *dev;
switch (irq)
{
#ifdef CONFIG_IMX1_UART1
#if defined(CONFIG_ARCH_CHIP_IMX1) || defined(CONFIG_ARCH_CHIP_IMXL)
case IMX_IRQ_UART1RX:
case IMX_IRQ_UART1TX:
#else
case IMX_IRQ_UART1:
#endif
dev = &g_uart1port;
break;
#endif
#ifdef CONFIG_IMX1_UART2
#if defined(CONFIG_ARCH_CHIP_IMX1) || defined(CONFIG_ARCH_CHIP_IMXL)
case IMX_IRQ_UART2RX:
case IMX_IRQ_UART2TX:
#else
case IMX_IRQ_UART2:
#endif
dev = &g_uart2port;
break;
#endif
#ifdef CONFIG_IMX1_UART3
#if defined(CONFIG_ARCH_CHIP_IMX1) || defined(CONFIG_ARCH_CHIP_IMXL)
case IMX_IRQ_UART3RX:
case IMX_IRQ_UART3TX:
#else
case IMX_IRQ_UART3:
#endif
dev = &g_uart3port;
break;
#endif
default:
PANIC();
break;
}
return dev;
}
/****************************************************************************
* Name: up_interrupt (and front-ends)
*
@ -879,12 +823,12 @@ static inline struct uart_dev_s *up_mapirq(int irq)
static int up_interrupt(int irq, void *context, FAR void *arg)
{
struct uart_dev_s *dev;
struct up_dev_s *priv;
struct uart_dev_s *dev = (struct uart_dev_s *)arg;
struct up_dev_s *priv;
uint32_t usr1;
int passes = 0;
int passes = 0;
dev = up_mapirq(irq);
DEBUGASSERT(dev != NULL && dev->priv != NULL);
priv = (struct up_dev_s *)dev->priv;
/* Loop until there are no characters to be transferred or,

2
arch/arm/src/imx6/imx_serial.c
View file

@ -595,7 +595,7 @@ static int imx_attach(struct uart_dev_s *dev)
/* Attach and enable the IRQ */
ret = irq_attach(priv->irq, imx_interrupt, priv);
ret = irq_attach(priv->irq, imx_interrupt, dev);
if (ret == OK)
{
/* Configure as a (high) level interrupt */

7
arch/arm/src/kinetis/Make.defs
View file

@ -116,6 +116,7 @@ CHIP_CSRCS += kinetis_lowputc.c kinetis_pin.c kinetis_pingpio.c
CHIP_CSRCS += kinetis_serialinit.c kinetis_serial.c
CHIP_CSRCS += kinetis_start.c kinetis_uid.c kinetis_wdog.c
CHIP_CSRCS += kinetis_cfmconfig.c
CHIP_CSRCS += kinetis_mpuinit.c
# Configuration-dependent Kinetis files
@ -124,7 +125,7 @@ CHIP_CSRCS += kinetis_timerisr.c
endif
ifeq ($(CONFIG_BUILD_PROTECTED),y)
CHIP_CSRCS += kinetis_userspace.c kinetis_mpuinit.c
CHIP_CSRCS += kinetis_userspace.c
endif
ifeq ($(CONFIG_KINETIS_GPIOIRQ),y)
@ -139,6 +140,10 @@ ifeq ($(CONFIG_KINETIS_SDHC),y)
CHIP_CSRCS += kinetis_sdhc.c
endif
ifeq ($(CONFIG_SPI),y)
CHIP_CSRCS += kinetis_spi.c
endif
ifeq ($(CONFIG_USBDEV),y)
CHIP_CSRCS += kinetis_usbdev.c
endif

6
arch/arm/src/kinetis/chip/kinetis_dspi.h
View file

@ -140,7 +140,7 @@
#define SPI_MCR_PCSIS_SHIFT (16) /* Bits 16-21: Peripheral Chip Select x Inactive State */
#define SPI_MCR_PCSIS_MASK (0x3f << SPI_MCR_PCSIS_SHIFT)
# define SPI_MCR_PCSIS_CS(n) ((1 << (n)) << SPI_MCR_PCSIS_SHIFT)
/* Bits 22–23: Reserved */
/* Bits 22-23: Reserved */
#define SPI_MCR_ROOE (1 << 24) /* Bit 24: Receive FIFO Overflow Overwrite Enable */
#define SPI_MCR_PCSSE (1 << 25) /* Bit 25: Peripheral Chip Select Strobe Enable */
#define SPI_MCR_MTFE (1 << 26) /* Bit 26: Modified Timing Format Enable */
@ -165,6 +165,7 @@
#define SPI_CTARM_BR_SHIFT (0) /* Bits 0-3: Baud Rate Scaler */
#define SPI_CTARM_BR_MASK (15 << SPI_CTARM_BR_SHIFT)
# define SPI_CTARM_BR(n) ((((n) & 0xf)) << SPI_CTARM_BR_SHIFT)
# define SPI_CTARM_BR_2 (0 << SPI_CTARM_BR_SHIFT)
# define SPI_CTARM_BR_4 (1 << SPI_CTARM_BR_SHIFT)
# define SPI_CTARM_BR_6 (2 << SPI_CTARM_BR_SHIFT)
@ -205,6 +206,7 @@
# define SPI_CTARM_CSSCK_65536 (15 << SPI_CTARM_CSSCK_SHIFT)
#define SPI_CTARM_PBR_SHIFT (16) /* Bits 16-17: Baud Rate Prescaler */
#define SPI_CTARM_PBR_MASK (3 << SPI_CTARM_PBR_SHIFT)
# define SPI_CTARM_PBR(n) (((n) & 0x3) << SPI_CTARM_PBR_SHIFT)
# define SPI_CTARM_PBR_2 (0 << SPI_CTARM_PBR_SHIFT)
# define SPI_CTARM_PBR_3 (1 << SPI_CTARM_PBR_SHIFT)
# define SPI_CTARM_PBR_5 (2 << SPI_CTARM_PBR_SHIFT)
@ -231,6 +233,7 @@
/* Bits 25-26: See common bits above */
#define SPI_CTARM_FMSZ_SHIFT (27) /* Bits 27-30: Frame Size */
#define SPI_CTARM_FMSZ_MASK (15 << SPI_CTARM_FMSZ_SHIFT)
#define SPI_CTARM_FMSZ(n) ((((n) & 0xf)) << SPI_CTARM_FMSZ_SHIFT)
#define SPI_CTARM_DBR (1 << 31) /* Bit 31: Double Baud Rate */
/* DSPI Clock and Transfer Attributes Register (Slave Mode) */
@ -281,6 +284,7 @@
#define SPI_PUSHR_TXDATA_SHIFT (0) /* Bits 0-15: Transmit Data */
#define SPI_PUSHR_TXDATA_MASK (0xffff << SPI_PUSHR_TXDATA_SHIFT)
# define SPI_PUSHR_TXDATA(d) (((d) & 0xffff) << SPI_PUSHR_TXDATA_SHIFT)
#define SPI_PUSHR_PCS_SHIFT (16) /* Bits 16-21: Select PCS signals to assert */
#define SPI_PUSHR_PCS_MASK (0x3f << SPI_PUSHR_PCS_SHIFT)
# define SPI_PUSHR_PCS(n) ((1 << (n)) << SPI_PUSHR_PCS_SHIFT)

8
arch/arm/src/kinetis/chip/kinetis_sim.h
View file

@ -1057,7 +1057,7 @@
#if defined(KINETIS_SIM_HAS_CLKDIV1_OUTDIV4)
# define SIM_CLKDIV1_OUTDIV4_SHIFT (16) /* Bits 16-19: Clock 4 output divider value */
# define SIM_CLKDIV1_OUTDIV4_MASK (15 << SIM_CLKDIV1_OUTDIV4_SHIFT)
# define SIM_CLKDIV1_OUTDIV4(n) ((uint32_t)((n)-1) << SIM_CLKDIV1_OUTDIV4_SHIFT) /* n=1..16 */
# define SIM_CLKDIV1_OUTDIV4(n) ((uint32_t)(((n)-1) & 0xf) << SIM_CLKDIV1_OUTDIV4_SHIFT) /* n=1..16 */
# define SIM_CLKDIV1_OUTDIV4_1 (0 << SIM_CLKDIV1_OUTDIV4_SHIFT) /* Divide by 1 */
# define SIM_CLKDIV1_OUTDIV4_2 (1 << SIM_CLKDIV1_OUTDIV4_SHIFT) /* Divide by 2 */
# define SIM_CLKDIV1_OUTDIV4_3 (2 << SIM_CLKDIV1_OUTDIV4_SHIFT) /* Divide by 3 */
@ -1078,7 +1078,7 @@
#if defined(KINETIS_SIM_HAS_CLKDIV1_OUTDIV3)
# define SIM_CLKDIV1_OUTDIV3_SHIFT (20) /* Bits 20-23: Clock 3 output divider value */
# define SIM_CLKDIV1_OUTDIV3_MASK (15 << SIM_CLKDIV1_OUTDIV3_SHIFT)
# define SIM_CLKDIV1_OUTDIV3(n) ((uint32_t)((n)-1) << SIM_CLKDIV1_OUTDIV3_SHIFT) /* n=1..16 */
# define SIM_CLKDIV1_OUTDIV3(n) ((uint32_t)(((n)-1) & 0xf) << SIM_CLKDIV1_OUTDIV3_SHIFT) /* n=1..16 */
# define SIM_CLKDIV1_OUTDIV3_1 (0 << SIM_CLKDIV1_OUTDIV3_SHIFT) /* Divide by 1 */
# define SIM_CLKDIV1_OUTDIV3_2 (1 << SIM_CLKDIV1_OUTDIV3_SHIFT) /* Divide by 2 */
# define SIM_CLKDIV1_OUTDIV3_3 (2 << SIM_CLKDIV1_OUTDIV3_SHIFT) /* Divide by 3 */
@ -1099,7 +1099,7 @@
#if defined(KINETIS_SIM_HAS_CLKDIV1_OUTDIV2)
# define SIM_CLKDIV1_OUTDIV2_SHIFT (24) /* Bits 24-27: Clock 2 output divider value */
# define SIM_CLKDIV1_OUTDIV2_MASK (15 << SIM_CLKDIV1_OUTDIV2_SHIFT)
# define SIM_CLKDIV1_OUTDIV2(n) ((uint32_t)((n)-1) << SIM_CLKDIV1_OUTDIV2_SHIFT) /* n=1..16 */
# define SIM_CLKDIV1_OUTDIV2(n) ((uint32_t)(((n)-1) & 0xf) << SIM_CLKDIV1_OUTDIV2_SHIFT) /* n=1..16 */
# define SIM_CLKDIV1_OUTDIV2_1 (0 << SIM_CLKDIV1_OUTDIV2_SHIFT) /* Divide by 1 */
# define SIM_CLKDIV1_OUTDIV2_2 (1 << SIM_CLKDIV1_OUTDIV2_SHIFT) /* Divide by 2 */
# define SIM_CLKDIV1_OUTDIV2_3 (2 << SIM_CLKDIV1_OUTDIV2_SHIFT) /* Divide by 3 */
@ -1119,7 +1119,7 @@
#endif
#define SIM_CLKDIV1_OUTDIV1_SHIFT (28) /* Bits 28-31: Clock 1 output divider value */
#define SIM_CLKDIV1_OUTDIV1_MASK (15 << SIM_CLKDIV1_OUTDIV1_SHIFT)
# define SIM_CLKDIV1_OUTDIV1(n) ((uint32_t)((n)-1) << SIM_CLKDIV1_OUTDIV1_SHIFT) /* n=1..16 */
# define SIM_CLKDIV1_OUTDIV1(n) ((uint32_t)(((n)-1) & 0xf) << SIM_CLKDIV1_OUTDIV1_SHIFT) /* n=1..16 */
# define SIM_CLKDIV1_OUTDIV1_1 (0 << SIM_CLKDIV1_OUTDIV1_SHIFT) /* Divide by 1 */
# define SIM_CLKDIV1_OUTDIV1_2 (1 << SIM_CLKDIV1_OUTDIV1_SHIFT) /* Divide by 2 */
# define SIM_CLKDIV1_OUTDIV1_3 (2 << SIM_CLKDIV1_OUTDIV1_SHIFT) /* Divide by 3 */

4
arch/arm/src/kinetis/kinetis_lpserial.c
View file

@ -63,11 +63,9 @@
#include "up_arch.h"
#include "up_internal.h"
#include "kinetis_config.h"
#include "chip.h"
#include "kinetis.h"
#include "chip/kinetis_lpuart.h"
#include "chip/kinetis_pinmux.h"
#include "kinetis.h"
/****************************************************************************
* Pre-processor Definitions

20
arch/arm/src/kinetis/kinetis_mpuinit.c
View file

@ -45,6 +45,7 @@
#include "mpu.h"
#include "kinetis_mpuinit.h"
#include "chip/kinetis_mpu.h"
#if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_ARM_MPU)
@ -120,5 +121,24 @@ void kinetis_mpu_uheap(uintptr_t start, size_t size)
mpu_user_intsram(start, size);
}
#elif defined(KINETIS_MPU)
/****************************************************************************
* Name: kinetis_mpudisable
*
* Description:
* Configure the MPU to permit All buss masters access to all resources.
*
****************************************************************************/
void kinetis_mpudisable(void)
{
uint32_t regval;
regval = getreg32(KINETIS_MPU_CESR);
regval &= ~MPU_CESR_VLD;
putreg32(regval, KINETIS_MPU_CESR);
}
#endif /* CONFIG_BUILD_PROTECTED && CONFIG_ARM_MPU */

12
arch/arm/src/kinetis/kinetis_mpuinit.h
View file

@ -61,6 +61,18 @@ void kinetis_mpuinitialize(void);
# define kinetis_mpuinitialize()
#endif
/****************************************************************************
* Name: kinetis_mpudisable
*
* Description:
* Configure the MPU to permit All buss masters access to all resources.
*
****************************************************************************/
#if !defined(CONFIG_BUILD_PROTECTED) && defined(KINETIS_MPU)
void kinetis_mpudisable(void);
#endif
/****************************************************************************
* Name: kinetis_mpu_uheap
*

1242
arch/arm/src/kinetis/kinetis_spi.c Normal file
View file

File diff suppressed because it is too large Load diff

7
arch/arm/src/kinetis/kinetis_start.c
View file

@ -51,6 +51,7 @@
#include "kinetis.h"
#include "chip/kinetis_smc.h"
#include "kinetis_mpuinit.h"
#include "kinetis_userspace.h"
#ifdef CONFIG_ARCH_FPU
@ -341,6 +342,12 @@ void __start(void)
#ifdef CONFIG_BUILD_PROTECTED
kinetis_userspace();
#else
# ifdef KINETIS_MPU
/* Disable the MPU so that all master may access all buses */
kinetis_mpudisable();
# endif
#endif
/* Initialize other on-board resources */

834
arch/arm/src/kinetis/kinetis_usbdev.c
View file

File diff suppressed because it is too large Load diff

2
arch/arm/src/kinetis/kinetis_usbotg.h
View file

@ -66,6 +66,4 @@ struct usbotg_bdtentry_s
struct usbdev_s;
int kinetis_usbpullup(FAR struct usbdev_s *dev, bool enable);
void kinetis_usbsuspend(FAR struct usbdev_s *dev, bool resume);
void khci_usbattach(void);
#endif /* __ARCH_ARM_SRC_KINETIS_KINETIS_USBOTG_H */

11
arch/arm/src/lpc31xx/lpc31_serial.c
View file

@ -1,7 +1,7 @@
/****************************************************************************
* arch/arm/src/lpc31xx/lpc31_serial.c
*
* Copyright (C) 2009, 2012-2013 Gregory Nutt. All rights reserved.
* Copyright (C) 2009, 2012-2013, 2017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
@ -444,7 +444,7 @@ static int up_attach(struct uart_dev_s *dev)
/* Attach and enable the IRQ */
ret = irq_attach(LPC31_IRQ_UART, up_interrupt, NULL);
ret = irq_attach(LPC31_IRQ_UART, up_interrupt, dev);
if (ret == OK)
{
/* Enable the interrupt (RX and TX interrupts are still disabled
@ -453,6 +453,7 @@ static int up_attach(struct uart_dev_s *dev)
up_enable_irq(LPC31_IRQ_UART);
}
return ret;
}
@ -484,9 +485,9 @@ static void up_detach(struct uart_dev_s *dev)
static int up_interrupt(int irq, void *context, FAR void *arg)
{
struct uart_dev_s *dev = &g_uartport;
uint8_t status;
int passes;
struct uart_dev_s *dev = (struct uart_dev_s *)arg;
uint8_t status;
int passes;
/* Loop until there are no characters to be transferred or,
* until we have been looping for a long time.

9
arch/arm/src/sama5/sam_dbgu.c
View file

@ -287,7 +287,7 @@ static int dbgu_attach(struct uart_dev_s *dev)
/* Attach and enable the IRQ */
ret = irq_attach(SAM_IRQ_DBGU, dbgu_interrupt, NULL);
ret = irq_attach(SAM_IRQ_DBGU, dbgu_interrupt, dev);
if (ret == OK)
{
/* Enable the interrupt (RX and TX interrupts are still disabled
@ -330,13 +330,16 @@ static void dbgu_detach(struct uart_dev_s *dev)
static int dbgu_interrupt(int irq, void *context, FAR void *arg)
{
struct uart_dev_s *dev = &g_dbgu_port;
struct dbgu_dev_s *priv = (struct dbgu_dev_s *)dev->priv;
struct uart_dev_s *dev = (struct uart_dev_s *)arg;
struct dbgu_dev_s *priv;
uint32_t pending;
uint32_t imr;
int passes;
bool handled;
DEBUGASSERT(dev != NULL && dev->priv != NULL);
priv = (struct dbgu_dev_s *)dev->priv;
/* Loop until there are no characters to be transferred or, until we have
* been looping for a long time.
*/

4
arch/arm/src/stm32/Make.defs
View file

@ -225,6 +225,10 @@ ifeq ($(CONFIG_OPAMP),y)
CHIP_CSRCS += stm32_opamp.c
endif
ifeq ($(CONFIG_HRTIM),y)
CHIP_CSRCS += stm32_hrtim.c
endif
ifeq ($(CONFIG_STM32_1WIREDRIVER),y)
CHIP_CSRCS += stm32_1wire.c
endif

462
arch/arm/src/stm32/chip/stm32f33xxx_hrtim.h
View file

@ -67,310 +67,190 @@
/* Register Offsets *********************************************************************************/
/* Register Offsets for HRTIM Master Timer */
/* Register Offsets Common for Master Timer and Timer X */
#define STM32_HRTIM_MASTER_MCR 0x0000 /* HRTIM Master Timer Control Register */
#define STM32_HRTIM_MASTER_MISR 0x0004 /* HRTIM Master Timer Interrupt Status Register */
#define STM32_HRTIM_MASTER_MICR 0x0008 /* HRTIM Master Timer Interrupt Clear Register */
#define STM32_HRTIM_MASTER_MDIER 0x000C /* HRTIM Master Timer DMA/Interrupt Enable Register */
#define STM32_HRTIM_MASTER_MCNTR 0x0010 /* HRTIM Master Timer Counter Register */
#define STM32_HRTIM_MASTER_MPER 0x0014 /* HRTIM Master Timer Period Register */
#define STM32_HRTIM_MASTER_MREP 0x0018 /* HRTIM Master Timer Repetition Register */
#define STM32_HRTIM_MASTER_MCMP1R 0x001C /* HRTIM Master Timer Compare 1 Register */
#define STM32_HRTIM_MASTER_MCMP2R 0x0024 /* HRTIM Master Timer Compare 2 Register */
#define STM32_HRTIM_MASTER_MCMP3R 0x0028 /* HRTIM Master Timer Compare 3 Register */
#define STM32_HRTIM_MASTER_MCMP4R 0x002C /* HRTIM Master Timer Compare 4 Register */
#define STM32_HRTIM_TIM_CR_OFFSET 0x0000 /* HRTIM Timer Control Register */
#define STM32_HRTIM_TIM_ISR_OFFSET 0x0004 /* HRTIM Timer Interrupt Status Register */
#define STM32_HRTIM_TIM_ICR_OFFSET 0x0008 /* HRTIM Timer Interrupt Clear Register */
#define STM32_HRTIM_TIM_DIER_OFFSET 0x000C /* HRTIM Timer DMA/Interrupt Enable Register */
#define STM32_HRTIM_TIM_CNTR_OFFSET 0x0010 /* HRTIM Timer Counter Register */
#define STM32_HRTIM_TIM_PER_OFFSET 0x0014 /* HRTIM Timer Period Register */
#define STM32_HRTIM_TIM_REPR_OFFSET 0x0018 /* HRTIM Timer Repetition Register */
#define STM32_HRTIM_TIM_CMP1R_OFFSET 0x001C /* HRTIM Timer Compare 1 Register */
#define STM32_HRTIM_TIM_CMP2R_OFFSET 0x0024 /* HRTIM Timer Compare 2 Register */
#define STM32_HRTIM_TIM_CMP3R_OFFSET 0x0028 /* HRTIM Timer Compare 3 Register */
#define STM32_HRTIM_TIM_CMP4R_OFFSET 0x002C /* HRTIM Timer Compare 4 Register */
/* Register Offsets for HRTIM Timers A-E */
/* Register offsets Specific for Timer A-E */
#define STM32_HRTIM_TIMX_CR 0x0000 /* HRTIM Timer X Control Register */
#define STM32_HRTIM_TIMX_ISR 0x0004 /* HRTIM Timer X Interrupt Status Register */
#define STM32_HRTIM_TIMX_ICR 0x0008 /* HRTIM Timer X Interrupt Clear Register */
#define STM32_HRTIM_TIMX_DIER 0x000C /* HRTIM Timer X DMA/Interrupt Enable Register */
#define STM32_HRTIM_TIMX_CNTR 0x0010 /* HRTIM Timer X Counter Register */
#define STM32_HRTIM_TIMX_PER 0x0014 /* HRTIM Timer X Period Register */
#define STM32_HRTIM_TIMX_REP 0x0018 /* HRTIM Timer X Repetition Register */
#define STM32_HRTIM_TIMX_CMP1R 0x001C /* HRTIM Timer X Compare 1 Register */
#define STM32_HRTIM_TIMX_CMP1CR 0x0020 /* HRTIM Timer X Compare 1 Compound Register */
#define STM32_HRTIM_TIMX_CMP2R 0x0024 /* HRTIM Timer X Compare 2 Register */
#define STM32_HRTIM_TIMX_CMP3R 0x0028 /* HRTIM Timer X Compare 3 Register */
#define STM32_HRTIM_TIMX_CMP4R 0x002C /* HRTIM Timer X Compare 4 Register */
#define STM32_HRTIM_TIMX_CPT1R 0x0030 /* HRTIM Timer X Capture 1 Register */
#define STM32_HRTIM_TIMX_CPT2R 0x0034 /* HRTIM Timer X Capture 2 Register */
#define STM32_HRTIM_TIMX_DTR 0x0038 /* HRTIM Timer X Deadtime Register */
#define STM32_HRTIM_TIMX_SET1R 0x003C /* HRTIM Timer X Output1 Set Register */
#define STM32_HRTIM_TIMX_RST1R 0x0040 /* HRTIM Timer X Output1 Reset Register */
#define STM32_HRTIM_TIMX_SET2R 0x0044 /* HRTIM Timer X Output2 Set Register */
#define STM32_HRTIM_TIMX_RST2R 0x0048 /* HRTIM Timer X Output2 Reset Register */
#define STM32_HRTIM_TIMX_EEFR1 0x004C /* HRTIM Timer X External Event Filtering Register 1 */
#define STM32_HRTIM_TIMX_EEFR2 0x0050 /* HRTIM Timer X External Event Filtering Register 2 */
#define STM32_HRTIM_TIMX_RSTR 0x0054 /* HRTIM Timer X Reset Register */
#define STM32_HRTIM_TIMX_CHPR 0x0058 /* HRTIM Timer X Chopper Register */
#define STM32_HRTIM_TIMX_CPT1CR 0x005C /* HRTIM Timer X Capture 1 Control Register */
#define STM32_HRTIM_TIMX_CPT2CR 0x0060 /* HRTIM Timer X Capture 2 Control Register */
#define STM32_HRTIM_TIMX_OUTR 0x0064 /* HRTIM Timer X Output Register */
#define STM32_HRTIM_TIMX_FLTR 0x0068 /* HRTIM Timer X Fault Register */
#define STM32_HRTIM_TIM_CMP1CR_OFFSET 0x0020 /* HRTIM Timer Compare 1 Compound Register */
#define STM32_HRTIM_TIM_CPT1R_OFFSET 0x0030 /* HRTIM Timer Capture 1 Register */
#define STM32_HRTIM_TIM_CPT2R_OFFSET 0x0034 /* HRTIM Timer Capture 2 Register */
#define STM32_HRTIM_TIM_DTR_OFFSET 0x0038 /* HRTIM Timer Deadtime Register */
#define STM32_HRTIM_TIM_SET1R_OFFSET 0x003C /* HRTIM Timer Output1 Set Register */
#define STM32_HRTIM_TIM_RST1R_OFFSET 0x0040 /* HRTIM Timer Output1 Reset Register */
#define STM32_HRTIM_TIM_SET2R_OFFSET 0x0044 /* HRTIM Timer Output2 Set Register */
#define STM32_HRTIM_TIM_RST2R_OFFSET 0x0048 /* HRTIM Timer Output2 Reset Register */
#define STM32_HRTIM_TIM_EEFR1_OFFSET 0x004C /* HRTIM Timer External Event Filtering Register 1 */
#define STM32_HRTIM_TIM_EEFR2_OFFSET 0x0050 /* HRTIM Timer External Event Filtering Register 2 */
#define STM32_HRTIM_TIM_RSTR_OFFSET 0x0054 /* HRTIM Timer Reset Register */
#define STM32_HRTIM_TIM_CHPR_OFFSET 0x0058 /* HRTIM Timer Chopper Register */
#define STM32_HRTIM_TIM_CPT1CR_OFFSET 0x005C /* HRTIM Timer Capture 1 Control Register */
#define STM32_HRTIM_TIM_CPT2CR_OFFSET 0x0060 /* HRTIM Timer Capture 2 Control Register */
#define STM32_HRTIM_TIM_OUTR_OFFSET 0x0064 /* HRTIM Timer Output Register */
#define STM32_HRTIM_TIM_FLTR_OFFSET 0x0068 /* HRTIM Timer Fault Register */
/* Register Offset for HRTIM Common */
#define STM32_HRTIM_CMN_CR1 0x0000 /* HRTIM Control Register 1 */
#define STM32_HRTIM_CMN_CR2 0x0004 /* HRTIM Control Register 2 */
#define STM32_HRTIM_CMN_ISR 0x0008 /* HRTIM Interrupt Status Register */
#define STM32_HRTIM_CMN_ICR 0x000C /* HRTIM Interrupt Clear Register */
#define STM32_HRTIM_CMN_IER 0x0010 /* HRTIM Interrupt Enable Register */
#define STM32_HRTIM_CMN_OENR 0x0014 /* HRTIM Output Enable Register */
#define STM32_HRTIM_CMN_DISR 0x0018 /* HRTIM Output Disable Register */
#define STM32_HRTIM_CMN_ODSR 0x001C /* HRTIM Output Disable Status Register */
#define STM32_HRTIM_CMN_BMCR 0x0020 /* HRTIM Burst Mode Control Register */
#define STM32_HRTIM_CMN_BMTRGR 0x0024 /* HRTIM Burst Mode Trigger Register */
#define STM32_HRTIM_CMN_BMCMPR 0x0028 /* HRTIM Burst Mode Compare Register */
#define STM32_HRTIM_CMN_BMPER 0x002C /* HRTIM Burst Mode Period Register */
#define STM32_HRTIM_CMN_EECR1 0x0030 /* HRTIM Timer External Event Control Register 1 */
#define STM32_HRTIM_CMN_EECR2 0x0034 /* HRTIM Timer External Event Control Register 2 */
#define STM32_HRTIM_CMN_EECR3 0x0038 /* HRTIM Timer External Event Control Register 3 */
#define STM32_HRTIM_CMN_ADC1R 0x003C /* HRTIM ADC Trigger 1 Register */
#define STM32_HRTIM_CMN_ADC2R 0x0040 /* HRTIM ADC Trigger 2 Register */
#define STM32_HRTIM_CMN_ADC3R 0x0044 /* HRTIM ADC Trigger 3 Register */
#define STM32_HRTIM_CMN_ADC4R 0x0048 /* HRTIM ADC Trigger 4 Register */
#define STM32_HRTIM_CMN_DLLCR 0x004C /* HRTIM DLL Control Register */
#define STM32_HRTIM_CMN_FLTINR1 0x0050 /* HRTIM Fault Input Register 1 */
#define STM32_HRTIM_CMN_FLTINR2 0x0054 /* HRTIM Fault Input Register 2 */
#define STM32_HRTIM_CMN_BDMUPDR 0x0058 /* HRTIM Master Timer Update Register */
#define STM32_HRTIM_CMN_BDTAUPR 0x005C /* HRTIM Timer A Update Register */
#define STM32_HRTIM_CMN_BDTBUPR 0x0060 /* HRTIM Timer B Update Register */
#define STM32_HRTIM_CMN_BDTCUPR 0x0064 /* HRTIM Timer C Update Register */
#define STM32_HRTIM_CMN_BDTDUPR 0x0068 /* HRTIM Timer D Update Register */
#define STM32_HRTIM_CMN_BDTEUPR 0x006C /* HRTIM Timer E Update Register */
#define STM32_HRTIM_CMN_BDMADR 0x0070 /* HRTIM DMA Data Register */
#define STM32_HRTIM_CMN_CR1_OFFSET 0x0000 /* HRTIM Control Register 1 */
#define STM32_HRTIM_CMN_CR2_OFFSET 0x0004 /* HRTIM Control Register 2 */
#define STM32_HRTIM_CMN_ISR_OFFSET 0x0008 /* HRTIM Interrupt Status Register */
#define STM32_HRTIM_CMN_ICR_OFFSET 0x000C /* HRTIM Interrupt Clear Register */
#define STM32_HRTIM_CMN_IER_OFFSET 0x0010 /* HRTIM Interrupt Enable Register */
#define STM32_HRTIM_CMN_OENR_OFFSET 0x0014 /* HRTIM Output Enable Register */
#define STM32_HRTIM_CMN_DISR_OFFSET 0x0018 /* HRTIM Output Disable Register */
#define STM32_HRTIM_CMN_ODSR_OFFSET 0x001C /* HRTIM Output Disable Status Register */
#define STM32_HRTIM_CMN_BMCR_OFFSET 0x0020 /* HRTIM Burst Mode Control Register */
#define STM32_HRTIM_CMN_BMTRGR_OFFSET 0x0024 /* HRTIM Burst Mode Trigger Register */
#define STM32_HRTIM_CMN_BMCMPR_OFFSET 0x0028 /* HRTIM Burst Mode Compare Register */
#define STM32_HRTIM_CMN_BMPER_OFFSET 0x002C /* HRTIM Burst Mode Period Register */
#define STM32_HRTIM_CMN_EECR1_OFFSET 0x0030 /* HRTIM Timer External Event Control Register 1 */
#define STM32_HRTIM_CMN_EECR2_OFFSET 0x0034 /* HRTIM Timer External Event Control Register 2 */
#define STM32_HRTIM_CMN_EECR3_OFFSET 0x0038 /* HRTIM Timer External Event Control Register 3 */
#define STM32_HRTIM_CMN_ADC1R_OFFSET 0x003C /* HRTIM ADC Trigger 1 Register */
#define STM32_HRTIM_CMN_ADC2R_OFFSET 0x0040 /* HRTIM ADC Trigger 2 Register */
#define STM32_HRTIM_CMN_ADC3R_OFFSET 0x0044 /* HRTIM ADC Trigger 3 Register */
#define STM32_HRTIM_CMN_ADC4R_OFFSET 0x0048 /* HRTIM ADC Trigger 4 Register */
#define STM32_HRTIM_CMN_DLLCR_OFFSET 0x004C /* HRTIM DLL Control Register */
#define STM32_HRTIM_CMN_FLTINR1_OFFSET 0x0050 /* HRTIM Fault Input Register 1 */
#define STM32_HRTIM_CMN_FLTINR2_OFFSET 0x0054 /* HRTIM Fault Input Register 2 */
#define STM32_HRTIM_CMN_BDMUPDR_OFFSET 0x0058 /* HRTIM Master Timer Update Register */
#define STM32_HRTIM_CMN_BDTAUPR_OFFSET 0x005C /* HRTIM Timer A Update Register */
#define STM32_HRTIM_CMN_BDTBUPR_OFFSET 0x0060 /* HRTIM Timer B Update Register */
#define STM32_HRTIM_CMN_BDTCUPR_OFFSET 0x0064 /* HRTIM Timer C Update Register */
#define STM32_HRTIM_CMN_BDTDUPR_OFFSET 0x0068 /* HRTIM Timer D Update Register */
#define STM32_HRTIM_CMN_BDTEUPR_OFFSET 0x006C /* HRTIM Timer E Update Register */
#define STM32_HRTIM_CMN_BDMADR_OFFSET 0x0070 /* HRTIM DMA Data Register */
/* Register Addresses *******************************************************************************/
/* HRTIM1 Master Timer */
#define STM32_HRTIM1_MASTER_MCR (STM32_HRTIM_MASTER_MCR+STM32_HRTIM1_MASTER_BASE)
#define STM32_HRTIM1_MASTER_MISR (STM32_HRTIM_MASTER_MISR+STM32_HRTIM1_MASTER_BASE)
#define STM32_HRTIM1_MASTER_MICR (STM32_HRTIM_MASTER_MICR+STM32_HRTIM1_MASTER_BASE)
#define STM32_HRTIM1_MASTER_MDIER (STM32_HRTIM_MASTER_MDIER+STM32_HRTIM1_MASTER_BASE)
#define STM32_HRTIM1_MASTER_MCNTR (STM32_HRTIM_MASTER_MCNTR+STM32_HRTIM1_MASTER_BASE)
#define STM32_HRTIM1_MASTER_MPER (STM32_HRTIM_MASTER_MPER+STM32_HRTIM1_MASTER_BASE)
#define STM32_HRTIM1_MASTER_MREP (STM32_HRTIM_MASTER_MREP+STM32_HRTIM1_MASTER_BASE)
#define STM32_HRTIM1_MASTER_MCMP1R (STM32_HRTIM_MASTER_MCMP1R+STM32_HRTIM1_MASTER_BASE)
#define STM32_HRTIM1_MASTER_MCMP2R (STM32_HRTIM_MASTER_MCMP2R+STM32_HRTIM1_MASTER_BASE)
#define STM32_HRTIM1_MASTER_MCMP3R (STM32_HRTIM_MASTER_MCMP3R+STM32_HRTIM1_MASTER_BASE)
#define STM32_HRTIM1_MASTER_MCMP4R (STM32_HRTIM_MASTER_MCMP4R+STM32_HRTIM1_MASTER_BASE)
/* HRTIM1 Timer A */
/* remove ? */
#define STM32_HRTIM1_TIMERA_CR (STM32_HRTIM_TIMERA_CR+STM32_HRTIM1_TIMERA_BASE)
#define STM32_HRTIM1_TIMERA_ISR (STM32_HRTIM_TIMERA_ISR+STM32_HRTIM1_TIMERA_BASE)
#define STM32_HRTIM1_TIMERA_ICR (STM32_HRTIM_TIMERA_ICR+STM32_HRTIM1_TIMERA_BASE)
#define STM32_HRTIM1_TIMERA_DIER (STM32_HRTIM_TIMERA_DIER+STM32_HRTIM1_TIMERA_BASE)
#define STM32_HRTIM1_TIMERA_CNTR (STM32_HRTIM_TIMERA_CNTR+STM32_HRTIM1_TIMERA_BASE)
#define STM32_HRTIM1_TIMERA_PER (STM32_HRTIM_TIMERA_PER+STM32_HRTIM1_TIMERA_BASE)
#define STM32_HRTIM1_TIMERA_REP (STM32_HRTIM_TIMERA_REP+STM32_HRTIM1_TIMERA_BASE)
#define STM32_HRTIM1_TIMERA_CMP1R (STM32_HRTIM_TIMERA_CMP1R+STM32_HRTIM1_TIMERA_BASE)
#define STM32_HRTIM1_TIMERA_CMP1CR (STM32_HRTIM_TIMERA_CMP1CR+STM32_HRTIM1_TIMERA_BASE)
#define STM32_HRTIM1_TIMERA_CMP2R (STM32_HRTIM_TIMERA_CMP2R+STM32_HRTIM1_TIMERA_BASE)
#define STM32_HRTIM1_TIMERA_CMP3R (STM32_HRTIM_TIMERA_CMP3R+STM32_HRTIM1_TIMERA_BASE)
#define STM32_HRTIM1_TIMERA_CMP4R (STM32_HRTIM_TIMERA_CMP4R+STM32_HRTIM1_TIMERA_BASE)
#define STM32_HRTIM1_TIMERA_CPT1R (STM32_HRTIM_TIMERA_CMPT1R+STM32_HRTIM1_TIMERA_BASE)
#define STM32_HRTIM1_TIMERA_CPT2R (STM32_HRTIM_TIMERA_CMPT2R+STM32_HRTIM1_TIMERA_BASE)
#define STM32_HRTIM1_TIMERA_DTR (STM32_HRTIM_TIMERA_DTR+STM32_HRTIM1_TIMERA_BASE)
#define STM32_HRTIM1_TIMERA_SET1R (STM32_HRTIM_TIMERA_SET1R+STM32_HRTIM1_TIMERA_BASE)
#define STM32_HRTIM1_TIMERA_RST1R (STM32_HRTIM_TIMERA_RST1R+STM32_HRTIM1_TIMERA_BASE)
#define STM32_HRTIM1_TIMERA_SET2R (STM32_HRTIM_TIMERA_SET2R+STM32_HRTIM1_TIMERA_BASE)
#define STM32_HRTIM1_TIMERA_RST2R (STM32_HRTIM_TIMERA_RST2R+STM32_HRTIM1_TIMERA_BASE)
#define STM32_HRTIM1_TIMERA_EEFR1 (STM32_HRTIM_TIMERA_EEFR1+STM32_HRTIM1_TIMERA_BASE)
#define STM32_HRTIM1_TIMERA_EEFR2 (STM32_HRTIM_TIMERA_EEFR2+STM32_HRTIM1_TIMERA_BASE)
#define STM32_HRTIM1_TIMERA_RSTR (STM32_HRTIM_TIMERA_RSTR+STM32_HRTIM1_TIMERA_BASE)
#define STM32_HRTIM1_TIMERA_CHPR (STM32_HRTIM_TIMERA_CHPR+STM32_HRTIM1_TIMERA_BASE)
#define STM32_HRTIM1_TIMERA_CPT1CR (STM32_HRTIM_TIMERA_CPT1CR+STM32_HRTIM1_TIMERA_BASE)
#define STM32_HRTIM1_TIMERA_CPT2CR (STM32_HRTIM_TIMERA_CPT2CR+STM32_HRTIM1_TIMERA_BASE)
#define STM32_HRTIM1_TIMERA_OUTR (STM32_HRTIM_TIMERA_OUTR+STM32_HRTIM1_TIMERA_BASE)
#define STM32_HRTIM1_TIMERA_FLTR (STM32_HRTIM_TIMERA_FLTR+STM32_HRTIM1_TIMERA_BASE)
#define STM32_HRTIM1_TIMERA_CR (STM32_HRTIM_TIM_CR_OFFSET+STM32_HRTIM1_TIMERA_BASE)
#define STM32_HRTIM1_TIMERA_ISR (STM32_HRTIM_TIM_ISR_OFFSET+STM32_HRTIM1_TIMERA_BASE)
#define STM32_HRTIM1_TIMERA_ICR (STM32_HRTIM_TIM_ICR_OFFSET+STM32_HRTIM1_TIMERA_BASE)
#define STM32_HRTIM1_TIMERA_DIER (STM32_HRTIM_TIM_DIER_OFFSET+STM32_HRTIM1_TIMERA_BASE)
#define STM32_HRTIM1_TIMERA_CNTR (STM32_HRTIM_TIM_CNTR_OFFSET+STM32_HRTIM1_TIMERA_BASE)
#define STM32_HRTIM1_TIMERA_PER (STM32_HRTIM_TIM_PER_OFFSET+STM32_HRTIM1_TIMERA_BASE)
#define STM32_HRTIM1_TIMERA_REP (STM32_HRTIM_TIM_REP_OFFSET+STM32_HRTIM1_TIMERA_BASE)
#define STM32_HRTIM1_TIMERA_CMP1R (STM32_HRTIM_TIM_CMP1R_OFFSET+STM32_HRTIM1_TIMERA_BASE)
#define STM32_HRTIM1_TIMERA_CMP1CR (STM32_HRTIM_TIM_CMP1CR_OFFSET+STM32_HRTIM1_TIMERA_BASE)
#define STM32_HRTIM1_TIMERA_CMP2R (STM32_HRTIM_TIM_CMP2R_OFFSET+STM32_HRTIM1_TIMERA_BASE)
#define STM32_HRTIM1_TIMERA_CMP3R (STM32_HRTIM_TIM_CMP3R_OFFSET+STM32_HRTIM1_TIMERA_BASE)
#define STM32_HRTIM1_TIMERA_CMP4R (STM32_HRTIM_TIM_CMP4R_OFFSET+STM32_HRTIM1_TIMERA_BASE)
#define STM32_HRTIM1_TIMERA_CPT1R (STM32_HRTIM_TIM_CMPT1R_OFFSET+STM32_HRTIM1_TIMERA_BASE)
#define STM32_HRTIM1_TIMERA_CPT2R (STM32_HRTIM_TIM_CMPT2R_OFFSET+STM32_HRTIM1_TIMERA_BASE)
#define STM32_HRTIM1_TIMERA_DTR (STM32_HRTIM_TIM_DTR_OFFSET+STM32_HRTIM1_TIMERA_BASE)
#define STM32_HRTIM1_TIMERA_SET1R (STM32_HRTIM_TIM_SET1R_OFFSET+STM32_HRTIM1_TIMERA_BASE)
#define STM32_HRTIM1_TIMERA_RST1R (STM32_HRTIM_TIM_RST1R_OFFSET+STM32_HRTIM1_TIMERA_BASE)
#define STM32_HRTIM1_TIMERA_SET2R (STM32_HRTIM_TIM_SET2R_OFFSET+STM32_HRTIM1_TIMERA_BASE)
#define STM32_HRTIM1_TIMERA_RST2R (STM32_HRTIM_TIM_RST2R_OFFSET+STM32_HRTIM1_TIMERA_BASE)
#define STM32_HRTIM1_TIMERA_EEFR1 (STM32_HRTIM_TIM_EEFR1_OFFSET+STM32_HRTIM1_TIMERA_BASE)
#define STM32_HRTIM1_TIMERA_EEFR2 (STM32_HRTIM_TIM_EEFR2_OFFSET+STM32_HRTIM1_TIMERA_BASE)
#define STM32_HRTIM1_TIMERA_RSTR (STM32_HRTIM_TIM_RSTR_OFFSET+STM32_HRTIM1_TIMERA_BASE)
#define STM32_HRTIM1_TIMERA_CHPR (STM32_HRTIM_TIM_CHPR_OFFSET+STM32_HRTIM1_TIMERA_BASE)
#define STM32_HRTIM1_TIMERA_CPT1CR (STM32_HRTIM_TIM_CPT1CR_OFFSET+STM32_HRTIM1_TIMERA_BASE)
#define STM32_HRTIM1_TIMERA_CPT2CR (STM32_HRTIM_TIM_CPT2CR_OFFSET+STM32_HRTIM1_TIMERA_BASE)
#define STM32_HRTIM1_TIMERA_OUTR (STM32_HRTIM_TIM_OUTR_OFFSET+STM32_HRTIM1_TIMERA_BASE)
#define STM32_HRTIM1_TIMERA_FLTR (STM32_HRTIM_TIM_FLTR_OFFSET+STM32_HRTIM1_TIMERA_BASE)
/* HRTIM1 Timer B */
#define STM32_HRTIM1_TIMERB_CR (STM32_HRTIM_TIMERB_CR+STM32_HRTIM1_TIMERB_BASE)
#define STM32_HRTIM1_TIMERB_ISR (STM32_HRTIM_TIMERB_ISR+STM32_HRTIM1_TIMERB_BASE)
#define STM32_HRTIM1_TIMERB_ICR (STM32_HRTIM_TIMERB_ICR+STM32_HRTIM1_TIMERB_BASE)
#define STM32_HRTIM1_TIMERB_DIER (STM32_HRTIM_TIMERB_DIER+STM32_HRTIM1_TIMERB_BASE)
#define STM32_HRTIM1_TIMERB_CNTR (STM32_HRTIM_TIMERB_CNTR+STM32_HRTIM1_TIMERB_BASE)
#define STM32_HRTIM1_TIMERB_PER (STM32_HRTIM_TIMERB_PER+STM32_HRTIM1_TIMERB_BASE)
#define STM32_HRTIM1_TIMERB_REP (STM32_HRTIM_TIMERB_REP+STM32_HRTIM1_TIMERB_BASE)
#define STM32_HRTIM1_TIMERB_CMP1R (STM32_HRTIM_TIMERB_CMP1R+STM32_HRTIM1_TIMERB_BASE)
#define STM32_HRTIM1_TIMERB_CMP1CR (STM32_HRTIM_TIMERB_CMP1CR+STM32_HRTIM1_TIMERB_BASE)
#define STM32_HRTIM1_TIMERB_CMP2R (STM32_HRTIM_TIMERB_CMP2R+STM32_HRTIM1_TIMERB_BASE)
#define STM32_HRTIM1_TIMERB_CMP3R (STM32_HRTIM_TIMERB_CMP3R+STM32_HRTIM1_TIMERB_BASE)
#define STM32_HRTIM1_TIMERB_CMP4R (STM32_HRTIM_TIMERB_CMP4R+STM32_HRTIM1_TIMERB_BASE)
#define STM32_HRTIM1_TIMERB_CPT1R (STM32_HRTIM_TIMERB_CMPT1R+STM32_HRTIM1_TIMERB_BASE)
#define STM32_HRTIM1_TIMERB_CPT2R (STM32_HRTIM_TIMERB_CMPT2R+STM32_HRTIM1_TIMERB_BASE)
#define STM32_HRTIM1_TIMERB_DTR (STM32_HRTIM_TIMERB_DTR+STM32_HRTIM1_TIMERB_BASE)
#define STM32_HRTIM1_TIMERB_SET1R (STM32_HRTIM_TIMERB_SET1R+STM32_HRTIM1_TIMERB_BASE)
#define STM32_HRTIM1_TIMERB_RST1R (STM32_HRTIM_TIMERB_RST1R+STM32_HRTIM1_TIMERB_BASE)
#define STM32_HRTIM1_TIMERB_SET2R (STM32_HRTIM_TIMERB_SET2R+STM32_HRTIM1_TIMERB_BASE)
#define STM32_HRTIM1_TIMERB_RST2R (STM32_HRTIM_TIMERB_RST2R+STM32_HRTIM1_TIMERB_BASE)
#define STM32_HRTIM1_TIMERB_EEFR1 (STM32_HRTIM_TIMERB_EEFR1+STM32_HRTIM1_TIMERB_BASE)
#define STM32_HRTIM1_TIMERB_EEFR2 (STM32_HRTIM_TIMERB_EEFR2+STM32_HRTIM1_TIMERB_BASE)
#define STM32_HRTIM1_TIMERB_RSTR (STM32_HRTIM_TIMERB_RSTR+STM32_HRTIM1_TIMERB_BASE)
#define STM32_HRTIM1_TIMERB_CHPR (STM32_HRTIM_TIMERB_CHPR+STM32_HRTIM1_TIMERB_BASE)
#define STM32_HRTIM1_TIMERB_CPT1CR (STM32_HRTIM_TIMERB_CPT1CR+STM32_HRTIM1_TIMERB_BASE)
#define STM32_HRTIM1_TIMERB_CPT2CR (STM32_HRTIM_TIMERB_CPT2CR+STM32_HRTIM1_TIMERB_BASE)
#define STM32_HRTIM1_TIMERB_OUTR (STM32_HRTIM_TIMERB_OUTR+STM32_HRTIM1_TIMERB_BASE)
#define STM32_HRTIM1_TIMERB_FLTR (STM32_HRTIM_TIMERB_FLTR+STM32_HRTIM1_TIMERB_BASE)
/* HRTIM1 Timer C */
#define STM32_HRTIM1_TIMERC_CR (STM32_HRTIM_TIMERC_CR+STM32_HRTIM1_TIMERC_BASE)
#define STM32_HRTIM1_TIMERC_ISR (STM32_HRTIM_TIMERC_ISR+STM32_HRTIM1_TIMERC_BASE)
#define STM32_HRTIM1_TIMERC_ICR (STM32_HRTIM_TIMERC_ICR+STM32_HRTIM1_TIMERC_BASE)
#define STM32_HRTIM1_TIMERC_DIER (STM32_HRTIM_TIMERC_DIER+STM32_HRTIM1_TIMERC_BASE)
#define STM32_HRTIM1_TIMERC_CNTR (STM32_HRTIM_TIMERC_CNTR+STM32_HRTIM1_TIMERC_BASE)
#define STM32_HRTIM1_TIMERC_PER (STM32_HRTIM_TIMERC_PER+STM32_HRTIM1_TIMERC_BASE)
#define STM32_HRTIM1_TIMERC_REP (STM32_HRTIM_TIMERC_REP+STM32_HRTIM1_TIMERC_BASE)
#define STM32_HRTIM1_TIMERC_CMP1R (STM32_HRTIM_TIMERC_CMP1R+STM32_HRTIM1_TIMERC_BASE)
#define STM32_HRTIM1_TIMERC_CMP1CR (STM32_HRTIM_TIMERC_CMP1CR+STM32_HRTIM1_TIMERC_BASE)
#define STM32_HRTIM1_TIMERC_CMP2R (STM32_HRTIM_TIMERC_CMP2R+STM32_HRTIM1_TIMERC_BASE)
#define STM32_HRTIM1_TIMERC_CMP3R (STM32_HRTIM_TIMERC_CMP3R+STM32_HRTIM1_TIMERC_BASE)
#define STM32_HRTIM1_TIMERC_CMP4R (STM32_HRTIM_TIMERC_CMP4R+STM32_HRTIM1_TIMERC_BASE)
#define STM32_HRTIM1_TIMERC_CPT1R (STM32_HRTIM_TIMERC_CMPT1R+STM32_HRTIM1_TIMERC_BASE)
#define STM32_HRTIM1_TIMERC_CPT2R (STM32_HRTIM_TIMERC_CMPT2R+STM32_HRTIM1_TIMERC_BASE)
#define STM32_HRTIM1_TIMERC_DTR (STM32_HRTIM_TIMERC_DTR+STM32_HRTIM1_TIMERC_BASE)
#define STM32_HRTIM1_TIMERC_SET1R (STM32_HRTIM_TIMERC_SET1R+STM32_HRTIM1_TIMERC_BASE)
#define STM32_HRTIM1_TIMERC_RST1R (STM32_HRTIM_TIMERC_RST1R+STM32_HRTIM1_TIMERC_BASE)
#define STM32_HRTIM1_TIMERC_SET2R (STM32_HRTIM_TIMERC_SET2R+STM32_HRTIM1_TIMERC_BASE)
#define STM32_HRTIM1_TIMERC_RST2R (STM32_HRTIM_TIMERC_RST2R+STM32_HRTIM1_TIMERC_BASE)
#define STM32_HRTIM1_TIMERC_EEFR1 (STM32_HRTIM_TIMERC_EEFR1+STM32_HRTIM1_TIMERC_BASE)
#define STM32_HRTIM1_TIMERC_EEFR2 (STM32_HRTIM_TIMERC_EEFR2+STM32_HRTIM1_TIMERC_BASE)
#define STM32_HRTIM1_TIMERC_RSTR (STM32_HRTIM_TIMERC_RSTR+STM32_HRTIM1_TIMERC_BASE)
#define STM32_HRTIM1_TIMERC_CHPR (STM32_HRTIM_TIMERC_CHPR+STM32_HRTIM1_TIMERC_BASE)
#define STM32_HRTIM1_TIMERC_CPT1CR (STM32_HRTIM_TIMERC_CPT1CR+STM32_HRTIM1_TIMERC_BASE)
#define STM32_HRTIM1_TIMERC_CPT2CR (STM32_HRTIM_TIMERC_CPT2CR+STM32_HRTIM1_TIMERC_BASE)
#define STM32_HRTIM1_TIMERC_OUTR (STM32_HRTIM_TIMERC_OUTR+STM32_HRTIM1_TIMERC_BASE)
#define STM32_HRTIM1_TIMERC_FLTR (STM32_HRTIM_TIMERC_FLTR+STM32_HRTIM1_TIMERC_BASE)
/* HRTIM1 Timer D */
#define STM32_HRTIM1_TIMERD_CR (STM32_HRTIM_TIMERD_CR+STM32_HRTIM1_TIMERD_BASE)
#define STM32_HRTIM1_TIMERD_ISR (STM32_HRTIM_TIMERD_ISR+STM32_HRTIM1_TIMERD_BASE)
#define STM32_HRTIM1_TIMERD_ICR (STM32_HRTIM_TIMERD_ICR+STM32_HRTIM1_TIMERD_BASE)
#define STM32_HRTIM1_TIMERD_DIER (STM32_HRTIM_TIMERD_DIER+STM32_HRTIM1_TIMERD_BASE)
#define STM32_HRTIM1_TIMERD_CNTR (STM32_HRTIM_TIMERD_CNTR+STM32_HRTIM1_TIMERD_BASE)
#define STM32_HRTIM1_TIMERD_PER (STM32_HRTIM_TIMERD_PER+STM32_HRTIM1_TIMERD_BASE)
#define STM32_HRTIM1_TIMERD_REP (STM32_HRTIM_TIMERD_REP+STM32_HRTIM1_TIMERD_BASE)
#define STM32_HRTIM1_TIMERD_CMP1R (STM32_HRTIM_TIMERD_CMP1R+STM32_HRTIM1_TIMERD_BASE)
#define STM32_HRTIM1_TIMERD_CMP1CR (STM32_HRTIM_TIMERD_CMP1CR+STM32_HRTIM1_TIMERD_BASE)
#define STM32_HRTIM1_TIMERD_CMP2R (STM32_HRTIM_TIMERD_CMP2R+STM32_HRTIM1_TIMERD_BASE)
#define STM32_HRTIM1_TIMERD_CMP3R (STM32_HRTIM_TIMERD_CMP3R+STM32_HRTIM1_TIMERD_BASE)
#define STM32_HRTIM1_TIMERD_CMP4R (STM32_HRTIM_TIMERD_CMP4R+STM32_HRTIM1_TIMERD_BASE)
#define STM32_HRTIM1_TIMERD_CPT1R (STM32_HRTIM_TIMERD_CMPT1R+STM32_HRTIM1_TIMERD_BASE)
#define STM32_HRTIM1_TIMERD_CPT2R (STM32_HRTIM_TIMERD_CMPT2R+STM32_HRTIM1_TIMERD_BASE)
#define STM32_HRTIM1_TIMERD_DTR (STM32_HRTIM_TIMERD_DTR+STM32_HRTIM1_TIMERD_BASE)
#define STM32_HRTIM1_TIMERD_SET1R (STM32_HRTIM_TIMERD_SET1R+STM32_HRTIM1_TIMERD_BASE)
#define STM32_HRTIM1_TIMERD_RST1R (STM32_HRTIM_TIMERD_RST1R+STM32_HRTIM1_TIMERD_BASE)
#define STM32_HRTIM1_TIMERD_SET2R (STM32_HRTIM_TIMERD_SET2R+STM32_HRTIM1_TIMERD_BASE)
#define STM32_HRTIM1_TIMERD_RST2R (STM32_HRTIM_TIMERD_RST2R+STM32_HRTIM1_TIMERD_BASE)
#define STM32_HRTIM1_TIMERD_EEFR1 (STM32_HRTIM_TIMERD_EEFR1+STM32_HRTIM1_TIMERD_BASE)
#define STM32_HRTIM1_TIMERD_EEFR2 (STM32_HRTIM_TIMERD_EEFR2+STM32_HRTIM1_TIMERD_BASE)
#define STM32_HRTIM1_TIMERD_RSTR (STM32_HRTIM_TIMERD_RSTR+STM32_HRTIM1_TIMERD_BASE)
#define STM32_HRTIM1_TIMERD_CHPR (STM32_HRTIM_TIMERD_CHPR+STM32_HRTIM1_TIMERD_BASE)
#define STM32_HRTIM1_TIMERD_CPT1CR (STM32_HRTIM_TIMERD_CPT1CR+STM32_HRTIM1_TIMERD_BASE)
#define STM32_HRTIM1_TIMERD_CPT2CR (STM32_HRTIM_TIMERD_CPT2CR+STM32_HRTIM1_TIMERD_BASE)
#define STM32_HRTIM1_TIMERD_OUTR (STM32_HRTIM_TIMERD_OUTR+STM32_HRTIM1_TIMERD_BASE)
#define STM32_HRTIM1_TIMERD_FLTR (STM32_HRTIM_TIMERD_FLTR+STM32_HRTIM1_TIMERD_BASE)
/* HRTIM1 Timer E */
#define STM32_HRTIM1_TIMERE_CR (STM32_HRTIM_TIMERE_CR+STM32_HRTIM1_TIMERE_BASE)
#define STM32_HRTIM1_TIMERE_ISR (STM32_HRTIM_TIMERE_ISR+STM32_HRTIM1_TIMERE_BASE)
#define STM32_HRTIM1_TIMERE_ICR (STM32_HRTIM_TIMERE_ICR+STM32_HRTIM1_TIMERE_BASE)
#define STM32_HRTIM1_TIMERE_DIER (STM32_HRTIM_TIMERE_DIER+STM32_HRTIM1_TIMERE_BASE)
#define STM32_HRTIM1_TIMERE_CNTR (STM32_HRTIM_TIMERE_CNTR+STM32_HRTIM1_TIMERE_BASE)
#define STM32_HRTIM1_TIMERE_PER (STM32_HRTIM_TIMERE_PER+STM32_HRTIM1_TIMERE_BASE)
#define STM32_HRTIM1_TIMERE_REP (STM32_HRTIM_TIMERE_REP+STM32_HRTIM1_TIMERE_BASE)
#define STM32_HRTIM1_TIMERE_CMP1R (STM32_HRTIM_TIMERE_CMP1R+STM32_HRTIM1_TIMERE_BASE)
#define STM32_HRTIM1_TIMERE_CMP1CR (STM32_HRTIM_TIMERE_CMP1CR+STM32_HRTIM1_TIMERE_BASE)
#define STM32_HRTIM1_TIMERE_CMP2R (STM32_HRTIM_TIMERE_CMP2R+STM32_HRTIM1_TIMERE_BASE)
#define STM32_HRTIM1_TIMERE_CMP3R (STM32_HRTIM_TIMERE_CMP3R+STM32_HRTIM1_TIMERE_BASE)
#define STM32_HRTIM1_TIMERE_CMP4R (STM32_HRTIM_TIMERE_CMP4R+STM32_HRTIM1_TIMERE_BASE)
#define STM32_HRTIM1_TIMERE_CPT1R (STM32_HRTIM_TIMERE_CMPT1R+STM32_HRTIM1_TIMERE_BASE)
#define STM32_HRTIM1_TIMERE_CPT2R (STM32_HRTIM_TIMERE_CMPT2R+STM32_HRTIM1_TIMERE_BASE)
#define STM32_HRTIM1_TIMERE_DTR (STM32_HRTIM_TIMERE_DTR+STM32_HRTIM1_TIMERE_BASE)
#define STM32_HRTIM1_TIMERE_SET1R (STM32_HRTIM_TIMERE_SET1R+STM32_HRTIM1_TIMERE_BASE)
#define STM32_HRTIM1_TIMERE_RST1R (STM32_HRTIM_TIMERE_RST1R+STM32_HRTIM1_TIMERE_BASE)
#define STM32_HRTIM1_TIMERE_SET2R (STM32_HRTIM_TIMERE_SET2R+STM32_HRTIM1_TIMERE_BASE)
#define STM32_HRTIM1_TIMERE_RST2R (STM32_HRTIM_TIMERE_RST2R+STM32_HRTIM1_TIMERE_BASE)
#define STM32_HRTIM1_TIMERE_EEFR1 (STM32_HRTIM_TIMERE_EEFR1+STM32_HRTIM1_TIMERE_BASE)
#define STM32_HRTIM1_TIMERE_EEFR2 (STM32_HRTIM_TIMERE_EEFR2+STM32_HRTIM1_TIMERE_BASE)
#define STM32_HRTIM1_TIMERE_RSTR (STM32_HRTIM_TIMERE_RSTR+STM32_HRTIM1_TIMERE_BASE)
#define STM32_HRTIM1_TIMERE_CHPR (STM32_HRTIM_TIMERE_CHPR+STM32_HRTIM1_TIMERE_BASE)
#define STM32_HRTIM1_TIMERE_CPT1CR (STM32_HRTIM_TIMERE_CPT1CR+STM32_HRTIM1_TIMERE_BASE)
#define STM32_HRTIM1_TIMERE_CPT2CR (STM32_HRTIM_TIMERE_CPT2CR+STM32_HRTIM1_TIMERE_BASE)
#define STM32_HRTIM1_TIMERE_OUTR (STM32_HRTIM_TIMERE_OUTR+STM32_HRTIM1_TIMERE_BASE)
#define STM32_HRTIM1_TIMERE_FLTR (STM32_HRTIM_TIMERE_FLTR+STM32_HRTIM1_TIMERE_BASE)
/* HRTIM1 Common Registers */
#define STM32_HRTIM_CMN_CR1 (STM32_HRTIM_CMN_CR1+STM32_HRTIM1_CMN_BASE)
#define STM32_HRTIM_CMN_CR2 (STM32_HRTIM_CMN_CR2+STM32_HRTIM1_CMN_BASE)
#define STM32_HRTIM_CMN_ISR (STM32_HRTIM_CMN_ISR+STM32_HRTIM1_CMN_BASE)
#define STM32_HRTIM_CMN_ICR (STM32_HRTIM_CMN_ICR+STM32_HRTIM1_CMN_BASE)
#define STM32_HRTIM_CMN_IER (STM32_HRTIM_CMN_IER+STM32_HRTIM1_CMN_BASE)
#define STM32_HRTIM_CMN_OENR (STM32_HRTIM_CMN_OENR+STM32_HRTIM1_CMN_BASE)
#define STM32_HRTIM_CMN_DISR (STM32_HRTIM_CMN_DISR+STM32_HRTIM1_CMN_BASE)
#define STM32_HRTIM_CMN_ODSR (STM32_HRTIM_CMN_ODSR+STM32_HRTIM1_CMN_BASE)
#define STM32_HRTIM_CMN_BMCR (STM32_HRTIM_CMN_BMCR+STM32_HRTIM1_CMN_BASE)
#define STM32_HRTIM_CMN_BMTGR (STM32_HRTIM_CMN_BMTGR+STM32_HRTIM1_CMN_BASE)
#define STM32_HRTIM_CMN_BMCMPR (STM32_HRTIM_CMN_MBCMPR+STM32_HRTIM1_CMN_BASE)
#define STM32_HRTIM_CMN_BMPER (STM32_HRTIM_CMN_BMPER+STM32_HRTIM1_CMN_BASE)
#define STM32_HRTIM_CMN_EECR1 (STM32_HRTIM_CMN_EECR1+STM32_HRTIM1_CMN_BASE)
#define STM32_HRTIM_CMN_EECR2 (STM32_HRTIM_CMN_EECR2+STM32_HRTIM1_CMN_BASE)
#define STM32_HRTIM_CMN_EECR3 (STM32_HRTIM_CMN_EECR3+STM32_HRTIM1_CMN_BASE)
#define STM32_HRTIM_CMN_ADC1R (STM32_HRTIM_CMN_ADC1R+STM32_HRTIM1_CMN_BASE)
#define STM32_HRTIM_CMN_ADC2R (STM32_HRTIM_CMN_ADC2R+STM32_HRTIM1_CMN_BASE)
#define STM32_HRTIM_CMN_ADC3R (STM32_HRTIM_CMN_ADC3R+STM32_HRTIM1_CMN_BASE)
#define STM32_HRTIM_CMN_ADC4R (STM32_HRTIM_CMN_ADC4R+STM32_HRTIM1_CMN_BASE)
#define STM32_HRTIM_CMN_DLLCR (STM32_HRTIM_CMN_DLLCR+STM32_HRTIM1_CMN_BASE)
#define STM32_HRTIM_CMN_FLTINR1 (STM32_HRTIM_CMN_FTLINR1+STM32_HRTIM1_CMN_BASE)
#define STM32_HRTIM_CMN_FLTINR2 (STM32_HRTIM_CMN_FLTINR2+STM32_HRTIM1_CMN_BASE)
#define STM32_HRTIM_CMN_BDMUPDR (STM32_HRTIM_CMN_BDMUPDR+STM32_HRTIM1_CMN_BASE)
#define STM32_HRTIM_CMN_BDTAUPR (STM32_HRTIM_CMN_BDTAUPR+STM32_HRTIM1_CMN_BASE)
#define STM32_HRTIM_CMN_BDTBUPR (STM32_HRTIM_CMN_BDTBUR+STM32_HRTIM1_CMN_BASE)
#define STM32_HRTIM_CMN_BDTCUPR (STM32_HRTIM_CMN_BDTCUPR+STM32_HRTIM1_CMN_BASE)
#define STM32_HRTIM_CMN_BDTDUPR (STM32_HRTIM_CMN_BDTDUPR+STM32_HRTIM1_CMN_BASE)
#define STM32_HRTIM_CMN_BDTEUPR (STM32_HRTIM_CMN_BDTEUPR+STM32_HRTIM1_CMN_BASE)
#define STM32_HRTIM_CMN_BDMADR (STM32_HRTIM_CMN_BDMADR+STM32_HRTIM1_CMN_BASE)
#define STM32_HRTIM_CMN_CR1 (STM32_HRTIM_CMN_CR1_OFFSET+STM32_HRTIM1_CMN_BASE)
#define STM32_HRTIM_CMN_CR2 (STM32_HRTIM_CMN_CR2_OFFSET+STM32_HRTIM1_CMN_BASE)
#define STM32_HRTIM_CMN_ISR (STM32_HRTIM_CMN_ISR_OFFSET+STM32_HRTIM1_CMN_BASE)
#define STM32_HRTIM_CMN_ICR (STM32_HRTIM_CMN_ICR_OFFSET+STM32_HRTIM1_CMN_BASE)
#define STM32_HRTIM_CMN_IER (STM32_HRTIM_CMN_IER_OFFSET+STM32_HRTIM1_CMN_BASE)
#define STM32_HRTIM_CMN_OENR (STM32_HRTIM_CMN_OENR_OFFSET+STM32_HRTIM1_CMN_BASE)
#define STM32_HRTIM_CMN_DISR (STM32_HRTIM_CMN_DISR_OFFSET+STM32_HRTIM1_CMN_BASE)
#define STM32_HRTIM_CMN_ODSR (STM32_HRTIM_CMN_ODSR_OFFSET+STM32_HRTIM1_CMN_BASE)
#define STM32_HRTIM_CMN_BMCR (STM32_HRTIM_CMN_BMCR_OFFSET+STM32_HRTIM1_CMN_BASE)
#define STM32_HRTIM_CMN_BMTGR (STM32_HRTIM_CMN_BMTGR_OFFSET+STM32_HRTIM1_CMN_BASE)
#define STM32_HRTIM_CMN_BMCMPR (STM32_HRTIM_CMN_MBCMPR_OFFSET+STM32_HRTIM1_CMN_BASE)
#define STM32_HRTIM_CMN_BMPER (STM32_HRTIM_CMN_BMPER_OFFSET+STM32_HRTIM1_CMN_BASE)
#define STM32_HRTIM_CMN_EECR1 (STM32_HRTIM_CMN_EECR1_OFFSET+STM32_HRTIM1_CMN_BASE)
#define STM32_HRTIM_CMN_EECR2 (STM32_HRTIM_CMN_EECR2_OFFSET+STM32_HRTIM1_CMN_BASE)
#define STM32_HRTIM_CMN_EECR3 (STM32_HRTIM_CMN_EECR3_OFFSET+STM32_HRTIM1_CMN_BASE)
#define STM32_HRTIM_CMN_ADC1R (STM32_HRTIM_CMN_ADC1R_OFFSET+STM32_HRTIM1_CMN_BASE)
#define STM32_HRTIM_CMN_ADC2R (STM32_HRTIM_CMN_ADC2R_OFFSET+STM32_HRTIM1_CMN_BASE)
#define STM32_HRTIM_CMN_ADC3R (STM32_HRTIM_CMN_ADC3R_OFFSET+STM32_HRTIM1_CMN_BASE)
#define STM32_HRTIM_CMN_ADC4R (STM32_HRTIM_CMN_ADC4R_OFFSET+STM32_HRTIM1_CMN_BASE)
#define STM32_HRTIM_CMN_DLLCR (STM32_HRTIM_CMN_DLLCR_OFFSET+STM32_HRTIM1_CMN_BASE)
#define STM32_HRTIM_CMN_FLTINR1 (STM32_HRTIM_CMN_FTLINR1_OFFSET+STM32_HRTIM1_CMN_BASE)
#define STM32_HRTIM_CMN_FLTINR2 (STM32_HRTIM_CMN_FLTINR2_OFFSET+STM32_HRTIM1_CMN_BASE)
#define STM32_HRTIM_CMN_BDMUPDR (STM32_HRTIM_CMN_BDMUPDR_OFFSET+STM32_HRTIM1_CMN_BASE)
#define STM32_HRTIM_CMN_BDTAUPR (STM32_HRTIM_CMN_BDTAUPR_OFFSET+STM32_HRTIM1_CMN_BASE)
#define STM32_HRTIM_CMN_BDTBUPR (STM32_HRTIM_CMN_BDTBUR_OFFSET+STM32_HRTIM1_CMN_BASE)
#define STM32_HRTIM_CMN_BDTCUPR (STM32_HRTIM_CMN_BDTCUPR_OFFSET+STM32_HRTIM1_CMN_BASE)
#define STM32_HRTIM_CMN_BDTDUPR (STM32_HRTIM_CMN_BDTDUPR_OFFSET+STM32_HRTIM1_CMN_BASE)
#define STM32_HRTIM_CMN_BDTEUPR (STM32_HRTIM_CMN_BDTEUPR_OFFSET+STM32_HRTIM1_CMN_BASE)
#define STM32_HRTIM_CMN_BDMADR (STM32_HRTIM_CMN_BDMADR_OFFSET+STM32_HRTIM1_CMN_BASE)
/* Register Bitfield Definitions ****************************************************/
/* Master Timer Control Register */
/* Control Register Bits Common to Master Timer and Timer A-E */
#define HRTIM_MCR_CKPSC_SHIFT 0 /* Bits 0-2: Clock prescaler */
#define HRTIM_MCR_CKPSC_MASK (7 << HRTIM_MCR_CKPSC_SHIFT)
# define HRTIM_MCR_CKPSC_NODIV (0 << HRTIM_MCR_CKPSC_SHIFT)
# define HRTIM_MCR_CKPSC_d2 (1 << HRTIM_MCR_CKPSC_SHIFT)
# define HRTIM_MCR_CKPSC_d4 (2 << HRTIM_MCR_CKPSC_SHIFT)
# define HRTIM_MCR_CKPSC_d8 (3 << HRTIM_MCR_CKPSC_SHIFT)
# define HRTIM_MCR_CKPSC_d16 (4 << HRTIM_MCR_CKPSC_SHIFT)
# define HRTIM_MCR_CKPSC_d32 (5 << HRTIM_MCR_CKPSC_SHIFT)
# define HRTIM_MCR_CKPSC_d64 (6 << HRTIM_MCR_CKPSC_SHIFT)
# define HRTIM_MCR_CKPSC_d128 (7 << HRTIM_MCR_CKPSC_SHIFT)
#define HRTIM_MCR_CONT (1 << 3) /* Bit 3: Continuous mode */
#define HRTIM_MCR_RETRIG (1 << 4) /* Bit 4: Re-triggerable mode */
#define HRTIM_MCR_HALF (1 << 5) /* Bit 5: Half mode */
#define HRTIM_MCR_SYNCIN_SHIFT 8 /* Bits 8-9: Synchronization input */
#define HRTIM_CMNCR_CKPSC_SHIFT 0 /* Bits 0-2: Clock prescaler */
#define HRTIM_CMNCR_CKPSC_MASK (7 << HRTIM_CMNCR_CKPSC_SHIFT)
# define HRTIM_CMNCR_CKPSC_NODIV (0 << HRTIM_CMNCR_CKPSC_SHIFT)
# define HRTIM_CMNCR_CKPSC_d2 (1 << HRTIM_CMNCR_CKPSC_SHIFT)
# define HRTIM_CMNCR_CKPSC_d4 (2 << HRTIM_CMNCR_CKPSC_SHIFT)
# define HRTIM_CMNCR_CKPSC_d8 (3 << HRTIM_CMNCR_CKPSC_SHIFT)
# define HRTIM_CMNCR_CKPSC_d16 (4 << HRTIM_CMNCR_CKPSC_SHIFT)
# define HRTIM_CMNCR_CKPSC_d32 (5 << HRTIM_CMNCR_CKPSC_SHIFT)
# define HRTIM_CMNCR_CKPSC_d64 (6 << HRTIM_CMNCR_CKPSC_SHIFT)
# define HRTIM_CMNCR_CKPSC_d128 (7 << HRTIM_CMNCR_CKPSC_SHIFT)
#define HRTIM_CMNCR_CONT (1 << 3) /* Bit 3: Continuous mode */
#define HRTIM_CMNCR_RETRIG (1 << 4) /* Bit 4: Re-triggerable mode */
#define HRTIM_CMNCR_HALF (1 << 5) /* Bit 5: Half mode */
/* Bits 6-9 differs */
#define HRTIM_CMNCR_SYNCRST (1 << 10) /* Bit 10: Synchronization Resets Master */
#define HRTIM_CMNCR_SYNCSTRTM (1 << 11) /* Bit 11: Synchronization Starts Master */
/* Bits 12-24 differs */
#define HRTIM_CMNCR_DACSYNC_SHIFT 25 /* Bits 25-26: DAC Synchronization*/
#define HRTIM_CMNCR_DACSYNC_MASK (3 << HRTIM_CMNCR_DACSYNC_SHIFT)
# define HRTIM_CMNCR_DACSYNC_00 (0 << HRTIM_CMNCR_DACSYNC_SHIFT) /* 00: */
# define HRTIM_CMNCR_DACSYNC_01 (1 << HRTIM_CMNCR_DACSYNC_SHIFT) /* 01: */
# define HRTIM_CMNCR_DACSYNC_10 (2 << HRTIM_CMNCR_DACSYNC_SHIFT) /* 10: */
# define HRTIM_CMNCR_DACSYNC_11 (3 << HRTIM_CMNCR_DACSYNC_SHIFT) /* 11: */
#define HRTIM_CMNCR_PREEN (1 << 27) /* Bit 27: Preload enable */
/* Bits 29-31 differs */
/* Control Register Bits specific to Master Timer */
/* Bits 0-5 common */
/* Bits 6-7 reserved */
/* Bits 10-11 common */
#define HRTIM_MCR_SYNCIN_SHIFT 8 /* Bits 8-9: Synchronization input */
#define HRTIM_MCR_SYNCIN_MASK (3 << HRTIM_MCR_SYNCIN_SHIFT)
# define HRTIM_MCR_SYNCIN_DIS (0 << HRTIM_MCR_SYNCIN_SHIFT) /* 00 disabled */
# define HRTIM_MCR_SYNCIN_INTE (2 << HRTIM_MCR_SYNCIN_SHIFT) /* 10: Internal Event */
# define HRTIM_MCR_SYNCIN_EXTE (3 << HRTIM_MCR_SYNCIN_SHIFT) /* 11: External Event */
#define HRTIM_MCR_SYNCRST (1 << 10) /* Bit 10: Synchronization Resets Master */
#define HRTIM_MCR_SYNCSTRTM (1 << 11) /* Bit 11: Synchronization Starts Master */
#define HRTIM_MCR_SYNCOUT_SHIFT 12 /* Bits 12-13: Synchronization output */
#define HRTIM_MCR_SYNCOUT_SHIFT 12 /* Bits 12-13: Synchronization output */
#define HRTIM_MCR_SYNCOUT_MASK (3 << HRTIM_MCR_SYNCOUT_SHIFT)
# define HRTIM_MCR_SYNCOUT_DIS (0 << HRTIM_MCR_SYNCOUT_SHIFT) /* 00: Disabled */
# define HRTIM_MCR_SYNCOUT_POS (2 << HRTIM_MCR_SYNCOUT_SHIFT) /* 10: Positive pulse on SCOUT */
# define HRTIM_MCR_SYNCOUT_NEG (3 << HRTIM_MCR_SYNCOUT_SHIFT) /* 11: Negative pulse on SCOUT */
#define HRTIM_MCR_SYNCSRC_SHIFT 14 /* Bits 14-15: Synchronization source*/
#define HRTIM_MCR_SYNCSRC_SHIFT 14 /* Bits 14-15: Synchronization source*/
#define HRTIM_MCR_SYNCSRC_MASK (3 << HRTIM_MCR_SYNCSRC_SHIFT)
# define HRTIM_MCR_SYNCSRC_MSTRT (0 << HRTIM_MCR_SYNCSRC_SHIFT) /* 00: Master timer Start */
# define HRTIM_MCR_SYNCSRC_MCMP1 (1 << HRTIM_MCR_SYNCSRC_SHIFT) /* 01: Master timer Compare 1 Event */
@ -382,15 +262,10 @@
#define HRTIM_MCR_TCCEN (1 << 19) /* Bit 19: Timer C counter enable */
#define HRTIM_MCR_TDCEN (1 << 20) /* Bit 20: Timer D counter enable */
#define HRTIM_MCR_TECEN (1 << 21) /* Bit 21: Timer E counter enable */
#define HRTIM_MCR_DACSYNC_SHIFT 25 /* Bits 25-26: DAC Synchronization*/
#define HRTIM_MCR_DACSYNC_MASK (3 << HRTIM_MCR_DACSYNC_SHIFT)
# define HRTIM_MCR_DACSYNC_00 (0 << HRTIM_MCR_DACSYNC_SHIFT) /* 00: */
# define HRTIM_MCR_DACSYNC_01 (1 << HRTIM_MCR_DACSYNC_SHIFT) /* 01: */
# define HRTIM_MCR_DACSYNC_10 (2 << HRTIM_MCR_DACSYNC_SHIFT) /* 10: */
# define HRTIM_MCR_DACSYNC_11 (3 << HRTIM_MCR_DACSYNC_SHIFT) /* 11: */
#define HRTIM_MCR_PREEN (1 << 27) /* Bit 27: Preload enable */
/* Bits 22-24 reserved */
/* Bits 25-27 common */
#define HRTIM_MCR_MREPU (1 << 29) /* Bit 29: Master Timer Repetition Update */
#define HRTIM_MCR_BRSTDMA_SHIFT 30 /* Bits 30-31: Burs DMA Update*/
#define HRTIM_MCR_BRSTDMA_SHIFT 30 /* Bits 30-31: Burs DMA Update*/
#define HRTIM_MCR_BRSTDMA_MASK (3 << HRTIM_MCR_BRSTDMA_SHIFT)
# define HRTIM_MCR_BRSTDMA_00 (0 << HRTIM_MCR_BRSTDMA_SHIFT) /* 00 */
# define HRTIM_MCR_BRSTDMA_01 (1 << HRTIM_MCR_BRSTDMA_SHIFT) /* 01 */
@ -468,24 +343,11 @@
#define HRTIM_MCMP4_SHIFT 0 /* Bits 0-15: Master Timer Compare 4 value */
#define HRTIM_MCMP4_MASK (0xffff << HRTIM_MCMP4_SHIFT)
/* Timer X Control Register */
/* Timer A-E Control Register */
#define HRTIM_TIMCR_CKPSC_SHIFT 0 /* Bits 0-2: HRTIM Timer X Clock Prescaler */
#define HRTIM_TIMCR_CKPSC_MASK (7 << HRTIM_TIMCR_CKPSC_SHIFT)
# define HRTIM_TIMCR_CKPSC_000 (0 << HRTIM_TIMCR_CKPSC_SHIFT) /* 000: */
# define HRTIM_TIMCR_CKPSC_001 (1 << HRTIM_TIMCR_CKPSC_SHIFT) /* 001: */
# define HRTIM_TIMCR_CKPSC_010 (2 << HRTIM_TIMCR_CKPSC_SHIFT) /* 010: */
# define HRTIM_TIMCR_CKPSC_011 (3 << HRTIM_TIMCR_CKPSC_SHIFT) /* 011: */
# define HRTIM_TIMCR_CKPSC_100 (4 << HRTIM_TIMCR_CKPSC_SHIFT) /* 100: */
# define HRTIM_TIMCR_CKPSC_101 (5 << HRTIM_TIMCR_CKPSC_SHIFT) /* 101: */
# define HRTIM_TIMCR_CKPSC_110 (6 << HRTIM_TIMCR_CKPSC_SHIFT) /* 110: */
# define HRTIM_TIMCR_CKPSC_111 (7 << HRTIM_TIMCR_CKPSC_SHIFT) /* 111: */
#define HRTIM_TIMCR_CONT (1 << 3) /* Bit 3: Continuous mode */
#define HRTIM_TIMCR_RETRIG (1 << 4) /* Bit 4: Re-triggerable mode */
#define HRTIM_TIMCR_HALF (1 << 5) /* Bit 5: Half mode enable */
#define HRTIM_TIMCR_PSHPLL (1 << 6) /* Bit 6:Push-Pull mode enable */
#define HRTIM_TIMCR_SYNCRS (1 << 10) /* Bit 10: Synchronization Resets Timer X */
#define HRTIM_TIMCR_SYNCSTR (1 << 11) /* Bit 11: Synchronization Starts Timer X */
/* Bits 0-5 common */
#define HRTIM_TIMCR_PSHPLL (1 << 6) /* Bit 6:Push-Pull mode enable */
/* Bits 10-11 common */
#define HRTIM_TIMCR_DELCMP2_SHIFT 12 /* Bits 12-13: CMP2 auto-delayed mode */
#define HRTIM_TIMCR_DELCMP2_MASK (3 << HRTIM_TIMCR_DELCMP2_SHIFT)
# define HRTIM_TIMCR_DELCMP2_00 (0 << HRTIM_TIMCR_DELCMP2_SHIFT) /* 00: */
@ -506,13 +368,7 @@
#define HRTIM_TIMCR_TDU (1 << 22) /* Bit 22: Timer D Update */
#define HRTIM_TIMCR_TEU (1 << 23) /* Bit 23: Timer E Update */
#define HRTIM_TIMCR_MSTU (1 << 24) /* Bit 24: Master Timer Update */
#define HRTIM_TIMCR_DACSYNC_SHIFT 25 /* Bits 25-26: DAC Synchronization */
#define HRTIM_TIMCR_DACSYNC_MASK (3 << HRTIM_TIMCR_DACSYNC_SHIFT)
# define HRTIM_TIMCR_DACSYNC_00 (0 << HRTIM_TIMCR_DACSYNC_SHIFT)
# define HRTIM_TIMCR_DACSYNC_01 (1 << HRTIM_TIMCR_DACSYNC_SHIFT)
# define HRTIM_TIMCR_DACSYNC_10 (2 << HRTIM_TIMCR_DACSYNC_SHIFT)
# define HRTIM_TIMCR_DACSYNC_11 (3 << HRTIM_TIMCR_DACSYNC_SHIFT)
#define HRTIM_TIMCR_PREEN (1 << 27) /* Bit 27: Preload Enable */
/* Bits 25-27 common */
#define HRTIM_TIMCR_UPDGAT_SHIFT 28 /* Bits 28-31: Update Gating */
#define HRTIM_TIMCR_UPDGAT_MASK (15 << HRTIM_TIMCR_UPDGAT_SHIFT)
# define HRTIM_TIMCR_UPDGAT_0000 (0 << HRTIM_TIMCR_UPDGAT_SHIFT) /* 0000: */
@ -838,7 +694,7 @@
# define HRTIM_TIMEEF1_EE2FLT_0 (0 << HRTIM_TIMEEF1_EE2FLT_SHIFT) /* 0000: No filtering */
# define HRTIM_TIMEEF1_EE2FLT_1 (1 << HRTIM_TIMEEF1_EE2FLT_SHIFT) /* 0001: Blanking from counter reset/roll-over to Compare 1 */
# define HRTIM_TIMEEF1_EE2FLT_2 (2 << HRTIM_TIMEEF1_EE2FLT_SHIFT) /* 0010: Blanking from counter reset/roll-over to Compare 2 */
# define HRTIM_TIMEEF1_EE2FLT_2 (3 << HRTIM_TIMEEF1_EE2FLT_SHIFT) /* 0011: Blanking from counter reset/roll-over to Compare 3 */
# define HRTIM_TIMEEF1_EE2FLT_3 (3 << HRTIM_TIMEEF1_EE2FLT_SHIFT) /* 0011: Blanking from counter reset/roll-over to Compare 3 */
# define HRTIM_TIMEEF1_EE2FLT_4 (4 << HRTIM_TIMEEF1_EE2FLT_SHIFT) /* 0100: Blanking from counter reset/roll-over to Compare 4 */
# define HRTIM_TIMEEF1_EE2FLT_5 (5 << HRTIM_TIMEEF1_EE2FLT_SHIFT) /* 0101: Blanking from TIMFLTR1 source */
# define HRTIM_TIMEEF1_EE2FLT_6 (6 << HRTIM_TIMEEF1_EE2FLT_SHIFT) /* 0110: Blanking from TIMFLTR2 source */

1
arch/arm/src/stm32/stm32.h
View file

@ -67,6 +67,7 @@
#include "stm32_flash.h"
#include "stm32_fsmc.h"
#include "stm32_gpio.h"
#include "stm32_hrtim.h"
#include "stm32_i2c.h"
#include "stm32_ltdc.h"
#include "stm32_opamp.h"

1908
arch/arm/src/stm32/stm32_hrtim.c Normal file
View file

File diff suppressed because it is too large Load diff

305
arch/arm/src/stm32/stm32_hrtim.h Normal file
View file

@ -0,0 +1,305 @@
/************************************************************************************
* arch/arm/src/stm32/stm32_hrtim.h
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
* Author: Mateusz Szafoni <raiden00@railab.me>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32_STM32_HRTIM_H
#define __ARCH_ARM_SRC_STM32_STM32_HRTIM_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#ifdef CONFIG_STM32_HRTIM1
#if defined(CONFIG_STM32_STM32F33XX)
# include "chip/stm32f33xxx_hrtim.h"
#else
# error
#endif
/************************************************************************************
* Pre-processor definitions
************************************************************************************/
/************************************************************************************
* Public Types
************************************************************************************/
/* HRTIM Timer X index */
enum stm32_hrtim_tim_e
{
HRTIM_TIMER_MASTER,
#ifdef CONFIG_STM32_HRTIM_TIMA
HRTIM_TIMER_TIMA,
#endif
#ifdef CONFIG_STM32_HRTIM_TIMB
HRTIM_TIMER_TIMB,
#endif
#ifdef CONFIG_STM32_HRTIM_TIMC
HRTIM_TIMER_TIMC,
#endif
#ifdef CONFIG_STM32_HRTIM_TIMD
HRTIM_TIMER_TIMD,
#endif
#ifdef CONFIG_STM32_HRTIM_TIME
HRTIM_TIMER_TIME,
#endif
};
/* Source which can force the Tx1/Tx2 output to its inactive state */
enum stm32_hrtim_out_rst_e
{
HRTIM_OUT_RST_UPDATE = (1 << 0),
HRTIM_OUT_RST_EXTEVNT10 = (1 << 1),
HRTIM_OUT_RST_EXTEVNT9 = (1 << 2),
HRTIM_OUT_RST_EXTEVNT8 = (1 << 3),
HRTIM_OUT_RST_EXTEVNT7 = (1 << 4),
HRTIM_OUT_RST_EXTEVNT6 = (1 << 5),
HRTIM_OUT_RST_EXTEVNT5 = (1 << 6),
HRTIM_OUT_RST_EXTEVNT4 = (1 << 7),
HRTIM_OUT_RST_EXTEVNT3 = (1 << 8),
HRTIM_OUT_RST_EXTEVNT2 = (1 << 9),
HRTIM_OUT_RST_EXTEVNT1 = (1 << 10),
HRTIM_OUT_RST_TIMEVNT9 = (1 << 11),
HRTIM_OUT_RST_TIMEVNT8 = (1 << 12),
HRTIM_OUT_RST_TIMEVNT7 = (1 << 13),
HRTIM_OUT_RST_TIMEVNT6 = (1 << 14),
HRTIM_OUT_RST_TIMEVNT5 = (1 << 15),
HRTIM_OUT_RST_TIMEVNT4 = (1 << 16),
HRTIM_OUT_RST_TIMEVNT3 = (1 << 17),
HRTIM_OUT_RST_TIMEVNT2 = (1 << 18),
HRTIM_OUT_RST_TIMEVNT1 = (1 << 19),
HRTIM_OUT_RST_MSTCMP4 = (1 << 20),
HRTIM_OUT_RST_MSTCMP3 = (1 << 21),
HRTIM_OUT_RST_MSTCMP2 = (1 << 22),
HRTIM_OUT_RST_MSTCMP1 = (1 << 23),
HRTIM_OUT_RST_MSTPER = (1 << 24),
HRTIM_OUT_RST_CMP4 = (1 << 25),
HRTIM_OUT_RST_CMP3 = (1 << 26),
HRTIM_OUT_RST_CMP2 = (1 << 27),
HRTIM_OUT_RST_CMP1 = (1 << 28),
HRTIM_OUT_RST_PER = (1 << 29),
HRTIM_OUT_RST_RESYNC = (1 << 30),
HRTIM_OUT_RST_SOFT = (1 << 31),
};
/* Source which can force the Tx1/Tx2 output to its active state */
enum stm32_hrtim_out_set_e
{
HRTIM_OUT_SET_UPDATE = (1 << 0),
HRTIM_OUT_SET_EXTEVNT10 = (1 << 1),
HRTIM_OUT_SET_EXTEVNT9 = (1 << 2),
HRTIM_OUT_SET_EXTEVNT8 = (1 << 3),
HRTIM_OUT_SET_EXTEVNT7 = (1 << 4),
HRTIM_OUT_SET_EXTEVNT6 = (1 << 5),
HRTIM_OUT_SET_EXTEVNT5 = (1 << 6),
HRTIM_OUT_SET_EXTEVNT4 = (1 << 7),
HRTIM_OUT_SET_EXTEVNT3 = (1 << 8),
HRTIM_OUT_SET_EXTEVNT2 = (1 << 9),
HRTIM_OUT_SET_EXTEVNT1 = (1 << 10),
HRTIM_OUT_SET_TIMEVNT9 = (1 << 11),
HRTIM_OUT_SET_TIMEVNT8 = (1 << 12),
HRTIM_OUT_SET_TIMEVNT7 = (1 << 13),
HRTIM_OUT_SET_TIMEVNT6 = (1 << 14),
HRTIM_OUT_SET_TIMEVNT5 = (1 << 15),
HRTIM_OUT_SET_TIMEVNT4 = (1 << 16),
HRTIM_OUT_SET_TIMEVNT3 = (1 << 17),
HRTIM_OUT_SET_TIMEVNT2 = (1 << 18),
HRTIM_OUT_SET_TIMEVNT1 = (1 << 19),
HRTIM_OUT_SET_MSTCMP4 = (1 << 20),
HRTIM_OUT_SET_MSTCMP3 = (1 << 21),
HRTIM_OUT_SET_MSTCMP2 = (1 << 22),
HRTIM_OUT_SET_MSTCMP1 = (1 << 23),
HRTIM_OUT_SET_MSTPER = (1 << 24),
HRTIM_OUT_SET_CMP4 = (1 << 25),
HRTIM_OUT_SET_CMP3 = (1 << 26),
HRTIM_OUT_SET_CMP2 = (1 << 27),
HRTIM_OUT_SET_CMP1 = (1 << 28),
HRTIM_OUT_SET_PER = (1 << 29),
HRTIM_OUT_SET_RESYNC = (1 << 30),
HRTIM_OUT_SET_SOFT = (1 << 31),
};
/* Events that can reset TimerX Counter */
enum stm32_hrtim_tim_rst_e
{
/* Timer owns events */
HRTIM_RST_UPDT,
HRTIM_RST_CMP4,
HRTIM_RST_CMP2,
/* Master Timer Events */
HRTIM_RST_MSTCMP4,
HRTIM_RST_MSTCMP3,
HRTIM_RST_MSTCMP2,
HRTIM_RST_MSTCMP1,
HRTIM_RST_MSTPER,
/* TimerX events */
HRTIM_RST_TECMP4,
HRTIM_RST_TECMP2,
HRTIM_RST_TECMP1,
HRTIM_RST_TDCMP4,
HRTIM_RST_TDCMP2,
HRTIM_RST_TDCMP1,
HRTIM_RST_TCCMP4,
HRTIM_RST_TCCMP2,
HRTIM_RST_TCCMP1,
HRTIM_RST_TBCMP4,
HRTIM_RST_TBCMP2,
HRTIM_RST_TBCMP1,
HRTIM_RST_TACMP4,
HRTIM_RST_TACMP2,
HRTIM_RST_TACMP1,
/* External Events */
HRTIM_RST_EXTEVNT10,
HRTIM_RST_EXTEVNT9,
HRTIM_RST_EXTEVNT8,
HRTIM_RST_EXTEVNT7,
HRTIM_RST_EXTEVNT6,
HRTIM_RST_EXTEVNT5,
HRTIM_RST_EXTEVNT4,
HRTIM_RST_EXTEVNT3,
HRTIM_RST_EXTEVNT2,
HRTIM_RST_EXTEVNT1,
};
/* HRTIM Timer X prescaler */
enum stm32_hrtim_tim_prescaler_e
{
HRTIM_PRESCALER_1,
HRTIM_PRESCALER_2,
HRTIM_PRESCALER_4,
HRTIM_PRESCALER_8,
HRTIM_PRESCALER_16,
HRTIM_PRESCALER_32,
HRTIM_PRESCALER_64,
HRTIM_PRESCALER_128,
};
/* HRTIM Fault Source */
enum stm32_hrtim_fault_src_e
{
HRTIM_FAULT_SRC_PIN,
HRTIM_FAULT_SRC_INTERNAL
};
/* HRTIM External Event Source
* NOTE: according to Table 82 from STM32F334XX Manual
*/
enum stm32_hrtim_eev_src_e
{
HRTIM_EEV_SRC_PIN,
HRTIM_EEV_SRC_ANALOG,
HRTIM_EEV_SRC_TRGO,
HRTIM_EEV_SRC_ADC
};
struct hrtim_dev_s
{
#ifdef CONFIG_HRTIM
/* Fields managed by common upper half HRTIM logic */
uint8_t hd_ocount; /* The number of times the device has been opened */
sem_t hd_closesem; /* Locks out new opens while close is in progress */
#endif
/* Fields provided by lower half HRTIM logic */
FAR void *hd_priv; /* Used by the arch-specific logic */
};
/************************************************************************************
* Public Function Prototypes
************************************************************************************/
#ifndef __ASSEMBLY__
#ifdef __cplusplus
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Name: stm32_hrtiminitialize
*
* Description:
* Initialize the HRTIM.
*
* Input Parameters:
* None
*
* Returned Value:
* Valid HRTIM device structure reference on succcess; a NULL on failure.
*
* Assumptions:
* 1. Clock to the HRTIM block has enabled,
* 2. Board-specific logic has already configured
*
****************************************************************************/
FAR struct hrtim_dev_s* stm32_hrtiminitialize(void);
/****************************************************************************
* Name: hrtim_register
****************************************************************************/
int hrtim_register(FAR const char *path, FAR struct hrtim_dev_s *dev);
#undef EXTERN
#ifdef __cplusplus
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* CONFIG_STM32_HRTIM1 */
#endif /* __ARCH_ARM_SRC_STM32_STM32_HRTIM_H */

6
arch/arm/src/stm32/stm32_pwm.c
View file

@ -1301,7 +1301,7 @@ static int pwm_timer(FAR struct stm32_pwmtimer_s *priv,
timclk = priv->pclk / prescaler;
reload = timclk / info->frequency;
if (reload < 1)
if (reload < 2)
{
reload = 1;
}
@ -1309,6 +1309,10 @@ static int pwm_timer(FAR struct stm32_pwmtimer_s *priv,
{
reload = 65535;
}
else
{
reload--;
}
pwminfo("TIM%u PCLK: %u frequency: %u TIMCLK: %u prescaler: %u reload: %u\n",
priv->timid, priv->pclk, info->frequency, timclk, prescaler, reload);

2
arch/arm/src/stm32/stm32f33xxx_rcc.c
View file

@ -332,9 +332,7 @@ static inline void rcc_enableapb2(void)
#ifdef CONFIG_STM32_HRTIM1
/* HRTIM1 Timer clock enable */
#ifdef CONFIG_STM32_FORCEPOWER
regval |= RCC_APB2ENR_HRTIM1EN;
#endif
#endif
putreg32(regval, STM32_RCC_APB2ENR);

80
arch/arm/src/stm32l4/Kconfig
View file

@ -220,6 +220,54 @@ config ARCH_CHIP_STM32L462VE
---help---
STM32 L4 Cortex M4, USB FS, AES, 512 Kb FLASH, 128+32 Kb SRAM
config ARCH_CHIP_STM32L475RG
bool "STM32L475RG"
select STM32L4_STM32L475XX
select STM32L4_FLASH_CONFIG_G
select STM32L4_IO_CONFIG_R
---help---
STM32 L4 Cortex M4, 1024Kb FLASH, 96+32 Kb SRAM, LQFP100
config ARCH_CHIP_STM32L475RE
bool "STM32L475RE"
select STM32L4_STM32L475XX
select STM32L4_FLASH_CONFIG_E
select STM32L4_IO_CONFIG_R
---help---
STM32 L4 Cortex M4, 512Kb FLASH, 96+32 Kb SRAM, LQFP100
config ARCH_CHIP_STM32L475RC
bool "STM32L475RC"
select STM32L4_STM32L475XX
select STM32L4_FLASH_CONFIG_E
select STM32L4_IO_CONFIG_R
---help---
STM32 L4 Cortex M4, 256Kb FLASH, 96+32 Kb SRAM, LQFP100
config ARCH_CHIP_STM32L475VG
bool "STM32L475VG"
select STM32L4_STM32L475XX
select STM32L4_FLASH_CONFIG_G
select STM32L4_IO_CONFIG_R
---help---
STM32 L4 Cortex M4, 1024Kb FLASH, 96+32 Kb SRAM, LQFP64
config ARCH_CHIP_STM32L475VE
bool "STM32L475VE"
select STM32L4_STM32L475XX
select STM32L4_FLASH_CONFIG_E
select STM32L4_IO_CONFIG_R
---help---
STM32 L4 Cortex M4, 512Kb FLASH, 96+32 Kb SRAM, LQFP64
config ARCH_CHIP_STM32L475VC
bool "STM32L475VC"
select STM32L4_STM32L475XX
select STM32L4_FLASH_CONFIG_E
select STM32L4_IO_CONFIG_R
---help---
STM32 L4 Cortex M4, 256Kb FLASH, 96+32 Kb SRAM, LQFP64
config ARCH_CHIP_STM32L476RG
bool "STM32L476RG"
select STM32L4_STM32L476XX
@ -322,6 +370,33 @@ config STM32L4_STM32L4X5
select STM32L4_HAVE_OTGFS
select STM32L4_HAVE_DFSDM1
config STM32L4_STM32L4X5
bool
default n
select ARCH_HAVE_FPU
select STM32L4_HAVE_USART1
select STM32L4_HAVE_USART2
select STM32L4_HAVE_USART3
select STM32L4_HAVE_UART4
select STM32L4_HAVE_UART5
select STM32L4_HAVE_ADC2
select STM32L4_HAVE_ADC3
select STM32L4_HAVE_DAC2
select STM32L4_HAVE_FSMC
select STM32L4_HAVE_TIM3
select STM32L4_HAVE_TIM4
select STM32L4_HAVE_TIM5
select STM32L4_HAVE_TIM7
select STM32L4_HAVE_TIM8
select STM32L4_HAVE_TIM17
select STM32L4_HAVE_LPTIM1
select STM32L4_HAVE_LPTIM2
select STM32L4_HAVE_COMP
select STM32L4_HAVE_SAI1
select STM32L4_HAVE_SAI2
select STM32L4_HAVE_SDMMC1
select STM32L4_HAVE_OTGFS
config STM32L4_STM32L4X6
bool
default n
@ -422,6 +497,11 @@ config STM32L4_STM32L471XX
default n
# TODO
config STM32L4_STM32L475XX
bool
default n
select STM32L4_STM32L4X5
config STM32L4_STM32L476XX
bool
default n

20
arch/arm/src/stm32l4/chip.h
View file

@ -51,6 +51,10 @@
#include "chip/stm32l4_pinmap.h"
#include "chip/stm32l4_memorymap.h"
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* If the common ARMv7-M vector handling logic is used, then it expects the
* following definition in this file that provides the number of supported external
* interrupts which, for this architecture, is provided in the arch/stm32l4/chip.h
@ -64,20 +68,4 @@
#define ARMV7M_DCACHE_LINESIZE 0 /* no cache */
#define ARMV7M_ICACHE_LINESIZE 0 /* no cache */
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/************************************************************************************
* Public Types
************************************************************************************/
/************************************************************************************
* Public Data
************************************************************************************/
/************************************************************************************
* Public Functions
************************************************************************************/
#endif /* __ARCH_ARM_SRC_STM32L4_CHIP_H */

9
arch/arm/src/stm32l4/chip/stm32l4_pinmap.h
View file

@ -1,6 +1,7 @@
/************************************************************************************
* arch/arm/src/stm32l4/chip/stm32l4_pinmap.h
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
* Copyright (C) 2015 Sebastien Lorquet. All rights reserved.
* Author: Sebastien Lorquet <sebastien@lorquet.fr>
*
@ -43,10 +44,12 @@
#include <nuttx/config.h>
#include "chip.h"
#if defined(CONFIG_STM32L4_STM32L4X6)
# include "chip/stm32l4x6xx_pinmap.h"
#elif defined(CONFIG_STM32L4_STM32L4X3)
#if defined(CONFIG_STM32L4_STM32L4X3)
# include "chip/stm32l4x3xx_pinmap.h"
#elif defined(CONFIG_STM32L4_STM32L4X5)
# include "chip/stm32l4x5xx_pinmap.h"
#elif defined(CONFIG_STM32L4_STM32L4X6)
# include "chip/stm32l4x6xx_pinmap.h"
#else
# error "Unsupported STM32 L4 pin map"
#endif

9
arch/arm/src/stm32l4/chip/stm32l4_syscfg.h
View file

@ -43,13 +43,14 @@
#include <nuttx/config.h>
#include "chip.h"
#if defined(CONFIG_STM32L4_STM32L4X6)
# include "chip/stm32l4x6xx_syscfg.h"
#elif defined(CONFIG_STM32L4_STM32L4X3)
#if defined(CONFIG_STM32L4_STM32L4X3)
# include "chip/stm32l4x3xx_syscfg.h"
#elif defined(CONFIG_STM32L4_STM32L4X5)
# include "chip/stm32l4x5xx_syscfg.h"
#elif defined(CONFIG_STM32L4_STM32L4X6)
# include "chip/stm32l4x6xx_syscfg.h"
#else
# error "Unsupported STM32 L4 chip"
#endif
#endif /* __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4_SYSCFG_H */

2
arch/arm/src/stm32l4/chip/stm32l4x3xx_rcc.h
View file

@ -126,7 +126,7 @@
#define RCC_CR_MSION (1 << 0) /* Bit 0: Internal Multi Speed clock enable */
#define RCC_CR_MSIRDY (1 << 1) /* Bit 1: Internal Multi Speed clock ready flag */
#define RCC_CR_MSIPLLEN (1 << 2) /* Bit 2: MSI clock PLL enable */
#define RCC_CR_MSIRGSEL (1 << 3) /* Bit 2: MSI clock range selection */
#define RCC_CR_MSIRGSEL (1 << 3) /* Bit 3: MSI clock range selection */
#define RCC_CR_MSIRANGE_SHIFT (4) /* Bits 7-4: MSI clock range */
#define RCC_CR_MSIRANGE_MASK (0x0f << RCC_CR_MSIRANGE_SHIFT)
# define RCC_CR_MSIRANGE_100K (0 << RCC_CR_MSIRANGE_SHIFT) /* 0000: around 100 kHz */

113
arch/arm/src/stm32l4/chip/stm32l4x5xx_dbgmcu.h Normal file
View file

@ -0,0 +1,113 @@
/****************************************************************************
* arch/arm/src/stm32l4/chip/stm32l4x5xx_dbgmcu.h
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
* Authors: Gregory Nutt <gnutt@nuttx.org>
* David Sidrane <david_s5@nscdg.com>
* Juha Niskanen <juha.niskanen@haltian.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4X5XX_DBGMCU_H
#define __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4X5XX_DBGMCU_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Register Addresses *******************************************************/
#define STM32_DBGMCU_IDCODE 0xe0042000 /* MCU identifier */
#define STM32_DBGMCU_CR 0xe0042004 /* MCU debug */
#define STM32_DBGMCU_APB1_FZ 0xe0042008 /* Debug MCU APB1 freeze register */
#define STM32_DBGMCU_APB1_FZ2 0xe004200c /* Debug MCU APB1 freeze register 2 */
#define STM32_DBGMCU_APB2_FZ 0xe0042010 /* Debug MCU APB2 freeze register */
/* Register Bitfield Definitions ********************************************/
/* MCU identifier */
#define DBGMCU_IDCODE_DEVID_SHIFT (0) /* Bits 11-0: Device Identifier */
#define DBGMCU_IDCODE_DEVID_MASK (0x0fff << DBGMCU_IDCODE_DEVID_SHIFT)
#define DBGMCU_IDCODE_REVID_SHIFT (16) /* Bits 31-16: Revision Identifier */
#define DBGMCU_IDCODE_REVID_MASK (0xffff << DBGMCU_IDCODE_REVID_SHIFT)
/* MCU debug */
#define DBGMCU_CR_SLEEP (1 << 0) /* Bit 0: Debug Sleep Mode */
#define DBGMCU_CR_STOP (1 << 1) /* Bit 1: Debug Stop Mode */
#define DBGMCU_CR_STANDBY (1 << 2) /* Bit 2: Debug Standby mode */
#define DBGMCU_CR_TRACEIOEN (1 << 5) /* Bit 5: Trace enabled */
#define DBGMCU_CR_TRACEMODE_SHIFT (6) /* Bits 7-6: Trace mode pin assignment */
#define DBGMCU_CR_TRACEMODE_MASK (3 << DBGMCU_CR_TRACEMODE_SHIFT)
# define DBGMCU_CR_ASYNCH (0 << DBGMCU_CR_TRACEMODE_SHIFT) /* Asynchronous Mode */
# define DBGMCU_CR_SYNCH1 (1 << DBGMCU_CR_TRACEMODE_SHIFT) /* Synchronous Mode, TRACEDATA size=1 */
# define DBGMCU_CR_SYNCH2 (2 << DBGMCU_CR_TRACEMODE_SHIFT) /* Synchronous Mode, TRACEDATA size=2 */
# define DBGMCU_CR_SYNCH4 (3 << DBGMCU_CR_TRACEMODE_SHIFT) /* Synchronous Mode, TRACEDATA size=4 */
/* Debug MCU APB1 freeze register */
#define DBGMCU_APB1_TIM2STOP (1 << 0) /* Bit 0: TIM2 stopped when core is halted */
#define DBGMCU_APB1_TIM3STOP (1 << 1) /* Bit 1: TIM3 stopped when core is halted */
#define DBGMCU_APB1_TIM4STOP (1 << 2) /* Bit 2: TIM4 stopped when core is halted */
#define DBGMCU_APB1_TIM5STOP (1 << 3) /* Bit 3: TIM5 stopped when core is halted */
#define DBGMCU_APB1_TIM6STOP (1 << 4) /* Bit 4: TIM6 stopped when core is halted */
#define DBGMCU_APB1_TIM7STOP (1 << 5) /* Bit 5: TIM7 stopped when core is halted */
#define DBGMCU_APB1_RTCSTOP (1 << 10) /* Bit 10: RTC stopped when Core is halted */
#define DBGMCU_APB1_WWDGSTOP (1 << 11) /* Bit 11: Window Watchdog stopped when core is halted */
#define DBGMCU_APB1_IWDGSTOP (1 << 12) /* Bit 12: Independent Watchdog stopped when core is halted */
#define DBGMCU_APB1_I2C1STOP (1 << 21) /* Bit 21: I2C1 SMBUS timeout mode stopped when Core is halted */
#define DBGMCU_APB1_I2C2STOP (1 << 22) /* Bit 22: I2C2 SMBUS timeout mode stopped when Core is halted */
#define DBGMCU_APB1_I2C3STOP (1 << 23) /* Bit 23: I2C3 SMBUS timeout mode stopped when Core is halted */
#define DBGMCU_APB1_CAN1STOP (1 << 25) /* Bit 25: CAN1 stopped when core is halted */
#define DBGMCU_APB1_LPTIM1STOP (1 << 31) /* Bit 31: LPTIM1 stopper when core is halted */
/* Debug MCU APB1 freeze register 2 */
#define DBGMCU_APB1_FZ2_LPTIM2STOP (1 << 5) /* Bit 5: LPTIM2 stopper when core is halted */
/* Debug MCU APB2 freeze register */
#define DBGMCU_APB2_TIM1STOP (1 << 11) /* Bit 11: TIM1 stopped when core is halted */
#define DBGMCU_APB2_TIM8STOP (1 << 13) /* Bit 13: TIM8 stopped when core is halted */
#define DBGMCU_APB2_TIM15STOP (1 << 16) /* Bit 16: TIM15 stopped when core is halted */
#define DBGMCU_APB2_TIM16STOP (1 << 17) /* Bit 17: TIM16 stopped when core is halted */
#define DBGMCU_APB2_TIM17STOP (1 << 18) /* Bit 18: TIM17 stopped when core is halted */
#endif /* __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4X5XXDBGMCU_H */

485
arch/arm/src/stm32l4/chip/stm32l4x5xx_dma.h Normal file
View file

@ -0,0 +1,485 @@
/************************************************************************************
* arch/arm/src/stm32l4/chip/stm32l4x6xx_dma.h
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4X5XX_DMA_H
#define __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4X5XX_DMA_H
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* 14 Channels Total: 7 DMA1 Channels(1-7) and 7 DMA2 channels (1-7) */
#define DMA1 0
#define DMA2 1
#define DMA3 2
#define DMA4 3
#define DMA5 4
#define DMA6 5
#define DMA7 6
/* Register Offsets *****************************************************************/
#define STM32L4_DMA_ISR_OFFSET 0x0000 /* DMA interrupt status register */
#define STM32L4_DMA_IFCR_OFFSET 0x0004 /* DMA interrupt flag clear register */
#define STM32L4_DMACHAN_OFFSET(n) (0x0014*(n))
#define STM32L4_DMACHAN1_OFFSET 0x0000
#define STM32L4_DMACHAN2_OFFSET 0x0014
#define STM32L4_DMACHAN3_OFFSET 0x0028
#define STM32L4_DMACHAN4_OFFSET 0x003c
#define STM32L4_DMACHAN5_OFFSET 0x0050
#define STM32L4_DMACHAN6_OFFSET 0x0064
#define STM32L4_DMACHAN7_OFFSET 0x0078
#define STM32L4_DMACHAN_CCR_OFFSET 0x0008 /* DMA channel configuration register */
#define STM32L4_DMACHAN_CNDTR_OFFSET 0x000c /* DMA channel number of data register */
#define STM32L4_DMACHAN_CPAR_OFFSET 0x0010 /* DMA channel peripheral address register */
#define STM32L4_DMACHAN_CMAR_OFFSET 0x0014 /* DMA channel memory address register */
#define STM32L4_DMA_CCR_OFFSET(n) (STM32L4_DMACHAN_CCR_OFFSET+STM32L4_DMACHAN_OFFSET(n))
#define STM32L4_DMA_CNDTR_OFFSET(n) (STM32L4_DMACHAN_CNDTR_OFFSET+STM32L4_DMACHAN_OFFSET(n))
#define STM32L4_DMA_CPAR_OFFSET(n) (STM32L4_DMACHAN_CPAR_OFFSET+STM32L4_DMACHAN_OFFSET(n))
#define STM32L4_DMA_CMAR_OFFSET(n) (STM32L4_DMACHAN_CMAR_OFFSET+STM32L4_DMACHAN_OFFSET(n))
#define STM32L4_DMA_CCR1_OFFSET 0x0008 /* DMA channel 1 configuration register */
#define STM32L4_DMA_CCR2_OFFSET 0x001c /* DMA channel 2 configuration register */
#define STM32L4_DMA_CCR3_OFFSET 0x0030 /* DMA channel 3 configuration register */
#define STM32L4_DMA_CCR4_OFFSET 0x0044 /* DMA channel 4 configuration register */
#define STM32L4_DMA_CCR5_OFFSET 0x0058 /* DMA channel 5 configuration register */
#define STM32L4_DMA_CCR6_OFFSET 0x006c /* DMA channel 6 configuration register */
#define STM32L4_DMA_CCR7_OFFSET 0x0080 /* DMA channel 7 configuration register */
#define STM32L4_DMA_CNDTR1_OFFSET 0x000c /* DMA channel 1 number of data register */
#define STM32L4_DMA_CNDTR2_OFFSET 0x0020 /* DMA channel 2 number of data register */
#define STM32L4_DMA_CNDTR3_OFFSET 0x0034 /* DMA channel 3 number of data register */
#define STM32L4_DMA_CNDTR4_OFFSET 0x0048 /* DMA channel 4 number of data register */
#define STM32L4_DMA_CNDTR5_OFFSET 0x005c /* DMA channel 5 number of data register */
#define STM32L4_DMA_CNDTR6_OFFSET 0x0070 /* DMA channel 6 number of data register */
#define STM32L4_DMA_CNDTR7_OFFSET 0x0084 /* DMA channel 7 number of data register */
#define STM32L4_DMA_CPAR1_OFFSET 0x0010 /* DMA channel 1 peripheral address register */
#define STM32L4_DMA_CPAR2_OFFSET 0x0024 /* DMA channel 2 peripheral address register */
#define STM32L4_DMA_CPAR3_OFFSET 0x0038 /* DMA channel 3 peripheral address register */
#define STM32L4_DMA_CPAR4_OFFSET 0x004c /* DMA channel 4 peripheral address register */
#define STM32L4_DMA_CPAR5_OFFSET 0x0060 /* DMA channel 5 peripheral address register */
#define STM32L4_DMA_CPAR6_OFFSET 0x0074 /* DMA channel 6 peripheral address register */
#define STM32L4_DMA_CPAR7_OFFSET 0x0088 /* DMA channel 7 peripheral address register */
#define STM32L4_DMA_CMAR1_OFFSET 0x0014 /* DMA channel 1 memory address register */
#define STM32L4_DMA_CMAR2_OFFSET 0x0028 /* DMA channel 2 memory address register */
#define STM32L4_DMA_CMAR3_OFFSET 0x003c /* DMA channel 3 memory address register */
#define STM32L4_DMA_CMAR4_OFFSET 0x0050 /* DMA channel 4 memory address register */
#define STM32L4_DMA_CMAR5_OFFSET 0x0064 /* DMA channel 5 memory address register */
#define STM32L4_DMA_CMAR6_OFFSET 0x0078 /* DMA channel 6 memory address register */
#define STM32L4_DMA_CMAR7_OFFSET 0x008c /* DMA channel 7 memory address register */
#define STM32L4_DMA_CSELR_OFFSET 0x00a8 /* DMA channel selection register */
/* Register Addresses ***************************************************************/
#define STM32L4_DMA1_ISRC (STM32L4_DMA1_BASE+STM32L4_DMA_ISR_OFFSET)
#define STM32L4_DMA1_IFCR (STM32L4_DMA1_BASE+STM32L4_DMA_IFCR_OFFSET)
#define STM32L4_DMA1_CCR(n) (STM32L4_DMA1_BASE+STM32L4_DMA_CCR_OFFSET(n))
#define STM32L4_DMA1_CCR1 (STM32L4_DMA1_BASE+STM32L4_DMA_CCR1_OFFSET)
#define STM32L4_DMA1_CCR2 (STM32L4_DMA1_BASE+STM32L4_DMA_CCR2_OFFSET)
#define STM32L4_DMA1_CCR3 (STM32L4_DMA1_BASE+STM32L4_DMA_CCR3_OFFSET)
#define STM32L4_DMA1_CCR4 (STM32L4_DMA1_BASE+STM32L4_DMA_CCR4_OFFSET)
#define STM32L4_DMA1_CCR5 (STM32L4_DMA1_BASE+STM32L4_DMA_CCR5_OFFSET)
#define STM32L4_DMA1_CCR6 (STM32L4_DMA1_BASE+STM32L4_DMA_CCR6_OFFSET)
#define STM32L4_DMA1_CCR7 (STM32L4_DMA1_BASE+STM32L4_DMA_CCR7_OFFSET)
#define STM32L4_DMA1_CNDTR(n) (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR_OFFSET(n))
#define STM32L4_DMA1_CNDTR1 (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR1_OFFSET)
#define STM32L4_DMA1_CNDTR2 (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR2_OFFSET)
#define STM32L4_DMA1_CNDTR3 (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR3_OFFSET)
#define STM32L4_DMA1_CNDTR4 (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR4_OFFSET)
#define STM32L4_DMA1_CNDTR5 (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR5_OFFSET)
#define STM32L4_DMA1_CNDTR6 (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR6_OFFSET)
#define STM32L4_DMA1_CNDTR7 (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR7_OFFSET)
#define STM32L4_DMA1_CPAR(n) (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR_OFFSET(n))
#define STM32L4_DMA1_CPAR1 (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR1_OFFSET)
#define STM32L4_DMA1_CPAR2 (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR2_OFFSET)
#define STM32L4_DMA1_CPAR3 (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR3_OFFSET)
#define STM32L4_DMA1_CPAR4 (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR4_OFFSET)
#define STM32L4_DMA1_CPAR5 (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR5_OFFSET)
#define STM32L4_DMA1_CPAR6 (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR6_OFFSET)
#define STM32L4_DMA1_CPAR7 (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR7_OFFSET)
#define STM32L4_DMA1_CMAR(n) (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR_OFFSET(n))
#define STM32L4_DMA1_CMAR1 (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR1_OFFSET)
#define STM32L4_DMA1_CMAR2 (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR2_OFFSET)
#define STM32L4_DMA1_CMAR3 (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR3_OFFSET)
#define STM32L4_DMA1_CMAR4 (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR4_OFFSET)
#define STM32L4_DMA1_CMAR5 (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR5_OFFSET)
#define STM32L4_DMA1_CMAR6 (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR6_OFFSET)
#define STM32L4_DMA1_CMAR7 (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR7_OFFSET)
#define STM32L4_DMA2_ISRC (STM32L4_DMA2_BASE+STM32L4_DMA_ISR_OFFSET)
#define STM32L4_DMA2_IFCR (STM32L4_DMA2_BASE+STM32L4_DMA_IFCR_OFFSET)
#define STM32L4_DMA2_CCR(n) (STM32L4_DMA2_BASE+STM32L4_DMA_CCR_OFFSET(n))
#define STM32L4_DMA2_CCR1 (STM32L4_DMA2_BASE+STM32L4_DMA_CCR1_OFFSET)
#define STM32L4_DMA2_CCR2 (STM32L4_DMA2_BASE+STM32L4_DMA_CCR2_OFFSET)
#define STM32L4_DMA2_CCR3 (STM32L4_DMA2_BASE+STM32L4_DMA_CCR3_OFFSET)
#define STM32L4_DMA2_CCR4 (STM32L4_DMA2_BASE+STM32L4_DMA_CCR4_OFFSET)
#define STM32L4_DMA2_CCR5 (STM32L4_DMA2_BASE+STM32L4_DMA_CCR5_OFFSET)
#define STM32L4_DMA2_CCR6 (STM32L4_DMA2_BASE+STM32L4_DMA_CCR6_OFFSET)
#define STM32L4_DMA2_CCR7 (STM32L4_DMA2_BASE+STM32L4_DMA_CCR7_OFFSET)
#define STM32L4_DMA2_CNDTR(n) (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR_OFFSET(n))
#define STM32L4_DMA2_CNDTR1 (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR1_OFFSET)
#define STM32L4_DMA2_CNDTR2 (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR2_OFFSET)
#define STM32L4_DMA2_CNDTR3 (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR3_OFFSET)
#define STM32L4_DMA2_CNDTR4 (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR4_OFFSET)
#define STM32L4_DMA2_CNDTR5 (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR5_OFFSET)
#define STM32L4_DMA2_CNDTR6 (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR6_OFFSET)
#define STM32L4_DMA2_CNDTR7 (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR7_OFFSET)
#define STM32L4_DMA2_CPAR(n) (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR_OFFSET(n))
#define STM32L4_DMA2_CPAR1 (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR1_OFFSET)
#define STM32L4_DMA2_CPAR2 (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR2_OFFSET)
#define STM32L4_DMA2_CPAR3 (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR3_OFFSET)
#define STM32L4_DMA2_CPAR4 (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR4_OFFSET)
#define STM32L4_DMA2_CPAR5 (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR5_OFFSET)
#define STM32L4_DMA2_CPAR6 (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR6_OFFSET)
#define STM32L4_DMA2_CPAR7 (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR7_OFFSET)
#define STM32L4_DMA2_CMAR(n) (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR_OFFSET(n))
#define STM32L4_DMA2_CMAR1 (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR1_OFFSET)
#define STM32L4_DMA2_CMAR2 (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR2_OFFSET)
#define STM32L4_DMA2_CMAR3 (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR3_OFFSET)
#define STM32L4_DMA2_CMAR4 (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR4_OFFSET)
#define STM32L4_DMA2_CMAR5 (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR5_OFFSET)
#define STM32L4_DMA2_CMAR6 (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR6_OFFSET)
#define STM32L4_DMA2_CMAR7 (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR7_OFFSET)
/* Register Bitfield Definitions ****************************************************/
#define DMA_CHAN_SHIFT(n) ((n) << 2)
#define DMA_CHAN_MASK 0x0f
#define DMA_CHAN_GIF_BIT (1 << 0) /* Bit 0: Channel Global interrupt flag */
#define DMA_CHAN_TCIF_BIT (1 << 1) /* Bit 1: Channel Transfer Complete flag */
#define DMA_CHAN_HTIF_BIT (1 << 2) /* Bit 2: Channel Half Transfer flag */
#define DMA_CHAN_TEIF_BIT (1 << 3) /* Bit 3: Channel Transfer Error flag */
/* DMA interrupt status register */
#define DMA_ISR_CHAN_SHIFT(n) DMA_CHAN_SHIFT(n)
#define DMA_ISR_CHAN_MASK(n) (DMA_CHAN_MASK << DMA_ISR_CHAN_SHIFT(n))
#define DMA_ISR_CHAN1_SHIFT (0) /* Bits 3-0: DMA Channel 1 interrupt status */
#define DMA_ISR_CHAN1_MASK (DMA_CHAN_MASK << DMA_ISR_CHAN1_SHIFT)
#define DMA_ISR_CHAN2_SHIFT (4) /* Bits 7-4: DMA Channel 2 interrupt status */
#define DMA_ISR_CHAN2_MASK (DMA_CHAN_MASK << DMA_ISR_CHAN2_SHIFT)
#define DMA_ISR_CHAN3_SHIFT (8) /* Bits 11-8: DMA Channel 3 interrupt status */
#define DMA_ISR_CHAN3_MASK (DMA_CHAN_MASK << DMA_ISR_CHAN3_SHIFT)
#define DMA_ISR_CHAN4_SHIFT (12) /* Bits 15-12: DMA Channel 4 interrupt status */
#define DMA_ISR_CHAN4_MASK (DMA_CHAN_MASK << DMA_ISR_CHAN4_SHIFT)
#define DMA_ISR_CHAN5_SHIFT (16) /* Bits 19-16: DMA Channel 5 interrupt status */
#define DMA_ISR_CHAN5_MASK (DMA_CHAN_MASK << DMA_ISR_CHAN5_SHIFT)
#define DMA_ISR_CHAN6_SHIFT (20) /* Bits 23-20: DMA Channel 6 interrupt status */
#define DMA_ISR_CHAN6_MASK (DMA_CHAN_MASK << DMA_ISR_CHAN6_SHIFT)
#define DMA_ISR_CHAN7_SHIFT (24) /* Bits 27-24: DMA Channel 7 interrupt status */
#define DMA_ISR_CHAN7_MASK (DMA_CHAN_MASK << DMA_ISR_CHAN7_SHIFT)
#define DMA_ISR_GIF(n) (DMA_CHAN_GIF_BIT << DMA_ISR_CHAN_SHIFT(n))
#define DMA_ISR_TCIF(n) (DMA_CHAN_TCIF_BIT << DMA_ISR_CHAN_SHIFT(n))
#define DMA_ISR_HTIF(n) (DMA_CHAN_HTIF_BIT << DMA_ISR_CHAN_SHIFT(n))
#define DMA_ISR_TEIF(n) (DMA_CHAN_TEIF_BIT << DMA_ISR_CHAN_SHIFT(n))
/* DMA interrupt flag clear register */
#define DMA_IFCR_CHAN_SHIFT(n) DMA_CHAN_SHIFT(n)
#define DMA_IFCR_CHAN_MASK(n) (DMA_CHAN_MASK << DMA_IFCR_CHAN_SHIFT(n))
#define DMA_IFCR_CHAN1_SHIFT (0) /* Bits 3-0: DMA Channel 1 interrupt flag clear */
#define DMA_IFCR_CHAN1_MASK (DMA_CHAN_MASK << DMA_IFCR_CHAN1_SHIFT)
#define DMA_IFCR_CHAN2_SHIFT (4) /* Bits 7-4: DMA Channel 2 interrupt flag clear */
#define DMA_IFCR_CHAN2_MASK (DMA_CHAN_MASK << DMA_IFCR_CHAN2_SHIFT)
#define DMA_IFCR_CHAN3_SHIFT (8) /* Bits 11-8: DMA Channel 3 interrupt flag clear */
#define DMA_IFCR_CHAN3_MASK (DMA_CHAN_MASK << DMA_IFCR_CHAN3_SHIFT)
#define DMA_IFCR_CHAN4_SHIFT (12) /* Bits 15-12: DMA Channel 4 interrupt flag clear */
#define DMA_IFCR_CHAN4_MASK (DMA_CHAN_MASK << DMA_IFCR_CHAN4_SHIFT)
#define DMA_IFCR_CHAN5_SHIFT (16) /* Bits 19-16: DMA Channel 5 interrupt flag clear */
#define DMA_IFCR_CHAN5_MASK (DMA_CHAN_MASK << DMA_IFCR_CHAN5_SHIFT)
#define DMA_IFCR_CHAN6_SHIFT (20) /* Bits 23-20: DMA Channel 6 interrupt flag clear */
#define DMA_IFCR_CHAN6_MASK (DMA_CHAN_MASK << DMA_IFCR_CHAN6_SHIFT)
#define DMA_IFCR_CHAN7_SHIFT (24) /* Bits 27-24: DMA Channel 7 interrupt flag clear */
#define DMA_IFCR_CHAN7_MASK (DMA_CHAN_MASK << DMA_IFCR_CHAN7_SHIFT)
#define DMA_IFCR_ALLCHANNELS (0x0fffffff)
#define DMA_IFCR_CGIF(n) (DMA_CHAN_GIF_BIT << DMA_IFCR_CHAN_SHIFT(n))
#define DMA_IFCR_CTCIF(n) (DMA_CHAN_TCIF_BIT << DMA_IFCR_CHAN_SHIFT(n))
#define DMA_IFCR_CHTIF(n) (DMA_CHAN_HTIF_BIT << DMA_IFCR_CHAN_SHIFT(n))
#define DMA_IFCR_CTEIF(n) (DMA_CHAN_TEIF_BIT << DMA_IFCR_CHAN_SHIFT(n))
/* DMA channel configuration register */
#define DMA_CCR_EN (1 << 0) /* Bit 0: Channel enable */
#define DMA_CCR_TCIE (1 << 1) /* Bit 1: Transfer complete interrupt enable */
#define DMA_CCR_HTIE (1 << 2) /* Bit 2: Half Transfer interrupt enable */
#define DMA_CCR_TEIE (1 << 3) /* Bit 3: Transfer error interrupt enable */
#define DMA_CCR_DIR (1 << 4) /* Bit 4: Data transfer direction */
#define DMA_CCR_CIRC (1 << 5) /* Bit 5: Circular mode */
#define DMA_CCR_PINC (1 << 6) /* Bit 6: Peripheral increment mode */
#define DMA_CCR_MINC (1 << 7) /* Bit 7: Memory increment mode */
#define DMA_CCR_PSIZE_SHIFT (8) /* Bits 8-9: Peripheral size */
#define DMA_CCR_PSIZE_MASK (3 << DMA_CCR_PSIZE_SHIFT)
# define DMA_CCR_PSIZE_8BITS (0 << DMA_CCR_PSIZE_SHIFT) /* 00: 8-bits */
# define DMA_CCR_PSIZE_16BITS (1 << DMA_CCR_PSIZE_SHIFT) /* 01: 16-bits */
# define DMA_CCR_PSIZE_32BITS (2 << DMA_CCR_PSIZE_SHIFT) /* 10: 32-bits */
#define DMA_CCR_MSIZE_SHIFT (10) /* Bits 10-11: Memory size */
#define DMA_CCR_MSIZE_MASK (3 << DMA_CCR_MSIZE_SHIFT)
# define DMA_CCR_MSIZE_8BITS (0 << DMA_CCR_MSIZE_SHIFT) /* 00: 8-bits */
# define DMA_CCR_MSIZE_16BITS (1 << DMA_CCR_MSIZE_SHIFT) /* 01: 16-bits */
# define DMA_CCR_MSIZE_32BITS (2 << DMA_CCR_MSIZE_SHIFT) /* 10: 32-bits */
#define DMA_CCR_PL_SHIFT (12) /* Bits 12-13: Channel Priority level */
#define DMA_CCR_PL_MASK (3 << DMA_CCR_PL_SHIFT)
# define DMA_CCR_PRILO (0 << DMA_CCR_PL_SHIFT) /* 00: Low */
# define DMA_CCR_PRIMED (1 << DMA_CCR_PL_SHIFT) /* 01: Medium */
# define DMA_CCR_PRIHI (2 << DMA_CCR_PL_SHIFT) /* 10: High */
# define DMA_CCR_PRIVERYHI (3 << DMA_CCR_PL_SHIFT) /* 11: Very high */
#define DMA_CCR_MEM2MEM (1 << 14) /* Bit 14: Memory to memory mode */
#define DMA_CCR_ALLINTS (DMA_CCR_TEIE|DMA_CCR_HTIE|DMA_CCR_TCIE)
/* DMA channel number of data register */
#define DMA_CNDTR_NDT_SHIFT (0) /* Bits 15-0: Number of data to Transfer */
#define DMA_CNDTR_NDT_MASK (0xffff << DMA_CNDTR_NDT_SHIFT)
/* DMA Channel mapping. Each DMA channel has a mapping to one of several
* possible sources/sinks of data. The requests from peripherals assigned to a
* channel are multiplexed together before entering the DMA block. This means
* that only one request on a given channel can be enabled at once.
*
* Alternative DMA channel selections are provided with a numeric suffix like _1,
* _2, etc. Drivers, however, will use the pin selection without the numeric suffix.
* Additional definitions are required in the board.h file.
*/
#define STM32L4_DMA1_CHAN1 (0)
#define STM32L4_DMA1_CHAN2 (1)
#define STM32L4_DMA1_CHAN3 (2)
#define STM32L4_DMA1_CHAN4 (3)
#define STM32L4_DMA1_CHAN5 (4)
#define STM32L4_DMA1_CHAN6 (5)
#define STM32L4_DMA1_CHAN7 (6)
#define STM32L4_DMA2_CHAN1 (7)
#define STM32L4_DMA2_CHAN2 (8)
#define STM32L4_DMA2_CHAN3 (9)
#define STM32L4_DMA2_CHAN4 (10)
#define STM32L4_DMA2_CHAN5 (11)
#define STM32L4_DMA2_CHAN6 (12)
#define STM32L4_DMA2_CHAN7 (13)
/* DMA Channel settings include a channel and an alternative function.
* Channel is in bits 0..7
* Request number is in bits 8..15
*/
#define DMACHAN_SETTING(chan, req) ((((req) & 0xff) << 8) | ((chan) & 0xff))
#define DMACHAN_SETTING_CHANNEL_MASK 0x00FF
#define DMACHAN_SETTING_CHANNEL_SHIFT (0)
#define DMACHAN_SETTING_FUNCTION_MASK 0xFF00
#define DMACHAN_SETTING_FUNCTION_SHIFT (8)
/* ADC */
#define DMACHAN_ADC1_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN1, 0)
#define DMACHAN_ADC1_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN3, 0)
#define DMACHAN_ADC2_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN1, 0)
#define DMACHAN_ADC2_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN4, 0)
#define DMACHAN_ADC3_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN1, 0)
#define DMACHAN_ADC3_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN5, 0)
/* DAC */
#define DMACHAN_DAC1_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN3, 6)
#define DMACHAN_DAC1_3 DMACHAN_SETTING(STM32L4_DMA2_CHAN4, 3)
#define DMACHAN_DAC2_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN4, 5)
#define DMACHAN_DAC2_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN5, 3)
/* DFSDM */
#define DMACHAN_DFSDM0 DMACHAN_SETTING(STM32L4_DMA1_CHAN4, 0)
#define DMACHAN_DFSDM1 DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 0)
#define DMACHAN_DFSDM2 DMACHAN_SETTING(STM32L4_DMA1_CHAN6, 0)
#define DMACHAN_DFSDM3 DMACHAN_SETTING(STM32L4_DMA1_CHAN7, 0)
/* I2C */
#define DMACHAN_I2C1_RX_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN7, 3)
#define DMACHAN_I2C1_RX_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN6, 5)
#define DMACHAN_I2C1_TX_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN6, 3)
#define DMACHAN_I2C1_TX_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN7, 5)
#define DMACHAN_I2C2_RX DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 3)
#define DMACHAN_I2C2_TX DMACHAN_SETTING(STM32L4_DMA1_CHAN4, 3)
#define DMACHAN_I2C3_RX DMACHAN_SETTING(STM32L4_DMA1_CHAN3, 3)
#define DMACHAN_I2C3_TX DMACHAN_SETTING(STM32L4_DMA1_CHAN2, 3)
/* QUADSPI */
#define DMACHAN_QUADSPI_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 5)
#define DMACHAN_QUADSPI_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN7, 3)
/* SAI */
#define DMACHAN_SAI1_A_1 DMACHAN_SETTING(STM32L4_DMA2_CHAN1, 1)
#define DMACHAN_SAI1_A_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN6, 1)
#define DMACHAN_SAI1_B_1 DMACHAN_SETTING(STM32L4_DMA2_CHAN2, 1)
#define DMACHAN_SAI1_B_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN7, 1)
#define DMACHAN_SAI2_A_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN6, 1)
#define DMACHAN_SAI2_A_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN3, 1)
#define DMACHAN_SAI2_B_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN7, 1)
#define DMACHAN_SAI2_B_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN4, 1)
/* SDMMC */
#define DMACHAN_SDMMC_1 DMACHAN_SETTING(STM32L4_DMA2_CHAN4, 7)
#define DMACHAN_SDMMC_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN5, 7)
/* SPI */
#define DMACHAN_SPI1_RX_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN2, 1)
#define DMACHAN_SPI1_RX_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN3, 4)
#define DMACHAN_SPI1_TX_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN3, 1)
#define DMACHAN_SPI1_TX_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN4, 4)
#define DMACHAN_SPI2_RX DMACHAN_SETTING(STM32L4_DMA1_CHAN4, 1)
#define DMACHAN_SPI2_TX DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 1)
#define DMACHAN_SPI3_RX DMACHAN_SETTING(STM32L4_DMA2_CHAN1, 3)
#define DMACHAN_SPI3_TX DMACHAN_SETTING(STM32L4_DMA2_CHAN2, 3)
/* SWPMI */
#define DMACHAN_SWPMI_RX DMACHAN_SETTING(STM32L4_DMA2_CHAN1, 4)
#define DMACHAN_SWPMI_TX DMACHAN_SETTING(STM32L4_DMA2_CHAN2, 4)
/* TIM */
#define DMACHAN_TIM1_CH1 DMACHAN_SETTING(STM32L4_DMA1_CHAN2, 7)
#define DMACHAN_TIM1_CH2 DMACHAN_SETTING(STM32L4_DMA1_CHAN3, 7)
#define DMACHAN_TIM1_CH3 DMACHAN_SETTING(STM32L4_DMA1_CHAN7, 7)
#define DMACHAN_TIM1_CH4 DMACHAN_SETTING(STM32L4_DMA1_CHAN4, 7)
#define DMACHAN_TIM1_COM DMACHAN_SETTING(STM32L4_DMA1_CHAN4, 7)
#define DMACHAN_TIM1_TRIG DMACHAN_SETTING(STM32L4_DMA1_CHAN4, 7)
#define DMACHAN_TIM1_UP DMACHAN_SETTING(STM32L4_DMA1_CHAN6, 7)
#define DMACHAN_TIM2_CH1 DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 4)
#define DMACHAN_TIM2_CH2 DMACHAN_SETTING(STM32L4_DMA1_CHAN7, 4)
#define DMACHAN_TIM2_CH3 DMACHAN_SETTING(STM32L4_DMA1_CHAN1, 4)
#define DMACHAN_TIM2_CH4 DMACHAN_SETTING(STM32L4_DMA1_CHAN7, 4)
#define DMACHAN_TIM2_UP DMACHAN_SETTING(STM32L4_DMA1_CHAN2, 4)
#define DMACHAN_TIM3_CH1 DMACHAN_SETTING(STM32L4_DMA1_CHAN6, 5)
#define DMACHAN_TIM3_CH3 DMACHAN_SETTING(STM32L4_DMA1_CHAN2, 5)
#define DMACHAN_TIM3_CH4 DMACHAN_SETTING(STM32L4_DMA1_CHAN3, 5)
#define DMACHAN_TIM3_TRIG DMACHAN_SETTING(STM32L4_DMA1_CHAN6, 5)
#define DMACHAN_TIM3_UP DMACHAN_SETTING(STM32L4_DMA1_CHAN3, 5)
#define DMACHAN_TIM4_CH1 DMACHAN_SETTING(STM32L4_DMA1_CHAN1, 6)
#define DMACHAN_TIM4_CH2 DMACHAN_SETTING(STM32L4_DMA1_CHAN4, 6)
#define DMACHAN_TIM4_CH3 DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 6)
#define DMACHAN_TIM4_UP DMACHAN_SETTING(STM32L4_DMA1_CHAN7, 6)
#define DMACHAN_TIM5_CH1 DMACHAN_SETTING(STM32L4_DMA2_CHAN5, 5)
#define DMACHAN_TIM5_CH2 DMACHAN_SETTING(STM32L4_DMA2_CHAN4, 5)
#define DMACHAN_TIM5_CH3 DMACHAN_SETTING(STM32L4_DMA2_CHAN2, 5)
#define DMACHAN_TIM5_CH4 DMACHAN_SETTING(STM32L4_DMA2_CHAN1, 5)
#define DMACHAN_TIM5_COM DMACHAN_SETTING(STM32L4_DMA2_CHAN1, 5)
#define DMACHAN_TIM5_TRIG DMACHAN_SETTING(STM32L4_DMA2_CHAN1, 5)
#define DMACHAN_TIM5_UP DMACHAN_SETTING(STM32L4_DMA2_CHAN2, 5)
#define DMACHAN_TIM6_UP_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN3, 6)
#define DMACHAN_TIM6_UP_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN4, 3)
#define DMACHAN_TIM7_UP_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN4, 5)
#define DMACHAN_TIM7_UP_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN5, 3)
#define DMACHAN_TIM8_CH1 DMACHAN_SETTING(STM32L4_DMA2_CHAN6, 7)
#define DMACHAN_TIM8_CH2 DMACHAN_SETTING(STM32L4_DMA2_CHAN7, 7)
#define DMACHAN_TIM8_CH3 DMACHAN_SETTING(STM32L4_DMA2_CHAN1, 7)
#define DMACHAN_TIM8_CH4 DMACHAN_SETTING(STM32L4_DMA2_CHAN2, 7)
#define DMACHAN_TIM8_COM DMACHAN_SETTING(STM32L4_DMA2_CHAN2, 7)
#define DMACHAN_TIM8_TRIG DMACHAN_SETTING(STM32L4_DMA2_CHAN2, 7)
#define DMACHAN_TIM8_UP DMACHAN_SETTING(STM32L4_DMA2_CHAN1, 7)
#define DMACHAN_TIM15_CH1 DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 7)
#define DMACHAN_TIM15_COM DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 7)
#define DMACHAN_TIM15_TRIG DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 7)
#define DMACHAN_TIM15_UP DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 7)
#define DMACHAN_TIM16_CH1_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN3, 4)
#define DMACHAN_TIM16_CH1_2 DMACHAN_SETTING(STM32L4_DMA1_CHAN6, 4)
#define DMACHAN_TIM16_UP_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN3, 4)
#define DMACHAN_TIM16_UP_2 DMACHAN_SETTING(STM32L4_DMA1_CHAN6, 4)
#define DMACHAN_TIM17_CH1_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN1, 5)
#define DMACHAN_TIM17_CH1_2 DMACHAN_SETTING(STM32L4_DMA1_CHAN7, 5)
#define DMACHAN_TIM17_UP_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN1, 5)
#define DMACHAN_TIM17_UP_2 DMACHAN_SETTING(STM32L4_DMA1_CHAN7, 5)
/* UART */
#define DMACHAN_USART1_RX_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 2)
#define DMACHAN_USART1_RX_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN7, 2)
#define DMACHAN_USART1_TX_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN4, 2)
#define DMACHAN_USART1_TX_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN6, 2)
#define DMACHAN_USART2_RX DMACHAN_SETTING(STM32L4_DMA1_CHAN6, 2)
#define DMACHAN_USART2_TX DMACHAN_SETTING(STM32L4_DMA1_CHAN7, 2)
#define DMACHAN_USART3_RX DMACHAN_SETTING(STM32L4_DMA1_CHAN3, 2)
#define DMACHAN_USART3_TX DMACHAN_SETTING(STM32L4_DMA1_CHAN2, 2)
#define DMACHAN_UART5_RX DMACHAN_SETTING(STM32L4_DMA2_CHAN2, 2)
#define DMACHAN_UART5_TX DMACHAN_SETTING(STM32L4_DMA2_CHAN1, 2)
#define DMACHAN_UART4_RX DMACHAN_SETTING(STM32L4_DMA2_CHAN5, 2)
#define DMACHAN_UART4_TX DMACHAN_SETTING(STM32L4_DMA2_CHAN3, 2)
#define DMACHAN_LPUART_RX DMACHAN_SETTING(STM32L4_DMA2_CHAN7, 4)
#define DMACHAN_LPUART_TX DMACHAN_SETTING(STM32L4_DMA2_CHAN6, 4)
#endif /* __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4X5XX_DMA_H */

112
arch/arm/src/stm32l4/chip/stm32l4x5xx_firewall.h Normal file
View file

@ -0,0 +1,112 @@
/************************************************************************************
* arch/arm/src/stm32l4/chip/stm32l4x5xx_firewall.h
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
* Copyright (C) 2016 Sebastien Lorquet. All rights reserved.
* Author: Sebastien Lorquet <sebastien@lorquet.fr>
* Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4X5XX_FIREWALL_H
#define __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4X5XX_FIREWALL_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
#include <sys/types.h>
#include "chip.h"
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* Register Offsets *****************************************************************/
#define STM32L4_FIREWALL_CSSA_OFFSET 0x0000
#define STM32L4_FIREWALL_CSL_OFFSET 0x0004
#define STM32L4_FIREWALL_NVDSSA_OFFSET 0x0008
#define STM32L4_FIREWALL_NVDSL_OFFSET 0x000C
#define STM32L4_FIREWALL_VDSSA_OFFSET 0x0010
#define STM32L4_FIREWALL_VDSL_OFFSET 0x0014
#define STM32L4_FIREWALL_CR_OFFSET 0x0020
/* Register Addresses ***************************************************************/
#define STM32L4_FIREWALL_CSSA (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_CSSA_OFFSET)
#define STM32L4_FIREWALL_CSL (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_CSL_OFFSET)
#define STM32L4_FIREWALL_NVDSSA (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_NVDSSA_OFFSET)
#define STM32L4_FIREWALL_NVDSL (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_NVDSL_OFFSET)
#define STM32L4_FIREWALL_VDSSA (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_VDSSA_OFFSET)
#define STM32L4_FIREWALL_VDSL (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_VDSL_OFFSET)
#define STM32L4_FIREWALL_CR (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_CR_OFFSET)
/* Register Bitfield Definitions ****************************************************/
/* Code Segment Start Address */
#define FIREWALL_CSSADD_SHIFT 8
#define FIREWALL_CSSADD_MASK (0xffff << FIREWALL_CSSADD_SHIFT)
/* Code Segment Length */
#define FIREWALL_CSSLENG_SHIFT 8
#define FIREWALL_CSSLENG_MASK (0x3fff << FIREWALL_CSSLENG_SHIFT)
/* Non-volatile Data Segment Start Address */
#define FIREWALL_NVDSADD_SHIFT 8
#define FIREWALL_NVDSADD_MASK (0xffff << FIREWALL_NVDSADD_SHIFT)
/* Non-volatile Data Segment Length */
#define FIREWALL_NVDSLENG_SHIFT 8
#define FIREWALL_NVDSLENG_MASK (0x3fff << FIREWALL_NVDSLENG_SHIFT)
/* Volatile Data Segment Start Address */
#define FIREWALL_VDSADD_SHIFT 6
#define FIREWALL_VDSADD_MASK (0x07ff << FIREWALL_VDSADD_SHIFT)
/* Volatile Data Segment Length */
#define FIREWALL_VDSLENG_SHIFT 6
#define FIREWALL_VDSLENG_MASK (0x07ff << FIREWALL_VDSLENG_SHIFT)
/* Configuration Register */
#define FIREWALL_CR_FPA (1 << 0) /* Bit 0: Firewall prearm */
#define FIREWALL_CR_VDS (1 << 1) /* Bit 1: Volatile data shared */
#define FIREWALL_CR_VDE (1 << 2) /* Bit 2: Volatile data execution */
#endif /* __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4X5XX_FIREWALL_H */

947
arch/arm/src/stm32l4/chip/stm32l4x5xx_otgfs.h Normal file
View file

@ -0,0 +1,947 @@
/****************************************************************************************************
* arch/arm/src/stm32l4/chip/stm32l4x5xx_otgfs.h
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
* Copyright (C) 2016 Omni Hoverboards Inc. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
* Paul Alexander Patience <paul-a.patience@polymtl.ca>
* dev@ziggurat29.com
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4X5XX_OTGFS_H
#define __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4X5XX_OTGFS_H
/****************************************************************************************************
* Included Files
****************************************************************************************************/
/****************************************************************************************************
* Pre-processor Definitions
****************************************************************************************************/
/* General definitions */
#define OTGFS_EPTYPE_CTRL (0) /* Control */
#define OTGFS_EPTYPE_ISOC (1) /* Isochronous */
#define OTGFS_EPTYPE_BULK (2) /* Bulk */
#define OTGFS_EPTYPE_INTR (3) /* Interrupt */
#define OTGFS_PID_DATA0 (0)
#define OTGFS_PID_DATA2 (1)
#define OTGFS_PID_DATA1 (2)
#define OTGFS_PID_MDATA (3) /* Non-control */
#define OTGFS_PID_SETUP (3) /* Control */
/* Register Offsets *********************************************************************************/
/* Core global control and status registers */
#define STM32L4_OTGFS_GOTGCTL_OFFSET 0x0000 /* Control and status register */
#define STM32L4_OTGFS_GOTGINT_OFFSET 0x0004 /* Interrupt register */
#define STM32L4_OTGFS_GAHBCFG_OFFSET 0x0008 /* AHB configuration register */
#define STM32L4_OTGFS_GUSBCFG_OFFSET 0x000c /* USB configuration register */
#define STM32L4_OTGFS_GRSTCTL_OFFSET 0x0010 /* Reset register */
#define STM32L4_OTGFS_GINTSTS_OFFSET 0x0014 /* Core interrupt register */
#define STM32L4_OTGFS_GINTMSK_OFFSET 0x0018 /* Interrupt mask register */
#define STM32L4_OTGFS_GRXSTSR_OFFSET 0x001c /* Receive status debug read/OTG status read register */
#define STM32L4_OTGFS_GRXSTSP_OFFSET 0x0020 /* Receive status debug read/OTG status pop register */
#define STM32L4_OTGFS_GRXFSIZ_OFFSET 0x0024 /* Receive FIFO size register */
#define STM32L4_OTGFS_HNPTXFSIZ_OFFSET 0x0028 /* Host non-periodic transmit FIFO size register */
#define STM32L4_OTGFS_DIEPTXF0_OFFSET 0x0028 /* Endpoint 0 Transmit FIFO size */
#define STM32L4_OTGFS_HNPTXSTS_OFFSET 0x002c /* Non-periodic transmit FIFO/queue status register */
#define STM32L4_OTGFS_GCCFG_OFFSET 0x0038 /* General core configuration register */
#define STM32L4_OTGFS_CID_OFFSET 0x003c /* Core ID register */
#define STM32L4_OTGFS_GLPMCFG_OFFSET 0x0054 /* LPM configuration register */
#define STM32L4_OTGFS_GPWRDN_OFFSET 0x0058 /* Power down register */
#define STM32L4_OTGFS_GADPCTL_OFSSET 0x005c /* ADP timer, control and status register */
#define STM32L4_OTGFS_HPTXFSIZ_OFFSET 0x0100 /* Host periodic transmit FIFO size register */
#define STM32L4_OTGFS_DIEPTXF_OFFSET(n) (104+(((n)-1) << 2))
/* Host-mode control and status registers */
#define STM32L4_OTGFS_HCFG_OFFSET 0x0400 /* Host configuration register */
#define STM32L4_OTGFS_HFIR_OFFSET 0x0404 /* Host frame interval register */
#define STM32L4_OTGFS_HFNUM_OFFSET 0x0408 /* Host frame number/frame time remaining register */
#define STM32L4_OTGFS_HPTXSTS_OFFSET 0x0410 /* Host periodic transmit FIFO/queue status register */
#define STM32L4_OTGFS_HAINT_OFFSET 0x0414 /* Host all channels interrupt register */
#define STM32L4_OTGFS_HAINTMSK_OFFSET 0x0418 /* Host all channels interrupt mask register */
#define STM32L4_OTGFS_HPRT_OFFSET 0x0440 /* Host port control and status register */
#define STM32L4_OTGFS_CHAN_OFFSET(n) (0x500 + ((n) << 5)
#define STM32L4_OTGFS_HCCHAR_CHOFFSET 0x0000 /* Host channel characteristics register */
#define STM32L4_OTGFS_HCINT_CHOFFSET 0x0008 /* Host channel interrupt register */
#define STM32L4_OTGFS_HCINTMSK_CHOFFSET 0x000c /* Host channel interrupt mask register */
#define STM32L4_OTGFS_HCTSIZ_CHOFFSET 0x0010 /* Host channel interrupt register */
#define STM32L4_OTGFS_HCCHAR_OFFSET(n) (0x500 + ((n) << 5))
#define STM32L4_OTGFS_HCINT_OFFSET(n) (0x508 + ((n) << 5))
#define STM32L4_OTGFS_HCINTMSK_OFFSET(n) (0x50c + ((n) << 5))
#define STM32L4_OTGFS_HCTSIZ_OFFSET(n) (0x510 + ((n) << 5))
/* Device-mode control and status registers */
#define STM32L4_OTGFS_DCFG_OFFSET 0x0800 /* Device configuration register */
#define STM32L4_OTGFS_DCTL_OFFSET 0x0804 /* Device control register */
#define STM32L4_OTGFS_DSTS_OFFSET 0x0808 /* Device status register */
#define STM32L4_OTGFS_DIEPMSK_OFFSET 0x0810 /* Device IN endpoint common interrupt mask register */
#define STM32L4_OTGFS_DOEPMSK_OFFSET 0x0814 /* Device OUT endpoint common interrupt mask register */
#define STM32L4_OTGFS_DAINT_OFFSET 0x0818 /* Device all endpoints interrupt register */
#define STM32L4_OTGFS_DAINTMSK_OFFSET 0x081c /* All endpoints interrupt mask register */
#define STM32L4_OTGFS_DVBUSDIS_OFFSET 0x0828 /* Device VBUS discharge time register */
#define STM32L4_OTGFS_DVBUSPULSE_OFFSET 0x082c /* Device VBUS pulsing time register */
#define STM32L4_OTGFS_DIEPEMPMSK_OFFSET 0x0834 /* Device IN endpoint FIFO empty interrupt mask register */
#define STM32L4_OTGFS_DIEP_OFFSET(n) (0x0900 + ((n) << 5))
#define STM32L4_OTGFS_DIEPCTL_EPOFFSET 0x0000 /* Device endpoint control register */
#define STM32L4_OTGFS_DIEPINT_EPOFFSET 0x0008 /* Device endpoint interrupt register */
#define STM32L4_OTGFS_DIEPTSIZ_EPOFFSET 0x0010 /* Device IN endpoint transfer size register */
#define STM32L4_OTGFS_DTXFSTS_EPOFFSET 0x0018 /* Device IN endpoint transmit FIFO status register */
#define STM32L4_OTGFS_DIEPCTL_OFFSET(n) (0x0900 + ((n) << 5))
#define STM32L4_OTGFS_DIEPINT_OFFSET(n) (0x0908 + ((n) << 5))
#define STM32L4_OTGFS_DIEPTSIZ_OFFSET(n) (0x910 + ((n) << 5))
#define STM32L4_OTGFS_DTXFSTS_OFFSET(n) (0x0918 + ((n) << 5))
#define STM32L4_OTGFS_DOEP_OFFSET(n) (0x0b00 + ((n) << 5))
#define STM32L4_OTGFS_DOEPCTL_EPOFFSET 0x0000 /* Device control OUT endpoint 0 control register */
#define STM32L4_OTGFS_DOEPINT_EPOFFSET 0x0008 /* Device endpoint-x interrupt register */
#define STM32L4_OTGFS_DOEPTSIZ_EPOFFSET 0x0010 /* Device endpoint OUT transfer size register */
#define STM32L4_OTGFS_DOEPCTL_OFFSET(n) (0x0b00 + ((n) << 5))
#define STM32L4_OTGFS_DOEPINT_OFFSET(n) (0x0b08 + ((n) << 5))
#define STM32L4_OTGFS_DOEPTSIZ_OFFSET(n) (0x0b10 + ((n) << 5))
/* Power and clock gating registers */
#define STM32L4_OTGFS_PCGCCTL_OFFSET 0x0e00 /* Power and clock gating control register */
/* Data FIFO (DFIFO) access registers */
#define STM32L4_OTGFS_DFIFO_DEP_OFFSET(n) (0x1000 + ((n) << 12))
#define STM32L4_OTGFS_DFIFO_HCH_OFFSET(n) (0x1000 + ((n) << 12))
/* Register Addresses *******************************************************************************/
#define STM32L4_OTGFS_GOTGCTL (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GOTGCTL_OFFSET)
#define STM32L4_OTGFS_GOTGINT (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GOTGINT_OFFSET)
#define STM32L4_OTGFS_GAHBCFG (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GAHBCFG_OFFSET)
#define STM32L4_OTGFS_GUSBCFG (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GUSBCFG_OFFSET)
#define STM32L4_OTGFS_GRSTCTL (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GRSTCTL_OFFSET)
#define STM32L4_OTGFS_GINTSTS (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GINTSTS_OFFSET)
#define STM32L4_OTGFS_GINTMSK (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GINTMSK_OFFSET)
#define STM32L4_OTGFS_GRXSTSR (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GRXSTSR_OFFSET)
#define STM32L4_OTGFS_GRXSTSP (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GRXSTSP_OFFSET)
#define STM32L4_OTGFS_GRXFSIZ (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GRXFSIZ_OFFSET)
#define STM32L4_OTGFS_HNPTXFSIZ (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HNPTXFSIZ_OFFSET)
#define STM32L4_OTGFS_DIEPTXF0 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DIEPTXF0_OFFSET)
#define STM32L4_OTGFS_HNPTXSTS (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HNPTXSTS_OFFSET)
#define STM32L4_OTGFS_GCCFG (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GCCFG_OFFSET)
#define STM32L4_OTGFS_CID (STM32L4_OTGFS_BASE+STM32L4_OTGFS_CID_OFFSET)
#define STM32L4_OTGFS_GLPMCFG (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GLPMCFG_OFFSET)
#define STM32L4_OTGFS_GPWRDN (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GPWRDN_OFFSET)
#define STM32L4_OTGFS_GADPCTL (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GADPCTL_OFSSET)
#define STM32L4_OTGFS_HPTXFSIZ (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HPTXFSIZ_OFFSET)
#define STM32L4_OTGFS_DIEPTXF(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DIEPTXF_OFFSET(n))
/* Host-mode control and status registers */
#define STM32L4_OTGFS_HCFG (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HCFG_OFFSET)
#define STM32L4_OTGFS_HFIR (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HFIR_OFFSET)
#define STM32L4_OTGFS_HFNUM (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HFNUM_OFFSET)
#define STM32L4_OTGFS_HPTXSTS (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HPTXSTS_OFFSET)
#define STM32L4_OTGFS_HAINT (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HAINT_OFFSET)
#define STM32L4_OTGFS_HAINTMSK (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HAINTMSK_OFFSET)
#define STM32L4_OTGFS_HPRT (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HPRT_OFFSET)
#define STM32L4_OTGFS_CHAN(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_CHAN_OFFSET(n))
#define STM32L4_OTGFS_HCCHAR(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HCCHAR_OFFSET(n))
#define STM32L4_OTGFS_HCINT(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HCINT_OFFSET(n))
#define STM32L4_OTGFS_HCINTMSK(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HCINTMSK_OFFSET(n))
#define STM32L4_OTGFS_HCTSIZ(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HCTSIZ_OFFSET(n))
/* Device-mode control and status registers */
#define STM32L4_OTGFS_DCFG (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DCFG_OFFSET)
#define STM32L4_OTGFS_DCTL (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DCTL_OFFSET)
#define STM32L4_OTGFS_DSTS (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DSTS_OFFSET)
#define STM32L4_OTGFS_DIEPMSK (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DIEPMSK_OFFSET)
#define STM32L4_OTGFS_DOEPMSK (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DOEPMSK_OFFSET)
#define STM32L4_OTGFS_DAINT (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DAINT_OFFSET)
#define STM32L4_OTGFS_DAINTMSK (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DAINTMSK_OFFSET)
#define STM32L4_OTGFS_DVBUSDIS (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DVBUSDIS_OFFSET)
#define STM32L4_OTGFS_DVBUSPULSE (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DVBUSPULSE_OFFSET)
#define STM32L4_OTGFS_DIEPEMPMSK (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DIEPEMPMSK_OFFSET)
#define STM32L4_OTGFS_DIEP(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DIEP_OFFSET(n))
#define STM32L4_OTGFS_DIEPCTL(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DIEPCTL_OFFSET(n))
#define STM32L4_OTGFS_DIEPINT(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DIEPINT_OFFSET(n))
#define STM32L4_OTGFS_DIEPTSIZ(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DIEPTSIZ_OFFSET(n))
#define STM32L4_OTGFS_DTXFSTS(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DTXFSTS_OFFSET(n))
#define STM32L4_OTGFS_DOEP(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DOEP_OFFSET(n))
#define STM32L4_OTGFS_DOEPCTL(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DOEPCTL_OFFSET(n))
#define STM32L4_OTGFS_DOEPINT(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DOEPINT_OFFSET(n))
#define STM32L4_OTGFS_DOEPTSIZ(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DOEPTSIZ_OFFSET(n))
/* Power and clock gating registers */
#define STM32L4_OTGFS_PCGCCTL (STM32L4_OTGFS_BASE+STM32L4_OTGFS_PCGCCTL_OFFSET)
/* Data FIFO (DFIFO) access registers */
#define STM32L4_OTGFS_DFIFO_DEP(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DFIFO_DEP_OFFSET(n))
#define STM32L4_OTGFS_DFIFO_HCH(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DFIFO_HCH_OFFSET(n))
/* Register Bitfield Definitions ********************************************************************/
/* Core global control and status registers */
/* Control and status register */
#define OTGFS_GOTGCTL_SRQSCS (1 << 0) /* Bit 0: Session request success */
#define OTGFS_GOTGCTL_SRQ (1 << 1) /* Bit 1: Session request */
/* Bits 2-7: Reserved */
#define OTGFS_GOTGCTL_HNGSCS (1 << 8) /* Bit 8: Host negotiation success */
#define OTGFS_GOTGCTL_HNPRQ (1 << 9) /* Bit 9: HNP request */
#define OTGFS_GOTGCTL_HSHNPEN (1 << 10) /* Bit 10: host set HNP enable */
#define OTGFS_GOTGCTL_DHNPEN (1 << 11) /* Bit 11: Device HNP enabled */
#define OTGFS_GOTGCTL_EHEN (1 << 12) /* Bit 12: Embedded host enable */
/* Bits 13-15: Reserved, must be kept at reset value */
#define OTGFS_GOTGCTL_CIDSTS (1 << 16) /* Bit 16: Connector ID status */
#define OTGFS_GOTGCTL_DBCT (1 << 17) /* Bit 17: Long/short debounce time */
#define OTGFS_GOTGCTL_ASVLD (1 << 18) /* Bit 18: A-session valid */
#define OTGFS_GOTGCTL_BSVLD (1 << 19) /* Bit 19: B-session valid */
#define OTGFS_GOTGCTL_OTGVER (1 << 20) /* Bit 20: OTG version */
/* Bits 21-31: Reserved, must be kept at reset value */
/* Interrupt register */
/* Bits 1:0 Reserved, must be kept at reset value */
#define OTGFS_GOTGINT_SEDET (1 << 2) /* Bit 2: Session end detected */
/* Bits 3-7: Reserved, must be kept at reset value */
#define OTGFS_GOTGINT_SRSSCHG (1 << 8) /* Bit 8: Session request success status change */
#define OTGFS_GOTGINT_HNSSCHG (1 << 9) /* Bit 9: Host negotiation success status change */
/* Bits 16:10 Reserved, must be kept at reset value */
#define OTGFS_GOTGINT_HNGDET (1 << 17) /* Bit 17: Host negotiation detected */
#define OTGFS_GOTGINT_ADTOCHG (1 << 18) /* Bit 18: A-device timeout change */
#define OTGFS_GOTGINT_DBCDNE (1 << 19) /* Bit 19: Debounce done */
#define OTGFS_GOTGINT_IDCHNG (1 << 20) /* Bit 20: Change in ID pin input value */
/* Bits 21-31: Reserved, must be kept at reset value */
/* AHB configuration register */
#define OTGFS_GAHBCFG_GINTMSK (1 << 0) /* Bit 0: Global interrupt mask */
/* Bits 1-6: Reserved, must be kept at reset value */
#define OTGFS_GAHBCFG_TXFELVL (1 << 7) /* Bit 7: TxFIFO empty level */
#define OTGFS_GAHBCFG_PTXFELVL (1 << 8) /* Bit 8: Periodic TxFIFO empty level */
/* Bits 20-31: Reserved, must be kept at reset value */
/* USB configuration register */
#define OTGFS_GUSBCFG_TOCAL_SHIFT (0) /* Bits 0-2: FS timeout calibration */
#define OTGFS_GUSBCFG_TOCAL_MASK (7 << OTGFS_GUSBCFG_TOCAL_SHIFT)
/* Bits 3-5: Reserved, must be kept at reset value */
#define OTGFS_GUSBCFG_PHYSEL (1 << 6) /* Bit 6: Full Speed serial transceiver select */
/* Bit 7: Reserved, must be kept at reset value */
#define OTGFS_GUSBCFG_SRPCAP (1 << 8) /* Bit 8: SRP-capable */
#define OTGFS_GUSBCFG_HNPCAP (1 << 9) /* Bit 9: HNP-capable */
#define OTGFS_GUSBCFG_TRDT_SHIFT (10) /* Bits 10-13: USB turnaround time */
#define OTGFS_GUSBCFG_TRDT_MASK (15 << OTGFS_GUSBCFG_TRDT_SHIFT)
# define OTGFS_GUSBCFG_TRDT(n) ((n) << OTGFS_GUSBCFG_TRDT_SHIFT)
/* Bits 14-28: Reserved, must be kept at reset value */
#define OTGFS_GUSBCFG_FHMOD (1 << 29) /* Bit 29: Force host mode */
#define OTGFS_GUSBCFG_FDMOD (1 << 30) /* Bit 30: Force device mode */
/* Bit 31: Reserved, must be kept at reset value */
/* Reset register */
#define OTGFS_GRSTCTL_CSRST (1 << 0) /* Bit 0: Core soft reset */
/* Bit 1 Reserved, must be kept at reset value */
#define OTGFS_GRSTCTL_FCRST (1 << 2) /* Bit 2: Host frame counter reset */
/* Bit 3 Reserved, must be kept at reset value */
#define OTGFS_GRSTCTL_RXFFLSH (1 << 4) /* Bit 4: RxFIFO flush */
#define OTGFS_GRSTCTL_TXFFLSH (1 << 5) /* Bit 5: TxFIFO flush */
#define OTGFS_GRSTCTL_TXFNUM_SHIFT (6) /* Bits 6-10: TxFIFO number */
#define OTGFS_GRSTCTL_TXFNUM_MASK (31 << OTGFS_GRSTCTL_TXFNUM_SHIFT)
# define OTGFS_GRSTCTL_TXFNUM_HNONPER (0 << OTGFS_GRSTCTL_TXFNUM_SHIFT) /* Non-periodic TxFIFO flush in host mode */
# define OTGFS_GRSTCTL_TXFNUM_HPER (1 << OTGFS_GRSTCTL_TXFNUM_SHIFT) /* Periodic TxFIFO flush in host mode */
# define OTGFS_GRSTCTL_TXFNUM_HALL (16 << OTGFS_GRSTCTL_TXFNUM_SHIFT) /* Flush all the transmit FIFOs in host mode.*/
# define OTGFS_GRSTCTL_TXFNUM_D(n) ((n) << OTGFS_GRSTCTL_TXFNUM_SHIFT) /* TXFIFO n flush in device mode, n=0-15 */
# define OTGFS_GRSTCTL_TXFNUM_DALL (16 << OTGFS_GRSTCTL_TXFNUM_SHIFT) /* Flush all the transmit FIFOs in device mode.*/
/* Bits 11-30: Reserved, must be kept at reset value */
#define OTGFS_GRSTCTL_AHBIDL (1 << 31) /* Bit 31: AHB master idle */
/* Core interrupt and Interrupt mask registers */
#define OTGFS_GINTSTS_CMOD (1 << 0) /* Bit 0: Current mode of operation */
# define OTGFS_GINTSTS_DEVMODE (0)
# define OTGFS_GINTSTS_HOSTMODE (OTGFS_GINTSTS_CMOD)
#define OTGFS_GINT_MMIS (1 << 1) /* Bit 1: Mode mismatch interrupt */
#define OTGFS_GINT_OTG (1 << 2) /* Bit 2: OTG interrupt */
#define OTGFS_GINT_SOF (1 << 3) /* Bit 3: Start of frame */
#define OTGFS_GINT_RXFLVL (1 << 4) /* Bit 4: RxFIFO non-empty */
#define OTGFS_GINT_NPTXFE (1 << 5) /* Bit 5: Non-periodic TxFIFO empty */
#define OTGFS_GINT_GINAKEFF (1 << 6) /* Bit 6: Global IN non-periodic NAK effective */
#define OTGFS_GINT_GONAKEFF (1 << 7) /* Bit 7: Global OUT NAK effective */
#define OTGFS_GINT_RES89 (3 << 8) /* Bits 8-9: Reserved, must be kept at reset value */
#define OTGFS_GINT_ESUSP (1 << 10) /* Bit 10: Early suspend */
#define OTGFS_GINT_USBSUSP (1 << 11) /* Bit 11: USB suspend */
#define OTGFS_GINT_USBRST (1 << 12) /* Bit 12: USB reset */
#define OTGFS_GINT_ENUMDNE (1 << 13) /* Bit 13: Enumeration done */
#define OTGFS_GINT_ISOODRP (1 << 14) /* Bit 14: Isochronous OUT packet dropped interrupt */
#define OTGFS_GINT_EOPF (1 << 15) /* Bit 15: End of periodic frame interrupt */
#define OTGFS_GINT_RES1617 (3 << 16) /* Bits 16-17: Reserved, must be kept at reset value */
#define OTGFS_GINT_IEP (1 << 18) /* Bit 18: IN endpoint interrupt */
#define OTGFS_GINT_OEP (1 << 19) /* Bit 19: OUT endpoint interrupt */
#define OTGFS_GINT_IISOIXFR (1 << 20) /* Bit 20: Incomplete isochronous IN transfer */
#define OTGFS_GINT_IISOOXFR (1 << 21) /* Bit 21: Incomplete isochronous OUT transfer (device) */
#define OTGFS_GINT_IPXFR (1 << 21) /* Bit 21: Incomplete periodic transfer (host) */
#define OTGFS_GINT_RES22 (1 << 22) /* Bit 22: Reserved, must be kept at reset value */
#define OTGFS_GINT_RSTDET (1 << 23) /* Bit 23: Reset detected interrupt */
#define OTGFS_GINT_HPRT (1 << 24) /* Bit 24: Host port interrupt */
#define OTGFS_GINT_HC (1 << 25) /* Bit 25: Host channels interrupt */
#define OTGFS_GINT_PTXFE (1 << 26) /* Bit 26: Periodic TxFIFO empty */
#define OTGFS_GINT_LPMINT (1 << 27) /* Bit 27: LPM interrupt */
#define OTGFS_GINT_CIDSCHG (1 << 28) /* Bit 28: Connector ID status change */
#define OTGFS_GINT_DISC (1 << 29) /* Bit 29: Disconnect detected interrupt */
#define OTGFS_GINT_SRQ (1 << 30) /* Bit 30: Session request/new session detected interrupt */
#define OTGFS_GINT_WKUP (1 << 31) /* Bit 31: Resume/remote wakeup detected interrupt */
/* Receive status debug read/OTG status read and pop registers (host mode) */
#define OTGFS_GRXSTSH_CHNUM_SHIFT (0) /* Bits 0-3: Channel number */
#define OTGFS_GRXSTSH_CHNUM_MASK (15 << OTGFS_GRXSTSH_CHNUM_SHIFT)
#define OTGFS_GRXSTSH_BCNT_SHIFT (4) /* Bits 4-14: Byte count */
#define OTGFS_GRXSTSH_BCNT_MASK (0x7ff << OTGFS_GRXSTSH_BCNT_SHIFT)
#define OTGFS_GRXSTSH_DPID_SHIFT (15) /* Bits 15-16: Data PID */
#define OTGFS_GRXSTSH_DPID_MASK (3 << OTGFS_GRXSTSH_DPID_SHIFT)
# define OTGFS_GRXSTSH_DPID_DATA0 (0 << OTGFS_GRXSTSH_DPID_SHIFT)
# define OTGFS_GRXSTSH_DPID_DATA2 (1 << OTGFS_GRXSTSH_DPID_SHIFT)
# define OTGFS_GRXSTSH_DPID_DATA1 (2 << OTGFS_GRXSTSH_DPID_SHIFT)
# define OTGFS_GRXSTSH_DPID_MDATA (3 << OTGFS_GRXSTSH_DPID_SHIFT)
#define OTGFS_GRXSTSH_PKTSTS_SHIFT (17) /* Bits 17-20: Packet status */
#define OTGFS_GRXSTSH_PKTSTS_MASK (15 << OTGFS_GRXSTSH_PKTSTS_SHIFT)
# define OTGFS_GRXSTSH_PKTSTS_INRECVD (2 << OTGFS_GRXSTSH_PKTSTS_SHIFT) /* IN data packet received */
# define OTGFS_GRXSTSH_PKTSTS_INDONE (3 << OTGFS_GRXSTSH_PKTSTS_SHIFT) /* IN transfer completed */
# define OTGFS_GRXSTSH_PKTSTS_DTOGERR (5 << OTGFS_GRXSTSH_PKTSTS_SHIFT) /* Data toggle error */
# define OTGFS_GRXSTSH_PKTSTS_HALTED (7 << OTGFS_GRXSTSH_PKTSTS_SHIFT) /* Channel halted */
/* Bits 21-31: Reserved, must be kept at reset value */
/* Receive status debug read/OTG status read and pop registers (device mode) */
#define OTGFS_GRXSTSD_EPNUM_SHIFT (0) /* Bits 0-3: Endpoint number */
#define OTGFS_GRXSTSD_EPNUM_MASK (15 << OTGFS_GRXSTSD_EPNUM_SHIFT)
#define OTGFS_GRXSTSD_BCNT_SHIFT (4) /* Bits 4-14: Byte count */
#define OTGFS_GRXSTSD_BCNT_MASK (0x7ff << OTGFS_GRXSTSD_BCNT_SHIFT)
#define OTGFS_GRXSTSD_DPID_SHIFT (15) /* Bits 15-16: Data PID */
#define OTGFS_GRXSTSD_DPID_MASK (3 << OTGFS_GRXSTSD_DPID_SHIFT)
# define OTGFS_GRXSTSD_DPID_DATA0 (0 << OTGFS_GRXSTSD_DPID_SHIFT)
# define OTGFS_GRXSTSD_DPID_DATA2 (1 << OTGFS_GRXSTSD_DPID_SHIFT)
# define OTGFS_GRXSTSD_DPID_DATA1 (2 << OTGFS_GRXSTSD_DPID_SHIFT)
# define OTGFS_GRXSTSD_DPID_MDATA (3 << OTGFS_GRXSTSD_DPID_SHIFT)
#define OTGFS_GRXSTSD_PKTSTS_SHIFT (17) /* Bits 17-20: Packet status */
#define OTGFS_GRXSTSD_PKTSTS_MASK (15 << OTGFS_GRXSTSD_PKTSTS_SHIFT)
# define OTGFS_GRXSTSD_PKTSTS_OUTNAK (1 << OTGFS_GRXSTSD_PKTSTS_SHIFT) /* Global OUT NAK */
# define OTGFS_GRXSTSD_PKTSTS_OUTRECVD (2 << OTGFS_GRXSTSD_PKTSTS_SHIFT) /* OUT data packet received */
# define OTGFS_GRXSTSD_PKTSTS_OUTDONE (3 << OTGFS_GRXSTSD_PKTSTS_SHIFT) /* OUT transfer completed */
# define OTGFS_GRXSTSD_PKTSTS_SETUPDONE (4 << OTGFS_GRXSTSD_PKTSTS_SHIFT) /* SETUP transaction completed */
# define OTGFS_GRXSTSD_PKTSTS_SETUPRECVD (6 << OTGFS_GRXSTSD_PKTSTS_SHIFT) /* SETUP data packet received */
#define OTGFS_GRXSTSD_FRMNUM_SHIFT (21) /* Bits 21-24: Frame number */
#define OTGFS_GRXSTSD_FRMNUM_MASK (15 << OTGFS_GRXSTSD_FRMNUM_SHIFT)
/* Bits 25-31: Reserved, must be kept at reset value */
/* Receive FIFO size register */
#define OTGFS_GRXFSIZ_MASK (0xffff)
/* Host non-periodic transmit FIFO size register */
#define OTGFS_HNPTXFSIZ_NPTXFSA_SHIFT (0) /* Bits 0-15: Non-periodic transmit RAM start address */
#define OTGFS_HNPTXFSIZ_NPTXFSA_MASK (0xffff << OTGFS_HNPTXFSIZ_NPTXFSA_SHIFT)
#define OTGFS_HNPTXFSIZ_NPTXFD_SHIFT (16) /* Bits 16-31: Non-periodic TxFIFO depth */
#define OTGFS_HNPTXFSIZ_NPTXFD_MASK (0xffff << OTGFS_HNPTXFSIZ_NPTXFD_SHIFT)
# define OTGFS_HNPTXFSIZ_NPTXFD_MIN (16 << OTGFS_HNPTXFSIZ_NPTXFD_SHIFT)
# define OTGFS_HNPTXFSIZ_NPTXFD_MAX (256 << OTGFS_HNPTXFSIZ_NPTXFD_SHIFT)
/* Endpoint 0 Transmit FIFO size */
#define OTGFS_DIEPTXF0_TX0FD_SHIFT (0) /* Bits 0-15: Endpoint 0 transmit RAM start address */
#define OTGFS_DIEPTXF0_TX0FD_MASK (0xffff << OTGFS_DIEPTXF0_TX0FD_SHIFT)
#define OTGFS_DIEPTXF0_TX0FSA_SHIFT (16) /* Bits 16-31: Endpoint 0 TxFIFO depth */
#define OTGFS_DIEPTXF0_TX0FSA_MASK (0xffff << OTGFS_DIEPTXF0_TX0FSA_SHIFT)
# define OTGFS_DIEPTXF0_TX0FSA_MIN (16 << OTGFS_DIEPTXF0_TX0FSA_SHIFT)
# define OTGFS_DIEPTXF0_TX0FSA_MAX (256 << OTGFS_DIEPTXF0_TX0FSA_SHIFT)
/* Non-periodic transmit FIFO/queue status register */
#define OTGFS_HNPTXSTS_NPTXFSAV_SHIFT (0) /* Bits 0-15: Non-periodic TxFIFO space available */
#define OTGFS_HNPTXSTS_NPTXFSAV_MASK (0xffff << OTGFS_HNPTXSTS_NPTXFSAV_SHIFT)
# define OTGFS_HNPTXSTS_NPTXFSAV_FULL (0 << OTGFS_HNPTXSTS_NPTXFSAV_SHIFT)
#define OTGFS_HNPTXSTS_NPTQXSAV_SHIFT (16) /* Bits 16-23: Non-periodic transmit request queue space available */
#define OTGFS_HNPTXSTS_NPTQXSAV_MASK (0xff << OTGFS_HNPTXSTS_NPTQXSAV_SHIFT)
# define OTGFS_HNPTXSTS_NPTQXSAV_FULL (0 << OTGFS_HNPTXSTS_NPTQXSAV_SHIFT)
#define OTGFS_HNPTXSTS_NPTXQTOP_SHIFT (24) /* Bits 24-30: Top of the non-periodic transmit request queue */
#define OTGFS_HNPTXSTS_NPTXQTOP_MASK (0x7f << OTGFS_HNPTXSTS_NPTXQTOP_SHIFT)
# define OTGFS_HNPTXSTS_TERMINATE (1 << 24) /* Bit 24: Terminate (last entry for selected channel/endpoint) */
# define OTGFS_HNPTXSTS_TYPE_SHIFT (25) /* Bits 25-26: Status */
# define OTGFS_HNPTXSTS_TYPE_MASK (3 << OTGFS_HNPTXSTS_TYPE_SHIFT)
# define OTGFS_HNPTXSTS_TYPE_INOUT (0 << OTGFS_HNPTXSTS_TYPE_SHIFT) /* IN/OUT token */
# define OTGFS_HNPTXSTS_TYPE_ZLP (1 << OTGFS_HNPTXSTS_TYPE_SHIFT) /* Zero-length transmit packet (device IN/host OUT) */
# define OTGFS_HNPTXSTS_TYPE_HALT (3 << OTGFS_HNPTXSTS_TYPE_SHIFT) /* Channel halt command */
# define OTGFS_HNPTXSTS_CHNUM_SHIFT (27) /* Bits 27-30: Channel number */
# define OTGFS_HNPTXSTS_CHNUM_MASK (15 << OTGFS_HNPTXSTS_CHNUM_SHIFT)
# define OTGFS_HNPTXSTS_EPNUM_SHIFT (27) /* Bits 27-30: Endpoint number */
# define OTGFS_HNPTXSTS_EPNUM_MASK (15 << OTGFS_HNPTXSTS_EPNUM_SHIFT)
/* Bit 31 Reserved, must be kept at reset value */
/* General core configuration register */
#define OTGFS_GCCFG_DCDET (1 << 0) /* Bit 0: Data contact detect */
#define OTGFS_GCCFG_PDET (1 << 1) /* Bit 1: Primary detect */
#define OTGFS_GCCFG_SDET (1 << 2) /* Bit 2: Secondary detect */
#define OTGFS_GCCFG_PS2DET (1 << 3) /* Bit 3: DM pull-up detect */
/* Bits 4-15: Reserved, must be kept at reset value */
#define OTGFS_GCCFG_PWRDWN (1 << 16) /* Bit 16: Power down */
#define OTGFS_GCCFG_BCDEN (1 << 18) /* Bit 17: Battery charging detector enable */
#define OTGFS_GCCFG_DCDEN (1 << 18) /* Bit 18: Data contact detection mode enable */
#define OTGFS_GCCFG_PDEN (1 << 19) /* Bit 19: Primary detection mode enable */
#define OTGFS_GCCFG_SDEN (1 << 20) /* Bit 20: Secondary detection mode enable */
#define OTGFS_GCCFG_VBDEN (1 << 21) /* Bit 21: USB VBUS detection enable */
/* Bits 22-31: Reserved, must be kept at reset value */
/* Core ID register (32-bit product ID) */
/* LPM configuration register */
#define OTGFS_GLPMCFG_LPMEN (1 << 0) /* Bit 0: XXX */
#define OTGFS_GLPMCFG_LPMACK (1 << 1) /* Bit 1: XXX */
#define OTGFS_GLPMCFG_BESL_SHIFT (2) /* Bits 2-5: XXX */
#define OTGFS_GLPMCFG_BESL_MASK (15 << OTGFS_GLPMCFG_BESL_SHIFT)
#define OTGFS_GLPMCFG_REMWAKE (1 << 6) /* Bit 6: XXX */
#define OTGFS_GLPMCFG_L1SSEN (1 << 7) /* Bit 7: XXX */
#define OTGFS_GLPMCFG_BESLTHRS_SHIFT (8) /* Bits 8-11: XXX */
#define OTGFS_GLPMCFG_BESLTHRS_MASK (15 << OTGFS_GLPMCFG_BESLTHRS_SHIFT)
#define OTGFS_GLPMCFG_L1DSEN (1 << 12) /* Bit 12: XXX */
#define OTGFS_GLPMCFG_LPMRSP_SHIFT (13) /* Bits 13-14: XXXX */
#define OTGFS_GLPMCFG_LPMRSP_MASK (3 << OTGFS_GLPMCFG_LPMRSP_SHIFT)
#define OTGFS_GLPMCFG_SLPSTS (1 << 15) /* Bit 15: XXX */
#define OTGFS_GLPMCFG_L1RSMOK (1 << 16) /* Bit 16: XXX */
#define OTGFS_GLPMCFG_LPMCHIDX_SHIFT (17) /* Bits 17-20: XXX */
#define OTGFS_GLPMCFG_LPMCHIDX_MASK (15 << OTGFS_GLPMCFG_LPMCHIDX_SHIFT)
#define OTGFS_GLPMCFG_LPMRCNT_SHIFT (21) /* Bits 21-23: XXX */
#define OTGFS_GLPMCFG_LPMRCNT_MASK (7 << OTGFS_GLPMCFG_LPMRCNT_SHIFT)
#define OTGFS_GLPMCFG_SNDLPM (1 << 24) /* Bit 24: XXX */
#define OTGFS_GLPMCFG_LPMRCNTSTS_SHIFT (25) /* Bits 25-27: XXX */
#define OTGFS_GLPMCFG_LPMRCNTSTS_MASK (7 << OTGFS_GLPMCFG_LPMRCNTSTS_SHIFT)
#define OTGFS_GLPMCFG_ENBESL (1 << 28) /* Bit 28: XXX */
/* Bits 29-31: Reserved, must be kept at reset value */
/* Power down register */
#define OTGFS_GPWRDN_ADPMEN (1 << 0) /* Bit 0: XXX */
#define OTGFS_GPWRDN_ADPIF (1 << 23) /* Bit 23: XXX */
/* ADP timer, control and status register */
#define OTGFS_GADPCTL_PRBDSCHG_SHIFT (0) /* Bits 0-1: XXX */
#define OTGFS_GADPCTL_PRBDSCHG_MASK (3 << OTGFS_GADPCTL_PRBDSCHG_SHIFT)
#define OTGFS_GADPCTL_PRBDELTA_SHIFT (2) /* Bits 2-3: XXX */
#define OTGFS_GADPCTL_PRBDELTA_MASK (3 << OTGFS_GADPCTL_PRBDELTA_SHIFT)
#define OTGFS_GADPCTL_PRBPER_SHIFT (4) /* Bits 4-5: XXX */
#define OTGFS_GADPCTL_PRBPER_MASK (15 << OTGFS_GADPCTL_PRBPER_SHIFT)
#define OTGFS_GADPCTL_RTIM_SHIFT (6) /* Bits 6-9: XXX */
#define OTGFS_GADPCTL_RTIM_SHIFT (6) /* Bits 6-9: XXX */
#define OTGFS_GADPCTL_ENAPRB (1 << 17) /* Bit 17: XXX */
#define OTGFS_GADPCTL_ENASNS (1 << 18) /* Bit 18: XXX */
#define OTGFS_GADPCTL_ADPRST (1 << 19) /* Bit 19: XXX */
#define OTGFS_GADPCTL_ADPEN (1 << 20) /* Bit 20: XXX */
#define OTGFS_GADPCTL_ADPPRBIF (1 << 21) /* Bit 21: XXX */
#define OTGFS_GADPCTL_ADPSNSIF (1 << 22) /* Bit 22: XXX */
#define OTGFS_GADPCTL_ADPTOIF (1 << 23) /* Bit 23: XXX */
#define OTGFS_GADPCTL_ADPPRBIM (1 << 24) /* Bit 24: XXX */
#define OTGFS_GADPCTL_ADPSNSIM (1 << 25) /* Bit 25: XXX */
#define OTGFS_GADPCTL_ADPTOIM (1 << 26) /* Bit 26: XXX */
#define OTGFS_GADPCTL_AR_SHIFT (27) /* Bits 27-28: XXX */
#define OTGFS_GADPCTL_AR_MASK (3 << OTGFS_GADPCTL_AR_SHIFT)
/* Host periodic transmit FIFO size register */
#define OTGFS_HPTXFSIZ_PTXSA_SHIFT (0) /* Bits 0-15: Host periodic TxFIFO start address */
#define OTGFS_HPTXFSIZ_PTXSA_MASK (0xffff << OTGFS_HPTXFSIZ_PTXSA_SHIFT)
#define OTGFS_HPTXFSIZ_PTXFD_SHIFT (16) /* Bits 16-31: Host periodic TxFIFO depth */
#define OTGFS_HPTXFSIZ_PTXFD_MASK (0xffff << OTGFS_HPTXFSIZ_PTXFD_SHIFT)
/* Device IN endpoint transmit FIFOn size register */
#define OTGFS_DIEPTXF_INEPTXSA_SHIFT (0) /* Bits 0-15: IN endpoint FIFOx transmit RAM start address */
#define OTGFS_DIEPTXF_INEPTXSA_MASK (0xffff << OTGFS_DIEPTXF_INEPTXSA_SHIFT)
#define OTGFS_DIEPTXF_INEPTXFD_SHIFT (16) /* Bits 16-31: IN endpoint TxFIFO depth */
#define OTGFS_DIEPTXF_INEPTXFD_MASK (0xffff << OTGFS_DIEPTXF_INEPTXFD_SHIFT)
# define OTGFS_DIEPTXF_INEPTXFD_MIN (16 << OTGFS_DIEPTXF_INEPTXFD_MASK)
/* Host-mode control and status registers */
/* Host configuration register */
#define OTGFS_HCFG_FSLSPCS_SHIFT (0) /* Bits 0-1: FS/LS PHY clock select */
#define OTGFS_HCFG_FSLSPCS_MASK (3 << OTGFS_HCFG_FSLSPCS_SHIFT)
# define OTGFS_HCFG_FSLSPCS_FS48MHz (1 << OTGFS_HCFG_FSLSPCS_SHIFT) /* FS host mode, PHY clock is running at 48 MHz */
# define OTGFS_HCFG_FSLSPCS_LS48MHz (1 << OTGFS_HCFG_FSLSPCS_SHIFT) /* LS host mode, Select 48 MHz PHY clock frequency */
# define OTGFS_HCFG_FSLSPCS_LS6MHz (2 << OTGFS_HCFG_FSLSPCS_SHIFT) /* LS host mode, Select 6 MHz PHY clock frequency */
#define OTGFS_HCFG_FSLSS (1 << 2) /* Bit 2: FS- and LS-only support */
/* Bits 31:3 Reserved, must be kept at reset value */
/* Host frame interval register */
#define OTGFS_HFIR_MASK (0xffff)
#define OTGFS_HFIR_RLDCTRL (1 << 16) /* Bit 16: XXX */
/* Host frame number/frame time remaining register */
#define OTGFS_HFNUM_FRNUM_SHIFT (0) /* Bits 0-15: Frame number */
#define OTGFS_HFNUM_FRNUM_MASK (0xffff << OTGFS_HFNUM_FRNUM_SHIFT)
#define OTGFS_HFNUM_FTREM_SHIFT (16) /* Bits 16-31: Frame time remaining */
#define OTGFS_HFNUM_FTREM_MASK (0xffff << OTGFS_HFNUM_FTREM_SHIFT)
/* Host periodic transmit FIFO/queue status register */
#define OTGFS_HPTXSTS_PTXFSAVL_SHIFT (0) /* Bits 0-15: Periodic transmit data FIFO space available */
#define OTGFS_HPTXSTS_PTXFSAVL_MASK (0xffff << OTGFS_HPTXSTS_PTXFSAVL_SHIFT)
# define OTGFS_HPTXSTS_PTXFSAVL_FULL (0 << OTGFS_HPTXSTS_PTXFSAVL_SHIFT)
#define OTGFS_HPTXSTS_PTXQSAV_SHIFT (16) /* Bits 16-23: Periodic transmit request queue space available */
#define OTGFS_HPTXSTS_PTXQSAV_MASK (0xff << OTGFS_HPTXSTS_PTXQSAV_SHIFT)
# define OTGFS_HPTXSTS_PTXQSAV_FULL (0 << OTGFS_HPTXSTS_PTXQSAV_SHIFT)
#define OTGFS_HPTXSTS_PTXQTOP_SHIFT (24) /* Bits 24-31: Top of the periodic transmit request queue */
#define OTGFS_HPTXSTS_PTXQTOP_MASK (0x7f << OTGFS_HPTXSTS_PTXQTOP_SHIFT)
# define OTGFS_HPTXSTS_TERMINATE (1 << 24) /* Bit 24: Terminate (last entry for selected channel/endpoint) */
# define OTGFS_HPTXSTS_TYPE_SHIFT (25) /* Bits 25-26: Type */
# define OTGFS_HPTXSTS_TYPE_MASK (3 << OTGFS_HPTXSTS_TYPE_SHIFT)
# define OTGFS_HPTXSTS_TYPE_INOUT (0 << OTGFS_HPTXSTS_TYPE_SHIFT) /* IN/OUT token */
# define OTGFS_HPTXSTS_TYPE_ZLP (1 << OTGFS_HPTXSTS_TYPE_SHIFT) /* Zero-length transmit packet */
# define OTGFS_HPTXSTS_TYPE_HALT (3 << OTGFS_HPTXSTS_TYPE_SHIFT) /* Disable channel command */
# define OTGFS_HPTXSTS_EPNUM_SHIFT (27) /* Bits 27-30: Endpoint number */
# define OTGFS_HPTXSTS_EPNUM_MASK (15 << OTGFS_HPTXSTS_EPNUM_SHIFT)
# define OTGFS_HPTXSTS_CHNUM_SHIFT (27) /* Bits 27-30: Channel number */
# define OTGFS_HPTXSTS_CHNUM_MASK (15 << OTGFS_HPTXSTS_CHNUM_SHIFT)
# define OTGFS_HPTXSTS_ODD (1 << 24) /* Bit 31: Send in odd (vs even) frame */
/* Host all channels interrupt and all channels interrupt mask registers */
#define OTGFS_HAINT(n) (1 << (n)) /* Bits 15:0 HAINTM: Channel interrupt */
/* Host port control and status register */
#define OTGFS_HPRT_PCSTS (1 << 0) /* Bit 0: Port connect status */
#define OTGFS_HPRT_PCDET (1 << 1) /* Bit 1: Port connect detected */
#define OTGFS_HPRT_PENA (1 << 2) /* Bit 2: Port enable */
#define OTGFS_HPRT_PENCHNG (1 << 3) /* Bit 3: Port enable/disable change */
#define OTGFS_HPRT_POCA (1 << 4) /* Bit 4: Port overcurrent active */
#define OTGFS_HPRT_POCCHNG (1 << 5) /* Bit 5: Port overcurrent change */
#define OTGFS_HPRT_PRES (1 << 6) /* Bit 6: Port resume */
#define OTGFS_HPRT_PSUSP (1 << 7) /* Bit 7: Port suspend */
#define OTGFS_HPRT_PRST (1 << 8) /* Bit 8: Port reset */
/* Bit 9: Reserved, must be kept at reset value */
#define OTGFS_HPRT_PLSTS_SHIFT (10) /* Bits 10-11: Port line status */
#define OTGFS_HPRT_PLSTS_MASK (3 << OTGFS_HPRT_PLSTS_SHIFT)
# define OTGFS_HPRT_PLSTS_DP (1 << 10) /* Bit 10: Logic level of OTG_FS_FS_DP */
# define OTGFS_HPRT_PLSTS_DM (1 << 11) /* Bit 11: Logic level of OTG_FS_FS_DM */
#define OTGFS_HPRT_PPWR (1 << 12) /* Bit 12: Port power */
#define OTGFS_HPRT_PTCTL_SHIFT (13) /* Bits 13-16: Port test control */
#define OTGFS_HPRT_PTCTL_MASK (15 << OTGFS_HPRT_PTCTL_SHIFT)
# define OTGFS_HPRT_PTCTL_DISABLED (0 << OTGFS_HPRT_PTCTL_SHIFT) /* Test mode disabled */
# define OTGFS_HPRT_PTCTL_J (1 << OTGFS_HPRT_PTCTL_SHIFT) /* Test_J mode */
# define OTGFS_HPRT_PTCTL_L (2 << OTGFS_HPRT_PTCTL_SHIFT) /* Test_K mode */
# define OTGFS_HPRT_PTCTL_SE0_NAK (3 << OTGFS_HPRT_PTCTL_SHIFT) /* Test_SE0_NAK mode */
# define OTGFS_HPRT_PTCTL_PACKET (4 << OTGFS_HPRT_PTCTL_SHIFT) /* Test_Packet mode */
# define OTGFS_HPRT_PTCTL_FORCE (5 << OTGFS_HPRT_PTCTL_SHIFT) /* Test_Force_Enable */
#define OTGFS_HPRT_PSPD_SHIFT (17) /* Bits 17-18: Port speed */
#define OTGFS_HPRT_PSPD_MASK (3 << OTGFS_HPRT_PSPD_SHIFT)
# define OTGFS_HPRT_PSPD_FS (1 << OTGFS_HPRT_PSPD_SHIFT) /* Full speed */
# define OTGFS_HPRT_PSPD_LS (2 << OTGFS_HPRT_PSPD_SHIFT) /* Low speed */
/* Bits 19-31: Reserved, must be kept at reset value */
/* Host channel-n characteristics register */
#define OTGFS_HCCHAR_MPSIZ_SHIFT (0) /* Bits 0-10: Maximum packet size */
#define OTGFS_HCCHAR_MPSIZ_MASK (0x7ff << OTGFS_HCCHAR_MPSIZ_SHIFT)
#define OTGFS_HCCHAR_EPNUM_SHIFT (11) /* Bits 11-14: Endpoint number */
#define OTGFS_HCCHAR_EPNUM_MASK (15 << OTGFS_HCCHAR_EPNUM_SHIFT)
#define OTGFS_HCCHAR_EPDIR (1 << 15) /* Bit 15: Endpoint direction */
# define OTGFS_HCCHAR_EPDIR_OUT (0)
# define OTGFS_HCCHAR_EPDIR_IN OTGFS_HCCHAR_EPDIR
/* Bit 16 Reserved, must be kept at reset value */
#define OTGFS_HCCHAR_LSDEV (1 << 17) /* Bit 17: Low-speed device */
#define OTGFS_HCCHAR_EPTYP_SHIFT (18) /* Bits 18-19: Endpoint type */
#define OTGFS_HCCHAR_EPTYP_MASK (3 << OTGFS_HCCHAR_EPTYP_SHIFT)
# define OTGFS_HCCHAR_EPTYP_CTRL (0 << OTGFS_HCCHAR_EPTYP_SHIFT) /* Control */
# define OTGFS_HCCHAR_EPTYP_ISOC (1 << OTGFS_HCCHAR_EPTYP_SHIFT) /* Isochronous */
# define OTGFS_HCCHAR_EPTYP_BULK (2 << OTGFS_HCCHAR_EPTYP_SHIFT) /* Bulk */
# define OTGFS_HCCHAR_EPTYP_INTR (3 << OTGFS_HCCHAR_EPTYP_SHIFT) /* Interrupt */
#define OTGFS_HCCHAR_MCNT_SHIFT (20) /* Bits 20-21: Multicount */
#define OTGFS_HCCHAR_MCNT_MASK (3 << OTGFS_HCCHAR_MCNT_SHIFT)
#define OTGFS_HCCHAR_DAD_SHIFT (22) /* Bits 22-28: Device address */
#define OTGFS_HCCHAR_DAD_MASK (0x7f << OTGFS_HCCHAR_DAD_SHIFT)
#define OTGFS_HCCHAR_ODDFRM (1 << 29) /* Bit 29: Odd frame */
#define OTGFS_HCCHAR_CHDIS (1 << 30) /* Bit 30: Channel disable */
#define OTGFS_HCCHAR_CHENA (1 << 31) /* Bit 31: Channel enable */
/* Host channel-n interrupt and Host channel-0 interrupt mask registers */
#define OTGFS_HCINT_XFRC (1 << 0) /* Bit 0: Transfer completed */
#define OTGFS_HCINT_CHH (1 << 1) /* Bit 1: Channel halted */
/* Bit 2: Reserved, must be kept at reset value */
#define OTGFS_HCINT_STALL (1 << 3) /* Bit 3: STALL response received interrupt */
#define OTGFS_HCINT_NAK (1 << 4) /* Bit 4: NAK response received interrupt */
#define OTGFS_HCINT_ACK (1 << 5) /* Bit 5: ACK response received/transmitted interrupt */
#define OTGFS_HCINT_TXERR (1 << 7) /* Bit 7: Transaction error */
#define OTGFS_HCINT_BBERR (1 << 8) /* Bit 8: Babble error */
#define OTGFS_HCINT_FRMOR (1 << 9) /* Bit 9: Frame overrun */
#define OTGFS_HCINT_DTERR (1 << 10) /* Bit 10: Data toggle error */
/* Bits 11-31 Reserved, must be kept at reset value */
/* Host channel-n interrupt register */
#define OTGFS_HCTSIZ_XFRSIZ_SHIFT (0) /* Bits 0-18: Transfer size */
#define OTGFS_HCTSIZ_XFRSIZ_MASK (0x7ffff << OTGFS_HCTSIZ_XFRSIZ_SHIFT)
#define OTGFS_HCTSIZ_PKTCNT_SHIFT (19) /* Bits 19-28: Packet count */
#define OTGFS_HCTSIZ_PKTCNT_MASK (0x3ff << OTGFS_HCTSIZ_PKTCNT_SHIFT)
#define OTGFS_HCTSIZ_DPID_SHIFT (29) /* Bits 29-30: Data PID */
#define OTGFS_HCTSIZ_DPID_MASK (3 << OTGFS_HCTSIZ_DPID_SHIFT)
# define OTGFS_HCTSIZ_DPID_DATA0 (0 << OTGFS_HCTSIZ_DPID_SHIFT)
# define OTGFS_HCTSIZ_DPID_DATA2 (1 << OTGFS_HCTSIZ_DPID_SHIFT)
# define OTGFS_HCTSIZ_DPID_DATA1 (2 << OTGFS_HCTSIZ_DPID_SHIFT)
# define OTGFS_HCTSIZ_DPID_MDATA (3 << OTGFS_HCTSIZ_DPID_SHIFT) /* Non-control */
# define OTGFS_HCTSIZ_PID_SETUP (3 << OTGFS_HCTSIZ_DPID_SHIFT) /* Control */
/* Bit 31 Reserved, must be kept at reset value */
/* Device-mode control and status registers */
/* Device configuration register */
#define OTGFS_DCFG_DSPD_SHIFT (0) /* Bits 0-1: Device speed */
#define OTGFS_DCFG_DSPD_MASK (3 << OTGFS_DCFG_DSPD_SHIFT)
# define OTGFS_DCFG_DSPD_FS (3 << OTGFS_DCFG_DSPD_SHIFT) /* Full speed */
#define OTGFS_DCFG_NZLSOHSK (1 << 2) /* Bit 2: Non-zero-length status OUT handshake */
/* Bit 3: Reserved, must be kept at reset value */
#define OTGFS_DCFG_DAD_SHIFT (4) /* Bits 4-10: Device address */
#define OTGFS_DCFG_DAD_MASK (0x7f << OTGFS_DCFG_DAD_SHIFT)
#define OTGFS_DCFG_PFIVL_SHIFT (11) /* Bits 11-12: Periodic frame interval */
#define OTGFS_DCFG_PFIVL_MASK (3 << OTGFS_DCFG_PFIVL_SHIFT)
# define OTGFS_DCFG_PFIVL_80PCT (0 << OTGFS_DCFG_PFIVL_SHIFT) /* 80% of the frame interval */
# define OTGFS_DCFG_PFIVL_85PCT (1 << OTGFS_DCFG_PFIVL_SHIFT) /* 85% of the frame interval */
# define OTGFS_DCFG_PFIVL_90PCT (2 << OTGFS_DCFG_PFIVL_SHIFT) /* 90% of the frame interval */
# define OTGFS_DCFG_PFIVL_95PCT (3 << OTGFS_DCFG_PFIVL_SHIFT) /* 95% of the frame interval */
/* Bits 13-31 Reserved, must be kept at reset value */
/* Device control register */
#define OTGFS_TESTMODE_DISABLED (0) /* Test mode disabled */
#define OTGFS_TESTMODE_J (1) /* Test_J mode */
#define OTGFS_TESTMODE_K (2) /* Test_K mode */
#define OTGFS_TESTMODE_SE0_NAK (3) /* Test_SE0_NAK mode */
#define OTGFS_TESTMODE_PACKET (4) /* Test_Packet mode */
#define OTGFS_TESTMODE_FORCE (5) /* Test_Force_Enable */
#define OTGFS_DCTL_RWUSIG (1 << 0) /* Bit 0: Remote wakeup signaling */
#define OTGFS_DCTL_SDIS (1 << 1) /* Bit 1: Soft disconnect */
#define OTGFS_DCTL_GINSTS (1 << 2) /* Bit 2: Global IN NAK status */
#define OTGFS_DCTL_GONSTS (1 << 3) /* Bit 3: Global OUT NAK status */
#define OTGFS_DCTL_TCTL_SHIFT (4) /* Bits 4-6: Test control */
#define OTGFS_DCTL_TCTL_MASK (7 << OTGFS_DCTL_TCTL_SHIFT)
# define OTGFS_DCTL_TCTL_DISABLED (0 << OTGFS_DCTL_TCTL_SHIFT) /* Test mode disabled */
# define OTGFS_DCTL_TCTL_J (1 << OTGFS_DCTL_TCTL_SHIFT) /* Test_J mode */
# define OTGFS_DCTL_TCTL_K (2 << OTGFS_DCTL_TCTL_SHIFT) /* Test_K mode */
# define OTGFS_DCTL_TCTL_SE0_NAK (3 << OTGFS_DCTL_TCTL_SHIFT) /* Test_SE0_NAK mode */
# define OTGFS_DCTL_TCTL_PACKET (4 << OTGFS_DCTL_TCTL_SHIFT) /* Test_Packet mode */
# define OTGFS_DCTL_TCTL_FORCE (5 << OTGFS_DCTL_TCTL_SHIFT) /* Test_Force_Enable */
#define OTGFS_DCTL_SGINAK (1 << 7) /* Bit 7: Set global IN NAK */
#define OTGFS_DCTL_CGINAK (1 << 8) /* Bit 8: Clear global IN NAK */
#define OTGFS_DCTL_SGONAK (1 << 9) /* Bit 9: Set global OUT NAK */
#define OTGFS_DCTL_CGONAK (1 << 10) /* Bit 10: Clear global OUT NAK */
#define OTGFS_DCTL_POPRGDNE (1 << 11) /* Bit 11: Power-on programming done */
/* Bits 12-17: Reserved, must be kept at reset value */
#define OTGFS_DCTL_DSBESLRJCT (1 << 18) /* Bit 18: Deep sleep BESL reject */
/* Bits 19-31: Reserved, must be kept at reset value */
/* Device status register */
#define OTGFS_DSTS_SUSPSTS (1 << 0) /* Bit 0: Suspend status */
#define OTGFS_DSTS_ENUMSPD_SHIFT (1) /* Bits 1-2: Enumerated speed */
#define OTGFS_DSTS_ENUMSPD_MASK (3 << OTGFS_DSTS_ENUMSPD_SHIFT)
# define OTGFS_DSTS_ENUMSPD_FS (3 << OTGFS_DSTS_ENUMSPD_MASK) /* Full speed */
/* Bits 4-7: Reserved, must be kept at reset value */
#define OTGFS_DSTS_EERR (1 << 3) /* Bit 3: Erratic error */
#define OTGFS_DSTS_SOFFN_SHIFT (8) /* Bits 8-21: Frame number of the received SOF */
#define OTGFS_DSTS_SOFFN_MASK (0x3fff << OTGFS_DSTS_SOFFN_SHIFT)
#define OTGFS_DSTS_SOFFN0 (1 << 8) /* Bits 8: Frame number even/odd bit */
#define OTGFS_DSTS_SOFFN_EVEN 0
#define OTGFS_DSTS_SOFFN_ODD OTGFS_DSTS_SOFFN0
#define OTGFS_DSTS_DEVLNSTS_SHIFT (22) /* Bits 22-23: XXX */
#define OTGFS_DSTS_DEVLNSTS_MASK (0x3 << OTGFS_DSTS_DEVLNSTS_SHIFT)
/* Bits 24-31: Reserved, must be kept at reset value */
/* Device IN endpoint common interrupt mask register */
#define OTGFS_DIEPMSK_XFRCM (1 << 0) /* Bit 0: Transfer completed interrupt mask */
#define OTGFS_DIEPMSK_EPDM (1 << 1) /* Bit 1: Endpoint disabled interrupt mask */
/* Bit 2: Reserved, must be kept at reset value */
#define OTGFS_DIEPMSK_TOM (1 << 3) /* Bit 3: Timeout condition mask (Non-isochronous endpoints) */
#define OTGFS_DIEPMSK_ITTXFEMSK (1 << 4) /* Bit 4: IN token received when TxFIFO empty mask */
#define OTGFS_DIEPMSK_INEPNMM (1 << 5) /* Bit 5: IN token received with EP mismatch mask */
#define OTGFS_DIEPMSK_INEPNEM (1 << 6) /* Bit 6: IN endpoint NAK effective mask */
/* Bits 7-12: Reserved, must be kept at reset value */
#define OTGFS_DIEPMSK_NAKM (1 << 13) /* Bit 13: NAK interrupt mask */
/* Bits 14-31: Reserved, must be kept at reset value */
/* Device OUT endpoint common interrupt mask register */
#define OTGFS_DOEPMSK_XFRCM (1 << 0) /* Bit 0: Transfer completed interrupt mask */
#define OTGFS_DOEPMSK_EPDM (1 << 1) /* Bit 1: Endpoint disabled interrupt mask */
/* Bit 2: Reserved, must be kept at reset value */
#define OTGFS_DOEPMSK_STUPM (1 << 3) /* Bit 3: SETUP phase done mask */
#define OTGFS_DOEPMSK_OTEPDM (1 << 4) /* Bit 4: OUT token received when endpoint disabled mask */
/* Bits 5-31: Reserved, must be kept at reset value */
/* Device all endpoints interrupt and All endpoints interrupt mask registers */
#define OTGFS_DAINT_IEP_SHIFT (0) /* Bits 0-15: IN endpoint interrupt bits */
#define OTGFS_DAINT_IEP_MASK (0xffff << OTGFS_DAINT_IEP_SHIFT)
# define OTGFS_DAINT_IEP(n) (1 << (n))
#define OTGFS_DAINT_OEP_SHIFT (16) /* Bits 16-31: OUT endpoint interrupt bits */
#define OTGFS_DAINT_OEP_MASK (0xffff << OTGFS_DAINT_OEP_SHIFT)
# define OTGFS_DAINT_OEP(n) (1 << ((n)+16))
/* Device VBUS discharge time register */
#define OTGFS_DVBUSDIS_MASK (0xffff)
/* Device VBUS pulsing time register */
#define OTGFS_DVBUSPULSE_MASK (0xffff)
/* Device IN endpoint FIFO empty interrupt mask register */
#define OTGFS_DIEPEMPMSK(n) (1 << (n))
/* Device control IN endpoint 0 control register */
#define OTGFS_DIEPCTL0_MPSIZ_SHIFT (0) /* Bits 0-1: Maximum packet size */
#define OTGFS_DIEPCTL0_MPSIZ_MASK (3 << OTGFS_DIEPCTL0_MPSIZ_SHIFT)
# define OTGFS_DIEPCTL0_MPSIZ_64 (0 << OTGFS_DIEPCTL0_MPSIZ_SHIFT) /* 64 bytes */
# define OTGFS_DIEPCTL0_MPSIZ_32 (1 << OTGFS_DIEPCTL0_MPSIZ_SHIFT) /* 32 bytes */
# define OTGFS_DIEPCTL0_MPSIZ_16 (2 << OTGFS_DIEPCTL0_MPSIZ_SHIFT) /* 16 bytes */
# define OTGFS_DIEPCTL0_MPSIZ_8 (3 << OTGFS_DIEPCTL0_MPSIZ_SHIFT) /* 8 bytes */
/* Bits 2-14: Reserved, must be kept at reset value */
#define OTGFS_DIEPCTL0_USBAEP (1 << 15) /* Bit 15: USB active endpoint */
/* Bit 16: Reserved, must be kept at reset value */
#define OTGFS_DIEPCTL0_NAKSTS (1 << 17) /* Bit 17: NAK status */
#define OTGFS_DIEPCTL0_EPTYP_SHIFT (18) /* Bits 18-19: Endpoint type */
#define OTGFS_DIEPCTL0_EPTYP_MASK (3 << OTGFS_DIEPCTL0_EPTYP_SHIFT)
# define OTGFS_DIEPCTL0_EPTYP_CTRL (0 << OTGFS_DIEPCTL0_EPTYP_SHIFT) /* Control (hard-coded) */
/* Bit 20: Reserved, must be kept at reset value */
#define OTGFS_DIEPCTL0_STALL (1 << 21) /* Bit 21: STALL handshake */
#define OTGFS_DIEPCTL0_TXFNUM_SHIFT (22) /* Bits 22-25: TxFIFO number */
#define OTGFS_DIEPCTL0_TXFNUM_MASK (15 << OTGFS_DIEPCTL0_TXFNUM_SHIFT)
#define OTGFS_DIEPCTL0_CNAK (1 << 26) /* Bit 26: Clear NAK */
#define OTGFS_DIEPCTL0_SNAK (1 << 27) /* Bit 27: Set NAK */
/* Bits 28-29: Reserved, must be kept at reset value */
#define OTGFS_DIEPCTL0_EPDIS (1 << 30) /* Bit 30: Endpoint disable */
#define OTGFS_DIEPCTL0_EPENA (1 << 31) /* Bit 31: Endpoint enable */
/* Device control IN endpoint n control register */
#define OTGFS_DIEPCTL_MPSIZ_SHIFT (0) /* Bits 0-10: Maximum packet size */
#define OTGFS_DIEPCTL_MPSIZ_MASK (0x7ff << OTGFS_DIEPCTL_MPSIZ_SHIFT)
/* Bits 11-14: Reserved, must be kept at reset value */
#define OTGFS_DIEPCTL_USBAEP (1 << 15) /* Bit 15: USB active endpoint */
#define OTGFS_DIEPCTL_EONUM (1 << 16) /* Bit 16: Even/odd frame */
# define OTGFS_DIEPCTL_EVEN (0)
# define OTGFS_DIEPCTL_ODD OTGFS_DIEPCTL_EONUM
# define OTGFS_DIEPCTL_DATA0 (0)
# define OTGFS_DIEPCTL_DATA1 OTGFS_DIEPCTL_EONUM
#define OTGFS_DIEPCTL_NAKSTS (1 << 17) /* Bit 17: NAK status */
#define OTGFS_DIEPCTL_EPTYP_SHIFT (18) /* Bits 18-19: Endpoint type */
#define OTGFS_DIEPCTL_EPTYP_MASK (3 << OTGFS_DIEPCTL_EPTYP_SHIFT)
# define OTGFS_DIEPCTL_EPTYP_CTRL (0 << OTGFS_DIEPCTL_EPTYP_SHIFT) /* Control */
# define OTGFS_DIEPCTL_EPTYP_ISOC (1 << OTGFS_DIEPCTL_EPTYP_SHIFT) /* Isochronous */
# define OTGFS_DIEPCTL_EPTYP_BULK (2 << OTGFS_DIEPCTL_EPTYP_SHIFT) /* Bulk */
# define OTGFS_DIEPCTL_EPTYP_INTR (3 << OTGFS_DIEPCTL_EPTYP_SHIFT) /* Interrupt */
/* Bit 20: Reserved, must be kept at reset value */
#define OTGFS_DIEPCTL_STALL (1 << 21) /* Bit 21: STALL handshake */
#define OTGFS_DIEPCTL_TXFNUM_SHIFT (22) /* Bits 22-25: TxFIFO number */
#define OTGFS_DIEPCTL_TXFNUM_MASK (15 << OTGFS_DIEPCTL_TXFNUM_SHIFT)
#define OTGFS_DIEPCTL_CNAK (1 << 26) /* Bit 26: Clear NAK */
#define OTGFS_DIEPCTL_SNAK (1 << 27) /* Bit 27: Set NAK */
#define OTGFS_DIEPCTL_SD0PID (1 << 28) /* Bit 28: Set DATA0 PID (interrupt/bulk) */
#define OTGFS_DIEPCTL_SEVNFRM (1 << 28) /* Bit 28: Set even frame (isochronous)) */
#define OTGFS_DIEPCTL_SODDFRM (1 << 29) /* Bit 29: Set odd frame (isochronous) */
#define OTGFS_DIEPCTL_EPDIS (1 << 30) /* Bit 30: Endpoint disable */
#define OTGFS_DIEPCTL_EPENA (1 << 31) /* Bit 31: Endpoint enable */
/* Device endpoint-n interrupt register */
#define OTGFS_DIEPINT_XFRC (1 << 0) /* Bit 0: Transfer completed interrupt */
#define OTGFS_DIEPINT_EPDISD (1 << 1) /* Bit 1: Endpoint disabled interrupt */
/* Bit 2: Reserved, must be kept at reset value */
#define OTGFS_DIEPINT_TOC (1 << 3) /* Bit 3: Timeout condition */
#define OTGFS_DIEPINT_ITTXFE (1 << 4) /* Bit 4: IN token received when TxFIFO is empty */
/* Bit 5: Reserved, must be kept at reset value */
#define OTGFS_DIEPINT_INEPNE (1 << 6) /* Bit 6: IN endpoint NAK effective */
#define OTGFS_DIEPINT_TXFE (1 << 7) /* Bit 7: Transmit FIFO empty */
/* Bits 8-31: Reserved, must be kept at reset value */
/* Device IN endpoint 0 transfer size register */
#define OTGFS_DIEPTSIZ0_XFRSIZ_SHIFT (0) /* Bits 0-6: Transfer size */
#define OTGFS_DIEPTSIZ0_XFRSIZ_MASK (0x7f << OTGFS_DIEPTSIZ0_XFRSIZ_SHIFT)
/* Bits 7-18: Reserved, must be kept at reset value */
#define OTGFS_DIEPTSIZ0_PKTCNT_SHIFT (19) /* Bits 19-20: Packet count */
#define OTGFS_DIEPTSIZ0_PKTCNT_MASK (3 << OTGFS_DIEPTSIZ0_PKTCNT_SHIFT)
/* Bits 21-31: Reserved, must be kept at reset value */
/* Device IN endpoint n transfer size register */
#define OTGFS_DIEPTSIZ_XFRSIZ_SHIFT (0) /* Bits 0-18: Transfer size */
#define OTGFS_DIEPTSIZ_XFRSIZ_MASK (0x7ffff << OTGFS_DIEPTSIZ_XFRSIZ_SHIFT)
#define OTGFS_DIEPTSIZ_PKTCNT_SHIFT (19) /* Bit 19-28: Packet count */
#define OTGFS_DIEPTSIZ_PKTCNT_MASK (0x3ff << OTGFS_DIEPTSIZ_PKTCNT_SHIFT)
#define OTGFS_DIEPTSIZ_MCNT_SHIFT (29) /* Bits 29-30: Multi count */
#define OTGFS_DIEPTSIZ_MCNT_MASK (3 << OTGFS_DIEPTSIZ_MCNT_SHIFT)
/* Bit 31: Reserved, must be kept at reset value */
/* Device OUT endpoint TxFIFO status register */
#define OTGFS_DTXFSTS_MASK (0xffff)
/* Device OUT endpoint 0 control register */
#define OTGFS_DOEPCTL0_MPSIZ_SHIFT (0) /* Bits 0-1: Maximum packet size */
#define OTGFS_DOEPCTL0_MPSIZ_MASK (3 << OTGFS_DOEPCTL0_MPSIZ_SHIFT)
# define OTGFS_DOEPCTL0_MPSIZ_64 (0 << OTGFS_DOEPCTL0_MPSIZ_SHIFT) /* 64 bytes */
# define OTGFS_DOEPCTL0_MPSIZ_32 (1 << OTGFS_DOEPCTL0_MPSIZ_SHIFT) /* 32 bytes */
# define OTGFS_DOEPCTL0_MPSIZ_16 (2 << OTGFS_DOEPCTL0_MPSIZ_SHIFT) /* 16 bytes */
# define OTGFS_DOEPCTL0_MPSIZ_8 (3 << OTGFS_DOEPCTL0_MPSIZ_SHIFT) /* 8 bytes */
/* Bits 2-14: Reserved, must be kept at reset value */
#define OTGFS_DOEPCTL0_USBAEP (1 << 15) /* Bit 15: USB active endpoint */
/* Bit 16: Reserved, must be kept at reset value */
#define OTGFS_DOEPCTL0_NAKSTS (1 << 17) /* Bit 17: NAK status */
#define OTGFS_DOEPCTL0_EPTYP_SHIFT (18) /* Bits 18-19: Endpoint type */
#define OTGFS_DOEPCTL0_EPTYP_MASK (3 << OTGFS_DOEPCTL0_EPTYP_SHIFT)
# define OTGFS_DOEPCTL0_EPTYP_CTRL (0 << OTGFS_DOEPCTL0_EPTYP_SHIFT) /* Control (hard-coded) */
#define OTGFS_DOEPCTL0_SNPM (1 << 20) /* Bit 20: Snoop mode */
#define OTGFS_DOEPCTL0_STALL (1 << 21) /* Bit 21: STALL handshake */
/* Bits 22-25: Reserved, must be kept at reset value */
#define OTGFS_DOEPCTL0_CNAK (1 << 26) /* Bit 26: Clear NAK */
#define OTGFS_DOEPCTL0_SNAK (1 << 27) /* Bit 27: Set NAK */
/* Bits 28-29: Reserved, must be kept at reset value */
#define OTGFS_DOEPCTL0_EPDIS (1 << 30) /* Bit 30: Endpoint disable */
#define OTGFS_DOEPCTL0_EPENA (1 << 31) /* Bit 31: Endpoint enable */
/* Device OUT endpoint n control register */
#define OTGFS_DOEPCTL_MPSIZ_SHIFT (0) /* Bits 0-10: Maximum packet size */
#define OTGFS_DOEPCTL_MPSIZ_MASK (0x7ff << OTGFS_DOEPCTL_MPSIZ_SHIFT)
/* Bits 11-14: Reserved, must be kept at reset value */
#define OTGFS_DOEPCTL_USBAEP (1 << 15) /* Bit 15: USB active endpoint */
#define OTGFS_DOEPCTL_DPID (1 << 16) /* Bit 16: Endpoint data PID (interrupt/buld) */
# define OTGFS_DOEPCTL_DATA0 (0)
# define OTGFS_DOEPCTL_DATA1 OTGFS_DOEPCTL_DPID
#define OTGFS_DOEPCTL_EONUM (1 << 16) /* Bit 16: Even/odd frame (isochronous) */
# define OTGFS_DOEPCTL_EVEN (0)
# define OTGFS_DOEPCTL_ODD OTGFS_DOEPCTL_EONUM
#define OTGFS_DOEPCTL_NAKSTS (1 << 17) /* Bit 17: NAK status */
#define OTGFS_DOEPCTL_EPTYP_SHIFT (18) /* Bits 18-19: Endpoint type */
#define OTGFS_DOEPCTL_EPTYP_MASK (3 << OTGFS_DOEPCTL_EPTYP_SHIFT)
# define OTGFS_DOEPCTL_EPTYP_CTRL (0 << OTGFS_DOEPCTL_EPTYP_SHIFT) /* Control */
# define OTGFS_DOEPCTL_EPTYP_ISOC (1 << OTGFS_DOEPCTL_EPTYP_SHIFT) /* Isochronous */
# define OTGFS_DOEPCTL_EPTYP_BULK (2 << OTGFS_DOEPCTL_EPTYP_SHIFT) /* Bulk */
# define OTGFS_DOEPCTL_EPTYP_INTR (3 << OTGFS_DOEPCTL_EPTYP_SHIFT) /* Interrupt */
#define OTGFS_DOEPCTL_SNPM (1 << 20) /* Bit 20: Snoop mode */
#define OTGFS_DOEPCTL_STALL (1 << 21) /* Bit 21: STALL handshake */
/* Bits 22-25: Reserved, must be kept at reset value */
#define OTGFS_DOEPCTL_CNAK (1 << 26) /* Bit 26: Clear NAK */
#define OTGFS_DOEPCTL_SNAK (1 << 27) /* Bit 27: Set NAK */
#define OTGFS_DOEPCTL_SD0PID (1 << 28) /* Bit 28: Set DATA0 PID (interrupt/bulk) */
#define OTGFS_DOEPCTL_SEVNFRM (1 << 28) /* Bit 28: Set even frame (isochronous) */
#define OTGFS_DOEPCTL_SD1PID (1 << 29) /* Bit 29: Set DATA1 PID (interrupt/bulk) */
#define OTGFS_DOEPCTL_SODDFRM (1 << 29) /* Bit 29: Set odd frame (isochronous */
#define OTGFS_DOEPCTL_EPDIS (1 << 30) /* Bit 30: Endpoint disable */
#define OTGFS_DOEPCTL_EPENA (1 << 31) /* Bit 31: Endpoint enable */
/* Device endpoint-n interrupt register */
#define OTGFS_DOEPINT_XFRC (1 << 0) /* Bit 0: Transfer completed interrupt */
#define OTGFS_DOEPINT_EPDISD (1 << 1) /* Bit 1: Endpoint disabled interrupt */
/* Bit 2: Reserved, must be kept at reset value */
#define OTGFS_DOEPINT_SETUP (1 << 3) /* Bit 3: SETUP phase done */
#define OTGFS_DOEPINT_OTEPDIS (1 << 4) /* Bit 4: OUT token received when endpoint disabled */
/* Bit 5: Reserved, must be kept at reset value */
#define OTGFS_DOEPINT_B2BSTUP (1 << 6) /* Bit 6: Back-to-back SETUP packets received */
/* Bits 7-31: Reserved, must be kept at reset value */
/* Device OUT endpoint-0 transfer size register */
#define OTGFS_DOEPTSIZ0_XFRSIZ_SHIFT (0) /* Bits 0-6: Transfer size */
#define OTGFS_DOEPTSIZ0_XFRSIZ_MASK (0x7f << OTGFS_DOEPTSIZ0_XFRSIZ_SHIFT)
/* Bits 7-18: Reserved, must be kept at reset value */
#define OTGFS_DOEPTSIZ0_PKTCNT (1 << 19) /* Bit 19 PKTCNT: Packet count */
/* Bits 20-28: Reserved, must be kept at reset value */
#define OTGFS_DOEPTSIZ0_STUPCNT_SHIFT (29) /* Bits 29-30: SETUP packet count */
#define OTGFS_DOEPTSIZ0_STUPCNT_MASK (3 << OTGFS_DOEPTSIZ0_STUPCNT_SHIFT)
/* Bit 31: Reserved, must be kept at reset value */
/* Device OUT endpoint-n transfer size register */
#define OTGFS_DOEPTSIZ_XFRSIZ_SHIFT (0) /* Bits 0-18: Transfer size */
#define OTGFS_DOEPTSIZ_XFRSIZ_MASK (0x7ffff << OTGFS_DOEPTSIZ_XFRSIZ_SHIFT)
#define OTGFS_DOEPTSIZ_PKTCNT_SHIFT (19) /* Bit 19-28: Packet count */
#define OTGFS_DOEPTSIZ_PKTCNT_MASK (0x3ff << OTGFS_DOEPTSIZ_PKTCNT_SHIFT)
#define OTGFS_DOEPTSIZ_STUPCNT_SHIFT (29) /* Bits 29-30: SETUP packet count */
#define OTGFS_DOEPTSIZ_STUPCNT_MASK (3 << OTGFS_DOEPTSIZ_STUPCNT_SHIFT)
#define OTGFS_DOEPTSIZ_RXDPID_SHIFT (29) /* Bits 29-30: Received data PID */
#define OTGFS_DOEPTSIZ_RXDPID_MASK (3 << OTGFS_DOEPTSIZ_RXDPID_SHIFT)
# define OTGFS_DOEPTSIZ_RXDPID_DATA0 (0 << OTGFS_DOEPTSIZ_RXDPID_SHIFT)
# define OTGFS_DOEPTSIZ_RXDPID_DATA2 (1 << OTGFS_DOEPTSIZ_RXDPID_SHIFT)
# define OTGFS_DOEPTSIZ_RXDPID_DATA1 (2 << OTGFS_DOEPTSIZ_RXDPID_SHIFT)
# define OTGFS_DOEPTSIZ_RXDPID_MDATA (3 << OTGFS_DOEPTSIZ_RXDPID_SHIFT)
/* Bit 31: Reserved, must be kept at reset value */
/* Power and clock gating control register */
#define OTGFS_PCGCCTL_STPPCLK (1 << 0) /* Bit 0: Stop PHY clock */
#define OTGFS_PCGCCTL_GATEHCLK (1 << 1) /* Bit 1: Gate HCLK */
/* Bits 2-3: Reserved, must be kept at reset value */
#define OTGFS_PCGCCTL_PHYSUSP (1 << 4) /* Bit 4: PHY Suspended */
#define OTGFS_PCGCCTL_ENL1GTG (1 << 5) /* Bit 5: Enable Sleep clock gating */
#define OTGFS_PCGCCTL_PHYSLEEP (1 << 6) /* Bit 6: PHY in Sleep */
#define OTGFS_PCGCCTL_SUSP (1 << 7) /* Bit 7: Deep Sleep */
/* Bits 8-31: Reserved, must be kept at reset value */
#endif /* __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4X5XX_OTGFS_H */

789
arch/arm/src/stm32l4/chip/stm32l4x5xx_pinmap.h Normal file
View file

@ -0,0 +1,789 @@
/************************************************************************************
* arch/arm/src/stm32l4/chip/stm32l4x5xx_pinmap.h
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
* Copyright (C) 2015-2016 Sebastien Lorquet. All rights reserved.
* Author: Sebastien Lorquet <sebastien@lorquet.fr>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4X5XX_PINMAP_H
#define __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4X5XX_PINMAP_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
#include "stm32l4_gpio.h"
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* Alternate Pin Functions. All members of the STM32L4xxx family share the same
* pin multiplexing (although they may differ in the pins physically available).
*
* Alternative pin selections are provided with a numeric suffix like _1, _2, etc.
* Drivers, however, will use the pin selection without the numeric suffix.
* Additional definitions are required in the board.h file. For example, if
* CAN1_RX connects vis PA11 on some board, then the following definitions should
* appear inthe board.h header file for that board:
*
* #define GPIO_CAN1_RX GPIO_CAN1_RX_1
*
* The driver will then automatically configre PA11 as the CAN1 RX pin.
*/
/* WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!!
* Additional effort is required to select specific GPIO options such as frequency,
* open-drain/push-pull, and pull-up/down! Just the basics are defined for most
* pins in this file.
*/
/* ADC */
#define GPIO_ADC1_IN1 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN0)
#define GPIO_ADC1_IN2 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN1)
#define GPIO_ADC1_IN3 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN2)
#define GPIO_ADC1_IN4 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN3)
#define GPIO_ADC1_IN5 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN0)
#define GPIO_ADC1_IN6 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN1)
#define GPIO_ADC1_IN7 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN2)
#define GPIO_ADC1_IN8 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN3)
#define GPIO_ADC1_IN9 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN4)
#define GPIO_ADC1_IN10 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN5)
#define GPIO_ADC1_IN11 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN6)
#define GPIO_ADC1_IN12 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN7)
#define GPIO_ADC1_IN13 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN4)
#define GPIO_ADC1_IN14 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN5)
#define GPIO_ADC1_IN15 (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN0)
#define GPIO_ADC1_IN16 (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN1)
#define GPIO_ADC2_IN1 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN0)
#define GPIO_ADC2_IN2 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN1)
#define GPIO_ADC2_IN3 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN2)
#define GPIO_ADC2_IN4 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN3)
#define GPIO_ADC2_IN5 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN0)
#define GPIO_ADC2_IN6 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN1)
#define GPIO_ADC2_IN7 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN2)
#define GPIO_ADC2_IN8 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN3)
#define GPIO_ADC2_IN9 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN4)
#define GPIO_ADC2_IN10 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN5)
#define GPIO_ADC2_IN11 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN6)
#define GPIO_ADC2_IN12 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN7)
#define GPIO_ADC2_IN13 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN4)
#define GPIO_ADC2_IN14 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN5)
#define GPIO_ADC2_IN15 (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN0)
#define GPIO_ADC2_IN16 (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN1)
#define GPIO_ADC3_IN1 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN0)
#define GPIO_ADC3_IN2 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN1)
#define GPIO_ADC3_IN3 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN2)
#define GPIO_ADC3_IN4 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN3)
#define GPIO_ADC3_IN6 (GPIO_ANALOG|GPIO_PORTF|GPIO_PIN3)
#define GPIO_ADC3_IN7 (GPIO_ANALOG|GPIO_PORTF|GPIO_PIN4)
#define GPIO_ADC3_IN8 (GPIO_ANALOG|GPIO_PORTF|GPIO_PIN5)
#define GPIO_ADC3_IN9 (GPIO_ANALOG|GPIO_PORTF|GPIO_PIN6)
#define GPIO_ADC3_IN10 (GPIO_ANALOG|GPIO_PORTF|GPIO_PIN7)
#define GPIO_ADC3_IN11 (GPIO_ANALOG|GPIO_PORTF|GPIO_PIN8)
#define GPIO_ADC3_IN12 (GPIO_ANALOG|GPIO_PORTF|GPIO_PIN9)
#define GPIO_ADC3_IN13 (GPIO_ANALOG|GPIO_PORTF|GPIO_PIN10)
/* CAN */
#define GPIO_CAN1_RX_1 (GPIO_ALT|GPIO_AF9 |GPIO_PORTA|GPIO_PIN11)
#define GPIO_CAN1_RX_2 (GPIO_ALT|GPIO_AF9 |GPIO_PORTB|GPIO_PIN8)
#define GPIO_CAN1_RX_3 (GPIO_ALT|GPIO_AF9 |GPIO_PORTD|GPIO_PIN0)
#define GPIO_CAN1_TX_1 (GPIO_ALT|GPIO_AF9 |GPIO_PORTA|GPIO_PIN12)
#define GPIO_CAN1_TX_2 (GPIO_ALT|GPIO_AF9 |GPIO_PORTB|GPIO_PIN9)
#define GPIO_CAN1_TX_3 (GPIO_ALT|GPIO_AF9 |GPIO_PORTD|GPIO_PIN1)
/* Clocks outputs */
#define GPIO_MCO (GPIO_ALT|GPIO_AF0 |GPIO_PORTA|GPIO_PIN8)
/* Comparators */
#define GPIO_COMP1_INM_1 (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN1)
#define GPIO_COMP1_INM_2 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN4)
#define GPIO_COMP1_INP_1 (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN2)
#define GPIO_COMP1_INP_2 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN5)
#define GPIO_COMP1_OUT_1 (GPIO_ALT|GPIO_AF12|GPIO_PORTB|GPIO_PIN0)
#define GPIO_COMP1_OUT_2 (GPIO_ALT|GPIO_AF12|GPIO_PORTB|GPIO_PIN10)
#define GPIO_COMP2_INM_1 (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN3)
#define GPIO_COMP2_INM_2 (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN7)
#define GPIO_COMP2_INP_1 (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN4)
#define GPIO_COMP2_INP_2 (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN6)
#define GPIO_COMP2_OUT_1 (GPIO_ALT|GPIO_AF12|GPIO_PORTB|GPIO_PIN5)
#define GPIO_COMP2_OUT_2 (GPIO_ALT|GPIO_AF12|GPIO_PORTB|GPIO_PIN11)
/* DAC */
#define GPIO_DAC1_OUT (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN4)
#define GPIO_DAC2_OUT (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN5)
/* Digital Filter for Sigma-Delta Modulators (DFSDM) */
#define GPIO_DFSDM_DATIN0_1 (GPIO_ALT|GPIO_AF6 |GPIO_PORTB|GPIO_PIN1)
#define GPIO_DFSDM_DATIN0_2 (GPIO_ALT|GPIO_AF6 |GPIO_PORTD|GPIO_PIN3)
#define GPIO_DFSDM_DATIN1_1 (GPIO_ALT|GPIO_AF6 |GPIO_PORTB|GPIO_PIN12)
#define GPIO_DFSDM_DATIN1_2 (GPIO_ALT|GPIO_AF6 |GPIO_PORTD|GPIO_PIN6)
#define GPIO_DFSDM_DATIN2_1 (GPIO_ALT|GPIO_AF6 |GPIO_PORTB|GPIO_PIN14)
#define GPIO_DFSDM_DATIN2_2 (GPIO_ALT|GPIO_AF6 |GPIO_PORTE|GPIO_PIN7)
#define GPIO_DFSDM_DATIN3_1 (GPIO_ALT|GPIO_AF6 |GPIO_PORTC|GPIO_PIN7)
#define GPIO_DFSDM_DATIN3_2 (GPIO_ALT|GPIO_AF6 |GPIO_PORTE|GPIO_PIN4)
#define GPIO_DFSDM_DATIN4_1 (GPIO_ALT|GPIO_AF6 |GPIO_PORTC|GPIO_PIN0)
#define GPIO_DFSDM_DATIN4_2 (GPIO_ALT|GPIO_AF6 |GPIO_PORTE|GPIO_PIN10)
#define GPIO_DFSDM_DATIN5_1 (GPIO_ALT|GPIO_AF6 |GPIO_PORTB|GPIO_PIN6)
#define GPIO_DFSDM_DATIN5_2 (GPIO_ALT|GPIO_AF6 |GPIO_PORTE|GPIO_PIN12)
#define GPIO_DFSDM_DATIN6_1 (GPIO_ALT|GPIO_AF6 |GPIO_PORTB|GPIO_PIN8)
#define GPIO_DFSDM_DATIN6_2 (GPIO_ALT|GPIO_AF6 |GPIO_PORTF|GPIO_PIN13)
#define GPIO_DFSDM_DATIN7_1 (GPIO_ALT|GPIO_AF6 |GPIO_PORTB|GPIO_PIN10)
#define GPIO_DFSDM_DATIN7_2 (GPIO_ALT|GPIO_AF6 |GPIO_PORTD|GPIO_PIN0)
#define GPIO_DFSDM_CKIN0_1 (GPIO_ALT|GPIO_AF6 |GPIO_PORTB|GPIO_PIN2)
#define GPIO_DFSDM_CKIN0_2 (GPIO_ALT|GPIO_AF6 |GPIO_PORTD|GPIO_PIN4)
#define GPIO_DFSDM_CKIN1_1 (GPIO_ALT|GPIO_AF6 |GPIO_PORTB|GPIO_PIN13)
#define GPIO_DFSDM_CKIN1_2 (GPIO_ALT|GPIO_AF6 |GPIO_PORTD|GPIO_PIN7)
#define GPIO_DFSDM_CKIN2_1 (GPIO_ALT|GPIO_AF6 |GPIO_PORTB|GPIO_PIN15)
#define GPIO_DFSDM_CKIN2_2 (GPIO_ALT|GPIO_AF6 |GPIO_PORTE|GPIO_PIN8)
#define GPIO_DFSDM_CKIN3_1 (GPIO_ALT|GPIO_AF6 |GPIO_PORTC|GPIO_PIN6)
#define GPIO_DFSDM_CKIN3_2 (GPIO_ALT|GPIO_AF6 |GPIO_PORTE|GPIO_PIN5)
#define GPIO_DFSDM_CKIN4_1 (GPIO_ALT|GPIO_AF6 |GPIO_PORTC|GPIO_PIN1)
#define GPIO_DFSDM_CKIN4_2 (GPIO_ALT|GPIO_AF6 |GPIO_PORTE|GPIO_PIN11)
#define GPIO_DFSDM_CKIN5_1 (GPIO_ALT|GPIO_AF6 |GPIO_PORTB|GPIO_PIN7)
#define GPIO_DFSDM_CKIN5_2 (GPIO_ALT|GPIO_AF6 |GPIO_PORTE|GPIO_PIN13)
#define GPIO_DFSDM_CKIN6_1 (GPIO_ALT|GPIO_AF6 |GPIO_PORTB|GPIO_PIN9)
#define GPIO_DFSDM_CKIN6_2 (GPIO_ALT|GPIO_AF6 |GPIO_PORTF|GPIO_PIN14)
#define GPIO_DFSDM_CKIN7_1 (GPIO_ALT|GPIO_AF6 |GPIO_PORTB|GPIO_PIN11)
#define GPIO_DFSDM_CKIN7_2 (GPIO_ALT|GPIO_AF6 |GPIO_PORTD|GPIO_PIN1)
#define GPIO_DFSDM_CKOUT_1 (GPIO_ALT|GPIO_AF6 |GPIO_PORTC|GPIO_PIN2)
#define GPIO_DFSDM_CKOUT_2 (GPIO_ALT|GPIO_AF6 |GPIO_PORTE|GPIO_PIN9)
/* Flexible Static Memory Controller (FSMC) */
#define GPIO_FMC_NL (GPIO_ALT|GPIO_AF12|GPIO_PORTB|GPIO_PIN7)
#define GPIO_FMC_NBL0 (GPIO_ALT|GPIO_AF12|GPIO_PORTE|GPIO_PIN0)
#define GPIO_FMC_NBL1 (GPIO_ALT|GPIO_AF12|GPIO_PORTE|GPIO_PIN1)
#define GPIO_FMC_CLK (GPIO_ALT|GPIO_AF12|GPIO_PORTD|GPIO_PIN3)
#define GPIO_FMC_NOE (GPIO_ALT|GPIO_AF12|GPIO_PORTD|GPIO_PIN4)
#define GPIO_FMC_NWE (GPIO_ALT|GPIO_AF12|GPIO_PORTD|GPIO_PIN5)
#define GPIO_FMC_NWAIT (GPIO_ALT|GPIO_AF12|GPIO_PORTD|GPIO_PIN6)
#define GPIO_FMC_NE1 (GPIO_ALT|GPIO_AF12|GPIO_PORTD|GPIO_PIN7)
#define GPIO_FMC_NE2 (GPIO_ALT|GPIO_AF12|GPIO_PORTG|GPIO_PIN9)
#define GPIO_FMC_NE3 (GPIO_ALT|GPIO_AF12|GPIO_PORTG|GPIO_PIN10)
#define GPIO_FMC_NE4 (GPIO_ALT|GPIO_AF12|GPIO_PORTG|GPIO_PIN12)
#define GPIO_FMC_INT3 (GPIO_ALT|GPIO_AF12|GPIO_PORTG|GPIO_PIN7)
#define GPIO_FMC_NCE3 (GPIO_ALT|GPIO_AF12|GPIO_PORTG|GPIO_PIN9)
#define GPIO_FMC_A0 (GPIO_ALT|GPIO_AF12|GPIO_PORTF|GPIO_PIN0)
#define GPIO_FMC_A1 (GPIO_ALT|GPIO_AF12|GPIO_PORTF|GPIO_PIN1)
#define GPIO_FMC_A2 (GPIO_ALT|GPIO_AF12|GPIO_PORTF|GPIO_PIN2)
#define GPIO_FMC_A3 (GPIO_ALT|GPIO_AF12|GPIO_PORTF|GPIO_PIN3)
#define GPIO_FMC_A4 (GPIO_ALT|GPIO_AF12|GPIO_PORTF|GPIO_PIN4)
#define GPIO_FMC_A5 (GPIO_ALT|GPIO_AF12|GPIO_PORTF|GPIO_PIN5)
#define GPIO_FMC_A6 (GPIO_ALT|GPIO_AF12|GPIO_PORTF|GPIO_PIN12)
#define GPIO_FMC_A7 (GPIO_ALT|GPIO_AF12|GPIO_PORTF|GPIO_PIN13)
#define GPIO_FMC_A8 (GPIO_ALT|GPIO_AF12|GPIO_PORTF|GPIO_PIN14)
#define GPIO_FMC_A9 (GPIO_ALT|GPIO_AF12|GPIO_PORTF|GPIO_PIN15)
#define GPIO_FMC_A10 (GPIO_ALT|GPIO_AF12|GPIO_PORTG|GPIO_PIN0)
#define GPIO_FMC_A11 (GPIO_ALT|GPIO_AF12|GPIO_PORTG|GPIO_PIN1)
#define GPIO_FMC_A12 (GPIO_ALT|GPIO_AF12|GPIO_PORTG|GPIO_PIN2)
#define GPIO_FMC_A13 (GPIO_ALT|GPIO_AF12|GPIO_PORTG|GPIO_PIN3)
#define GPIO_FMC_A14 (GPIO_ALT|GPIO_AF12|GPIO_PORTG|GPIO_PIN4)
#define GPIO_FMC_A15 (GPIO_ALT|GPIO_AF12|GPIO_PORTG|GPIO_PIN5)
#define GPIO_FMC_A16 (GPIO_ALT|GPIO_AF12|GPIO_PORTD|GPIO_PIN11)
#define GPIO_FMC_A17 (GPIO_ALT|GPIO_AF12|GPIO_PORTD|GPIO_PIN12)
#define GPIO_FMC_A18 (GPIO_ALT|GPIO_AF12|GPIO_PORTD|GPIO_PIN13)
#define GPIO_FMC_A19 (GPIO_ALT|GPIO_AF12|GPIO_PORTE|GPIO_PIN3)
#define GPIO_FMC_A20 (GPIO_ALT|GPIO_AF12|GPIO_PORTE|GPIO_PIN4)
#define GPIO_FMC_A21 (GPIO_ALT|GPIO_AF12|GPIO_PORTE|GPIO_PIN5)
#define GPIO_FMC_A22 (GPIO_ALT|GPIO_AF12|GPIO_PORTE|GPIO_PIN6)
#define GPIO_FMC_A23 (GPIO_ALT|GPIO_AF12|GPIO_PORTE|GPIO_PIN2)
#define GPIO_FMC_A24 (GPIO_ALT|GPIO_AF12|GPIO_PORTG|GPIO_PIN13)
#define GPIO_FMC_A25 (GPIO_ALT|GPIO_AF12|GPIO_PORTG|GPIO_PIN14)
#define GPIO_FMC_D0 (GPIO_ALT|GPIO_AF12|GPIO_PORTD|GPIO_PIN14)
#define GPIO_FMC_D1 (GPIO_ALT|GPIO_AF12|GPIO_PORTD|GPIO_PIN15)
#define GPIO_FMC_D2 (GPIO_ALT|GPIO_AF12|GPIO_PORTD|GPIO_PIN0)
#define GPIO_FMC_D3 (GPIO_ALT|GPIO_AF12|GPIO_PORTD|GPIO_PIN1)
#define GPIO_FMC_D4 (GPIO_ALT|GPIO_AF12|GPIO_PORTE|GPIO_PIN7)
#define GPIO_FMC_D5 (GPIO_ALT|GPIO_AF12|GPIO_PORTE|GPIO_PIN8)
#define GPIO_FMC_D6 (GPIO_ALT|GPIO_AF12|GPIO_PORTE|GPIO_PIN9)
#define GPIO_FMC_D7 (GPIO_ALT|GPIO_AF12|GPIO_PORTE|GPIO_PIN10)
#define GPIO_FMC_D8 (GPIO_ALT|GPIO_AF12|GPIO_PORTE|GPIO_PIN11)
#define GPIO_FMC_D9 (GPIO_ALT|GPIO_AF12|GPIO_PORTE|GPIO_PIN12)
#define GPIO_FMC_D10 (GPIO_ALT|GPIO_AF12|GPIO_PORTE|GPIO_PIN13)
#define GPIO_FMC_D11 (GPIO_ALT|GPIO_AF12|GPIO_PORTE|GPIO_PIN14)
#define GPIO_FMC_D12 (GPIO_ALT|GPIO_AF12|GPIO_PORTE|GPIO_PIN15)
#define GPIO_FMC_D13 (GPIO_ALT|GPIO_AF12|GPIO_PORTD|GPIO_PIN8)
#define GPIO_FMC_D14 (GPIO_ALT|GPIO_AF12|GPIO_PORTD|GPIO_PIN9)
#define GPIO_FMC_D15 (GPIO_ALT|GPIO_AF12|GPIO_PORTD|GPIO_PIN10)
/* I2C */
/* Note: STM32L496xx/4A6xx devices have few additional mappings for
* I2C1-3 that are not defined here.
*/
#define GPIO_I2C1_SDA_1 (GPIO_ALT|GPIO_AF4 |GPIO_PORTB|GPIO_PIN7)
#define GPIO_I2C1_SDA_2 (GPIO_ALT|GPIO_AF4 |GPIO_PORTB|GPIO_PIN9)
#define GPIO_I2C1_SDA_3 (GPIO_ALT|GPIO_AF4 |GPIO_PORTG|GPIO_PIN13)
#define GPIO_I2C1_SCL_1 (GPIO_ALT|GPIO_AF4 |GPIO_PORTB|GPIO_PIN6)
#define GPIO_I2C1_SCL_2 (GPIO_ALT|GPIO_AF4 |GPIO_PORTB|GPIO_PIN8)
#define GPIO_I2C1_SCL_3 (GPIO_ALT|GPIO_AF4 |GPIO_PORTG|GPIO_PIN14)
#define GPIO_I2C1_SMBA_1 (GPIO_ALT|GPIO_AF4 |GPIO_PORTB|GPIO_PIN5)
#define GPIO_I2C1_SMBA_2 (GPIO_ALT|GPIO_AF4 |GPIO_PORTG|GPIO_PIN15)
#define GPIO_I2C2_SDA_1 (GPIO_ALT|GPIO_AF4 |GPIO_PORTB|GPIO_PIN11)
#define GPIO_I2C2_SDA_2 (GPIO_ALT|GPIO_AF4 |GPIO_PORTB|GPIO_PIN14)
#define GPIO_I2C2_SDA_3 (GPIO_ALT|GPIO_AF4 |GPIO_PORTF|GPIO_PIN0)
#define GPIO_I2C2_SCL_1 (GPIO_ALT|GPIO_AF4 |GPIO_PORTB|GPIO_PIN10)
#define GPIO_I2C2_SCL_2 (GPIO_ALT|GPIO_AF4 |GPIO_PORTB|GPIO_PIN13)
#define GPIO_I2C2_SCL_3 (GPIO_ALT|GPIO_AF4 |GPIO_PORTF|GPIO_PIN1)
#define GPIO_I2C2_SMBA_1 (GPIO_ALT|GPIO_AF4 |GPIO_PORTB|GPIO_PIN12)
#define GPIO_I2C2_SMBA_2 (GPIO_ALT|GPIO_AF4 |GPIO_PORTF|GPIO_PIN2)
#define GPIO_I2C3_SDA_1 (GPIO_ALT|GPIO_AF4 |GPIO_PORTC|GPIO_PIN1)
#define GPIO_I2C3_SDA_2 (GPIO_ALT|GPIO_AF4 |GPIO_PORTG|GPIO_PIN8)
#define GPIO_I2C3_SCL_1 (GPIO_ALT|GPIO_AF4 |GPIO_PORTC|GPIO_PIN0)
#define GPIO_I2C3_SCL_2 (GPIO_ALT|GPIO_AF4 |GPIO_PORTG|GPIO_PIN7)
#define GPIO_I2C3_SMBA_1 (GPIO_ALT|GPIO_AF4 |GPIO_PORTB|GPIO_PIN2)
#define GPIO_I2C3_SMBA_2 (GPIO_ALT|GPIO_AF4 |GPIO_PORTG|GPIO_PIN6)
/* JTAG */
#define GPIO_JTCK_SWCLK (GPIO_ALT|GPIO_AF0|GPIO_PORTA|GPIO_PIN14)
#define GPIO_JTDI (GPIO_ALT|GPIO_AF0|GPIO_PORTA|GPIO_PIN15)
#define GPIO_JTDO (GPIO_ALT|GPIO_AF0|GPIO_PORTB|GPIO_PIN3)
#define GPIO_JTMS_SWDIO (GPIO_ALT|GPIO_AF0|GPIO_PORTA|GPIO_PIN13)
#define GPIO_JTRST (GPIO_ALT|GPIO_AF0|GPIO_PORTB|GPIO_PIN4)
/* OTG FS */
#define GPIO_OTGFS_SOF (GPIO_ALT|GPIO_AF10|GPIO_PORTA|GPIO_PIN8)
#define GPIO_OTGFS_ID (GPIO_ALT|GPIO_AF10|GPIO_PORTA|GPIO_PIN10)
#define GPIO_OTGFS_DM (GPIO_ALT|GPIO_AF10|GPIO_PORTA|GPIO_PIN11)
#define GPIO_OTGFS_DP (GPIO_ALT|GPIO_AF10|GPIO_PORTA|GPIO_PIN12)
#define GPIO_OTGFS_NOE_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTA|GPIO_PIN13)
#define GPIO_OTGFS_NOE_2 (GPIO_ALT|GPIO_AF10|GPIO_PORTC|GPIO_PIN9)
/* QUADSPI */
#define GPIO_QSPI_NCS_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTB|GPIO_PIN11)
#define GPIO_QSPI_NCS_2 (GPIO_ALT|GPIO_AF10|GPIO_PORTE|GPIO_PIN11)
#define GPIO_QSPI_CLK_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTB|GPIO_PIN10)
#define GPIO_QSPI_CLK_2 (GPIO_ALT|GPIO_AF10|GPIO_PORTE|GPIO_PIN10)
#define GPIO_QSPI_BK1_IO0_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTB|GPIO_PIN1)
#define GPIO_QSPI_BK1_IO0_2 (GPIO_ALT|GPIO_AF10|GPIO_PORTE|GPIO_PIN12)
#define GPIO_QSPI_BK1_IO1_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTB|GPIO_PIN0)
#define GPIO_QSPI_BK1_IO1_2 (GPIO_ALT|GPIO_AF10|GPIO_PORTE|GPIO_PIN13)
#define GPIO_QSPI_BK1_IO2_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTA|GPIO_PIN7)
#define GPIO_QSPI_BK1_IO2_2 (GPIO_ALT|GPIO_AF10|GPIO_PORTE|GPIO_PIN14)
#define GPIO_QSPI_BK1_IO3_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTA|GPIO_PIN6)
#define GPIO_QSPI_BK1_IO3_2 (GPIO_ALT|GPIO_AF10|GPIO_PORTE|GPIO_PIN15)
/* RTC */
#define GPIO_RTC_OUT (GPIO_ALT|GPIO_AF0 |GPIO_PORTB|GPIO_PIN2)
#define GPIO_RTC_REFIN (GPIO_ALT|GPIO_AF0 |GPIO_PORTB|GPIO_PIN15)
/* SAI */
#define GPIO_SAI1_EXTCLK (GPIO_ALT|GPIO_AF13|GPIO_PORTA|GPIO_PIN0)
#define GPIO_SAI1_FS_A_1 (GPIO_ALT|GPIO_AF13|GPIO_PORTB|GPIO_PIN9)
#define GPIO_SAI1_FS_A_2 (GPIO_ALT|GPIO_AF13|GPIO_PORTE|GPIO_PIN4)
#define GPIO_SAI1_SCK_A_1 (GPIO_ALT|GPIO_AF13|GPIO_PORTB|GPIO_PIN10)
#define GPIO_SAI1_SCK_A_2 (GPIO_ALT|GPIO_AF13|GPIO_PORTE|GPIO_PIN5)
#define GPIO_SAI1_SD_A_1 (GPIO_ALT|GPIO_AF13|GPIO_PORTC|GPIO_PIN3)
#define GPIO_SAI1_SD_A_2 (GPIO_ALT|GPIO_AF13|GPIO_PORTD|GPIO_PIN6)
#define GPIO_SAI1_SD_A_3 (GPIO_ALT|GPIO_AF13|GPIO_PORTE|GPIO_PIN6)
#define GPIO_SAI1_MCLK_A_1 (GPIO_ALT|GPIO_AF13|GPIO_PORTB|GPIO_PIN8)
#define GPIO_SAI1_MCLK_A_2 (GPIO_ALT|GPIO_AF13|GPIO_PORTE|GPIO_PIN2)
#define GPIO_SAI1_FS_B_1 (GPIO_ALT|GPIO_AF13|GPIO_PORTA|GPIO_PIN4)
#define GPIO_SAI1_FS_B_2 (GPIO_ALT|GPIO_AF13|GPIO_PORTB|GPIO_PIN6)
#define GPIO_SAI1_FS_B_3 (GPIO_ALT|GPIO_AF13|GPIO_PORTF|GPIO_PIN9)
#define GPIO_SAI1_FS_B_4 (GPIO_ALT|GPIO_AF13|GPIO_PORTE|GPIO_PIN9)
#define GPIO_SAI1_SCK_B_1 (GPIO_ALT|GPIO_AF13|GPIO_PORTB|GPIO_PIN3)
#define GPIO_SAI1_SCK_B_2 (GPIO_ALT|GPIO_AF13|GPIO_PORTE|GPIO_PIN8)
#define GPIO_SAI1_SCK_B_3 (GPIO_ALT|GPIO_AF13|GPIO_PORTF|GPIO_PIN8)
#define GPIO_SAI1_SD_B_1 (GPIO_ALT|GPIO_AF13|GPIO_PORTB|GPIO_PIN5)
#define GPIO_SAI1_SD_B_2 (GPIO_ALT|GPIO_AF13|GPIO_PORTE|GPIO_PIN3)
#define GPIO_SAI1_SD_B_3 (GPIO_ALT|GPIO_AF13|GPIO_PORTE|GPIO_PIN7)
#define GPIO_SAI1_SD_B_4 (GPIO_ALT|GPIO_AF13|GPIO_PORTF|GPIO_PIN6)
#define GPIO_SAI1_MCLK_B_1 (GPIO_ALT|GPIO_AF13|GPIO_PORTB|GPIO_PIN4)
#define GPIO_SAI1_MCLK_B_2 (GPIO_ALT|GPIO_AF13|GPIO_PORTE|GPIO_PIN10)
#define GPIO_SAI1_MCLK_B_3 (GPIO_ALT|GPIO_AF13|GPIO_PORTF|GPIO_PIN7)
#define GPIO_SAI2_EXTCLK_1 (GPIO_ALT|GPIO_AF13|GPIO_PORTA|GPIO_PIN2)
#define GPIO_SAI2_EXTCLK_2 (GPIO_ALT|GPIO_AF13|GPIO_PORTC|GPIO_PIN9)
#define GPIO_SAI2_FS_A_1 (GPIO_ALT|GPIO_AF13|GPIO_PORTB|GPIO_PIN12)
#define GPIO_SAI2_FS_A_2 (GPIO_ALT|GPIO_AF13|GPIO_PORTD|GPIO_PIN12)
#define GPIO_SAI2_FS_A_3 (GPIO_ALT|GPIO_AF13|GPIO_PORTG|GPIO_PIN10)
#define GPIO_SAI2_SCK_A_1 (GPIO_ALT|GPIO_AF13|GPIO_PORTB|GPIO_PIN13)
#define GPIO_SAI2_SCK_A_2 (GPIO_ALT|GPIO_AF13|GPIO_PORTD|GPIO_PIN10)
#define GPIO_SAI2_SCK_A_3 (GPIO_ALT|GPIO_AF13|GPIO_PORTG|GPIO_PIN9)
#define GPIO_SAI2_SD_A_1 (GPIO_ALT|GPIO_AF13|GPIO_PORTB|GPIO_PIN15)
#define GPIO_SAI2_SD_A_2 (GPIO_ALT|GPIO_AF13|GPIO_PORTD|GPIO_PIN11)
#define GPIO_SAI2_SD_A_3 (GPIO_ALT|GPIO_AF13|GPIO_PORTG|GPIO_PIN12)
#define GPIO_SAI2_MCLK_A_1 (GPIO_ALT|GPIO_AF13|GPIO_PORTB|GPIO_PIN14)
#define GPIO_SAI2_MCLK_A_2 (GPIO_ALT|GPIO_AF13|GPIO_PORTC|GPIO_PIN6)
#define GPIO_SAI2_MCLK_A_3 (GPIO_ALT|GPIO_AF13|GPIO_PORTD|GPIO_PIN9)
#define GPIO_SAI2_MCLK_A_4 (GPIO_ALT|GPIO_AF13|GPIO_PORTG|GPIO_PIN11)
#define GPIO_SAI2_FS_B_1 (GPIO_ALT|GPIO_AF13|GPIO_PORTA|GPIO_PIN15)
#define GPIO_SAI2_FS_B_2 (GPIO_ALT|GPIO_AF13|GPIO_PORTG|GPIO_PIN3)
#define GPIO_SAI2_SCK_B_1 (GPIO_ALT|GPIO_AF13|GPIO_PORTC|GPIO_PIN10)
#define GPIO_SAI2_SCK_B_2 (GPIO_ALT|GPIO_AF13|GPIO_PORTG|GPIO_PIN2)
#define GPIO_SAI2_SD_B_1 (GPIO_ALT|GPIO_AF13|GPIO_PORTC|GPIO_PIN12)
#define GPIO_SAI2_SD_B_2 (GPIO_ALT|GPIO_AF13|GPIO_PORTG|GPIO_PIN5)
#define GPIO_SAI2_MCLK_B_1 (GPIO_ALT|GPIO_AF13|GPIO_PORTC|GPIO_PIN7)
#define GPIO_SAI2_MCLK_B_2 (GPIO_ALT|GPIO_AF13|GPIO_PORTC|GPIO_PIN11)
#define GPIO_SAI2_MCLK_B_3 (GPIO_ALT|GPIO_AF13|GPIO_PORTG|GPIO_PIN4)
/* SDIO */
#define GPIO_SDMMC1_CK (GPIO_ALT|GPIO_AF12|GPIO_PORTC|GPIO_PIN12)
#define GPIO_SDMMC1_CMD (GPIO_ALT|GPIO_AF12|GPIO_PORTD|GPIO_PIN2)
#define GPIO_SDMMC1_D0 (GPIO_ALT|GPIO_AF12|GPIO_PORTC|GPIO_PIN8)
#define GPIO_SDMMC1_D1 (GPIO_ALT|GPIO_AF12|GPIO_PORTC|GPIO_PIN9)
#define GPIO_SDMMC1_D2 (GPIO_ALT|GPIO_AF12|GPIO_PORTC|GPIO_PIN10)
#define GPIO_SDMMC1_D3 (GPIO_ALT|GPIO_AF12|GPIO_PORTC|GPIO_PIN11)
#define GPIO_SDMMC1_D4 (GPIO_ALT|GPIO_AF12|GPIO_PORTB|GPIO_PIN8)
#define GPIO_SDMMC1_D5 (GPIO_ALT|GPIO_AF12|GPIO_PORTB|GPIO_PIN9)
#define GPIO_SDMMC1_D6 (GPIO_ALT|GPIO_AF12|GPIO_PORTC|GPIO_PIN6)
#define GPIO_SDMMC1_D7 (GPIO_ALT|GPIO_AF12|GPIO_PORTC|GPIO_PIN7)
/* Single Wire Protocol Interface */
#define GPIO_SWPMI1_IO (GPIO_ALT|GPIO_AF12|GPIO_PORTB|GPIO_PIN12)
#define GPIO_SWPMI1_TX (GPIO_ALT|GPIO_AF12|GPIO_PORTB|GPIO_PIN13)
#define GPIO_SWPMI1_RX (GPIO_ALT|GPIO_AF12|GPIO_PORTB|GPIO_PIN14)
#define GPIO_SWPMI1_SUSPEND (GPIO_ALT|GPIO_AF12|GPIO_PORTB|GPIO_PIN15)
/* SPI */
#define GPIO_SPI1_NSS_1 (GPIO_ALT|GPIO_AF5 |GPIO_PORTA|GPIO_PIN4)
#define GPIO_SPI1_NSS_2 (GPIO_ALT|GPIO_AF5 |GPIO_PORTA|GPIO_PIN15)
#define GPIO_SPI1_NSS_3 (GPIO_ALT|GPIO_AF5 |GPIO_PORTE|GPIO_PIN12)
#define GPIO_SPI1_NSS_4 (GPIO_ALT|GPIO_AF5 |GPIO_PORTG|GPIO_PIN5)
#define GPIO_SPI1_SCK_1 (GPIO_ALT|GPIO_AF5 |GPIO_PORTA|GPIO_PIN5)
#define GPIO_SPI1_SCK_2 (GPIO_ALT|GPIO_AF5 |GPIO_PORTB|GPIO_PIN3)
#define GPIO_SPI1_SCK_3 (GPIO_ALT|GPIO_AF5 |GPIO_PORTE|GPIO_PIN13)
#define GPIO_SPI1_SCK_4 (GPIO_ALT|GPIO_AF5 |GPIO_PORTG|GPIO_PIN2)
#define GPIO_SPI1_MOSI_1 (GPIO_ALT|GPIO_AF5 |GPIO_PORTA|GPIO_PIN7)
#define GPIO_SPI1_MOSI_2 (GPIO_ALT|GPIO_AF5 |GPIO_PORTB|GPIO_PIN5)
#define GPIO_SPI1_MOSI_3 (GPIO_ALT|GPIO_AF5 |GPIO_PORTE|GPIO_PIN15)
#define GPIO_SPI1_MOSI_4 (GPIO_ALT|GPIO_AF5 |GPIO_PORTG|GPIO_PIN4)
#define GPIO_SPI1_MISO_1 (GPIO_ALT|GPIO_AF5 |GPIO_PORTA|GPIO_PIN6)
#define GPIO_SPI1_MISO_2 (GPIO_ALT|GPIO_AF5 |GPIO_PORTB|GPIO_PIN4)
#define GPIO_SPI1_MISO_3 (GPIO_ALT|GPIO_AF5 |GPIO_PORTE|GPIO_PIN14)
#define GPIO_SPI1_MISO_4 (GPIO_ALT|GPIO_AF5 |GPIO_PORTG|GPIO_PIN3)
#define GPIO_SPI2_NSS_1 (GPIO_ALT|GPIO_AF5 |GPIO_PORTB|GPIO_PIN9)
#define GPIO_SPI2_NSS_2 (GPIO_ALT|GPIO_AF5 |GPIO_PORTB|GPIO_PIN12)
#define GPIO_SPI2_NSS_3 (GPIO_ALT|GPIO_AF5 |GPIO_PORTD|GPIO_PIN0)
#define GPIO_SPI2_SCK_1 (GPIO_ALT|GPIO_AF5 |GPIO_PORTB|GPIO_PIN10)
#define GPIO_SPI2_SCK_2 (GPIO_ALT|GPIO_AF5 |GPIO_PORTB|GPIO_PIN13)
#define GPIO_SPI2_SCK_3 (GPIO_ALT|GPIO_AF5 |GPIO_PORTD|GPIO_PIN1)
#define GPIO_SPI2_MOSI_1 (GPIO_ALT|GPIO_AF5 |GPIO_PORTB|GPIO_PIN15)
#define GPIO_SPI2_MOSI_2 (GPIO_ALT|GPIO_AF5 |GPIO_PORTC|GPIO_PIN3)
#define GPIO_SPI2_MOSI_3 (GPIO_ALT|GPIO_AF5 |GPIO_PORTD|GPIO_PIN4)
#define GPIO_SPI2_MISO_1 (GPIO_ALT|GPIO_AF5 |GPIO_PORTB|GPIO_PIN14)
#define GPIO_SPI2_MISO_2 (GPIO_ALT|GPIO_AF5 |GPIO_PORTC|GPIO_PIN2)
#define GPIO_SPI2_MISO_3 (GPIO_ALT|GPIO_AF5 |GPIO_PORTD|GPIO_PIN3)
#define GPIO_SPI3_NSS_1 (GPIO_ALT|GPIO_AF6 |GPIO_PORTA|GPIO_PIN4)
#define GPIO_SPI3_NSS_2 (GPIO_ALT|GPIO_AF6 |GPIO_PORTA|GPIO_PIN15)
#define GPIO_SPI3_NSS_3 (GPIO_ALT|GPIO_AF6 |GPIO_PORTG|GPIO_PIN12)
#define GPIO_SPI3_SCK_1 (GPIO_ALT|GPIO_AF6 |GPIO_PORTB|GPIO_PIN3)
#define GPIO_SPI3_SCK_2 (GPIO_ALT|GPIO_AF6 |GPIO_PORTC|GPIO_PIN10)
#define GPIO_SPI3_SCK_3 (GPIO_ALT|GPIO_AF6 |GPIO_PORTG|GPIO_PIN9)
#define GPIO_SPI3_MOSI_1 (GPIO_ALT|GPIO_AF6 |GPIO_PORTB|GPIO_PIN5)
#define GPIO_SPI3_MOSI_2 (GPIO_ALT|GPIO_AF6 |GPIO_PORTC|GPIO_PIN12)
#define GPIO_SPI3_MOSI_3 (GPIO_ALT|GPIO_AF6 |GPIO_PORTG|GPIO_PIN11)
#define GPIO_SPI3_MISO_1 (GPIO_ALT|GPIO_AF6 |GPIO_PORTB|GPIO_PIN4)
#define GPIO_SPI3_MISO_2 (GPIO_ALT|GPIO_AF6 |GPIO_PORTC|GPIO_PIN11)
#define GPIO_SPI3_MISO_3 (GPIO_ALT|GPIO_AF6 |GPIO_PORTG|GPIO_PIN10)
/* Timers */
#define GPIO_TIM1_CH1IN_1 (GPIO_ALT|GPIO_AF1 |GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN8)
#define GPIO_TIM1_CH1IN_2 (GPIO_ALT|GPIO_AF1 |GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTE|GPIO_PIN9)
#define GPIO_TIM1_CH1OUT_1 (GPIO_ALT|GPIO_AF1 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN8)
#define GPIO_TIM1_CH1OUT_2 (GPIO_ALT|GPIO_AF1 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN9)
#define GPIO_TIM1_CH2IN_1 (GPIO_ALT|GPIO_AF1 |GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN9)
#define GPIO_TIM1_CH2IN_2 (GPIO_ALT|GPIO_AF1 |GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTE|GPIO_PIN11)
#define GPIO_TIM1_CH2OUT_1 (GPIO_ALT|GPIO_AF1 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN9)
#define GPIO_TIM1_CH2OUT_2 (GPIO_ALT|GPIO_AF1 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN11)
#define GPIO_TIM1_CH3IN_1 (GPIO_ALT|GPIO_AF1 |GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN10)
#define GPIO_TIM1_CH3IN_2 (GPIO_ALT|GPIO_AF1 |GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTE|GPIO_PIN13)
#define GPIO_TIM1_CH3OUT_1 (GPIO_ALT|GPIO_AF1 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN10)
#define GPIO_TIM1_CH3OUT_2 (GPIO_ALT|GPIO_AF1 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN13)
#define GPIO_TIM1_CH4IN_1 (GPIO_ALT|GPIO_AF1 |GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN11)
#define GPIO_TIM1_CH4IN_2 (GPIO_ALT|GPIO_AF1 |GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTE|GPIO_PIN14)
#define GPIO_TIM1_CH4OUT_1 (GPIO_ALT|GPIO_AF1 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN11)
#define GPIO_TIM1_CH4OUT_2 (GPIO_ALT|GPIO_AF1 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN14)
#define GPIO_TIM1_CH1N_1 (GPIO_ALT|GPIO_AF1 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN7)
#define GPIO_TIM1_CH1N_2 (GPIO_ALT|GPIO_AF1 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN13)
#define GPIO_TIM1_CH1N_3 (GPIO_ALT|GPIO_AF1 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN8)
#define GPIO_TIM1_CH2N_1 (GPIO_ALT|GPIO_AF1 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN0)
#define GPIO_TIM1_CH2N_2 (GPIO_ALT|GPIO_AF1 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN14)
#define GPIO_TIM1_CH2N_3 (GPIO_ALT|GPIO_AF1 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN10)
#define GPIO_TIM1_CH3N_1 (GPIO_ALT|GPIO_AF1 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN1)
#define GPIO_TIM1_CH3N_2 (GPIO_ALT|GPIO_AF1 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN15)
#define GPIO_TIM1_CH3N_3 (GPIO_ALT|GPIO_AF1 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN12)
#define GPIO_TIM1_BKIN_1 (GPIO_ALT|GPIO_AF1 |GPIO_PORTA|GPIO_PIN6)
#define GPIO_TIM1_BKIN_2 (GPIO_ALT|GPIO_AF1 |GPIO_PORTB|GPIO_PIN12)
#define GPIO_TIM1_BKIN_3 (GPIO_ALT|GPIO_AF1 |GPIO_PORTE|GPIO_PIN15)
#define GPIO_TIM1_BKIN_COMP1 (GPIO_ALT|GPIO_AF3 |GPIO_PORTE|GPIO_PIN15)
#define GPIO_TIM1_BKIN_COMP2_1 (GPIO_ALT|GPIO_AF12|GPIO_PORTA|GPIO_PIN6)
#define GPIO_TIM1_BKIN_COMP2_2 (GPIO_ALT|GPIO_AF3 |GPIO_PORTB|GPIO_PIN12)
#define GPIO_TIM1_BKIN2 (GPIO_ALT|GPIO_AF2 |GPIO_PORTA|GPIO_PIN11)
#define GPIO_TIM1_BKIN2_COMP1 (GPIO_ALT|GPIO_AF12|GPIO_PORTA|GPIO_PIN11)
#define GPIO_TIM1_BKIN2_COMP2 (GPIO_ALT|GPIO_AF3 |GPIO_PORTE|GPIO_PIN14)
#define GPIO_TIM1_ETR_1 (GPIO_ALT|GPIO_AF1 |GPIO_PORTA|GPIO_PIN12)
#define GPIO_TIM1_ETR_2 (GPIO_ALT|GPIO_AF1 |GPIO_PORTE|GPIO_PIN7)
#define GPIO_TIM2_CH1IN_1 (GPIO_ALT|GPIO_AF1 |GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN0)
#define GPIO_TIM2_CH1IN_2 (GPIO_ALT|GPIO_AF1 |GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN5)
#define GPIO_TIM2_CH1IN_3 (GPIO_ALT|GPIO_AF1 |GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN15)
#define GPIO_TIM2_CH1OUT_1 (GPIO_ALT|GPIO_AF1 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN0)
#define GPIO_TIM2_CH1OUT_2 (GPIO_ALT|GPIO_AF1 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN5)
#define GPIO_TIM2_CH1OUT_3 (GPIO_ALT|GPIO_AF1 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN15)
#define GPIO_TIM2_CH2IN_1 (GPIO_ALT|GPIO_AF1 |GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN1)
#define GPIO_TIM2_CH2IN_2 (GPIO_ALT|GPIO_AF1 |GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN3)
#define GPIO_TIM2_CH2OUT_1 (GPIO_ALT|GPIO_AF1 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN1)
#define GPIO_TIM2_CH2OUT_2 (GPIO_ALT|GPIO_AF1 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN3)
#define GPIO_TIM2_CH3IN_1 (GPIO_ALT|GPIO_AF1 |GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN2)
#define GPIO_TIM2_CH3IN_2 (GPIO_ALT|GPIO_AF1 |GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN10)
#define GPIO_TIM2_CH3OUT_1 (GPIO_ALT|GPIO_AF1 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN2)
#define GPIO_TIM2_CH3OUT_2 (GPIO_ALT|GPIO_AF1 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN10)
#define GPIO_TIM2_CH4IN_1 (GPIO_ALT|GPIO_AF1 |GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN3)
#define GPIO_TIM2_CH4IN_2 (GPIO_ALT|GPIO_AF1 |GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN11)
#define GPIO_TIM2_CH4OUT_1 (GPIO_ALT|GPIO_AF1 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN3)
#define GPIO_TIM2_CH4OUT_2 (GPIO_ALT|GPIO_AF1 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN11)
#define GPIO_TIM2_BKIN (GPIO_ALT|GPIO_AF2 |GPIO_PORTE|GPIO_PIN14)
#define GPIO_TIM2_ETR_1 (GPIO_ALT|GPIO_AF14|GPIO_PORTA|GPIO_PIN0)
#define GPIO_TIM2_ETR_2 (GPIO_ALT|GPIO_AF2 |GPIO_PORTA|GPIO_PIN5)
#define GPIO_TIM2_ETR_3 (GPIO_ALT|GPIO_AF2 |GPIO_PORTA|GPIO_PIN15)
#define GPIO_TIM3_CH1IN_1 (GPIO_ALT|GPIO_AF2 |GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN6)
#define GPIO_TIM3_CH1IN_2 (GPIO_ALT|GPIO_AF2 |GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN4)
#define GPIO_TIM3_CH1IN_3 (GPIO_ALT|GPIO_AF2 |GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTC|GPIO_PIN6)
#define GPIO_TIM3_CH1IN_4 (GPIO_ALT|GPIO_AF2 |GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTE|GPIO_PIN3)
#define GPIO_TIM3_CH1OUT_1 (GPIO_ALT|GPIO_AF2 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN6)
#define GPIO_TIM3_CH1OUT_2 (GPIO_ALT|GPIO_AF2 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN4)
#define GPIO_TIM3_CH1OUT_3 (GPIO_ALT|GPIO_AF2 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN6)
#define GPIO_TIM3_CH1OUT_4 (GPIO_ALT|GPIO_AF2 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN3)
#define GPIO_TIM3_CH2IN_1 (GPIO_ALT|GPIO_AF2 |GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN7)
#define GPIO_TIM3_CH2IN_2 (GPIO_ALT|GPIO_AF2 |GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN5)
#define GPIO_TIM3_CH2IN_3 (GPIO_ALT|GPIO_AF2 |GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTC|GPIO_PIN7)
#define GPIO_TIM3_CH2IN_4 (GPIO_ALT|GPIO_AF2 |GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTE|GPIO_PIN4)
#define GPIO_TIM3_CH2OUT_1 (GPIO_ALT|GPIO_AF2 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN7)
#define GPIO_TIM3_CH2OUT_2 (GPIO_ALT|GPIO_AF2 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN5)
#define GPIO_TIM3_CH2OUT_3 (GPIO_ALT|GPIO_AF2 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN7)
#define GPIO_TIM3_CH2OUT_4 (GPIO_ALT|GPIO_AF2 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN4)
#define GPIO_TIM3_CH3IN_1 (GPIO_ALT|GPIO_AF2 |GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN0)
#define GPIO_TIM3_CH3IN_2 (GPIO_ALT|GPIO_AF2 |GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTC|GPIO_PIN8)
#define GPIO_TIM3_CH3IN_3 (GPIO_ALT|GPIO_AF2 |GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTE|GPIO_PIN5)
#define GPIO_TIM3_CH3OUT_1 (GPIO_ALT|GPIO_AF2 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN0)
#define GPIO_TIM3_CH3OUT_2 (GPIO_ALT|GPIO_AF2 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN8)
#define GPIO_TIM3_CH3OUT_3 (GPIO_ALT|GPIO_AF2 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN5)
#define GPIO_TIM3_CH4IN_1 (GPIO_ALT|GPIO_AF2 |GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN1)
#define GPIO_TIM3_CH4IN_2 (GPIO_ALT|GPIO_AF2 |GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTC|GPIO_PIN9)
#define GPIO_TIM3_CH4IN_3 (GPIO_ALT|GPIO_AF2 |GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTE|GPIO_PIN6)
#define GPIO_TIM3_CH4OUT_1 (GPIO_ALT|GPIO_AF2 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN1)
#define GPIO_TIM3_CH4OUT_2 (GPIO_ALT|GPIO_AF2 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN9)
#define GPIO_TIM3_CH4OUT_3 (GPIO_ALT|GPIO_AF2 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN6)
#define GPIO_TIM3_ETR_1 (GPIO_ALT|GPIO_AF2 |GPIO_PORTD|GPIO_PIN2)
#define GPIO_TIM3_ETR_2 (GPIO_ALT|GPIO_AF2 |GPIO_PORTE|GPIO_PIN2)
#define GPIO_TIM4_CH1IN_1 (GPIO_ALT|GPIO_AF2 |GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN6)
#define GPIO_TIM4_CH1IN_2 (GPIO_ALT|GPIO_AF2 |GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTD|GPIO_PIN12)
#define GPIO_TIM4_CH1OUT_1 (GPIO_ALT|GPIO_AF2 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN6)
#define GPIO_TIM4_CH1OUT_2 (GPIO_ALT|GPIO_AF2 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN12)
#define GPIO_TIM4_CH2IN_1 (GPIO_ALT|GPIO_AF2 |GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN7)
#define GPIO_TIM4_CH2IN_2 (GPIO_ALT|GPIO_AF2 |GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTD|GPIO_PIN13)
#define GPIO_TIM4_CH2OUT_1 (GPIO_ALT|GPIO_AF2 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN7)
#define GPIO_TIM4_CH2OUT_2 (GPIO_ALT|GPIO_AF2 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN13)
#define GPIO_TIM4_CH3IN_1 (GPIO_ALT|GPIO_AF2 |GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN8)
#define GPIO_TIM4_CH3IN_2 (GPIO_ALT|GPIO_AF2 |GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTD|GPIO_PIN14)
#define GPIO_TIM4_CH3OUT_1 (GPIO_ALT|GPIO_AF2 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN8)
#define GPIO_TIM4_CH3OUT_2 (GPIO_ALT|GPIO_AF2 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN14)
#define GPIO_TIM4_CH4IN_1 (GPIO_ALT|GPIO_AF2 |GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN9)
#define GPIO_TIM4_CH4IN_2 (GPIO_ALT|GPIO_AF2 |GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTD|GPIO_PIN15)
#define GPIO_TIM4_CH4OUT_1 (GPIO_ALT|GPIO_AF2 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN9)
#define GPIO_TIM4_CH4OUT_2 (GPIO_ALT|GPIO_AF2 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN15)
#define GPIO_TIM4_ETR (GPIO_ALT|GPIO_AF2 |GPIO_PORTE|GPIO_PIN0)
#define GPIO_TIM5_CH1IN_1 (GPIO_ALT|GPIO_AF2 |GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN0)
#define GPIO_TIM5_CH1IN_2 (GPIO_ALT|GPIO_AF2 |GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTF|GPIO_PIN6)
#define GPIO_TIM5_CH1OUT_1 (GPIO_ALT|GPIO_AF2 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN0)
#define GPIO_TIM5_CH1OUT_2 (GPIO_ALT|GPIO_AF2 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTF|GPIO_PIN6)
#define GPIO_TIM5_CH2IN_1 (GPIO_ALT|GPIO_AF2 |GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN1)
#define GPIO_TIM5_CH2IN_2 (GPIO_ALT|GPIO_AF2 |GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTF|GPIO_PIN7)
#define GPIO_TIM5_CH2OUT_1 (GPIO_ALT|GPIO_AF2 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN1)
#define GPIO_TIM5_CH2OUT_2 (GPIO_ALT|GPIO_AF2 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTF|GPIO_PIN7)
#define GPIO_TIM5_CH3IN_1 (GPIO_ALT|GPIO_AF2 |GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN2)
#define GPIO_TIM5_CH3IN_2 (GPIO_ALT|GPIO_AF2 |GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTF|GPIO_PIN8)
#define GPIO_TIM5_CH3OUT_1 (GPIO_ALT|GPIO_AF2 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN2)
#define GPIO_TIM5_CH3OUT_2 (GPIO_ALT|GPIO_AF2 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTF|GPIO_PIN8)
#define GPIO_TIM5_CH4IN_1 (GPIO_ALT|GPIO_AF2 |GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN3)
#define GPIO_TIM5_CH4IN_2 (GPIO_ALT|GPIO_AF2 |GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTF|GPIO_PIN9)
#define GPIO_TIM5_CH4OUT_1 (GPIO_ALT|GPIO_AF2 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN3)
#define GPIO_TIM5_CH4OUT_2 (GPIO_ALT|GPIO_AF2 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTF|GPIO_PIN9)
#define GPIO_TIM5_ETR (GPIO_ALT|GPIO_AF1 |GPIO_PORTF|GPIO_PIN6)
#define GPIO_TIM8_CH1IN (GPIO_ALT|GPIO_AF3 |GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTC|GPIO_PIN6)
#define GPIO_TIM8_CH1OUT (GPIO_ALT|GPIO_AF3 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN6)
#define GPIO_TIM8_CH2IN (GPIO_ALT|GPIO_AF3 |GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTC|GPIO_PIN7)
#define GPIO_TIM8_CH2OUT (GPIO_ALT|GPIO_AF3 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN7)
#define GPIO_TIM8_CH3IN (GPIO_ALT|GPIO_AF3 |GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTC|GPIO_PIN8)
#define GPIO_TIM8_CH3OUT (GPIO_ALT|GPIO_AF3 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN8)
#define GPIO_TIM8_CH4IN (GPIO_ALT|GPIO_AF3 |GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTC|GPIO_PIN9)
#define GPIO_TIM8_CH4OUT (GPIO_ALT|GPIO_AF3 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN9)
#define GPIO_TIM8_CH1N_1 (GPIO_ALT|GPIO_AF3 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN5)
#define GPIO_TIM8_CH1N_2 (GPIO_ALT|GPIO_AF3 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN7)
#define GPIO_TIM8_CH2N_1 (GPIO_ALT|GPIO_AF3 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN0)
#define GPIO_TIM8_CH2N_2 (GPIO_ALT|GPIO_AF3 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN14)
#define GPIO_TIM8_CH3N_1 (GPIO_ALT|GPIO_AF3 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN1)
#define GPIO_TIM8_CH3N_2 (GPIO_ALT|GPIO_AF3 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN15)
#define GPIO_TIM8_BKIN_1 (GPIO_ALT|GPIO_AF3 |GPIO_PORTA|GPIO_PIN6)
#define GPIO_TIM8_BKIN_2 (GPIO_ALT|GPIO_AF3 |GPIO_PORTB|GPIO_PIN7)
#define GPIO_TIM8_BKIN_COMP1 (GPIO_ALT|GPIO_AF13|GPIO_PORTB|GPIO_PIN7)
#define GPIO_TIM8_BKIN_COMP2 (GPIO_ALT|GPIO_AF13|GPIO_PORTA|GPIO_PIN6)
#define GPIO_TIM8_BKIN2_1 (GPIO_ALT|GPIO_AF3 |GPIO_PORTB|GPIO_PIN6)
#define GPIO_TIM8_BKIN2_2 (GPIO_ALT|GPIO_AF1 |GPIO_PORTC|GPIO_PIN9)
#define GPIO_TIM8_BKIN2_COMP1 (GPIO_ALT|GPIO_AF14|GPIO_PORTC|GPIO_PIN9)
#define GPIO_TIM8_BKIN2_COMP2 (GPIO_ALT|GPIO_AF12|GPIO_PORTB|GPIO_PIN6)
#define GPIO_TIM8_ETR (GPIO_ALT|GPIO_AF3 |GPIO_PORTA|GPIO_PIN0)
#define GPIO_TIM15_CH1IN_1 (GPIO_ALT|GPIO_AF14|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN2)
#define GPIO_TIM15_CH1IN_2 (GPIO_ALT|GPIO_AF14|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN14)
#define GPIO_TIM15_CH1IN_3 (GPIO_ALT|GPIO_AF14|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTF|GPIO_PIN9)
#define GPIO_TIM15_CH1IN_4 (GPIO_ALT|GPIO_AF14|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTG|GPIO_PIN10)
#define GPIO_TIM15_CH1OUT_1 (GPIO_ALT|GPIO_AF14|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN2)
#define GPIO_TIM15_CH1OUT_2 (GPIO_ALT|GPIO_AF14|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN14)
#define GPIO_TIM15_CH1OUT_3 (GPIO_ALT|GPIO_AF14|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTF|GPIO_PIN9)
#define GPIO_TIM15_CH1OUT_4 (GPIO_ALT|GPIO_AF14|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTG|GPIO_PIN10)
#define GPIO_TIM15_CH2IN_1 (GPIO_ALT|GPIO_AF14|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN3)
#define GPIO_TIM15_CH2IN_2 (GPIO_ALT|GPIO_AF14|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN15)
#define GPIO_TIM15_CH2IN_3 (GPIO_ALT|GPIO_AF14|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTF|GPIO_PIN10)
#define GPIO_TIM15_CH2IN_4 (GPIO_ALT|GPIO_AF14|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTG|GPIO_PIN11)
#define GPIO_TIM15_CH2OUT_1 (GPIO_ALT|GPIO_AF14|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN3)
#define GPIO_TIM15_CH2OUT_2 (GPIO_ALT|GPIO_AF14|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN15)
#define GPIO_TIM15_CH2OUT_3 (GPIO_ALT|GPIO_AF14|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTF|GPIO_PIN10)
#define GPIO_TIM15_CH2OUT_4 (GPIO_ALT|GPIO_AF14|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTG|GPIO_PIN11)
#define GPIO_TIM15_CH1N_1 (GPIO_ALT|GPIO_AF14|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN1)
#define GPIO_TIM15_CH1N_2 (GPIO_ALT|GPIO_AF14|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN13)
#define GPIO_TIM15_CH1N_3 (GPIO_ALT|GPIO_AF14|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTG|GPIO_PIN9)
#define GPIO_TIM15_BKIN_1 (GPIO_ALT|GPIO_AF14|GPIO_PORTA|GPIO_PIN9)
#define GPIO_TIM15_BKIN_2 (GPIO_ALT|GPIO_AF14|GPIO_PORTB|GPIO_PIN12)
#define GPIO_TIM16_CH1IN_1 (GPIO_ALT|GPIO_AF14|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN6)
#define GPIO_TIM16_CH1IN_2 (GPIO_ALT|GPIO_AF14|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN8)
#define GPIO_TIM16_CH1IN_3 (GPIO_ALT|GPIO_AF14|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTE|GPIO_PIN0)
#define GPIO_TIM16_CH1OUT_1 (GPIO_ALT|GPIO_AF14|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN6)
#define GPIO_TIM16_CH1OUT_2 (GPIO_ALT|GPIO_AF14|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN8)
#define GPIO_TIM16_CH1OUT_3 (GPIO_ALT|GPIO_AF14|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN0)
#define GPIO_TIM16_CH1N (GPIO_ALT|GPIO_AF14|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN6)
#define GPIO_TIM16_BKIN (GPIO_ALT|GPIO_AF14|GPIO_PORTB|GPIO_PIN5)
#define GPIO_TIM17_CH1IN_1 (GPIO_ALT|GPIO_AF14|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN7)
#define GPIO_TIM17_CH1IN_2 (GPIO_ALT|GPIO_AF14|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN9)
#define GPIO_TIM17_CH1IN_3 (GPIO_ALT|GPIO_AF14|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTE|GPIO_PIN1)
#define GPIO_TIM17_CH1OUT_1 (GPIO_ALT|GPIO_AF14|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN7)
#define GPIO_TIM17_CH1OUT_2 (GPIO_ALT|GPIO_AF14|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN9)
#define GPIO_TIM17_CH1OUT_3 (GPIO_ALT|GPIO_AF14|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN1)
#define GPIO_TIM17_CH1N (GPIO_ALT|GPIO_AF14|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN7)
#define GPIO_TIM17_BKIN_1 (GPIO_ALT|GPIO_AF14|GPIO_PORTA|GPIO_PIN10)
#define GPIO_TIM17_BKIN_2 (GPIO_ALT|GPIO_AF14|GPIO_PORTB|GPIO_PIN4)
#define GPIO_LPTIM1_IN1_1 (GPIO_ALT|GPIO_AF1 |GPIO_PORTB|GPIO_PIN5)
#define GPIO_LPTIM1_IN1_2 (GPIO_ALT|GPIO_AF1 |GPIO_PORTC|GPIO_PIN0)
#define GPIO_LPTIM1_IN1_3 (GPIO_ALT|GPIO_AF1 |GPIO_PORTG|GPIO_PIN10)
#define GPIO_LPTIM1_IN2_1 (GPIO_ALT|GPIO_AF1 |GPIO_PORTB|GPIO_PIN7)
#define GPIO_LPTIM1_IN2_2 (GPIO_ALT|GPIO_AF1 |GPIO_PORTC|GPIO_PIN2)
#define GPIO_LPTIM1_IN2_3 (GPIO_ALT|GPIO_AF1 |GPIO_PORTG|GPIO_PIN11)
#define GPIO_LPTIM1_OUT_1 (GPIO_ALT|GPIO_AF1 |GPIO_PORTB|GPIO_PIN2)
#define GPIO_LPTIM1_OUT_2 (GPIO_ALT|GPIO_AF1 |GPIO_PORTC|GPIO_PIN1)
#define GPIO_LPTIM1_OUT_3 (GPIO_ALT|GPIO_AF1 |GPIO_PORTG|GPIO_PIN15)
#define GPIO_LPTIM1_ETR_1 (GPIO_ALT|GPIO_AF1 |GPIO_PORTB|GPIO_PIN6)
#define GPIO_LPTIM1_ETR_2 (GPIO_ALT|GPIO_AF1 |GPIO_PORTC|GPIO_PIN3)
#define GPIO_LPTIM1_ETR_3 (GPIO_ALT|GPIO_AF1 |GPIO_PORTG|GPIO_PIN12)
#define GPIO_LPTIM2_IN1_1 (GPIO_ALT|GPIO_AF14|GPIO_PORTB|GPIO_PIN1)
#define GPIO_LPTIM2_IN1_2 (GPIO_ALT|GPIO_AF14|GPIO_PORTC|GPIO_PIN0)
#define GPIO_LPTIM2_IN1_3 (GPIO_ALT|GPIO_AF14|GPIO_PORTD|GPIO_PIN12)
#define GPIO_LPTIM2_OUT_1 (GPIO_ALT|GPIO_AF14|GPIO_PORTA|GPIO_PIN4)
#define GPIO_LPTIM2_OUT_2 (GPIO_ALT|GPIO_AF14|GPIO_PORTA|GPIO_PIN8)
#define GPIO_LPTIM2_OUT_3 (GPIO_ALT|GPIO_AF14|GPIO_PORTD|GPIO_PIN13)
#define GPIO_LPTIM2_ETR_1 (GPIO_ALT|GPIO_AF14|GPIO_PORTA|GPIO_PIN5)
#define GPIO_LPTIM2_ETR_2 (GPIO_ALT|GPIO_AF14|GPIO_PORTC|GPIO_PIN3)
#define GPIO_LPTIM2_ETR_3 (GPIO_ALT|GPIO_AF14|GPIO_PORTD|GPIO_PIN11)
/* Touch Sensing Controller */
#define GPIO_TSC_SYNC (GPIO_ALT|GPIO_AF9 |GPIO_PORTD|GPIO_PIN2)
#define GPIO_TSC_G1_IO1 (GPIO_ALT|GPIO_AF9 |GPIO_PORTB|GPIO_PIN12)
#define GPIO_TSC_G1_IO2 (GPIO_ALT|GPIO_AF9 |GPIO_PORTB|GPIO_PIN13)
#define GPIO_TSC_G1_IO3 (GPIO_ALT|GPIO_AF9 |GPIO_PORTB|GPIO_PIN14)
#define GPIO_TSC_G1_IO4 (GPIO_ALT|GPIO_AF9 |GPIO_PORTB|GPIO_PIN15)
#define GPIO_TSC_G2_IO1 (GPIO_ALT|GPIO_AF9 |GPIO_PORTB|GPIO_PIN4)
#define GPIO_TSC_G2_IO2 (GPIO_ALT|GPIO_AF9 |GPIO_PORTB|GPIO_PIN5)
#define GPIO_TSC_G2_IO3 (GPIO_ALT|GPIO_AF9 |GPIO_PORTB|GPIO_PIN6)
#define GPIO_TSC_G2_IO4 (GPIO_ALT|GPIO_AF9 |GPIO_PORTB|GPIO_PIN7)
#define GPIO_TSC_G3_IO1 (GPIO_ALT|GPIO_AF9 |GPIO_PORTA|GPIO_PIN15)
#define GPIO_TSC_G3_IO2 (GPIO_ALT|GPIO_AF9 |GPIO_PORTC|GPIO_PIN10)
#define GPIO_TSC_G3_IO3 (GPIO_ALT|GPIO_AF9 |GPIO_PORTC|GPIO_PIN11)
#define GPIO_TSC_G3_IO4 (GPIO_ALT|GPIO_AF9 |GPIO_PORTC|GPIO_PIN12)
#define GPIO_TSC_G4_IO1 (GPIO_ALT|GPIO_AF9 |GPIO_PORTC|GPIO_PIN6)
#define GPIO_TSC_G4_IO2 (GPIO_ALT|GPIO_AF9 |GPIO_PORTC|GPIO_PIN7)
#define GPIO_TSC_G4_IO3 (GPIO_ALT|GPIO_AF9 |GPIO_PORTC|GPIO_PIN8)
#define GPIO_TSC_G4_IO4 (GPIO_ALT|GPIO_AF9 |GPIO_PORTC|GPIO_PIN9)
#define GPIO_TSC_G5_IO1 (GPIO_ALT|GPIO_AF9 |GPIO_PORTE|GPIO_PIN10)
#define GPIO_TSC_G5_IO2 (GPIO_ALT|GPIO_AF9 |GPIO_PORTE|GPIO_PIN11)
#define GPIO_TSC_G5_IO3 (GPIO_ALT|GPIO_AF9 |GPIO_PORTE|GPIO_PIN12)
#define GPIO_TSC_G5_IO4 (GPIO_ALT|GPIO_AF9 |GPIO_PORTE|GPIO_PIN13)
#define GPIO_TSC_G6_IO1 (GPIO_ALT|GPIO_AF9 |GPIO_PORTD|GPIO_PIN10)
#define GPIO_TSC_G6_IO2 (GPIO_ALT|GPIO_AF9 |GPIO_PORTD|GPIO_PIN11)
#define GPIO_TSC_G6_IO3 (GPIO_ALT|GPIO_AF9 |GPIO_PORTD|GPIO_PIN12)
#define GPIO_TSC_G6_IO4 (GPIO_ALT|GPIO_AF9 |GPIO_PORTD|GPIO_PIN13)
#define GPIO_TSC_G7_IO1 (GPIO_ALT|GPIO_AF9 |GPIO_PORTE|GPIO_PIN2)
#define GPIO_TSC_G7_IO2 (GPIO_ALT|GPIO_AF9 |GPIO_PORTE|GPIO_PIN3)
#define GPIO_TSC_G7_IO3 (GPIO_ALT|GPIO_AF9 |GPIO_PORTE|GPIO_PIN4)
#define GPIO_TSC_G7_IO4 (GPIO_ALT|GPIO_AF9 |GPIO_PORTE|GPIO_PIN5)
#define GPIO_TSC_G8_IO1 (GPIO_ALT|GPIO_AF9 |GPIO_PORTF|GPIO_PIN14)
#define GPIO_TSC_G8_IO2 (GPIO_ALT|GPIO_AF9 |GPIO_PORTF|GPIO_PIN15)
#define GPIO_TSC_G8_IO3 (GPIO_ALT|GPIO_AF9 |GPIO_PORTG|GPIO_PIN0)
#define GPIO_TSC_G8_IO4 (GPIO_ALT|GPIO_AF9 |GPIO_PORTG|GPIO_PIN1)
/* IR interface (with timers 16 and 17) */
#define GPIO_IR_OUT_1 (GPIO_ALT|GPIO_AF1 |GPIO_PORTA|GPIO_PIN13)
#define GPIO_IR_OUT_2 (GPIO_ALT|GPIO_AF1 |GPIO_PORTB|GPIO_PIN9)
/* Trace */
#define GPIO_TRACECK (GPIO_ALT|GPIO_AF0 |GPIO_PORTE|GPIO_PIN2)
#define GPIO_TRACED0 (GPIO_ALT|GPIO_AF0 |GPIO_PORTE|GPIO_PIN3)
#define GPIO_TRACED1 (GPIO_ALT|GPIO_AF0 |GPIO_PORTE|GPIO_PIN4)
#define GPIO_TRACED2 (GPIO_ALT|GPIO_AF0 |GPIO_PORTE|GPIO_PIN5)
#define GPIO_TRACED3 (GPIO_ALT|GPIO_AF0 |GPIO_PORTE|GPIO_PIN6)
/* UARTs/USARTs */
#define GPIO_USART1_TX_1 (GPIO_ALT|GPIO_AF7 |GPIO_PORTA|GPIO_PIN9)
#define GPIO_USART1_TX_2 (GPIO_ALT|GPIO_AF7 |GPIO_PORTB|GPIO_PIN6)
#define GPIO_USART1_TX_3 (GPIO_ALT|GPIO_AF7 |GPIO_PORTG|GPIO_PIN9)
#define GPIO_USART1_RX_1 (GPIO_ALT|GPIO_AF7 |GPIO_PORTA|GPIO_PIN10)
#define GPIO_USART1_RX_2 (GPIO_ALT|GPIO_AF7 |GPIO_PORTB|GPIO_PIN7)
#define GPIO_USART1_RX_3 (GPIO_ALT|GPIO_AF7 |GPIO_PORTG|GPIO_PIN10)
#define GPIO_USART1_CK_1 (GPIO_ALT|GPIO_AF7 |GPIO_PORTA|GPIO_PIN8)
#define GPIO_USART1_CK_2 (GPIO_ALT|GPIO_AF7 |GPIO_PORTB|GPIO_PIN5)
#define GPIO_USART1_CK_3 (GPIO_ALT|GPIO_AF7 |GPIO_PORTG|GPIO_PIN13)
#define GPIO_USART1_CTS_1 (GPIO_ALT|GPIO_AF7 |GPIO_PORTA|GPIO_PIN11)
#define GPIO_USART1_CTS_2 (GPIO_ALT|GPIO_AF7 |GPIO_PORTB|GPIO_PIN4)
#define GPIO_USART1_CTS_3 (GPIO_ALT|GPIO_AF7 |GPIO_PORTG|GPIO_PIN11)
#define GPIO_USART1_RTS_DE_1 (GPIO_ALT|GPIO_AF7 |GPIO_PORTA|GPIO_PIN12)
#define GPIO_USART1_RTS_DE_2 (GPIO_ALT|GPIO_AF7 |GPIO_PORTB|GPIO_PIN3)
#define GPIO_USART1_RTS_DE_3 (GPIO_ALT|GPIO_AF7 |GPIO_PORTG|GPIO_PIN12)
#define GPIO_USART2_TX_1 (GPIO_ALT|GPIO_AF7 |GPIO_PORTA|GPIO_PIN2)
#define GPIO_USART2_TX_2 (GPIO_ALT|GPIO_AF7 |GPIO_PORTD|GPIO_PIN5)
#define GPIO_USART2_RX_1 (GPIO_ALT|GPIO_AF7 |GPIO_PORTA|GPIO_PIN3)
#define GPIO_USART2_RX_2 (GPIO_ALT|GPIO_AF7 |GPIO_PORTD|GPIO_PIN6)
#define GPIO_USART2_CK_1 (GPIO_ALT|GPIO_AF7 |GPIO_PORTA|GPIO_PIN4)
#define GPIO_USART2_CK_2 (GPIO_ALT|GPIO_AF7 |GPIO_PORTD|GPIO_PIN7)
#define GPIO_USART2_CTS_1 (GPIO_ALT|GPIO_AF7 |GPIO_PORTA|GPIO_PIN0)
#define GPIO_USART2_CTS_2 (GPIO_ALT|GPIO_AF7 |GPIO_PORTD|GPIO_PIN3)
#define GPIO_USART2_RTS_DE_1 (GPIO_ALT|GPIO_AF7 |GPIO_PORTA|GPIO_PIN1)
#define GPIO_USART2_RTS_DE_2 (GPIO_ALT|GPIO_AF7 |GPIO_PORTD|GPIO_PIN4)
#define GPIO_USART3_TX_1 (GPIO_ALT|GPIO_AF7 |GPIO_PORTB|GPIO_PIN10)
#define GPIO_USART3_TX_2 (GPIO_ALT|GPIO_AF7 |GPIO_PORTC|GPIO_PIN4)
#define GPIO_USART3_TX_3 (GPIO_ALT|GPIO_AF7 |GPIO_PORTC|GPIO_PIN10)
#define GPIO_USART3_TX_4 (GPIO_ALT|GPIO_AF7 |GPIO_PORTD|GPIO_PIN8)
#define GPIO_USART3_RX_1 (GPIO_ALT|GPIO_AF7 |GPIO_PORTB|GPIO_PIN11)
#define GPIO_USART3_RX_2 (GPIO_ALT|GPIO_AF7 |GPIO_PORTC|GPIO_PIN5)
#define GPIO_USART3_RX_3 (GPIO_ALT|GPIO_AF7 |GPIO_PORTC|GPIO_PIN11)
#define GPIO_USART3_RX_4 (GPIO_ALT|GPIO_AF7 |GPIO_PORTD|GPIO_PIN9)
#define GPIO_USART3_CK_1 (GPIO_ALT|GPIO_AF7 |GPIO_PORTB|GPIO_PIN0)
#define GPIO_USART3_CK_2 (GPIO_ALT|GPIO_AF7 |GPIO_PORTB|GPIO_PIN12)
#define GPIO_USART3_CK_3 (GPIO_ALT|GPIO_AF7 |GPIO_PORTC|GPIO_PIN12)
#define GPIO_USART3_CK_4 (GPIO_ALT|GPIO_AF7 |GPIO_PORTD|GPIO_PIN10)
#define GPIO_USART3_CTS_1 (GPIO_ALT|GPIO_AF7 |GPIO_PORTA|GPIO_PIN6)
#define GPIO_USART3_CTS_2 (GPIO_ALT|GPIO_AF7 |GPIO_PORTB|GPIO_PIN13)
#define GPIO_USART3_CTS_3 (GPIO_ALT|GPIO_AF7 |GPIO_PORTD|GPIO_PIN11)
#define GPIO_USART3_RTS_DE_1 (GPIO_ALT|GPIO_AF7 |GPIO_PORTB|GPIO_PIN1)
#define GPIO_USART3_RTS_DE_2 (GPIO_ALT|GPIO_AF7 |GPIO_PORTB|GPIO_PIN14)
#define GPIO_USART3_RTS_DE_3 (GPIO_ALT|GPIO_AF7 |GPIO_PORTD|GPIO_PIN2)
#define GPIO_USART3_RTS_DE_4 (GPIO_ALT|GPIO_AF7 |GPIO_PORTD|GPIO_PIN12)
#define GPIO_UART4_TX_1 (GPIO_ALT|GPIO_AF8 |GPIO_PORTA|GPIO_PIN0)
#define GPIO_UART4_TX_2 (GPIO_ALT|GPIO_AF8 |GPIO_PORTC|GPIO_PIN10)
#define GPIO_UART4_RX_1 (GPIO_ALT|GPIO_AF8 |GPIO_PORTA|GPIO_PIN1)
#define GPIO_UART4_RX_2 (GPIO_ALT|GPIO_AF8 |GPIO_PORTC|GPIO_PIN11)
#define GPIO_UART4_CTS (GPIO_ALT|GPIO_AF8 |GPIO_PORTB|GPIO_PIN7)
#define GPIO_UART4_RTS_DE (GPIO_ALT|GPIO_AF8 |GPIO_PORTA|GPIO_PIN15)
#define GPIO_UART5_TX (GPIO_ALT|GPIO_AF8 |GPIO_PORTC|GPIO_PIN12)
#define GPIO_UART5_RX (GPIO_ALT|GPIO_AF8 |GPIO_PORTD|GPIO_PIN2)
#define GPIO_UART5_CTS (GPIO_ALT|GPIO_AF8 |GPIO_PORTB|GPIO_PIN5)
#define GPIO_UART5_RTS_DE (GPIO_ALT|GPIO_AF8 |GPIO_PORTB|GPIO_PIN4)
#define GPIO_LPUART1_TX_1 (GPIO_ALT|GPIO_AF8 |GPIO_PORTB|GPIO_PIN11)
#define GPIO_LPUART1_TX_2 (GPIO_ALT|GPIO_AF8 |GPIO_PORTC|GPIO_PIN1)
#define GPIO_LPUART1_TX_3 (GPIO_ALT|GPIO_AF8 |GPIO_PORTG|GPIO_PIN7)
#define GPIO_LPUART1_RX_1 (GPIO_ALT|GPIO_AF8 |GPIO_PORTB|GPIO_PIN10)
#define GPIO_LPUART1_RX_2 (GPIO_ALT|GPIO_AF8 |GPIO_PORTC|GPIO_PIN0)
#define GPIO_LPUART1_RX_3 (GPIO_ALT|GPIO_AF8 |GPIO_PORTG|GPIO_PIN8)
#define GPIO_LPUART1_CTS_1 (GPIO_ALT|GPIO_AF8 |GPIO_PORTB|GPIO_PIN13)
#define GPIO_LPUART1_CTS_2 (GPIO_ALT|GPIO_AF8 |GPIO_PORTG|GPIO_PIN5)
#define GPIO_LPUART1_RTS_DE_1 (GPIO_ALT|GPIO_AF8 |GPIO_PORTB|GPIO_PIN12)
#define GPIO_LPUART1_RTS_DE_2 (GPIO_ALT|GPIO_AF8 |GPIO_PORTG|GPIO_PIN6)
#endif /* __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4X5XX_PINMAP_H */

710
arch/arm/src/stm32l4/chip/stm32l4x5xx_rcc.h Normal file
View file

@ -0,0 +1,710 @@
/****************************************************************************************************
* arch/arm/src/stm32l4/chip/stm32l4x6xx_rcc.h
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
* Copyright (C) 2016 Sebastien Lorquet. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
* Sebastien Lorquet <sebastien@lorquet.fr>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4X5XX_RCC_H
#define __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4X5XX_RCC_H
/****************************************************************************************************
* Included Files
****************************************************************************************************/
#include <nuttx/config.h>
#if defined(CONFIG_STM32L4_STM32L4X5)
/****************************************************************************************************
* Pre-processor Definitions
****************************************************************************************************/
/* Register Offsets *********************************************************************************/
#define STM32L4_RCC_CR_OFFSET 0x0000 /* Clock control register */
#define STM32L4_RCC_ICSCR_OFFSET 0x0004 /* Internal clock sources calibration register */
#define STM32L4_RCC_CFGR_OFFSET 0x0008 /* Clock configuration register */
#define STM32L4_RCC_PLLCFG_OFFSET 0x000c /* PLL configuration register */
#define STM32L4_RCC_PLLSAI1CFG_OFFSET 0x0010 /* PLLSAI1 configuration register */
#define STM32L4_RCC_PLLSAI2CFG_OFFSET 0x0014 /* PLLSAI2 configuration register */
#define STM32L4_RCC_CIER_OFFSET 0x0018 /* Clock interrupt enable register */
#define STM32L4_RCC_CIFR_OFFSET 0x001c /* Clock interrupt flag register */
#define STM32L4_RCC_CICR_OFFSET 0x0020 /* Clock interrupt clear register */
#define STM32L4_RCC_AHB1RSTR_OFFSET 0x0028 /* AHB1 peripheral reset register */
#define STM32L4_RCC_AHB2RSTR_OFFSET 0x002c /* AHB2 peripheral reset register */
#define STM32L4_RCC_AHB3RSTR_OFFSET 0x0030 /* AHB3 peripheral reset register */
#define STM32L4_RCC_APB1RSTR1_OFFSET 0x0038 /* APB1 Peripheral reset register 1 */
#define STM32L4_RCC_APB1RSTR2_OFFSET 0x003c /* APB1 Peripheral reset register 2 */
#define STM32L4_RCC_APB2RSTR_OFFSET 0x0040 /* APB2 Peripheral reset register */
#define STM32L4_RCC_AHB1ENR_OFFSET 0x0048 /* AHB1 Peripheral Clock enable register */
#define STM32L4_RCC_AHB2ENR_OFFSET 0x004c /* AHB2 Peripheral Clock enable register */
#define STM32L4_RCC_AHB3ENR_OFFSET 0x0050 /* AHB3 Peripheral Clock enable register */
#define STM32L4_RCC_APB1ENR1_OFFSET 0x0058 /* APB1 Peripheral Clock enable register 1 */
#define STM32L4_RCC_APB1ENR2_OFFSET 0x005c /* APB1 Peripheral Clock enable register 2 */
#define STM32L4_RCC_APB2ENR_OFFSET 0x0060 /* APB2 Peripheral Clock enable register */
#define STM32L4_RCC_AHB1SMENR_OFFSET 0x0068 /* RCC AHB1 low power mode peripheral clock enable register */
#define STM32L4_RCC_AHB2SMENR_OFFSET 0x006c /* RCC AHB2 low power mode peripheral clock enable register */
#define STM32L4_RCC_AHB3SMENR_OFFSET 0x0070 /* RCC AHB3 low power mode peripheral clock enable register */
#define STM32L4_RCC_APB1SMENR1_OFFSET 0x0078 /* RCC APB1 low power mode peripheral clock enable register 1 */
#define STM32L4_RCC_APB1SMENR2_OFFSET 0x007c /* RCC APB1 low power mode peripheral clock enable register 2 */
#define STM32L4_RCC_APB2SMENR_OFFSET 0x0080 /* RCC APB2 low power mode peripheral clock enable register */
#define STM32L4_RCC_CCIPR_OFFSET 0x0088 /* Peripherals independent clock configuration register 1 */
#define STM32L4_RCC_BDCR_OFFSET 0x0090 /* Backup domain control register */
#define STM32L4_RCC_CSR_OFFSET 0x0094 /* Control/status register */
/* Register Addresses *******************************************************************************/
#define STM32L4_RCC_CR (STM32L4_RCC_BASE+STM32L4_RCC_CR_OFFSET)
#define STM32L4_RCC_ICSCR (STM32L4_RCC_BASE+STM32L4_RCC_ICSCR_OFFSET)
#define STM32L4_RCC_CFGR (STM32L4_RCC_BASE+STM32L4_RCC_CFGR_OFFSET)
#define STM32L4_RCC_PLLCFG (STM32L4_RCC_BASE+STM32L4_RCC_PLLCFG_OFFSET)
#define STM32L4_RCC_PLLSAI1CFG (STM32L4_RCC_BASE+STM32L4_RCC_PLLSAI1CFG_OFFSET)
#define STM32L4_RCC_PLLSAI2CFG (STM32L4_RCC_BASE+STM32L4_RCC_PLLSAI2CFG_OFFSET)
#define STM32L4_RCC_CIER (STM32L4_RCC_BASE+STM32L4_RCC_CIER_OFFSET)
#define STM32L4_RCC_CIFR (STM32L4_RCC_BASE+STM32L4_RCC_CIFR_OFFSET)
#define STM32L4_RCC_CICR (STM32L4_RCC_BASE+STM32L4_RCC_CICR_OFFSET)
#define STM32L4_RCC_AHB1RSTR (STM32L4_RCC_BASE+STM32L4_RCC_AHB1RSTR_OFFSET)
#define STM32L4_RCC_AHB2RSTR (STM32L4_RCC_BASE+STM32L4_RCC_AHB2RSTR_OFFSET)
#define STM32L4_RCC_AHB3RSTR (STM32L4_RCC_BASE+STM32L4_RCC_AHB3RSTR_OFFSET)
#define STM32L4_RCC_APB1RSTR1 (STM32L4_RCC_BASE+STM32L4_RCC_APB1RSTR1_OFFSET)
#define STM32L4_RCC_APB1RSTR2 (STM32L4_RCC_BASE+STM32L4_RCC_APB1RSTR2_OFFSET)
#define STM32L4_RCC_APB2RSTR (STM32L4_RCC_BASE+STM32L4_RCC_APB2RSTR_OFFSET)
#define STM32L4_RCC_AHB1ENR (STM32L4_RCC_BASE+STM32L4_RCC_AHB1ENR_OFFSET)
#define STM32L4_RCC_AHB2ENR (STM32L4_RCC_BASE+STM32L4_RCC_AHB2ENR_OFFSET)
#define STM32L4_RCC_AHB3ENR (STM32L4_RCC_BASE+STM32L4_RCC_AHB3ENR_OFFSET)
#define STM32L4_RCC_APB1ENR1 (STM32L4_RCC_BASE+STM32L4_RCC_APB1ENR1_OFFSET)
#define STM32L4_RCC_APB1ENR2 (STM32L4_RCC_BASE+STM32L4_RCC_APB1ENR2_OFFSET)
#define STM32L4_RCC_APB2ENR (STM32L4_RCC_BASE+STM32L4_RCC_APB2ENR_OFFSET)
#define STM32L4_RCC_AHB1SMENR (STM32L4_RCC_BASE+STM32L4_RCC_AHB1SMENR_OFFSET)
#define STM32L4_RCC_AHB2SMENR (STM32L4_RCC_BASE+STM32L4_RCC_AHB2SMENR)
#define STM32L4_RCC_AHB3SMENR (STM32L4_RCC_BASE+STM32L4_RCC_AHB3SMENR_OFFSET)
#define STM32L4_RCC_APB1SMENR1 (STM32L4_RCC_BASE+STM32L4_RCC_APB1SMENR1_OFFSET)
#define STM32L4_RCC_APB1SMENR2 (STM32L4_RCC_BASE+STM32L4_RCC_APB1SMENR2_OFFSET)
#define STM32L4_RCC_APB2SMENR (STM32L4_RCC_BASE+STM32L4_RCC_APB2SMENR_OFFSET)
#define STM32L4_RCC_CCIPR (STM32L4_RCC_BASE+STM32L4_RCC_CCIPR_OFFSET)
#define STM32L4_RCC_BDCR (STM32L4_RCC_BASE+STM32L4_RCC_BDCR_OFFSET)
#define STM32L4_RCC_CSR (STM32L4_RCC_BASE+STM32L4_RCC_CSR_OFFSET)
/* Register Bitfield Definitions ********************************************************************/
/* Clock control register */
#define RCC_CR_MSION (1 << 0) /* Bit 0: Internal Multi Speed clock enable */
#define RCC_CR_MSIRDY (1 << 1) /* Bit 1: Internal Multi Speed clock ready flag */
#define RCC_CR_MSIPLLEN (1 << 2) /* Bit 2: MSI clock PLL enable */
#define RCC_CR_MSIRGSEL (1 << 3) /* Bit 3: MSI clock range selection */
#define RCC_CR_MSIRANGE_SHIFT (4) /* Bits 7-4: MSI clock range */
#define RCC_CR_MSIRANGE_MASK (0x0f << RCC_CR_MSIRANGE_SHIFT)
# define RCC_CR_MSIRANGE_100K (0 << RCC_CR_MSIRANGE_SHIFT) /* 0000: around 100 kHz */
# define RCC_CR_MSIRANGE_200K (1 << RCC_CR_MSIRANGE_SHIFT) /* 0001: around 200 kHz */
# define RCC_CR_MSIRANGE_400K (2 << RCC_CR_MSIRANGE_SHIFT) /* 0010: around 400 kHz */
# define RCC_CR_MSIRANGE_800K (3 << RCC_CR_MSIRANGE_SHIFT) /* 0011: around 800 kHz */
# define RCC_CR_MSIRANGE_1M (4 << RCC_CR_MSIRANGE_SHIFT) /* 0100: around 1 MHz */
# define RCC_CR_MSIRANGE_2M (5 << RCC_CR_MSIRANGE_SHIFT) /* 0101: around 2 MHz */
# define RCC_CR_MSIRANGE_4M (6 << RCC_CR_MSIRANGE_SHIFT) /* 0110: around 4 MHz */
# define RCC_CR_MSIRANGE_8M (7 << RCC_CR_MSIRANGE_SHIFT) /* 0111: around 8 MHz */
# define RCC_CR_MSIRANGE_16M (8 << RCC_CR_MSIRANGE_SHIFT) /* 1000: around 16 MHz */
# define RCC_CR_MSIRANGE_24M (9 << RCC_CR_MSIRANGE_SHIFT) /* 1001: around 24 MHz */
# define RCC_CR_MSIRANGE_32M (10 << RCC_CR_MSIRANGE_SHIFT) /* 1010: around 32 MHz */
# define RCC_CR_MSIRANGE_48M (11 << RCC_CR_MSIRANGE_SHIFT) /* 1011: around 48 MHz */
#define RCC_CR_HSION (1 << 8) /* Bit 8: Internal High Speed clock enable */
#define RCC_CR_HSIKERON (1 << 9) /* Bit 9: HSI16 always enable for peripheral kernels */
#define RCC_CR_HSIRDY (1 << 10) /* Bit 10: Internal High Speed clock ready flag */
#define RCC_CR_HSIASFS (1 << 11) /* Bit 11: HSI automatic start from stop */
#define RCC_CR_HSEON (1 << 16) /* Bit 16: External High Speed clock enable */
#define RCC_CR_HSERDY (1 << 17) /* Bit 17: External High Speed clock ready flag */
#define RCC_CR_HSEBYP (1 << 18) /* Bit 18: External High Speed clock Bypass */
#define RCC_CR_CSSON (1 << 19) /* Bit 19: Clock Security System enable */
#define RCC_CR_PLLON (1 << 24) /* Bit 24: PLL enable */
#define RCC_CR_PLLRDY (1 << 25) /* Bit 25: PLL clock ready flag */
#define RCC_CR_PLLSAI1ON (1 << 26) /* Bit 26: PLLSAI1 enable */
#define RCC_CR_PLLSAI1RDY (1 << 27) /* Bit 27: PLLSAI1 clock ready flag */
#define RCC_CR_PLLSAI2ON (1 << 28) /* Bit 28: PLLSAI2 enable */
#define RCC_CR_PLLSAI2RDY (1 << 29) /* Bit 29: PLLSAI2 clock ready flag */
/* Internal Clock Sources Calibration */
#define RCC_CR_MSICAL_SHIFT (0) /* Bits 7-0: Internal Multi Speed clock Calibration */
#define RCC_CR_MSICAL_MASK (0xff << RCC_CR_MSICAL_SHIFT)
#define RCC_CR_MSITRIM_SHIFT (8) /* Bits 15-8: Internal Multi Speed clock trimming */
#define RCC_CR_MSITRIM_MASK (0xff << RCC_CR_MSITRIM_SHIFT)
#define RCC_CR_HSICAL_SHIFT (16) /* Bits 23-16: Internal High Speed clock Calibration */
#define RCC_CR_HSICAL_MASK (0xff << RCC_CR_HSICAL_SHIFT)
#define RCC_CR_HSITRIM_SHIFT (24) /* Bits 28-24: Internal High Speed clock trimming */
#define RCC_CR_HSITRIM_MASK (0x1f << RCC_CR_HSITRIM_SHIFT)
/* Clock configuration register */
#define RCC_CFGR_SW_SHIFT (0) /* Bits 0-1: System clock Switch */
#define RCC_CFGR_SW_MASK (3 << RCC_CFGR_SW_SHIFT)
# define RCC_CFGR_SW_MSI (0 << RCC_CFGR_SW_SHIFT) /* 00: HSI selected as system clock */
# define RCC_CFGR_SW_HSI (1 << RCC_CFGR_SW_SHIFT) /* 00: HSI selected as system clock */
# define RCC_CFGR_SW_HSE (2 << RCC_CFGR_SW_SHIFT) /* 01: HSE selected as system clock */
# define RCC_CFGR_SW_PLL (3 << RCC_CFGR_SW_SHIFT) /* 10: PLL selected as system clock */
#define RCC_CFGR_SWS_SHIFT (2) /* Bits 2-3: System Clock Switch Status */
#define RCC_CFGR_SWS_MASK (3 << RCC_CFGR_SWS_SHIFT)
# define RCC_CFGR_SWS_MSI (0 << RCC_CFGR_SWS_SHIFT) /* 00: HSI oscillator used as system clock */
# define RCC_CFGR_SWS_HSI (1 << RCC_CFGR_SWS_SHIFT) /* 00: HSI oscillator used as system clock */
# define RCC_CFGR_SWS_HSE (2 << RCC_CFGR_SWS_SHIFT) /* 01: HSE oscillator used as system clock */
# define RCC_CFGR_SWS_PLL (3 << RCC_CFGR_SWS_SHIFT) /* 10: PLL used as system clock */
#define RCC_CFGR_HPRE_SHIFT (4) /* Bits 4-7: AHB prescaler */
#define RCC_CFGR_HPRE_MASK (0x0f << RCC_CFGR_HPRE_SHIFT)
# define RCC_CFGR_HPRE_SYSCLK (0 << RCC_CFGR_HPRE_SHIFT) /* 0xxx: SYSCLK not divided */
# define RCC_CFGR_HPRE_SYSCLKd2 (8 << RCC_CFGR_HPRE_SHIFT) /* 1000: SYSCLK divided by 2 */
# define RCC_CFGR_HPRE_SYSCLKd4 (9 << RCC_CFGR_HPRE_SHIFT) /* 1001: SYSCLK divided by 4 */
# define RCC_CFGR_HPRE_SYSCLKd8 (10 << RCC_CFGR_HPRE_SHIFT) /* 1010: SYSCLK divided by 8 */
# define RCC_CFGR_HPRE_SYSCLKd16 (11 << RCC_CFGR_HPRE_SHIFT) /* 1011: SYSCLK divided by 16 */
# define RCC_CFGR_HPRE_SYSCLKd64 (12 << RCC_CFGR_HPRE_SHIFT) /* 1100: SYSCLK divided by 64 */
# define RCC_CFGR_HPRE_SYSCLKd128 (13 << RCC_CFGR_HPRE_SHIFT) /* 1101: SYSCLK divided by 128 */
# define RCC_CFGR_HPRE_SYSCLKd256 (14 << RCC_CFGR_HPRE_SHIFT) /* 1110: SYSCLK divided by 256 */
# define RCC_CFGR_HPRE_SYSCLKd512 (15 << RCC_CFGR_HPRE_SHIFT) /* 1111: SYSCLK divided by 512 */
#define RCC_CFGR_PPRE1_SHIFT (8) /* Bits 8-10: APB Low speed prescaler (APB1) */
#define RCC_CFGR_PPRE1_MASK (7 << RCC_CFGR_PPRE1_SHIFT)
# define RCC_CFGR_PPRE1_HCLK (0 << RCC_CFGR_PPRE1_SHIFT) /* 0xx: HCLK not divided */
# define RCC_CFGR_PPRE1_HCLKd2 (4 << RCC_CFGR_PPRE1_SHIFT) /* 100: HCLK divided by 2 */
# define RCC_CFGR_PPRE1_HCLKd4 (5 << RCC_CFGR_PPRE1_SHIFT) /* 101: HCLK divided by 4 */
# define RCC_CFGR_PPRE1_HCLKd8 (6 << RCC_CFGR_PPRE1_SHIFT) /* 110: HCLK divided by 8 */
# define RCC_CFGR_PPRE1_HCLKd16 (7 << RCC_CFGR_PPRE1_SHIFT) /* 111: HCLK divided by 16 */
#define RCC_CFGR_PPRE2_SHIFT (11) /* Bits 11-13: APB High speed prescaler (APB2) */
#define RCC_CFGR_PPRE2_MASK (7 << RCC_CFGR_PPRE2_SHIFT)
# define RCC_CFGR_PPRE2_HCLK (0 << RCC_CFGR_PPRE2_SHIFT) /* 0xx: HCLK not divided */
# define RCC_CFGR_PPRE2_HCLKd2 (4 << RCC_CFGR_PPRE2_SHIFT) /* 100: HCLK divided by 2 */
# define RCC_CFGR_PPRE2_HCLKd4 (5 << RCC_CFGR_PPRE2_SHIFT) /* 101: HCLK divided by 4 */
# define RCC_CFGR_PPRE2_HCLKd8 (6 << RCC_CFGR_PPRE2_SHIFT) /* 110: HCLK divided by 8 */
# define RCC_CFGR_PPRE2_HCLKd16 (7 << RCC_CFGR_PPRE2_SHIFT) /* 111: HCLK divided by 16 */
#define RCC_CFGR_STOPWUCK (1 << 15) /* Bit 15: Wakeup from Stop and CSS backup clock selection */
# define RCC_CFGR_STOPWUCK_MSI (0 << 15) /* 0: MSI */
# define RCC_CFGR_STOPWUCK_HSI (1 << 15) /* 0: HSI */
#define RCC_CFGR_MCO_SHIFT (24) /* Bits 24-26: Microcontroller Clock Output */
#define RCC_CFGR_MCO_MASK (7 << RCC_CFGR_MCO_SHIFT)
# define RCC_CFGR_MCO_NONE (0 << RCC_CFGR_MCO_SHIFT) /* 000: Disabled */
# define RCC_CFGR_MCO_SYSCLK (1 << RCC_CFGR_MCO_SHIFT) /* 001: SYSCLK system clock selected */
# define RCC_CFGR_MCO_MSI (2 << RCC_CFGR_MCO_SHIFT) /* 010: MSI clock selected */
# define RCC_CFGR_MCO_HSI (3 << RCC_CFGR_MCO_SHIFT) /* 011: HSI clock selected */
# define RCC_CFGR_MCO_HSE (4 << RCC_CFGR_MCO_SHIFT) /* 100: HSE clock selected */
# define RCC_CFGR_MCO_PLL (5 << RCC_CFGR_MCO_SHIFT) /* 101: Main PLL selected */
# define RCC_CFGR_MCO_LSI (6 << RCC_CFGR_MCO_SHIFT) /* 110: LSI clock selected */
# define RCC_CFGR_MCO_LSE (7 << RCC_CFGR_MCO_SHIFT) /* 111: LSE clock selected */
#define RCC_CFGR_MCOPRE_SHIFT (28) /* Bits 28-30: MCO prescaler */
#define RCC_CFGR_MCOPRE_MASK (7 << RCC_CFGR_MCOPRE_SHIFT)
# define RCC_CFGR_MCOPRE_NONE (0 << RCC_CFGR_MCOPRE_SHIFT) /* 000: no division */
# define RCC_CFGR_MCOPRE_DIV2 (1 << RCC_CFGR_MCOPRE_SHIFT) /* 001: division by 2 */
# define RCC_CFGR_MCOPRE_DIV4 (2 << RCC_CFGR_MCOPRE_SHIFT) /* 010: division by 4 */
# define RCC_CFGR_MCOPRE_DIV8 (3 << RCC_CFGR_MCOPRE_SHIFT) /* 011: division by 8 */
# define RCC_CFGR_MCOPRE_DIV16 (4 << RCC_CFGR_MCOPRE_SHIFT) /* 100: division by 16 */
/* PLL configuration register */
#define RCC_PLLCFG_PLLSRC_SHIFT (0) /* Bit 0-1: Main PLL(PLL) and audio PLLs (PLLSAIx)
* entry clock source */
#define RCC_PLLCFG_PLLSRC_MASK (3 << RCC_PLLCFG_PLLSRC_SHIFT)
# define RCC_PLLCFG_PLLSRC_NONE (0 << RCC_PLLCFG_PLLSRC_SHIFT) /* 000: No clock sent to PLLs */
# define RCC_PLLCFG_PLLSRC_MSI (1 << RCC_PLLCFG_PLLSRC_SHIFT) /* 001: MSI selected as PLL source */
# define RCC_PLLCFG_PLLSRC_HSI (2 << RCC_PLLCFG_PLLSRC_SHIFT) /* 001: HSI selected as PLL source */
# define RCC_PLLCFG_PLLSRC_HSE (3 << RCC_PLLCFG_PLLSRC_SHIFT) /* 001: HSE selected as PLL source */
#define RCC_PLLCFG_PLLM_SHIFT (4) /* Bits 4-6: Main PLL (PLL) input clock divider */
#define RCC_PLLCFG_PLLM_MASK (0x07 << RCC_PLLCFG_PLLM_SHIFT)
# define RCC_PLLCFG_PLLM(n) ((n-1) << RCC_PLLCFG_PLLM_SHIFT) /* m = 1..8 */
#define RCC_PLLCFG_PLLN_SHIFT (8) /* Bits 6-14: Main PLL (PLL) VCO multiplier */
#define RCC_PLLCFG_PLLN_MASK (0x7f << RCC_PLLCFG_PLLN_SHIFT)
# define RCC_PLLCFG_PLLN(n) ((n) << RCC_PLLCFG_PLLN_SHIFT) /* n = 8..86 */
#define RCC_PLLCFG_PLLPEN (1 << 16) /* Bit 16: Main PLL PLLSAI3CLK output enable */
#define RCC_PLLCFG_PLLP (1 << 17) /* Bit 17: Main PLL div factor for PLLSAI3CLK */
# define RCC_PLLCFG_PLLP_7 0 /* 0: PLLP = 7 */
# define RCC_PLLCFG_PLLP_17 RCC_PLLCFG_PLLP /* 1: PLLP = 17 */
#define RCC_PLLCFG_PLLQEN (1 << 20) /* Bit 20: Main PLL PLL48M1CLK output enable */
#define RCC_PLLCFG_PLLQ_SHIFT (21)
#define RCC_PLLCFG_PLLQ_MASK (3 << RCC_PLLCFG_PLLQ_SHIFT)
# define RCC_PLLCFG_PLLQ(n) ((((n)>>1)-1)<< RCC_PLLCFG_PLLQ_SHIFT) /* n=2,4,6,8 */
# define RCC_PLLCFG_PLLQ_2 (0 << RCC_PLLCFG_PLLQ_SHIFT) /* 00: PLLQ = 2 */
# define RCC_PLLCFG_PLLQ_4 (1 << RCC_PLLCFG_PLLQ_SHIFT) /* 01: PLLQ = 4 */
# define RCC_PLLCFG_PLLQ_6 (2 << RCC_PLLCFG_PLLQ_SHIFT) /* 10: PLLQ = 6 */
# define RCC_PLLCFG_PLLQ_8 (3 << RCC_PLLCFG_PLLQ_SHIFT) /* 11: PLLQ = 8 */
#define RCC_PLLCFG_PLLREN (1 << 24) /* Bit 24: Main PLL PLLCLK output enable */
#define RCC_PLLCFG_PLLR_SHIFT (25)
#define RCC_PLLCFG_PLLR_MASK (3 << RCC_PLLCFG_PLLR_SHIFT)
# define RCC_PLLCFG_PLLR(n) ((((n)>>1)-1)<< RCC_PLLCFG_PLLR_SHIFT) /* n=2,4,6,8 */
# define RCC_PLLCFG_PLLR_2 (0 << RCC_PLLCFG_PLLR_SHIFT) /* 00: PLLR = 2 */
# define RCC_PLLCFG_PLLR_4 (1 << RCC_PLLCFG_PLLR_SHIFT) /* 01: PLLR = 4 */
# define RCC_PLLCFG_PLLR_6 (2 << RCC_PLLCFG_PLLR_SHIFT) /* 10: PLLR = 6 */
# define RCC_PLLCFG_PLLR_8 (3 << RCC_PLLCFG_PLLR_SHIFT) /* 11: PLLR = 8 */
#define RCC_PLLCFG_RESET (0x00001000) /* PLLCFG reset value */
/* PLLSAI1 Configuration register */
#define RCC_PLLSAI1CFG_PLLN_SHIFT (8) /* Bits 6-14: SAI1 PLL (PLLSAI1) VCO multiplier */
#define RCC_PLLSAI1CFG_PLLN_MASK (0x7f << RCC_PLLSAI1CFG_PLLN_SHIFT)
# define RCC_PLLSAI1CFG_PLLN(n) ((n) << RCC_PLLSAI1CFG_PLLN_SHIFT) /* n = 8..86 */
#define RCC_PLLSAI1CFG_PLLPEN (1 << 16) /* Bit 16: SAI1 PLL PLLSAI1CLK output enable */
#define RCC_PLLSAI1CFG_PLLP (1 << 17) /* Bit 17: Main PLL div factor for PLLSAI1CLK */
# define RCC_PLLSAI1CFG_PLLP_7 0 /* 0: PLLP = 7 */
# define RCC_PLLSAI1CFG_PLLP_17 RCC_PLLSAI1CFG_PLLP /* 1: PLLP = 17 */
#define RCC_PLLSAI1CFG_PLLQEN (1 << 20) /* Bit 20: Main PLL PLL48M2CLK output enable */
#define RCC_PLLSAI1CFG_PLLQ_SHIFT (21)
#define RCC_PLLSAI1CFG_PLLQ_MASK (3 << RCC_PLLSAI1CFG_PLLQ_SHIFT)
# define RCC_PLLSAI1CFG_PLLQ(n) ((((n)>>1)-1)<< RCC_PLLSAI1CFG_PLLQ_SHIFT) /* n=2,4,6,8 */
# define RCC_PLLSAI1CFG_PLLQ_2 (0 << RCC_PLLSAI1CFG_PLLQ_SHIFT) /* 00: PLLQ = 2 */
# define RCC_PLLSAI1CFG_PLLQ_4 (1 << RCC_PLLSAI1CFG_PLLQ_SHIFT) /* 01: PLLQ = 4 */
# define RCC_PLLSAI1CFG_PLLQ_6 (2 << RCC_PLLSAI1CFG_PLLQ_SHIFT) /* 10: PLLQ = 6 */
# define RCC_PLLSAI1CFG_PLLQ_8 (3 << RCC_PLLSAI1CFG_PLLQ_SHIFT) /* 11: PLLQ = 8 */
#define RCC_PLLSAI1CFG_PLLREN (1 << 24) /* Bit 24: SAI1 PLL PLLADC1CLK output enable */
#define RCC_PLLSAI1CFG_PLLR_SHIFT (25)
#define RCC_PLLSAI1CFG_PLLR_MASK (3 << RCC_PLLSAI1CFG_PLLR_SHIFT)
# define RCC_PLLSAI1CFG_PLLR(n) ((((n)>>1)-1)<< RCC_PLLSAI1CFG_PLLR_SHIFT) /* n=2,4,6,8 */
# define RCC_PLLSAI1CFG_PLLR_2 (0 << RCC_PLLSAI1CFG_PLLR_SHIFT) /* 00: PLLR = 2 */
# define RCC_PLLSAI1CFG_PLLR_4 (1 << RCC_PLLSAI1CFG_PLLR_SHIFT) /* 01: PLLR = 4 */
# define RCC_PLLSAI1CFG_PLLR_6 (2 << RCC_PLLSAI1CFG_PLLR_SHIFT) /* 10: PLLR = 6 */
# define RCC_PLLSAI1CFG_PLLR_8 (3 << RCC_PLLSAI1CFG_PLLR_SHIFT) /* 11: PLLR = 8 */
/* PLLSAI2 Configuration register */
#define RCC_PLLSAI2CFG_PLLN_SHIFT (8) /* Bits 6-14: SAI2 PLL (PLLSAI2) VCO multiplier */
#define RCC_PLLSAI2CFG_PLLN_MASK (0x7f << RCC_PLLSAI2CFG_PLLN_SHIFT)
# define RCC_PLLSAI2CFG_PLLN(n) ((n) << RCC_PLLSAI2CFG_PLLN_SHIFT) /* n = 8..86 */
#define RCC_PLLSAI2CFG_PLLPEN (1 << 16) /* Bit 16: SAI1 PLL PLLSAI2CLK output enable */
#define RCC_PLLSAI2CFG_PLLP (1 << 17) /* Bit 17: Main PLL div factor for PLLSAI2CLK */
# define RCC_PLLSAI2CFG_PLLP_7 0 /* 0: PLLP = 7 */
# define RCC_PLLSAI2CFG_PLLP_17 RCC_PLLSAI2CFG_PLLP /* 1: PLLP = 17 */
#define RCC_PLLSAI2CFG_PLLREN (1 << 24) /* Bit 24: SAI2 PLL PLLADC2CLK output enable */
#define RCC_PLLSAI2CFG_PLLR_SHIFT (25)
#define RCC_PLLSAI2CFG_PLLR_MASK (3 << RCC_PLLSAI2CFG_PLLR_SHIFT)
# define RCC_PLLSAI2CFG_PLLR(n) ((((n)>>1)-1)<< RCC_PLLSAI2CFG_PLLR_SHIFT) /* n=2,4,6,8 */
# define RCC_PLLSAI2CFG_PLLR_2 (0 << RCC_PLLSAI2CFG_PLLR_SHIFT) /* 00: PLLR = 2 */
# define RCC_PLLSAI2CFG_PLLR_4 (1 << RCC_PLLSAI2CFG_PLLR_SHIFT) /* 01: PLLR = 4 */
# define RCC_PLLSAI2CFG_PLLR_6 (2 << RCC_PLLSAI2CFG_PLLR_SHIFT) /* 10: PLLR = 6 */
# define RCC_PLLSAI2CFG_PLLR_8 (3 << RCC_PLLSAI2CFG_PLLR_SHIFT) /* 11: PLLR = 8 */
/* Clock interrupt enable register */
#define RCC_CIR_LSIRDYIE (1 << 0) /* Bit 0: LSI Ready Interrupt Enable */
#define RCC_CIR_LSERDYIE (1 << 1) /* Bit 1: LSE Ready Interrupt Enable */
#define RCC_CIR_MSIRDYIE (1 << 2) /* Bit 2: MSI Ready Interrupt Enable */
#define RCC_CIR_HSIRDYIE (1 << 3) /* Bit 3: HSI Ready Interrupt Enable */
#define RCC_CIR_HSERDYIE (1 << 4) /* Bit 4: HSE Ready Interrupt Enable */
#define RCC_CIR_PLLRDYIE (1 << 5) /* Bit 5: PLL Ready Interrupt Enable */
#define RCC_CIR_PLLSAI1RDYIE (1 << 6) /* Bit 6: PLLSAI1 Ready Interrupt enable */
#define RCC_CIR_PLLSAI2RDYIE (1 << 7) /* Bit 7: PLLSAI2 Ready Interrupt enable */
#define RCC_CIR_LSECSSIE (1 << 9) /* Bit 9: LSE Clock Security System Interrupt Enable */
/* Clock interrupt flag register */
#define RCC_CIR_LSIRDYIF (1 << 0) /* Bit 0: LSI Ready Interrupt Flag */
#define RCC_CIR_LSERDYIF (1 << 1) /* Bit 1: LSE Ready Interrupt Flag */
#define RCC_CIR_MSIRDYIF (1 << 2) /* Bit 2: MSI Ready Interrupt Flag */
#define RCC_CIR_HSIRDYIF (1 << 3) /* Bit 3: HSI Ready Interrupt Flag */
#define RCC_CIR_HSERDYIF (1 << 4) /* Bit 4: HSE Ready Interrupt Flag */
#define RCC_CIR_PLLRDYIF (1 << 5) /* Bit 5: PLL Ready Interrupt Flag */
#define RCC_CIR_PLLSAI1RDYIF (1 << 6) /* Bit 6: PLLSAI1 Ready Interrupt Flag */
#define RCC_CIR_PLLSAI2RDYIF (1 << 7) /* Bit 7: PLLSAI2 Ready Interrupt Flag */
#define RCC_CIR_CSSF (1 << 8) /* Bit 8: Clock Security System Interrupt Flag */
#define RCC_CIR_LSECSSIF (1 << 9) /* Bit 9: LSE Clock Security System Interrupt Flag */
#define RCC_CIR_HSI48RDYIF (1 << 10) /* Bit 10: HSI48 Ready Interrupt Flag */
/* Clock interrupt clear register */
#define RCC_CIR_LSIRDYIC (1 << 0) /* Bit 0: LSI Ready Interrupt Clear */
#define RCC_CIR_LSERDYIC (1 << 1) /* Bit 1: LSE Ready Interrupt Clear */
#define RCC_CIR_MSIRDYIC (1 << 2) /* Bit 2: MSI Ready Interrupt Clear */
#define RCC_CIR_HSIRDYIC (1 << 3) /* Bit 3: HSI Ready Interrupt Clear */
#define RCC_CIR_HSERDYIC (1 << 4) /* Bit 4: HSE Ready Interrupt Clear */
#define RCC_CIR_PLLRDYIC (1 << 5) /* Bit 5: PLL Ready Interrupt Clear */
#define RCC_CIR_PLLSAI1RDYIC (1 << 6) /* Bit 6: PLLSAI1 Ready Interrupt Clear */
#define RCC_CIR_PLLSAI2RDYIC (1 << 7) /* Bit 7: PLLSAI2 Ready Interrupt Clear */
#define RCC_CIR_CSSC (1 << 8) /* Bit 8: Clock Security System Interrupt Clear */
#define RCC_CIR_LSECSSIC (1 << 9) /* Bit 9: LSE Clock Security System Interrupt Clear */
/* AHB1 peripheral reset register */
#define RCC_AHB1RSTR_DMA1RST (1 << 0) /* Bit 0: DMA1 reset */
#define RCC_AHB1RSTR_DMA2RST (1 << 1) /* Bit 1: DMA2 reset */
#define RCC_AHB1RSTR_FLASHRST (1 << 8) /* Bit 8: Flash memory interface reset */
#define RCC_AHB1RSTR_CRCRST (1 << 12) /* Bit 12: CRC reset */
#define RCC_AHB1RSTR_TSCRST (1 << 16) /* Bit 16: Touch Sensing Controller reset */
/* AHB2 peripheral reset register */
#define RCC_AHB1ENR_GPIOEN(port) (1 << (port))
#define RCC_AHB2RSTR_GPIOARST (1 << 0) /* Bit 0: IO port A reset */
#define RCC_AHB2RSTR_GPIOBRST (1 << 1) /* Bit 1: IO port B reset */
#define RCC_AHB2RSTR_GPIOCRST (1 << 2) /* Bit 2: IO port C reset */
#define RCC_AHB2RSTR_GPIODRST (1 << 3) /* Bit 3: IO port D reset */
#define RCC_AHB2RSTR_GPIOERST (1 << 4) /* Bit 4: IO port E reset */
#define RCC_AHB2RSTR_GPIOFRST (1 << 5) /* Bit 5: IO port F reset */
#define RCC_AHB2RSTR_GPIOGRST (1 << 6) /* Bit 6: IO port G reset */
#define RCC_AHB2RSTR_GPIOHRST (1 << 7) /* Bit 7: IO port H reset */
#define RCC_AHB2RSTR_OTGFSRST (1 << 12) /* Bit 12: USB OTG FS module reset */
#define RCC_AHB2RSTR_ADCRST (1 << 13) /* Bit 13: ADC interface reset (common to all ADCs) */
#define RCC_AHB2RSTR_RNGRST (1 << 18) /* Bit 18: Random number generator module reset */
/* AHB3 peripheral reset register */
#define RCC_AHB3RSTR_FSMCRST (1 << 0) /* Bit 0: Flexible static memory controller module reset */
#define RCC_AHB3RSTR_QSPIRST (1 << 8) /* Bit 8: Quad SPI module reset */
/* APB1 Peripheral reset register 1 */
#define RCC_APB1RSTR1_TIM2RST (1 << 0) /* Bit 0: TIM2 reset */
#define RCC_APB1RSTR1_TIM3RST (1 << 1) /* Bit 1: TIM3 reset */
#define RCC_APB1RSTR1_TIM4RST (1 << 2) /* Bit 2: TIM4 reset */
#define RCC_APB1RSTR1_TIM5RST (1 << 3) /* Bit 3: TIM5 reset */
#define RCC_APB1RSTR1_TIM6RST (1 << 4) /* Bit 4: TIM6 reset */
#define RCC_APB1RSTR1_TIM7RST (1 << 5) /* Bit 5: TIM7 reset */
#define RCC_APB1RSTR1_SPI2RST (1 << 14) /* Bit 14: SPI2 reset */
#define RCC_APB1RSTR1_SPI3RST (1 << 15) /* Bit 15: SPI3 reset */
#define RCC_APB1RSTR1_USART2RST (1 << 17) /* Bit 17: USART2 reset */
#define RCC_APB1RSTR1_USART3RST (1 << 18) /* Bit 18: USART3 reset */
#define RCC_APB1RSTR1_UART4RST (1 << 19) /* Bit 19: USART4 reset */
#define RCC_APB1RSTR1_UART5RST (1 << 20) /* Bit 20: USART5 reset */
#define RCC_APB1RSTR1_I2C1RST (1 << 21) /* Bit 21: I2C1 reset */
#define RCC_APB1RSTR1_I2C2RST (1 << 22) /* Bit 22: I2C2 reset */
#define RCC_APB1RSTR1_I2C3RST (1 << 23) /* Bit 23: I2C3 reset */
#define RCC_APB1RSTR1_CAN1RST (1 << 25) /* Bit 25: CAN1 reset */
#define RCC_APB1RSTR1_PWRRST (1 << 28) /* Bit 28: Power interface reset */
#define RCC_APB1RSTR1_DAC1RST (1 << 29) /* Bit 29: DAC1 reset */
#define RCC_APB1RSTR1_OPAMPRST (1 << 30) /* Bit 30: OPAMP reset */
#define RCC_APB1RSTR1_LPTIM1RST (1 << 31) /* Bit 31: Low-power Timer 1 reset */
/* APB1 Peripheral reset register 2 */
#define RCC_APB1RSTR2_LPUART1RST (1 << 0) /* Bit 0: Low-power UART 1 reset */
#define RCC_APB1RSTR2_SWPMI1RST (1 << 2) /* Bit 2: Single Wire Protocol reset */
#define RCC_APB1RSTR2_LPTIM2RST (1 << 5) /* Bit 5: Low-power Timer 2 reset */
/* APB2 Peripheral reset register */
#define RCC_APB2RSTR_SYSCFGRST (1 << 0) /* Bit 0: System configuration controller reset */
#define RCC_APB2RSTR_SDMMCRST (1 << 10) /* Bit 10: SDMMC reset */
#define RCC_APB2RSTR_TIM1RST (1 << 11) /* Bit 11: TIM1 reset */
#define RCC_APB2RSTR_SPI1RST (1 << 12) /* Bit 12: SPI1 reset */
#define RCC_APB2RSTR_TIM8RST (1 << 13) /* Bit 13: TIM8 reset */
#define RCC_APB2RSTR_USART1RST (1 << 14) /* Bit 14: USART1 reset */
#define RCC_APB2RSTR_TIM15RST (1 << 16) /* Bit 16: TIM15 reset */
#define RCC_APB2RSTR_TIM16RST (1 << 17) /* Bit 17: TIM16 reset */
#define RCC_APB2RSTR_TIM17RST (1 << 18) /* Bit 18: TIM17 reset */
#define RCC_APB2RSTR_SAI1RST (1 << 21) /* Bit 21: SAI1 reset */
#define RCC_APB2RSTR_SAI2RST (1 << 22) /* Bit 22: SAI2 reset */
#define RCC_APB2RSTR_DFSDMRST (1 << 24) /* Bit 24: DFSDM reset */
/* AHB1 Peripheral Clock enable register */
#define RCC_AHB1ENR_DMA1EN (1 << 0) /* Bit 0: DMA1 enable */
#define RCC_AHB1ENR_DMA2EN (1 << 1) /* Bit 1: DMA2 enable */
#define RCC_AHB1ENR_FLASHEN (1 << 8) /* Bit 8: Flash memory interface enable */
#define RCC_AHB1ENR_CRCEN (1 << 12) /* Bit 12: CRC enable */
#define RCC_AHB1ENR_TSCEN (1 << 16) /* Bit 16: Touch Sensing Controller enable */
/* AHB2 Peripheral Clock enable register */
#define RCC_AHB2ENR_GPIOAEN (1 << 0) /* Bit 0: IO port A enable */
#define RCC_AHB2ENR_GPIOBEN (1 << 1) /* Bit 1: IO port B enable */
#define RCC_AHB2ENR_GPIOCEN (1 << 2) /* Bit 2: IO port C enable */
#define RCC_AHB2ENR_GPIODEN (1 << 3) /* Bit 3: IO port D enable */
#define RCC_AHB2ENR_GPIOEEN (1 << 4) /* Bit 4: IO port E enable */
#define RCC_AHB2ENR_GPIOFEN (1 << 5) /* Bit 5: IO port F enable */
#define RCC_AHB2ENR_GPIOGEN (1 << 6) /* Bit 6: IO port G enable */
#define RCC_AHB2ENR_GPIOHEN (1 << 7) /* Bit 7: IO port H enable */
#define RCC_AHB2ENR_OTGFSEN (1 << 12) /* Bit 12: USB OTG FS module enable */
#define RCC_AHB2ENR_ADCEN (1 << 13) /* Bit 13: ADC interface enable (common to all ADCs) */
#define RCC_AHB2ENR_RNGEN (1 << 18) /* Bit 18: Random number generator module enable */
/* AHB3 Peripheral Clock enable register */
#define RCC_AHB3ENR_FSMCEN (1 << 0) /* Bit 0: Flexible static memory controller module enable */
#define RCC_AHB3ENR_QSPIEN (1 << 8) /* Bit 8: Quad SPI module enable */
/* APB1 Peripheral Clock enable register 1 */
#define RCC_APB1ENR1_TIM2EN (1 << 0) /* Bit 0: TIM2 enable */
#define RCC_APB1ENR1_TIM3EN (1 << 1) /* Bit 1: TIM3 enable */
#define RCC_APB1ENR1_TIM4EN (1 << 2) /* Bit 2: TIM4 enable */
#define RCC_APB1ENR1_TIM5EN (1 << 3) /* Bit 3: TIM5 enable */
#define RCC_APB1ENR1_TIM6EN (1 << 4) /* Bit 4: TIM6 enable */
#define RCC_APB1ENR1_TIM7EN (1 << 5) /* Bit 5: TIM7 enable */
#define RCC_APB1ENR1_WWDGEN (1 << 11) /* Bit 11: Windowed Watchdog enable */
#define RCC_APB1ENR1_SPI2EN (1 << 14) /* Bit 14: SPI2 enable */
#define RCC_APB1ENR1_SPI3EN (1 << 15) /* Bit 15: SPI3 enable */
#define RCC_APB1ENR1_USART2EN (1 << 17) /* Bit 17: USART2 enable */
#define RCC_APB1ENR1_USART3EN (1 << 18) /* Bit 18: USART3 enable */
#define RCC_APB1ENR1_UART4EN (1 << 19) /* Bit 19: USART4 enable */
#define RCC_APB1ENR1_UART5EN (1 << 20) /* Bit 20: USART5 enable */
#define RCC_APB1ENR1_I2C1EN (1 << 21) /* Bit 21: I2C1 enable */
#define RCC_APB1ENR1_I2C2EN (1 << 22) /* Bit 22: I2C2 enable */
#define RCC_APB1ENR1_I2C3EN (1 << 23) /* Bit 23: I2C3 enable */
#define RCC_APB1ENR1_CAN1EN (1 << 25) /* Bit 25: CAN1 enable */
#define RCC_APB1ENR1_PWREN (1 << 28) /* Bit 28: Power interface enable */
#define RCC_APB1ENR1_DAC1EN (1 << 29) /* Bit 29: DAC1 enable */
#define RCC_APB1ENR1_OPAMPEN (1 << 30) /* Bit 30: OPAMP enable */
#define RCC_APB1ENR1_LPTIM1EN (1 << 31) /* Bit 31: Low-power Timer 1 enable */
/* APB1 Peripheral Clock enable register 2 */
#define RCC_APB1ENR2_LPUART1EN (1 << 0) /* Bit 0: Low-power UART 1 enable */
#define RCC_APB1ENR2_SWPMI1EN (1 << 2) /* Bit 2: Single Wire Protocol enable */
#define RCC_APB1ENR2_LPTIM2EN (1 << 5) /* Bit 5: Low-power Timer 2 enable */
/* APB2 Peripheral Clock enable register */
#define RCC_APB2ENR_SYSCFGEN (1 << 0) /* Bit 0: System configuration controller enable */
#define RCC_APB2ENR_FWEN (1 << 7) /* Bit 7: Firewall enable */
#define RCC_APB2ENR_SDMMCEN (1 << 10) /* Bit 10: SDMMC enable */
#define RCC_APB2ENR_TIM1EN (1 << 11) /* Bit 11: TIM1 enable */
#define RCC_APB2ENR_SPI1EN (1 << 12) /* Bit 12: SPI1 enable */
#define RCC_APB2ENR_TIM8EN (1 << 13) /* Bit 13: TIM8 enable */
#define RCC_APB2ENR_USART1EN (1 << 14) /* Bit 14: USART1 enable */
#define RCC_APB2ENR_TIM15EN (1 << 16) /* Bit 16: TIM15 enable */
#define RCC_APB2ENR_TIM16EN (1 << 17) /* Bit 17: TIM16 enable */
#define RCC_APB2ENR_TIM17EN (1 << 18) /* Bit 18: TIM17 enable */
#define RCC_APB2ENR_SAI1EN (1 << 21) /* Bit 21: SAI1 enable */
#define RCC_APB2ENR_SAI2EN (1 << 22) /* Bit 22: SAI2 enable */
#define RCC_APB2ENR_DFSDMEN (1 << 24) /* Bit 24: DFSDM enable */
/* RCC AHB1 low power mode peripheral clock enable register */
#define RCC_AHB1SMENR_DMA1LPSMEN (1 << 0) /* Bit 0: DMA1 enable during Sleep mode */
#define RCC_AHB1SMENR_DMA2LPSMEN (1 << 1) /* Bit 1: DMA2 enable during Sleep mode */
#define RCC_AHB1SMENR_FLASHLPSMEN (1 << 8) /* Bit 8: Flash memory interface enable during Sleep mode */
#define RCC_AHB1SMENR_SRAM1SMEN (1 << 9) /* Bit 9: SRAM1 enable during Sleep mode */
#define RCC_AHB1SMENR_CRCLPSMEN (1 << 12) /* Bit 12: CRC enable during Sleep mode */
#define RCC_AHB1SMENR_TSCLPSMEN (1 << 16) /* Bit 16: Touch Sensing Controller enable during Sleep mode */
/* RCC AHB2 low power mode peripheral clock enable register */
#define RCC_AHB2SMENR_GPIOASMEN (1 << 0) /* Bit 0: IO port A enable during Sleep mode */
#define RCC_AHB2SMENR_GPIOBSMEN (1 << 1) /* Bit 1: IO port B enable during Sleep mode */
#define RCC_AHB2SMENR_GPIOCSMEN (1 << 2) /* Bit 2: IO port C enable during Sleep mode */
#define RCC_AHB2SMENR_GPIODSMEN (1 << 3) /* Bit 3: IO port D enable during Sleep mode */
#define RCC_AHB2SMENR_GPIOESMEN (1 << 4) /* Bit 4: IO port E enable during Sleep mode */
#define RCC_AHB2SMENR_GPIOFSMEN (1 << 5) /* Bit 5: IO port F enable during Sleep mode */
#define RCC_AHB2SMENR_GPIOGSMEN (1 << 6) /* Bit 6: IO port G enable during Sleep mode */
#define RCC_AHB2SMENR_GPIOHSMEN (1 << 7) /* Bit 7: IO port H enable during Sleep mode */
#define RCC_AHB2SMENR_SRAM2SMEN (1 << 9) /* Bit 9: SRAM2 enable during Sleep mode */
#define RCC_AHB2SMENR_OTGFSSMEN (1 << 12) /* Bit 12: USB OTG FS module enable during Sleep mode */
#define RCC_AHB2SMENR_ADCSMEN (1 << 13) /* Bit 13: ADC interface enable during Sleep mode (common to all ADCs) */
#define RCC_AHB2SMENR_RNGSMEN (1 << 18) /* Bit 18: Random number generator module enable during Sleep mode */
/* RCC AHB3 low power mode peripheral clock enable register */
#define RCC_AHB3SMENR_FSMCSMEN (1 << 0) /* Bit 0: Flexible static memory controller module enable during Sleep mode */
#define RCC_AHB3SMENR_QSPISMEN (1 << 8) /* Bit 8: Quad SPI module enable during Sleep mode */
/* RCC APB1 low power mode peripheral clock enable register 1 */
#define RCC_APB1SMENR1_TIM2SMEN (1 << 0) /* Bit 0: TIM2 enable during Sleep mode */
#define RCC_APB1SMENR1_TIM3SMEN (1 << 1) /* Bit 1: TIM3 enable during Sleep mode */
#define RCC_APB1SMENR1_TIM4SMEN (1 << 2) /* Bit 2: TIM4 enable during Sleep mode */
#define RCC_APB1SMENR1_TIM5SMEN (1 << 3) /* Bit 3: TIM5 enable during Sleep mode */
#define RCC_APB1SMENR1_TIM6SMEN (1 << 4) /* Bit 4: TIM6 enable during Sleep mode */
#define RCC_APB1SMENR1_TIM7SMEN (1 << 5) /* Bit 5: TIM7 enable during Sleep mode */
#define RCC_APB1SMENR1_WWDGSMEN (1 << 11) /* Bit 11: Windowed Watchdog enable during Sleep mode */
#define RCC_APB1SMENR1_SPI2SMEN (1 << 14) /* Bit 14: SPI2 enable during Sleep mode */
#define RCC_APB1SMENR1_SPI3SMEN (1 << 15) /* Bit 15: SPI3 enable during Sleep mode */
#define RCC_APB1SMENR1_USART2SMEN (1 << 17) /* Bit 17: USART2 enable during Sleep mode */
#define RCC_APB1SMENR1_USART3SMEN (1 << 18) /* Bit 18: USART3 enable during Sleep mode */
#define RCC_APB1SMENR1_UART4SMEN (1 << 19) /* Bit 19: USART4 enable during Sleep mode */
#define RCC_APB1SMENR1_UART5SMEN (1 << 20) /* Bit 20: USART5 enable during Sleep mode */
#define RCC_APB1SMENR1_I2C1SMEN (1 << 21) /* Bit 21: I2C1 enable during Sleep mode */
#define RCC_APB1SMENR1_I2C2SMEN (1 << 22) /* Bit 22: I2C2 enable during Sleep mode */
#define RCC_APB1SMENR1_I2C3SMEN (1 << 23) /* Bit 23: I2C3 enable during Sleep mode */
#define RCC_APB1SMENR1_CAN1SMEN (1 << 25) /* Bit 25: CAN1 enable during Sleep mode */
#define RCC_APB1SMENR1_PWRSMEN (1 << 28) /* Bit 28: Power interface enable during Sleep mode */
#define RCC_APB1SMENR1_DAC1SMEN (1 << 29) /* Bit 29: DAC1 enable during Sleep mode */
#define RCC_APB1SMENR1_OPAMPSMEN (1 << 30) /* Bit 30: OPAMP enable during Sleep mode */
#define RCC_APB1SMENR1_LPTIM1SMEN (1 << 31) /* Bit 31: Low-power Timer 1 enable during Sleep mode */
/* RCC APB1 low power modeperipheral clock enable register 2 */
#define RCC_APB1SMENR2_LPUART1SMEN (1 << 0) /* Bit 0: Low-power UART 1 enable during Sleep mode */
#define RCC_APB1SMENR2_SWPMI1SMEN (1 << 2) /* Bit 2: Single Wire Protocol enable during Sleep mode */
#define RCC_APB1SMENR2_LPTIM2SMEN (1 << 5) /* Bit 5: Low-power Timer 2 enable during Sleep mode */
/* RCC APB2 low power mode peripheral clock enable register */
#define RCC_APB2SMENR_SYSCFGSMEN (1 << 0) /* Bit 0: System configuration controller enable during Sleep mode */
#define RCC_APB2SMENR_SDMMCSMEN (1 << 10) /* Bit 10: SDMMC enable during Sleep mode */
#define RCC_APB2SMENR_TIM1SMEN (1 << 11) /* Bit 11: TIM1 enable during Sleep mode */
#define RCC_APB2SMENR_SPI1SMEN (1 << 12) /* Bit 12: SPI1 enable during Sleep mode */
#define RCC_APB2SMENR_TIM8SMEN (1 << 13) /* Bit 13: TIM8 enable during Sleep mode */
#define RCC_APB2SMENR_USART1SMEN (1 << 14) /* Bit 14: USART1 enable during Sleep mode */
#define RCC_APB2SMENR_TIM15SMEN (1 << 16) /* Bit 16: TIM15 enable during Sleep mode */
#define RCC_APB2SMENR_TIM16SMEN (1 << 17) /* Bit 17: TIM16 enable during Sleep mode */
#define RCC_APB2SMENR_TIM17SMEN (1 << 18) /* Bit 18: TIM17 enable during Sleep mode */
#define RCC_APB2SMENR_SAI1SMEN (1 << 21) /* Bit 21: SAI1 enable during Sleep mode */
#define RCC_APB2SMENR_SAI2SMEN (1 << 22) /* Bit 22: SAI2 enable during Sleep mode */
#define RCC_APB2SMENR_DFSDMSMEN (1 << 24) /* Bit 24: DFSDM enable during Sleep mode */
/* Peripheral Independent Clock Configuration register */
#define RCC_CCIPR_USART1SEL_SHIFT (0)
#define RCC_CCIPR_USART1SEL_MASK (3 << RCC_CCIPR_USART1SEL_SHIFT)
# define RCC_CCIPR_USART1SEL_PCLK (0 << RCC_CCIPR_USART1SEL_SHIFT)
# define RCC_CCIPR_USART1SEL_SYSCLK (1 << RCC_CCIPR_USART1SEL_SHIFT)
# define RCC_CCIPR_USART1SEL_HSI (2 << RCC_CCIPR_USART1SEL_SHIFT)
# define RCC_CCIPR_USART1SEL_LSE (3 << RCC_CCIPR_USART1SEL_SHIFT)
#define RCC_CCIPR_USART2SEL_SHIFT (2)
#define RCC_CCIPR_USART2SEL_MASK (3 << RCC_CCIPR_USART2SEL_SHIFT)
# define RCC_CCIPR_USART2SEL_PCLK (0 << RCC_CCIPR_USART2SEL_SHIFT)
# define RCC_CCIPR_USART2SEL_SYSCLK (1 << RCC_CCIPR_USART2SEL_SHIFT)
# define RCC_CCIPR_USART2SEL_HSI (2 << RCC_CCIPR_USART2SEL_SHIFT)
# define RCC_CCIPR_USART2SEL_LSE (3 << RCC_CCIPR_USART2SEL_SHIFT)
#define RCC_CCIPR_USART3SEL_SHIFT (4)
#define RCC_CCIPR_USART3SEL_MASK (3 << RCC_CCIPR_USART3SEL_SHIFT)
# define RCC_CCIPR_USART3SEL_PCLK (0 << RCC_CCIPR_USART3SEL_SHIFT)
# define RCC_CCIPR_USART3SEL_SYSCLK (1 << RCC_CCIPR_USART3SEL_SHIFT)
# define RCC_CCIPR_USART3SEL_HSI (2 << RCC_CCIPR_USART3SEL_SHIFT)
# define RCC_CCIPR_USART3SEL_LSE (3 << RCC_CCIPR_USART3SEL_SHIFT)
#define RCC_CCIPR_UART4SEL_SHIFT (6)
#define RCC_CCIPR_UART4SEL_MASK (3 << RCC_CCIPR_UART4SEL_SHIFT)
# define RCC_CCIPR_UART4SEL_PCLK (0 << RCC_CCIPR_UART4SEL_SHIFT)
# define RCC_CCIPR_UART4SEL_SYSCLK (1 << RCC_CCIPR_UART4SEL_SHIFT)
# define RCC_CCIPR_UART4SEL_HSI (2 << RCC_CCIPR_UART4SEL_SHIFT)
# define RCC_CCIPR_UART4SEL_LSE (3 << RCC_CCIPR_UART4SEL_SHIFT)
#define RCC_CCIPR_UART5SEL_SHIFT (8)
#define RCC_CCIPR_UART5SEL_MASK (3 << RCC_CCIPR_UART5SEL_SHIFT)
# define RCC_CCIPR_UART5SEL_PCLK (0 << RCC_CCIPR_UART5SEL_SHIFT)
# define RCC_CCIPR_UART5SEL_SYSCLK (1 << RCC_CCIPR_UART5SEL_SHIFT)
# define RCC_CCIPR_UART5SEL_HSI (2 << RCC_CCIPR_UART5SEL_SHIFT)
# define RCC_CCIPR_UART5SEL_LSE (3 << RCC_CCIPR_UART5SEL_SHIFT)
#define RCC_CCIPR_LPUART1SEL_SHIFT (10)
#define RCC_CCIPR_LPUART1SEL_MASK (3 << RCC_CCIPR_LPUART1SEL_SHIFT)
# define RCC_CCIPR_LPUART1SEL_PCLK (0 << RCC_CCIPR_LPUART1SEL_SHIFT)
# define RCC_CCIPR_LPUART1SEL_SYSCLK (1 << RCC_CCIPR_LPUART1SEL_SHIFT)
# define RCC_CCIPR_LPUART1SEL_HSI (2 << RCC_CCIPR_LPUART1SEL_SHIFT)
# define RCC_CCIPR_LPUART1SEL_LSE (3 << RCC_CCIPR_LPUART1SEL_SHIFT)
#define RCC_CCIPR_I2C1SEL_SHIFT (12)
#define RCC_CCIPR_I2C1SEL_MASK (3 << RCC_CCIPR_I2C1SEL_SHIFT)
# define RCC_CCIPR_I2C1SEL_PCLK (0 << RCC_CCIPR_I2C1SEL_SHIFT)
# define RCC_CCIPR_I2C1SEL_SYSCLK (1 << RCC_CCIPR_I2C1SEL_SHIFT)
# define RCC_CCIPR_I2C1SEL_HSI (2 << RCC_CCIPR_I2C1SEL_SHIFT)
#define RCC_CCIPR_I2C2SEL_SHIFT (14)
#define RCC_CCIPR_I2C2SEL_MASK (3 << RCC_CCIPR_I2C2SEL_SHIFT)
# define RCC_CCIPR_I2C2SEL_PCLK (0 << RCC_CCIPR_I2C2SEL_SHIFT)
# define RCC_CCIPR_I2C2SEL_SYSCLK (1 << RCC_CCIPR_I2C2SEL_SHIFT)
# define RCC_CCIPR_I2C2SEL_HSI (2 << RCC_CCIPR_I2C2SEL_SHIFT)
#define RCC_CCIPR_I2C3SEL_SHIFT (16)
#define RCC_CCIPR_I2C3SEL_MASK (3 << RCC_CCIPR_I2C3SEL_SHIFT)
# define RCC_CCIPR_I2C3SEL_PCLK (0 << RCC_CCIPR_I2C3SEL_SHIFT)
# define RCC_CCIPR_I2C3SEL_SYSCLK (1 << RCC_CCIPR_I2C3SEL_SHIFT)
# define RCC_CCIPR_I2C3SEL_HSI (2 << RCC_CCIPR_I2C3SEL_SHIFT)
#define RCC_CCIPR_LPTIM1SEL_SHIFT (18)
#define RCC_CCIPR_LPTIM1SEL_MASK (3 << RCC_CCIPR_LPTIM1SEL_SHIFT)
# define RCC_CCIPR_LPTIM1SEL_PCLK (0 << RCC_CCIPR_LPTIM1SEL_SHIFT)
# define RCC_CCIPR_LPTIM1SEL_LSI (1 << RCC_CCIPR_LPTIM1SEL_SHIFT)
# define RCC_CCIPR_LPTIM1SEL_HSI (2 << RCC_CCIPR_LPTIM1SEL_SHIFT)
# define RCC_CCIPR_LPTIM1SEL_LSE (3 << RCC_CCIPR_LPTIM1SEL_SHIFT)
#define RCC_CCIPR_LPTIM2SEL_SHIFT (20)
#define RCC_CCIPR_LPTIM2SEL_MASK (3 << RCC_CCIPR_LPTIM2SEL_SHIFT)
# define RCC_CCIPR_LPTIM2SEL_PCLK (0 << RCC_CCIPR_LPTIM2SEL_SHIFT)
# define RCC_CCIPR_LPTIM2SEL_LSI (1 << RCC_CCIPR_LPTIM2SEL_SHIFT)
# define RCC_CCIPR_LPTIM2SEL_HSI (2 << RCC_CCIPR_LPTIM2SEL_SHIFT)
# define RCC_CCIPR_LPTIM2SEL_LSE (3 << RCC_CCIPR_LPTIM2SEL_SHIFT)
#define RCC_CCIPR_SAI1SEL_SHIFT (22)
#define RCC_CCIPR_SAI1SEL_MASK (3 << RCC_CCIPR_SAI1SEL_SHIFT)
# define RCC_CCIPR_SAI1SEL_PLLSAI1 (0 << RCC_CCIPR_SAI1SEL_SHIFT)
# define RCC_CCIPR_SAI1SEL_PLLSAI2 (1 << RCC_CCIPR_SAI1SEL_SHIFT)
# define RCC_CCIPR_SAI1SEL_PLLMAIN (2 << RCC_CCIPR_SAI1SEL_SHIFT)
# define RCC_CCIPR_SAI1SEL_EXTCLK (3 << RCC_CCIPR_SAI1SEL_SHIFT)
#define RCC_CCIPR_SAI2SEL_SHIFT (24)
#define RCC_CCIPR_SAI2SEL_MASK (3 << RCC_CCIPR_SAI2SEL_SHIFT)
# define RCC_CCIPR_SAI2SEL_PLLSAI1 (0 << RCC_CCIPR_SAI2SEL_SHIFT)
# define RCC_CCIPR_SAI2SEL_PLLSAI2 (1 << RCC_CCIPR_SAI2SEL_SHIFT)
# define RCC_CCIPR_SAI2SEL_PLLMAIN (2 << RCC_CCIPR_SAI2SEL_SHIFT)
# define RCC_CCIPR_SAI2SEL_EXTCLK (3 << RCC_CCIPR_SAI2SEL_SHIFT)
#define RCC_CCIPR_CLK48SEL_SHIFT (26)
#define RCC_CCIPR_CLK48SEL_MASK (3 << RCC_CCIPR_CLK48SEL_SHIFT)
# define RCC_CCIPR_CLK48SEL_NONE (0 << RCC_CCIPR_CLK48SEL_SHIFT)
# define RCC_CCIPR_CLK48SEL_PLLSAI1 (1 << RCC_CCIPR_CLK48SEL_SHIFT)
# define RCC_CCIPR_CLK48SEL_PLLMAIN (2 << RCC_CCIPR_CLK48SEL_SHIFT)
# define RCC_CCIPR_CLK48SEL_MSI (3 << RCC_CCIPR_CLK48SEL_SHIFT)
#define RCC_CCIPR_ADCSEL_SHIFT (28)
#define RCC_CCIPR_ADCSEL_MASK (3 << RCC_CCIPR_ADCSEL_SHIFT)
# define RCC_CCIPR_ADCSEL_NONE (0 << RCC_CCIPR_ADCSEL_SHIFT)
# define RCC_CCIPR_ADCSEL_PLLSAI1 (1 << RCC_CCIPR_ADCSEL_SHIFT)
# define RCC_CCIPR_ADCSEL_PLLSAI2 (2 << RCC_CCIPR_ADCSEL_SHIFT)
# define RCC_CCIPR_ADCSEL_SYSCLK (3 << RCC_CCIPR_ADCSEL_SHIFT)
#define RCC_CCIPR_SWPMI1SEL (1 << 30)
# define RCC_CCIPR_SWPMI1SEL_PCLK 0
# define RCC_CCIPR_SWPMI1SEL_HSI RCC_CCIPR_SWPMI1SEL
#define RCC_CCIPR_DFSDMSEL (1 << 31)
# define RCC_CCIPR_DFSDMSEL_PCLK 0
# define RCC_CCIPR_DFSDMSEL_SYSCLK RCC_CCIPR_DFSDMSEL
/* Backup domain control register */
#define RCC_BDCR_LSEON (1 << 0) /* Bit 0: External Low Speed oscillator enable */
#define RCC_BDCR_LSERDY (1 << 1) /* Bit 1: External Low Speed oscillator Ready */
#define RCC_BDCR_LSEBYP (1 << 2) /* Bit 2: External Low Speed oscillator Bypass */
#define RCC_BDCR_LSEDRV_SHIFT (3) /* Bits 3-4: LSE oscillator drive capability */
#define RCC_BDCR_LSEDRV_MASK (3 << RCC_BDCR_LSEDRV_SHIFT)
# define RCC_BDCR_LSEDRV_LOWER (0 << RCC_BDCR_LSEDRV_SHIFT) /* 00: Lower driving capability */
# define RCC_BDCR_LSEDRV_MIDLOW (1 << RCC_BDCR_LSEDRV_SHIFT) /* 01: Medium Low driving capability */
# define RCC_BDCR_LSEDRV_MIDHI (2 << RCC_BDCR_LSEDRV_SHIFT) /* 10: Medium High driving capability*/
# define RCC_BDCR_LSEDRV_HIGER (3 << RCC_BDCR_LSEDRV_SHIFT) /* 11: Higher driving capability */
#define RCC_BDCR_LSECSSON (1 << 5) /* Bit 5: CSS on LSE enable */
#define RCC_BDCR_LSECSSD (1 << 6) /* Bit 6: CSS on LSE failure Detection */
#define RCC_BDCR_RTCSEL_SHIFT (8) /* Bits 9:8: RTC clock source selection */
#define RCC_BDCR_RTCSEL_MASK (3 << RCC_BDCR_RTCSEL_SHIFT)
# define RCC_BDCR_RTCSEL_NOCLK (0 << RCC_BDCR_RTCSEL_SHIFT) /* 00: No clock */
# define RCC_BDCR_RTCSEL_LSE (1 << RCC_BDCR_RTCSEL_SHIFT) /* 01: LSE oscillator clock used as RTC clock */
# define RCC_BDCR_RTCSEL_LSI (2 << RCC_BDCR_RTCSEL_SHIFT) /* 10: LSI oscillator clock used as RTC clock */
# define RCC_BDCR_RTCSEL_HSE (3 << RCC_BDCR_RTCSEL_SHIFT) /* 11: HSE oscillator clock divided by 32 used as RTC clock */
#define RCC_BDCR_RTCEN (1 << 15) /* Bit 15: RTC clock enable */
#define RCC_BDCR_BDRST (1 << 16) /* Bit 16: Backup domain software reset */
#define RCC_BDCR_LSCOEN (1 << 24) /* Bit 24: Low speed clock output enable */
#define RCC_BDCR_LSCOSEL (1 << 25) /* Bit 25: Low speed clock output selection */
# define RCC_BCDR_LSCOSEL_LSI 0 /* LSI selected */
# define RCC_BDCR_LSCOSEL_LSE RCC_BDCR_LSCOSEL /* LSE selected */
/* Control/status register */
#define RCC_CSR_LSION (1 << 0) /* Bit 0: Internal Low Speed oscillator enable */
#define RCC_CSR_LSIRDY (1 << 1) /* Bit 1: Internal Low Speed oscillator Ready */
#define RCC_CSR_MSISRANGE_SHIFT 8
# define RCC_CSR_MSISRANGE_MASK (0x0F << RCC_CSR_MSISRANGE_SHIFT) /* MSI range after Standby mode */
# define RCC_CSR_MSISRANGE_1M (4 << RCC_CSR_MSISRANGE_SHIFT) /* 0100: around 1 MHz */
# define RCC_CSR_MSISRANGE_2M (5 << RCC_CSR_MSISRANGE_SHIFT) /* 0101: around 2 MHz */
# define RCC_CSR_MSISRANGE_4M (6 << RCC_CSR_MSISRANGE_SHIFT) /* 0110: around 4 MHz */
# define RCC_CSR_MSISRANGE_8M (7 << RCC_CSR_MSISRANGE_SHIFT) /* 0111: around 8 MHz */
#define RCC_CSR_RMVF (1 << 23) /* Bit 23: Remove reset flag */
#define RCC_CSR_FWRSTF (1 << 24) /* Bit 24: Firewall reset flag */
#define RCC_CSR_OBLRSTF (1 << 25) /* Bit 25: Option byte loader reset flag */
#define RCC_CSR_PINRSTF (1 << 26) /* Bit 26: PIN reset flag */
#define RCC_CSR_BORRSTF (1 << 27) /* Bit 27: BOR reset flag */
#define RCC_CSR_SFTRSTF (1 << 28) /* Bit 28: Software Reset flag */
#define RCC_CSR_IWDGRSTF (1 << 29) /* Bit 29: Independent Watchdog reset flag */
#define RCC_CSR_WWDGRSTF (1 << 30) /* Bit 30: Window watchdog reset flag */
#define RCC_CSR_LPWRRSTF (1 << 31) /* Bit 31: Low-Power reset flag */
#endif /* CONFIG_STM32L4_STM32L4X5 */
#endif /* __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4X5XX_RCC_H */

177
arch/arm/src/stm32l4/chip/stm32l4x5xx_syscfg.h Normal file
View file

@ -0,0 +1,177 @@
/****************************************************************************************************
* arch/arm/src/stm32l4/chip/stm32l4x5xx_syscfg.h
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4X5XX_SYSCFG_H
#define __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4X5XX_SYSCFG_H
/****************************************************************************************************
* Included Files
****************************************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#if defined(CONFIG_STM32L4_STM32L4X5)
/****************************************************************************************************
* Pre-processor Definitions
****************************************************************************************************/
/* Register Offsets *********************************************************************************/
#define STM32L4_SYSCFG_MEMRMP_OFFSET 0x0000 /* SYSCFG memory remap register */
#define STM32L4_SYSCFG_CFGR1_OFFSET 0x0004 /* SYSCFG configuration register 1 */
#define STM32L4_SYSCFG_EXTICR_OFFSET(p) (0x0008 + ((p) & 0x000c)) /* Registers are displaced by 4! */
#define STM32L4_SYSCFG_EXTICR1_OFFSET 0x0008 /* SYSCFG external interrupt configuration register 1 */
#define STM32L4_SYSCFG_EXTICR2_OFFSET 0x000c /* SYSCFG external interrupt configuration register 2 */
#define STM32L4_SYSCFG_EXTICR3_OFFSET 0x0010 /* SYSCFG external interrupt configuration register 3 */
#define STM32L4_SYSCFG_EXTICR4_OFFSET 0x0014 /* SYSCFG external interrupt configuration register 4 */
#define STM32L4_SYSCFG_SCSR_OFFSET 0x0018 /* SYSCFG SRAM2 control and status register */
#define STM32L4_SYSCFG_CFGR2_OFFSET 0x001c /* SYSCFG configuration register 2 */
#define STM32L4_SYSCFG_SWPR_OFFSET 0x0020 /* SYSCFG SRAM2 write protection register */
#define STM32L4_SYSCFG_SKR_OFFSET 0x0024 /* SYSCFG SRAM2 key register */
/* Register Addresses *******************************************************************************/
#define STM32L4_SYSCFG_MEMRMP (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_MEMRMP_OFFSET)
#define STM32L4_SYSCFG_CFGR1 (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_CFGR1_OFFSET)
#define STM32L4_SYSCFG_EXTICR(p) (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_EXTICR_OFFSET(p))
#define STM32L4_SYSCFG_EXTICR1 (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_EXTICR1_OFFSET)
#define STM32L4_SYSCFG_EXTICR2 (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_EXTICR2_OFFSET)
#define STM32L4_SYSCFG_EXTICR3 (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_EXTICR3_OFFSET)
#define STM32L4_SYSCFG_EXTICR4 (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_EXTICR4_OFFSET)
#define STM32L4_SYSCFG_SCSR (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_SCSR_OFFSET)
#define STM32L4_SYSCFG_CFGR2 (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_CFGR2_OFFSET)
#define STM32L4_SYSCFG_SWPR (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_SWPR_OFFSET)
#define STM32L4_SYSCFG_SKR (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_SKR_OFFSET)
/* Register Bitfield Definitions ********************************************************************/
/* SYSCFG memory remap register */
#define SYSCFG_MEMRMP_SHIFT (0) /* Bits 2:0 MEM_MODE: Memory mapping selection */
#define SYSCFG_MEMRMP_MASK (7 << SYSCFG_MEMRMP_SHIFT)
# define SYSCFG_MEMRMP_FLASH (0 << SYSCFG_MEMRMP_SHIFT) /* 000: Main Flash memory mapped at 0x0000 0000 */
# define SYSCFG_MEMRMP_SYSTEM (1 << SYSCFG_MEMRMP_SHIFT) /* 001: System Flash memory mapped at 0x0000 0000 */
# define SYSCFG_MEMRMP_FMC (2 << SYSCFG_MEMRMP_SHIFT) /* 010: FSMC Bank1 (NOR/PSRAM 1 and 2) mapped at 0x0000 0000 */
# define SYSCFG_MEMRMP_SRAM (3 << SYSCFG_MEMRMP_SHIFT) /* 011: SRAM1 (112kB) mapped at 0x0000 0000 */
# define SYSCFG_MEMRMP_QSPI (6 << SYSCFG_MEMRMP_SHIFT) /* 110: QUADSPI mapped at 0x0000 0000 */
#define SYSCFG_FBMODE (1 << 8) /* Bit 8: Flash Bank mode selection */
/* SYSCFG configuration register 1 */
#define SYSCFG_CFGR1_FWDIS (1 << 0) /* Bit 0: Firewall disable */
#define SYSCFG_CFGR1_BOOSTEN (1 << 8) /* Bit 8: I/O analog switch voltage booster enable (use when vdd is low) */
#define SYSCFG_CFGR1_I2C_PB6_FMP (1 << 16) /* Bit 16: Fast-mode Plus (Fm+) driving capability activation on PB6 */
#define SYSCFG_CFGR1_I2C_PB7_FMP (1 << 17) /* Bit 17: Fast-mode Plus (Fm+) driving capability activation on PB7 */
#define SYSCFG_CFGR1_I2C_PB8_FMP (1 << 18) /* Bit 18: Fast-mode Plus (Fm+) driving capability activation on PB8 */
#define SYSCFG_CFGR1_I2C_PB9_FMP (1 << 19) /* Bit 19: Fast-mode Plus (Fm+) driving capability activation on PB9 */
#define SYSCFG_CFGR1_I2C1_FMP (1 << 20) /* Bit 20: I2C1 Fast-mode Plus (Fm+) driving capability activation */
#define SYSCFG_CFGR1_I2C2_FMP (1 << 21) /* Bit 21: I2C2 Fast-mode Plus (Fm+) driving capability activation */
#define SYSCFG_CFGR1_I2C3_FMP (1 << 22) /* Bit 22: I2C3 Fast-mode Plus (Fm+) driving capability activation */
#define SYSCFG_CFGR1_FPU_IE0 (1 << 26) /* Bit 26: FPU Invalid operation interrupt enable */
#define SYSCFG_CFGR1_FPU_IE1 (1 << 27) /* Bit 27: FPU Divide-by-zero interrupt enable */
#define SYSCFG_CFGR1_FPU_IE2 (1 << 28) /* Bit 28: FPU Underflow interrupt enable */
#define SYSCFG_CFGR1_FPU_IE3 (1 << 29) /* Bit 29: FPU Overflow interrupt enable */
#define SYSCFG_CFGR1_FPU_IE4 (1 << 30) /* Bit 30: FPU Input denormal interrupt enable */
#define SYSCFG_CFGR1_FPU_IE5 (1 << 31) /* Bit 31: FPU Inexact interrupt enable */
/* SYSCFG external interrupt configuration register 1-4 */
#define SYSCFG_EXTICR_PORTA (0) /* 0000: PA[x] pin */
#define SYSCFG_EXTICR_PORTB (1) /* 0001: PB[x] pin */
#define SYSCFG_EXTICR_PORTC (2) /* 0010: PC[x] pin */
#define SYSCFG_EXTICR_PORTD (3) /* 0011: PD[x] pin */
#define SYSCFG_EXTICR_PORTE (4) /* 0100: PE[x] pin */
#define SYSCFG_EXTICR_PORTF (5) /* 0101: PF[C] pin */
#define SYSCFG_EXTICR_PORTG (6) /* 0110: PG[x] pin */
#define SYSCFG_EXTICR_PORTH (7) /* 0111: PH[x] pin (only on STM32L496xx/4A6xx) */
#define SYSCFG_EXTICR_PORTI (8) /* 1000: PI[x] pin (only on STM32L496xx/4A6xx) */
#define SYSCFG_EXTICR_PORT_MASK (15)
#define SYSCFG_EXTICR_EXTI_SHIFT(g) (((g) & 3) << 2)
#define SYSCFG_EXTICR_EXTI_MASK(g) (SYSCFG_EXTICR_PORT_MASK << (SYSCFG_EXTICR_EXTI_SHIFT(g)))
#define SYSCFG_EXTICR1_EXTI0_SHIFT (0) /* Bits 0-2: EXTI 0 configuration */
#define SYSCFG_EXTICR1_EXTI0_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR1_EXTI0_SHIFT)
#define SYSCFG_EXTICR1_EXTI1_SHIFT (4) /* Bits 4-6: EXTI 1 configuration */
#define SYSCFG_EXTICR1_EXTI1_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR1_EXTI1_SHIFT)
#define SYSCFG_EXTICR1_EXTI2_SHIFT (8) /* Bits 8-10: EXTI 2 configuration */
#define SYSCFG_EXTICR1_EXTI2_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR1_EXTI2_SHIFT)
#define SYSCFG_EXTICR1_EXTI3_SHIFT (12) /* Bits 12-14: EXTI 3 configuration */
#define SYSCFG_EXTICR1_EXTI3_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR1_EXTI3_SHIFT)
#define SYSCFG_EXTICR2_EXTI4_SHIFT (0) /* Bits 0-2: EXTI 4 configuration */
#define SYSCFG_EXTICR2_EXTI4_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR2_EXTI4_SHIFT)
#define SYSCFG_EXTICR2_EXTI5_SHIFT (4) /* Bits 4-6: EXTI 5 configuration */
#define SYSCFG_EXTICR2_EXTI5_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR2_EXTI5_SHIFT)
#define SYSCFG_EXTICR2_EXTI6_SHIFT (8) /* Bits 8-10: EXTI 6 configuration */
#define SYSCFG_EXTICR2_EXTI6_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR2_EXTI6_SHIFT)
#define SYSCFG_EXTICR2_EXTI7_SHIFT (12) /* Bits 12-14: EXTI 7 configuration */
#define SYSCFG_EXTICR2_EXTI7_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR2_EXTI7_SHIFT)
#define SYSCFG_EXTICR3_EXTI8_SHIFT (0) /* Bits 0-2: EXTI 8 configuration */
#define SYSCFG_EXTICR3_EXTI8_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR3_EXTI8_SHIFT)
#define SYSCFG_EXTICR3_EXTI9_SHIFT (4) /* Bits 4-6: EXTI 9 configuration */
#define SYSCFG_EXTICR3_EXTI9_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR3_EXTI9_SHIFT)
#define SYSCFG_EXTICR3_EXTI10_SHIFT (8) /* Bits 8-10: EXTI 10 configuration */
#define SYSCFG_EXTICR3_EXTI10_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR3_EXTI10_SHIFT)
#define SYSCFG_EXTICR3_EXTI11_SHIFT (12) /* Bits 12-14: EXTI 11 configuration */
#define SYSCFG_EXTICR3_EXTI11_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR3_EXTI11_SHIFT)
#define SYSCFG_EXTICR4_EXTI12_SHIFT (0) /* Bits 0-2: EXTI 12 configuration */
#define SYSCFG_EXTICR4_EXTI12_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR4_EXTI12_SHIFT)
#define SYSCFG_EXTICR4_EXTI13_SHIFT (4) /* Bits 4-6: EXTI 13 configuration */
#define SYSCFG_EXTICR4_EXTI13_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR4_EXTI13_SHIFT)
#define SYSCFG_EXTICR4_EXTI14_SHIFT (8) /* Bits 8-10: EXTI 14 configuration */
#define SYSCFG_EXTICR4_EXTI14_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR4_EXTI14_SHIFT)
#define SYSCFG_EXTICR4_EXTI15_SHIFT (12) /* Bits 12-14: EXTI 15 configuration */
#define SYSCFG_EXTICR4_EXTI15_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR4_EXTI15_SHIFT)
/* SYSCFG SRAM2 control and status register */
#define SYSCFG_SCSR_SRAM2ER (1 << 0) /* Bit 0: SRAM2 Erase */
#define SYSCFG_SCSR_SRAM2BSY (1 << 1) /* Bit 1: SRAM2 busy in erase operation */
/* SYSCFG configuration register 2 */
#define SYSCFG_CFGR2_CLL (1 << 0) /* Bit 0: Cortex-M4 LOCKUP (Hardfault) output enable (TIMx break enable, see refman) */
#define SYSCFG_CFGR2_SPL (1 << 1) /* Bit 1: SRAM2 parity lock enable (same) */
#define SYSCFG_CFGR2_PVDL (1 << 2) /* Bit 2: PVD lock enable (same) */
#define SYSCFG_CFGR2_ECCL (1 << 3) /* Bit 3: ECC lock enable (same) */
#define SYSCFG_CFGR2_SPF (1 << 8) /* Bit 8: SRAM2 parity error flag */
#endif /* CONFIG_STM32L4_STM32L4X5 */
#endif /* __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4X5XX_SYSCFG_H */

7
arch/arm/src/stm32l4/chip/stm32l4x6xx_firewall.h
View file

@ -72,22 +72,27 @@
/* Register Bitfield Definitions ****************************************************/
/* Code Segment Start Address */
#define FIREWALL_CSSADD_SHIFT 8
#define FIREWALL_CSSADD_MASK (0xFFFF << FIREWALL_CSSADD_SHIFT)
/* Code Segment Length */
#define FIREWALL_CSSLENG_SHIFT 8
#define FIREWALL_CSSLENG_MASK (0x3FFF << FIREWALL_CSSLENG_SHIFT)
/* Non-volatile Data Segment Start Address */
#define FIREWALL_NVDSADD_SHIFT 8
#define FIREWALL_NVDSADD_MASK (0xFFFF << FIREWALL_NVDSADD_SHIFT)
/* Non-volatile Data Segment Length */
#define FIREWALL_NVDSLENG_SHIFT 8
#define FIREWALL_NVDSLENG_MASK (0x3FFF << FIREWALL_NVDSLENG_SHIFT)
/* Volatile Data Segment Start Address */
#define FIREWALL_VDSADD_SHIFT 6
#if defined(CONFIG_STM32L4_STM32L496XX)
#define FIREWALL_VDSADD_MASK (0x0FFF << FIREWALL_VDSADD_SHIFT)
@ -96,6 +101,7 @@
#endif
/* Volatile Data Segment Length */
#define FIREWALL_VDSLENG_SHIFT 6
#if defined(CONFIG_STM32L4_STM32L496XX)
#define FIREWALL_VDSLENG_MASK (0x0FFF << FIREWALL_VDSLENG_SHIFT)
@ -104,6 +110,7 @@
#endif
/* Configuration Register */
#define FIREWALL_CR_FPA (1 << 0) /* Bit 0: Firewall prearm */
#define FIREWALL_CR_VDS (1 << 1) /* Bit 1: Volatile data shared */
#define FIREWALL_CR_VDE (1 << 2) /* Bit 2: Volatile data execution */

58
arch/arm/src/stm32l4/chip/stm32l4x6xx_otgfs.h
View file

@ -439,7 +439,9 @@
# define OTGFS_HNPTXSTS_EPNUM_SHIFT (27) /* Bits 27-30: Endpoint number */
# define OTGFS_HNPTXSTS_EPNUM_MASK (15 << OTGFS_HNPTXSTS_EPNUM_SHIFT)
/* Bit 31 Reserved, must be kept at reset value */
/* General core configuration register */
#define OTGFS_GCCFG_DCDET (1 << 0) /* Bit 0: Data contact detect */
#define OTGFS_GCCFG_PDET (1 << 1) /* Bit 1: Primary detect */
#define OTGFS_GCCFG_SDET (1 << 2) /* Bit 2: Secondary detect */
@ -453,35 +455,48 @@
#define OTGFS_GCCFG_VBDEN (1 << 21) /* Bit 21: USB VBUS detection enable */
/* Bits 22-31: Reserved, must be kept at reset value */
/* Core ID register (32-bit product ID) */
/* Core ID register (32-bit product ID) */
//XXX GLPMCFG
#define OTGFS_GLPMCFG_LPMEN (1 << 0) /* Bit 0: XXX */
#define OTGFS_GLPMCFG_LPMACK (1 << 1) /* Bit 1: XXX */
//#define OTGFS_GLPMCFG_BESL
#define OTGFS_GLPMCFG_REMWAKE (1 << 6) /* Bit 6: XXX */
#define OTGFS_GLPMCFG_L1SSEN (1 << 7) /* Bit 7: XXX */
//#define OTGFS_GLPMCFG_BESLTHRS
/* LPM configuration register */
#define OTGFS_GLPMCFG_LPMEN (1 << 0) /* Bit 0: XXX */
#define OTGFS_GLPMCFG_LPMACK (1 << 1) /* Bit 1: XXX */
#define OTGFS_GLPMCFG_BESL_SHIFT (2) /* Bits 2-5: XXX */
#define OTGFS_GLPMCFG_BESL_MASK (15 << OTGFS_GLPMCFG_BESL_SHIFT)
#define OTGFS_GLPMCFG_REMWAKE (1 << 6) /* Bit 6: XXX */
#define OTGFS_GLPMCFG_L1SSEN (1 << 7) /* Bit 7: XXX */
#define OTGFS_GLPMCFG_BESLTHRS_SHIFT (8) /* Bits 8-11: XXX */
#define OTGFS_GLPMCFG_BESLTHRS_MASK (15 << OTGFS_GLPMCFG_BESLTHRS_SHIFT)
#define OTGFS_GLPMCFG_L1DSEN (1 << 12) /* Bit 12: XXX */
//#define OTGFS_GLPMCFG_LPMRSP
#define OTGFS_GLPMCFG_LPMRSP_SHIFT (13) /* Bits 13-14: XXXX */
#define OTGFS_GLPMCFG_LPMRSP_MASK (3 << OTGFS_GLPMCFG_LPMRSP_SHIFT)
#define OTGFS_GLPMCFG_SLPSTS (1 << 15) /* Bit 15: XXX */
#define OTGFS_GLPMCFG_L1RSMOK (1 << 16) /* Bit 16: XXX */
//#define OTGFS_GLPMCFG_LPMCHIDX
//#define OTGFS_GLPMCFG_LPMRCNT
#define OTGFS_GLPMCFG_LPMCHIDX_SHIFT (17) /* Bits 17-20: XXX */
#define OTGFS_GLPMCFG_LPMCHIDX_MASK (15 << OTGFS_GLPMCFG_LPMCHIDX_SHIFT)
#define OTGFS_GLPMCFG_LPMRCNT_SHIFT (21) /* Bits 21-23: XXX */
#define OTGFS_GLPMCFG_LPMRCNT_MASK (7 << OTGFS_GLPMCFG_LPMRCNT_SHIFT)
#define OTGFS_GLPMCFG_SNDLPM (1 << 24) /* Bit 24: XXX */
//#define OTGFS_GLPMCFG_LPMRCNTSTS
#define OTGFS_GLPMCFG_LPMRCNTSTS_SHIFT (25) /* Bits 25-27: XXX */
#define OTGFS_GLPMCFG_LPMRCNTSTS_MASK (7 << OTGFS_GLPMCFG_LPMRCNTSTS_SHIFT)
#define OTGFS_GLPMCFG_ENBESL (1 << 28) /* Bit 28: XXX */
/* Bits 29-31: Reserved, must be kept at reset value */
//XXX GPWRDN
#define OTGFS_GPWRDN_ADPMEN (1 << 0) /* Bit 0: XXX */
/* Power down register */
#define OTGFS_GPWRDN_ADPMEN (1 << 0) /* Bit 0: XXX */
#define OTGFS_GPWRDN_ADPIF (1 << 23) /* Bit 23: XXX */
//XXX GADPCTL
//#define OTGFS_GADPCTL_PRBDSCHG
//#define OTGFS_GADPCTL_PRBDELTA
//#define OTGFS_GADPCTL_PRBPER
//#define OTGFS_GADPCTL_RTIM
/* ADP timer, control and status register */
#define OTGFS_GADPCTL_PRBDSCHG_SHIFT (0) /* Bits 0-1: XXX */
#define OTGFS_GADPCTL_PRBDSCHG_MASK (3 << OTGFS_GADPCTL_PRBDSCHG_SHIFT)
#define OTGFS_GADPCTL_PRBDELTA_SHIFT (2) /* Bits 2-3: XXX */
#define OTGFS_GADPCTL_PRBDELTA_MASK (3 << OTGFS_GADPCTL_PRBDELTA_SHIFT)
#define OTGFS_GADPCTL_PRBPER_SHIFT (4) /* Bits 4-5: XXX */
#define OTGFS_GADPCTL_PRBPER_MASK (15 << OTGFS_GADPCTL_PRBPER_SHIFT)
#define OTGFS_GADPCTL_RTIM_SHIFT (6) /* Bits 6-9: XXX */
#define OTGFS_GADPCTL_RTIM_SHIFT (6) /* Bits 6-9: XXX */
#define OTGFS_GADPCTL_ENAPRB (1 << 17) /* Bit 17: XXX */
#define OTGFS_GADPCTL_ENASNS (1 << 18) /* Bit 18: XXX */
#define OTGFS_GADPCTL_ADPRST (1 << 19) /* Bit 19: XXX */
@ -492,7 +507,8 @@
#define OTGFS_GADPCTL_ADPPRBIM (1 << 24) /* Bit 24: XXX */
#define OTGFS_GADPCTL_ADPSNSIM (1 << 25) /* Bit 25: XXX */
#define OTGFS_GADPCTL_ADPTOIM (1 << 26) /* Bit 26: XXX */
//#define OTGFS_GADPCTL_AR
#define OTGFS_GADPCTL_AR_SHIFT (27) /* Bits 27-28: XXX */
#define OTGFS_GADPCTL_AR_MASK (3 << OTGFS_GADPCTL_AR_SHIFT)
/* Host periodic transmit FIFO size register */
@ -622,7 +638,6 @@
#define OTGFS_HCINT_STALL (1 << 3) /* Bit 3: STALL response received interrupt */
#define OTGFS_HCINT_NAK (1 << 4) /* Bit 4: NAK response received interrupt */
#define OTGFS_HCINT_ACK (1 << 5) /* Bit 5: ACK response received/transmitted interrupt */
//#define OTGFS_HCINT_NYET (1 << 6) /* Bit 6: Response received interrupt */
#define OTGFS_HCINT_TXERR (1 << 7) /* Bit 7: Transaction error */
#define OTGFS_HCINT_BBERR (1 << 8) /* Bit 8: Babble error */
#define OTGFS_HCINT_FRMOR (1 << 9) /* Bit 9: Frame overrun */
@ -704,7 +719,6 @@
#define OTGFS_DSTS_SOFFN_ODD OTGFS_DSTS_SOFFN0
#define OTGFS_DSTS_DEVLNSTS_SHIFT (22) /* Bits 22-23: XXX */
#define OTGFS_DSTS_DEVLNSTS_MASK (0x3 << OTGFS_DSTS_DEVLNSTS_SHIFT)
//XXX
/* Bits 24-31: Reserved, must be kept at reset value */
/* Device IN endpoint common interrupt mask register */

3
arch/arm/src/stm32l4/chip/stm32l4x6xx_pinmap.h
View file

@ -233,7 +233,6 @@
#define GPIO_DFSDM_CKOUT_1 (GPIO_ALT|GPIO_AF6 |GPIO_PORTC|GPIO_PIN2)
#define GPIO_DFSDM_CKOUT_2 (GPIO_ALT|GPIO_AF6 |GPIO_PORTE|GPIO_PIN9)
/* Flexible Static Memory Controller (FSMC) */
#define GPIO_FMC_NL (GPIO_ALT|GPIO_AF12|GPIO_PORTB|GPIO_PIN7)
@ -776,7 +775,7 @@
#define GPIO_LPTIM2_ETR_2 (GPIO_ALT|GPIO_AF14|GPIO_PORTC|GPIO_PIN3)
#define GPIO_LPTIM2_ETR_3 (GPIO_ALT|GPIO_AF14|GPIO_PORTD|GPIO_PIN11)
/* Touch Screen Controller */
/* Touch Sensing Controller */
#define GPIO_TSC_SYNC (GPIO_ALT|GPIO_AF9 |GPIO_PORTD|GPIO_PIN2)

2
arch/arm/src/stm32l4/chip/stm32l4x6xx_rcc.h
View file

@ -127,7 +127,7 @@
#define RCC_CR_MSION (1 << 0) /* Bit 0: Internal Multi Speed clock enable */
#define RCC_CR_MSIRDY (1 << 1) /* Bit 1: Internal Multi Speed clock ready flag */
#define RCC_CR_MSIPLLEN (1 << 2) /* Bit 2: MSI clock PLL enable */
#define RCC_CR_MSIRGSEL (1 << 3) /* Bit 2: MSI clock range selection */
#define RCC_CR_MSIRGSEL (1 << 3) /* Bit 3: MSI clock range selection */
#define RCC_CR_MSIRANGE_SHIFT (4) /* Bits 7-4: MSI clock range */
#define RCC_CR_MSIRANGE_MASK (0x0f << RCC_CR_MSIRANGE_SHIFT)
# define RCC_CR_MSIRANGE_100K (0 << RCC_CR_MSIRANGE_SHIFT) /* 0000: around 100 kHz */

5
arch/arm/src/stm32l4/stm32l4_comp.c
View file

@ -47,7 +47,8 @@
#include <errno.h>
#if !(defined(CONFIG_STM32L4_STM32L4X3) || defined(CONFIG_STM32L4_STM32L4X6))
#if !(defined(CONFIG_STM32L4_STM32L4X3) || defined(CONFIG_STM32L4_STM32L4X5) || \
defined(CONFIG_STM32L4_STM32L4X6))
# error "Unrecognized STM32 chip"
#endif
@ -170,7 +171,7 @@ int stm32l4_compconfig(int cmp, const struct stm32l4_comp_config_s *cfg)
case STM32L4_COMP_INM_PIN_2:
stm32l4_configgpio(cmp == STM32L4_COMP1 ? GPIO_COMP1_INM_2 : GPIO_COMP2_INM_2);
#if defined(CONFIG_STM32L4_STM32L4X6)
#if defined(CONFIG_STM32L4_STM32L4X5) || defined(CONFIG_STM32L4_STM32L4X6)
regval |= COMP_CSR_INMSEL_PIN2;
#else
regval |= COMP_CSR_INMSEL_INMESEL;

2
arch/arm/src/stm32l4/stm32l4_comp.h
View file

@ -86,7 +86,7 @@ enum stm32l4_comp_inm_e
STM32L4_COMP_INM_PIN_5 /* COMP1: PA5, COMP2: PA5 */
};
#elif defined(CONFIG_STM32L4_STM32L4X6)
#elif defined(CONFIG_STM32L4_STM32L4X5) || defined(CONFIG_STM32L4_STM32L4X6)
/* Comparators */
enum stm32l4_comp_e

8
arch/arm/src/stm32l4/stm32l4_dbgmcu.h
View file

@ -45,10 +45,12 @@
#include "chip.h"
#if defined(CONFIG_STM32L4_STM32L4X6)
# include "chip/stm32l4x6xx_dbgmcu.h"
#elif defined(CONFIG_STM32L4_STM32L4X3)
#if defined(CONFIG_STM32L4_STM32L4X3)
# include "chip/stm32l4x3xx_dbgmcu.h"
#elif defined(CONFIG_STM32L4_STM32L4X5)
# include "chip/stm32l4x5xx_dbgmcu.h"
#elif defined(CONFIG_STM32L4_STM32L4X6)
# include "chip/stm32l4x6xx_dbgmcu.h"
#else
# error "Unsupported STM32L4 chip"
#endif

3
arch/arm/src/stm32l4/stm32l4_dma.c
View file

@ -49,7 +49,8 @@
* TODO: do we need separate implementation for STM32L4X3?
*/
#if defined(CONFIG_STM32L4_STM32L4X6) || defined(CONFIG_STM32L4_STM32L4X3)
#if defined(CONFIG_STM32L4_STM32L4X3) || defined(CONFIG_STM32L4_STM32L4X5) || \
defined(CONFIG_STM32L4_STM32L4X6)
#include "stm32l4x6xx_dma.c"
#else
# error "Unsupported STM32L4 chip"

8
arch/arm/src/stm32l4/stm32l4_dma.h
View file

@ -49,10 +49,12 @@
/* Include the correct DMA register definitions for this STM32 family */
#if defined(CONFIG_STM32L4_STM32L4X6)
# include "chip/stm32l4x6xx_dma.h"
#elif defined(CONFIG_STM32L4_STM32L4X3)
#if defined(CONFIG_STM32L4_STM32L4X3)
# include "chip/stm32l4x3xx_dma.h"
#elif defined(CONFIG_STM32L4_STM32L4X5)
# include "chip/stm32l4x5xx_dma.h"
#elif defined(CONFIG_STM32L4_STM32L4X6)
# include "chip/stm32l4x6xx_dma.h"
#else
# error "Unsupported STM32L4 chip"
#endif

3
arch/arm/src/stm32l4/stm32l4_exti_comp.c
View file

@ -69,7 +69,8 @@ static struct comp_callback_s g_comp_handlers[STM32L4_COMP_NUM];
static const uint32_t g_comp_lines[STM32L4_COMP_NUM] =
{
#if defined(CONFIG_STM32L4_STM32L4X3) || defined (CONFIG_STM32L4_STM32L4X6)
#if defined(CONFIG_STM32L4_STM32L4X3) || defined (CONFIG_STM32L4_STM32L4X5) || \
defined(CONFIG_STM32L4_STM32L4X6)
EXTI1_COMP1,
EXTI1_COMP2
#else

8
arch/arm/src/stm32l4/stm32l4_firewall.h
View file

@ -47,10 +47,12 @@
/* Include the correct firewall register definitions for this STM32L4 family */
#if defined(CONFIG_STM32L4_STM32L4X6)
# include "chip/stm32l4x6xx_firewall.h"
#elif defined(CONFIG_STM32L4_STM32L4X3)
#if defined(CONFIG_STM32L4_STM32L4X3)
# include "chip/stm32l4x3xx_firewall.h"
#elif defined(CONFIG_STM32L4_STM32L4X5)
# include "chip/stm32l4x5xx_firewall.h"
#elif defined(CONFIG_STM32L4_STM32L4X6)
# include "chip/stm32l4x6xx_firewall.h"
#else
# error "Unsupported STM32L4 chip"
#endif

3
arch/arm/src/stm32l4/stm32l4_flash.c
View file

@ -62,7 +62,8 @@
#include "up_arch.h"
#if !(defined(CONFIG_STM32L4_STM32L4X3) || defined(CONFIG_STM32L4_STM32L4X6))
#if !(defined(CONFIG_STM32L4_STM32L4X3) || defined(CONFIG_STM32L4_STM32L4X5) || \
defined(CONFIG_STM32L4_STM32L4X6))
# error "Unrecognized STM32 chip"
#endif

3
arch/arm/src/stm32l4/stm32l4_gpio.h
View file

@ -54,7 +54,8 @@
#include "chip.h"
#if defined(CONFIG_STM32L4_STM32L4X6) || defined(CONFIG_STM32L4_STM32L4X3)
#if defined(CONFIG_STM32L4_STM32L4X3) || defined(CONFIG_STM32L4_STM32L4X5) || \
defined(CONFIG_STM32L4_STM32L4X6)
# include "chip/stm32l4_gpio.h"
#else
# error "Unsupported STM32L4 chip"

10
arch/arm/src/stm32l4/stm32l4_otgfs.h
View file

@ -47,10 +47,16 @@
#include "stm32l4.h"
#include "chip/stm32l4x6xx_otgfs.h"
#if defined(CONFIG_STM32L4_OTGFS)
#if defined(CONFIG_STM32L4_STM32L4X5)
# include "chip/stm32l4x5xx_otgfs.h"
#elif defined(CONFIG_STM32L4_STM32L4X6)
# include "chip/stm32l4x6xx_otgfs.h"
#else
# error "Unsupported STM32L4 chip"
#endif
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/

6
arch/arm/src/stm32l4/stm32l4_pm.h
View file

@ -97,7 +97,8 @@ int stm32l4_pmstop(bool lpds);
*
****************************************************************************/
#if defined(CONFIG_STM32L4_STM32L4X6) || defined(CONFIG_STM32L4_STM32L4X3)
#if defined(CONFIG_STM32L4_STM32L4X3) || defined(CONFIG_STM32L4_STM32L4X5) || \
defined(CONFIG_STM32L4_STM32L4X6)
int stm32l4_pmstop2(void);
#endif
@ -158,7 +159,8 @@ void stm32l4_pmsleep(bool sleeponexit);
*
****************************************************************************/
#if defined(CONFIG_STM32L4_STM32L4X6) || defined(CONFIG_STM32L4_STM32L4X3)
#if defined(CONFIG_STM32L4_STM32L4X3) || defined(CONFIG_STM32L4_STM32L4X5) || \
defined(CONFIG_STM32L4_STM32L4X6)
int stm32l4_pmlpr(void);
#endif

5
arch/arm/src/stm32l4/stm32l4_pmlpr.c
View file

@ -48,7 +48,8 @@
#include "stm32l4_pm.h"
#include "stm32l4_rcc.h"
#if defined(CONFIG_STM32L4_STM32L4X6) || defined(CONFIG_STM32L4_STM32L4X3)
#if defined(CONFIG_STM32L4_STM32L4X3) || defined(CONFIG_STM32L4_STM32L4X5) || \
defined(CONFIG_STM32L4_STM32L4X6)
/****************************************************************************
* Public Functions
@ -108,4 +109,4 @@ int stm32l4_pmlpr(void)
return OK;
}
#endif /* CONFIG_STM32L4_STM32L4X6 || CONFIG_STM32L4_STM32L4X3 */
#endif /* CONFIG_STM32L4_STM32L4X3 || CONFIG_STM32L4_STM32L4X5 || CONFIG_STM32L4_STM32L4X6 */

3
arch/arm/src/stm32l4/stm32l4_pmstandby.c
View file

@ -72,7 +72,8 @@ int stm32l4_pmstandby(void)
{
uint32_t regval;
#if defined(CONFIG_STM32L4_STM32L4X6) || defined(CONFIG_STM32L4_STM32L4X3)
#if defined(CONFIG_STM32L4_STM32L4X3) || defined(CONFIG_STM32L4_STM32L4X5) || \
defined(CONFIG_STM32L4_STM32L4X6)
/* Clear the Wake-Up Flags by setting the CWUFx bits in the power status
* clear register
*/

6
arch/arm/src/stm32l4/stm32l4_pmstop.c
View file

@ -109,7 +109,8 @@ int stm32l4_pmstop(bool lpds)
{
uint32_t regval;
#if defined(CONFIG_STM32L4_STM32L4X6) || defined(CONFIG_STM32L4_STM32L4X3)
#if defined(CONFIG_STM32L4_STM32L4X3) || defined(CONFIG_STM32L4_STM32L4X5) || \
defined(CONFIG_STM32L4_STM32L4X6)
/* Clear Low-Power Mode Selection (LPMS) bits in power control register 1. */
regval = getreg32(STM32L4_PWR_CR1);
regval &= ~PWR_CR1_LPMS_MASK;
@ -160,7 +161,8 @@ int stm32l4_pmstop(bool lpds)
*
****************************************************************************/
#if defined(CONFIG_STM32L4_STM32L4X6) || defined(CONFIG_STM32L4_STM32L4X3)
#if defined(CONFIG_STM32L4_STM32L4X3) || defined(CONFIG_STM32L4_STM32L4X5) || \
defined(CONFIG_STM32L4_STM32L4X6)
int stm32l4_pmstop2(void)
{
uint32_t regval;

6
arch/arm/src/stm32l4/stm32l4_pwm.c
View file

@ -842,7 +842,7 @@ static int stm32l4pwm_timer(FAR struct stm32l4_pwmtimer_s *priv,
timclk = priv->pclk / prescaler;
reload = timclk / info->frequency;
if (reload < 1)
if (reload < 2)
{
reload = 1;
}
@ -850,6 +850,10 @@ static int stm32l4pwm_timer(FAR struct stm32l4_pwmtimer_s *priv,
{
reload = 65535;
}
else
{
reload--;
}
pwminfo("TIM%u PCLK: %u frequency: %u TIMCLK: %u prescaler: %u reload: %u\n",
priv->timid, priv->pclk, info->frequency, timclk, prescaler, reload);

8
arch/arm/src/stm32l4/stm32l4_rcc.c
View file

@ -78,10 +78,12 @@
/* Include chip-specific clocking initialization logic */
#if defined(CONFIG_STM32L4_STM32L4X6)
# include "stm32l4x6xx_rcc.c"
#elif defined(CONFIG_STM32L4_STM32L4X3)
#if defined(CONFIG_STM32L4_STM32L4X3)
# include "stm32l4x3xx_rcc.c"
#elif defined(CONFIG_STM32L4_STM32L4X5)
# include "stm32l4x5xx_rcc.c"
#elif defined(CONFIG_STM32L4_STM32L4X6)
# include "stm32l4x6xx_rcc.c"
#else
# error "Unsupported STM32L4 chip"
#endif

10
arch/arm/src/stm32l4/stm32l4_rcc.h
View file

@ -45,10 +45,12 @@
#include "up_arch.h"
#include "chip.h"
#if defined(CONFIG_STM32L4_STM32L4X6)
# include "chip/stm32l4x6xx_rcc.h"
#elif defined(CONFIG_STM32L4_STM32L4X3)
#if defined(CONFIG_STM32L4_STM32L4X3)
# include "chip/stm32l4x3xx_rcc.h"
#elif defined(CONFIG_STM32L4_STM32L4X5)
# include "chip/stm32l4x5xx_rcc.h"
#elif defined(CONFIG_STM32L4_STM32L4X6)
# include "chip/stm32l4x6xx_rcc.h"
#else
# error "Unsupported STM32L4 chip"
#endif
@ -64,7 +66,7 @@
#define EXTERN extern "C"
extern "C"
{
#else
#elseO
#define EXTERN extern
#endif

3
arch/arm/src/stm32l4/stm32l4_uart.h
View file

@ -45,7 +45,8 @@
#include "chip.h"
#if defined(CONFIG_STM32L4_STM32L4X6) || defined(CONFIG_STM32L4_STM32L4X3)
#if defined(CONFIG_STM32L4_STM32L4X3) || defined(CONFIG_STM32L4_STM32L4X5) || \
defined(CONFIG_STM32L4_STM32L4X6)
# include "chip/stm32l4_uart.h"
#else
# error "Unsupported STM32L4 chip"

9
arch/arm/src/stm32l4/stm32l4_usbhost.h
View file

@ -47,10 +47,17 @@
#include <stdint.h>
#include "chip.h"
#include "chip/stm32l4x6xx_otgfs.h"
#if defined(CONFIG_STM32L4_OTGFS) && defined(CONFIG_USBHOST)
#if defined(CONFIG_STM32L4_STM32L4X5)
# include "chip/stm32l4x5xx_otgfs.h"
#elif defined(CONFIG_STM32L4_STM32L4X6)
# include "chip/stm32l4x6xx_otgfs.h"
#else
# error "Unsupported STM32L4 chip"
#endif
/************************************************************************************
* Public Types
************************************************************************************/

893
arch/arm/src/stm32l4/stm32l4x5xx_rcc.c Normal file
View file

@ -0,0 +1,893 @@
/****************************************************************************
* arch/arm/src/stm32l4/stm32l4x5xx_rcc.c
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
* Copyright (C) 2016 Sebastien Lorquet. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
* Sebastien Lorquet <sebastien@lorquet.fr>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <arch/stm32l4/chip.h>
#include "stm32l4_pwr.h"
#include "stm32l4_flash.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Allow up to 100 milliseconds for the high speed clock to become ready.
* that is a very long delay, but if the clock does not become ready we are
* hosed anyway. Normally this is very fast, but I have seen at least one
* board that required this long, long timeout for the HSE to be ready.
*/
#define HSERDY_TIMEOUT (100 * CONFIG_BOARD_LOOPSPERMSEC)
/* Same for HSI and MSI */
#define HSIRDY_TIMEOUT HSERDY_TIMEOUT
#define MSIRDY_TIMEOUT HSERDY_TIMEOUT
/* HSE divisor to yield ~1MHz RTC clock */
#define HSE_DIVISOR (STM32L4_HSE_FREQUENCY + 500000) / 1000000
/****************************************************************************
* Private Data
****************************************************************************/
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Name: rcc_reset
*
* Description:
* Reset the RCC clock configuration to the default reset state
*
****************************************************************************/
static inline void rcc_reset(void)
{
uint32_t regval;
/* Enable the Internal High Speed clock (HSI) */
regval = getreg32(STM32L4_RCC_CR);
regval |= RCC_CR_HSION;
putreg32(regval, STM32L4_RCC_CR);
/* Reset CFGR register */
putreg32(0x00000000, STM32L4_RCC_CFGR);
/* Reset HSION, HSEON, CSSON and PLLON bits */
regval = getreg32(STM32L4_RCC_CR);
regval &= ~(RCC_CR_HSION | RCC_CR_HSEON | RCC_CR_CSSON | RCC_CR_PLLON);
putreg32(regval, STM32L4_RCC_CR);
/* Reset PLLCFGR register to reset default */
putreg32(RCC_PLLCFG_RESET, STM32L4_RCC_PLLCFG);
/* Reset HSEBYP bit */
regval = getreg32(STM32L4_RCC_CR);
regval &= ~RCC_CR_HSEBYP;
putreg32(regval, STM32L4_RCC_CR);
/* Disable all interrupts */
putreg32(0x00000000, STM32L4_RCC_CIER);
}
/****************************************************************************
* Name: rcc_enableahb1
*
* Description:
* Enable selected AHB1 peripherals
*
****************************************************************************/
static inline void rcc_enableahb1(void)
{
uint32_t regval;
/* Set the appropriate bits in the AHB1ENR register to enable the
* selected AHB1 peripherals.
*/
regval = getreg32(STM32L4_RCC_AHB1ENR);
#ifdef CONFIG_STM32L4_DMA1
/* DMA 1 clock enable */
regval |= RCC_AHB1ENR_DMA1EN;
#endif
#ifdef CONFIG_STM32L4_DMA2
/* DMA 2 clock enable */
regval |= RCC_AHB1ENR_DMA2EN;
#endif
#ifdef CONFIG_STM32L4_CRC
/* CRC clock enable */
regval |= RCC_AHB1ENR_CRCEN;
#endif
#ifdef CONFIG_STM32L4_TSC
/* TSC clock enable */
regval |= RCC_AHB1ENR_TSCEN;
#endif
putreg32(regval, STM32L4_RCC_AHB1ENR); /* Enable peripherals */
}
/****************************************************************************
* Name: rcc_enableahb2
*
* Description:
* Enable selected AHB2 peripherals
*
****************************************************************************/
static inline void rcc_enableahb2(void)
{
uint32_t regval;
/* Set the appropriate bits in the AHB2ENR register to enabled the
* selected AHB2 peripherals.
*/
regval = getreg32(STM32L4_RCC_AHB2ENR);
/* Enable GPIOA, GPIOB, .... GPIOH */
#if STM32L4_NPORTS > 0
regval |= (RCC_AHB2ENR_GPIOAEN
#if STM32L4_NPORTS > 1
| RCC_AHB2ENR_GPIOBEN
#endif
#if STM32L4_NPORTS > 2
| RCC_AHB2ENR_GPIOCEN
#endif
#if STM32L4_NPORTS > 3
| RCC_AHB2ENR_GPIODEN
#endif
#if STM32L4_NPORTS > 4
| RCC_AHB2ENR_GPIOEEN
#endif
#if STM32L4_NPORTS > 5
| RCC_AHB2ENR_GPIOFEN
#endif
#if STM32L4_NPORTS > 6
| RCC_AHB2ENR_GPIOGEN
#endif
#if STM32L4_NPORTS > 7
| RCC_AHB2ENR_GPIOHEN
#endif
);
#endif
#ifdef CONFIG_STM32L4_OTGFS
/* USB OTG FS clock enable */
regval |= RCC_AHB2ENR_OTGFSEN;
#endif
#if defined(CONFIG_STM32L4_ADC1) || defined(CONFIG_STM32L4_ADC2) || defined(CONFIG_STM32L4_ADC3)
/* ADC clock enable */
regval |= RCC_AHB2ENR_ADCEN;
#endif
#ifdef CONFIG_STM32L4_RNG
/* Random number generator clock enable */
regval |= RCC_AHB2ENR_RNGEN;
#endif
putreg32(regval, STM32L4_RCC_AHB2ENR); /* Enable peripherals */
}
/****************************************************************************
* Name: rcc_enableahb3
*
* Description:
* Enable selected AHB3 peripherals
*
****************************************************************************/
static inline void rcc_enableahb3(void)
{
uint32_t regval;
/* Set the appropriate bits in the AHB3ENR register to enabled the
* selected AHB3 peripherals.
*/
regval = getreg32(STM32L4_RCC_AHB3ENR);
#ifdef CONFIG_STM32L4_FSMC
/* Flexible static memory controller module clock enable */
regval |= RCC_AHB3ENR_FSMCEN;
#endif
#ifdef CONFIG_STM32L4_QSPI
/* QuadSPI module clock enable */
regval |= RCC_AHB3ENR_QSPIEN;
#endif
putreg32(regval, STM32L4_RCC_AHB3ENR); /* Enable peripherals */
}
/****************************************************************************
* Name: rcc_enableapb1
*
* Description:
* Enable selected APB1 peripherals
*
****************************************************************************/
static inline void rcc_enableapb1(void)
{
uint32_t regval;
/* Set the appropriate bits in the APB1ENR register to enabled the
* selected APB1 peripherals.
*/
regval = getreg32(STM32L4_RCC_APB1ENR1);
#ifdef CONFIG_STM32L4_TIM2
/* TIM2 clock enable */
regval |= RCC_APB1ENR1_TIM2EN;
#endif
#ifdef CONFIG_STM32L4_TIM3
/* TIM3 clock enable */
regval |= RCC_APB1ENR1_TIM3EN;
#endif
#ifdef CONFIG_STM32L4_TIM4
/* TIM4 clock enable */
regval |= RCC_APB1ENR1_TIM4EN;
#endif
#ifdef CONFIG_STM32L4_TIM5
/* TIM5 clock enable */
regval |= RCC_APB1ENR1_TIM5EN;
#endif
#ifdef CONFIG_STM32L4_TIM6
/* TIM6 clock enable */
regval |= RCC_APB1ENR1_TIM6EN;
#endif
#ifdef CONFIG_STM32L4_TIM7
/* TIM7 clock enable */
regval |= RCC_APB1ENR1_TIM7EN;
#endif
#ifdef CONFIG_STM32L4_SPI2
/* SPI2 clock enable */
regval |= RCC_APB1ENR1_SPI2EN;
#endif
#ifdef CONFIG_STM32L4_SPI3
/* SPI3 clock enable */
regval |= RCC_APB1ENR1_SPI3EN;
#endif
#ifdef CONFIG_STM32L4_USART2
/* USART 2 clock enable */
regval |= RCC_APB1ENR1_USART2EN;
#endif
#ifdef CONFIG_STM32L4_USART3
/* USART3 clock enable */
regval |= RCC_APB1ENR1_USART3EN;
#endif
#ifdef CONFIG_STM32L4_UART4
/* UART4 clock enable */
regval |= RCC_APB1ENR1_UART4EN;
#endif
#ifdef CONFIG_STM32L4_UART5
/* UART5 clock enable */
regval |= RCC_APB1ENR1_UART5EN;
#endif
#ifdef CONFIG_STM32L4_I2C1
/* I2C1 clock enable */
regval |= RCC_APB1ENR1_I2C1EN;
#endif
#ifdef CONFIG_STM32L4_I2C2
/* I2C2 clock enable */
regval |= RCC_APB1ENR1_I2C2EN;
#endif
#ifdef CONFIG_STM32L4_I2C3
/* I2C3 clock enable */
regval |= RCC_APB1ENR1_I2C3EN;
#endif
#ifdef CONFIG_STM32L4_CAN1
/* CAN 1 clock enable */
regval |= RCC_APB1ENR1_CAN1EN;
#endif
/* Power interface clock enable. The PWR block is always enabled so that
* we can set the internal voltage regulator as required.
*/
regval |= RCC_APB1ENR1_PWREN;
#if defined (CONFIG_STM32L4_DAC1) || defined(CONFIG_STM32L4_DAC2)
/* DAC interface clock enable */
regval |= RCC_APB1ENR1_DACEN;
#endif
#ifdef CONFIG_STM32L4_OPAMP
/* OPAMP clock enable */
regval |= RCC_APB1ENR1_OPAMPEN;
#endif
#ifdef CONFIG_STM32L4_LPTIM1
/* Low power timer 1 clock enable */
regval |= RCC_APB1ENR1_LPTIM1EN;
#endif
putreg32(regval, STM32L4_RCC_APB1ENR1); /* Enable peripherals */
/* Second APB1 register */
regval = getreg32(STM32L4_RCC_APB1ENR2);
#ifdef CONFIG_STM32L4_LPUART1
/* Low power uart clock enable */
regval |= RCC_APB1ENR2_LPUART1EN;
#endif
#ifdef CONFIG_STM32L4_SWPMI
/* Single-wire protocol master clock enable */
regval |= RCC_APB1ENR2_SWPMI1EN;
#endif
#ifdef CONFIG_STM32L4_LPTIM2
/* Low power timer 2 clock enable */
regval |= RCC_APB1ENR2_LPTIM2EN;
#endif
putreg32(regval, STM32L4_RCC_APB1ENR2); /* Enable peripherals */
}
/****************************************************************************
* Name: rcc_enableapb2
*
* Description:
* Enable selected APB2 peripherals
*
****************************************************************************/
static inline void rcc_enableapb2(void)
{
uint32_t regval;
/* Set the appropriate bits in the APB2ENR register to enabled the
* selected APB2 peripherals.
*/
regval = getreg32(STM32L4_RCC_APB2ENR);
#ifdef CONFIG_STM32L4_SYSCFG
/* System configuration controller clock enable */
regval |= RCC_APB2ENR_SYSCFGEN;
#endif
#ifdef CONFIG_STM32L4_FIREWALL
/* Firewall clock enable */
regval |= RCC_APB2ENR_FWEN;
#endif
#ifdef CONFIG_STM32L4_SDMMC
/* SDMMC clock enable */
regval |= RCC_APB2ENR_SDMMCEN;
#endif
#ifdef CONFIG_STM32L4_TIM1
/* TIM1 clock enable */
regval |= RCC_APB2ENR_TIM1EN;
#endif
#ifdef CONFIG_STM32L4_SPI1
/* SPI1 clock enable */
regval |= RCC_APB2ENR_SPI1EN;
#endif
#ifdef CONFIG_STM32L4_TIM8
/* TIM8 clock enable */
regval |= RCC_APB2ENR_TIM8EN;
#endif
#ifdef CONFIG_STM32L4_USART1
/* USART1 clock enable */
regval |= RCC_APB2ENR_USART1EN;
#endif
#ifdef CONFIG_STM32L4_TIM15
/* TIM15 clock enable */
regval |= RCC_APB2ENR_TIM15EN;
#endif
#ifdef CONFIG_STM32L4_TIM16
/* TIM16 clock enable */
regval |= RCC_APB2ENR_TIM16EN;
#endif
#ifdef CONFIG_STM32L4_TIM17
/* TIM17 clock enable */
regval |= RCC_APB2ENR_TIM17EN;
#endif
#ifdef CONFIG_STM32L4_SAI1
/* SAI1 clock enable */
regval |= RCC_APB2ENR_SAI1EN;
#endif
#ifdef CONFIG_STM32L4_SAI2
/* SAI2 clock enable */
regval |= RCC_APB2ENR_SAI2EN;
#endif
#ifdef CONFIG_STM32L4_DFSDM1
/* DFSDM clock enable */
regval |= RCC_APB2ENR_DFSDMEN;
#endif
putreg32(regval, STM32L4_RCC_APB2ENR); /* Enable peripherals */
}
/****************************************************************************
* Name: stm32l4_stdclockconfig
*
* Description:
* Called to change to new clock based on settings in board.h
*
* NOTE: This logic would need to be extended if you need to select low-
* power clocking modes!
****************************************************************************/
#ifndef CONFIG_ARCH_BOARD_STM32L4_CUSTOM_CLOCKCONFIG
static void stm32l4_stdclockconfig(void)
{
uint32_t regval;
volatile int32_t timeout;
#ifdef STM32L4_BOARD_USEHSI
/* Enable Internal High-Speed Clock (HSI) */
regval = getreg32(STM32L4_RCC_CR);
regval |= RCC_CR_HSION; /* Enable HSI */
putreg32(regval, STM32L4_RCC_CR);
/* Wait until the HSI is ready (or until a timeout elapsed) */
for (timeout = HSIRDY_TIMEOUT; timeout > 0; timeout--)
{
/* Check if the HSIRDY flag is the set in the CR */
if ((getreg32(STM32L4_RCC_CR) & RCC_CR_HSIRDY) != 0)
{
/* If so, then break-out with timeout > 0 */
break;
}
}
#elif defined(STM32L4_BOARD_USEMSI)
/* Enable Internal Multi-Speed Clock (MSI) */
/* Wait until the MSI is either off or ready (or until a timeout elapsed) */
for (timeout = MSIRDY_TIMEOUT; timeout > 0; timeout--)
{
if ((regval = getreg32(STM32L4_RCC_CR)), (regval & RCC_CR_MSIRDY) || ~(regval & RCC_CR_MSION))
{
/* If so, then break-out with timeout > 0 */
break;
}
}
/* setting MSIRANGE */
regval = getreg32(STM32L4_RCC_CR);
regval |= (STM32L4_BOARD_MSIRANGE | RCC_CR_MSION); /* Enable MSI and frequency */
putreg32(regval, STM32L4_RCC_CR);
/* Wait until the MSI is ready (or until a timeout elapsed) */
for (timeout = MSIRDY_TIMEOUT; timeout > 0; timeout--)
{
/* Check if the MSIRDY flag is the set in the CR */
if ((getreg32(STM32L4_RCC_CR) & RCC_CR_MSIRDY) != 0)
{
/* If so, then break-out with timeout > 0 */
break;
}
}
#elif defined(STM32L4_BOARD_USEHSE)
/* Enable External High-Speed Clock (HSE) */
regval = getreg32(STM32L4_RCC_CR);
regval |= RCC_CR_HSEON; /* Enable HSE */
putreg32(regval, STM32L4_RCC_CR);
/* Wait until the HSE is ready (or until a timeout elapsed) */
for (timeout = HSERDY_TIMEOUT; timeout > 0; timeout--)
{
/* Check if the HSERDY flag is the set in the CR */
if ((getreg32(STM32L4_RCC_CR) & RCC_CR_HSERDY) != 0)
{
/* If so, then break-out with timeout > 0 */
break;
}
}
#else
# error stm32l4_stdclockconfig(), must have one of STM32L4_BOARD_USEHSI, STM32L4_BOARD_USEMSI, STM32L4_BOARD_USEHSE defined
#endif
/* Check for a timeout. If this timeout occurs, then we are hosed. We
* have no real back-up plan, although the following logic makes it look
* as though we do.
*/
if (timeout > 0)
{
#warning todo: regulator voltage according to clock freq
#if 0
/* Ensure Power control is enabled before modifying it. */
regval = getreg32(STM32L4_RCC_APB1ENR);
regval |= RCC_APB1ENR_PWREN;
putreg32(regval, STM32L4_RCC_APB1ENR);
/* Select regulator voltage output Scale 1 mode to support system
* frequencies up to 168 MHz.
*/
regval = getreg32(STM32L4_PWR_CR);
regval &= ~PWR_CR_VOS_MASK;
regval |= PWR_CR_VOS_SCALE_1;
putreg32(regval, STM32L4_PWR_CR);
#endif
/* Set the HCLK source/divider */
regval = getreg32(STM32L4_RCC_CFGR);
regval &= ~RCC_CFGR_HPRE_MASK;
regval |= STM32L4_RCC_CFGR_HPRE;
putreg32(regval, STM32L4_RCC_CFGR);
/* Set the PCLK2 divider */
regval = getreg32(STM32L4_RCC_CFGR);
regval &= ~RCC_CFGR_PPRE2_MASK;
regval |= STM32L4_RCC_CFGR_PPRE2;
putreg32(regval, STM32L4_RCC_CFGR);
/* Set the PCLK1 divider */
regval = getreg32(STM32L4_RCC_CFGR);
regval &= ~RCC_CFGR_PPRE1_MASK;
regval |= STM32L4_RCC_CFGR_PPRE1;
putreg32(regval, STM32L4_RCC_CFGR);
#ifdef CONFIG_RTC_HSECLOCK
/* Set the RTC clock divisor */
regval = getreg32(STM32L4_RCC_CFGR);
regval &= ~RCC_CFGR_RTCPRE_MASK;
regval |= RCC_CFGR_RTCPRE(HSE_DIVISOR);
putreg32(regval, STM32L4_RCC_CFGR);
#endif
/* Set the PLL source and main divider */
regval = getreg32(STM32L4_RCC_PLLCFG);
/* Configure Main PLL */
/* Set the PLL dividers and multipliers to configure the main PLL */
regval = (STM32L4_PLLCFG_PLLM | STM32L4_PLLCFG_PLLN | STM32L4_PLLCFG_PLLP
| STM32L4_PLLCFG_PLLQ | STM32L4_PLLCFG_PLLR);
#ifdef STM32L4_PLLCFG_PLLP_ENABLED
regval |= RCC_PLLCFG_PLLPEN;
#endif
#ifdef STM32L4_PLLCFG_PLLQ_ENABLED
regval |= RCC_PLLCFG_PLLQEN;
#endif
#ifdef STM32L4_PLLCFG_PLLR_ENABLED
regval |= RCC_PLLCFG_PLLREN;
#endif
/* XXX The choice of clock source to PLL (all three) is independent
* of the sys clock source choice, review the STM32L4_BOARD_USEHSI
* name; probably split it into two, one for PLL source and one
* for sys clock source.
*/
#ifdef STM32L4_BOARD_USEHSI
regval |= RCC_PLLCFG_PLLSRC_HSI;
#elif defined(STM32L4_BOARD_USEMSI)
regval |= RCC_PLLCFG_PLLSRC_MSI;
#else /* if STM32L4_BOARD_USEHSE */
regval |= RCC_PLLCFG_PLLSRC_HSE;
#endif
putreg32(regval, STM32L4_RCC_PLLCFG);
/* Enable the main PLL */
regval = getreg32(STM32L4_RCC_CR);
regval |= RCC_CR_PLLON;
putreg32(regval, STM32L4_RCC_CR);
/* Wait until the PLL is ready */
while ((getreg32(STM32L4_RCC_CR) & RCC_CR_PLLRDY) == 0)
{
}
#ifdef CONFIG_STM32L4_SAI1PLL
/* Configure SAI1 PLL */
regval = getreg32(STM32L4_RCC_PLLSAI1CFG);
/* Set the PLL dividers and multipliers to configure the SAI1 PLL */
regval = (STM32L4_PLLSAI1CFG_PLLN | STM32L4_PLLSAI1CFG_PLLP
| STM32L4_PLLSAI1CFG_PLLQ | STM32L4_PLLSAI1CFG_PLLR);
#ifdef STM32L4_PLLSAI1CFG_PLLP_ENABLED
regval |= RCC_PLLSAI1CFG_PLLPEN;
#endif
#ifdef STM32L4_PLLSAI1CFG_PLLQ_ENABLED
regval |= RCC_PLLSAI1CFG_PLLQEN;
#endif
#ifdef STM32L4_PLLSAI1CFG_PLLR_ENABLED
regval |= RCC_PLLSAI1CFG_PLLREN;
#endif
putreg32(regval, STM32L4_RCC_PLLSAI1CFG);
/* Enable the SAI1 PLL */
regval = getreg32(STM32L4_RCC_CR);
regval |= RCC_CR_PLLSAI1ON;
putreg32(regval, STM32L4_RCC_CR);
/* Wait until the PLL is ready */
while ((getreg32(STM32L4_RCC_CR) & RCC_CR_PLLSAI1RDY) == 0)
{
}
#endif
#ifdef CONFIG_STM32L4_SAI2PLL
/* Configure SAI2 PLL */
regval = getreg32(STM32L4_RCC_PLLSAI2CFG);
/* Set the PLL dividers and multipliers to configure the SAI2 PLL */
regval = (STM32L4_PLLSAI2CFG_PLLN | STM32L4_PLLSAI2CFG_PLLP |
STM32L4_PLLSAI2CFG_PLLR);
#ifdef STM32L4_PLLSAI2CFG_PLLP_ENABLED
regval |= RCC_PLLSAI2CFG_PLLPEN;
#endif
#ifdef STM32L4_PLLSAI2CFG_PLLR_ENABLED
regval |= RCC_PLLSAI2CFG_PLLREN;
#endif
putreg32(regval, STM32L4_RCC_PLLSAI2CFG);
/* Enable the SAI2 PLL */
regval = getreg32(STM32L4_RCC_CR);
regval |= RCC_CR_PLLSAI2ON;
putreg32(regval, STM32L4_RCC_CR);
/* Wait until the PLL is ready */
while ((getreg32(STM32L4_RCC_CR) & RCC_CR_PLLSAI2RDY) == 0)
{
}
#endif
/* Enable FLASH prefetch, instruction cache, data cache, and 4 wait states */
#ifdef CONFIG_STM32L4_FLASH_PREFETCH
regval = (FLASH_ACR_LATENCY_4 | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_PRFTEN);
#else
regval = (FLASH_ACR_LATENCY_4 | FLASH_ACR_ICEN | FLASH_ACR_DCEN);
#endif
putreg32(regval, STM32L4_FLASH_ACR);
/* Select the main PLL as system clock source */
regval = getreg32(STM32L4_RCC_CFGR);
regval &= ~RCC_CFGR_SW_MASK;
regval |= RCC_CFGR_SW_PLL;
putreg32(regval, STM32L4_RCC_CFGR);
/* Wait until the PLL source is used as the system clock source */
while ((getreg32(STM32L4_RCC_CFGR) & RCC_CFGR_SWS_MASK) != RCC_CFGR_SWS_PLL)
{
}
#if defined(CONFIG_STM32L4_IWDG) || defined(CONFIG_RTC_LSICLOCK)
/* Low speed internal clock source LSI */
stm32l4_rcc_enablelsi();
#endif
#if defined(STM32L4_USE_LSE)
/* Low speed external clock source LSE
*
* TODO: There is another case where the LSE needs to
* be enabled: if the MCO1 pin selects LSE as source.
* XXX and other cases, like automatic trimming of MSI for USB use
*/
/* ensure Power control is enabled since it is indirectly required
* to alter the LSE parameters.
*/
stm32l4_pwr_enableclk(true);
/* XXX other LSE settings must be made before turning on the oscillator
* and we need to ensure it is first off before doing so.
*/
/* Turn on the LSE oscillator
* XXX this will almost surely get moved since we also want to use
* this for automatically trimming MSI, etc.
*/
stm32l4_rcc_enablelse();
# if defined(STM32L4_BOARD_USEMSI)
/* Now that LSE is up, auto trim the MSI */
regval = getreg32(STM32L4_RCC_CR);
regval |= RCC_CR_MSIPLLEN;
putreg32(regval, STM32L4_RCC_CR);
# endif
#endif
#if defined(STM32L4_USE_CLK48)
/* XXX sanity if sdmmc1 or usb or rng, then we need to set the clk48 source
* and then we can also do away with STM32L4_USE_CLK48, and give better
* warning messages
*
* XXX sanity if our STM32L4_CLK48_SEL is YYY then we need to have already
* enabled ZZZ
*/
regval = getreg32(STM32L4_RCC_CCIPR);
regval &= RCC_CCIPR_CLK48SEL_MASK;
regval |= STM32L4_CLK48_SEL;
putreg32(regval, STM32L4_RCC_CCIPR);
#endif
}
}
#endif
/****************************************************************************
* Name: rcc_enableperipherals
****************************************************************************/
static inline void rcc_enableperipherals(void)
{
rcc_enableahb1();
rcc_enableahb2();
rcc_enableahb3();
rcc_enableapb1();
rcc_enableapb2();
}
/****************************************************************************
* Public Functions
****************************************************************************/

2
arch/arm/src/stm32l4/stm32l4x6xx_rcc.c
View file

@ -129,7 +129,7 @@ static inline void rcc_enableahb1(void)
{
uint32_t regval;
/* Set the appropriate bits in the AHB1ENR register to enabled the
/* Set the appropriate bits in the AHB1ENR register to enable the
* selected AHB1 peripherals.
*/

6
arch/misoc/src/common/misoc_serial.c
View file

@ -313,7 +313,7 @@ static int misoc_attach(struct uart_dev_s *dev)
{
struct misoc_dev_s *priv = (struct misoc_dev_s *)dev->priv;
(void)irq_attach(priv->irq, misoc_uart_interrupt, NULL);
(void)irq_attach(priv->irq, misoc_uart_interrupt, dev);
up_enable_irq(priv->irq);
return OK;
@ -351,10 +351,10 @@ static void misoc_detach(struct uart_dev_s *dev)
static int misoc_uart_interrupt(int irq, void *context, FAR void *arg)
{
struct uart_dev_s *dev = (struct uart_dev_s *)arg;
uint32_t stat;
struct uart_dev_s *dev = NULL;
dev = &g_uart1port;
DEBUGASSERT(dev != NULL);
/* Read as much as we can */

30
arch/renesas/src/sh1/sh1_serial.c
View file

@ -485,17 +485,17 @@ static int up_attach(struct uart_dev_s *dev)
/* Attach the RDR full IRQ (RXI) that is enabled by the RIE SCR bit */
ret = irq_attach(priv->irq + SH1_RXI_IRQ_OFFSET, up_interrupt, NULL);
ret = irq_attach(priv->irq + SH1_RXI_IRQ_OFFSET, up_interrupt, dev);
if (ret == OK)
{
/* The RIE interrupt enable also enables the receive error interrupt (ERI) */
ret = irq_attach(priv->irq + SH1_ERI_IRQ_OFFSET, up_interrupt, NULL);
ret = irq_attach(priv->irq + SH1_ERI_IRQ_OFFSET, up_interrupt, dev);
if (ret == OK)
{
/* Attach the TDR empty IRQ (TXI) enabled by the TIE SCR bit */
ret = irq_attach(priv->irq + SH1_TXI_IRQ_OFFSET, up_interrupt, NULL);
ret = irq_attach(priv->irq + SH1_TXI_IRQ_OFFSET, up_interrupt, dev);
if (ret == OK)
{
#ifdef CONFIG_ARCH_IRQPRIO
@ -569,28 +569,10 @@ static void up_detach(struct uart_dev_s *dev)
static int up_interrupt(int irq, void *context, FAR void *arg)
{
struct uart_dev_s *dev = NULL;
struct up_dev_s *priv;
struct uart_dev_s *dev = (struct uart_dev_s *)arg;
struct up_dev_s *priv;
#ifdef CONFIG_SH1_SCI0
if ((irq >= g_sci0priv.irq) &&
(irq <= g_sci0priv.irq + SH1_SCI_NIRQS))
{
dev = &g_sci0port;
}
else
#endif
#ifdef CONFIG_SH1_SCI1
if ((irq >= g_sci1priv.irq) &&
(irq <= g_sci1priv.irq + SH1_SCI_NIRQS))
{
dev = &g_sci1port;
}
else
#endif
{
PANIC();
}
DEBUGASSERT(dev != NULL && dev->priv != NULL);
priv = (struct up_dev_s*)dev->priv;
/* Get the current SCI status */

249
configs/b-l475e-iot01a/README.txt Normal file
View file

@ -0,0 +1,249 @@
README
======
This README discusses the port of NuttX to the STMicro B-L475E-IOT01A
Discovery kit powered by STM32L475VG Cortex-M4. This board targets IoT
nodes with a choice of connectivity options including WiFi, Bluetooth LE,
NFC, and sub-GHZ RF at 868 or 915 MHz, as well as a long list of various
environmental sensors.
Contents
========
o STATUS
o Board Features
o LEDs and Buttons
o Serial Console
o Configurations
STATUS
======
o 2017-06-10: I have no hardware in hand and I am not sure that I will
even pursue this port. This README is really no more than a thought
experiment at the present time.
A few days ago, I did add support for the STM32L4x5 MCU family to
NuttX. But no work has yet been done for this board port other
than writing this README file.
o 2017-06-13: I just learned that development boards will not be
available for another month.
Board Features
==============
B-L475E-IOT01A Discovery kit key features and specifications:
o MCU: STM32L475 Series MCU based on ARM Cortex-M4 core with 1 MB
Flash memory, 128 KB SRAM
o Storage: 64 Mbit (8MB)  Quad-SPI Flash memory (Macronix)
o Connectivity:
- Bluetooth 4.1 LE module (SPBTLE-RF)
- Sub-GHz (868 or 915 MHz) low-power-programmable RF module (SPSGRF-868
or SPSGRF-915)
- Wi-Fi module based on Inventek ISM43362-M3G-L44 (802.11 b/g/n
compliant)
- Dynamic NFC tag based on M24SR with its printed NFC antenna
o Sensors:
- 2x digital omni-directional microphones (MP34DT01)
- Capacitive digital sensor for relative humidity and temperature
(HTS221)
- 3-axis magnetometer (LIS3MDL)
- 3D accelerometer and 3D gyroscope (LSM6DSL)
- 260-1260 hPa absolute digital output barometer (LPS22HB)
- Time-of-Flight and gesture-detection sensor (VL53L0X
o USB – 1x micro USB OTG port (Full speed)
o Expansion – Arduino UNO V3 headers, PMOD header
o Debugging – On-board ST-LINK/V2-1 debugger/programmer with USB
re-enumeration capability: mass storage, virtual COM port and debug
port
o Misc – 2 push-buttons (user and reset)
o Power Supply – 5V via ST LINK USB VBUS or external sources
The board supports ARM mbed online compiler, but can also be programmed
using IDEs such as IAR, Keil, and GCC-based IDEs. STMicro also provides
HAL libraries and code samples as part of the STM32Cube Package, as well
as X-CUBE-AWS expansion software to connect to the Amazon Web Services
(AWS) IoT platform.
NOTES:
1. The board usese Wi-Fi® module Inventek ISM43362-M3G-L44 (802.11 b/g/n
compliant), which consists of BCM43362 and STM32F205 host processor
that has a standard SPI or UART interface capability. It means you
will only use AT command to talk with Wi-Fi® module by SPI. All the
tcp/ip stack is built-in STM32F205 in Wi-Fi® module.
This cannot integrate cleanly with the NuttX network stack. A
USERSOCK option was recently added that would permit implementation
of the Inventek support in an applications. But that would then
preclude the 6loWPAN integration into IPv6.
2. The board uses Bluetooth® V4.1 module (SPBTLE-RF), which has built-in
BLE stack. Similar with wifi, you only use simple AT command to talk
with this BLE module.
3. STMicro provides contiki 6lowpan for mesh.
http://www.st.com/en/embedded-software/osxcontiki6lp.html but mesh
network is not popular in the market, star network is the mainstream
for its simplicity and robustness.
LEDs and Buttons
================
The black button B1 located on top side is the reset of the STM32L475VGT6.
The blue button B1 located top side is available to be used as a digital
input or as alternate function Wake-up. When the button is depressed the logic state is "0", otherwise the logic state is "1".
Two green LEDs (LD1 and LD2), located on the top side are available for the user. To light a LED a high logic state "1" should be written in the corresponding GPIO.
Reference Color Name Comment
B2 blue Wake-up Alternate function Wake-up
LD1 green LED1 PA5 (alternate with ARD.D13)
LD2 green LED2 PB14
These LEDs are not used by the board port unless CONFIG_ARCH_LEDS is
selected. In that case, the usage by the board port is defined in
include/board.h and src/lpc31_leds.c. The LEDs are used to encode
OS-related events as follows:
SYMBOL Meaning LED state
LED2 LED1
------------------- ----------------------- -------- --------
LED_STARTED NuttX has been started OFF OFF
LED_HEAPALLOCATE Heap has been allocated OFF OFF
LED_IRQSENABLED Interrupts enabled OFF OFF
LED_STACKCREATED Idle stack created ON OFF
LED_INIRQ In an interrupt N/C N/C
LED_SIGNAL In a signal handler N/C N/C
LED_ASSERTION An assertion failed N/C N/C
LED_PANIC The system has crashed N/C Blinking
LED_IDLE MCU is is sleep mode Not used
Thus if LED2 is statically on, NuttX has successfully booted and is,
apparently, running normmally. If LED1 is flashing at approximately
2Hz, then a fatal error has been detected and the system has halted.
NOTE: That LED2 is not used after completion of booting and may
be used by other board-specific logic.
Of course, if CONFIG_ARCH_LEDS is not selected, then both LEDs are
available for use by other logic.
Serial Console
==============
Arduino Serial Shield
---------------------
An TLL-to-RS232 Converter shield may be used with UART4:
UART4:
-------------- ---------------- ------------------
STM32L475VGTx Board Signal Arduino Connector
-------------- ---------------- ------------------
UART4_RX PA1 ARD.D0-UART4_RX CN3 pin1 RX/D0
UART4_TX PA0 ARD.D1-UART4_TX CN3 pin2 TX/D1
-------------- ---------------- ------------------
Virtual COM Port
----------------
The serial interface USART1 is directly available as a virtual COM port
of the PC connected to the ST-LINK/V2-1 USB connector CN7.
USART1:
-------------- ---------------- --------------
STM32L475VGTx Board Signal STM32F103CBT6
-------------- ---------------- --------------
USART1_TX PB6 ST-LINK-UART1_TX USART2_RX PA3
UAART1_RX PB7 ST-LINK-UART1_RX USART2_TX PA2
-------------- ---------------- --------------
The virtual COM port settings are configured as: 115200 b/s, 8 bits data,
no parity, 1 stop bit, no flow control.
Other Options
-------------
USART2 - Available on CN10 if solder bridges closed.
-------------- ---------------- ---------------------------
STM32L475VGTx Board Signal PMOD / Solder Bridges
-------------- ---------------- ---------------------------
USART2_RX PD4 PMOD-UART2_RX CN10 pin1 or 2 (SB12, SB14)
USART2_TX PD5 PMOD-UART2_TX CN10 pin2 TX/D1 (SB20)
-------------- ---------------- ---------------------------
USART3 - Dedicated to ISM43362-M3G-L44 Serial-to-Wifi Module.
-------------- ---------------- ------------------
STM32L475VGTx Board Signal Arduino Connector
-------------- ---------------- ------------------
USART3_RX PD9 INTERNAL-UART3_RX CN3 pin1 RX/D0
USART3_TX PD8 INTERNAL-UART3_TX CN3 pin2 TX/D1
-------------- ---------------- ------------------
Configurations
==============
Information Common to All Configurations
----------------------------------------
Each B-L475E-IOT01A configuration is maintained in a sub-directory and
can be selected as follow:
cd tools
./configure.sh b-l475e-iot01a/<subdir>
cd -
Before building, make sure that:
1. The PATH environment variable include the correct path to the
directory than holds your toolchain binaries.
2. Check the .config file. Make sure that the configuration is set for
your build platform (e.g., Linux vs. Windows) and that the toolchain
is set for the toolchain type you are using.
The <subdir> that is provided above as an argument to the
tools/configure.sh must be is one of those listed below.
And then build NuttX by simply typing the following. At the conclusion of
the make, the nuttx binary will reside in an ELF file called, simply,
nuttx.
make oldconfig
make
Where 'make oldconfig' brings the configuration up to data with the current configuration data and 'make' will compile all of the source
files and generate the final binary.
NOTES:
1. These configurations use the mconf-based configuration tool. To
change any of these configurations using that tool, you should:
a. Build and install the kconfig-mconf tool. See nuttx/README.txt
see additional README.txt files in the NuttX tools repository.
b. Execute 'make menuconfig' in nuttx/ in order to start the
reconfiguration process.
2. Unless stated otherwise, all configurations generate console
output on USART1 (i.e., for ST-Link Virtual COM port).
3. All of these configurations are set up to build under Windows using the
"GNU Tools for ARM Embedded Processors" that is maintained by ARM
(unless stated otherwise in the description of the configuration).
https://launchpad.net/gcc-arm-embedded
That toolchain selection can easily be reconfigured using
'make menuconfig'. Here are the relevant current settings:
Build Setup:
CONFIG_HOST_WINDOWS=y : Window environment
CONFIG_WINDOWS_CYGWIN=y : Cywin under Windows
System Type -> Toolchain:
CONFIG_ARMV7M_TOOLCHAIN_GNU_EABIW=y : GNU ARM EABI toolchain
Configuration sub-directories
-----------------------------

18
configs/freedom-k66f/include/board.h
View file

@ -348,6 +348,24 @@
#define PIN_I2C0_SCL PIN_I2C0_SCL_3
#define PIN_I2C0_SDA PIN_I2C0_SDA_3
/* RF/WIFI
*
* J6 Pin Name K66 Name
* ------ ----- ------ ---------
* 1 GND
* 2 P3V3
* 3 CE PTB20 PTB20
* 4 CS PTD4 SPI1_PCS0 (use as GPIO)
* 5 SCK PTD5 SPI1_SCK
* 6 MOSI PTD6 SPI1_MOSI
* 7 MISO PTD7 SPI1_MISO
* 8 IRQ PTC18 PTC18
*/
#define PIN_SPI1_SCK PIN_SPI1_SCK_3
#define PIN_SPI1_OUT PIN_SPI1_SOUT_3
#define PIN_SPI1_SIN PIN_SPI1_SIN_3
/*
* Ethernet MAC/KSZ8081 PHY
* ------------------------

70
configs/freedom-k66f/nsh/defconfig
View file

@ -28,6 +28,7 @@ CONFIG_BUILD_FLAT=y
# CONFIG_MOTOROLA_SREC is not set
CONFIG_RAW_BINARY=y
# CONFIG_UBOOT_UIMAGE is not set
# CONFIG_DFU_BINARY is not set
#
# Customize Header Files
@ -89,6 +90,7 @@ CONFIG_ARCH_CHIP_KINETIS=y
# CONFIG_ARCH_CHIP_LPC2378 is not set
# CONFIG_ARCH_CHIP_LPC31XX is not set
# CONFIG_ARCH_CHIP_LPC43XX is not set
# CONFIG_ARCH_CHIP_MOXART is not set
# CONFIG_ARCH_CHIP_NUC1XX is not set
# CONFIG_ARCH_CHIP_SAMA5 is not set
# CONFIG_ARCH_CHIP_SAMD is not set
@ -96,11 +98,12 @@ CONFIG_ARCH_CHIP_KINETIS=y
# CONFIG_ARCH_CHIP_SAM34 is not set
# CONFIG_ARCH_CHIP_SAMV7 is not set
# CONFIG_ARCH_CHIP_STM32 is not set
# CONFIG_ARCH_CHIP_STM32F0 is not set
# CONFIG_ARCH_CHIP_STM32F7 is not set
# CONFIG_ARCH_CHIP_STM32L4 is not set
# CONFIG_ARCH_CHIP_STR71X is not set
# CONFIG_ARCH_CHIP_TMS570 is not set
# CONFIG_ARCH_CHIP_MOXART is not set
# CONFIG_ARCH_CHIP_XMC4 is not set
# CONFIG_ARCH_ARM7TDMI is not set
# CONFIG_ARCH_ARM926EJS is not set
# CONFIG_ARCH_ARM920T is not set
@ -121,8 +124,6 @@ CONFIG_ARCH_CORTEXM4=y
# CONFIG_ARCH_CORTEXR7F is not set
CONFIG_ARCH_FAMILY="armv7-m"
CONFIG_ARCH_CHIP="kinetis"
# CONFIG_ARCH_TOOLCHAIN_IAR is not set
CONFIG_ARCH_TOOLCHAIN_GNU=y
CONFIG_ARMV7M_USEBASEPRI=y
CONFIG_ARCH_HAVE_CMNVECTOR=y
CONFIG_ARMV7M_CMNVECTOR=y
@ -189,6 +190,7 @@ CONFIG_ARCH_CHIP_MK66FN2M0VMD18=y
# CONFIG_KINETIS_HAVE_UART5 is not set
CONFIG_KINETIS_HAVE_LPUART0=y
# CONFIG_KINETIS_HAVE_LPUART1 is not set
CONFIG_KINETIS_SERIALDRIVER=y
# CONFIG_KINETIS_LPUART is not set
CONFIG_KINETIS_UART=y
# CONFIG_ARCH_FAMILY_K20 is not set
@ -200,11 +202,14 @@ CONFIG_ARCH_FAMILY_K66=y
#
# Kinetis Peripheral Support
#
CONFIG_KINETIS_HAVE_FTM3=y
CONFIG_KINETIS_HAVE_I2C1=y
CONFIG_KINETIS_HAVE_I2C2=y
CONFIG_KINETIS_HAVE_I2C3=y
CONFIG_KINETIS_HAVE_SPI1=y
CONFIG_KINETIS_HAVE_SPI2=y
CONFIG_KINETIS_HAVE_TPM1=y
CONFIG_KINETIS_HAVE_TPM2=y
# CONFIG_KINETIS_TRACE is not set
# CONFIG_KINETIS_FLEXBUS is not set
# CONFIG_KINETIS_UART0 is not set
@ -218,7 +223,7 @@ CONFIG_KINETIS_UART4=y
# CONFIG_KINETIS_FLEXCAN0 is not set
# CONFIG_KINETIS_FLEXCAN1 is not set
# CONFIG_KINETIS_SPI0 is not set
# CONFIG_KINETIS_SPI1 is not set
CONFIG_KINETIS_SPI1=y
# CONFIG_KINETIS_SPI2 is not set
CONFIG_KINETIS_I2C0=y
# CONFIG_KINETIS_I2C1 is not set
@ -236,6 +241,8 @@ CONFIG_KINETIS_FTM0=y
# CONFIG_KINETIS_FTM1 is not set
# CONFIG_KINETIS_FTM2 is not set
CONFIG_KINETIS_FTM3=y
# CONFIG_KINETIS_TPM1 is not set
# CONFIG_KINETIS_TPM2 is not set
# CONFIG_KINETIS_LPTIMER is not set
CONFIG_KINETIS_RTC=y
# CONFIG_KINETIS_EWM is not set
@ -279,6 +286,17 @@ CONFIG_KINETIS_PORTDINTS=y
# Kinetis UART Configuration
#
#
# Serial Driver Configuration
#
CONFIG_KINETIS_UART_BREAKS=y
CONFIG_KINETIS_UART_EXTEDED_BREAK=y
CONFIG_KINETIS_SERIALBRK_BSDCOMPAT=y
# CONFIG_KINETIS_UART_SINGLEWIRE is not set
CONFIG_SERIAL_TERMIOS=y
# CONFIG_ARCH_TOOLCHAIN_IAR is not set
CONFIG_ARCH_TOOLCHAIN_GNU=y
#
# Architecture Options
#
@ -298,6 +316,7 @@ CONFIG_ARCH_HAVE_MPU=y
# CONFIG_ARCH_HAVE_EXTCLK is not set
# CONFIG_ARCH_HAVE_POWEROFF is not set
CONFIG_ARCH_HAVE_RESET=y
# CONFIG_ARCH_HAVE_RTC_SUBSECONDS is not set
# CONFIG_ARCH_USE_MPU is not set
# CONFIG_ARCH_IRQPRIO is not set
CONFIG_ARCH_STACKDUMP=y
@ -422,6 +441,8 @@ CONFIG_SCHED_WAITPID=y
#
# CONFIG_PTHREAD_MUTEX_TYPES is not set
CONFIG_PTHREAD_MUTEX_ROBUST=y
# CONFIG_PTHREAD_MUTEX_UNSAFE is not set
# CONFIG_PTHREAD_MUTEX_BOTH is not set
CONFIG_NPTHREAD_KEYS=4
# CONFIG_PTHREAD_CLEANUP is not set
# CONFIG_CANCELLATION_POINTS is not set
@ -515,16 +536,25 @@ CONFIG_DEV_ZERO=y
# CONFIG_ARCH_HAVE_PWM_PULSECOUNT is not set
# CONFIG_ARCH_HAVE_PWM_MULTICHAN is not set
CONFIG_PWM=y
# CONFIG_ARCH_HAVE_I2CRESET is not set
CONFIG_ARCH_HAVE_I2CRESET=y
CONFIG_I2C=y
# CONFIG_I2C_SLAVE is not set
# CONFIG_I2C_POLLED is not set
CONFIG_I2C_RESET=y
# CONFIG_I2C_TRACE is not set
CONFIG_I2C_DRIVER=y
# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set
# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set
# CONFIG_ARCH_HAVE_SPI_BITORDER is not set
# CONFIG_SPI is not set
CONFIG_SPI=y
# CONFIG_SPI_SLAVE is not set
CONFIG_SPI_EXCHANGE=y
# CONFIG_SPI_CMDDATA is not set
# CONFIG_SPI_CALLBACK is not set
# CONFIG_SPI_HWFEATURES is not set
CONFIG_SPI_CS_DELAY_CONTROL=y
# CONFIG_SPI_DRIVER is not set
# CONFIG_SPI_BITBANG is not set
# CONFIG_I2S is not set
#
@ -554,6 +584,7 @@ CONFIG_INPUT=y
# CONFIG_INPUT_ADS7843E is not set
# CONFIG_INPUT_MXT is not set
# CONFIG_INPUT_STMPE811 is not set
# CONFIG_INPUT_CYPRESS_MBR3108 is not set
CONFIG_BUTTONS=y
CONFIG_BUTTONS_LOWER=y
CONFIG_BUTTONS_NPOLLWAITERS=2
@ -585,6 +616,7 @@ CONFIG_MMCSD_NSLOTS=1
CONFIG_MMCSD_MULTIBLOCK_DISABLE=y
CONFIG_MMCSD_MMCSUPPORT=y
CONFIG_MMCSD_HAVECARDDETECT=y
# CONFIG_MMCSD_SPI is not set
CONFIG_ARCH_HAVE_SDIO=y
# CONFIG_SDIO_DMA is not set
# CONFIG_ARCH_HAVE_SDIOWAIT_WRCOMPLETE is not set
@ -633,7 +665,7 @@ CONFIG_SERIAL_NPOLLWAITERS=2
# CONFIG_SERIAL_IFLOWCONTROL is not set
# CONFIG_SERIAL_OFLOWCONTROL is not set
# CONFIG_SERIAL_DMA is not set
# CONFIG_ARCH_HAVE_SERIAL_TERMIOS is not set
CONFIG_ARCH_HAVE_SERIAL_TERMIOS=y
CONFIG_UART1_SERIAL_CONSOLE=y
# CONFIG_UART4_SERIAL_CONSOLE is not set
# CONFIG_OTHER_SERIAL_CONSOLE is not set
@ -667,6 +699,7 @@ CONFIG_UART4_2STOP=0
# CONFIG_PSEUDOTERM is not set
# CONFIG_USBDEV is not set
# CONFIG_USBHOST is not set
# CONFIG_USBMISC is not set
# CONFIG_HAVE_USBTRACE is not set
# CONFIG_DRIVERS_WIRELESS is not set
# CONFIG_DRIVERS_CONTACTLESS is not set
@ -675,7 +708,9 @@ CONFIG_UART4_2STOP=0
# System Logging
#
# CONFIG_ARCH_SYSLOG is not set
CONFIG_SYSLOG_WRITE=y
# CONFIG_RAMLOG is not set
# CONFIG_SYSLOG_BUFFER is not set
# CONFIG_SYSLOG_INTBUFFER is not set
# CONFIG_SYSLOG_TIMESTAMP is not set
CONFIG_SYSLOG_SERIAL_CONSOLE=y
@ -751,6 +786,11 @@ CONFIG_MM_REGIONS=1
# CONFIG_ARCH_HAVE_HEAP2 is not set
# CONFIG_GRAN is not set
#
# Common I/O Buffer Support
#
# CONFIG_MM_IOB is not set
#
# Audio Support
#
@ -759,6 +799,7 @@ CONFIG_MM_REGIONS=1
#
# Wireless Support
#
# CONFIG_WIRELESS is not set
#
# Binary Loader
@ -934,13 +975,12 @@ CONFIG_EXAMPLES_BUTTONS_NAME7="BUTTON7"
# CONFIG_EXAMPLES_MM is not set
# CONFIG_EXAMPLES_MODBUS is not set
# CONFIG_EXAMPLES_MOUNT is not set
# CONFIG_EXAMPLES_NRF24L01TERM is not set
CONFIG_EXAMPLES_NSH=y
# CONFIG_EXAMPLES_NULL is not set
# CONFIG_EXAMPLES_NX is not set
# CONFIG_EXAMPLES_NXFFS is not set
# CONFIG_EXAMPLES_NXHELLO is not set
# CONFIG_EXAMPLES_NXIMAGE is not set
# CONFIG_EXAMPLES_NX is not set
# CONFIG_EXAMPLES_NXLINES is not set
# CONFIG_EXAMPLES_NXTERM is not set
# CONFIG_EXAMPLES_NXTEXT is not set
@ -971,6 +1011,7 @@ CONFIG_EXAMPLES_PWM_DUTYPCT=50
# CONFIG_EXAMPLES_USBSERIAL is not set
# CONFIG_EXAMPLES_WATCHDOG is not set
# CONFIG_EXAMPLES_WEBSERVER is not set
# CONFIG_EXAMPLES_XBC_TEST is not set
#
# File System Utilities
@ -1160,3 +1201,14 @@ CONFIG_READLINE_CMD_HISTORY_LEN=16
# CONFIG_SYSTEM_UBLOXMODEM is not set
# CONFIG_SYSTEM_VI is not set
# CONFIG_SYSTEM_ZMODEM is not set
#
# Wireless Libraries and NSH Add-Ons
#
#
# IEEE 802.15.4 applications
#
# CONFIG_IEEE802154_LIBMAC is not set
# CONFIG_IEEE802154_LIBUTILS is not set
# CONFIG_IEEE802154_I8SAK is not set

11
configs/freedom-k66f/src/freedom-k66f.h
View file

@ -57,6 +57,7 @@
#define HAVE_PROC 1
#define HAVE_MMCSD 1
#define HAVE_AUTOMOUNTER 1
#define HAVE_SPI 1
#define HAVE_USBDEV 1
#if defined(CONFIG_KINETIS_RTC)
@ -173,6 +174,11 @@
# undef CONFIG_KINETIS_SPI2
#endif
#if !defined(CONFIG_KINETIS_SPI0) && !defined(CONFIG_KINETIS_SPI1) && \
!defined(CONFIG_KINETIS_SPI3)
# undef HAVE_SPI
#endif
/* FREEDOM-K66F GPIOs ****************************************************************/
/* A micro Secure Digital (SD) card slot is available on the FRDM-K66F connected to
* the SD Host Controller (SDHC) signals of the MCU. This slot will accept micro
@ -223,6 +229,11 @@
#define GPIO_LED_G (GPIO_LOWDRIVE | GPIO_OUTPUT_ONE | PIN_PORTE | PIN6)
#define GPIO_LED_B (GPIO_LOWDRIVE | GPIO_OUTPUT_ONE | PIN_PORTA | PIN11)
/* SPI1 on J6 */
#define PIN_CE (GPIO_LOWDRIVE | GPIO_OUTPUT_ONE | PIN_PORTB | PIN20)
#define PIN_SPI1_PCS0 (GPIO_LOWDRIVE | GPIO_OUTPUT_ONE | PIN_PORTD | PIN4)
/************************************************************************************
* Public data
************************************************************************************/

19
configs/freedom-k66f/src/k66_bringup.c
View file

@ -47,8 +47,10 @@
#include <debug.h>
#include <nuttx/board.h>
#include <nuttx/spi/spi.h>
#include <nuttx/input/buttons.h>
#include "kinetis_spi.h"
#include "freedom-k66f.h"
#if defined(CONFIG_LIB_BOARDCTL) || defined(CONFIG_BOARD_INITIALIZE)
@ -67,6 +69,9 @@
int k66_bringup(void)
{
#ifdef HAVE_SPI
FAR struct spi_dev_s *spi1;
#endif
int ret;
#ifdef HAVE_PROC
@ -151,8 +156,20 @@ int k66_bringup(void)
}
#endif
#ifdef HAVE_SPI
/* Verify we can initialize SPI bus 1 */
spi1 = kinetis_spibus_initialize(1);
if (!spi1)
{
syslog(LOG_ERR, "ERROR:FAILED to initialize SPI port 1\n");
return -ENODEV;
}
#endif
UNUSED(ret);
return OK;
}
#endif /* CONFIG_LIB_BOARDCTL CONFIG_BOARD_INITIALIZE */

9
configs/freedom-k66f/src/k66_spi.c
View file

@ -53,7 +53,7 @@
#include "freedom-k66f.h"
#if defined(CONFIG_KINETIS_SPI0) || defined(CONFIG_KINETIS_SPI1) || \
defined(CONFIG_KINETIS_SPI2)
defined(CONFIG_KINETIS_SPI2)
/************************************************************************************
* Public Functions
@ -69,7 +69,10 @@
void weak_function k66_spidev_initialize(void)
{
# warning "Missing logic"
/* Initialize the CE CS pins on J6 RF/WIFI connector */
kinetis_pinconfig(PIN_CE);
kinetis_pinconfig(PIN_SPI1_PCS0);
}
/************************************************************************************
@ -118,7 +121,7 @@ uint8_t kinetis_spi0status(FAR struct spi_dev_s *dev, uint32_t devid)
void kinetis_spi1select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected)
{
spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert");
# warning "Missing logic"
kinetis_gpiowrite(PIN_SPI1_PCS0, !selected);
}
uint8_t kinetis_spi1status(FAR struct spi_dev_s *dev, uint32_t devid)

99
configs/nucleo-f334r8/src/stm32_hrtim.c Normal file
View file

@ -0,0 +1,99 @@
/****************************************************************************
* configs/nucleo-f334r8/src/stm32_hrtim.c
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
* Author: Mateusz Szafoni <raiden00@railab.me>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdbool.h>
#include <errno.h>
#include <debug.h>
#include <nuttx/board.h>
#include "stm32.h"
#if defined(CONFIG_HRTIM) && defined(CONFIG_STM32_HRTIM1)
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: stm32_hrtim_setup
*
* Description:
* Initialize HRTIM driver
*
* Returned Value:
* 0 on success, a negated errno value on failure
*
****************************************************************************/
int stm32_hrtim_setup(void)
{
static bool initialized = false;
struct hrtim_dev_s* hrtim = NULL;
int ret;
if (!initialized)
{
/* Get the HRTIM interface */
hrtim = stm32_hrtiminitialize();
if (hrtim == NULL)
{
tmrerr("ERROR: Failed to get HRTIM1 interface\n");
return -ENODEV;
}
/* Register the HRTIM character driver at /dev/hrtim0 */
ret = hrtim_register("/dev/hrtim0", hrtim);
if (ret < 0)
{
tmrerr("ERROR: hrtim_register failed: %d\n", ret);
return ret;
}
initialized = true;
}
return OK;
}
#endif /* CONFIG_HRTIM && CONFIG_STM32_HRTIM1 */

4
configs/stm32f103-minimum/src/Makefile
View file

@ -53,6 +53,10 @@ else
CSRCS += stm32_userleds.c
endif
ifeq ($(CONFIG_DEV_GPIO),y)
CSRCS += stm32_gpio.c
endif
ifeq ($(CONFIG_PWM),y)
CSRCS += stm32_pwm.c
endif

9
configs/stm32f103-minimum/src/stm32_bringup.c
View file

@ -112,6 +112,15 @@ int stm32_bringup(void)
#endif
int ret = OK;
#ifdef CONFIG_DEV_GPIO
ret = stm32_gpio_initialize();
if (ret < 0)
{
syslog(LOG_ERR, "Failed to initialize GPIO Driver: %d\n", ret);
return ret;
}
#endif
#ifdef CONFIG_MMCSD
ret = stm32_mmcsd_initialize(MMCSD_MINOR);
if (ret < 0)

332
configs/stm32f103-minimum/src/stm32_gpio.c Normal file
View file

@ -0,0 +1,332 @@
/****************************************************************************
* configs/stm32f103-minimum/src/stm32_gpio.c
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
* Copyright (C) 2017 Alan Carvalho de Assis. All rights reserved.
* Author: Alan Carvalho de Assis <acassis@gmail.com>
*
* Based on: configs/sim/src/sim_gpio.c
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdbool.h>
#include <assert.h>
#include <debug.h>
#include <nuttx/clock.h>
#include <nuttx/wdog.h>
#include <nuttx/ioexpander/gpio.h>
#include <arch/board/board.h>
#include "chip.h"
#include "stm32.h"
#include "stm32f103_minimum.h"
#if defined(CONFIG_DEV_GPIO) && !defined(CONFIG_GPIO_LOWER_HALF)
/****************************************************************************
* Private Types
****************************************************************************/
struct stm32gpio_dev_s
{
struct gpio_dev_s gpio;
uint8_t id;
};
struct stm32gpint_dev_s
{
struct stm32gpio_dev_s stm32gpio;
pin_interrupt_t callback;
};
/****************************************************************************
* Private Function Prototypes
****************************************************************************/
static int gpin_read(FAR struct gpio_dev_s *dev, FAR bool *value);
static int gpout_read(FAR struct gpio_dev_s *dev, FAR bool *value);
static int gpout_write(FAR struct gpio_dev_s *dev, bool value);
static int gpint_read(FAR struct gpio_dev_s *dev, FAR bool *value);
static int gpint_attach(FAR struct gpio_dev_s *dev,
pin_interrupt_t callback);
static int gpint_enable(FAR struct gpio_dev_s *dev, bool enable);
/****************************************************************************
* Private Data
****************************************************************************/
static const struct gpio_operations_s gpin_ops =
{
.go_read = gpin_read,
.go_write = NULL,
.go_attach = NULL,
.go_enable = NULL,
};
static const struct gpio_operations_s gpout_ops =
{
.go_read = gpout_read,
.go_write = gpout_write,
.go_attach = NULL,
.go_enable = NULL,
};
static const struct gpio_operations_s gpint_ops =
{
.go_read = gpint_read,
.go_write = NULL,
.go_attach = gpint_attach,
.go_enable = gpint_enable,
};
#if BOARD_NGPIOIN > 0
/* This array maps the GPIO pins used as INPUT */
static const uint32_t g_gpioinputs[BOARD_NGPIOIN] =
{
GPIO_IN1,
};
static struct stm32gpio_dev_s g_gpin[BOARD_NGPIOIN];
#endif
#if BOARD_NGPIOOUT
/* This array maps the GPIO pins used as OUTPUT */
static const uint32_t g_gpiooutputs[BOARD_NGPIOOUT] =
{
GPIO_OUT1,
};
static struct stm32gpio_dev_s g_gpout[BOARD_NGPIOOUT];
#endif
#if BOARD_NGPIOINT > 0
/* This array maps the GPIO pins used as INTERRUPT INPUTS */
static const uint32_t g_gpiointinputs[BOARD_NGPIOINT] =
{
GPIO_INT1,
};
static struct stm32gpint_dev_s g_gpint[BOARD_NGPIOINT];
#endif
/****************************************************************************
* Private Functions
****************************************************************************/
static int stm32gpio_interrupt(int irq, void *context, void *arg)
{
FAR struct stm32gpint_dev_s *stm32gpint = (FAR struct stm32gpint_dev_s *)arg;
DEBUGASSERT(stm32gpint != NULL && stm32gpint->callback != NULL);
gpioinfo("Interrupt! callback=%p\n", stm32gpint->callback);
stm32gpint->callback(&stm32gpint->stm32gpio.gpio);
return OK;
}
static int gpin_read(FAR struct gpio_dev_s *dev, FAR bool *value)
{
FAR struct stm32gpio_dev_s *stm32gpio = (FAR struct stm32gpio_dev_s *)dev;
DEBUGASSERT(stm32gpio != NULL && value != NULL);
DEBUGASSERT(stm32gpio->id < BOARD_NGPIOIN);
gpioinfo("Reading...\n");
*value = stm32_gpioread(g_gpioinputs[stm32gpio->id]);
return OK;
}
static int gpout_read(FAR struct gpio_dev_s *dev, FAR bool *value)
{
FAR struct stm32gpio_dev_s *stm32gpio = (FAR struct stm32gpio_dev_s *)dev;
DEBUGASSERT(stm32gpio != NULL && value != NULL);
DEBUGASSERT(stm32gpio->id < BOARD_NGPIOOUT);
gpioinfo("Reading...\n");
*value = stm32_gpioread(g_gpiooutputs[stm32gpio->id]);
return OK;
}
static int gpout_write(FAR struct gpio_dev_s *dev, bool value)
{
FAR struct stm32gpio_dev_s *stm32gpio = (FAR struct stm32gpio_dev_s *)dev;
DEBUGASSERT(stm32gpio != NULL);
DEBUGASSERT(stm32gpio->id < BOARD_NGPIOOUT);
gpioinfo("Writing %d\n", (int)value);
stm32_gpiowrite(g_gpiooutputs[stm32gpio->id], value);
return OK;
}
static int gpint_read(FAR struct gpio_dev_s *dev, FAR bool *value)
{
FAR struct stm32gpint_dev_s *stm32gpint = (FAR struct stm32gpint_dev_s *)dev;
DEBUGASSERT(stm32gpint != NULL && value != NULL);
DEBUGASSERT(stm32gpint->stm32gpio && stm32gpint->stm32gpio.id < BOARD_NGPIOINT);
gpioinfo("Reading int pin...\n");
*value = stm32_gpioread(g_gpiointinputs[stm32gpint->stm32gpio.id]);
return OK;
}
static int gpint_attach(FAR struct gpio_dev_s *dev,
pin_interrupt_t callback)
{
FAR struct stm32gpint_dev_s *stm32gpint = (FAR struct stm32gpint_dev_s *)dev;
gpioinfo("Attaching the callback\n");
/* Make sure the interrupt is disabled */
(void)stm32_gpiosetevent(g_gpiointinputs[stm32gpint->stm32gpio.id], false,
false, false, NULL, NULL);
gpioinfo("Attach %p\n", callback);
stm32gpint->callback = callback;
return OK;
}
static int gpint_enable(FAR struct gpio_dev_s *dev, bool enable)
{
FAR struct stm32gpint_dev_s *stm32gpint = (FAR struct stm32gpint_dev_s *)dev;
if (enable)
{
if (stm32gpint->callback != NULL)
{
gpioinfo("Enabling the interrupt\n");
/* Configure the interrupt for rising edge */
(void)stm32_gpiosetevent(g_gpiointinputs[stm32gpint->stm32gpio.id],
true, false, false, stm32gpio_interrupt,
&g_gpint[stm32gpint->stm32gpio.id]);
}
}
else
{
gpioinfo("Disable the interrupt\n");
(void)stm32_gpiosetevent(g_gpiointinputs[stm32gpint->stm32gpio.id],
false, false, false, NULL, NULL);
}
return OK;
}
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: stm32_gpio_initialize
*
* Description:
* Initialize GPIO drivers for use with /apps/examples/gpio
*
****************************************************************************/
int stm32_gpio_initialize(void)
{
int i;
int pincount = 0;
#if BOARD_NGPIOIN > 0
for (i = 0; i < BOARD_NGPIOIN; i++)
{
/* Setup and register the GPIO pin */
g_gpin[i].gpio.gp_pintype = GPIO_INPUT_PIN;
g_gpin[i].gpio.gp_ops = &gpin_ops;
g_gpin[i].id = i;
(void)gpio_pin_register(&g_gpin[i].gpio, pincount);
/* Configure the pin that will be used as input */
stm32_configgpio(g_gpioinputs[i]);
pincount++;
}
#endif
#if BOARD_NGPIOOUT > 0
for (i = 0; i < BOARD_NGPIOOUT; i++)
{
/* Setup and register the GPIO pin */
g_gpout[i].gpio.gp_pintype = GPIO_OUTPUT_PIN;
g_gpout[i].gpio.gp_ops = &gpout_ops;
g_gpout[i].id = i;
(void)gpio_pin_register(&g_gpout[i].gpio, pincount);
/* Configure the pin that will be used as output */
stm32_gpiowrite(g_gpiooutputs[i], 0);
stm32_configgpio(g_gpiooutputs[i]);
pincount++;
}
#endif
#if BOARD_NGPIOINT > 0
for (i = 0; i < BOARD_NGPIOINT; i++)
{
/* Setup and register the GPIO pin */
g_gpint[i].stm32gpio.gpio.gp_pintype = GPIO_INTERRUPT_PIN;
g_gpint[i].stm32gpio.gpio.gp_ops = &gpint_ops;
g_gpint[i].stm32gpio.id = i;
(void)gpio_pin_register(&g_gpint[i].stm32gpio.gpio, pincount);
/* Configure the pin that will be used as interrupt input */
stm32_configgpio(g_gpiointinputs[i]);
pincount++;
}
#endif
return 0;
}
#endif /* CONFIG_DEV_GPIO && !CONFIG_GPIO_LOWER_HALF */

2
configs/stm32f103-minimum/src/stm32_mfrc522.c
View file

@ -88,7 +88,7 @@ int stm32_mfrc522initialize(FAR const char *devpath)
}
/* Then register the MFRC522 */
ret = mfrc522_register(devpath, spi);
if (ret < 0)
{

2
configs/stm32f103-minimum/src/stm32_spi.c
View file

@ -136,7 +136,7 @@ void stm32_spi1select(FAR struct spi_dev_s *dev, uint32_t devid,
#endif
#if defined(CONFIG_CL_MFRC522)
if (devid == SPIDEV_WIRELESS(0))
if (devid == SPIDEV_CONTACTLESS(0))
{
stm32_gpiowrite(GPIO_CS_MFRC522, !selected);
}

2
configs/stm32f103-minimum/src/stm32_tone.c
View file

@ -2,7 +2,7 @@
* configs/stm32f103minimum/src/stm32_tone.c
*
* Copyright (C) 2016 Gregory Nutt. All rights reserved.
* Author: Alan Carvalho de Assis <acassis@gmail.com>
* Author: Alan Carvalho de Assis <acassis@gmail.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions

24
configs/stm32f103-minimum/src/stm32f103_minimum.h
View file

@ -129,6 +129,18 @@
#define GPIO_USB_PULLUP (GPIO_OUTPUT|GPIO_CNF_OUTPP|GPIO_MODE_50MHz|\
GPIO_OUTPUT_SET|GPIO_PORTC|GPIO_PIN13)
/* GPIO pins used by the GPIO Subsystem */
#define BOARD_NGPIOIN 1 /* Amount of GPIO Input pins */
#define BOARD_NGPIOOUT 1 /* Amount of GPIO Output pins */
#define BOARD_NGPIOINT 1 /* Amount of GPIO Input w/ Interruption pins */
#define GPIO_IN1 (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_PORTA|GPIO_PIN0)
#define GPIO_OUT1 (GPIO_OUTPUT|GPIO_CNF_OUTPP|GPIO_MODE_50MHz|\
GPIO_OUTPUT_SET|GPIO_PORTA|GPIO_PIN1)
#define GPIO_INT1 (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_PORTA|GPIO_PIN2)
/************************************************************************************
* Public Functions
************************************************************************************/
@ -155,6 +167,18 @@
int stm32_bringup(void);
/****************************************************************************
* Name: stm32_gpio_initialize
*
* Description:
* Initialize GPIO drivers for use with /apps/examples/gpio
*
****************************************************************************/
#ifdef CONFIG_DEV_GPIO
int stm32_gpio_initialize(void);
#endif
/************************************************************************************
* Name: stm32_spidev_initialize
*

3
configs/teensy-3.x/include/board.h
View file

@ -179,6 +179,9 @@
#define BOARD_USB_CLKSRC SIM_SOPT2_USBSRC
#define BOARD_USB_FREQ BOARD_SIM_CLKDIV2_FREQ
/* Allow USBOTG-FS Controller to Read from FLASH */
#define BOARD_USB_FLASHACCESS
/* PWM Configuration */
/* FTM0 Channels */

73
configs/teensy-3.x/nsh/defconfig
View file

@ -12,12 +12,6 @@
# CONFIG_HOST_OSX is not set
CONFIG_HOST_WINDOWS=y
# CONFIG_HOST_OTHER is not set
CONFIG_TOOLCHAIN_WINDOWS=y
# CONFIG_WINDOWS_NATIVE is not set
CONFIG_WINDOWS_CYGWIN=y
# CONFIG_WINDOWS_UBUNTU is not set
# CONFIG_WINDOWS_MSYS is not set
# CONFIG_WINDOWS_OTHER is not set
#
# Build Configuration
@ -34,6 +28,7 @@ CONFIG_INTELHEX_BINARY=y
# CONFIG_MOTOROLA_SREC is not set
CONFIG_RAW_BINARY=y
# CONFIG_UBOOT_UIMAGE is not set
# CONFIG_DFU_BINARY is not set
#
# Customize Header Files
@ -53,7 +48,7 @@ CONFIG_DEBUG_ALERT=y
CONFIG_ARCH_HAVE_STACKCHECK=y
# CONFIG_STACK_COLORATION is not set
# CONFIG_ARCH_HAVE_HEAPCHECK is not set
# CONFIG_DEBUG_SYMBOLS is not set
CONFIG_DEBUG_SYMBOLS=y
CONFIG_ARCH_HAVE_CUSTOMOPT=y
# CONFIG_DEBUG_NOOPT is not set
# CONFIG_DEBUG_CUSTOMOPT is not set
@ -95,6 +90,7 @@ CONFIG_ARCH_CHIP_KINETIS=y
# CONFIG_ARCH_CHIP_LPC2378 is not set
# CONFIG_ARCH_CHIP_LPC31XX is not set
# CONFIG_ARCH_CHIP_LPC43XX is not set
# CONFIG_ARCH_CHIP_MOXART is not set
# CONFIG_ARCH_CHIP_NUC1XX is not set
# CONFIG_ARCH_CHIP_SAMA5 is not set
# CONFIG_ARCH_CHIP_SAMD is not set
@ -102,11 +98,12 @@ CONFIG_ARCH_CHIP_KINETIS=y
# CONFIG_ARCH_CHIP_SAM34 is not set
# CONFIG_ARCH_CHIP_SAMV7 is not set
# CONFIG_ARCH_CHIP_STM32 is not set
# CONFIG_ARCH_CHIP_STM32F0 is not set
# CONFIG_ARCH_CHIP_STM32F7 is not set
# CONFIG_ARCH_CHIP_STM32L4 is not set
# CONFIG_ARCH_CHIP_STR71X is not set
# CONFIG_ARCH_CHIP_TMS570 is not set
# CONFIG_ARCH_CHIP_MOXART is not set
# CONFIG_ARCH_CHIP_XMC4 is not set
# CONFIG_ARCH_ARM7TDMI is not set
# CONFIG_ARCH_ARM926EJS is not set
# CONFIG_ARCH_ARM920T is not set
@ -127,8 +124,6 @@ CONFIG_ARCH_CORTEXM4=y
# CONFIG_ARCH_CORTEXR7F is not set
CONFIG_ARCH_FAMILY="armv7-m"
CONFIG_ARCH_CHIP="kinetis"
# CONFIG_ARCH_TOOLCHAIN_IAR is not set
CONFIG_ARCH_TOOLCHAIN_GNU=y
# CONFIG_ARMV7M_USEBASEPRI is not set
CONFIG_ARCH_HAVE_CMNVECTOR=y
# CONFIG_ARMV7M_CMNVECTOR is not set
@ -147,15 +142,11 @@ CONFIG_ARM_HAVE_MPU_UNIFIED=y
# CONFIG_ARMV7M_HAVE_DCACHE is not set
# CONFIG_ARMV7M_HAVE_ITCM is not set
# CONFIG_ARMV7M_HAVE_DTCM is not set
# CONFIG_ARMV7M_TOOLCHAIN_IARW is not set
# CONFIG_ARMV7M_TOOLCHAIN_ATOLLIC is not set
# CONFIG_ARMV7M_TOOLCHAIN_IARL is not set
# CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT is not set
# CONFIG_ARMV7M_TOOLCHAIN_CODEREDW is not set
# CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYW is not set
# CONFIG_ARMV7M_TOOLCHAIN_DEVKITARM is not set
# CONFIG_ARMV7M_TOOLCHAIN_GNU_EABIL is not set
CONFIG_ARMV7M_TOOLCHAIN_GNU_EABIW=y
# CONFIG_ARMV7M_TOOLCHAIN_RAISONANCE is not set
# CONFIG_ARMV7M_TOOLCHAIN_CODEREDL is not set
# CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYL is not set
CONFIG_ARMV7M_TOOLCHAIN_GNU_EABIL=y
# CONFIG_ARMV7M_HAVE_STACKCHECK is not set
# CONFIG_ARMV7M_ITMSYSLOG is not set
@ -199,6 +190,7 @@ CONFIG_ARCH_CHIP_MK20DX256VLH7=y
CONFIG_KINETIS_HAVE_UART5=y
# CONFIG_KINETIS_HAVE_LPUART0 is not set
# CONFIG_KINETIS_HAVE_LPUART1 is not set
CONFIG_KINETIS_SERIALDRIVER=y
# CONFIG_KINETIS_LPUART is not set
CONFIG_KINETIS_UART=y
CONFIG_ARCH_FAMILY_K20=y
@ -210,11 +202,14 @@ CONFIG_ARCH_FAMILY_K20=y
#
# Kinetis Peripheral Support
#
# CONFIG_KINETIS_HAVE_FTM3 is not set
CONFIG_KINETIS_HAVE_I2C1=y
# CONFIG_KINETIS_HAVE_I2C2 is not set
# CONFIG_KINETIS_HAVE_I2C3 is not set
# CONFIG_KINETIS_HAVE_SPI1 is not set
# CONFIG_KINETIS_HAVE_SPI2 is not set
# CONFIG_KINETIS_HAVE_TPM1 is not set
# CONFIG_KINETIS_HAVE_TPM2 is not set
# CONFIG_KINETIS_TRACE is not set
# CONFIG_KINETIS_FLEXBUS is not set
CONFIG_KINETIS_UART0=y
@ -261,7 +256,18 @@ CONFIG_KINETIS_UART0=y
#
# Kinetis UART Configuration
#
#
# Serial Driver Configuration
#
CONFIG_KINETIS_UART_BREAKS=y
# CONFIG_KINETIS_UART_EXTEDED_BREAK is not set
CONFIG_KINETIS_SERIALBRK_BSDCOMPAT=y
# CONFIG_KINETIS_UART_SINGLEWIRE is not set
CONFIG_KINETIS_UARTFIFOS=y
CONFIG_SERIAL_TERMIOS=y
# CONFIG_ARCH_TOOLCHAIN_IAR is not set
CONFIG_ARCH_TOOLCHAIN_GNU=y
#
# Architecture Options
@ -282,6 +288,7 @@ CONFIG_ARCH_HAVE_MPU=y
# CONFIG_ARCH_HAVE_EXTCLK is not set
# CONFIG_ARCH_HAVE_POWEROFF is not set
CONFIG_ARCH_HAVE_RESET=y
# CONFIG_ARCH_HAVE_RTC_SUBSECONDS is not set
# CONFIG_ARCH_USE_MPU is not set
# CONFIG_ARCH_IRQPRIO is not set
CONFIG_ARCH_STACKDUMP=y
@ -389,6 +396,8 @@ CONFIG_SCHED_WAITPID=y
#
# CONFIG_PTHREAD_MUTEX_TYPES is not set
CONFIG_PTHREAD_MUTEX_ROBUST=y
# CONFIG_PTHREAD_MUTEX_UNSAFE is not set
# CONFIG_PTHREAD_MUTEX_BOTH is not set
CONFIG_NPTHREAD_KEYS=4
# CONFIG_PTHREAD_CLEANUP is not set
# CONFIG_CANCELLATION_POINTS is not set
@ -469,7 +478,7 @@ CONFIG_DEV_NULL=y
# CONFIG_ARCH_HAVE_PWM_PULSECOUNT is not set
# CONFIG_ARCH_HAVE_PWM_MULTICHAN is not set
# CONFIG_PWM is not set
# CONFIG_ARCH_HAVE_I2CRESET is not set
CONFIG_ARCH_HAVE_I2CRESET=y
# CONFIG_I2C is not set
# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set
# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set
@ -557,7 +566,7 @@ CONFIG_STANDARD_SERIAL=y
# CONFIG_SERIAL_IFLOWCONTROL is not set
# CONFIG_SERIAL_OFLOWCONTROL is not set
# CONFIG_SERIAL_DMA is not set
# CONFIG_ARCH_HAVE_SERIAL_TERMIOS is not set
CONFIG_ARCH_HAVE_SERIAL_TERMIOS=y
CONFIG_UART0_SERIAL_CONSOLE=y
# CONFIG_OTHER_SERIAL_CONSOLE is not set
# CONFIG_NO_SERIAL_CONSOLE is not set
@ -577,6 +586,7 @@ CONFIG_UART0_2STOP=0
# CONFIG_PSEUDOTERM is not set
# CONFIG_USBDEV is not set
# CONFIG_USBHOST is not set
# CONFIG_USBMISC is not set
# CONFIG_HAVE_USBTRACE is not set
# CONFIG_DRIVERS_WIRELESS is not set
# CONFIG_DRIVERS_CONTACTLESS is not set
@ -585,7 +595,9 @@ CONFIG_UART0_2STOP=0
# System Logging
#
# CONFIG_ARCH_SYSLOG is not set
CONFIG_SYSLOG_WRITE=y
# CONFIG_RAMLOG is not set
# CONFIG_SYSLOG_BUFFER is not set
# CONFIG_SYSLOG_INTBUFFER is not set
# CONFIG_SYSLOG_TIMESTAMP is not set
CONFIG_SYSLOG_SERIAL_CONSOLE=y
@ -645,6 +657,11 @@ CONFIG_MM_REGIONS=1
# CONFIG_ARCH_HAVE_HEAP2 is not set
# CONFIG_GRAN is not set
#
# Common I/O Buffer Support
#
# CONFIG_MM_IOB is not set
#
# Audio Support
#
@ -653,6 +670,7 @@ CONFIG_MM_REGIONS=1
#
# Wireless Support
#
# CONFIG_WIRELESS is not set
#
# Binary Loader
@ -808,13 +826,12 @@ CONFIG_BUILTIN_PROXY_STACKSIZE=1024
# CONFIG_EXAMPLES_MM is not set
# CONFIG_EXAMPLES_MODBUS is not set
# CONFIG_EXAMPLES_MOUNT is not set
# CONFIG_EXAMPLES_NRF24L01TERM is not set
CONFIG_EXAMPLES_NSH=y
# CONFIG_EXAMPLES_NULL is not set
# CONFIG_EXAMPLES_NX is not set
# CONFIG_EXAMPLES_NXFFS is not set
# CONFIG_EXAMPLES_NXHELLO is not set
# CONFIG_EXAMPLES_NXIMAGE is not set
# CONFIG_EXAMPLES_NX is not set
# CONFIG_EXAMPLES_NXLINES is not set
# CONFIG_EXAMPLES_NXTERM is not set
# CONFIG_EXAMPLES_NXTEXT is not set
@ -839,6 +856,7 @@ CONFIG_EXAMPLES_NSH=y
# CONFIG_EXAMPLES_TOUCHSCREEN is not set
# CONFIG_EXAMPLES_WATCHDOG is not set
# CONFIG_EXAMPLES_WEBSERVER is not set
# CONFIG_EXAMPLES_XBC_TEST is not set
#
# File System Utilities
@ -1006,3 +1024,14 @@ CONFIG_READLINE_ECHO=y
# CONFIG_SYSTEM_UBLOXMODEM is not set
# CONFIG_SYSTEM_VI is not set
# CONFIG_SYSTEM_ZMODEM is not set
#
# Wireless Libraries and NSH Add-Ons
#
#
# IEEE 802.15.4 applications
#
# CONFIG_IEEE802154_LIBMAC is not set
# CONFIG_IEEE802154_LIBUTILS is not set
# CONFIG_IEEE802154_I8SAK is not set

8
configs/teensy-3.x/src/k20_appinit.c
View file

@ -80,14 +80,6 @@ int board_app_initialize(uintptr_t arg)
{
int ret;
#ifdef CONFIG_USBDEV
/* Teensy is powered from usb and (bug?) only boots from being programmed,
* so if usb is compiled in signal the controller driver that we're attached now.
*/
khci_usbattach();
#endif
#ifdef CONFIG_PWM
/* Initialize PWM and register the PWM device. */

58
configs/teensy-3.x/usbnsh/defconfig
View file

@ -28,6 +28,7 @@ CONFIG_INTELHEX_BINARY=y
# CONFIG_MOTOROLA_SREC is not set
CONFIG_RAW_BINARY=y
# CONFIG_UBOOT_UIMAGE is not set
# CONFIG_DFU_BINARY is not set
#
# Customize Header Files
@ -89,6 +90,7 @@ CONFIG_ARCH_CHIP_KINETIS=y
# CONFIG_ARCH_CHIP_LPC2378 is not set
# CONFIG_ARCH_CHIP_LPC31XX is not set
# CONFIG_ARCH_CHIP_LPC43XX is not set
# CONFIG_ARCH_CHIP_MOXART is not set
# CONFIG_ARCH_CHIP_NUC1XX is not set
# CONFIG_ARCH_CHIP_SAMA5 is not set
# CONFIG_ARCH_CHIP_SAMD is not set
@ -96,11 +98,12 @@ CONFIG_ARCH_CHIP_KINETIS=y
# CONFIG_ARCH_CHIP_SAM34 is not set
# CONFIG_ARCH_CHIP_SAMV7 is not set
# CONFIG_ARCH_CHIP_STM32 is not set
# CONFIG_ARCH_CHIP_STM32F0 is not set
# CONFIG_ARCH_CHIP_STM32F7 is not set
# CONFIG_ARCH_CHIP_STM32L4 is not set
# CONFIG_ARCH_CHIP_STR71X is not set
# CONFIG_ARCH_CHIP_TMS570 is not set
# CONFIG_ARCH_CHIP_MOXART is not set
# CONFIG_ARCH_CHIP_XMC4 is not set
# CONFIG_ARCH_ARM7TDMI is not set
# CONFIG_ARCH_ARM926EJS is not set
# CONFIG_ARCH_ARM920T is not set
@ -121,8 +124,6 @@ CONFIG_ARCH_CORTEXM4=y
# CONFIG_ARCH_CORTEXR7F is not set
CONFIG_ARCH_FAMILY="armv7-m"
CONFIG_ARCH_CHIP="kinetis"
# CONFIG_ARCH_TOOLCHAIN_IAR is not set
CONFIG_ARCH_TOOLCHAIN_GNU=y
# CONFIG_ARMV7M_USEBASEPRI is not set
CONFIG_ARCH_HAVE_CMNVECTOR=y
# CONFIG_ARMV7M_CMNVECTOR is not set
@ -189,6 +190,7 @@ CONFIG_ARCH_CHIP_MK20DX256VLH7=y
CONFIG_KINETIS_HAVE_UART5=y
# CONFIG_KINETIS_HAVE_LPUART0 is not set
# CONFIG_KINETIS_HAVE_LPUART1 is not set
CONFIG_KINETIS_SERIALDRIVER=y
# CONFIG_KINETIS_LPUART is not set
CONFIG_KINETIS_UART=y
CONFIG_ARCH_FAMILY_K20=y
@ -200,11 +202,14 @@ CONFIG_ARCH_FAMILY_K20=y
#
# Kinetis Peripheral Support
#
# CONFIG_KINETIS_HAVE_FTM3 is not set
CONFIG_KINETIS_HAVE_I2C1=y
# CONFIG_KINETIS_HAVE_I2C2 is not set
# CONFIG_KINETIS_HAVE_I2C3 is not set
# CONFIG_KINETIS_HAVE_SPI1 is not set
# CONFIG_KINETIS_HAVE_SPI2 is not set
# CONFIG_KINETIS_HAVE_TPM1 is not set
# CONFIG_KINETIS_HAVE_TPM2 is not set
# CONFIG_KINETIS_TRACE is not set
# CONFIG_KINETIS_FLEXBUS is not set
CONFIG_KINETIS_UART0=y
@ -251,7 +256,18 @@ CONFIG_KINETIS_USBOTG=y
#
# Kinetis UART Configuration
#
#
# Serial Driver Configuration
#
CONFIG_KINETIS_UART_BREAKS=y
# CONFIG_KINETIS_UART_EXTEDED_BREAK is not set
CONFIG_KINETIS_SERIALBRK_BSDCOMPAT=y
# CONFIG_KINETIS_UART_SINGLEWIRE is not set
CONFIG_KINETIS_UARTFIFOS=y
CONFIG_SERIAL_TERMIOS=y
# CONFIG_ARCH_TOOLCHAIN_IAR is not set
CONFIG_ARCH_TOOLCHAIN_GNU=y
#
# Architecture Options
@ -272,6 +288,7 @@ CONFIG_ARCH_HAVE_MPU=y
# CONFIG_ARCH_HAVE_EXTCLK is not set
# CONFIG_ARCH_HAVE_POWEROFF is not set
CONFIG_ARCH_HAVE_RESET=y
# CONFIG_ARCH_HAVE_RTC_SUBSECONDS is not set
# CONFIG_ARCH_USE_MPU is not set
# CONFIG_ARCH_IRQPRIO is not set
CONFIG_ARCH_STACKDUMP=y
@ -386,6 +403,8 @@ CONFIG_SCHED_WAITPID=y
#
# CONFIG_PTHREAD_MUTEX_TYPES is not set
CONFIG_PTHREAD_MUTEX_ROBUST=y
# CONFIG_PTHREAD_MUTEX_UNSAFE is not set
# CONFIG_PTHREAD_MUTEX_BOTH is not set
CONFIG_NPTHREAD_KEYS=4
# CONFIG_PTHREAD_CLEANUP is not set
# CONFIG_CANCELLATION_POINTS is not set
@ -466,7 +485,7 @@ CONFIG_DEV_NULL=y
# CONFIG_ARCH_HAVE_PWM_PULSECOUNT is not set
# CONFIG_ARCH_HAVE_PWM_MULTICHAN is not set
# CONFIG_PWM is not set
# CONFIG_ARCH_HAVE_I2CRESET is not set
CONFIG_ARCH_HAVE_I2CRESET=y
# CONFIG_I2C is not set
# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set
# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set
@ -554,7 +573,7 @@ CONFIG_STANDARD_SERIAL=y
# CONFIG_SERIAL_IFLOWCONTROL is not set
# CONFIG_SERIAL_OFLOWCONTROL is not set
# CONFIG_SERIAL_DMA is not set
# CONFIG_ARCH_HAVE_SERIAL_TERMIOS is not set
CONFIG_ARCH_HAVE_SERIAL_TERMIOS=y
CONFIG_UART0_SERIAL_CONSOLE=y
# CONFIG_OTHER_SERIAL_CONSOLE is not set
# CONFIG_NO_SERIAL_CONSOLE is not set
@ -579,8 +598,8 @@ CONFIG_USBDEV=y
#
# CONFIG_USBDEV_ISOCHRONOUS is not set
CONFIG_USBDEV_DUALSPEED=y
CONFIG_USBDEV_SELFPOWERED=y
# CONFIG_USBDEV_BUSPOWERED is not set
# CONFIG_USBDEV_SELFPOWERED is not set
CONFIG_USBDEV_BUSPOWERED=y
CONFIG_USBDEV_MAXPOWER=100
# CONFIG_USBDEV_DMA is not set
# CONFIG_ARCH_USBDEV_STALLQUEUE is not set
@ -617,6 +636,7 @@ CONFIG_CDCACM_VENDORSTR="NuttX"
CONFIG_CDCACM_PRODUCTSTR="CDC/ACM Serial"
# CONFIG_USBMSC is not set
# CONFIG_USBHOST is not set
# CONFIG_USBMISC is not set
CONFIG_HAVE_USBTRACE=y
CONFIG_USBMONITOR=y
CONFIG_USBMONITOR_STACKSIZE=2048
@ -634,7 +654,9 @@ CONFIG_USBMONITOR_TRACEINTERRUPTS=y
# System Logging
#
# CONFIG_ARCH_SYSLOG is not set
CONFIG_SYSLOG_WRITE=y
# CONFIG_RAMLOG is not set
# CONFIG_SYSLOG_BUFFER is not set
# CONFIG_SYSLOG_INTBUFFER is not set
# CONFIG_SYSLOG_TIMESTAMP is not set
CONFIG_SYSLOG_SERIAL_CONSOLE=y
@ -694,6 +716,11 @@ CONFIG_MM_REGIONS=1
# CONFIG_ARCH_HAVE_HEAP2 is not set
# CONFIG_GRAN is not set
#
# Common I/O Buffer Support
#
# CONFIG_MM_IOB is not set
#
# Audio Support
#
@ -858,13 +885,12 @@ CONFIG_BUILTIN_PROXY_STACKSIZE=1024
# CONFIG_EXAMPLES_MM is not set
# CONFIG_EXAMPLES_MODBUS is not set
# CONFIG_EXAMPLES_MOUNT is not set
# CONFIG_EXAMPLES_NRF24L01TERM is not set
CONFIG_EXAMPLES_NSH=y
# CONFIG_EXAMPLES_NULL is not set
# CONFIG_EXAMPLES_NX is not set
# CONFIG_EXAMPLES_NXFFS is not set
# CONFIG_EXAMPLES_NXHELLO is not set
# CONFIG_EXAMPLES_NXIMAGE is not set
# CONFIG_EXAMPLES_NX is not set
# CONFIG_EXAMPLES_NXLINES is not set
# CONFIG_EXAMPLES_NXTERM is not set
# CONFIG_EXAMPLES_NXTEXT is not set
@ -890,6 +916,7 @@ CONFIG_EXAMPLES_NSH=y
# CONFIG_EXAMPLES_USBSERIAL is not set
# CONFIG_EXAMPLES_WATCHDOG is not set
# CONFIG_EXAMPLES_WEBSERVER is not set
# CONFIG_EXAMPLES_XBC_TEST is not set
#
# File System Utilities
@ -1062,6 +1089,8 @@ CONFIG_SYSTEM_HEXED_STACKSIZE=2048
CONFIG_SYSTEM_HEXED_PRIORITY=100
# CONFIG_SYSTEM_INSTALL is not set
CONFIG_SYSTEM_RAMTEST=y
CONFIG_SYSTEM_RAMTEST_PRIORITY=100
CONFIG_SYSTEM_RAMTEST_STACKSIZE=1024
CONFIG_READLINE_HAVE_EXTMATCH=y
CONFIG_SYSTEM_READLINE=y
CONFIG_READLINE_ECHO=y
@ -1077,3 +1106,14 @@ CONFIG_READLINE_CMD_HISTORY_LEN=16
# CONFIG_SYSTEM_UBLOXMODEM is not set
# CONFIG_SYSTEM_VI is not set
# CONFIG_SYSTEM_ZMODEM is not set
#
# Wireless Libraries and NSH Add-Ons
#
#
# IEEE 802.15.4 applications
#
# CONFIG_IEEE802154_LIBMAC is not set
# CONFIG_IEEE802154_LIBUTILS is not set
# CONFIG_IEEE802154_I8SAK is not set

9
drivers/mtd/at25.c
View file

@ -524,6 +524,12 @@ static ssize_t at25_read(FAR struct mtd_dev_s *dev, off_t offset, size_t nbytes,
finfo("offset: %08lx nbytes: %d\n", (long)offset, (int)nbytes);
/* Lock the SPI bus NOW because the following call must be executed with
* the bus locked.
*/
at25_lock(priv->dev);
/* Wait for any preceding write to complete. We could simplify things by
* perform this wait at the end of each write operation (rather than at
* the beginning of ALL operations), but have the wait first will slightly
@ -532,9 +538,8 @@ static ssize_t at25_read(FAR struct mtd_dev_s *dev, off_t offset, size_t nbytes,
at25_waitwritecomplete(priv);
/* Lock the SPI bus and select this FLASH part */
/* Select this FLASH part */
at25_lock(priv->dev);
SPI_SELECT(priv->dev, SPIDEV_FLASH(0), true);
/* Send "Read from Memory " instruction */

19
drivers/mtd/is25xp.c
View file

@ -4,7 +4,7 @@
*
* Copyright (C) 2016 Marten Svanfeldt. All rights reserved.
*
* Copyright (C) 2009-2011, 2013 Gregory Nutt. All rights reserved.
* Copyright (C) 2009-2011, 2013, 2017 Gregory Nutt. All rights reserved.
* Author: Ken Pettit <pettitkd@gmail.com>
*
* Copied from / based on m25px.c and sst25.c drivers written by
@ -568,8 +568,9 @@ static inline void is25xp_pagewrite(struct is25xp_dev_s *priv, FAR const uint8_t
************************************************************************************/
#ifdef CONFIG_MTD_BYTE_WRITE
static inline void is25xp_bytewrite(struct is25xp_dev_s *priv, FAR const uint8_t *buffer,
off_t offset, uint16_t count)
static inline void is25xp_bytewrite(struct is25xp_dev_s *priv,
FAR const uint8_t *buffer, off_t offset,
uint16_t count)
{
finfo("offset: %08lx count:%d\n", (long)offset, count);
@ -748,6 +749,12 @@ static ssize_t is25xp_read(FAR struct mtd_dev_s *dev, off_t offset, size_t nbyte
finfo("offset: %08lx nbytes: %d\n", (long)offset, (int)nbytes);
/* Lock the SPI bus NOW because the following call must be executed with
* the bus locked.
*/
is25xp_lock(priv->dev);
/* Wait for any preceding write to complete. We could simplify things by
* perform this wait at the end of each write operation (rather than at
* the beginning of ALL operations), but have the wait first will slightly
@ -759,9 +766,8 @@ static ssize_t is25xp_read(FAR struct mtd_dev_s *dev, off_t offset, size_t nbyte
is25xp_waitwritecomplete(priv);
}
/* Lock the SPI bus and select this FLASH part */
/* Select this FLASH part */
is25xp_lock(priv->dev);
SPI_SELECT(priv->dev, SPIDEV_FLASH(0), true);
/* Send "Read from Memory " instruction */
@ -782,6 +788,7 @@ static ssize_t is25xp_read(FAR struct mtd_dev_s *dev, off_t offset, size_t nbyte
SPI_SELECT(priv->dev, SPIDEV_FLASH(0), false);
is25xp_unlock(priv->dev);
finfo("return nbytes: %d\n", (int)nbytes);
return nbytes;
}
@ -812,6 +819,7 @@ static ssize_t is25xp_write(FAR struct mtd_dev_s *dev, off_t offset, size_t nbyt
startpage = offset / (1 << priv->pageshift);
endpage = (offset + nbytes) / (1 << priv->pageshift);
is25xp_lock(priv->dev);
if (startpage == endpage)
{
/* All bytes within one programmable page. Just do the write. */
@ -856,6 +864,7 @@ static ssize_t is25xp_write(FAR struct mtd_dev_s *dev, off_t offset, size_t nbyt
priv->lastwaswrite = true;
}
is25xp_unlock(priv->dev);
return nbytes;
}
#endif /* CONFIG_MTD_BYTE_WRITE */

16
drivers/mtd/m25px.c
View file

@ -3,7 +3,7 @@
* Driver for SPI-based M25P1 (128Kbit), M25P64 (32Mbit), M25P64 (64Mbit), and
* M25P128 (128Mbit) FLASH (and compatible).
*
* Copyright (C) 2009-2011, 2013 Gregory Nutt. All rights reserved.
* Copyright (C) 2009-2011, 2013, 2017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
@ -798,6 +798,12 @@ static ssize_t m25p_read(FAR struct mtd_dev_s *dev, off_t offset, size_t nbytes,
finfo("offset: %08lx nbytes: %d\n", (long)offset, (int)nbytes);
/* Lock the SPI bus NOW because the following call must be executed with
* the bus locked.
*/
m25p_lock(priv->dev);
/* Wait for any preceding write to complete. We could simplify things by
* perform this wait at the end of each write operation (rather than at
* the beginning of ALL operations), but have the wait first will slightly
@ -806,12 +812,11 @@ static ssize_t m25p_read(FAR struct mtd_dev_s *dev, off_t offset, size_t nbytes,
m25p_waitwritecomplete(priv);
/* Lock the SPI bus and select this FLASH part */
/* Select this FLASH part */
m25p_lock(priv->dev);
SPI_SELECT(priv->dev, SPIDEV_FLASH(0), true);
/* Send "Read from Memory " instruction */
/* Send "Read from Memory" instruction */
(void)SPI_SEND(priv->dev, M25P_READ);
@ -829,6 +834,7 @@ static ssize_t m25p_read(FAR struct mtd_dev_s *dev, off_t offset, size_t nbytes,
SPI_SELECT(priv->dev, SPIDEV_FLASH(0), false);
m25p_unlock(priv->dev);
finfo("return nbytes: %d\n", (int)nbytes);
return nbytes;
}
@ -859,6 +865,7 @@ static ssize_t m25p_write(FAR struct mtd_dev_s *dev, off_t offset, size_t nbytes
startpage = offset / (1 << priv->pageshift);
endpage = (offset + nbytes) / (1 << priv->pageshift);
m25p_lock(priv->dev);
if (startpage == endpage)
{
/* All bytes within one programmable page. Just do the write. */
@ -901,6 +908,7 @@ static ssize_t m25p_write(FAR struct mtd_dev_s *dev, off_t offset, size_t nbytes
}
}
m25p_unlock(priv->dev);
return nbytes;
}
#endif /* CONFIG_MTD_BYTE_WRITE */

13
drivers/mtd/ramtron.c
View file

@ -532,8 +532,8 @@ static inline void ramtron_sendaddr(const struct ramtron_dev_s *priv, uint32_t a
* Name: ramtron_pagewrite
************************************************************************************/
static inline int ramtron_pagewrite(struct ramtron_dev_s *priv, FAR const uint8_t *buffer,
off_t page)
static inline int ramtron_pagewrite(struct ramtron_dev_s *priv,
FAR const uint8_t *buffer, off_t page)
{
off_t offset = page << priv->pageshift;
@ -663,6 +663,12 @@ static ssize_t ramtron_read(FAR struct mtd_dev_s *dev, off_t offset, size_t nbyt
finfo("offset: %08lx nbytes: %d\n", (long)offset, (int)nbytes);
/* Lock the SPI bus NOW because the ramtron_waitwritecomplete call must be
* executed with the bus locked.
*/
ramtron_lock(priv);
#ifndef CONFIG_RAMTRON_WRITEWAIT
/* Wait for any preceding write to complete. We could simplify things by
* perform this wait at the end of each write operation (rather than at
@ -673,9 +679,8 @@ static ssize_t ramtron_read(FAR struct mtd_dev_s *dev, off_t offset, size_t nbyt
(void)ramtron_waitwritecomplete(priv);
#endif
/* Lock the SPI bus and select this FLASH part */
/* Select this FLASH part */
ramtron_lock(priv);
SPI_SELECT(priv->dev, SPIDEV_FLASH(0), true);
/* Send "Read from Memory " instruction */

19
drivers/mtd/sst25xx.c
View file

@ -546,8 +546,9 @@ static inline void sst25xx_pagewrite(struct sst25xx_dev_s *priv, FAR const uint8
************************************************************************************/
#ifdef CONFIG_MTD_BYTE_WRITE
static inline void sst25xx_bytewrite(struct sst25xx_dev_s *priv, FAR const uint8_t *buffer,
off_t offset, uint16_t count)
static inline void sst25xx_bytewrite(struct sst25xx_dev_s *priv,
FAR const uint8_t *buffer, off_t offset,
uint16_t count)
{
finfo("offset: %08lx count:%d\n", (long)offset, count);
@ -679,7 +680,8 @@ static ssize_t sst25xx_bread(FAR struct mtd_dev_s *dev, off_t startblock, size_t
/* On this device, we can handle the block read just like the byte-oriented read */
nbytes = sst25xx_read(dev, startblock << priv->pageshift, nblocks << priv->pageshift, buffer);
nbytes = sst25xx_read(dev, startblock << priv->pageshift,
nblocks << priv->pageshift, buffer);
if (nbytes > 0)
{
return nbytes >> priv->pageshift;
@ -726,6 +728,12 @@ static ssize_t sst25xx_read(FAR struct mtd_dev_s *dev, off_t offset, size_t nbyt
finfo("offset: %08lx nbytes: %d\n", (long)offset, (int)nbytes);
/* Lock the SPI bus NOW because the following conditional call to
* sst25xx_waitwritecomplete must be executed with the bus locked.
*/
sst25xx_lock(priv->dev);
/* Wait for any preceding write to complete. We could simplify things by
* perform this wait at the end of each write operation (rather than at
* the beginning of ALL operations), but have the wait first will slightly
@ -737,9 +745,8 @@ static ssize_t sst25xx_read(FAR struct mtd_dev_s *dev, off_t offset, size_t nbyt
sst25xx_waitwritecomplete(priv);
}
/* Lock the SPI bus and select this FLASH part */
/* Select this FLASH part */
sst25xx_lock(priv->dev);
SPI_SELECT(priv->dev, SPIDEV_FLASH(0), true);
/* Send "Read from Memory " instruction */
@ -790,6 +797,7 @@ static ssize_t sst25xx_write(FAR struct mtd_dev_s *dev, off_t offset, size_t nby
startpage = offset / (1 << priv->pageshift);
endpage = (offset + nbytes) / (1 << priv->pageshift);
sst25xx_lock(priv->dev);
if (startpage == endpage)
{
/* All bytes within one programmable page. Just do the write. */
@ -834,6 +842,7 @@ static ssize_t sst25xx_write(FAR struct mtd_dev_s *dev, off_t offset, size_t nby
priv->lastwaswrite = true;
}
sst25xx_unlock(priv->dev);
return nbytes;
}
#endif /* CONFIG_MTD_BYTE_WRITE */

4
drivers/mtd/sst26.c
View file

@ -8,7 +8,7 @@
*
* For SST25VF064, see sst25cxx.c driver instead.
*
* Copyright (C) 2009-2011, 2013, 2016 Gregory Nutt. All rights reserved.
* Copyright (C) 2009-2011, 2013, 2016-2017 Gregory Nutt. All rights reserved.
* Author: Ken Pettit <pettitkd@gmail.com>
* Author: Sebastien Lorquet <sebastien@lorquet.fr>
*
@ -791,6 +791,7 @@ static ssize_t sst26_write(FAR struct mtd_dev_s *dev, off_t offset, size_t nbyte
startpage = offset / (1 << priv->pageshift);
endpage = (offset + nbytes) / (1 << priv->pageshift);
sst26_lock(priv->dev);
if (startpage == endpage)
{
/* All bytes within one programmable page. Just do the write. */
@ -835,6 +836,7 @@ static ssize_t sst26_write(FAR struct mtd_dev_s *dev, off_t offset, size_t nbyte
priv->lastwaswrite = true;
}
sst26_unlock(priv->dev);
return nbytes;
}
#endif /* CONFIG_MTD_BYTE_WRITE */

40
drivers/mtd/w25.c
View file

@ -2,7 +2,7 @@
* drivers/mtd/w25.c
* Driver for SPI-based W25x16, x32, and x64 and W25q16, q32, q64, and q128 FLASH
*
* Copyright (C) 2012-2013 Gregory Nutt. All rights reserved.
* Copyright (C) 2012-2013, 2017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
@ -337,9 +337,16 @@ static inline int w25_readid(struct w25_dev_s *priv)
finfo("priv: %p\n", priv);
/* Lock the SPI bus, configure the bus, and select this FLASH part. */
/* Lock and configure the SPI bus */
w25_lock(priv->spi);
/* Wait for any preceding write or erase operation to complete. */
(void)w25_waitwritecomplete(priv);
/* Select this FLASH part. */
SPI_SELECT(priv->spi, SPIDEV_FLASH(0), true);
/* Send the "Read ID (RDID)" command and read the first three ID bytes */
@ -440,19 +447,20 @@ static inline int w25_readid(struct w25_dev_s *priv)
#ifndef CONFIG_W25_READONLY
static void w25_unprotect(FAR struct w25_dev_s *priv)
{
/* Select this FLASH part */
/* Lock and configure the SPI bus */
SPI_SELECT(priv->spi, SPIDEV_FLASH(0), true);
w25_lock(priv->spi);
/* Wait for any preceding write or erase operation to complete. */
(void)w25_waitwritecomplete(priv);
/* Send "Write enable (WREN)" */
w25_wren(priv);
/* Re-select this FLASH part (This might not be necessary... but is it shown in
* the SST25 timing diagrams from which this code was leveraged.)
*/
/* Select this FLASH part */
SPI_SELECT(priv->spi, SPIDEV_FLASH(0), false);
SPI_SELECT(priv->spi, SPIDEV_FLASH(0), true);
/* Send "Write enable status (EWSR)" */
@ -463,6 +471,11 @@ static void w25_unprotect(FAR struct w25_dev_s *priv)
SPI_SEND(priv->spi, 0);
SPI_SEND(priv->spi, 0);
/* Deselect the FLASH and unlock the bus */
SPI_SELECT(priv->spi, SPIDEV_FLASH(0), false);
w25_unlock(priv->spi);
}
#endif
@ -474,7 +487,11 @@ static uint8_t w25_waitwritecomplete(struct w25_dev_s *priv)
{
uint8_t status;
/* Loop as long as the memory is busy with a write cycle */
/* Loop as long as the memory is busy with a write cycle. Device sets BUSY
* flag to a 1 state whhen previous write or erase command is still executing
* and during this time, device will ignore further instructions except for
* "Read Status Register" and "Erase/Program Suspend" instructions.
*/
do
{
@ -802,7 +819,7 @@ static void w25_pagewrite(struct w25_dev_s *priv, FAR const uint8_t *buffer,
#if defined(CONFIG_MTD_BYTE_WRITE) && !defined(CONFIG_W25_READONLY)
static inline void w25_bytewrite(struct w25_dev_s *priv, FAR const uint8_t *buffer,
off_t offset, uint16_t count)
off_t offset, uint16_t count)
{
finfo("offset: %08lx count:%d\n", (long)offset, count);
@ -1070,6 +1087,7 @@ static ssize_t w25_bread(FAR struct mtd_dev_s *dev, off_t startblock, size_t nbl
{
nbytes >>= W25_SECTOR512_SHIFT;
}
#else
nbytes = w25_read(dev, startblock << W25_PAGE_SHIFT, nblocks << W25_PAGE_SHIFT, buffer);
if (nbytes > 0)
@ -1157,6 +1175,7 @@ static ssize_t w25_write(FAR struct mtd_dev_s *dev, off_t offset, size_t nbytes,
startpage = offset / W25_PAGE_SIZE;
endpage = (offset + nbytes) / W25_PAGE_SIZE;
w25_lock(priv->spi);
if (startpage == endpage)
{
/* All bytes within one programmable page. Just do the write. */
@ -1198,6 +1217,7 @@ static ssize_t w25_write(FAR struct mtd_dev_s *dev, off_t offset, size_t nbytes,
}
}
w25_unlock(priv->spi);
return nbytes;
}
#endif /* defined(CONFIG_MTD_BYTE_WRITE) && !defined(CONFIG_W25_READONLY) */

Some files were not shown because too many files have changed in this diff Show more