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Misc updates to SAM3U register definition files for SAM4S compatibility

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This commit is contained in:
Gregory Nutt 2013-06-12 12:35:48 -06:00
parent fa45b86b4d
commit 535dc49dea
9 changed files with 602 additions and 306 deletions
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14
arch/arm/src/sam34/chip/sam_pwm.h
View file

@ -1,5 +1,6 @@
/****************************************************************************************
* arch/arm/src/sam34/chip/sam_pwm.h
* Pulse Width Modulation Controller (PWM) definitions for the SAM3U and SAM4S
*
* Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
@ -83,6 +84,9 @@
#define SAM_PWM_EL0MR_OFFSET 0x07c /* PWM Event Line 0 Mode Register */
#define SAM_PWM_EL1MR_OFFSET 0x080 /* PWM Event Line 1 Mode Register */
/* 0x084-0x0ac: Reserved */
#if defined(CONFIG_ARCH_CHIP_SAM4S)
# define SAM_PWM_SMMR_OFFSET 0x0b0 /* PWM Stepper Motor Mode Register */
#endif
/* 0x0b4-0x0e0: Reserved */
#define SAM_PWM_WPCR_OFFSET 0x0e4 /* PWM Write Protect Control Register */
#define SAM_PWM_WPSR_OFFSET 0x0e8 /* PWM Write Protect Status Register */
@ -215,6 +219,10 @@
#define SAM_PWM_FPE (SAM_PWM_BASE+SAM_PWM_FPE_OFFSET)
#define SAM_PWM_EL0MR (SAM_PWM_BASE+SAM_PWM_EL0MR_OFFSET)
#define SAM_PWM_EL1MR (SAM_PWM_BASE+SAM_PWM_EL1MR_OFFSET)
#if defined(CONFIG_ARCH_CHIP_SAM4S)
# define SAM_PWM_SMMR_OFFSET 0x0b0 /* PWM Stepper Motor Mode Register */
# define SAM_PWM_SMMR_OFFSET 0x0b0 /* PWM Stepper Motor Mode Register */
#endif
#define SAM_PWM_WPCR (SAM_PWM_BASE+SAM_PWM_WPCR_OFFSET)
#define SAM_PWM_WPSR (SAM_PWM_BASE+SAM_PWM_WPSR_OFFSET)
@ -518,6 +526,12 @@
#define PWM_ELMR_CSEL6 (1 << 6) /* Bit 6: Comparison 6 Selection */
#define PWM_ELMR_CSEL7 (1 << 7) /* Bit 7: Comparison 7 Selection */
/* PWM Stepper Motor Mode Register */
#if defined(CONFIG_ARCH_CHIP_SAM4S)
# warning SAM4S not yet integrated
#endif
/* PWM Write Protect Control Register */
#define PWM_WPCR_WPCMD_SHIFT (0) /* Bits 0-1: Write Protect Command */

3
arch/arm/src/sam34/chip/sam_rstc.h
View file

@ -1,5 +1,6 @@
/****************************************************************************************
* arch/arm/src/sam34/chip/sam_rstc.h
* Reset Controller (RSTC) definitions for the SAM3U and SAM4S
*
* Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
@ -68,6 +69,7 @@
#define RSTC_CR_EXTRST (1 << 3) /* Bit 3: External Reset */
#define RSTC_CR_KEY_SHIFT (24) /* Bits 24-31: Password */
#define RSTC_CR_KEY_MASK (0xff << RSTC_CR_KEY_SHIFT)
# define RSTC_CR_KEY (0xa5 << RSTC_CR_KEY_SHIFT)
#define RSTC_SR_URSTS (1 << 0) /* Bit 0: User Reset Status */
#define RSTC_SR_RSTTYP_SHIFT (8) /* Bits 8-10: Reset Type */
@ -86,6 +88,7 @@
#define RSTC_MR_ERSTL_MASK (15 << RSTC_MR_ERSTL_SHIFT)
#define RSTC_MR_KEY_SHIFT (24) /* Bits 24-31: Password */
#define RSTC_MR_KEY_MASK (0xff << RSTC_CR_KEY_SHIFT)
# define RSTC_MR_KEY (0xa5 << RSTC_CR_KEY_SHIFT)
/****************************************************************************************
* Public Types

87
arch/arm/src/sam34/chip/sam_rtc.h
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@ -1,5 +1,6 @@
/****************************************************************************************
* arch/arm/src/sam34/chip/sam_rtc.h
* Real-time Clock (RTC) definitions for the SAM3U and SAM4S
*
* Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
@ -81,6 +82,8 @@
/* RTC register bit definitions *********************************************************/
/* RTC Control Register */
#define RTC_CR_UPDTIM (1 << 0) /* Bit 0: Update Request Time Register */
#define RTC_CR_UPDCAL (1 << 1) /* Bit 1: Update Request Calendar Register */
#define RTC_CR_TIMEVSEL_SHIFT (8) /* Bits 8-9: Time Event Selection */
@ -95,8 +98,56 @@
# define RTC_CR_CALEVSEL_MONTH (1 << RTC_CR_CALEVSEL_SHIFT)
# define RTC_CR_CALEVSEL_YEAR (2 << RTC_CR_CALEVSEL_SHIFT)
/* RTC Mode Register */
#define RTC_MR_HRMOD (1 << 0) /* Bit 0: 12-/24-hour Mode */
#if defined(CONFIG_ARCH_CHIP_SAM4S)
# define RTC_MR_PERSIAN (1 << 1) /* Bit 1: PERSIAN Calendar */
# define RTC_MR_NEGPPM (1 << 4) /* Bit 4: Negative PPM Correction */
# define RTC_MR_CORRECTION_SHIFT (8) /* Bits 8-14: Slow Clock Correction */
# define RTC_MR_CORRECTION_
# define RTC_MR_HIGHPPM (1 << 15) /* Bit 15: HIGH PPM Correction */
# define RTC_MR_OUT0_SHIFT (16) /* Bits 16-18: RTCOUT0 Output Source Selection */
# define RTC_MR_OUT0_MASK (7 << RTC_MR_OUT0_SHIFT)
# define RTC_MR_OUT0_NOWAVE (0 << RTC_MR_OUT0_SHIFT) /* No waveform, stuck at 0 */
# define RTC_MR_OUT0_FREQ1HZ (1 << RTC_MR_OUT0_SHIFT) /* 1Hz square wave */
# define RTC_MR_OUT0_FREQ32HZ (2 << RTC_MR_OUT0_SHIFT) /* 32Hz square wave */
# define RTC_MR_OUT0_FREQ64HZ (3 << RTC_MR_OUT0_SHIFT) /* 64Hz square wave */
# define RTC_MR_OUT0_FREQ512HZ (4 << RTC_MR_OUT0_SHIFT) /* 512Hz square wave */
# define RTC_MR_OUT0_ALARM_TOGGLE (5 << RTC_MR_OUT0_SHIFT) /* Output toggles when alarm flag rises */
# define RTC_MR_OUT0_ALARM_FLAG (6 << RTC_MR_OUT0_SHIFT) /* Output is a copy of the alarm flag */
# define RTC_MR_OUT0_PROG_PULSE (7 << RTC_MR_OUT0_SHIFT) /* Duty cycle programmable pulse */
# define RTC_MR_OUT1_SHIFT (20) /* Bits 20-22: RTCOUT1 Output Source Selection */
# define RTC_MR_OUT1_MASK (7 << RTC_MR_OUT1_SHIFT)
# define RTC_MR_OUT1_NOWAVE (0 << RTC_MR_OUT1_SHIFT) /* No waveform, stuck at 0 */
# define RTC_MR_OUT1_FREQ1HZ (1 << RTC_MR_OUT1_SHIFT) /* 1Hz square wave */
# define RTC_MR_OUT1_FREQ32HZ (2 << RTC_MR_OUT1_SHIFT) /* 32Hz square wave */
# define RTC_MR_OUT1_FREQ64HZ (3 << RTC_MR_OUT1_SHIFT) /* 64Hz square wave */
# define RTC_MR_OUT1_FREQ512HZ (4 << RTC_MR_OUT1_SHIFT) /* 512Hz square wave */
# define RTC_MR_OUT1_ALARM_TOGGLE (5 << RTC_MR_OUT1_SHIFT) /* Output toggles when alarm flag rises */
# define RTC_MR_OUT1_ALARM_FLAG (6 << RTC_MR_OUT1_SHIFT) /* Output is a copy of the alarm flag */
# define RTC_MR_OUT1_PROG_PULSE (7 << RTC_MR_OUT1_SHIFT) /* Duty cycle programmable pulse */
# define RTC_MR_THIGH_SHIFT (24) /* Bits 24-26: High Duration of the Output Pulse */
# define RTC_MR_THIGH_MASK (7 << RTC_MR_THIGH_SHIFT)
# define RTC_MR_THIGH_ 31MS (0 << RTC_MR_THIGH_SHIFT) /* 31.2 ms */
# define RTC_MR_THIGH_ 16MS (1 << RTC_MR_THIGH_SHIFT) /* 15.6 ms */
# define RTC_MR_THIGH_ 4MS (2 << RTC_MR_THIGH_SHIFT) /* 3.91 ms */
# define RTC_MR_THIGH_ 976US (3 << RTC_MR_THIGH_SHIFT) /* 976 µs */
# define RTC_MR_THIGH_ 488US (4 << RTC_MR_THIGH_SHIFT) /* 488 µs */
# define RTC_MR_THIGH_ 22US (5 << RTC_MR_THIGH_SHIFT) /* 122 µs */
# define RTC_MR_THIGH_ 0US (6 << RTC_MR_THIGH_SHIFT) /* 30.5 µs */
# define RTC_MR_THIGH_ 15US (7 << RTC_MR_THIGH_SHIFT) /* 15.2 µs */
# define RTC_MR_TPERIOD_SHIFT (28) /* Bits 28-29: Period of the Output Pulse */
# define RTC_MR_TPERIOD_MASK (3 << RTC_MR_TPERIOD_SHIFT)
# define RTC_MR_TPERIOD_ 1S (0 << RTC_MR_TPERIOD_SHIFT) /* 1 second */
# define RTC_MR_TPERIOD_ 500MS (1 << RTC_MR_TPERIOD_SHIFT) /* 500 ms */
# define RTC_MR_TPERIOD_ 250MS (2 << RTC_MR_TPERIOD_SHIFT) /* 250 ms */
# define RTC_MR_TPERIOD_ 125MS (3 << RTC_MR_TPERIOD_SHIFT) /* 125 ms */
#endif
/* RTC Time Register */
#define RTC_TIMR_SEC_SHIFT (0) /* Bits 0-6: Current Second */
#define RTC_TIMR_SEC_MASK (0x7f << RTC_TIMR_SEC_SHIFT)
#define RTC_TIMR_MIN_SHIFT (8) /* Bits 8-14: Current Minute */
@ -105,6 +156,8 @@
#define RTC_TIMR_HOUR_MASK (0x3f << RTC_TIMR_HOUR_SHIFT)
#define RTC_TIMR_AMPM (1 << 22) /* Bit 22: Ante Meridiem Post Meridiem Indicator */
/* RTC Calendar Register */
#define RTC_CALR_CENT_SHIFT (0) /* Bits 0-6: Current Century */
#define RTC_CALR_CENT_MASK (0x7f << RTC_TIMR_HOUR_SHIFT)
#define RTC_CALR_YEAR_SHIFT (8) /* Bits 8-15: Current Year */
@ -116,6 +169,8 @@
#define RTC_CALR_DATE_SHIFT (24) /* Bits 24-29: Current Day in Current Month */
#define RTC_CALR_DATE_MASK (0x3f << RTC_CALR_DATE_SHIFT)
/* RTC Time Alarm Register */
#define RTC_TIMALR_SEC_SHIFT (0) /* Bits 0-6: Second Alarm */
#define RTC_TIMALR_SEC_MASK (0x7f << RTC_TIMALR_SEC_SHIFT)
#define RTC_TIMALR_SECEN (1 << 7) /* Bit 7: Second Alarm Enable */
@ -127,43 +182,73 @@
#define RTC_TIMALR_AMPM (1 << 22) /* Bit 22: AM/PM Indicator */
#define RTC_TIMALR_HOUREN (1 << 23) /* Bit 23: Hour Alarm Enable */
/* RTC Calendar Alarm Register */
#define RTC_CALALR_MONTH_SHIFT (16) /* Bits 16-20: Month Alarm */
#define RTC_CALALR_MONTH_MASK (0x1f << RTC_CALALR_MONTH_SHIFT)
#define RTC_CALALR_MTHEN (1 << 23) /* Bit 23: Month Alarm Enable */
#define RTC_CALALR_DATE_SHIFT (24) /* Bits 24-29: Date Alarm */
#define RTC_CALALR_DATE_MASK (0x3c << RTC_CALALR_DATE_SHIFT)
#define RTC_CALALR_DATE_MASK (0x3f << RTC_CALALR_DATE_SHIFT)
#define RTC_CALALR_DATEEN (1 << 31) /* Bit 31: Date Alarm Enable */
/* RTC Status Register */
#define RTC_SR_ACKUPD (1 << 0) /* Bit 0: Acknowledge for Update */
#define RTC_SR_ALARM (1 << 1) /* Bit 1: Alarm Flag */
#define RTC_SR_SEC (1 << 2) /* Bit 2: Second Event */
#define RTC_SR_TIMEV (1 << 3) /* Bit 3: Time Event */
#define RTC_SR_CALEV (1 << 4) /* Bit 4: Calendar Event */
#if defined(CONFIG_ARCH_CHIP_SAM4S)
# define RTC_SR_TDERR (1 << 5) /* Bit 5: Time and/or Date Free Running Error */
#endif
/* RTC Status Clear Command Register */
#define RTC_SCCR_ACKCLR (1 << 0) /* Bit 0: Acknowledge Clear */
#define RTC_SCCR_ALRCLR (1 << 1) /* Bit 1: Alarm Clear */
#define RTC_SCCR_SECCLR (1 << 2) /* Bit 2: Second Clear */
#define RTC_SCCR_TIMCLR (1 << 3) /* Bit 3: Time Clear */
#define RTC_SCCR_CALCLR (1 << 4) /* Bit 4: Calendar Clear */
#if defined(CONFIG_ARCH_CHIP_SAM4S)
# define RTC_SR_TDERRCLR (1 << 5) /* Bit 5: Time and/or Date Free Running Error Clear */
#endif
/* RTC Interrupt Enable Register */
#define RTC_IER_ACKEN (1 << 0) /* Bit 0: Acknowledge Update Interrupt Enable */
#define RTC_IER_ALREN (1 << 1) /* Bit 1: Alarm Interrupt Enable */
#define RTC_IER_SECEN (1 << 2) /* Bit 2: Second Event Interrupt Enable */
#define RTC_IER_TIMEN (1 << 3) /* Bit 3: Time Event Interrupt Enable */
#define RTC_IER_CALEN (1 << 4) /* Bit 4: Calendar Event Interrupt Enable */
#if defined(CONFIG_ARCH_CHIP_SAM4S)
# define RTC_SR_TDERREN (1 << 5) /* Bit 5: Time and/or Date Error Interrupt Enable */
#endif
/* RTC Interrupt Disable Register */
#define RTC_IDR_ACKDIS (1 << 0) /* Bit 0: Acknowledge Update Interrupt Disable */
#define RTC_IDR_ALRDIS (1 << 1) /* Bit 1: Alarm Interrupt Disable */
#define RTC_IDR_SECDIS (1 << 2) /* Bit 2: Second Event Interrupt Disable */
#define RTC_IDR_TIMDIS (1 << 3) /* Bit 3: Time Event Interrupt Disable */
#define RTC_IDR_CALDIS (1 << 4) /* Bit 4: Calendar Event Interrupt Disable */
#if defined(CONFIG_ARCH_CHIP_SAM4S)
# define RTC_SR_TDERRDIS (1 << 5) /* Bit 5: Time and/or Date Error Interrupt Disable */
#endif
/* RTC Interrupt Mask Register */
#define RTC_IMR_ACK (1 << 0) /* Bit 0: Acknowledge Update Interrupt Mask */
#define RTC_IMR_ALR (1 << 1) /* Bit 1: Alarm Interrupt Mask */
#define RTC_IMR_SEC (1 << 2) /* Bit 2: Second Event Interrupt Mask */
#define RTC_IMR_TIM (1 << 3) /* Bit 3: Time Event Interrupt Mask */
#define RTC_IMR_CAL (1 << 4) /* Bit 4: Calendar Event Interrupt Mask */
/* RTC Valid Entry Register */
#define RTC_VER_NVTIM (1 << 0) /* Bit 0: Non-valid Time */
#define RTC_VER_NVCAL (1 << 1) /* Bit 1: Non-valid Calendar */
#define RTC_VER_NVTIMALR (1 << 2) /* Bit 2: Non-valid Time Alarm */

13
arch/arm/src/sam34/chip/sam_rtt.h
View file

@ -1,5 +1,6 @@
/****************************************************************************************
* arch/arm/src/sam34/chip/sam_rtt.h
* Real-time Timer (RTT) definitions for the SAM3U and SAM4S
*
* Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
@ -65,12 +66,24 @@
/* RTT register bit definitions ********************************************************/
/* Real-time Timer Mode Register */
#define RTT_MR_RTPRES_SHIFT (0) /* Bits 0-15: Real-time Timer Prescaler Value */
#define RTT_MR_RTPRES__MASK (0xffff << RTT_MR_RTPRES_SHIFT)
#define RTT_MR_ALMIEN (1 << 16) /* Bit 16: Alarm Interrupt Enable */
#define RTT_MR_RTTINCIEN (1 << 17) /* Bit 17: Real-time Timer Increment Int Enable */
#define RTT_MR_RTTRST (1 << 18) /* Bit 18: Real-time Timer Restart */
#if defined(CONFIG_ARCH_CHIP_SAM4S)
# define RTT_MR_RTTDIS (1 << 20) /* Bit 20: Real-time Timer Disable */
# define RTT_MR_RTC1HZ (1 << 24) /* Bit 24: Real-Time Clock 1Hz Clock Selection */
#endif
/* Real-time Timer Alarm Register (32-bit alarm value) */
/* Real-time Timer Value Register (32-bit timer value) */
/* Real-time Timer Status Register */
#define RTT_SR_ALMS (1 << 0) /* Bit 0: Real-time Alarm Status */
#define RTT_SR_RTTINC (1 << 1) /* Bit 1: Real-time Timer Increment */

647
arch/arm/src/sam34/chip/sam_smc.h
View file

@ -1,5 +1,6 @@
/****************************************************************************************
* arch/arm/src/sam34/chip/sam_smc.h
* Static Memory Controller (SMC) definitions for the SAM3U and SAM4S
*
* Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
@ -51,369 +52,437 @@
/* SMC register offsets *****************************************************************/
#define SAM_SMC_CFG_OFFSET 0x000 /* SMC NFC Configuration Register */
#define SAM_SMC_CTRL_OFFSET 0x004 /* SMC NFC Control Register */
#define SAM_SMC_SR_OFFSET 0x008 /* SMC NFC Status Register */
#define SAM_SMC_IER_OFFSET 0x00c /* SMC NFC Interrupt Enable Register */
#define SAM_SMC_IDR_OFFSET 0x010 /* SMC NFC Interrupt Disable Register */
#define SAM_SMC_IMR_OFFSET 0x014 /* SMC NFC Interrupt Mask Register */
#define SAM_SMC_ADDR_OFFSET 0x018 /* SMC NFC Address Cycle Zero Register */
#define SAM_SMC_BANK_OFFSET 0x01c /* SMC Bank Address Register */
#define SAM_SMC_ECCCTRL_OFFSET 0x020 /* SMC ECC Control Register */
#define SAM_SMC_ECCMD_OFFSET 0x024 /* SMC ECC Mode Register */
#define SAM_SMC_ECCSR1_OFFSET 0x028 /* SMC ECC Status 1 Register */
#define SAM_SMC_ECCPR0_OFFSET 0x02c /* SMC ECC parity 0 Register */
#define SAM_SMC_ECCPR1_OFFSET 0x030 /* SMC ECC parity 1 Register */
#define SAM_SMC_ECCSR2_OFFSET 0x034 /* SMC ECC status 2 Register */
#define SAM_SMC_ECCPR2_OFFSET 0x038 /* SMC ECC parity 2 Register */
#define SAM_SMC_ECCPR3_OFFSET 0x03c /* SMC ECC parity 3 Register */
#define SAM_SMC_ECCPR4_OFFSET 0x040 /* SMC ECC parity 4 Register */
#define SAM_SMC_ECCPR5_OFFSET 0x044 /* SMC ECC parity 5 Register */
#define SAM_SMC_ECCPR6_OFFSET 0x048 /* SMC ECC parity 6 Register */
#define SAM_SMC_ECCPR7_OFFSET 0x04c /* SMC ECC parity 7 Register */
#define SAM_SMC_ECCPR8_OFFSET 0x050 /* SMC ECC parity 8 Register */
#define SAM_SMC_ECCPR9_OFFSET 0x054 /* SMC ECC parity 9 Register */
#define SAM_SMC_ECCPR10_OFFSET 0x058 /* SMC ECC parity 10 Register */
#define SAM_SMC_ECCPR11_OFFSET 0x05c /* SMC ECC parity 11 Register */
#define SAM_SMC_ECCPR12_OFFSET 0x060 /* SMC ECC parity 12 Register */
#define SAM_SMC_ECCPR13_OFFSET 0x064 /* SMC ECC parity 13 Register */
#define SAM_SMC_ECCPR14_OFFSET 0x068 /* SMC ECC parity 14 Register */
#define SAM_SMC_ECCPR15_OFFSET 0x06c /* SMC ECC parity 15 Register */
#if defined(CONFIG_ARCH_CHIP_SAM3U)
# define SAM_SMC_CFG_OFFSET 0x0000 /* SMC NFC Configuration Register */
# define SAM_SMC_CTRL_OFFSET 0x0004 /* SMC NFC Control Register */
# define SAM_SMC_SR_OFFSET 0x0008 /* SMC NFC Status Register */
# define SAM_SMC_IER_OFFSET 0x000c /* SMC NFC Interrupt Enable Register */
# define SAM_SMC_IDR_OFFSET 0x0010 /* SMC NFC Interrupt Disable Register */
# define SAM_SMC_IMR_OFFSET 0x0014 /* SMC NFC Interrupt Mask Register */
# define SAM_SMC_ADDR_OFFSET 0x0018 /* SMC NFC Address Cycle Zero Register */
# define SAM_SMC_BANK_OFFSET 0x001c /* SMC Bank Address Register */
# define SAM_SMC_ECCCTRL_OFFSET 0x0020 /* SMC ECC Control Register */
# define SAM_SMC_ECCMD_OFFSET 0x0024 /* SMC ECC Mode Register */
# define SAM_SMC_ECCSR1_OFFSET 0x0028 /* SMC ECC Status 1 Register */
# define SAM_SMC_ECCPR0_OFFSET 0x002c /* SMC ECC parity 0 Register */
# define SAM_SMC_ECCPR1_OFFSET 0x0030 /* SMC ECC parity 1 Register */
# define SAM_SMC_ECCSR2_OFFSET 0x0034 /* SMC ECC status 2 Register */
# define SAM_SMC_ECCPR2_OFFSET 0x0038 /* SMC ECC parity 2 Register */
# define SAM_SMC_ECCPR3_OFFSET 0x003c /* SMC ECC parity 3 Register */
# define SAM_SMC_ECCPR4_OFFSET 0x0040 /* SMC ECC parity 4 Register */
# define SAM_SMC_ECCPR5_OFFSET 0x0044 /* SMC ECC parity 5 Register */
# define SAM_SMC_ECCPR6_OFFSET 0x0048 /* SMC ECC parity 6 Register */
# define SAM_SMC_ECCPR7_OFFSET 0x004c /* SMC ECC parity 7 Register */
# define SAM_SMC_ECCPR8_OFFSET 0x0050 /* SMC ECC parity 8 Register */
# define SAM_SMC_ECCPR9_OFFSET 0x0054 /* SMC ECC parity 9 Register */
# define SAM_SMC_ECCPR10_OFFSET 0x0058 /* SMC ECC parity 10 Register */
# define SAM_SMC_ECCPR11_OFFSET 0x005c /* SMC ECC parity 11 Register */
# define SAM_SMC_ECCPR12_OFFSET 0x0060 /* SMC ECC parity 12 Register */
# define SAM_SMC_ECCPR13_OFFSET 0x0064 /* SMC ECC parity 13 Register */
# define SAM_SMC_ECCPR14_OFFSET 0x0068 /* SMC ECC parity 14 Register */
# define SAM_SMC_ECCPR15_OFFSET 0x006c /* SMC ECC parity 15 Register */
#define SAM_SMCCS_OFFSET(n) (0x070+((n)*0x014))
#define SAM_SMCCS_SETUP_OFFSET 0x000 /* SMC SETUP Register */
#define SAM_SMCCS_PULSE_OFFSET 0x004 /* SMC PULSE Register */
#define SAM_SMCCS_CYCLE_OFFSET 0x008 /* SMC CYCLE Register */
#define SAM_SMCCS_TIMINGS_OFFSET 0x00c /* SMC TIMINGS Register */
#define SAM_SMCCS_MODE_OFFSET 0x010 /* SMC MODE Register */
# define SAM_SMCCS_OFFSET(n) (0x0070+((n)*0x014))
# define SAM_SMCCS_SETUP_OFFSET 0x0000 /* SMC Setup register */
# define SAM_SMCCS_PULSE_OFFSET 0x0004 /* SMC Pulse Register */
# define SAM_SMCCS_CYCLE_OFFSET 0x0008 /* SMC Cycle Register */
# define SAM_SMCCS_TIMINGS_OFFSET 0x000c /* SMC Timings Register */
# define SAM_SMCCS_MODE_OFFSET 0x0010 /* SMC Mode Register */
#define SAM_SMC_OCMS_OFFSET 0x110 /* SMC OCMS MODE Register */
#define SAM_SMC_KEY1_OFFSET 0x114 /* SMC KEY1 Register */
#define SAM_SMC_KEY2_OFFSET 0x118 /* SMC KEY2 Register */
#define SAM_SMC_WPCR_OFFSET 0x1e4 /* Write Protection Control Register */
#define SAM_SMC_WPSR_OFFSET 0x1e8 /* Write Protection Status Register */
# define SAM_SMC_OCMS_OFFSET 0x0110 /* SMC OCMS Mode Register */
# define SAM_SMC_KEY1_OFFSET 0x0114 /* SMC KEY1 Register */
# define SAM_SMC_KEY2_OFFSET 0x0118 /* SMC KEY2 Register */
# define SAM_SMC_WPCR_OFFSET 0x01e4 /* Write Protection Control Register */
# define SAM_SMC_WPSR_OFFSET 0x01e8 /* Write Protection Status Register */
#elif defined(CONFIG_ARCH_CHIP_SAM4S)
# define SAM_SMCCS_OFFSET(n) ((n) << 4)
# define SAM_SMCCS_SETUP_OFFSET 0x0000 /* SMC Setup Register */
# define SAM_SMCCS_PULSE_OFFSET 0x0004 /* SMC Pulse Register */
# define SAM_SMCCS_CYCLE_OFFSET 0x0008 /* SMC Cycle Register */
# define SAM_SMCCS_MODE_OFFSET 0x000c /* SMC Mode Register */
# define SAM_SMC_OCMS_OFFSET 0x0080 /* SMC OCMS Mode Register */
# define SAM_SMC_KEY1_OFFSET 0x0084 /* SMC KEY1 Register */
# define SAM_SMC_KEY2_OFFSET 0x0088 /* SMC KEY2 Register */
# define SAM_SMC_WPCR_OFFSET 0x00e4 /* Write Protection Control Register */
# define SAM_SMC_WPSR_OFFSET 0x00e8 /* Write Protection Status Register */
#else
# error Unrecognized SAM architecture
#endif
/* SMC register adresses ****************************************************************/
#define SAM_SMC_CFG (SAM_SMC_BASE+SAM_SMC_CFG_OFFSET)
#define SAM_SMC_CTRL (SAM_SMC_BASE+SAM_SMC_CTRL_OFFSET)
#define SAM_SMC_SR (SAM_SMC_BASE+SAM_SMC_SR_OFFSET)
#define SAM_SMC_IER (SAM_SMC_BASE+SAM_SMC_IER_OFFSET)
#define SAM_SMC_IDR (SAM_SMC_BASE+SAM_SMC_IDR_OFFSET)
#define SAM_SMC_IMR (SAM_SMC_BASE+SAM_SMC_IMR_OFFSET)
#define SAM_SMC_ADDR (SAM_SMC_BASE+SAM_SMC_ADDR_OFFSET)
#define SAM_SMC_BANK (SAM_SMC_BASE+SAM_SMC_BANK_OFFSET)
#define SAM_SMC_ECCCTRL (SAM_SMC_BASE+SAM_SMC_ECCCTRL_OFFSET)
#define SAM_SMC_ECCMD (SAM_SMC_BASE+SAM_SMC_ECCMD_OFFSET)
#define SAM_SMC_ECCSR1 (SAM_SMC_BASE+SAM_SMC_ECCSR1_OFFSET)
#define SAM_SMC_ECCPR0 (SAM_SMC_BASE+SAM_SMC_ECCPR0_OFFSET)
#define SAM_SMC_ECCPR1 (SAM_SMC_BASE+SAM_SMC_ECCPR1_OFFSET)
#define SAM_SMC_ECCSR2 (SAM_SMC_BASE+SAM_SMC_ECCSR2_OFFSET)
#define SAM_SMC_ECCPR2 (SAM_SMC_BASE+SAM_SMC_ECCPR2_OFFSET)
#define SAM_SMC_ECCPR3 (SAM_SMC_BASE+SAM_SMC_ECCPR3_OFFSET)
#define SAM_SMC_ECCPR4 (SAM_SMC_BASE+SAM_SMC_ECCPR4_OFFSET)
#define SAM_SMC_ECCPR5 (SAM_SMC_BASE+SAM_SMC_ECCPR5_OFFSET)
#define SAM_SMC_ECCPR6 (SAM_SMC_BASE+SAM_SMC_ECCPR6_OFFSET)
#define SAM_SMC_ECCPR7 (SAM_SMC_BASE+SAM_SMC_ECCPR7_OFFSET)
#define SAM_SMC_ECCPR8 (SAM_SMC_BASE+SAM_SMC_ECCPR8_OFFSET)
#define SAM_SMC_ECCPR9 (SAM_SMC_BASE+SAM_SMC_ECCPR9_OFFSET)
#define SAM_SMC_ECCPR10 (SAM_SMC_BASE+SAM_SMC_ECCPR10_OFFSET)
#define SAM_SMC_ECCPR11 (SAM_SMC_BASE+SAM_SMC_ECCPR11_OFFSET)
#define SAM_SMC_ECCPR12 (SAM_SMC_BASE+SAM_SMC_ECCPR12_OFFSET)
#define SAM_SMC_ECCPR13 (SAM_SMC_BASE+SAM_SMC_ECCPR13_OFFSET)
#define SAM_SMC_ECCPR14 (SAM_SMC_BASE+SAM_SMC_ECCPR14_OFFSET)
#define SAM_SMC_ECCPR15 (SAM_SMC_BASE+SAM_SMC_ECCPR15_OFFSET)
#if defined(CONFIG_ARCH_CHIP_SAM3U)
# define SAM_SMC_CFG (SAM_SMC_BASE+SAM_SMC_CFG_OFFSET)
# define SAM_SMC_CTRL (SAM_SMC_BASE+SAM_SMC_CTRL_OFFSET)
# define SAM_SMC_SR (SAM_SMC_BASE+SAM_SMC_SR_OFFSET)
# define SAM_SMC_IER (SAM_SMC_BASE+SAM_SMC_IER_OFFSET)
# define SAM_SMC_IDR (SAM_SMC_BASE+SAM_SMC_IDR_OFFSET)
# define SAM_SMC_IMR (SAM_SMC_BASE+SAM_SMC_IMR_OFFSET)
# define SAM_SMC_ADDR (SAM_SMC_BASE+SAM_SMC_ADDR_OFFSET)
# define SAM_SMC_BANK (SAM_SMC_BASE+SAM_SMC_BANK_OFFSET)
# define SAM_SMC_ECCCTRL (SAM_SMC_BASE+SAM_SMC_ECCCTRL_OFFSET)
# define SAM_SMC_ECCMD (SAM_SMC_BASE+SAM_SMC_ECCMD_OFFSET)
# define SAM_SMC_ECCSR1 (SAM_SMC_BASE+SAM_SMC_ECCSR1_OFFSET)
# define SAM_SMC_ECCPR0 (SAM_SMC_BASE+SAM_SMC_ECCPR0_OFFSET)
# define SAM_SMC_ECCPR1 (SAM_SMC_BASE+SAM_SMC_ECCPR1_OFFSET)
# define SAM_SMC_ECCSR2 (SAM_SMC_BASE+SAM_SMC_ECCSR2_OFFSET)
# define SAM_SMC_ECCPR2 (SAM_SMC_BASE+SAM_SMC_ECCPR2_OFFSET)
# define SAM_SMC_ECCPR3 (SAM_SMC_BASE+SAM_SMC_ECCPR3_OFFSET)
# define SAM_SMC_ECCPR4 (SAM_SMC_BASE+SAM_SMC_ECCPR4_OFFSET)
# define SAM_SMC_ECCPR5 (SAM_SMC_BASE+SAM_SMC_ECCPR5_OFFSET)
# define SAM_SMC_ECCPR6 (SAM_SMC_BASE+SAM_SMC_ECCPR6_OFFSET)
# define SAM_SMC_ECCPR7 (SAM_SMC_BASE+SAM_SMC_ECCPR7_OFFSET)
# define SAM_SMC_ECCPR8 (SAM_SMC_BASE+SAM_SMC_ECCPR8_OFFSET)
# define SAM_SMC_ECCPR9 (SAM_SMC_BASE+SAM_SMC_ECCPR9_OFFSET)
# define SAM_SMC_ECCPR10 (SAM_SMC_BASE+SAM_SMC_ECCPR10_OFFSET)
# define SAM_SMC_ECCPR11 (SAM_SMC_BASE+SAM_SMC_ECCPR11_OFFSET)
# define SAM_SMC_ECCPR12 (SAM_SMC_BASE+SAM_SMC_ECCPR12_OFFSET)
# define SAM_SMC_ECCPR13 (SAM_SMC_BASE+SAM_SMC_ECCPR13_OFFSET)
# define SAM_SMC_ECCPR14 (SAM_SMC_BASE+SAM_SMC_ECCPR14_OFFSET)
# define SAM_SMC_ECCPR15 (SAM_SMC_BASE+SAM_SMC_ECCPR15_OFFSET)
#endif
#define SAM_SMCCS_BASE(n) (SAM_SMC_BASE+SAM_SMCCS_OFFSET(n))
# define SAM_SMC_CS0_BASE (SAM_SMC_BASE+SAM_SMCCS_OFFSET(0))
# define SAM_SMC_CS1_BASE (SAM_SMC_BASE+SAM_SMCCS_OFFSET(1))
# define SAM_SMC_CS2_BASE (SAM_SMC_BASE+SAM_SMCCS_OFFSET(2))
# define SAM_SMC_CS3_BASE (SAM_SMC_BASE+SAM_SMCCS_OFFSET(3))
#define SAM_SMCCS_SETUP(n) (SAM_SMCCS_BASE(n)+SAM_SMCCS_SETUP_OFFSET)
#define SAM_SMCCS_PULSE(n) (SAM_SMCCS_BASE(n)+SAM_SMCCS_PULSE_OFFSET)
#define SAM_SMCCS_CYCLE(n) (SAM_SMCCS_BASE(n)+SAM_SMCCS_CYCLE_OFFSET)
#define SAM_SMCCS_TIMINGS(n) (SAM_SMCCS_BASE(n)+SAM_SMCCS_TIMINGS_OFFSET)
#define SAM_SMCCS_MODE(n) (SAM_SMCCS_BASE(n)+SAM_SMCCS_MODE_OFFSET)
#define SAM_SMCCS_BASE(n) (SAM_SMC_BASE+SAM_SMCCS_OFFSET(n))
# define SAM_SMC_CS0_BASE (SAM_SMC_BASE+SAM_SMCCS_OFFSET(0))
# define SAM_SMC_CS1_BASE (SAM_SMC_BASE+SAM_SMCCS_OFFSET(1))
# define SAM_SMC_CS2_BASE (SAM_SMC_BASE+SAM_SMCCS_OFFSET(2))
# define SAM_SMC_CS3_BASE (SAM_SMC_BASE+SAM_SMCCS_OFFSET(3))
#define SAM_SMCCS_SETUP(n) (SAM_SMCCS_BASE(n)+SAM_SMCCS_SETUP_OFFSET)
#define SAM_SMCCS_PULSE(n) (SAM_SMCCS_BASE(n)+SAM_SMCCS_PULSE_OFFSET)
#define SAM_SMCCS_CYCLE(n) (SAM_SMCCS_BASE(n)+SAM_SMCCS_CYCLE_OFFSET)
#if defined(CONFIG_ARCH_CHIP_SAM3U)
# define SAM_SMCCS_TIMINGS(n) (SAM_SMCCS_BASE(n)+SAM_SMCCS_TIMINGS_OFFSET)
#enmdif
#define SAM_SMCCS_MODE(n) (SAM_SMCCS_BASE(n)+SAM_SMCCS_MODE_OFFSET)
#define SAM_SMC_OCMS (SAM_SMC_BASE+SAM_SMC_OCMS_OFFSET)
#define SAM_SMC_KEY1 (SAM_SMC_BASE+SAM_SMC_KEY1_OFFSET)
#define SAM_SMC_KEY2 (SAM_SMC_BASE+SAM_SMC_KEY2_OFFSET)
#define SAM_SMC_WPCR (SAM_SMC_BASE+SAM_SMC_WPCR_OFFSET)
#define SAM_SMC_WPSR (SAM_SMC_BASE+SAM_SMC_WPSR_OFFSET)
#define SAM_SMC_OCMS (SAM_SMC_BASE+SAM_SMC_OCMS_OFFSET)
#define SAM_SMC_KEY1 (SAM_SMC_BASE+SAM_SMC_KEY1_OFFSET)
#define SAM_SMC_KEY2 (SAM_SMC_BASE+SAM_SMC_KEY2_OFFSET)
#define SAM_SMC_WPCR (SAM_SMC_BASE+SAM_SMC_WPCR_OFFSET)
#define SAM_SMC_WPSR (SAM_SMC_BASE+SAM_SMC_WPSR_OFFSET)
/* SMC register bit definitions *********************************************************/
/* SMC NFC Configuration Register */
#define SMC_CFG_PAGESIZE_SHIFT (0) /* Bits 0-1: Page size of NAND Flash device */
#define SMC_CFG_PAGESIZE_MASK (3 << SMC_CFG_PAGESIZE_SHIFT)
# define SMC_CFG_PAGESIZE_16 BYTES (0 << SMC_CFG_PAGESIZE_SHIFT) /* 528 Bytes 16 byte */
# define SMC_CFG_PAGESIZE_ 2 BYTES (1 << SMC_CFG_PAGESIZE_SHIFT) /* 1056 Bytes 32 bytes */
# define SMC_CFG_PAGESIZE_64 BYTES (2 << SMC_CFG_PAGESIZE_SHIFT) /* 2112 Bytes 64 bytes */
# define SMC_CFG_PAGESIZE_128 BYTES (3 << SMC_CFG_PAGESIZE_SHIFT) /* 4224 Bytes 128 bytes */
#define SMC_CFG_WSPARE (1 << 8) /* Bit 8: Write Spare Area */
#define SMC_CFG_RSPARE (1 << 9) /* Bit 9: Read Spare Area */
#define SMC_CFG_EDGECTRL (1 << 12) /* Bit 12: Rising/Falling Edge Detection Control */
#define SMC_CFG_RBEDGE (1 << 13) /* Bit 13: Ready/Busy Signal Edge Detection */
#define SMC_CFG_DTOCYC_SHIFT (16) /* Bits 16-19: Data Timeout Cycle Number */
#define SMC_CFG_DTOCYC_MASK (15 << SMC_CFG_DTOCYC_SHIFT)
#define SMC_CFG_DTOMUL_SHIFT (20) /* Bits 20-22: Data Timeout Multiplier */
#define SMC_CFG_DTOMUL_MASK (7 << SMC_CFG_DTOMUL_SHIFT)
# define SMC_CFG_DTOMUL_1 (0 << SMC_CFG_DTOMUL_SHIFT)
# define SMC_CFG_DTOMUL_16 (1 << SMC_CFG_DTOMUL_SHIFT)
# define SMC_CFG_DTOMUL_128 (2 << SMC_CFG_DTOMUL_SHIFT)
# define SMC_CFG_DTOMUL_256 (3 << SMC_CFG_DTOMUL_SHIFT)
# define SMC_CFG_DTOMUL_1024 (4 << SMC_CFG_DTOMUL_SHIFT)
# define SMC_CFG_DTOMUL_4096 (5 << SMC_CFG_DTOMUL_SHIFT)
# define SMC_CFG_DTOMUL_65536 (6 << SMC_CFG_DTOMUL_SHIFT)
# define SMC_CFG_DTOMUL_1048576 (7 << SMC_CFG_DTOMUL_SHIFT)
#if defined(CONFIG_ARCH_CHIP_SAM3U)
# define SMC_CFG_PAGESIZE_SHIFT (0) /* Bits 0-1: Page size of NAND Flash device */
# define SMC_CFG_PAGESIZE_MASK (3 << SMC_CFG_PAGESIZE_SHIFT)
# define SMC_CFG_PAGESIZE_16 BYTES (0 << SMC_CFG_PAGESIZE_SHIFT) /* 528 Bytes 16 byte */
# define SMC_CFG_PAGESIZE_ 2 BYTES (1 << SMC_CFG_PAGESIZE_SHIFT) /* 1056 Bytes 32 bytes */
# define SMC_CFG_PAGESIZE_64 BYTES (2 << SMC_CFG_PAGESIZE_SHIFT) /* 2112 Bytes 64 bytes */
# define SMC_CFG_PAGESIZE_128 BYTES (3 << SMC_CFG_PAGESIZE_SHIFT) /* 4224 Bytes 128 bytes */
# define SMC_CFG_WSPARE (1 << 8) /* Bit 8: Write Spare Area */
# define SMC_CFG_RSPARE (1 << 9) /* Bit 9: Read Spare Area */
# define SMC_CFG_EDGECTRL (1 << 12) /* Bit 12: Rising/Falling Edge Detection Control */
# define SMC_CFG_RBEDGE (1 << 13) /* Bit 13: Ready/Busy Signal Edge Detection */
# define SMC_CFG_DTOCYC_SHIFT (16) /* Bits 16-19: Data Timeout Cycle Number */
# define SMC_CFG_DTOCYC_MASK (15 << SMC_CFG_DTOCYC_SHIFT)
# define SMC_CFG_DTOMUL_SHIFT (20) /* Bits 20-22: Data Timeout Multiplier */
# define SMC_CFG_DTOMUL_MASK (7 << SMC_CFG_DTOMUL_SHIFT)
# define SMC_CFG_DTOMUL_1 (0 << SMC_CFG_DTOMUL_SHIFT)
# define SMC_CFG_DTOMUL_16 (1 << SMC_CFG_DTOMUL_SHIFT)
# define SMC_CFG_DTOMUL_128 (2 << SMC_CFG_DTOMUL_SHIFT)
# define SMC_CFG_DTOMUL_256 (3 << SMC_CFG_DTOMUL_SHIFT)
# define SMC_CFG_DTOMUL_1024 (4 << SMC_CFG_DTOMUL_SHIFT)
# define SMC_CFG_DTOMUL_4096 (5 << SMC_CFG_DTOMUL_SHIFT)
# define SMC_CFG_DTOMUL_65536 (6 << SMC_CFG_DTOMUL_SHIFT)
# define SMC_CFG_DTOMUL_1048576 (7 << SMC_CFG_DTOMUL_SHIFT)
#endif
/* SMC NFC Control Register */
#define SMC_CTRL_NFCEN (1 << 0) /* Bit 0: NAND Flash Controller Enable */
#define SMC_CTRL_NFCDIS (1 << 1) /* Bit 1: NAND Flash Controller Disable */
#if defined(CONFIG_ARCH_CHIP_SAM3U)
# define SMC_CTRL_NFCEN (1 << 0) /* Bit 0: NAND Flash Controller Enable */
# define SMC_CTRL_NFCDIS (1 << 1) /* Bit 1: NAND Flash Controller Disable */
#endif
/* SMC NFC Status Register, SMC NFC Interrupt Enable Register, SMC NFC Interrupt
* Disable Register, and SMC NFC Interrupt Mask Register common bit-field definitions
*/
#define SMC_SR_SMCSTS (1 << 0) /* Bit 0: NAND Flash Controller status (SR only) */
#define SMC_INT_RBRISE (1 << 4) /* Bit 4: Ready Busy Rising Edge Detection Interrupt */
#define SMC_INT_RBFALL (1 << 5) /* Bit 5: Ready Busy Falling Edge Detection Interrupt */
#define SMC_SR_NFCBUSY (1 << 8) /* Bit 8: NFC Busy (SR only) */
#define SMC_SR_NFCWR (1 << 11) /* Bit 11: NFC Write/Read Operation (SR only) */
#define SMC_SR_NFCSID (1 << 12) /* Bit 13: NFC Chip Select ID (SR only) */
#define SMC_INT_XFRDONE (1 << 16) /* Bit 16: Transfer Done Interrupt */
#define SMC_INT_CMDDONE (1 << 17) /* Bit 17: Command Done Interrupt */
#define SMC_INT_DTOE (1 << 20) /* Bit 20: Data Timeout Error Interrupt */
#define SMC_INT_UNDEF (1 << 21) /* Bit 21: Undefined Area Access Interrupt */
#define SMC_INT_AWB (1 << 22) /* Bit 22: Accessing While Busy Interrupt */
#define SMC_INT_NFCASE (1 << 23) /* Bit 23: NFC Access Size Error Interrupt */
#define SMC_INT_RBEDGE(n) (1<<((n)+24))
#define SMC_INT_RB_EDGE0 (1 << 24) /* Bit 24: Ready/Busy Line 0 Interrupt */
#define SMC_INT_RB_EDGE1 (1 << 25) /* Bit 25: Ready/Busy Line 1 Interrupt */
#define SMC_INT_RB_EDGE2 (1 << 26) /* Bit 26: Ready/Busy Line 2 Interrupt */
#define SMC_INT_RB_EDGE3 (1 << 27) /* Bit 27: Ready/Busy Line 3 Interrupt */
#define SMC_INT_RB_EDGE4 (1 << 28) /* Bit 28: Ready/Busy Line 4 Interrupt */
#define SMC_INT_RB_EDGE5 (1 << 29) /* Bit 29: Ready/Busy Line 5 Interrupt */
#define SMC_INT_RB_EDGE6 (1 << 30) /* Bit 30: Ready/Busy Line 6 Interrupt */
#define SMC_INT_RB_EDGE7 (1 << 31) /* Bit 31: Ready/Busy Line 7 Interrupt */
#if defined(CONFIG_ARCH_CHIP_SAM3U)
# define SMC_SR_SMCSTS (1 << 0) /* Bit 0: NAND Flash Controller status (SR only) */
# define SMC_INT_RBRISE (1 << 4) /* Bit 4: Ready Busy Rising Edge Detection Interrupt */
# define SMC_INT_RBFALL (1 << 5) /* Bit 5: Ready Busy Falling Edge Detection Interrupt */
# define SMC_SR_NFCBUSY (1 << 8) /* Bit 8: NFC Busy (SR only) */
# define SMC_SR_NFCWR (1 << 11) /* Bit 11: NFC Write/Read Operation (SR only) */
# define SMC_SR_NFCSID (1 << 12) /* Bit 13: NFC Chip Select ID (SR only) */
# define SMC_INT_XFRDONE (1 << 16) /* Bit 16: Transfer Done Interrupt */
# define SMC_INT_CMDDONE (1 << 17) /* Bit 17: Command Done Interrupt */
# define SMC_INT_DTOE (1 << 20) /* Bit 20: Data Timeout Error Interrupt */
# define SMC_INT_UNDEF (1 << 21) /* Bit 21: Undefined Area Access Interrupt */
# define SMC_INT_AWB (1 << 22) /* Bit 22: Accessing While Busy Interrupt */
# define SMC_INT_NFCASE (1 << 23) /* Bit 23: NFC Access Size Error Interrupt */
# define SMC_INT_RBEDGE(n) (1<<((n)+24))
# define SMC_INT_RB_EDGE0 (1 << 24) /* Bit 24: Ready/Busy Line 0 Interrupt */
# define SMC_INT_RB_EDGE1 (1 << 25) /* Bit 25: Ready/Busy Line 1 Interrupt */
# define SMC_INT_RB_EDGE2 (1 << 26) /* Bit 26: Ready/Busy Line 2 Interrupt */
# define SMC_INT_RB_EDGE3 (1 << 27) /* Bit 27: Ready/Busy Line 3 Interrupt */
# define SMC_INT_RB_EDGE4 (1 << 28) /* Bit 28: Ready/Busy Line 4 Interrupt */
# define SMC_INT_RB_EDGE5 (1 << 29) /* Bit 29: Ready/Busy Line 5 Interrupt */
# define SMC_INT_RB_EDGE6 (1 << 30) /* Bit 30: Ready/Busy Line 6 Interrupt */
# define SMC_INT_RB_EDGE7 (1 << 31) /* Bit 31: Ready/Busy Line 7 Interrupt */
#endif
/* SMC NFC Address Cycle Zero Register */
#define SMC_ADDR_ADDR_CYCLE0_SHIFT (3) /* Bits 0-7: NAND Flash Array Address cycle 0 */
#define SMC_ADDR_ADDR_CYCLE0_SHIFT (3) /* Bits 0-7: NAND Flash Array Address cycle 0 */
#if defined(CONFIG_ARCH_CHIP_SAM3U)
# define SMC_ADDR_CYCLE0_SHIFT (3) /* Bits 0-7: NAND Flash Array Address cycle 0 */
# define SMC_ADDR_CYCLE0_MASK (0xff << SMC_ADDR_CYCLE0_SHIFT)
#endif
/* SMC NFC Bank Register */
#define SMC_BANK_SHIFT (0) /* Bits 0-2: Bank identifier */
#define SMC_BANK_MASK (7 << SMC_BANK_SHIFT)
#if defined(CONFIG_ARCH_CHIP_SAM3U)
# define SMC_BANK_SHIFT (0) /* Bits 0-2: Bank identifier */
# define SMC_BANK_MASK (7 << SMC_BANK_SHIFT)
#endif
/* SMC ECC Control Register */
#define SMC_ECCCTRL_RST (1 << 0) /* Bit 0: Reset ECC */
#define SMC_ECCCTRL_SWRST (1 << 1) /* Bit 1: Software Reset */
#if defined(CONFIG_ARCH_CHIP_SAM3U)
# define SMC_ECCCTRL_RST (1 << 0) /* Bit 0: Reset ECC */
# define SMC_ECCCTRL_SWRST (1 << 1) /* Bit 1: Software Reset */
#endif
/* SMC ECC MODE Register */
#define SMC_ECCMD_ECC_PAGESIZE_SHIFT (0) /* Bits 0-1 */
#define SMC_ECCMD_ECC_PAGESIZE_MASK (3 << SMC_ECCMD_ECC_PAGESIZE_SHIFT)
# define SMC_ECCMD_ECC_PAGESIZE_528 (0 << SMC_ECCMD_ECC_PAGESIZE_SHIFT)
# define SMC_ECCMD_ECC_PAGESIZE_1056 (1 << SMC_ECCMD_ECC_PAGESIZE_SHIFT)
# define SMC_ECCMD_ECC_PAGESIZE_2112 (2 << SMC_ECCMD_ECC_PAGESIZE_SHIFT)
# define SMC_ECCMD_ECC_PAGESIZE_4224 (3 << SMC_ECCMD_ECC_PAGESIZE_SHIFT)
#define SMC_ECCMD_TYPCORREC_SHIFT (4) /* Bits 4-5: type of correction */
#define SMC_ECCMD_TYPCORREC_MASK (3 << SMC_ECCMD_TYPCORREC_SHIFT)
# define SMC_ECCMD_TYPCORREC_PAGE (0 << SMC_ECCMD_TYPCORREC_SHIFT) /* 1 bit correction for a page */
# define SMC_ECCMD_TYPCORREC_256 (1 << SMC_ECCMD_TYPCORREC_SHIFT) /* 1 bit correction for 256 bytes */
# define SMC_ECCMD_TYPCORREC_512 (2 << SMC_ECCMD_TYPCORREC_SHIFT) /* 1 bit correction for 512 bytes */
#if defined(CONFIG_ARCH_CHIP_SAM3U)
# define SMC_ECCMD_ECC_PAGESIZE_SHIFT (0) /* Bits 0-1 */
# define SMC_ECCMD_ECC_PAGESIZE_MASK (3 << SMC_ECCMD_ECC_PAGESIZE_SHIFT)
# define SMC_ECCMD_ECC_PAGESIZE_528 (0 << SMC_ECCMD_ECC_PAGESIZE_SHIFT)
# define SMC_ECCMD_ECC_PAGESIZE_1056 (1 << SMC_ECCMD_ECC_PAGESIZE_SHIFT)
# define SMC_ECCMD_ECC_PAGESIZE_2112 (2 << SMC_ECCMD_ECC_PAGESIZE_SHIFT)
# define SMC_ECCMD_ECC_PAGESIZE_4224 (3 << SMC_ECCMD_ECC_PAGESIZE_SHIFT)
# define SMC_ECCMD_TYPCORREC_SHIFT (4) /* Bits 4-5: type of correction */
# define SMC_ECCMD_TYPCORREC_MASK (3 << SMC_ECCMD_TYPCORREC_SHIFT)
# define SMC_ECCMD_TYPCORREC_PAGE (0 << SMC_ECCMD_TYPCORREC_SHIFT) /* 1 bit correction for a page */
# define SMC_ECCMD_TYPCORREC_256 (1 << SMC_ECCMD_TYPCORREC_SHIFT) /* 1 bit correction for 256 bytes */
# define SMC_ECCMD_TYPCORREC_512 (2 << SMC_ECCMD_TYPCORREC_SHIFT) /* 1 bit correction for 512 bytes */
#endif
/* SMC ECC Status Register 1 */
#define _RECERR (0) /* Recoverable Error */
#define _ECCERR (1) /* ECC Error */
#define _MULERR (2) /* Multiple Error */
#if defined(CONFIG_ARCH_CHIP_SAM3U)
# define _RECERR (0) /* Recoverable Error */
# define _ECCERR (1) /* ECC Error */
# define _MULERR (2) /* Multiple Error */
#define SMC_ECCSR1_RECERR(n) (1 << (((n)<<4)+_RECERR))
#define SMC_ECCSR1_ECCERR(n) (1 << (((n)<<4)+_ECCERR))
#define SMC_ECCSR1_MULERR(n) (1 << (((n)<<4)+_MULERR))
# define SMC_ECCSR1_RECERR(n) (1 << (((n)<<4)+_RECERR))
# define SMC_ECCSR1_ECCERR(n) (1 << (((n)<<4)+_ECCERR))
# define SMC_ECCSR1_MULERR(n) (1 << (((n)<<4)+_MULERR))
#define SMC_ECCSR1_RECERR0 SMC_ECCSR1_RECERR(0)
#define SMC_ECCSR1_ECCERR0 SMC_ECCSR1_ECCERR(0)
#define SMC_ECCSR1_MULERR0 SMC_ECCSR1_MULERR(0)
#define SMC_ECCSR1_RECERR1 SMC_ECCSR1_RECERR(1)
#define SMC_ECCSR1_ECCERR1 SMC_ECCSR1_ECCERR(1)
#define SMC_ECCSR1_MULERR1 SMC_ECCSR1_MULERR(1)
#define SMC_ECCSR1_RECERR2 SMC_ECCSR1_RECERR(2)
#define SMC_ECCSR1_ECCERR2 SMC_ECCSR1_ECCERR(2)
#define SMC_ECCSR1_MULERR2 SMC_ECCSR1_MULERR(2)
#define SMC_ECCSR1_RECERR3 SMC_ECCSR1_RECERR(3)
#define SMC_ECCSR1_ECCERR3 SMC_ECCSR1_ECCERR(3)
#define SMC_ECCSR1_MULERR3 SMC_ECCSR1_MULERR(3)
#define SMC_ECCSR1_RECERR4 SMC_ECCSR1_RECERR(4)
#define SMC_ECCSR1_ECCERR4 SMC_ECCSR1_ECCERR(4)
#define SMC_ECCSR1_MULERR4 SMC_ECCSR1_MULERR(4)
#define SMC_ECCSR1_RECERR5 SMC_ECCSR1_RECERR(5)
#define SMC_ECCSR1_ECCERR5 SMC_ECCSR1_ECCERR(5)
#define SMC_ECCSR1_MULERR5 SMC_ECCSR1_MULERR(5)
#define SMC_ECCSR1_RECERR6 SMC_ECCSR1_RECERR(6)
#define SMC_ECCSR1_ECCERR6 SMC_ECCSR1_ECCERR(6)
#define SMC_ECCSR1_MULERR6 SMC_ECCSR1_MULERR(6)
#define SMC_ECCSR1_RECERR7 SMC_ECCSR1_RECERR(7)
#define SMC_ECCSR1_ECCERR7 SMC_ECCSR1_ECCERR(7)
#define SMC_ECCSR1_MULERR7 SMC_ECCSR1_MULERR(7)
# define SMC_ECCSR1_RECERR0 SMC_ECCSR1_RECERR(0)
# define SMC_ECCSR1_ECCERR0 SMC_ECCSR1_ECCERR(0)
# define SMC_ECCSR1_MULERR0 SMC_ECCSR1_MULERR(0)
# define SMC_ECCSR1_RECERR1 SMC_ECCSR1_RECERR(1)
# define SMC_ECCSR1_ECCERR1 SMC_ECCSR1_ECCERR(1)
# define SMC_ECCSR1_MULERR1 SMC_ECCSR1_MULERR(1)
# define SMC_ECCSR1_RECERR2 SMC_ECCSR1_RECERR(2)
# define SMC_ECCSR1_ECCERR2 SMC_ECCSR1_ECCERR(2)
# define SMC_ECCSR1_MULERR2 SMC_ECCSR1_MULERR(2)
# define SMC_ECCSR1_RECERR3 SMC_ECCSR1_RECERR(3)
# define SMC_ECCSR1_ECCERR3 SMC_ECCSR1_ECCERR(3)
# define SMC_ECCSR1_MULERR3 SMC_ECCSR1_MULERR(3)
# define SMC_ECCSR1_RECERR4 SMC_ECCSR1_RECERR(4)
# define SMC_ECCSR1_ECCERR4 SMC_ECCSR1_ECCERR(4)
# define SMC_ECCSR1_MULERR4 SMC_ECCSR1_MULERR(4)
# define SMC_ECCSR1_RECERR5 SMC_ECCSR1_RECERR(5)
# define SMC_ECCSR1_ECCERR5 SMC_ECCSR1_ECCERR(5)
# define SMC_ECCSR1_MULERR5 SMC_ECCSR1_MULERR(5)
# define SMC_ECCSR1_RECERR6 SMC_ECCSR1_RECERR(6)
# define SMC_ECCSR1_ECCERR6 SMC_ECCSR1_ECCERR(6)
# define SMC_ECCSR1_MULERR6 SMC_ECCSR1_MULERR(6)
# define SMC_ECCSR1_RECERR7 SMC_ECCSR1_RECERR(7)
# define SMC_ECCSR1_ECCERR7 SMC_ECCSR1_ECCERR(7)
# define SMC_ECCSR1_MULERR7 SMC_ECCSR1_MULERR(7)
#endif
/* SMC ECC Status Register 2 */
#define SMC_ECCSR2_RECERR(n) (1 << ((((n)-8)<<4)+_RECERR))
#define SMC_ECCSR2_ECCERR(n) (1 << ((((n)-8)<<4)+_ECCERR))
#define SMC_ECCSR2_MULERR(n) (1 << ((((n)-8)<<4)+_MULERR))
#if defined(CONFIG_ARCH_CHIP_SAM3U)
# define SMC_ECCSR2_RECERR(n) (1 << ((((n)-8)<<4)+_RECERR))
# define SMC_ECCSR2_ECCERR(n) (1 << ((((n)-8)<<4)+_ECCERR))
# define SMC_ECCSR2_MULERR(n) (1 << ((((n)-8)<<4)+_MULERR))
#define SMC_ECCSR2_RECERR8 SMC_ECCSR2_RECERR(8)
#define SMC_ECCSR2_ECCERR8 SMC_ECCSR2_ECCERR(8)
#define SMC_ECCSR2_MULERR8 SMC_ECCSR2_MULERR(8)
#define SMC_ECCSR2_RECERR9 SMC_ECCSR2_RECERR(9)
#define SMC_ECCSR2_ECCERR9 SMC_ECCSR2_ECCERR(9)
#define SMC_ECCSR2_MULERR9 SMC_ECCSR2_MULERR(9)
#define SMC_ECCSR2_RECERR10 SMC_ECCSR2_RECERR(10)
#define SMC_ECCSR2_ECCERR10 SMC_ECCSR2_ECCERR(10)
#define SMC_ECCSR2_MULERR10 SMC_ECCSR2_MULERR(10)
#define SMC_ECCSR2_RECERR11 SMC_ECCSR2_RECERR(11)
#define SMC_ECCSR2_ECCERR11 SMC_ECCSR2_ECCERR(11)
#define SMC_ECCSR2_MULERR11 SMC_ECCSR2_MULERR(11)
#define SMC_ECCSR2_RECERR12 SMC_ECCSR2_RECERR(12)
#define SMC_ECCSR2_ECCERR12 SMC_ECCSR2_ECCERR(12)
#define SMC_ECCSR2_MULERR12 SMC_ECCSR2_MULERR(12)
#define SMC_ECCSR2_RECERR13 SMC_ECCSR2_RECERR(13)
#define SMC_ECCSR2_ECCERR13 SMC_ECCSR2_ECCERR(13)
#define SMC_ECCSR2_MULERR13 SMC_ECCSR2_MULERR(13)
#define SMC_ECCSR1_RECERR14 SMC_ECCSR2_RECERR(14)
#define SMC_ECCSR1_ECCERR14 SMC_ECCSR2_ECCERR(14)
#define SMC_ECCSR1_MULERR14 SMC_ECCSR2_MULERR(14)
#define SMC_ECCSR1_RECERR15 SMC_ECCSR2_RECERR(15)
#define SMC_ECCSR1_ECCERR15 SMC_ECCSR2_ECCERR(15)
#define SMC_ECCSR1_MULERR15 SMC_ECCSR2_MULERR(15)
# define SMC_ECCSR2_RECERR8 SMC_ECCSR2_RECERR(8)
# define SMC_ECCSR2_ECCERR8 SMC_ECCSR2_ECCERR(8)
# define SMC_ECCSR2_MULERR8 SMC_ECCSR2_MULERR(8)
# define SMC_ECCSR2_RECERR9 SMC_ECCSR2_RECERR(9)
# define SMC_ECCSR2_ECCERR9 SMC_ECCSR2_ECCERR(9)
# define SMC_ECCSR2_MULERR9 SMC_ECCSR2_MULERR(9)
# define SMC_ECCSR2_RECERR10 SMC_ECCSR2_RECERR(10)
# define SMC_ECCSR2_ECCERR10 SMC_ECCSR2_ECCERR(10)
# define SMC_ECCSR2_MULERR10 SMC_ECCSR2_MULERR(10)
# define SMC_ECCSR2_RECERR11 SMC_ECCSR2_RECERR(11)
# define SMC_ECCSR2_ECCERR11 SMC_ECCSR2_ECCERR(11)
# define SMC_ECCSR2_MULERR11 SMC_ECCSR2_MULERR(11)
# define SMC_ECCSR2_RECERR12 SMC_ECCSR2_RECERR(12)
# define SMC_ECCSR2_ECCERR12 SMC_ECCSR2_ECCERR(12)
# define SMC_ECCSR2_MULERR12 SMC_ECCSR2_MULERR(12)
# define SMC_ECCSR2_RECERR13 SMC_ECCSR2_RECERR(13)
# define SMC_ECCSR2_ECCERR13 SMC_ECCSR2_ECCERR(13)
# define SMC_ECCSR2_MULERR13 SMC_ECCSR2_MULERR(13)
# define SMC_ECCSR1_RECERR14 SMC_ECCSR2_RECERR(14)
# define SMC_ECCSR1_ECCERR14 SMC_ECCSR2_ECCERR(14)
# define SMC_ECCSR1_MULERR14 SMC_ECCSR2_MULERR(14)
# define SMC_ECCSR1_RECERR15 SMC_ECCSR2_RECERR(15)
# define SMC_ECCSR1_ECCERR15 SMC_ECCSR2_ECCERR(15)
# define SMC_ECCSR1_MULERR15 SMC_ECCSR2_MULERR(15)
#endif
/* Registers for 1 ECC for a page of 512/1024/2048/4096 bytes */
/* SMC_ECC_PR0 */
#define SMC_ECCPR0_BITADDR_SHIFT (0) /* Bits 0-3: Bit Address */
#define SMC_ECCPR0_BITADDR_MASK (15 << SMC_ECCPR0_BITADDR_SHIFT)
#define SMC_ECCPR0_WORDADDR_SHIFT (4) /* Bits 4-15: Word Address */
#define SMC_ECCPR0_WORDADDR_MASK (0xfff << SMC_ECCPR0_WORDADDR_SHIFT)
#if defined(CONFIG_ARCH_CHIP_SAM3U)
# define SMC_ECCPR0_BITADDR_SHIFT (0) /* Bits 0-3: Bit Address */
# define SMC_ECCPR0_BITADDR_MASK (15 << SMC_ECCPR0_BITADDR_SHIFT)
# define SMC_ECCPR0_WORDADDR_SHIFT (4) /* Bits 4-15: Word Address */
# define SMC_ECCPR0_WORDADDR_MASK (0xfff << SMC_ECCPR0_WORDADDR_SHIFT)
#define SMC_ECCPR1_NPARITY_SHIFT (0) /* Bits 0-15 */
#define SMC_ECCPR1_NPARITY_MASK (0xffff << SMC_ECCPR1_NPARITY_SHIFT)
# define SMC_ECCPR1_NPARITY_SHIFT (0) /* Bits 0-15 */
# define SMC_ECCPR1_NPARITY_MASK (0xffff << SMC_ECCPR1_NPARITY_SHIFT)
#endif
/* Registers for 1 ECC per 512 bytes for a page of 512/2048/4096 bytes, 8-bit word */
#define SMC_ECCPR512_BITADDR_SHIFT (0) /* Bits 0-3: Bit Address */
#define SMC_ECCPR512_BITADDR_MASK (15 << SMC_ECCPR512_BITADDR_SHIFT)
#define SMC_ECCPR512_WORDADDR_SHIFT (4) /* Bits 4-15: Word Address */
#define SMC_ECCPR512_WORDADDR_MASK (0xfff << SMC_ECCPR512_WORDADDR_SHIFT)
#define SMC_ECCPR512_NPARITY_SHIFT (12) /* Bits 12-23 (or is it 31?) */
#define SMC_ECCPR512_NPARITY_MASK (0xfff << SMC_ECCPR512_NPARITY_SHIFT)
#if defined(CONFIG_ARCH_CHIP_SAM3U)
# define SMC_ECCPR512_BITADDR_SHIFT (0) /* Bits 0-3: Bit Address */
# define SMC_ECCPR512_BITADDR_MASK (15 << SMC_ECCPR512_BITADDR_SHIFT)
# define SMC_ECCPR512_WORDADDR_SHIFT (4) /* Bits 4-15: Word Address */
# define SMC_ECCPR512_WORDADDR_MASK (0xfff << SMC_ECCPR512_WORDADDR_SHIFT)
# define SMC_ECCPR512_NPARITY_SHIFT (12) /* Bits 12-23 (or is it 31?) */
# define SMC_ECCPR512_NPARITY_MASK (0xfff << SMC_ECCPR512_NPARITY_SHIFT)
#endif
/* Registers for 1 ECC per 256 bytes for a page of 512/2048/4096 bytes, 8-bit word */
#define SMC_ECCPR256_BITADDR_SHIFT (0) /* Bits 0-2: Bit Address */
#define SMC_ECCPR256_BITADDR_MASK (7 << SMC_ECCPR256_BITADDR_SHIFT)
#define SMC_ECCPR256_WORDADDR_SHIFT (4) /* Bits 4-10: Word Address */
#define SMC_ECCPR256_WORDADDR_MASK (0x7f << SMC_ECCPR256_WORDADDR_SHIFT)
#define SMC_ECCPR256_NPARITY_SHIFT (12) /* Bits 12-22 */
#define SMC_ECCPR256_NPARITY_MASK (0x7ff << SMC_ECCPR256_NPARITY_SHIFT)
#if defined(CONFIG_ARCH_CHIP_SAM3U)
# define SMC_ECCPR256_BITADDR_SHIFT (0) /* Bits 0-2: Bit Address */
# define SMC_ECCPR256_BITADDR_MASK (7 << SMC_ECCPR256_BITADDR_SHIFT)
# define SMC_ECCPR256_WORDADDR_SHIFT (4) /* Bits 4-10: Word Address */
# define SMC_ECCPR256_WORDADDR_MASK (0x7f << SMC_ECCPR256_WORDADDR_SHIFT)
# define SMC_ECCPR256_NPARITY_SHIFT (12) /* Bits 12-22 */
# define SMC_ECCPR256_NPARITY_MASK (0x7ff << SMC_ECCPR256_NPARITY_SHIFT)
#endif
/* SMC Setup Register */
#define SMCCS_SETUP_NWESETUP_SHIFT (0) /* Bits 0-5: NWE Setup length */
#define SMCCS_SETUP_NWESETUP_MASK (63 << SMCCS_SETUP_NWESETUP_SHIFT)
#define SMCCS_SETUP_NCSWRSETUP_SHIFT (8) /* Bits 8-13: NCS Setup length in Write access */
#define SMCCS_SETUP_NCSWRSETUP_MASK (63 << SMCCS_SETUP_NCSWRSETUP_SHIFT)
#define SMCCS_SETUP_NRDSETUP_SHIFT (16) /* Bits 16-21: NRD Setup length */
#define SMCCS_SETUP_NRDSETUP_MASK (63 << SMCCS_SETUP_NRDSETUP_SHIFT)
#define SMCCS_SETUP_NCSRDSETUP_SHIFT (24) /* Bits 24-29: NCS Setup length in Read access */
#define SMCCS_SETUP_NCSRDSETUP_MASK (63 << SMCCS_SETUP_NCSRDSETUP_SHIFT)
#define SMCCS_SETUP_NWESETUP_SHIFT (0) /* Bits 0-5: NWE Setup length */
#define SMCCS_SETUP_NWESETUP_MASK (63 << SMCCS_SETUP_NWESETUP_SHIFT)
#define SMCCS_SETUP_NCSWRSETUP_SHIFT (8) /* Bits 8-13: NCS Setup length in Write access */
#define SMCCS_SETUP_NCSWRSETUP_MASK (63 << SMCCS_SETUP_NCSWRSETUP_SHIFT)
#define SMCCS_SETUP_NRDSETUP_SHIFT (16) /* Bits 16-21: NRD Setup length */
#define SMCCS_SETUP_NRDSETUP_MASK (63 << SMCCS_SETUP_NRDSETUP_SHIFT)
#define SMCCS_SETUP_NCSRDSETUP_SHIFT (24) /* Bits 24-29: NCS Setup length in Read access */
#define SMCCS_SETUP_NCSRDSETUP_MASK (63 << SMCCS_SETUP_NCSRDSETUP_SHIFT)
/* SMC Pulse Register */
#define SMCCS_PULSE_NWEPULSE_SHIFT (0) /* Bits 0-5: NWE Pulse Length */
#define SMCCS_PULSE_NWEPULSE_MASK (63 << SMCCS_PULSE_NWEPULSE_SHIFT)
#define SMCCS_PULSE_NCSWRPULSE_SHIFT (8) /* Bits 8-13: NCS Pulse Length in WRITE Access */
#define SMCCS_PULSE_NCSWRPULSE_MASK (63 << SMCCS_PULSE_NCSWRPULSE_SHIFT)
#define SMCCS_PULSE_RDPULSE_SHIFT (16) /* Bits 16-21: NRD Pulse Length */
#define SMCCS_PULSE_RDPULSE_MASK (63 << SMCCS_PULSE_RDPULSE_SHIFT)
#define SMCCS_PULSE_NCSRDPULSE_SHIFT (24) /* Bits 24-29: NCS Pulse Length in READ Access */
#define SMCCS_PULSE_NCSRDPULSE_MASK (63 << SMCCS_PULSE_NCSRDPULSE_SHIFT)
#define SMCCS_PULSE_NWEPULSE_SHIFT (0) /* Bits 0-5: NWE Pulse Length */
#define SMCCS_PULSE_NWEPULSE_MASK (63 << SMCCS_PULSE_NWEPULSE_SHIFT)
#define SMCCS_PULSE_NCSWRPULSE_SHIFT (8) /* Bits 8-13: NCS Pulse Length in WRITE Access */
#define SMCCS_PULSE_NCSWRPULSE_MASK (63 << SMCCS_PULSE_NCSWRPULSE_SHIFT)
#define SMCCS_PULSE_NRDPULSE_SHIFT (16) /* Bits 16-21: NRD Pulse Length */
#define SMCCS_PULSE_NRDPULSE_MASK (63 << SMCCS_PULSE_NRDPULSE_SHIFT)
#define SMCCS_PULSE_NCSRDPULSE_SHIFT (24) /* Bits 24-29: NCS Pulse Length in READ Access */
#define SMCCS_PULSE_NCSRDPULSE_MASK (63 << SMCCS_PULSE_NCSRDPULSE_SHIFT)
/* SMC Cycle Register */
#define SMCCS_CYCLE_NWECYCLE_SHIFT (0) /* Bits 0-8: Total Write Cycle Length */
#define SMCCS_CYCLE_NWECYCLE_MASK (0x1ff << SMCCS_CYCLE_NWECYCLE_SHIFT)
#define SMCCS_CYCLE_NRDCYCLE_SHIFT (16) /* Bits 16-24: Total Read Cycle Length */
#define SMCCS_CYCLE_NRDCYCLE_MASK (0x1ff << SMCCS_CYCLE_NRDCYCLE_SHIFT)
#define SMCCS_CYCLE_NWECYCLE_SHIFT (0) /* Bits 0-8: Total Write Cycle Length */
#define SMCCS_CYCLE_NWECYCLE_MASK (0x1ff << SMCCS_CYCLE_NWECYCLE_SHIFT)
#define SMCCS_CYCLE_NRDCYCLE_SHIFT (16) /* Bits 16-24: Total Read Cycle Length */
#define SMCCS_CYCLE_NRDCYCLE_MASK (0x1ff << SMCCS_CYCLE_NRDCYCLE_SHIFT)
/* SMC Timings Register */
#define SMCCS_TIMINGS_TCLR_SHIFT (0) /* Bits 0-3: CLE to REN Low Delay */
#define SMCCS_TIMINGS_TCLR_MASK (15 << SMCCS_TIMINGS_TCLR_SHIFT)
#define SMCCS_TIMINGS_TADL_SHIFT (4) /* Bits 4-7: ALE to Data Start */
#define SMCCS_TIMINGS_TADL_MASK (15 << SMCCS_TIMINGS_TADL_SHIFT)
#define SMCCS_TIMINGS_TAR_SHIFT (8) /* Bits 8-11: ALE to REN Low Delay */
#define SMCCS_TIMINGS_TAR_MASK (15 << SMCCS_TIMINGS_TAR_SHIFT)
#define SMCCS_TIMINGS_OCMS (1 << 12) /* Bit 12: Off Chip Memory Scrambling Enable */
#define SMCCS_TIMINGS_TRR_SHIFT (16) /* Bits 16-19: Ready to REN Low Delay */
#define SMCCS_TIMINGS_TRR_MASK (15 << SMCCS_TIMINGS_TRR_SHIFT)
#define SMCCS_TIMINGS_TWB_SHIFT (24) /* Bits 24-27: WEN High to REN to Busy */
#define SMCCS_TIMINGS_TWB_MASK (15 << SMCCS_TIMINGS_TWB_SHIFT)
#define SMCCS_TIMINGS_RBNSEL_SHIFT (28) /* Bits 28-30: Ready/Busy Line Selection */
#define SMCCS_TIMINGS_RBNSEL_MASK (7 << SMCCS_TIMINGS_RBNSEL_SHIFT)
#define SMCCS_TIMINGS_NFSEL (1 << 31) /* Bit 31: NAND Flash Selection */
#if defined(CONFIG_ARCH_CHIP_SAM3U)
# define SMCCS_TIMINGS_TCLR_SHIFT (0) /* Bits 0-3: CLE to REN Low Delay */
# define SMCCS_TIMINGS_TCLR_MASK (15 << SMCCS_TIMINGS_TCLR_SHIFT)
# define SMCCS_TIMINGS_TADL_SHIFT (4) /* Bits 4-7: ALE to Data Start */
# define SMCCS_TIMINGS_TADL_MASK (15 << SMCCS_TIMINGS_TADL_SHIFT)
# define SMCCS_TIMINGS_TAR_SHIFT (8) /* Bits 8-11: ALE to REN Low Delay */
# define SMCCS_TIMINGS_TAR_MASK (15 << SMCCS_TIMINGS_TAR_SHIFT)
# define SMCCS_TIMINGS_OCMS (1 << 12) /* Bit 12: Off Chip Memory Scrambling Enable */
# define SMCCS_TIMINGS_TRR_SHIFT (16) /* Bits 16-19: Ready to REN Low Delay */
# define SMCCS_TIMINGS_TRR_MASK (15 << SMCCS_TIMINGS_TRR_SHIFT)
# define SMCCS_TIMINGS_TWB_SHIFT (24) /* Bits 24-27: WEN High to REN to Busy */
# define SMCCS_TIMINGS_TWB_MASK (15 << SMCCS_TIMINGS_TWB_SHIFT)
# define SMCCS_TIMINGS_RBNSEL_SHIFT (28) /* Bits 28-30: Ready/Busy Line Selection */
# define SMCCS_TIMINGS_RBNSEL_MASK (7 << SMCCS_TIMINGS_RBNSEL_SHIFT)
# define SMCCS_TIMINGS_NFSEL (1 << 31) /* Bit 31: NAND Flash Selection */
#endif
/* SMC Mode Register */
#define SMCCS_MODE_READMODE (1 << 0) /* Bit 0: Read mode */
#define SMCCS_MODE_WRITEMODE (1 << 1) /* Bit 1: Write mode */
#define SMCCS_MODE_EXNWMODE_SHIFT (4) /* Bits 4-5: NWAIT Mode */
#define SMCCS_MODE_EXNWMODE_MASK (3 << SMCCS_MODE_EXNWMODE_SHIFT)
# define SMCCS_EXNWMODE_DISABLED (0 << SMCCS_MODE_EXNWMODE_SHIFT)
# define SMCCS_EXNWMODE_FROZEN (2 << SMCCS_MODE_EXNWMODE_SHIFT)
# define SMCCS_EXNWMODE_READY (3 << SMCCS_MODE_EXNWMODE_SHIFT)
#define SMCCS_MODE_BAT (1 << 8) /* Bit 8: Byte Access Type */
#define SMCCS_MODE_DBW_SHIFT (12) /* Bits 12-13: Data Bus Width */
#define SMCCS_MODE_DBW_MASK (3 << SMCCS_MODE_DBW_SHIFT)
# define SMCCS_MODE_DBW_8BITS (0 << 12) /* 8 bits */
# define SMCCS_MODE_DBW_16BITS (1 << 12) /* 16 bits */
# define SMCCS_MODE_DBW_32BITS (2 << 12) /* 32 bits */
#define SMCCS_MODE_TDFCYCLES_SHIFT (16) /* Bits 16-19: Data Float Time */
#define SMCCS_MODE_TDFCYCLES_MASK (15 << SMCCS_MODE_TDFCYCLES_SHIFT)
#define SMCCS_MODE_TDFMODE (1 << 20) /* Bit 20: TDF Optimization */
#define SMCCS_MODE_PMEN (1 << 24) /* Bit 24: Page Mode Enabled */
#define SMCCS_MODE_PS_SHIFT (28) /* Bits 28-29: Page Size */
#define SMCCS_MODE_PS_MASK (3 << SMCCS_MODE_PS_SHIFT)
# define SMCCS_MODE_PS_SIZE_4BYTES (0 << SMCCS_MODE_PS_SHIFT) /* 4 bytes */
# define SMCCS_MODE_PS_SIZE_8BYTES (1 << SMCCS_MODE_PS_SHIFT) /* 8 bytes */
# define SMCCS_MODE_PS_SIZE_16BYTES (2 << SMCCS_MODE_PS_SHIFT) /* 16 bytes */
# define SMCCS_MODE_PS_SIZE_32BYTES (3 << SMCCS_MODE_PS_SHIFT) /* 32 bytes */
#define SMCCS_MODE_READMODE (1 << 0) /* Bit 0: Read mode */
#define SMCCS_MODE_WRITEMODE (1 << 1) /* Bit 1: Write mode */
#define SMCCS_MODE_EXNWMODE_SHIFT (4) /* Bits 4-5: NWAIT Mode */
#define SMCCS_MODE_EXNWMODE_MASK (3 << SMCCS_MODE_EXNWMODE_SHIFT)
# define SMCCS_EXNWMODE_DISABLED (0 << SMCCS_MODE_EXNWMODE_SHIFT)
# define SMCCS_EXNWMODE_FROZEN (2 << SMCCS_MODE_EXNWMODE_SHIFT)
# define SMCCS_EXNWMODE_READY (3 << SMCCS_MODE_EXNWMODE_SHIFT)
/* SMC OCMS Register */
#if defined(CONFIG_ARCH_CHIP_SAM3U)
# define SMCCS_MODE_BAT (1 << 8) /* Bit 8: Byte Access Type */
# define SMCCS_MODE_DBW_SHIFT (12) /* Bits 12-13: Data Bus Width */
# define SMCCS_MODE_DBW_MASK (3 << SMCCS_MODE_DBW_SHIFT)
# define SMCCS_MODE_DBW_8BITS (0 << 12) /* 8 bits */
# define SMCCS_MODE_DBW_16BITS (1 << 12) /* 16 bits */
# define SMCCS_MODE_DBW_32BITS (2 << 12) /* 32 bits */
#endif
#define SMC_OCMS_SMSE (1 << 0) /* Bit 0: Static Memory Controller Scrambling Enable */
#define SMC_OCMS_SRSE (1 << 1) /* Bit 1: SRAM Scrambling Enable */
#define SMCCS_MODE_TDFCYCLES_SHIFT (16) /* Bits 16-19: Data Float Time */
#define SMCCS_MODE_TDFCYCLES_MASK (15 << SMCCS_MODE_TDFCYCLES_SHIFT)
#define SMCCS_MODE_TDFMODE (1 << 20) /* Bit 20: TDF Optimization */
#define SMCCS_MODE_PMEN (1 << 24) /* Bit 24: Page Mode Enabled */
#define SMCCS_MODE_PS_SHIFT (28) /* Bits 28-29: Page Size */
#define SMCCS_MODE_PS_MASK (3 << SMCCS_MODE_PS_SHIFT)
# define SMCCS_MODE_PS_SIZE_4BYTES (0 << SMCCS_MODE_PS_SHIFT) /* 4 bytes */
# define SMCCS_MODE_PS_SIZE_8BYTES (1 << SMCCS_MODE_PS_SHIFT) /* 8 bytes */
# define SMCCS_MODE_PS_SIZE_16BYTES (2 << SMCCS_MODE_PS_SHIFT) /* 16 bytes */
# define SMCCS_MODE_PS_SIZE_32BYTES (3 << SMCCS_MODE_PS_SHIFT) /* 32 bytes */
/* SMC Write Protection Control */
/* SMC OCMS Mode Register */
#define SMC_WPCR_WPPEN (1 << 9) /* Bit 9: Write Protection Enable */
#define SMC_WPCR_WPKEY_SHIFT (8) /* Bits 8-31: Write Protection KEY password */
#define SMC_WPCR_WPKEY_MASK (0x00ffffff << SMC_WPCR_WPKEY_SHIFT)
#define SMC_OCMS_SMSE (1 << 0) /* Bit 0: Static Memory Controller Scrambling Enable */
#define SMC_OCMS_SRSE (1 << 1) /* Bit 1: SRAM Scrambling Enable */
#if defined(CONFIG_ARCH_CHIP_SAM4S)
# define SMC_OCMS_CSSE(n) (1 << ((n)+16)) /* Chip Select (n=0-3) Scrambling Enable */
# define SMC_OCMS_CS0SE (1 << 16) /* Bit 16: Chip Select 0 Scrambling Enable */
# define SMC_OCMS_CS1SE (1 << 17) /* Bit 17: Chip Select 1 Scrambling Enable */
# define SMC_OCMS_CS2SE (1 << 18) /* Bit 18: Chip Select 2 Scrambling Enable */
# define SMC_OCMS_CS3SE (1 << 19) /* Bit 19: Chip Select 3 Scrambling Enable */
#endif
/* SMC KEY1/2 Registers (32-bit data) */
/* SMC Write Protect Mode Register */
#define SMC_WPCR_WPPEN (1 << 9) /* Bit 9: Write Protection Enable */
#define SMC_WPCR_WPKEY_SHIFT (8) /* Bits 8-31: Write Protection KEY password */
#define SMC_WPCR_WPKEY_MASK (0x00ffffff << SMC_WPCR_WPKEY_SHIFT)
# define SMC_WPCR_WPKEY (0x00534d43 << SMC_WPCR_WPKEY_SHIFT)
/* SMC Write Protection Status */
#define SMC_WPSR_PVS_SHIFT (0) /* Bits 0-3: Write Protection Violation Status */
#define SMC_WPSR_PVS_MASK (15 << SMC_WPSR_PVS_SHIFT)
# define SMC_WPSR_PVS_NONE (0 << SMC_WPSR_PVS_SHIFT) /* No Write Protection Violation */
# define SMC_WPSR_PVS_ RCREG (1 << SMC_WPSR_PVS_SHIFT) /* Attempt to write a control reg */
# define SMC_WPSR_PVS_RESET (2 << SMC_WPSR_PVS_SHIFT) /* Software reset */
# define SMC_WPSR_PVS_BOTH (3 << SMC_WPSR_PVS_SHIFT) /* Write + reset */
#if defined(CONFIG_ARCH_CHIP_SAM3U)
# define SMC_WPSR_PVS_SHIFT (0) /* Bits 0-3: Write Protection Violation Status */
# define SMC_WPSR_PVS_MASK (15 << SMC_WPSR_PVS_SHIFT)
# define SMC_WPSR_PVS_NONE (0 << SMC_WPSR_PVS_SHIFT) /* No Write Protection Violation */
# define SMC_WPSR_PVS_ RCREG (1 << SMC_WPSR_PVS_SHIFT) /* Attempt to write a control reg */
# define SMC_WPSR_PVS_RESET (2 << SMC_WPSR_PVS_SHIFT) /* Software reset */
# define SMC_WPSR_PVS_BOTH (3 << SMC_WPSR_PVS_SHIFT) /* Write + reset */
#elif defined(CONFIG_ARCH_CHIP_SAM4S)
# define SMC_WPSR_WPVS (1 << 0) /* Bit 0: Write Protect Violation Source */
#endif
#define SMC_WPSR_WPVSRC_SHIFT (8) /* Bits 8-23: Write Protection Violation Source */
#define SMC_WPSR_WPVSRC_MASK (0xffff << SMC_WPSR_WPVSRC_SHIFT)

1
arch/arm/src/sam34/chip/sam_spi.h
View file

@ -1,5 +1,6 @@
/****************************************************************************************
* arch/arm/src/sam34/chip/sam_spi.h
* Serial Peripheral Interface (SPI) definitions for the SAM3U and SAM4S
*
* Copyright (C) 2009, 2011, 2013 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>

21
arch/arm/src/sam34/chip/sam_ssc.h
View file

@ -1,5 +1,6 @@
/****************************************************************************************
* arch/arm/src/sam34/chip/sam_ssc.h
* Synchronous Serial Controller (SSC) definitions for the SAM3U and SAM4S
*
* Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
@ -74,7 +75,7 @@
#define SAM_SSC_WPMR_OFFSET 0x0e4 /* Write Protect Mode Register */
#define SAM_SSC_WPSR_OFFSET 0x0e8 /* Write Protect Status Register */
/* 0x050-0x0fc: Reserved */
/* 0x100-0x124: Reserved */
/* 0x100-0x124: Reserved for PDC registers */
/* SSC register adresses ****************************************************************/
@ -121,7 +122,7 @@
# define SSC_RCMR_CKS_RK (2 << SSC_RCMR_CKS_SHIFT) /* RK pin */
#define SSC_RCMR_CKO_SHIFT (2) /* Bits 2-4: Receive Clock Output Mode Selection */
#define SSC_RCMR_CKO_MASK (7 << SSC_RCMR_CKO_SHIFT)
# define SSC_RCMR_CKO_ NONE (0 << SSC_RCMR_CKO_SHIFT) /* None */
# define SSC_RCMR_CKO_NONE (0 << SSC_RCMR_CKO_SHIFT) /* None */
# define SSC_RCMR_CKO_CONTINUOUS (1 << SSC_RCMR_CKO_SHIFT) /* Continuous Receive Clock */
# define SSC_RCMR_CKO_XFERS (2 << SSC_RCMR_CKO_SHIFT) /* Receive Clock only during data transfers */
#define SSC_RCMR_CKI (1 << 5) /* Bit 5: Receive Clock Inversion */
@ -142,12 +143,11 @@
# define SSC_RCMR_START_ANYEDGE (7 << SSC_RCMR_START_SHIFT) /* Any edge on RF signal */
# define SSC_RCMR_START_CMP0 (8 << SSC_RCMR_START_SHIFT) /* Compare 0 */
#define SSC_RCMR_STOP (1 << 12) /* Bit 12: Receive Stop Select */
#define SSC_RCMR_STTDLY_SHIFT (15) /* Bits 16-23: Receive Start Delay */
#define SSC_RCMR_STTDLY_SHIFT (16) /* Bits 16-23: Receive Start Delay */
#define SSC_RCMR_STTDLY_MASK (0xff << SSC_RCMR_STTDLY_SHIFT)
#define SSC_RCMR_PERIOD_SHIFT (24) /* Bits 24-31: Receive Period Divider Selection */
#define SSC_RCMR_PERIOD_MASK (0xff << SSC_RCMR_PERIOD_SHIFT)
/* SSC Receive Frame Mode Register */
#define SSC_RFMR_DATLEN_SHIFT (0) /* Bits 0-4: Data Length */
@ -162,7 +162,7 @@
#define SSC_RFMR_FSOS_MASK (7 << SSC_RFMR_FSOS_SHIFT)
# define SSC_RFMR_FSOS_NONE (0 << SSC_RFMR_FSOS_SHIFT) /* None */
# define SSC_RFMR_FSOS_NEG (1 << SSC_RFMR_FSOS_SHIFT) /* 0x1 Negative Pulse */
# define SSC_RFMR_FSOS_POW (2 << SSC_RFMR_FSOS_SHIFT) /* 0x2 Positive Pulse */
# define SSC_RFMR_FSOS_POS (2 << SSC_RFMR_FSOS_SHIFT) /* 0x2 Positive Pulse */
# define SSC_RFMR_FSOS_LOW (3 << SSC_RFMR_FSOS_SHIFT) /* 0x3 Driven Low during data transfer */
# define SSC_RFMR_FSOS_HIGH (4 << SSC_RFMR_FSOS_SHIFT) /* 0x4 Driven High during data transfer */
# define SSC_RFMR_FSOS_TOGGLE (5 << SSC_RFMR_FSOS_SHIFT) /* 0x5 Toggling at each start of data transfer */
@ -175,11 +175,11 @@
#define SSC_TCMR_CKS_SHIFT (0) /* Bits 0-1: Transmit Clock Selection */
#define SSC_TCMR_CKS_MASK (3 << SSC_TCMR_CKS_SHIFT)
# define SSC_TCMR_CKS_DIVIDED (0 << SSC_TCMR_CKS_SHIFT) /* Divided Clock */
# define SSC_TCMR_CKS_TK (1 << SSC_TCMR_CKS_SHIFT) /* TK Clock signal */
# define SSC_TCMR_CKS_RK (2 << SSC_TCMR_CKS_SHIFT) /* RK pin */
# define SSC_TCMR_CKS_RK (2 << SSC_TCMR_CKS_SHIFT) /* RK Clock signal */
# define SSC_TCMR_CKS_TK (1 << SSC_TCMR_CKS_SHIFT) /* TK Pin */
#define SSC_TCMR_CKO_SHIFT (2) /* Bits 2-4: Transmit Clock Output Mode Selection */
#define SSC_TCMR_CKO_MASK (7 << SSC_TCMR_CKO_SHIFT)
# define SSC_TCMR_CKO_ NONE (0 << SSC_TCMR_CKO_SHIFT) /* None */
# define SSC_TCMR_CKO_NONE (0 << SSC_TCMR_CKO_SHIFT) /* None */
# define SSC_TCMR_CKO_CONTINUOUS (1 << SSC_TCMR_CKO_SHIFT) /* Continuous Transmit Clock */
# define SSC_TCMR_CKO_XFERS (2 << SSC_TCMR_CKO_SHIFT) /* Transmit Clock only during data transfers */
#define SSC_TCMR_CKI (1 << 5) /* Bit 5: Transmit Clock Inversion */
@ -217,7 +217,7 @@
#define SSC_TFMR_FSOS_MASK (7 << SSC_TFMR_FSOS_SHIFT)
# define SSC_TFMR_FSOS_NONE (0 << SSC_TFMR_FSOS_SHIFT) /* None */
# define SSC_TFMR_FSOS_NEG (1 << SSC_TFMR_FSOS_SHIFT) /* 0x1 Negative Pulse */
# define SSC_TFMR_FSOS_POW (2 << SSC_TFMR_FSOS_SHIFT) /* 0x2 Positive Pulse */
# define SSC_TFMR_FSOS_POS (2 << SSC_TFMR_FSOS_SHIFT) /* 0x2 Positive Pulse */
# define SSC_TFMR_FSOS_LOW (3 << SSC_TFMR_FSOS_SHIFT) /* 0x3 Driven Low during data transfer */
# define SSC_TFMR_FSOS_HIGH (4 << SSC_TFMR_FSOS_SHIFT) /* 0x4 Driven High during data transfer */
# define SSC_TFMR_FSOS_TOGGLE (5 << SSC_TFMR_FSOS_SHIFT) /* 0x5 Toggling at each start of data transfer */
@ -226,6 +226,8 @@
#define SSC_TFMR_FSLENEXT_SHIFT (28) /* Bits 28-31: FSLEN Field Extension */
#define SSC_TFMR_FSLENEXT_MASK (15 << SSC_TFMR_FSLENEXT_SHIFT)
/* SSC Receive/Transmit Holding Registers (32-bit data) */
/* SSC Receive Synchronization Holding Register */
#define SSC_RSHR_RSDAT_SHIFT (0) /* Bits 0-15: Receive Synchronization Data */
@ -270,6 +272,7 @@
#define SSC_WPMR_WPEN (1 << 0) /* Bit 0: Write Protect Enable */
#define SSC_WPMR_WPKEY_SHIFT (8) /* Bits 8-31: Write Protect KEY */
#define SSC_WPMR_WPKEY_MASK (0x00ffffff << SSC_WPMR_WPKEY_SHIFT)
# define SSC_WPMR_WPKEY (0x00535343 << SSC_WPMR_WPKEY_SHIFT)
/* SSC Write Protect Status Register */

113
arch/arm/src/sam34/chip/sam_tc.h
View file

@ -1,5 +1,6 @@
/************************************************************************************************
* arch/arm/src/sam34/chip/sam_tc.h
* Timer Counter (TC) definitions for the SAM3U and SAM4S
*
* Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
@ -56,7 +57,10 @@
#define SAM_TCN_OFFSET(n) (0x00 + ((n)<<6)) /* 0x00, 0x40, 0x80 */
#define SAM_TCN_CCR_OFFSET 0x00 /* Channel Control Register */
#define SAM_TCN_CMR_OFFSET 0x04 /* Channel Mode Register */
/* 0x08 Reserved */
#if defined(CONFIG_ARCH_CHIP_SAM4S)
#define SAM_TCN_SMMR_OFFSET 0x08 /* Stepper Motor Mode Register */
#endif
/* 0x0c Reserved */
#define SAM_TCN_CV_OFFSET 0x10 /* Counter Value */
#define SAM_TCN_RA_OFFSET 0x14 /* Register A */
@ -75,8 +79,11 @@
#define SAM_TC_QIDR_OFFSET 0xcc /* QDEC Interrupt Disable Register */
#define SAM_TC_QIMR_OFFSET 0xd0 /* QDEC Interrupt Mask Register */
#define SAM_TC_QISR_OFFSET 0xd4 /* QDEC Interrupt Status Register */
/* 0xd8 Reserved */
/* 0xe4 Reserved */
#if defined(CONFIG_ARCH_CHIP_SAM4S)
# define SAM_TCN_FMR_OFFSET 0xd8 /* Fault Mode Register */
# define SAM_TCN_WPMR_OFFSET 0xe4 /* Write Protect Mode Register */
#endif
/* TC register adresses *************************************************************************/
@ -84,6 +91,9 @@
#define SAM_TC_CCR(n) (SAM_TCN_BASE(n)+SAM_TCN_CCR_OFFSET)
#define SAM_TC_CMR(n) (SAM_TCN_BASE(n)+SAM_TCN_CMR_OFFSET)
#if defined(CONFIG_ARCH_CHIP_SAM4S)
# define SAM_TCN_SMMR(n) (SAM_TCN_BASE(n)+SAM_TCN_SMMR_OFFSET)
#endif
#define SAM_TC_CV(n) (SAM_TCN_BASE(n)+SAM_TCN_CV_OFFSET)
#define SAM_TC_RA(n) (SAM_TCN_BASE(n)+SAM_TCN_RA_OFFSET)
#define SAM_TC_RB(n) (SAM_TCN_BASE(n)+SAM_TCN_RB_OFFSET)
@ -92,9 +102,16 @@
#define SAM_TC_IER(n) (SAM_TCN_BASE(n)+SAM_TCN_IER_OFFSET)
#define SAM_TC_IDR(n) (SAM_TCN_BASE(n)+SAM_TCN_IDR_OFFSET)
#define SAM_TC_IMR(n) (SAM_TCN_BASE(n)+SAM_TCN_IMR_OFFSET)
#if defined(CONFIG_ARCH_CHIP_SAM4S)
# define SAM_TCN_FMR(n) (SAM_TCN_BASE(n)+SAM_TCN_FMR_OFFSET)
# define SAM_TCN_WPMR(n) (SAM_TCN_BASE(n)+SAM_TCN_WPMR_OFFSET)
#endif
#define SAM_TC0_CCR (SAM_TC0_BASE+SAM_TCN_CCR_OFFSET)
#define SAM_TC0_CMR (SAM_TC0_BASE+SAM_TCN_CMR_OFFSET)
#if defined(CONFIG_ARCH_CHIP_SAM4S)
# define SAM_TC0_SMMR (SAM_TC0_BASE+SAM_TCN_SMMR_OFFSET)
#endif
#define SAM_TC0_CV (SAM_TC0_BASE+SAM_TCN_CV_OFFSET)
#define SAM_TC0_RA (SAM_TC0_BASE+SAM_TCN_RA_OFFSET)
#define SAM_TC0_RB (SAM_TC0_BASE+SAM_TCN_RB_OFFSET)
@ -103,9 +120,16 @@
#define SAM_TC0_IER (SAM_TC0_BASE+SAM_TCN_IER_OFFSET)
#define SAM_TC0_IDR (SAM_TC0_BASE+SAM_TCN_IDR_OFFSET)
#define SAM_TC0_IMR (SAM_TC0_BASE+SAM_TCN_IMR_OFFSET)
#if defined(CONFIG_ARCH_CHIP_SAM4S)
# define SAM_TC0_FMR (SAM_TC0_BASE+SAM_TCN_FMR_OFFSET)
# define SAM_TC0_WPMR (SAM_TC0_BASE+SAM_TCN_WPMR_OFFSET)
#endif
#define SAM_TC1_CCR (SAM_TC1_BASE+SAM_TCN_CCR_OFFSET)
#define SAM_TC1_CMR (SAM_TC1_BASE+SAM_TCN_CMR_OFFSET)
#if defined(CONFIG_ARCH_CHIP_SAM4S)
# define SAM_TC1_SMMR (SAM_TC1_BASE+SAM_TCN_SMMR_OFFSET)
#endif
#define SAM_TC1_CV (SAM_TC1_BASE+SAM_TCN_CV_OFFSET)
#define SAM_TC1_RA (SAM_TC1_BASE+SAM_TCN_RA_OFFSET)
#define SAM_TC1_RB (SAM_TC1_BASE+SAM_TCN_RB_OFFSET)
@ -114,9 +138,16 @@
#define SAM_TC1_IER (SAM_TC1_BASE+SAM_TCN_IER_OFFSET)
#define SAM_TC1_IDR (SAM_TC1_BASE+SAM_TCN_IDR_OFFSET)
#define SAM_TC1_IMR (SAM_TC1_BASE+SAM_TCN_IMR_OFFSET)
#if defined(CONFIG_ARCH_CHIP_SAM4S)
# define SAM_TC1_FMR (SAM_TC1_BASE+SAM_TCN_FMR_OFFSET)
# define SAM_TC1_WPMR (SAM_TC1_BASE+SAM_TCN_WPMR_OFFSET)
#endif
#define SAM_TC2_CCR (SAM_TC2_BASE+SAM_TCN_CCR_OFFSET)
#define SAM_TC2_CMR (SAM_TC2_BASE+SAM_TCN_CMR_OFFSET)
#if defined(CONFIG_ARCH_CHIP_SAM4S)
# define SAM_TC2_SMMR (SAM_TC2_BASE+SAM_TCN_SMMR_OFFSET)
#endif
#define SAM_TC2_CV (SAM_TC2_BASE+SAM_TCN_CV_OFFSET)
#define SAM_TC2_RA (SAM_TC2_BASE+SAM_TCN_RA_OFFSET)
#define SAM_TC2_RB (SAM_TC2_BASE+SAM_TCN_RB_OFFSET)
@ -125,6 +156,64 @@
#define SAM_TC2_IER (SAM_TC2_BASE+SAM_TCN_IER_OFFSET)
#define SAM_TC2_IDR (SAM_TC2_BASE+SAM_TCN_IDR_OFFSET)
#define SAM_TC2_IMR (SAM_TC2_BASE+SAM_TCN_IMR_OFFSET)
#if defined(CONFIG_ARCH_CHIP_SAM4S)
# define SAM_TC2_FMR (SAM_TC2_BASE+SAM_TCN_FMR_OFFSET)
# define SAM_TC2_WPMR (SAM_TC2_BASE+SAM_TCN_WPMR_OFFSET)
#endif
#define SAM_TC3_CCR (SAM_TC3_BASE+SAM_TCN_CCR_OFFSET)
#define SAM_TC3_CMR (SAM_TC3_BASE+SAM_TCN_CMR_OFFSET)
#if defined(CONFIG_ARCH_CHIP_SAM4S)
# define SAM_TC3_SMMR (SAM_TC3_BASE+SAM_TCN_SMMR_OFFSET)
#endif
#define SAM_TC3_CV (SAM_TC3_BASE+SAM_TCN_CV_OFFSET)
#define SAM_TC3_RA (SAM_TC3_BASE+SAM_TCN_RA_OFFSET)
#define SAM_TC3_RB (SAM_TC3_BASE+SAM_TCN_RB_OFFSET)
#define SAM_TC3_RC (SAM_TC3_BASE+SAM_TCN_RC_OFFSET)
#define SAM_TC3_SR (SAM_TC3_BASE+SAM_TCN_SR_OFFSET)
#define SAM_TC3_IER (SAM_TC3_BASE+SAM_TCN_IER_OFFSET)
#define SAM_TC3_IDR (SAM_TC3_BASE+SAM_TCN_IDR_OFFSET)
#define SAM_TC3_IMR (SAM_TC3_BASE+SAM_TCN_IMR_OFFSET)
#if defined(CONFIG_ARCH_CHIP_SAM4S)
# define SAM_TC3_FMR (SAM_TC3_BASE+SAM_TCN_FMR_OFFSET)
# define SAM_TC3_WPMR (SAM_TC3_BASE+SAM_TCN_WPMR_OFFSET)
#endif
#define SAM_TC4_CCR (SAM_TC4_BASE+SAM_TCN_CCR_OFFSET)
#define SAM_TC4_CMR (SAM_TC4_BASE+SAM_TCN_CMR_OFFSET)
#if defined(CONFIG_ARCH_CHIP_SAM4S)
# define SAM_TC4_SMMR (SAM_TC4_BASE+SAM_TCN_SMMR_OFFSET)
#endif
#define SAM_TC4_CV (SAM_TC4_BASE+SAM_TCN_CV_OFFSET)
#define SAM_TC4_RA (SAM_TC4_BASE+SAM_TCN_RA_OFFSET)
#define SAM_TC4_RB (SAM_TC4_BASE+SAM_TCN_RB_OFFSET)
#define SAM_TC4_RC (SAM_TC4_BASE+SAM_TCN_RC_OFFSET)
#define SAM_TC4_SR (SAM_TC4_BASE+SAM_TCN_SR_OFFSET)
#define SAM_TC4_IER (SAM_TC4_BASE+SAM_TCN_IER_OFFSET)
#define SAM_TC4_IDR (SAM_TC4_BASE+SAM_TCN_IDR_OFFSET)
#define SAM_TC4_IMR (SAM_TC4_BASE+SAM_TCN_IMR_OFFSET)
#if defined(CONFIG_ARCH_CHIP_SAM4S)
# define SAM_TC4_FMR (SAM_TC4_BASE+SAM_TCN_FMR_OFFSET)
# define SAM_TC4_WPMR (SAM_TC4_BASE+SAM_TCN_WPMR_OFFSET)
#endif
#define SAM_TC5_CCR (SAM_TC5_BASE+SAM_TCN_CCR_OFFSET)
#define SAM_TC5_CMR (SAM_TC5_BASE+SAM_TCN_CMR_OFFSET)
#if defined(CONFIG_ARCH_CHIP_SAM4S)
# define SAM_TC5_SMMR (SAM_TC5_BASE+SAM_TCN_SMMR_OFFSET)
#endif
#define SAM_TC5_CV (SAM_TC5_BASE+SAM_TCN_CV_OFFSET)
#define SAM_TC5_RA (SAM_TC5_BASE+SAM_TCN_RA_OFFSET)
#define SAM_TC5_RB (SAM_TC5_BASE+SAM_TCN_RB_OFFSET)
#define SAM_TC5_RC (SAM_TC5_BASE+SAM_TCN_RC_OFFSET)
#define SAM_TC5_SR (SAM_TC5_BASE+SAM_TCN_SR_OFFSET)
#define SAM_TC5_IER (SAM_TC5_BASE+SAM_TCN_IER_OFFSET)
#define SAM_TC5_IDR (SAM_TC5_BASE+SAM_TCN_IDR_OFFSET)
#define SAM_TC5_IMR (SAM_TC5_BASE+SAM_TCN_IMR_OFFSET)
#if defined(CONFIG_ARCH_CHIP_SAM4S)
# define SAM_TC5_FMR (SAM_TC5_BASE+SAM_TCN_FMR_OFFSET)
# define SAM_TC5_WPMR (SAM_TC5_BASE+SAM_TCN_WPMR_OFFSET)
#endif
/* Timer common registers */
@ -308,6 +397,12 @@
# define TCN_CMR_BSWTRG_CLEAR (2 << TCN_CMR_BSWTRG_SHIFT)
# define TCN_CMR_BSWTRG_TOGGLE (3 << TCN_CMR_BSWTRG_SHIFT)
/* Stepper Motor Mode Register */
#if defined(CONFIG_ARCH_CHIP_SAM4S)
# warning SAM4S not yet integrated
#endif
/* TC Counter Value Register */
#define TCN_CV_SHIFT (0) /* Bits 0-15: Counter Value */
@ -332,6 +427,18 @@
#define TCN_SR_MTIOA (1 << 17) /* Bit 17: TIOA Mirror (SR only) */
#define TCN_SR_MTIOB (1 << 18) /* Bit 18: TIOB Mirror (SR only)*/
/* Fault Mode Register */
#if defined(CONFIG_ARCH_CHIP_SAM4S)
# warning SAM4S not yet integrated
#endif
/* Write Protect Mode Register */
#if defined(CONFIG_ARCH_CHIP_SAM4S)
# warning SAM4S not yet integrated
#endif
/************************************************************************************************
* Public Types
************************************************************************************************/

9
arch/arm/src/sam34/chip/sam_twi.h
View file

@ -1,5 +1,6 @@
/****************************************************************************************
* arch/arm/src/sam34/chip/sam_twi.h
* Two-wire Interface (TWI) definitions for the SAM3U and SAM4S
*
* Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
@ -125,13 +126,13 @@
# define TWI_MMR_IADRSZ_3BYTE (2 << TWI_MMR_IADRSZ_SHIFT) /* Two-byte internal device address */
# define TWI_MMR_IADRSZ_3BYTE (3 << TWI_MMR_IADRSZ_SHIFT) /* Three-byte internal device address */
#define TWI_MMR_MREAD (1 << 12) /* Bit 12: Master Read Direction */
#define TWI_MMR_DADR_SHIFT (16) /* Bits 16-23: Device Address */
#define TWI_MMR_DADR_MASK (0xff << TWI_MMR_DADR_SHIFT)
#define TWI_MMR_DADR_SHIFT (16) /* Bits 16-22: Device Address */
#define TWI_MMR_DADR_MASK (0x7f << TWI_MMR_DADR_SHIFT)
/* TWI Slave Mode Register */
#define TWI_SMR_SADR_SHIFT (16) /* Bits 16-23: Slave Address */
#define TWI_SMR_SADR_MASK (0xff << TWI_SMR_SADR_SHIFT)
#define TWI_SMR_SADR_SHIFT (16) /* Bits 16-22: Slave Address */
#define TWI_SMR_SADR_MASK (0x7f << TWI_SMR_SADR_SHIFT)
/* TWI Internal Address Register */