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Add Basic support for BL602(UART timer CLIC)

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This commit is contained in:
Lei Chen 2020-12-17 19:04:46 +08:00 committed by Brennan Ashton
parent 673a4b5b39
commit 58bd873729
49 changed files with 17301 additions and 1 deletions
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11
arch/risc-v/Kconfig
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@ -44,6 +44,12 @@ config ARCH_CHIP_GAP8
GreenwavesTechnologies GAP8 features a 1+8-core RI5CY DSP-like
processor, which originally comes from the ETH PULP platform.
config ARCH_CHIP_BL602
bool "BouffaloLab BL602"
select ARCH_RV32IM
---help---
BouffaloLab BL602(rv32imfc)
config ARCH_CHIP_RISCV_CUSTOM
bool "Custom RISC-V chip"
select ARCH_CHIP_CUSTOM
@ -80,6 +86,7 @@ config ARCH_CHIP
default "litex" if ARCH_CHIP_LITEX
default "nr5m100" if ARCH_CHIP_NR5
default "gap8" if ARCH_CHIP_GAP8
default "bl602" if ARCH_CHIP_BL602
config NR5_MPU
bool "MPU support"
@ -112,5 +119,7 @@ endif
if ARCH_CHIP_GAP8
source arch/risc-v/src/gap8/Kconfig
endif
if ARCH_CHIP_BL602
source arch/risc-v/src/bl602/Kconfig
endif
endif

36
arch/risc-v/include/bl602/chip.h Normal file
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@ -0,0 +1,36 @@
/****************************************************************************
* arch/risc-v/include/bl602/chip.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_RISCV_INCLUDE_BL602_CHIP_H
#define __ARCH_RISCV_INCLUDE_BL602_CHIP_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <sys/types.h>
#include <stdint.h>
#include <stdbool.h>
#include <arch/irq.h>
#include "riscv_internal.h"
#endif /* __ARCH_RISCV_INCLUDE_BL602_CHIP_H */

242
arch/risc-v/include/bl602/irq.h Normal file
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@ -0,0 +1,242 @@
/****************************************************************************
* arch/risc-v/include/bl602/irq.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_RISCV_INCLUDE_BL602_IRQ_H
#define __ARCH_RISCV_INCLUDE_BL602_IRQ_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <arch/irq.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* CLINT Base Address */
#define CLIC_TIMER_ENABLE_ADDRESS (0x02800407)
/* In mstatus register */
#define MIE_MSIE (0x1 << 3) /* Machine Software Interrupt Enable */
/* Map RISC-V exception code to NuttX IRQ */
/* IRQ 0-15 : (exception:interrupt=0) */
#define BL602_IRQ_IAMISALIGNED (0) /* Instruction Address Misaligned */
#define BL602_IRQ_IAFAULT (1) /* Instruction Address Fault */
#define BL602_IRQ_IINSTRUCTION (2) /* Illegal Instruction */
#define BL602_IRQ_BPOINT (3) /* Break Point */
#define BL602_IRQ_LAMISALIGNED (4) /* Load Address Misaligned */
#define BL602_IRQ_LAFAULT (5) /* Load Access Fault */
#define BL602_IRQ_SAMISALIGNED (6) /* Store/AMO Address Misaligned */
#define BL602_IRQ_SAFAULT (7) /* Store/AMO Access Fault */
#define BL602_IRQ_ECALLU (8) /* Environment Call from U-mode */
/* 9-10: Reserved */
#define BL602_IRQ_ECALLM (11) /* Environment Call from M-mode */
/* 12-15: Reserved */
/* IRQ 16- : (async event:interrupt=1) */
#define BL602_IRQ_NUM_BASE (16)
#define BL602_IRQ_ASYNC (16)
#define BL602_IRQ_MSOFT (BL602_IRQ_ASYNC + 3) /* Machine Software Int */
#define BL602_IRQ_MTIMER (BL602_IRQ_ASYNC + 7) /* Machine Timer Int */
#define BL602_IRQ_MEXT (BL602_IRQ_ASYNC + 11) /* Machine External Int */
/* Machine Global External Interrupt */
#define BL602_IRQ_BMX_ERR \
(BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 0) /* BMX Error Interrupt */
#define BL602_IRQ_BMX_TO \
(BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 1) /* BMX Timeout Interrupt */
#define BL602_IRQ_L1C_BMX_ERR \
(BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 2) /* L1C BMX Error Interrupt */
#define BL602_IRQ_L1C_BMX_TO \
(BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 3) /* L1C BMX Timeout Interrupt */
#define BL602_IRQ_SEC_BMX_ERR \
(BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 4) /* SEC BMX Error Interrupt */
#define BL602_IRQ_RF_TOP_INT0 \
(BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 5) /* RF_TOP_INT0 Interrupt */
#define BL602_IRQ_RF_TOP_INT1 \
(BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 6) /* RF_TOP_INT1 Interrupt */
#define BL602_IRQ_SDIO \
(BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 7) /* SDIO Interrupt */
#define BL602_IRQ_DMA_BMX_ERR \
(BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 8) /* DMA BMX Error Interrupt */
#define BL602_IRQ_SEC_GMAC \
(BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 9) /* SEC_ENG_GMAC_INT Interrupt */
#define BL602_IRQ_SEC_CDET \
(BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 10) /* SEC_ENG_CDET_INT Interrupt */
#define BL602_IRQ_SEC_PKA \
(BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 11) /* SEC_ENG_PKA_INT Interrupt */
#define BL602_IRQ_SEC_TRNG \
(BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 12) /* SEC_ENG_TRNG_INT Interrupt */
#define BL602_IRQ_SEC_AES \
(BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 13) /* SEC_ENG_AES_INT Interrupt */
#define BL602_IRQ_SEC_SHA \
(BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 14) /* SEC_ENG_SHA_INT Interrupt */
#define BL602_IRQ_DMA_ALL \
(BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 15) /* DMA ALL Interrupt */
#define BL602_IRQ_RESERVED0 \
(BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 16) /* RESERVED Interrupt */
#define BL602_IRQ_RESERVED1 \
(BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 17) /* RESERVED Interrupt */
#define BL602_IRQ_RESERVED2 \
(BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 18) /* RESERVED Interrupt */
#define BL602_IRQ_IRTX_IRQn \
(BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 19) /* IR TX Interrupt */
#define BL602_IRQ_IRRX_IRQn \
(BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 20) /* IR RX Interrupt */
#define BL602_IRQ_RESERVED3 \
(BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 21) /* RESERVED Interrupt */
#define BL602_IRQ_RESERVED4 \
(BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 22) /* RESERVED Interrupt */
#define BL602_IRQ_SF_CTRL \
(BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 23) /* SF_CTRL Interrupt */
#define BL602_IRQ_RESERVED5 \
(BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 24) /* RESERVED Interrupt */
#define BL602_IRQ_GPADC_DMA \
(BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 25) /* GPADC_DMA Interrupt */
#define BL602_IRQ_EFUSE \
(BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 26) /* Efuse Interrupt */
#define BL602_IRQ_SPI \
(BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 27) /* SPI Interrupt */
#define BL602_IRQ_RESERVED6 \
(BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 28) /* RESERVED Interrupt */
#define BL602_IRQ_UART0 \
(BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 29) /* UART Interrupt */
#define BL602_IRQ_UART1 \
(BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 30) /* UART1 Interrupt */
#define BL602_IRQ_RESERVED7 \
(BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 31) /* RESERVED Interrupt */
#define BL602_IRQ_I2C \
(BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 32) /* I2C Interrupt */
#define BL602_IRQ_RESERVED8 \
(BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 33) /* RESERVED Interrupt */
#define BL602_IRQ_PWM \
(BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 34) /* PWM Interrupt */
#define BL602_IRQ_RESERVED9 \
(BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 35) /* RESERVED Interrupt */
#define BL602_IRQ_TIMER_CH0 \
(BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 36) /* Timer Channel 0 Interrupt */
#define BL602_IRQ_TIMER_CH1 \
(BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 37) /* Timer Channel 1 Interrupt */
#define BL602_IRQ_TIMER_WDT \
(BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 38) /* Timer Watch Dog Interrupt */
#define BL602_IRQ_RESERVED10 \
(BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 39) /* RESERVED Interrupt */
#define BL602_IRQ_RESERVED11 \
(BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 40) /* RESERVED Interrupt */
#define BL602_IRQ_RESERVED12 \
(BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 41) /* RESERVED Interrupt */
#define BL602_IRQ_RESERVED13 \
(BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 42) /* RESERVED Interrupt */
#define BL602_IRQ_RESERVED14 \
(BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 43) /* RESERVED Interrupt */
#define BL602_IRQ_GPIO_INT0 \
(BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 44) /* RESERVED Interrupt */
#define BL602_IRQ_RESERVED16 \
(BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 45) /* RESERVED Interrupt */
#define BL602_IRQ_RESERVED17 \
(BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 46) /* RESERVED Interrupt */
#define BL602_IRQ_RESERVED18 \
(BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 47) /* RESERVED Interrupt */
#define BL602_IRQ_RESERVED19 \
(BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 48) /* RESERVED Interrupt */
#define BL602_IRQ_RESERVED20 \
(BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 49) /* RESERVED Interrupt */
#define BL602_IRQ_PDS_WAKEUP \
(BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 50) /* PDS Wakeup Interrupt */
#define BL602_IRQ_HBN_OUT0 \
(BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 51) /* Hibernate out 0 Interrupt */
#define BL602_IRQ_HBN_OUT1 \
(BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 52) /* Hibernate out 1 Interrupt */
#define BL602_IRQ_BOR \
(BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 53) /* BOR Interrupt */
#define BL602_IRQ_WIFI \
(BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 54) /* WIFI To CPU Interrupt */
#define BL602_IRQ_BZ_PHY \
(BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 55) /* RESERVED Interrupt */
#define BL602_IRQ_BLE \
(BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 56) /* RESERVED Interrupt */
#define BL602_IRQ_MAC_TXRX_TIMER \
(BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + \
57) /* mac_int_tx_rx_timer Interrupt */
#define BL602_IRQ_MAC_TXRX_MISC \
(BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + \
58) /* mac_int_tx_rx_misc Interrupt */
#define BL602_IRQ_MAC_RX_TRG \
(BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + \
59) /* mac_int_rx_trigger Interrupt */
#define BL602_IRQ_MAC_TX_TRG \
(BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + \
60) /* mac_int_tx_trigger Interrupt */
#define BL602_IRQ_MAC_GEN \
(BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 61) /* mac_int_gen Interrupt */
#define BL602_IRQ_MAC_PORT_TRG \
(BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + \
62) /* mac_int_port_trigger Interrupt */
#define BL602_IRQ_WIFI_IPC_PUBLIC \
(BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 63) /* wifi IPC public Interrupt */
/* Total number of IRQs */
#define NR_IRQS (64 + 16)
/****************************************************************************
* Public Types
****************************************************************************/
#ifndef __ASSEMBLY__
/****************************************************************************
* Public Data
****************************************************************************/
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
EXTERN irqstate_t up_irq_save(void);
EXTERN void up_irq_restore(irqstate_t);
EXTERN irqstate_t up_irq_enable(void);
EXTERN void up_disable_irq(int irq);
EXTERN void up_enable_irq(int irq);
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_RISCV_INCLUDE_BL602_IRQ_H */

79
arch/risc-v/src/bl602/Kconfig Normal file
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@ -0,0 +1,79 @@
#
# For a description of the syntax of this configuration file,
# see the file kconfig-language.txt in the NuttX tools repository.
#
comment "BL602 Configuration Options"
menu "BL602 Peripheral Support"
config BL602_HAVE_UART0
bool
default y
select UART0_SERIALDRIVER
select ARCH_HAVE_SERIAL_TERMIOS
config BL602_UART0
bool "UART0"
default y
select ARCH_HAVE_UART0
config BL602_UART0_TX_PIN
int "UART0 tx pin num"
default 16
depends on BL602_UART0
config BL602_UART0_RX_PIN
int "UART0 rx pin num"
default 7
depends on BL602_UART0
config BL602_UART0_RTS_PIN
int "UART0 rts pin num"
default -1
depends on BL602_UART0
config BL602_UART0_CTS_PIN
int "UART0 cts pin num"
default -1
depends on BL602_UART0
config BL602_HAVE_UART1
bool
default y
select UART1_SERIALDRIVER
select ARCH_HAVE_SERIAL_TERMIOS
config BL602_UART1
bool "UART1"
default y
select ARCH_HAVE_UART1
config BL602_UART1_TX_PIN
int "UART1 tx pin num"
default 4
depends on BL602_UART1
config BL602_UART1_RX_PIN
int "UART1 rx pin num"
default 3
depends on BL602_UART1
config BL602_UART1_RTS_PIN
int "UART1 rts pin num"
default -1
depends on BL602_UART1
config BL602_UART1_CTS_PIN
int "UART1 cts pin num"
default -1
depends on BL602_UART1
config BL602_TIMER0
bool "TIMER0"
default y
config BL602_TIMER1
bool "TIMER1"
default y
endmenu

59
arch/risc-v/src/bl602/Make.defs Normal file
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@ -0,0 +1,59 @@
############################################################################
# arch/risc-v/src/bl602/Make.defs
#
# Licensed to the Apache Software Foundation (ASF) under one or more
# contributor license agreements. See the NOTICE file distributed with
# this work for additional information regarding copyright ownership. The
# ASF licenses this file to you under the Apache License, Version 2.0 (the
# "License"); you may not use this file except in compliance with the
# License. You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
# License for the specific language governing permissions and limitations
# under the License.
#
############################################################################
# Specify our HEAD assembly file. This will be linked as
# the first object file, so it will appear at address 0
HEAD_ASRC = bl602_vectors.S
# Specify our general Assembly files
CHIP_ASRCS = bl602_head.S riscv_syscall.S bl602_entry.S
# Specify C code within the common directory to be included
CMN_CSRCS += riscv_initialize.c riscv_swint.c
CMN_CSRCS += riscv_createstack.c riscv_exit.c
CMN_CSRCS += riscv_assert.c riscv_blocktask.c riscv_copystate.c riscv_initialstate.c
CMN_CSRCS += riscv_interruptcontext.c riscv_modifyreg32.c riscv_puts.c riscv_mdelay.c
CMN_CSRCS += riscv_releasepending.c riscv_reprioritizertr.c
CMN_CSRCS += riscv_releasestack.c riscv_stackframe.c bl602_schedulesigaction.c
CMN_CSRCS += riscv_sigdeliver.c riscv_udelay.c riscv_unblocktask.c riscv_usestack.c
ifeq ($(CONFIG_STACK_COLORATION),y)
CMN_CSRCS += riscv_checkstack.c
endif
ifeq ($(CONFIG_ARCH_HAVE_VFORK),y)
CMN_CSRCS += riscv_vfork.c
endif
# Specify our C code within this directory to be included
CHIP_CSRCS = bl602_allocateheap.c
CHIP_CSRCS += bl602_idle.c bl602_irq.c bl602_irq_dispatch.c
CHIP_CSRCS += bl602_serial.c bl602_lowputc.c
CHIP_CSRCS += bl602_start.c bl602_timerisr.c
ifeq ($(CONFIG_TIMER),y)
CHIP_CSRCS += bl602_tim.c bl602_tim_lowerhalf.c bl602_oneshot_lowerhalf.c
endif
CHIP_CSRCS += bl602_glb.c bl602_gpio.c bl602_hbn.c
# INCLUDES += ${shell $(INCDIR) "$(CC)" $(ARCH_SRCDIR)$(DELIM)chip$(DELIM)hardware}

65
arch/risc-v/src/bl602/bl602_allocateheap.c Normal file
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@ -0,0 +1,65 @@
/****************************************************************************
* arch/risc-v/src/bl602/bl602_allocateheap.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <arch/board/board.h>
#include "chip.h"
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: up_addregion
****************************************************************************/
void up_addregion(void)
{
}
/****************************************************************************
* Name: up_allocate_heap
*
* Description:
* This function will be called to dynamically set aside the heap region.
*
* For the kernel build (CONFIG_BUILD_KERNEL=y) with both kernel- and
* user-space heaps (CONFIG_MM_KERNEL_HEAP=y), this function provides the
* size of the unprotected, user-space heap.
*
* If a protected kernel-space heap is provided, the kernel heap must be
* allocated (and protected) by an analogous up_allocate_kheap().
*
****************************************************************************/
extern uint8_t _heap_start;
extern uint8_t _heap_size;
void up_allocate_heap(FAR void **heap_start, size_t *heap_size)
{
*heap_start = (FAR void *)&_heap_start;
*heap_size = (size_t)&_heap_size;
}

172
arch/risc-v/src/bl602/bl602_boot2.h Normal file
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@ -0,0 +1,172 @@
/****************************************************************************
* arch/risc-v/src/bl602/bl602_boot2.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_RISCV_SRC_BL602_HARDWARE_BL602_BOOT2_H
#define __ARCH_RISCV_SRC_BL602_HARDWARE_BL602_BOOT2_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <stdint.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Public Types
****************************************************************************/
#ifndef __ASSEMBLY__
/* Partition table error type definition */
enum pt_table_error_e
{
PT_ERROR_SUCCESS, /* Partition table error type:success */
PT_ERROR_TABLE_NOT_VALID, /* Partition table error type:entry not found */
PT_ERROR_ENTRY_NOT_FOUND, /* Partition table error type:entry not found */
PT_ERROR_ENTRY_UPDATE_FAIL, /* Partition table error type:entry update fail
*/
PT_ERROR_CRC32, /* Partition table error type:crc32 error */
PT_ERROR_PARAMETER, /* Partition table error type:input parameter error */
PT_ERROR_FALSH_READ, /* Partition table error type:flash read error */
PT_ERROR_FALSH_WRITE, /* Partition table error type:flash write error */
PT_ERROR_FALSH_ERASE /* Partition table error type:flash erase error */
};
/* Partition id type definition */
enum pt_table_id_e
{
PT_TABLE_ID_0, /* Partition table ID 0 */
PT_TABLE_ID_1, /* Partition table ID 1 */
PT_TABLE_ID_INVALID, /* Partition table ID invalid */
};
/* Partition id type definition */
enum pt_table_entry_type_e
{
PT_ENTRY_FW_CPU0, /* Partition entry type:CPU0 firmware */
PT_ENTRY_FW_CPU1, /* Partition entry type:CPU1 firmware */
PT_ENTRY_MAX = 16, /* Partition entry type:Max */
};
/* Partition table config definition */
struct pt_table_config_s
{
uint32_t magic_code; /* Partition table magic code */
uint16_t version; /* Partition table verdion */
uint16_t entry_cnt; /* Partition table entry count */
uint32_t age; /* Partition table age */
uint32_t crc32; /* Partition table CRC32 value */
};
/* Partition table entry config definition */
struct pt_table_entry_config_s
{
uint8_t type; /* Partition entry type */
uint8_t device; /* Partition entry device */
uint8_t active_index; /* Partition entry active index */
uint8_t name[9]; /* Partition entry name */
uint32_t address[2]; /* Partition entry start address */
uint32_t max_len[2]; /* Partition entry max length */
uint32_t len; /* Partition entry length */
uint32_t age; /* Partition entry age */
};
/* Partition table stuff config definition */
struct pt_table_stuff_config_s
{
struct pt_table_config_s pt_table; /* Partition table */
struct pt_table_entry_config_s
pt_entries[PT_ENTRY_MAX]; /* Partition entries */
uint32_t crc32; /* Partition entries crc32 */
};
/****************************************************************************
* Public Data
****************************************************************************/
#ifdef __cplusplus
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Inline Functions
****************************************************************************/
/****************************************************************************
* Name: <Inline function name>
*
* Description:
* Description of the operation of the inline function.
*
* Input Parameters:
* A list of input parameters, one-per-line, appears here along with a
* description of each input parameter.
*
* Returned Value:
* Description of the value returned by this function (if any),
* including an enumeration of all possible error values.
*
* Assumptions/Limitations:
* Anything else that one might need to know to use this function.
*
****************************************************************************/
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: <Global function name>
*
* Description:
* Description of the operation of the function.
*
* Input Parameters:
* A list of input parameters, one-per-line, appears here along with a
* description of each input parameter.
*
* Returned Value:
* Description of the value returned by this function (if any),
* including an enumeration of all possible error values.
*
* Assumptions/Limitations:
* Anything else that one might need to know to use this function.
*
****************************************************************************/
#undef EXTERN
#ifdef __cplusplus
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_RISCV_SRC_BL602_HARDWARE_BL602_BOOT2_H */

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/****************************************************************************
* arch/risc-v/src/bl602/bl602_config.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_RISCV_SRC_BL602_BL602_CONFIG_H
#define __ARCH_RISCV_SRC_BL602_BL602_CONFIG_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <arch/chip/chip.h>
#include <arch/board/board.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#undef HAVE_UART_DEVICE
#if defined(CONFIG_BL602_UART0) || defined(CONFIG_BL602_UART1)
#define HAVE_UART_DEVICE 1
#endif
#if defined(CONFIG_UART0_SERIAL_CONSOLE) && defined(CONFIG_BL602_UART0)
#undef CONFIG_UART1_SERIAL_CONSOLE
#define HAVE_SERIAL_CONSOLE 1
#elif defined(CONFIG_UART1_SERIAL_CONSOLE) && defined(CONFIG_BL602_UART1)
#undef CONFIG_UART0_SERIAL_CONSOLE
#define HAVE_SERIAL_CONSOLE 1
#else
#undef CONFIG_UART0_SERIAL_CONSOLE
#undef CONFIG_UART1_SERIAL_CONSOLE
#undef HAVE_SERIAL_CONSOLE
#endif
#endif /* __ARCH_RISCV_SRC_BL602_BL602_CONFIG_H */

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/****************************************************************************
* arch/risc-v/src/bl602/bl602_entry.S
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/* This is defined in sifive/platform.h, but that can't be included from
* assembly. */
#define CLINT_CTRL_ADDR 0x02000000
#define MSTATUS_FS 0x00006000
#define MSTATUS_MIE 0x00000008
.section .init
.globl bl602_start
.globl __start
.type bl602_start,@function
__start:
bl602_start:
.cfi_startproc
.cfi_undefined ra
.option push
.option norelax
/*disable IRQ*/
li t0, MSTATUS_MIE
csrc mstatus, t0
la gp, __global_pointer$
.option pop
la sp, _sp_main
#ifndef RUN_IN_RAM
/* Load boot2 partition address */
la a0, __boot2_pt_addr_src
la a1, __boot2_pt_addr_start
la a2, __boot2_pt_addr_end
bgeu a1, a2, 2f
1:
lw t0, (a0)
sw t0, (a1)
addi a0, a0, 4
addi a1, a1, 4
bltu a1, a2, 1b
2:
/* Load boot2 flashCfg address */
jal boot2_get_flash_addr
la a1, __boot2_flash_cfg_start
la a2, __boot2_flash_cfg_end
bgeu a1, a2, 2f
1:
lw t0, (a0)
sw t0, (a1)
addi a0, a0, 4
addi a1, a1, 4
bltu a1, a2, 1b
2:
#endif
/* Load data section */
la a0, _data_load
la a1, _data_run
la a2, _data_run_end
bgeu a1, a2, 2f
1:
lw t0, (a0)
sw t0, (a1)
addi a0, a0, 4
addi a1, a1, 4
bltu a1, a2, 1b
2:
/* Clear bss section */
la a0, __bss_start
la a1, __bss_end
bgeu a0, a1, 3f
1:
sw zero, (a0)
addi a0, a0, 4
bltu a0, a1, 1b
/* Clear bss section */
la a0, __wifi_bss_start
la a1, __wifi_bss_end
bgeu a0, a1, 3f
1:
sw zero, (a0)
addi a0, a0, 4
bltu a0, a1, 1b
3:
/* Call global constructors */
#if 0
la a0, __libc_fini_array
call atexit
call __libc_init_array
#endif
#ifndef __riscv_float_abi_soft
/* Enable FPU */
li t0, MSTATUS_FS
csrs mstatus, t0
csrr t1, mstatus
and t1, t1, t0
beqz t1, 1f
fssr x0
1:
#endif
#if defined(ENABLE_SMP)
smp_resume(t0, t1)
csrr a0, mhartid
bnez a0, 2f
#endif
auipc ra, 0
addi sp, sp, -16
#if __riscv_xlen == 32
sw ra, 8(sp)
#else
sd ra, 8(sp)
#endif
/* argc = argv = 0 */
li a0, 0
li a1, 0
call bfl_main
#if 0
tail exit
#endif
1:
j 1b
#if defined(ENABLE_SMP)
2:
la t0, trap_entry
csrw mtvec, t0
csrr a0, mhartid
la t1, _sp_main
slli t0, a0, 10
sub sp, t1, t0
auipc ra, 0
addi sp, sp, -16
#if __riscv_xlen == 32
sw ra, 8(sp)
#else
sd ra, 8(sp)
#endif
call secondary_main
tail exit
1:
j 1b
#endif
.cfi_endproc

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/****************************************************************************
* arch/risc-v/src/bl602/bl602_glb.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include "hardware/bl602_glb.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Private Types
****************************************************************************/
/****************************************************************************
* Private Function Prototypes
****************************************************************************/
/****************************************************************************
* Private Data
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Name: <Static function name>
*
* Description:
* Description of the operation of the static function.
*
* Input Parameters:
* A list of input parameters, one-per-line, appears here along with a
* description of each input parameter.
*
* Returned Value:
* Description of the value returned by this function (if any),
* including an enumeration of all possible error values.
*
* Assumptions/Limitations:
* Anything else that one might need to know to use this function.
*
****************************************************************************/
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: glb_uart_fun_sel
*
* Description:
* Select UART signal function.
*
* Input Parameters:
* sig: UART signal
* fun: UART function
*
* Returned Value:
* None
*
****************************************************************************/
void glb_uart_fun_sel(enum glb_uart_sig_e sig, enum glb_uart_sig_fun_e fun)
{
uint32_t sig_pos = 0;
uint32_t tmp_val = 0;
tmp_val = BL_RD_REG(GLB_BASE, GLB_UART_SIG_SEL_0);
sig_pos = (sig * 4);
/* Clear original val */
tmp_val = tmp_val & (~(0xf << sig_pos));
/* Set new value */
tmp_val = tmp_val | (fun << sig_pos);
BL_WR_REG(GLB_BASE, GLB_UART_SIG_SEL_0, tmp_val);
}
/****************************************************************************
* Name: glb_ahb_slave1_reset
*
* Description:
* Select UART signal function.
*
* Input Parameters:
* sig: UART signal
* fun: UART function
*
* Returned Value:
* None
*
****************************************************************************/
void glb_ahb_slave1_reset(enum bl_ahb_slave1_e slave1)
{
uint32_t tmp_val = 0;
tmp_val = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG1);
tmp_val &= (~(1 << slave1));
BL_WR_REG(GLB_BASE, GLB_SWRST_CFG1, tmp_val);
BL_DRV_DUMMY;
tmp_val = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG1);
tmp_val |= (1 << slave1);
BL_WR_REG(GLB_BASE, GLB_SWRST_CFG1, tmp_val);
BL_DRV_DUMMY;
tmp_val = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG1);
tmp_val &= (~(1 << slave1));
BL_WR_REG(GLB_BASE, GLB_SWRST_CFG1, tmp_val);
}

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/****************************************************************************
* arch/risc-v/src/bl602/bl602_gpio.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <stdint.h>
#include "hardware/bl602_gpio.h"
#include "hardware/bl602_glb.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Private Types
****************************************************************************/
/****************************************************************************
* Private Function Prototypes
****************************************************************************/
/****************************************************************************
* Private Data
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Name: <Static function name>
*
* Description:
* Description of the operation of the static function.
*
* Input Parameters:
* A list of input parameters, one-per-line, appears here along with a
* description of each input parameter.
*
* Returned Value:
* Description of the value returned by this function (if any),
* including an enumeration of all possible error values.
*
* Assumptions/Limitations:
* Anything else that one might need to know to use this function.
*
****************************************************************************/
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: gpio_init
*
* Description:
* Init a gpio pin.
*
* Input Parameters:
* cfg: gpio configuration
*
* Returned Value:
* Description of the value returned by this function (if any),
* including an enumeration of all possible error values.
*
* Assumptions/Limitations:
* Anything else that one might need to know to use this function.
*
****************************************************************************/
void gpio_init(struct gpio_cfg_s *cfg)
{
uint8_t gpio_pin = cfg->gpio_pin;
uint32_t *p_out;
uint32_t pos;
uint32_t tmp_out;
uint32_t tmp_val;
p_out = (uint32_t *)(GLB_BASE + GLB_GPIO_OUTPUT_EN_OFFSET +
((gpio_pin >> 5) << 2));
pos = gpio_pin % 32;
tmp_out = *p_out;
/* Disable output anyway */
tmp_out &= (~(1 << pos));
*p_out = tmp_out;
tmp_val = BL_RD_WORD(GLB_BASE + GLB_GPIO_OFFSET + gpio_pin / 2 * 4);
if (gpio_pin % 2 == 0)
{
/* Set input or output */
if (cfg->gpio_mode == GPIO_MODE_OUTPUT)
{
tmp_val = BL_CLR_REG_BIT(tmp_val, GLB_REG_GPIO_0_IE);
tmp_out |= (1 << pos);
}
else
{
tmp_val = BL_SET_REG_BIT(tmp_val, GLB_REG_GPIO_0_IE);
}
/* Set pull up or down */
tmp_val = BL_CLR_REG_BIT(tmp_val, GLB_REG_GPIO_0_PU);
tmp_val = BL_CLR_REG_BIT(tmp_val, GLB_REG_GPIO_0_PD);
if (cfg->pull_type == GPIO_PULL_UP)
{
tmp_val = BL_SET_REG_BIT(tmp_val, GLB_REG_GPIO_0_PU);
}
else if (cfg->pull_type == GPIO_PULL_DOWN)
{
tmp_val = BL_SET_REG_BIT(tmp_val, GLB_REG_GPIO_0_PD);
}
tmp_val = BL_SET_REG_BITS_VAL(tmp_val, GLB_REG_GPIO_0_DRV, cfg->drive);
tmp_val =
BL_SET_REG_BITS_VAL(tmp_val, GLB_REG_GPIO_0_SMT, cfg->smt_ctrl);
tmp_val =
BL_SET_REG_BITS_VAL(tmp_val, GLB_REG_GPIO_0_FUNC_SEL, cfg->gpio_fun);
}
else
{
/* Set input or output */
if (cfg->gpio_mode == GPIO_MODE_OUTPUT)
{
tmp_val = BL_CLR_REG_BIT(tmp_val, GLB_REG_GPIO_1_IE);
tmp_out |= (1 << pos);
}
else
{
tmp_val = BL_SET_REG_BIT(tmp_val, GLB_REG_GPIO_1_IE);
}
/* Set pull up or down */
tmp_val = BL_CLR_REG_BIT(tmp_val, GLB_REG_GPIO_1_PU);
tmp_val = BL_CLR_REG_BIT(tmp_val, GLB_REG_GPIO_1_PD);
if (cfg->pull_type == GPIO_PULL_UP)
{
tmp_val = BL_SET_REG_BIT(tmp_val, GLB_REG_GPIO_1_PU);
}
else if (cfg->pull_type == GPIO_PULL_DOWN)
{
tmp_val = BL_SET_REG_BIT(tmp_val, GLB_REG_GPIO_1_PD);
}
tmp_val = BL_SET_REG_BITS_VAL(tmp_val, GLB_REG_GPIO_1_DRV, cfg->drive);
tmp_val =
BL_SET_REG_BITS_VAL(tmp_val, GLB_REG_GPIO_1_SMT, cfg->smt_ctrl);
tmp_val =
BL_SET_REG_BITS_VAL(tmp_val, GLB_REG_GPIO_1_FUNC_SEL, cfg->gpio_fun);
}
BL_WR_WORD(GLB_BASE + GLB_GPIO_OFFSET + gpio_pin / 2 * 4, tmp_val);
*p_out = tmp_out;
}

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/****************************************************************************
* <Relative path to the file>
* <Optional one line file description>
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include "hardware/bl602_hbn.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Private Types
****************************************************************************/
/****************************************************************************
* Private Function Prototypes
****************************************************************************/
/****************************************************************************
* Private Data
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Name: <Static function name>
*
* Description:
* Description of the operation of the static function.
*
* Input Parameters:
* A list of input parameters, one-per-line, appears here along with a
* description of each input parameter.
*
* Returned Value:
* Description of the value returned by this function (if any),
* including an enumeration of all possible error values.
*
* Assumptions/Limitations:
* Anything else that one might need to know to use this function.
*
****************************************************************************/
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: hbn_set_uart_clk_sel
*
* Description:
* Select uart clock source.
*
* Input Parameters:
* clk_sel: uart clock type selection
*
* Returned Value:
* Description of the value returned by this function (if any),
* including an enumeration of all possible error values.
*
* Assumptions/Limitations:
* Anything else that one might need to know to use this function.
*
****************************************************************************/
void hbn_set_uart_clk_sel(enum hbn_uart_clk_type_e clk_sel)
{
uint32_t tmp_val;
tmp_val = BL_RD_REG(HBN_BASE, HBN_GLB);
tmp_val = BL_SET_REG_BITS_VAL(tmp_val, HBN_UART_CLK_SEL, clk_sel);
BL_WR_REG(HBN_BASE, HBN_GLB, tmp_val);
}

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arch/risc-v/src/bl602/bl602_head.S Normal file
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/****************************************************************************
* arch/risc-v/src/bl602/bl602_head.S
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <arch/rv32im/irq.h>
/****************************************************************************
* Public Symbols
****************************************************************************/
.global exception_common
/****************************************************************************
* Name: exception_common
****************************************************************************/
.align 8
exception_common:
addi sp, sp, -XCPTCONTEXT_SIZE
sw x1, 1*4(sp) /* ra */
sw x3, 3*4(sp) /* gp */
sw x4, 4*4(sp) /* tp */
sw x5, 5*4(sp) /* t0 */
sw x6, 6*4(sp) /* t1 */
sw x7, 7*4(sp) /* t2 */
sw x8, 8*4(sp) /* s0 */
sw x9, 9*4(sp) /* s1 */
sw x10, 10*4(sp) /* a0 */
sw x11, 11*4(sp) /* a1 */
sw x12, 12*4(sp) /* a2 */
sw x13, 13*4(sp) /* a3 */
sw x14, 14*4(sp) /* a4 */
sw x15, 15*4(sp) /* a5 */
sw x16, 16*4(sp) /* a6 */
sw x17, 17*4(sp) /* a7 */
sw x18, 18*4(sp) /* s2 */
sw x19, 19*4(sp) /* s3 */
sw x20, 20*4(sp) /* s4 */
sw x21, 21*4(sp) /* s5 */
sw x22, 22*4(sp) /* s6 */
sw x23, 23*4(sp) /* s7 */
sw x24, 24*4(sp) /* s8 */
sw x25, 25*4(sp) /* s9 */
sw x26, 26*4(sp) /* s10 */
sw x27, 27*4(sp) /* s11 */
sw x28, 28*4(sp) /* t3 */
sw x29, 29*4(sp) /* t4 */
sw x30, 30*4(sp) /* t5 */
sw x31, 31*4(sp) /* t6 */
csrr s0, mstatus
sw s0, 32*4(sp) /* mstatus */
addi s0, sp, XCPTCONTEXT_SIZE
sw s0, 2*4(sp) /* original SP */
/* Setup arg0(exception cause), arg1(context) */
csrr a0, mcause /* exception cause */
csrr s0, mepc
sw s0, 0(sp) /* exception PC */
mv a1, sp /* context = sp */
#if CONFIG_ARCH_INTERRUPTSTACK > 3
/* Switch to interrupt stack */
lui sp, %hi(g_intstackbase)
addi sp, sp, %lo(g_intstackbase)
#endif
/* Call interrupt handler in C */
jal x1, bl602_dispatch_irq
/* If context switch is needed, return a new sp */
mv sp, a0
lw s0, 0(sp) /* restore mepc */
csrw mepc, s0
lw s0, 32*4(sp) /* restore mstatus */
csrw mstatus, s0
lw x3, 3*4(sp) /* gp */
lw x4, 4*4(sp) /* tp */
lw x5, 5*4(sp) /* t0 */
lw x6, 6*4(sp) /* t1 */
lw x7, 7*4(sp) /* t2 */
lw x8, 8*4(sp) /* s0 */
lw x9, 9*4(sp) /* s1 */
lw x10, 10*4(sp) /* a0 */
lw x11, 11*4(sp) /* a1 */
lw x12, 12*4(sp) /* a2 */
lw x13, 13*4(sp) /* a3 */
lw x14, 14*4(sp) /* a4 */
lw x15, 15*4(sp) /* a5 */
lw x16, 16*4(sp) /* a6 */
lw x17, 17*4(sp) /* a7 */
lw x18, 18*4(sp) /* s2 */
lw x19, 19*4(sp) /* s3 */
lw x20, 20*4(sp) /* s4 */
lw x21, 21*4(sp) /* s5 */
lw x22, 22*4(sp) /* s6 */
lw x23, 23*4(sp) /* s7 */
lw x24, 24*4(sp) /* s8 */
lw x25, 25*4(sp) /* s9 */
lw x26, 26*4(sp) /* s10 */
lw x27, 27*4(sp) /* s11 */
lw x28, 28*4(sp) /* t3 */
lw x29, 29*4(sp) /* t4 */
lw x30, 30*4(sp) /* t5 */
lw x31, 31*4(sp) /* t6 */
lw x1, 1*4(sp) /* ra */
lw sp, 2*4(sp) /* restore original sp */
/* Return from Machine Interrupt */
mret
/************************************************************************************
* Name: g_intstackalloc and g_intstackbase
************************************************************************************/
#if CONFIG_ARCH_INTERRUPTSTACK > 3
.bss
.align 4
.global g_intstackalloc
.global g_intstackbase
.type g_intstackalloc, object
.type g_intstackbase, object
g_intstackalloc:
.skip ((CONFIG_ARCH_INTERRUPTSTACK & ~3))
g_intstackbase:
.skip 4
.size g_intstackbase, 4
.size g_intstackalloc, (CONFIG_ARCH_INTERRUPTSTACK & ~3)
#endif

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/****************************************************************************
* arch/risc-v/src/bl602/bl602_idle.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <nuttx/irq.h>
#include <nuttx/arch.h>
#include <nuttx/board.h>
#include <arch/board/board.h>
#include "riscv_internal.h"
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: up_idle
*
* Description:
* up_idle() is the logic that will be executed when their is no other
* ready-to-run task. This is processor idle time and will continue until
* some interrupt occurs to cause a context switch from the idle task.
*
* Processing in this state may be processor-specific. e.g., this is where
* power management operations might be performed.
*
****************************************************************************/
void up_idle(void)
{
#if defined(CONFIG_SUPPRESS_INTERRUPTS) || defined(CONFIG_SUPPRESS_TIMER_INTS)
/* If the system is idle and there are no timer interrupts, then process
* "fake" timer interrupts. Hopefully, something will wake up.
*/
nxsched_process_timer();
#else
/* This would be an appropriate place to put some MCU-specific logic to
* sleep in a reduced power mode until an interrupt occurs to save power
*/
asm("WFI");
#endif
}

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/****************************************************************************
* arch/risc-v/src/bl602/bl602_irq.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <stdio.h>
#include <debug.h>
#include <nuttx/arch.h>
#include <nuttx/board.h>
#include <arch/irq.h>
#include <arch/board/board.h>
#include "riscv_internal.h"
#include "riscv_arch.h"
#include "hardware/clic.h"
#include "chip.h"
void bl_irq_enable(unsigned int source)
{
*(volatile uint8_t *)(CLIC_HART0_ADDR + CLIC_INTIE + source) = 1;
}
void bl_irq_disable(unsigned int source)
{
*(volatile uint8_t *)(CLIC_HART0_ADDR + CLIC_INTIE + source) = 0;
}
void bl_irq_pending_set(unsigned int source)
{
*(volatile uint8_t *)(CLIC_HART0_ADDR + CLIC_INTIP + source) = 1;
}
void bl_irq_pending_clear(unsigned int source)
{
*(volatile uint8_t *)(CLIC_HART0_ADDR + CLIC_INTIP + source) = 0;
}
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: up_irqinitialize
****************************************************************************/
void up_irqinitialize(void)
{
/* Disable Machine interrupts */
up_irq_save();
#if defined(CONFIG_STACK_COLORATION) && CONFIG_ARCH_INTERRUPTSTACK > 3
/* Colorize the interrupt stack for debug purposes */
size_t intstack_size = (CONFIG_ARCH_INTERRUPTSTACK & ~3);
up_stack_color((FAR void *)((uintptr_t)&g_intstackbase - intstack_size),
intstack_size);
#endif
/* currents_regs is non-NULL only while processing an interrupt */
g_current_regs = NULL;
/* Attach the ecall interrupt handler */
irq_attach(BL602_IRQ_ECALLM, up_swint, NULL);
#ifndef CONFIG_SUPPRESS_INTERRUPTS
/* And finally, enable interrupts */
up_irq_enable();
#endif
}
/****************************************************************************
* Name: up_disable_irq
*
* Description:
* Disable the IRQ specified by 'irq'
*
****************************************************************************/
void up_disable_irq(int irq)
{
uint32_t oldstat;
if (irq == BL602_IRQ_MSOFT)
{
/* Read mstatus & clear machine software interrupt enable in mie */
asm volatile("csrrc %0, mie, %1" : "=r"(oldstat) : "r"(MIE_MSIE));
}
else if (irq == BL602_IRQ_MTIMER)
{
*(volatile uint8_t *)CLIC_TIMER_ENABLE_ADDRESS = 0;
/* Read mstatus & clear machine timer interrupt enable in mie */
asm volatile("csrrc %0, mie, %1" : "=r"(oldstat) : "r"(MIE_MTIE));
}
else
{
ASSERT(irq < 64 + 16 + BL602_IRQ_ASYNC);
bl_irq_disable(irq - BL602_IRQ_ASYNC);
}
}
/****************************************************************************
* Name: up_enable_irq
*
* Description:
* Enable the IRQ specified by 'irq'
*
****************************************************************************/
void up_enable_irq(int irq)
{
uint32_t oldstat;
if (irq == BL602_IRQ_MSOFT)
{
/* Read mstatus & set machine software interrupt enable in mie */
asm volatile("csrrs %0, mie, %1" : "=r"(oldstat) : "r"(MIE_MSIE));
}
else if (irq == BL602_IRQ_MTIMER)
{
*(volatile uint8_t *)CLIC_TIMER_ENABLE_ADDRESS = 1;
/* Read mstatus & set machine timer interrupt enable in mie */
asm volatile("csrrs %0, mie, %1"
: "=r"(oldstat)
: "r"(MIE_MTIE | 0x1 << 11));
}
else
{
ASSERT(irq < 64 + 16 + BL602_IRQ_ASYNC);
bl_irq_enable(irq - BL602_IRQ_ASYNC);
}
}
/****************************************************************************
* Name: up_get_newintctx
*
* Description:
* Return initial mstatus when a task is created.
*
****************************************************************************/
uint32_t up_get_newintctx(void)
{
/* Set machine previous privilege mode to machine mode.
* Also set machine previous interrupt enable
*/
return (MSTATUS_MPPM | MSTATUS_MPIE);
}
/****************************************************************************
* Name: up_ack_irq
*
* Description:
* Acknowledge the IRQ
*
****************************************************************************/
void up_ack_irq(int irq)
{
}
/****************************************************************************
* Name: up_irq_save
*
* Description:
* Return the current interrupt state and disable interrupts
*
****************************************************************************/
irqstate_t up_irq_save(void)
{
uint32_t oldstat;
/* Read mstatus & clear machine interrupt enable (MIE) in mstatus */
asm volatile("csrrc %0, mstatus, %1" : "=r"(oldstat) : "r"(MSTATUS_MIE));
return oldstat;
}
/****************************************************************************
* Name: up_irq_restore
*
* Description:
* Restore previous IRQ mask state
*
****************************************************************************/
void up_irq_restore(irqstate_t flags)
{
/* Write flags to mstatus */
asm volatile("csrw mstatus, %0"
: /* no output */
: "r"(flags));
}
/****************************************************************************
* Name: up_irq_enable
*
* Description:
* Return the current interrupt state and enable interrupts
*
****************************************************************************/
irqstate_t up_irq_enable(void)
{
uint32_t oldstat;
/* Enable MEIE (machine external interrupt enable) */
asm volatile("csrrs %0, mie, %1" : "=r"(oldstat) : "r"(MIE_MEIE));
/* Read mstatus & set machine interrupt enable (MIE) in mstatus */
asm volatile("csrrs %0, mstatus, %1" : "=r"(oldstat) : "r"(MSTATUS_MIE));
return oldstat;
}

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/****************************************************************************
* arch/risc-v/src/bl602/bl602_irq_dispatch.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <assert.h>
#include <nuttx/irq.h>
#include <nuttx/arch.h>
#include <nuttx/board.h>
#include <arch/board/board.h>
#include "riscv_arch.h"
#include "riscv_internal.h"
#include "chip.h"
/****************************************************************************
* Public Data
****************************************************************************/
volatile uint32_t *g_current_regs;
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* bl602_dispatch_irq
****************************************************************************/
void *bl602_dispatch_irq(uint32_t vector, uint32_t *regs)
{
uint32_t irq = vector & 0x3ff; /* E24 [9:0] */
uint32_t *mepc = regs;
/* If current is interrupt */
if (vector & 0x80000000u)
{
irq += BL602_IRQ_ASYNC;
}
/* NOTE: In case of ecall, we need to adjust mepc in the context */
if (BL602_IRQ_ECALLM == irq)
{
*mepc += 4;
}
/* Acknowledge the interrupt */
up_ack_irq(irq);
#ifdef CONFIG_SUPPRESS_INTERRUPTS
PANIC();
#else
/* Current regs non-zero indicates that we are processing an interrupt;
* g_current_regs is also used to manage interrupt level context switches.
*
* Nested interrupts are not supported
*/
DEBUGASSERT(g_current_regs == NULL);
g_current_regs = regs;
/* Deliver the IRQ */
irq_dispatch(irq, regs);
#endif
/* If a context switch occurred while processing the interrupt then
* g_current_regs may have change value. If we return any value different
* from the input regs, then the lower level will know that a context
* switch occurred during interrupt processing.
*/
regs = (uint32_t *)g_current_regs;
g_current_regs = NULL;
return regs;
}

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/****************************************************************************
* boards/risc-v/bl602/evb/src/bl602_lowputc.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <sys/types.h>
#include <stdint.h>
#include <stdbool.h>
#include <unistd.h>
#include <string.h>
#include <errno.h>
#include <debug.h>
#include <nuttx/irq.h>
#include <nuttx/serial/serial.h>
#include <arch/board/board.h>
#include "hardware/bl602_gpio.h"
#include "hardware/bl602_glb.h"
#include "hardware/bl602_hbn.h"
#include "hardware/bl602_uart.h"
#include "bl602_lowputc.h"
#include "riscv_arch.h"
#include "riscv_internal.h"
#include "bl602_config.h"
#include "chip.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Select UART parameters for the selected console */
#ifdef HAVE_SERIAL_CONSOLE
#if defined(CONFIG_UART0_SERIAL_CONSOLE)
#define BL602_CONSOLE_IDX 0
#define BL602_CONSOLE_BASE UART0_BASE
#define BL602_CONSOLE_BAUD CONFIG_UART0_BAUD
#define BL602_CONSOLE_BITS CONFIG_UART0_BITS
#define BL602_CONSOLE_PARITY CONFIG_UART0_PARITY
#define BL602_CONSOLE_2STOP CONFIG_UART0_2STOP
#ifdef UART0_IFLOWCONTROL
#define BL602_CONSOLE_IFLOWCTL UART0_IFLOWCONTROL
#else
#define BL602_CONSOLE_IFLOWCTL 0
#endif
#ifdef UART0_OFLOWCONTROL
#define BL602_CONSOLE_OFLOWCTL UART0_OFLOWCONTROL
#else
#define BL602_CONSOLE_OFLOWCTL 0
#endif
#define BL602_CONSOLE_TX_PIN CONFIG_BL602_UART0_TX_PIN
#define BL602_CONSOLE_RX_PIN CONFIG_BL602_UART0_RX_PIN
#define BL602_CONSOLE_RTS_PIN CONFIG_BL602_UART0_RTS_PIN
#define BL602_CONSOLE_CTS_PIN CONFIG_BL602_UART0_CTS_PIN
#define HAVE_UART
#elif defined(CONFIG_UART1_SERIAL_CONSOLE)
#define BL602_CONSOLE_IDX 1
#define BL602_CONSOLE_BASE UART1_BASE
#define BL602_CONSOLE_BAUD CONFIG_UART1_BAUD
#define BL602_CONSOLE_BITS CONFIG_UART1_BITS
#define BL602_CONSOLE_PARITY CONFIG_UART1_PARITY
#define BL602_CONSOLE_2STOP CONFIG_UART1_2STOP
#ifdef UART1_IFLOWCONTROL
#define BL602_CONSOLE_IFLOWCTL UART1_IFLOWCONTROL
#else
#define BL602_CONSOLE_IFLOWCTL 0
#endif
#ifdef UART1_OFLOWCONTROL
#define BL602_CONSOLE_OFLOWCTL UART1_OFLOWCONTROL
#else
#define BL602_CONSOLE_OFLOWCTL 0
#endif
#define BL602_CONSOLE_TX_PIN CONFIG_BL602_UART1_TX_PIN
#define BL602_CONSOLE_RX_PIN CONFIG_BL602_UART1_RX_PIN
#define BL602_CONSOLE_RTS_PIN CONFIG_BL602_UART1_RTS_PIN
#define BL602_CONSOLE_CTS_PIN CONFIG_BL602_UART1_CTS_PIN
#define HAVE_UART
#endif
#endif /* HAVE_CONSOLE */
#define _BL602_UART_CLOCK (160 * 1000 * 1000UL) /* UART clock */
/****************************************************************************
* Private Data
****************************************************************************/
#ifdef HAVE_SERIAL_CONSOLE
static const struct uart_config_s g_bl602_console_config =
{
.idx = BL602_CONSOLE_IDX,
.baud = BL602_CONSOLE_BAUD,
.parity = BL602_CONSOLE_PARITY,
.data_bits = BL602_CONSOLE_BITS,
.stop_bits = BL602_CONSOLE_2STOP,
#ifdef BL602_CONSOLE_IFLOWCTL
.iflow_ctl = BL602_CONSOLE_IFLOWCTL,
#else
.iflow_ctl = 0,
#endif
#ifdef BL602_CONSOLE_OFLOWCTL
.oflow_ctl = BL602_CONSOLE_OFLOWCTL,
#else
.oflow_ctl = 0,
#endif
.tx_pin = BL602_CONSOLE_TX_PIN,
.rx_pin = BL602_CONSOLE_RX_PIN,
.rts_pin = BL602_CONSOLE_RTS_PIN,
.cts_pin = BL602_CONSOLE_CTS_PIN,
};
#endif /* HAVE_SERIAL_CONSOLE */
/****************************************************************************
* Private Functions
****************************************************************************/
static void uart_gpio_init(uint8_t id,
uint8_t tx_pin,
uint8_t rx_pin,
uint8_t cts_pin,
uint8_t rts_pin)
{
struct gpio_cfg_s cfg;
enum glb_uart_sig_fun_e tx_sigfun;
enum glb_uart_sig_fun_e rx_sigfun;
cfg.drive = 1;
cfg.smt_ctrl = 1;
cfg.gpio_fun = 7;
cfg.gpio_pin = rx_pin;
cfg.gpio_mode = GPIO_MODE_AF;
cfg.pull_type = GPIO_PULL_UP;
gpio_init(&cfg);
cfg.gpio_pin = tx_pin;
cfg.gpio_mode = GPIO_MODE_AF;
cfg.pull_type = GPIO_PULL_UP;
gpio_init(&cfg);
/* select uart gpio function */
if (id == 0)
{
tx_sigfun = GLB_UART_SIG_FUN_UART0_TXD;
rx_sigfun = GLB_UART_SIG_FUN_UART0_RXD;
}
else
{
tx_sigfun = GLB_UART_SIG_FUN_UART1_TXD;
rx_sigfun = GLB_UART_SIG_FUN_UART1_RXD;
}
glb_uart_fun_sel(tx_pin % 8, tx_sigfun);
glb_uart_fun_sel(rx_pin % 8, rx_sigfun);
}
static void bl602_enable_uart_clk(uint8_t enable,
enum hbn_uart_clk_type_e clk_sel,
uint8_t div)
{
uint32_t tmp_val;
/* disable UART clock first */
tmp_val = BL_RD_REG(GLB_BASE, GLB_CLK_CFG2);
tmp_val = BL_CLR_REG_BIT(tmp_val, GLB_UART_CLK_EN);
BL_WR_REG(GLB_BASE, GLB_CLK_CFG2, tmp_val);
/* Set div */
tmp_val = BL_RD_REG(GLB_BASE, GLB_CLK_CFG2);
tmp_val = BL_SET_REG_BITS_VAL(tmp_val, GLB_UART_CLK_DIV, div);
BL_WR_REG(GLB_BASE, GLB_CLK_CFG2, tmp_val);
/* Select clock source for uart */
hbn_set_uart_clk_sel(clk_sel);
/* Set enable or disable */
tmp_val = BL_RD_REG(GLB_BASE, GLB_CLK_CFG2);
if (enable)
{
tmp_val = BL_SET_REG_BIT(tmp_val, GLB_UART_CLK_EN);
}
else
{
tmp_val = BL_CLR_REG_BIT(tmp_val, GLB_UART_CLK_EN);
}
BL_WR_REG(GLB_BASE, GLB_CLK_CFG2, tmp_val);
}
/****************************************************************************
* Public Functions
****************************************************************************/
void bl602_uart_configure(uint32_t uartbase,
const struct uart_config_s *config)
{
uint32_t tmp_val;
uint32_t div = 0;
uint32_t fraction = 0;
uint32_t tmp_tx_cfg = 0;
uint32_t tmp_rx_cfg = 0;
enum uart_databits_e data_bits;
enum uart_stopbits_e stop_bits;
bl602_enable_uart_clk(1, HBN_UART_CLK_160M, 3);
uart_gpio_init(config->idx,
config->tx_pin,
config->rx_pin,
config->cts_pin,
config->rts_pin);
/* Disable all interrupt */
tmp_val = BL_RD_REG(uartbase, UART_INT_MASK);
tmp_val |= 0xff;
BL_WR_REG(uartbase, UART_INT_MASK, tmp_val);
/* Disable uart before config */
tmp_val = BL_RD_REG(uartbase, UART_UTX_CONFIG);
BL_WR_REG(
uartbase, UART_UTX_CONFIG, BL_CLR_REG_BIT(tmp_val, UART_CR_UTX_EN));
tmp_val = BL_RD_REG(uartbase, UART_URX_CONFIG);
BL_WR_REG(
uartbase, UART_URX_CONFIG, BL_CLR_REG_BIT(tmp_val, UART_CR_URX_EN));
/* cal the baud rate divisor */
fraction = (_BL602_UART_CLOCK / (3 + 1)) * 10 / config->baud % 10;
div = (_BL602_UART_CLOCK / (3 + 1)) / config->baud;
if (fraction >= 5)
{
++div;
}
/* set the baud rate register value */
BL_WR_REG(
uartbase, UART_BIT_PRD, ((div - 1) << 0x10) | ((div - 1) & 0xffff));
/* configure parity type */
tmp_tx_cfg = BL_RD_REG(uartbase, UART_UTX_CONFIG);
tmp_rx_cfg = BL_RD_REG(uartbase, UART_URX_CONFIG);
switch (config->parity)
{
case UART_PARITY_NONE:
tmp_tx_cfg = BL_CLR_REG_BIT(tmp_tx_cfg, UART_CR_UTX_PRT_EN);
tmp_rx_cfg = BL_CLR_REG_BIT(tmp_rx_cfg, UART_CR_URX_PRT_EN);
break;
case UART_PARITY_ODD:
tmp_tx_cfg = BL_SET_REG_BIT(tmp_tx_cfg, UART_CR_UTX_PRT_EN);
tmp_tx_cfg = BL_SET_REG_BIT(tmp_tx_cfg, UART_CR_UTX_PRT_SEL);
tmp_rx_cfg = BL_SET_REG_BIT(tmp_rx_cfg, UART_CR_URX_PRT_EN);
tmp_rx_cfg = BL_SET_REG_BIT(tmp_rx_cfg, UART_CR_URX_PRT_SEL);
break;
case UART_PARITY_EVEN:
tmp_tx_cfg = BL_SET_REG_BIT(tmp_tx_cfg, UART_CR_UTX_PRT_EN);
tmp_tx_cfg = BL_CLR_REG_BIT(tmp_tx_cfg, UART_CR_UTX_PRT_SEL);
tmp_rx_cfg = BL_SET_REG_BIT(tmp_rx_cfg, UART_CR_URX_PRT_EN);
tmp_rx_cfg = BL_CLR_REG_BIT(tmp_rx_cfg, UART_CR_URX_PRT_SEL);
break;
default:
break;
}
if (config->data_bits == 5)
{
data_bits = UART_DATABITS_5;
}
else if (config->data_bits == 6)
{
data_bits = UART_DATABITS_6;
}
else if (config->data_bits == 7)
{
data_bits = UART_DATABITS_7;
}
else
{
data_bits = UART_DATABITS_8;
}
if (config->stop_bits == 1)
{
stop_bits = UART_STOPBITS_2;
}
else
{
stop_bits = UART_STOPBITS_1;
}
/* Configure data bits */
tmp_tx_cfg =
BL_SET_REG_BITS_VAL(tmp_tx_cfg, UART_CR_UTX_BIT_CNT_D, (data_bits + 4));
tmp_rx_cfg =
BL_SET_REG_BITS_VAL(tmp_rx_cfg, UART_CR_URX_BIT_CNT_D, (data_bits + 4));
/* Configure tx stop bits */
tmp_tx_cfg =
BL_SET_REG_BITS_VAL(tmp_tx_cfg, UART_CR_UTX_BIT_CNT_P, (stop_bits + 1));
/* Configure tx cts flow control function */
if (config->oflow_ctl)
{
tmp_tx_cfg = BL_SET_REG_BIT(tmp_tx_cfg, UART_CR_UTX_CTS_EN);
}
else
{
tmp_tx_cfg = BL_CLR_REG_BIT(tmp_tx_cfg, UART_CR_UTX_CTS_EN);
}
/* Disable rx input de-glitch function */
tmp_rx_cfg = BL_CLR_REG_BIT(tmp_rx_cfg, UART_CR_URX_DEG_EN);
if (config->iflow_ctl)
{
tmp_tx_cfg = BL_SET_REG_BIT(tmp_tx_cfg, UART_CR_URX_RTS_SW_MODE);
}
else
{
tmp_rx_cfg = BL_CLR_REG_BIT(tmp_rx_cfg, UART_CR_URX_RTS_SW_MODE);
}
/* Write back */
BL_WR_REG(uartbase, UART_UTX_CONFIG, tmp_tx_cfg);
BL_WR_REG(uartbase, UART_URX_CONFIG, tmp_rx_cfg);
/* Configure LSB-first */
tmp_tx_cfg = BL_RD_REG(uartbase, UART_DATA_CONFIG);
tmp_tx_cfg = BL_CLR_REG_BIT(tmp_tx_cfg, UART_CR_UART_BIT_INV);
BL_WR_REG(uartbase, UART_DATA_CONFIG, tmp_tx_cfg);
/* Enable tx free run mode */
tmp_val = BL_RD_REG(uartbase, UART_UTX_CONFIG);
BL_WR_REG(
uartbase, UART_UTX_CONFIG, BL_SET_REG_BIT(tmp_val, UART_CR_UTX_FRM_EN));
/* Deal with uart fifo configure register */
tmp_val = BL_RD_REG(uartbase, UART_FIFO_CONFIG_1);
/* Configure dma tx fifo threshold */
tmp_val = BL_SET_REG_BITS_VAL(tmp_val, UART_TX_FIFO_TH, 0x10 - 1);
/* Configure dma rx fifo threshold */
tmp_val = BL_SET_REG_BITS_VAL(tmp_val, UART_RX_FIFO_TH, 0x10 - 1);
BL_WR_REG(uartbase, UART_FIFO_CONFIG_1, tmp_val);
/* Enable UART tx rx unit */
tmp_val = BL_RD_REG(uartbase, UART_UTX_CONFIG);
BL_WR_REG(
uartbase, UART_UTX_CONFIG, BL_SET_REG_BIT(tmp_val, UART_CR_UTX_EN));
tmp_val = BL_RD_REG(uartbase, UART_URX_CONFIG);
BL_WR_REG(
uartbase, UART_URX_CONFIG, BL_SET_REG_BIT(tmp_val, UART_CR_URX_EN));
}
/****************************************************************************
* Name: up_lowputc
*
* Description:
* Output one byte on the serial console
*
****************************************************************************/
void up_lowputc(char ch)
{
#ifdef HAVE_SERIAL_CONSOLE
/* Wait for FIFO */
while (
BL_GET_REG_BITS_VAL(BL_RD_REG(BL602_CONSOLE_BASE, UART_FIFO_CONFIG_1),
UART_TX_FIFO_CNT) == 0)
;
BL_WR_BYTE(BL602_CONSOLE_BASE + UART_FIFO_WDATA_OFFSET, ch);
#endif /* HAVE_CONSOLE */
}
void bl602_lowsetup(void)
{
#ifdef HAVE_SERIAL_CONSOLE
/* Configure the console UART (if any) */
bl602_uart_configure(BL602_CONSOLE_BASE, &g_bl602_console_config);
up_lowputc('A');
up_lowputc('\r');
up_lowputc('\n');
#endif /* HAVE_SERIAL_CONSOLE */
}

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/**
* incubator-nuttx/arch/risc-v/src/bl602/bl602_lowputc.h
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __ARCH_RISCV_SRC_BL602_LOWPUTC_H
#define __ARCH_RISCV_SRC_BL602_LOWPUTC_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
#ifndef __ASSEMBLY__
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
struct uart_config_s
{
uint8_t idx; /* Uart idx */
uint32_t baud; /* Configured baud */
uint8_t iflow_ctl; /* Input flow control supported */
uint8_t oflow_ctl; /* Output flow control supported. */
uint8_t data_bits; /* Number of bits per word */
bool stop_bits; /* true=2 stop bits; false=1 stop bit */
uint8_t parity; /* Parity selection: 0=none, 1=odd, 2=even */
uint8_t tx_pin; /* TX pin */
uint8_t rx_pin; /* RX pin */
uint8_t cts_pin; /* CTS pin */
uint8_t rts_pin; /* RTS pin */
};
/****************************************************************************
* Name: bl602_lowsetup
****************************************************************************/
EXTERN void bl602_lowsetup(void);
EXTERN void bl602_uart_configure(uint32_t base_addr,
const struct uart_config_s *config);
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_RISCV_SRC_BL602_LOWPUTC_H */

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/****************************************************************************
* arch/arm/src/bl602/bl602_oneshot_lowerhalf.c
*
* Copyright (C) 2016 Gregory Nutt. All rights reserved.
* Authors: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <time.h>
#include <assert.h>
#include <debug.h>
#include <nuttx/irq.h>
#include <nuttx/kmalloc.h>
#include <nuttx/timers/oneshot.h>
#include <hardware/bl602_timer.h>
#include "bl602_oneshot_lowerhalf.h"
#define TIMER_MAX_VALUE (0xFFFFFFFF)
#define TIMER_CLK_DIV (160)
#define TIMER_CLK_FREQ (160000000UL / (TIMER_CLK_DIV))
/****************************************************************************
* Private Types
****************************************************************************/
/* This structure describes the state of the oneshot timer lower-half driver
*/
struct bl602_oneshot_lowerhalf_s
{
/* This is the part of the lower half driver that is visible to the upper-
* half client of the driver. This must be the first thing in this
* structure so that pointers to struct oneshot_lowerhalf_s are cast
* compatible to struct bl602_oneshot_lowerhalf_s and vice versa.
*/
struct oneshot_lowerhalf_s lh; /* Common lower-half driver fields */
uint32_t freq;
/* Private lower half data follows */
oneshot_callback_t callback; /* Internal handler that receives callback */
FAR void * arg; /* Argument that is passed to the handler */
uint8_t tim; /* timer tim 0,1 */
uint8_t irq; /* IRQ associated with this UART */
bool started; /* True: Timer has been started */
};
/****************************************************************************
* Private Function Prototypes
****************************************************************************/
static int bl602_max_delay(FAR struct oneshot_lowerhalf_s *lower,
FAR struct timespec * ts);
static int bl602_start(FAR struct oneshot_lowerhalf_s *lower,
oneshot_callback_t callback,
FAR void * arg,
FAR const struct timespec * ts);
static int bl602_cancel(FAR struct oneshot_lowerhalf_s *lower,
FAR struct timespec * ts);
/****************************************************************************
* Private Data
****************************************************************************/
/* Lower half operations */
static const struct oneshot_operations_s g_oneshot_ops =
{
.max_delay = bl602_max_delay,
.start = bl602_start,
.cancel = bl602_cancel,
};
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Name: bl602_oneshot_handler
*
* Description:
* Timer expiration handler
*
* Input Parameters:
* arg - Should be the same argument provided when bl602_oneshot_start()
* was called.
*
* Returned Value:
* None
*
****************************************************************************/
static int bl602_oneshot_handler(int irq, FAR void *context, FAR void *arg)
{
FAR struct bl602_oneshot_lowerhalf_s *priv =
(FAR struct bl602_oneshot_lowerhalf_s *)arg;
oneshot_callback_t callback;
FAR void * cbarg;
/* Clear Interrupt Bits */
uint32_t int_id;
uint32_t tmp_val;
uint32_t tmp_addr;
int_id = BL_RD_WORD(TIMER_BASE + TIMER_TMSR2_OFFSET + 4 * priv->tim);
tmp_addr = TIMER_BASE + TIMER_TICR2_OFFSET + 4 * priv->tim;
tmp_val = BL_RD_WORD(tmp_addr);
/* Comparator 0 match interrupt */
if (BL_IS_REG_BIT_SET(int_id, TIMER_TMSR_0))
{
BL_WR_WORD(tmp_addr, BL_SET_REG_BIT(tmp_val, TIMER_TCLR_0));
callback = priv->callback;
cbarg = priv->arg;
if (callback)
{
callback(&priv->lh, cbarg);
}
}
/* Comparator 1 match interrupt */
if (BL_IS_REG_BIT_SET(int_id, TIMER_TMSR_1))
{
BL_WR_WORD(tmp_addr, BL_SET_REG_BIT(tmp_val, TIMER_TCLR_1));
}
/* Comparator 2 match interrupt */
if (BL_IS_REG_BIT_SET(int_id, TIMER_TMSR_2))
{
BL_WR_WORD(tmp_addr, BL_SET_REG_BIT(tmp_val, TIMER_TCLR_2));
}
return 0;
}
/****************************************************************************
* Name: bl602_max_delay
*
* Description:
* Determine the maximum delay of the one-shot timer (in microseconds)
*
* Input Parameters:
* lower An instance of the lower-half oneshot state structure. This
* structure must have been previously initialized via a call to
* oneshot_initialize();
* ts The location in which to return the maximum delay.
*
* Returned Value:
* Zero (OK) is returned on success; a negated errno value is returned
* on failure.
*
****************************************************************************/
static int bl602_max_delay(FAR struct oneshot_lowerhalf_s *lower,
FAR struct timespec * ts)
{
FAR struct bl602_oneshot_lowerhalf_s *priv =
(FAR struct bl602_oneshot_lowerhalf_s *)lower;
uint64_t usecs;
DEBUGASSERT(priv != NULL && ts != NULL);
usecs = (uint64_t)(UINT32_MAX / priv->freq) * (uint64_t)USEC_PER_SEC;
uint64_t sec = usecs / 1000000;
usecs -= 1000000 * sec;
ts->tv_sec = (time_t)sec;
ts->tv_nsec = (long)(usecs * 1000);
return OK;
}
/****************************************************************************
* Name: bl602_start
*
* Description:
* Start the oneshot timer
*
* Input Parameters:
* lower An instance of the lower-half oneshot state structure. This
* structure must have been previously initialized via a call to
* oneshot_initialize();
* handler The function to call when when the oneshot timer expires.
* arg An opaque argument that will accompany the callback.
* ts Provides the duration of the one shot timer.
*
* Returned Value:
* Zero (OK) is returned on success; a negated errno value is returned
* on failure.
*
****************************************************************************/
static int bl602_start(FAR struct oneshot_lowerhalf_s *lower,
oneshot_callback_t callback,
FAR void * arg,
FAR const struct timespec * ts)
{
FAR struct bl602_oneshot_lowerhalf_s *priv =
(FAR struct bl602_oneshot_lowerhalf_s *)lower;
irqstate_t flags;
uint64_t usec;
DEBUGASSERT(priv != NULL && callback != NULL && ts != NULL);
if (priv->started == true)
{
/* Yes.. then cancel it */
tmrinfo("Already running... cancelling\n");
bl602_cancel(lower, NULL);
}
/* Save the callback information and start the timer */
flags = enter_critical_section();
priv->callback = callback;
priv->arg = arg;
/* Express the delay in microseconds */
usec = (uint64_t)ts->tv_sec * USEC_PER_SEC +
(uint64_t)(ts->tv_nsec / NSEC_PER_USEC);
timer_setcompvalue(
priv->tim, TIMER_COMP_ID_0, usec / (TIMER_CLK_FREQ / priv->freq));
timer_setpreloadvalue(priv->tim, 0);
irq_attach(priv->irq, bl602_oneshot_handler, (void *)priv);
up_enable_irq(priv->irq);
timer_intmask(priv->tim, TIMER_INT_COMP_0, 0);
timer_enable(priv->tim);
priv->started = true;
leave_critical_section(flags);
return OK;
}
/****************************************************************************
* Name: bl602_cancel
*
* Description:
* Cancel the oneshot timer and return the time remaining on the timer.
*
* NOTE: This function may execute at a high rate with no timer running (as
* when pre-emption is enabled and disabled).
*
* Input Parameters:
* lower Caller allocated instance of the oneshot state structure. This
* structure must have been previously initialized via a call to
* oneshot_initialize();
* ts The location in which to return the time remaining on the
* oneshot timer. A time of zero is returned if the timer is
* not running.
*
* Returned Value:
* Zero (OK) is returned on success. A call to up_timer_cancel() when
* the timer is not active should also return success; a negated errno
* value is returned on any failure.
*
****************************************************************************/
static int bl602_cancel(FAR struct oneshot_lowerhalf_s *lower,
FAR struct timespec * ts)
{
FAR struct bl602_oneshot_lowerhalf_s *priv =
(FAR struct bl602_oneshot_lowerhalf_s *)lower;
irqstate_t flags;
DEBUGASSERT(priv != NULL);
/* Cancel the timer */
if (priv->started)
{
flags = enter_critical_section();
timer_disable(priv->tim);
priv->started = false;
up_disable_irq(priv->irq);
timer_intmask(priv->tim, TIMER_INT_COMP_0, 1);
priv->callback = NULL;
priv->arg = NULL;
leave_critical_section(flags);
return OK;
}
return -ENODEV;
}
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: oneshot_initialize
*
* Description:
* Initialize the oneshot timer and return a oneshot lower half driver
* instance.
*
* Input Parameters:
* chan Timer counter channel to be used.
* resolution The required resolution of the timer in units of
* microseconds. NOTE that the range is restricted to the
* range of uint16_t (excluding zero).
*
* Returned Value:
* On success, a non-NULL instance of the oneshot lower-half driver is
* returned. NULL is return on any failure.
*
****************************************************************************/
FAR struct oneshot_lowerhalf_s *oneshot_initialize(int chan,
uint16_t resolution)
{
FAR struct bl602_oneshot_lowerhalf_s *priv;
timer_cfg_t timstr;
/* Allocate an instance of the lower half driver */
priv = (FAR struct bl602_oneshot_lowerhalf_s *)kmm_zalloc(
sizeof(struct bl602_oneshot_lowerhalf_s));
if (priv == NULL)
{
tmrerr("ERROR: Failed to initialized state structure\n");
return NULL;
}
/* Initialize the lower-half driver structure */
priv->started = false;
priv->lh.ops = &g_oneshot_ops;
priv->freq = TIMER_CLK_FREQ / resolution;
priv->tim = chan;
if (priv->tim == 0)
{
priv->irq = BL602_IRQ_TIMER_CH0;
}
else
{
priv->irq = BL602_IRQ_TIMER_CH1;
}
/* Initialize the contained BL602 oneshot timer */
timstr.timer_ch = chan; /* Timer channel */
timstr.clk_src = TIMER_CLKSRC_FCLK; /* Timer clock source */
timstr.pl_trig_src =
TIMER_PRELOAD_TRIG_COMP0; /* Timer count register preload trigger source
* slelect */
timstr.count_mode = TIMER_COUNT_PRELOAD; /* Timer count mode */
timstr.clock_division =
(TIMER_CLK_DIV * resolution) - 1; /* Timer clock divison value */
timstr.match_val0 = TIMER_MAX_VALUE; /* Timer match 0 value 0 */
timstr.match_val1 = TIMER_MAX_VALUE; /* Timer match 1 value 0 */
timstr.match_val2 = TIMER_MAX_VALUE; /* Timer match 2 value 0 */
timstr.pre_load_val = TIMER_MAX_VALUE; /* Timer preload value */
timer_intmask(chan, TIMER_INT_ALL, 1);
/* timer disable */
timer_disable(chan);
timer_init(&timstr);
return &priv->lh;
}

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/****************************************************************************
* arch/risc-v/src/bl602/bl602_oneshot.h
*
* Copyright (C) 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_BL602_ONESHOT_H
#define __ARCH_ARM_SRC_BL602_ONESHOT_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <time.h>
#include <nuttx/irq.h>
#include "bl602_tim_lowerhalf.h"
#ifdef CONFIG_BL602_ONESHOT
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#if !defined(CONFIG_BL602_ONESHOT_MAXTIMERS) || \
CONFIG_BL602_ONESHOT_MAXTIMERS < 1
#undef CONFIG_BL602_ONESHOT_MAXTIMERS
#define CONFIG_BL602_ONESHOT_MAXTIMERS 1
#endif
#if CONFIG_BL602_ONESHOT_MAXTIMERS > 8
#warning Additional logic required to handle more than 8 timers
#undef CONFIG_BL602_ONESHOT_MAXTIMERS
#define CONFIG_BL602_ONESHOT_MAXTIMERS 8
#endif
/****************************************************************************
* Public Types
****************************************************************************/
/* This describes the callback function that will be invoked when the oneshot
* timer expires. The oneshot fires, the client will receive:
*
* arg - The opaque argument provided when the interrupt was registered
*/
typedef void (*oneshot_handler_t)(void *arg);
/* The oneshot client must allocate an instance of this structure and called
* bl602_oneshot_initialize() before using the oneshot facilities. The
* client should not access the contents of this structure directly since
* the contents are subject to change.
*/
struct bl602_oneshot_s
{
uint8_t chan; /* The timer/counter in use */
#if CONFIG_BL602_ONESHOT_MAXTIMERS > 1
uint8_t cbndx; /* Timer callback handler index */
#endif
volatile bool running; /* True: the timer is running */
FAR struct bl602_tim_dev_s *tch; /* Pointer returned by
* bl602_tim_init() */
volatile oneshot_handler_t handler; /* Oneshot expiration callback */
volatile void * arg; /* The argument that will accompany
* the callback */
uint32_t frequency;
uint32_t period;
};
/****************************************************************************
* Public Data
****************************************************************************/
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: bl602_oneshot_initialize
*
* Description:
* Initialize the oneshot timer wrapper
*
* Input Parameters:
* oneshot Caller allocated instance of the oneshot state structure
* chan Timer counter channel to be used.
* resolution The required resolution of the timer in units of
* microseconds. NOTE that the range is restricted to the
* range of uint16_t (excluding zero).
*
* Returned Value:
* Zero (OK) is returned on success; a negated errno value is returned
* on failure.
*
****************************************************************************/
int bl602_oneshot_initialize(struct bl602_oneshot_s *oneshot,
int chan,
uint16_t resolution);
/****************************************************************************
* Name: bl602_oneshot_max_delay
*
* Description:
* Determine the maximum delay of the one-shot timer (in microseconds)
*
****************************************************************************/
int bl602_oneshot_max_delay(struct bl602_oneshot_s *oneshot, uint64_t *usec);
/****************************************************************************
* Name: bl602_oneshot_start
*
* Description:
* Start the oneshot timer
*
* Input Parameters:
* oneshot Caller allocated instance of the oneshot state structure. This
* structure must have been previously initialized via a call to
* bl602_oneshot_initialize();
* handler The function to call when when the oneshot timer expires.
* arg An opaque argument that will accompany the callback.
* ts Provides the duration of the one shot timer.
*
* Returned Value:
* Zero (OK) is returned on success; a negated errno value is returned
* on failure.
*
****************************************************************************/
int bl602_oneshot_start(struct bl602_oneshot_s *oneshot,
oneshot_handler_t handler,
void * arg,
const struct timespec * ts);
/****************************************************************************
* Name: bl602_oneshot_cancel
*
* Description:
* Cancel the oneshot timer and return the time remaining on the timer.
*
* NOTE: This function may execute at a high rate with no timer running (as
* when pre-emption is enabled and disabled).
*
* Input Parameters:
* oneshot Caller allocated instance of the oneshot state structure. This
* structure must have been previously initialized via a call to
* bl602_oneshot_initialize();
* ts The location in which to return the time remaining on the
* oneshot timer. A time of zero is returned if the timer is
* not running.
*
* Returned Value:
* Zero (OK) is returned on success. A call to up_timer_cancel() when
* the timer is not active should also return success; a negated errno
* value is returned on any failure.
*
****************************************************************************/
int bl602_oneshot_cancel(struct bl602_oneshot_s *oneshot,
struct timespec * ts);
#undef EXTERN
#ifdef __cplusplus
}
#endif
#endif /* CONFIG_BL602_ONESHOT */
#endif /* __ARCH_ARM_SRC_BL602_ONESHOT_H */

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/****************************************************************************
* arch/risc-v/src/bl602/bl602_schedulesigaction.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <sched.h>
#include <debug.h>
#include <nuttx/irq.h>
#include <nuttx/arch.h>
#include <arch/bl602/irq.h>
#include "sched/sched.h"
#include "riscv_internal.h"
#include "riscv_arch.h"
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: up_schedule_sigaction
*
* Description:
* This function is called by the OS when one or more
* signal handling actions have been queued for execution.
* The architecture specific code must configure things so
* that the 'igdeliver' callback is executed on the thread
* specified by 'tcb' as soon as possible.
*
* This function may be called from interrupt handling logic.
*
* This operation should not cause the task to be unblocked
* nor should it cause any immediate execution of sigdeliver.
* Typically, a few cases need to be considered:
*
* (1) This function may be called from an interrupt handler
* During interrupt processing, all xcptcontext structures
* should be valid for all tasks. That structure should
* be modified to invoke sigdeliver() either on return
* from (this) interrupt or on some subsequent context
* switch to the recipient task.
* (2) If not in an interrupt handler and the tcb is NOT
* the currently executing task, then again just modify
* the saved xcptcontext structure for the recipient
* task so it will invoke sigdeliver when that task is
* later resumed.
* (3) If not in an interrupt handler and the tcb IS the
* currently executing task -- just call the signal
* handler now.
*
****************************************************************************/
void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
{
irqstate_t flags;
uint32_t int_ctx;
sinfo("tcb=0x%p sigdeliver=0x%p\n", tcb, sigdeliver);
/* Make sure that interrupts are disabled */
flags = enter_critical_section();
/* Refuse to handle nested signal actions */
if (!tcb->xcp.sigdeliver)
{
/* First, handle some special cases when the signal is
* being delivered to the currently executing task.
*/
sinfo("rtcb=0x%p g_current_regs=0x%p\n", this_task(), g_current_regs);
if (tcb == this_task())
{
/* CASE 1: We are not in an interrupt handler and
* a task is signalling itself for some reason.
*/
if (!g_current_regs)
{
/* In this case just deliver the signal now. */
sigdeliver(tcb);
}
/* CASE 2: We are in an interrupt handler AND the
* interrupted task is the same as the one that
* must receive the signal, then we will have to modify
* the return state as well as the state in the TCB.
*
* Hmmm... there looks like a latent bug here: The following
* logic would fail in the strange case where we are in an
* interrupt handler, the thread is signalling itself, but
* a context switch to another task has occurred so that
* g_current_regs does not refer to the thread of this_task()!
*/
else
{
/* Save the return EPC and STATUS registers. These will be
* restored by the signal trampoline after the signals have
* been delivered.
*/
tcb->xcp.sigdeliver = sigdeliver;
tcb->xcp.saved_epc = g_current_regs[REG_EPC];
tcb->xcp.saved_int_ctx = g_current_regs[REG_INT_CTX];
/* Then set up to vector to the trampoline with interrupts
* disabled
*/
g_current_regs[REG_EPC] = (uint32_t)up_sigdeliver;
int_ctx = g_current_regs[REG_INT_CTX];
int_ctx &= ~MSTATUS_MIE;
g_current_regs[REG_INT_CTX] = int_ctx;
/* And make sure that the saved context in the TCB
* is the same as the interrupt return context.
*/
up_savestate(tcb->xcp.regs);
sinfo("PC/STATUS Saved: %08lx/%08lx New: %08lx/%08lx\n",
tcb->xcp.saved_epc,
tcb->xcp.saved_int_ctx,
g_current_regs[REG_EPC],
g_current_regs[REG_INT_CTX]);
}
}
/* Otherwise, we are (1) signaling a task is not running
* from an interrupt handler or (2) we are not in an
* interrupt handler and the running task is signalling
* some non-running task.
*/
else
{
/* Save the return EPC and STATUS registers. These will be
* restored by the signal trampoline after the signals have
* been delivered.
*/
tcb->xcp.sigdeliver = sigdeliver;
tcb->xcp.saved_epc = tcb->xcp.regs[REG_EPC];
tcb->xcp.saved_int_ctx = tcb->xcp.regs[REG_INT_CTX];
/* Then set up to vector to the trampoline with interrupts
* disabled
*/
tcb->xcp.regs[REG_EPC] = (uint32_t)up_sigdeliver;
int_ctx = tcb->xcp.regs[REG_INT_CTX];
int_ctx &= ~MSTATUS_MIE;
tcb->xcp.regs[REG_INT_CTX] = int_ctx;
sinfo("PC/STATUS Saved: %08lx/%08lx New: %08lx/%08lx\n",
tcb->xcp.saved_epc,
tcb->xcp.saved_int_ctx,
tcb->xcp.regs[REG_EPC],
tcb->xcp.regs[REG_INT_CTX]);
}
}
leave_critical_section(flags);
}

984
arch/risc-v/src/bl602/bl602_serial.c Normal file
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@ -0,0 +1,984 @@
/****************************************************************************
* arch/risc-v/src/bl602/bl602_serial.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <sys/types.h>
#include <stdint.h>
#include <stdbool.h>
#include <unistd.h>
#include <string.h>
#include <errno.h>
#include <debug.h>
#include <nuttx/irq.h>
#include <nuttx/serial/serial.h>
#include <arch/board/board.h>
#include "bl602_lowputc.h"
#include "hardware/bl602_gpio.h"
#include "hardware/bl602_uart.h"
#include "hardware/bl602_glb.h"
#include "riscv_arch.h"
#include "riscv_internal.h"
#include "bl602_config.h"
#include "chip.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Select UART parameters for the selected console */
#ifdef HAVE_SERIAL_CONSOLE
#if defined(CONFIG_UART0_SERIAL_CONSOLE)
#define BL602_CONSOLE_IDX 0
#define BL602_CONSOLE_BAUD CONFIG_UART0_BAUD
#define BL602_CONSOLE_BITS CONFIG_UART0_BITS
#define BL602_CONSOLE_PARITY CONFIG_UART0_PARITY
#define BL602_CONSOLE_2STOP CONFIG_UART0_2STOP
#define BL602_CONSOLE_TX GPIO_UART0_TX
#define BL602_CONSOLE_RX GPIO_UART0_RX
#define HAVE_UART
#elif defined(CONFIG_UART1_SERIAL_CONSOLE)
#define BL602_CONSOLE_IDX 1
#define BL602_CONSOLE_BAUD CONFIG_UART1_BAUD
#define BL602_CONSOLE_BITS CONFIG_UART1_BITS
#define BL602_CONSOLE_PARITY CONFIG_UART1_PARITY
#define BL602_CONSOLE_2STOP CONFIG_UART1_2STOP
#define BL602_CONSOLE_TX GPIO_UART1_TX
#define BL602_CONSOLE_RX GPIO_UART1_RX
#define HAVE_UART
#endif
#endif /* HAVE_CONSOLE */
/* If we are not using the serial driver for the console, then we still must
* provide some minimal implementation of up_putc.
*/
#ifdef USE_SERIALDRIVER
/* Which UART with be tty0/console and which tty1? The console will always
* be ttyS0. If there is no console then will use the lowest numbered UART.
*/
#ifdef HAVE_SERIAL_CONSOLE
#if defined(CONFIG_UART0_SERIAL_CONSOLE)
#define CONSOLE_DEV g_uart0port /* UART0 is console */
#define TTYS0_DEV g_uart0port /* UART0 is ttyS0 */
#undef TTYS1_DEV /* No ttyS1 */
#define SERIAL_CONSOLE 1
#elif defined(CONFIG_UART1_SERIAL_CONSOLE)
#define CONSOLE_DEV g_uart1port /* UART0 is console */
#error "I'm confused... Do we have a serial console or not?"
#endif
#else
#undef CONSOLE_DEV /* No console */
#undef CONFIG_UART0_SERIAL_CONSOLE
#if defined(CONFIG_BL602_UART0)
#define TTYS0_DEV g_uart0port /* UART0 is ttyS0 */
#undef TTYS1_DEV /* No ttyS1 */
#define SERIAL_CONSOLE 1
#else
#undef TTYS0_DEV
#undef TTYS1_DEV
#endif
#endif
/* Common initialization logic will not not know that the all of the UARTs
* have been disabled. So, as a result, we may still have to provide
* stub implementations of up_earlyserialinit(), up_serialinit(), and
* up_putc().
*/
#ifdef HAVE_UART_DEVICE
/****************************************************************************
* Private Types
****************************************************************************/
struct up_dev_s
{
const uint32_t uartbase; /* Base address of UART registers */
uint8_t irq; /* IRQ associated with this UART */
struct uart_config_s config;
};
/****************************************************************************
* Private Function Prototypes
****************************************************************************/
/* Serial driver methods */
static int up_setup(struct uart_dev_s *dev);
static void up_shutdown(struct uart_dev_s *dev);
static int up_attach(struct uart_dev_s *dev);
static void up_detach(struct uart_dev_s *dev);
static int up_ioctl(struct file *filep, int cmd, unsigned long arg);
static int up_receive(struct uart_dev_s *dev, unsigned int *status);
static void up_rxint(struct uart_dev_s *dev, bool enable);
static bool up_rxavailable(struct uart_dev_s *dev);
static void up_send(struct uart_dev_s *dev, int ch);
static void up_txint(struct uart_dev_s *dev, bool enable);
static bool up_txready(struct uart_dev_s *dev);
static bool up_txempty(struct uart_dev_s *dev);
/****************************************************************************
* Private Data
****************************************************************************/
static const struct uart_ops_s g_uart_ops =
{
.setup = up_setup,
.shutdown = up_shutdown,
.attach = up_attach,
.detach = up_detach,
.ioctl = up_ioctl,
.receive = up_receive,
.rxint = up_rxint,
.rxavailable = up_rxavailable,
#ifdef CONFIG_SERIAL_IFLOWCONTROL
.rxflowcontrol = NULL,
#endif
.send = up_send,
.txint = up_txint,
.txready = up_txready,
.txempty = up_txempty,
};
/* I/O buffers */
#ifdef CONFIG_BL602_UART0
static char g_uart0rxbuffer[CONFIG_UART0_RXBUFSIZE];
static char g_uart0txbuffer[CONFIG_UART0_TXBUFSIZE];
static struct up_dev_s g_uart0priv =
{
.uartbase = UART0_BASE,
.irq = BL602_IRQ_UART0,
.config =
{
.idx = 0,
.baud = CONFIG_UART0_BAUD,
.parity = CONFIG_UART0_PARITY,
.data_bits = CONFIG_UART0_BITS,
.stop_bits = CONFIG_UART0_2STOP,
.tx_pin = CONFIG_BL602_UART0_TX_PIN,
.rx_pin = CONFIG_BL602_UART0_RX_PIN,
.rts_pin = CONFIG_BL602_UART0_RTS_PIN,
.cts_pin = CONFIG_BL602_UART0_CTS_PIN,
#ifdef CONFIG_UART0_IFLOWCONTROL
.iflow_ctl = CONFIG_UART0_IFLOWCONTROL,
#else
.iflow_ctl = 0,
#endif
#ifdef CONFIG_UART0_OFLOWCONTROL
.oflow_ctl = CONFIG_UART0_OFLOWCONTROL,
#else
.oflow_ctl = 0,
#endif
},
};
static uart_dev_t g_uart0port =
{
#ifdef CONFIG_UART0_SERIAL_CONSOLE
.isconsole = 1,
#endif
.recv =
{
.size = CONFIG_UART0_RXBUFSIZE,
.buffer = g_uart0rxbuffer,
},
.xmit =
{
.size = CONFIG_UART0_TXBUFSIZE,
.buffer = g_uart0txbuffer,
},
.ops = &g_uart_ops,
.priv = (void *)&g_uart0priv,
};
#endif
#ifdef CONFIG_BL602_UART1
static char g_uart1rxbuffer[CONFIG_UART1_RXBUFSIZE];
static char g_uart1txbuffer[CONFIG_UART1_TXBUFSIZE];
static struct up_dev_s g_uart1priv =
{
.uartbase = UART1_BASE,
.irq = BL602_IRQ_UART1,
.config =
{
.idx = 1,
.baud = CONFIG_UART1_BAUD,
.parity = CONFIG_UART1_PARITY,
.data_bits = CONFIG_UART1_BITS,
.stop_bits = CONFIG_UART1_2STOP,
.tx_pin = CONFIG_BL602_UART1_TX_PIN,
.rx_pin = CONFIG_BL602_UART1_RX_PIN,
.rts_pin = CONFIG_BL602_UART1_RTS_PIN,
.cts_pin = CONFIG_BL602_UART1_CTS_PIN,
#ifdef CONFIG_UART1_IFLOWCONTROL
.iflow_ctl = CONFIG_UART1_IFLOWCONTROL,
#else
.iflow_ctl = 0,
#endif
#ifdef CONFIG_UART1_OFLOWCONTROL
.oflow_ctl = CONFIG_UART1_OFLOWCONTROL,
#else
.oflow_ctl = 0,
#endif
},
};
static uart_dev_t g_uart1port =
{
#ifdef CONFIG_UART1_SERIAL_CONSOLE
.isconsole = 1,
#endif
.recv =
{
.size = CONFIG_UART1_RXBUFSIZE,
.buffer = g_uart1rxbuffer,
},
.xmit =
{
.size = CONFIG_UART1_TXBUFSIZE,
.buffer = g_uart1txbuffer,
},
.ops = &g_uart_ops,
.priv = (void *)&g_uart1priv,
};
#endif
static struct uart_dev_s *const g_uart_devs[] =
{
#ifdef CONFIG_BL602_UART0
[0] = &g_uart0port,
#endif
#ifdef CONFIG_BL602_UART1
[1] = &g_uart1port
#endif
};
/****************************************************************************
* Name: uart_interrupt
*
* Description:
* This is the UART interrupt handler. It will be invoked when an
* interrupt received on the 'irq' It should call uart_transmitchars or
* uart_receivechar to perform the appropriate data transfers. The
* interrupt handling logic must be able to map the 'irq' number into the
* appropriate uart_dev_s structure in order to call these functions.
*
****************************************************************************/
static int __uart_interrupt(int irq, FAR void *context, FAR void *arg)
{
uart_dev_t * dev = (uart_dev_t *)arg;
struct up_dev_s *uart_priv = dev->priv;
uint32_t tmp_val = 0;
uint32_t mask_val = 0;
tmp_val = BL_RD_REG(uart_priv->uartbase, UART_INT_STS);
mask_val = BL_RD_REG(uart_priv->uartbase, UART_INT_MASK);
/* Length of uart rx data transfer arrived interrupt */
if (BL_IS_REG_BIT_SET(tmp_val, UART_URX_END_INT) &&
!BL_IS_REG_BIT_SET(mask_val, UART_CR_URX_END_MASK))
{
BL_WR_REG(uart_priv->uartbase, UART_INT_CLEAR, 0x2);
/* Receive Data ready */
uart_recvchars(dev);
}
/* Tx fifo ready interrupt,auto-cleared when data is pushed */
if (BL_IS_REG_BIT_SET(tmp_val, UART_UTX_FIFO_INT) &&
!BL_IS_REG_BIT_SET(mask_val, UART_CR_UTX_FIFO_MASK))
{
/* Transmit data request interrupt */
uart_xmitchars(dev);
}
/* Rx fifo ready interrupt,auto-cleared when data is popped */
if (BL_IS_REG_BIT_SET(tmp_val, UART_URX_FIFO_INT) &&
!BL_IS_REG_BIT_SET(mask_val, UART_CR_URX_FIFO_MASK))
{
/* Receive Data ready */
uart_recvchars(dev);
}
return OK;
}
/****************************************************************************
* Name: up_setup
*
* Description:
* Configure the UART baud, bits, parity, etc. This method is called the
* first time that the serial port is opened.
*
****************************************************************************/
static int up_setup(struct uart_dev_s *dev)
{
struct up_dev_s *uart_priv = (struct up_dev_s *)dev->priv;
bl602_uart_configure(uart_priv->uartbase, &uart_priv->config);
return OK;
}
/****************************************************************************
* Name: up_shutdown
*
* Description:
* Disable the UART. This method is called when the serial
* port is closed
*
****************************************************************************/
static void up_shutdown(struct uart_dev_s *dev)
{
uint32_t tmp_val;
struct up_dev_s *uart_priv = (struct up_dev_s *)dev->priv;
/* Disable uart before config */
tmp_val = BL_RD_REG(uart_priv->uartbase, UART_UTX_CONFIG);
BL_WR_REG(uart_priv->uartbase,
UART_UTX_CONFIG,
BL_CLR_REG_BIT(tmp_val, UART_CR_UTX_EN));
tmp_val = BL_RD_REG(uart_priv->uartbase, UART_URX_CONFIG);
BL_WR_REG(uart_priv->uartbase,
UART_URX_CONFIG,
BL_CLR_REG_BIT(tmp_val, UART_CR_URX_EN));
}
/****************************************************************************
* Name: up_attach
*
* Description:
* Configure the UART to operation in interrupt driven mode. This method
* is called when the serial port is opened. Normally, this is just after
* the the setup() method is called, however, the serial console may
* operate in a non-interrupt driven mode during the boot phase.
*
* RX and TX interrupts are not enabled by the attach method (unless the
* hardware supports multiple levels of interrupt enabling). The RX and TX
* interrupts are not enabled until the txint() and rxint() are called.
*
****************************************************************************/
static int up_attach(struct uart_dev_s *dev)
{
int ret;
struct up_dev_s *priv = (struct up_dev_s *)dev->priv;
ret = irq_attach(priv->irq, __uart_interrupt, (void *)dev);
if (ret == OK)
{
up_enable_irq(priv->irq);
}
return ret;
}
/****************************************************************************
* Name: up_detach
*
* Description:
* Detach UART interrupts. This method is called when the serial port is
* closed normally just before the shutdown method is called. The
* exception is the serial console which is never shutdown.
*
****************************************************************************/
static void up_detach(struct uart_dev_s *dev)
{
struct up_dev_s *priv = (struct up_dev_s *)dev->priv;
/* Disable interrupts */
up_disable_irq(priv->irq);
/* Detach from the interrupt */
irq_detach(priv->irq);
}
/****************************************************************************
* Name: up_ioctl
*
* Description:
* All ioctl calls will be routed through this method
*
****************************************************************************/
static int up_ioctl(struct file *filep, int cmd, unsigned long arg)
{
#if defined(CONFIG_SERIAL_TERMIOS) || defined(CONFIG_SERIAL_TIOCSERGSTRUCT)
struct inode * inode = filep->f_inode;
struct uart_dev_s *dev = inode->i_private;
#endif
int ret = OK;
switch (cmd)
{
#ifdef CONFIG_SERIAL_TERMIOS
case TCGETS:
do
{
struct termios * termiosp = (struct termios *)arg;
struct up_dev_s *priv = (struct up_dev_s *)dev->priv;
if (!termiosp)
{
ret = -EINVAL;
break;
}
termiosp->c_cflag = 0;
/* Return parity */
termiosp->c_cflag = ((priv->parity != 0) ? PARENB : 0) |
((priv->parity == 1) ? PARODD : 0);
/* Return stop bits */
termiosp->c_cflag |= (priv->stop_bits) ? CSTOPB : 0;
/* Return flow control */
termiosp->c_cflag |= (priv->iflow_ctl) ? CRTS_IFLOW : 0;
termiosp->c_cflag |= (priv->oflow_ctl) ? CCTS_OFLOW : 0;
/* Return baud */
cfsetispeed(termiosp, priv->baud);
/* Return number of bits */
switch (priv->data_bits)
{
case 5:
termiosp->c_cflag |= CS5;
break;
case 6:
termiosp->c_cflag |= CS6;
break;
case 7:
termiosp->c_cflag |= CS7;
break;
default:
case 8:
termiosp->c_cflag |= CS8;
break;
}
}
while (0);
break;
case TCSETS:
do
{
struct termios * termiosp = (struct termios *)arg;
struct up_dev_s * priv = (struct up_dev_s *)dev->priv;
struct uart_config_s config;
uint32_t tmp_val;
if (!termiosp)
{
ret = -EINVAL;
break;
}
/* Decode baud. */
ret = OK;
config.baud = cfgetispeed(termiosp);
/* Decode number of bits */
switch (termiosp->c_cflag & CSIZE)
{
case CS5:
config.data_bits = 5;
break;
case CS6:
config.data_bits = 6;
break;
case CS7:
config.data_bits = 7;
break;
case CS8:
config.data_bits = 8;
break;
default:
ret = -EINVAL;
break;
}
/* Decode parity */
if ((termiosp->c_cflag & PARENB) != 0)
{
config.parity = (termiosp->c_cflag & PARODD) ? 1 : 2;
}
else
{
config.parity = 0;
}
/* Decode stop bits */
config.stop_bits = (termiosp->c_cflag & CSTOPB) != 0;
/* Decode flow control */
if (priv->idx == 0)
{
#if CONFIG_UART0_IFLOWCONTROL
config.iflow_ctl = (termiosp->c_cflag & CRTS_IFLOW) != 0;
#endif
#if CONFIG_UART0_OFLOWCONTROL
config.oflow_ctl = (termiosp->c_cflag & CCTS_OFLOW) != 0;
#endif
}
else
{
#if CONFIG_UART1_IFLOWCONTROL
config.iflow_ctl = (termiosp->c_cflag & CRTS_IFLOW) != 0;
#endif
#if CONFIG_UART1_OFLOWCONTROL
config.oflow_ctl = (termiosp->c_cflag & CCTS_OFLOW) != 0;
#endif
}
/* Verify that all settings are valid before committing */
if (ret == OK)
{
/* Commit */
memcpy(&priv->config, &config, sizeof(config));
/* effect the changes immediately - note that we do not
* implement TCSADRAIN / TCSAFLUSH
*/
tmp_val = BL_RD_REG(priv->uartbase, UART_INT_MASK);
bl602_uart_configure(priv->uartbase, &config);
BL_WR_REG(priv->uartbase, UART_INT_MASK, tmp_val);
}
}
while (0);
break;
#endif /* CONFIG_SERIAL_TERMIOS */
default:
ret = -ENOTTY;
break;
}
return ret;
}
/****************************************************************************
* Name: up_receive
*
* Description:
* Called (usually) from the interrupt level to receive one
* character from the UART. Error bits associated with the
* receipt are provided in the return 'status'.
*
****************************************************************************/
static int up_receive(struct uart_dev_s *dev, unsigned int *status)
{
struct up_dev_s *priv = (struct up_dev_s *)dev->priv;
int rxdata;
/* Return status information */
if (status)
{
*status = 0; /* We are not yet tracking serial errors */
}
/* if uart fifo cnts > 0 */
if (BL_GET_REG_BITS_VAL(BL_RD_REG(priv->uartbase, UART_FIFO_CONFIG_1),
UART_RX_FIFO_CNT) > 0)
{
rxdata = BL_RD_BYTE(priv->uartbase + UART_FIFO_RDATA_OFFSET);
}
else
{
rxdata = -1;
}
return rxdata;
}
/****************************************************************************
* Name: up_rxint
*
* Description:
* Call to enable or disable RX interrupts
*
****************************************************************************/
static void up_rxint(struct uart_dev_s *dev, bool enable)
{
uint32_t tmp_val;
struct up_dev_s *priv = (struct up_dev_s *)dev->priv;
irqstate_t flags = enter_critical_section();
if (enable)
{
#ifndef CONFIG_SUPPRESS_SERIAL_INTS
tmp_val = BL_RD_REG(priv->uartbase, UART_INT_MASK);
tmp_val &= ~(1 << UART_INT_RX_FIFO_REQ);
tmp_val &= ~(1 << UART_INT_RX_END);
BL_WR_REG(priv->uartbase, UART_INT_MASK, tmp_val);
#endif
}
else
{
tmp_val = BL_RD_REG(priv->uartbase, UART_INT_MASK);
tmp_val |= (1 << UART_INT_RX_FIFO_REQ);
tmp_val |= (1 << UART_INT_RX_END);
BL_WR_REG(priv->uartbase, UART_INT_MASK, tmp_val);
}
leave_critical_section(flags);
}
/****************************************************************************
* Name: up_rxavailable
*
* Description:
* Return true if the receive register is not empty
*
****************************************************************************/
static bool up_rxavailable(struct uart_dev_s *dev)
{
struct up_dev_s *priv = (struct up_dev_s *)dev->priv;
/* Return true is data is available in the receive data buffer */
uint32_t rxcnt = BL_GET_REG_BITS_VAL(
BL_RD_REG(priv->uartbase, UART_FIFO_CONFIG_1), UART_RX_FIFO_CNT);
return rxcnt != 0;
}
/****************************************************************************
* Name: up_send
*
* Description:
* This method will send one byte on the UART.
*
****************************************************************************/
static void up_send(struct uart_dev_s *dev, int ch)
{
struct up_dev_s *priv = (struct up_dev_s *)dev->priv;
/* Wait for FIFO */
while (BL_GET_REG_BITS_VAL(BL_RD_REG(priv->uartbase, UART_FIFO_CONFIG_1),
UART_TX_FIFO_CNT) == 0)
;
BL_WR_BYTE(priv->uartbase + UART_FIFO_WDATA_OFFSET, ch);
}
/****************************************************************************
* Name: up_txint
*
* Description:
* Call to enable or disable TX interrupts
*
****************************************************************************/
static void up_txint(struct uart_dev_s *dev, bool enable)
{
struct up_dev_s *priv = (struct up_dev_s *)dev->priv;
irqstate_t flags;
uint32_t tmp_val;
flags = enter_critical_section();
if (enable)
{
#ifndef CONFIG_SUPPRESS_SERIAL_INTS
/* Enable the TX interrupt */
tmp_val = BL_RD_REG(priv->uartbase, UART_INT_MASK);
tmp_val &= ~(1 << UART_INT_TX_FIFO_REQ);
BL_WR_REG(priv->uartbase, UART_INT_MASK, tmp_val);
/* Fake a TX interrupt here by just calling uart_xmitchars() with
* interrupts disabled (note this may recurse).
*/
uart_xmitchars(dev);
#endif
}
else
{
/* Disable the TX interrupt */
tmp_val = BL_RD_REG(priv->uartbase, UART_INT_MASK);
tmp_val |= (1 << UART_INT_TX_FIFO_REQ);
BL_WR_REG(priv->uartbase, UART_INT_MASK, tmp_val);
}
leave_critical_section(flags);
}
/****************************************************************************
* Name: up_txready
*
* Description:
* Return true if the tranmsit data register is not full
*
****************************************************************************/
static bool up_txready(struct uart_dev_s *dev)
{
struct up_dev_s *priv = (struct up_dev_s *)dev->priv;
/* Return TRUE if the TX FIFO is not full */
uint32_t txcnt = BL_GET_REG_BITS_VAL(
BL_RD_REG(priv->uartbase, UART_FIFO_CONFIG_1), UART_TX_FIFO_CNT);
return (txcnt != 0);
}
/****************************************************************************
* Name: up_txempty
*
* Description:
* Return true if the tranmsit data register is empty
*
****************************************************************************/
static bool up_txempty(struct uart_dev_s *dev)
{
struct up_dev_s *priv = (struct up_dev_s *)dev->priv;
/* Return TRUE if the TX is pending */
uint32_t txcnt = BL_GET_REG_BITS_VAL(
BL_RD_REG(priv->uartbase, UART_FIFO_CONFIG_1), UART_TX_FIFO_CNT);
return (txcnt == 0);
}
/****************************************************************************
* Public Functions
****************************************************************************/
#ifdef USE_EARLYSERIALINIT
/****************************************************************************
* Name: up_earlyserialinit
*
* Description:
* Performs the low level UART initialization early in debug so that the
* serial console will be available during bootup. This must be called
* before up_serialinit. NOTE: This function depends on GPIO pin
* configuration performed in up_consoleinit() and main clock iniialization
* performed in up_clkinitialize().
*
****************************************************************************/
void up_earlyserialinit(void)
{
#ifdef HAVE_SERIAL_CONSOLE
/* Configuration whichever one is the console */
CONSOLE_DEV.isconsole = true;
up_setup(&CONSOLE_DEV);
#endif
}
#endif
/****************************************************************************
* Name: up_serialinit
*
* Description:
* Register serial console and serial ports. This assumes
* that up_earlyserialinit was called previously.
*
****************************************************************************/
void up_serialinit(void)
{
int i;
char devname[16];
#ifdef HAVE_SERIAL_CONSOLE
/* Register the console */
uart_register("/dev/console", &CONSOLE_DEV);
#endif
/* Register all UARTs */
strcpy(devname, "/dev/ttySx");
for (i = 0; i < sizeof(g_uart_devs) / sizeof(g_uart_devs[0]); i++)
{
if (g_uart_devs[i] == 0)
{
continue;
}
/* Don't create a device for the console - we did that above */
if (g_uart_devs[i]->isconsole)
{
continue;
}
/* Register USARTs as devices in increasing order */
devname[9] = '0' + i;
uart_register(devname, g_uart_devs[i]);
}
}
/****************************************************************************
* Name: up_putc
*
* Description:
* Provide priority, low-level access to support OS debug writes
*
****************************************************************************/
int up_putc(int ch)
{
#ifdef HAVE_SERIAL_CONSOLE
struct up_dev_s *priv = (struct up_dev_s *)CONSOLE_DEV.priv;
(void)priv;
irqstate_t flags = enter_critical_section();
/* Check for LF */
if (ch == '\n')
{
/* Add CR */
up_lowputc('\r');
}
up_lowputc(ch);
leave_critical_section(flags);
#endif
return ch;
}
/****************************************************************************
* Name: up_earlyserialinit, up_serialinit, and up_putc
*
* Description:
* stubs that may be needed. These stubs would be used if all UARTs are
* disabled. In that case, the logic in common/up_initialize() is not
* smart enough to know that there are not UARTs and will still expect
* these interfaces to be provided.
*
****************************************************************************/
#else /* HAVE_UART_DEVICE */
void up_earlyserialinit(void)
{
}
void up_serialinit(void)
{
}
int up_putc(int ch)
{
return ch;
}
#endif /* HAVE_UART_DEVICE */
#else /* USE_SERIALDRIVER */
/****************************************************************************
* Name: up_putc
*
* Description:
* Provide priority, low-level access to support OS debug writes
*
****************************************************************************/
int up_putc(int ch)
{
#ifdef HAVE_SERIAL_CONSOLE
/* Check for LF */
if (ch == '\n')
{
/* Add CR */
up_lowputc('\r');
}
up_lowputc(ch);
#endif
return ch;
}
#endif /* USE_SERIALDRIVER */

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/****************************************************************************
* arch/risc-v/src/bl602/bl602_init.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <stdint.h>
#include <nuttx/config.h>
#include <arch/board/board.h>
#include "bl602_boot2.h"
#include "chip.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#ifdef CONFIG_DEBUG_FEATURES
#define showprogress(c) up_lowputc(c)
#else
#define showprogress(c)
#endif
#define PARTITION_BOOT2_RAM_ADDR_ACTIVE (0x42049C00)
#define PARTITION_HEADER_BOOT2_RAM_ADDR (0x42049C04)
#define PARTITION_BOOT2_FLASH_HEADER (0x42049d14)
#define PARTITION_BOOT2_FLASH_CONFIG (0x42049d18)
#define PARTITION_MAGIC (0x54504642)
#define PARTITION_FW_PART_NAME "FW"
#define PARTITION_FW_PART_HEADER_SIZE (0x1000)
/* TODO use header file from project */
#define FW_XIP_ADDRESS (0x23000000)
#define BL602_IDLESTACK_SIZE (CONFIG_IDLETHREAD_STACKSIZE & ~3)
/****************************************************************************
* Private Data
****************************************************************************/
/* g_idle_topstack: _sbss is the start of the BSS region as defined by the
* linker script. _ebss lies at the end of the BSS region. The idle task
* stack starts at the end of BSS and is of size CONFIG_IDLETHREAD_STACKSIZE.
* The IDLE thread is the thread that the system boots on and, eventually,
* becomes the IDLE, do nothing task that runs only when there is nothing
* else to run. The heap continues from there until the end of memory.
* g_idle_topstack is a read-only variable the provides this computed
* address.
*/
static uint8_t idle_stack[BL602_IDLESTACK_SIZE];
/* Dont change the name of varaible, since we refer this
* boot2_partition_table in linker script
*/
static struct
{
uint8_t partition_active_idx;
uint8_t pad[3];
struct pt_table_stuff_config_s table;
} boot2_partition_table;
/****************************************************************************
* Public Data
****************************************************************************/
uint32_t g_idle_topstack = (uintptr_t)idle_stack + BL602_IDLESTACK_SIZE;
/****************************************************************************
* Public Functions
****************************************************************************/
extern void bl602_lowsetup(void);
extern void exception_common(void);
extern void bl602_boardinitialize(void);
/****************************************************************************
* Name: boot2_get_flash_addr
****************************************************************************/
uint32_t boot2_get_flash_addr(void)
{
extern uint8_t __boot2_flash_cfg_src;
return (uint32_t)(&__boot2_flash_cfg_src +
(sizeof(boot2_partition_table.table.pt_entries[0]) *
boot2_partition_table.table.pt_table.entry_cnt));
}
/****************************************************************************
* Name: bfl_main
****************************************************************************/
void bfl_main(void)
{
/* set interrupt vector */
asm volatile("csrw mtvec, %0" ::"r"((uintptr_t)exception_common + 2));
/* Configure the UART so we can get debug output */
bl602_lowsetup();
#ifdef USE_EARLYSERIALINIT
up_earlyserialinit();
#endif
/* Do board initialization */
bl602_boardinitialize();
/* Call nx_start() */
nx_start();
/* Shouldn't get here */
while (1)
;
}

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/****************************************************************************
* boards/risc-v/bl602/evb/src/bl602_tim.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <hardware/bl602_timer.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#define TIMER_MAX_MATCH 3
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: timer_getcompvalue
*
* Description:
* Get the specified channel and match comparator value.
*
* Input Parameters:
* timer_ch - TIMER channel type.
* cmp_no - TIMER comparator ID type.
*
* Returned Value:
* Match comapre register value
*
****************************************************************************/
uint32_t timer_getcompvalue(timer_chan_t timer_ch, timer_comp_id_t cmp_no)
{
uint32_t tmp_val;
tmp_val = BL_RD_WORD(TIMER_BASE + TIMER_TMR2_0_OFFSET +
4 * (TIMER_MAX_MATCH * timer_ch + cmp_no));
return tmp_val;
}
/****************************************************************************
* Name: timer_setcompvalue
*
* Description:
* TIMER set specified channel and comparator compare value
*
* Input Parameters:
* timer_ch - TIMER channel type.
* cmp_no - TIMER comparator ID type.
* val - TIMER match comapre register value.
*
* Returned Value:
* None
*
****************************************************************************/
void timer_setcompvalue(timer_chan_t timer_ch,
timer_comp_id_t cmp_no,
uint32_t val)
{
BL_WR_WORD(TIMER_BASE + TIMER_TMR2_0_OFFSET +
4 * (TIMER_MAX_MATCH * timer_ch + cmp_no),
val);
}
/****************************************************************************
* Name: timer_getcountervalue
*
* Description:
* TIMER get the specified channel count value.
*
* Input Parameters:
* timer_ch - TIMER channel type
*
* Returned Value:
* TIMER count register value
*
****************************************************************************/
uint32_t timer_getcountervalue(timer_chan_t timer_ch)
{
uint32_t tmp_val;
uint32_t tmp_addr;
/* TO avoid risk of reading, don't read TCVWR directly
* request for read
*/
tmp_addr = TIMER_BASE + TIMER_TCVWR2_OFFSET + 4 * timer_ch;
BL_WR_WORD(tmp_addr, 1);
/* Need wait */
tmp_val = BL_RD_WORD(tmp_addr);
tmp_val = BL_RD_WORD(tmp_addr);
tmp_val = BL_RD_WORD(tmp_addr);
return tmp_val;
}
/****************************************************************************
* Name: timer_getmatchstatus
*
* Description:
* TIMER get specified channel and comparator match status
*
* Input Parameters:
* timer_ch - TIMER channel type.
* cmp_no - TIMER comparator ID type.
*
* Returned Value:
* 0 or 1
*
****************************************************************************/
uint32_t timer_getmatchstatus(timer_chan_t timer_ch, timer_comp_id_t cmp_no)
{
uint32_t tmp_val;
uint32_t bit_status = 0;
tmp_val = BL_RD_WORD(TIMER_BASE + TIMER_TMSR2_OFFSET + 4 * timer_ch);
switch (cmp_no)
{
case TIMER_COMP_ID_0:
bit_status = BL_IS_REG_BIT_SET(tmp_val, TIMER_TMSR_0) ? 1 : 0;
break;
case TIMER_COMP_ID_1:
bit_status = BL_IS_REG_BIT_SET(tmp_val, TIMER_TMSR_1) ? 1 : 0;
break;
case TIMER_COMP_ID_2:
bit_status = BL_IS_REG_BIT_SET(tmp_val, TIMER_TMSR_2) ? 1 : 0;
break;
default:
break;
}
return bit_status;
}
/****************************************************************************
* Name: timer_getpreloadvalue
*
* Description:
* TIMER get specified channel preload value
*
* Input Parameters:
* timer_ch - TIMER channel type.
*
* Returned Value:
* Preload register value.
*
****************************************************************************/
uint32_t timer_getpreloadvalue(timer_chan_t timer_ch)
{
uint32_t tmp_val;
tmp_val = BL_RD_WORD(TIMER_BASE + TIMER_TPLVR2_OFFSET + 4 * timer_ch);
return tmp_val;
}
/****************************************************************************
* Name: timer_setpreloadvalue
*
* Description:
* TIMER set preload register low 32bits value
*
* Input Parameters:
* timer_ch - TIMER channel type.
* val - Preload register low 32bits value.
*
* Returned Value:
* None.
*
****************************************************************************/
void timer_setpreloadvalue(timer_chan_t timer_ch, uint32_t val)
{
BL_WR_WORD(TIMER_BASE + TIMER_TPLVR2_OFFSET + 4 * timer_ch, val);
}
/****************************************************************************
* Name: timer_setpreloadtrigsrc
*
* Description:
* TIMER set preload trigger source,COMP0,COMP1,COMP2 or None
*
* Input Parameters:
* timer_ch - TIMER channel type.
* pl_src - TIMER preload source type.
*
* Returned Value:
* None.
*
****************************************************************************/
void timer_setpreloadtrigsrc(timer_chan_t timer_ch,
timer_preload_trig_t pl_src)
{
BL_WR_WORD(TIMER_BASE + TIMER_TPLCR2_OFFSET + 4 * timer_ch, pl_src);
}
/****************************************************************************
* Name: timer_setcountmode
*
* Description:
* TIMER set count mode:preload or free run
*
* Input Parameters:
* timer_ch - TIMER channel type.
* count_mode - TIMER count mode: TIMER_COUNT_PRELOAD or
*TIMER_COUNT_FREERUN.
*
* Returned Value:
* None.
*
****************************************************************************/
void timer_setcountmode(timer_chan_t timer_ch, timer_countmode_t count_mode)
{
uint32_t tmpval;
tmpval = BL_RD_WORD(TIMER_BASE + TIMER_TCMR_OFFSET);
tmpval &= (~(1 << (timer_ch + 1)));
tmpval |= (count_mode << (timer_ch + 1));
BL_WR_WORD(TIMER_BASE + TIMER_TCMR_OFFSET, tmpval);
}
/****************************************************************************
* Name: timer_clearintstatus
*
* Description:
* TIMER clear interrupt status
*
* Input Parameters:
* timer_ch - TIMER channel type.
* cmp_no - TIMER macth comparator ID type.
*
* Returned Value:
* None.
*
****************************************************************************/
void timer_clearintstatus(timer_chan_t timer_ch, timer_comp_id_t cmp_no)
{
uint32_t tmp_addr;
uint32_t tmp_val;
tmp_addr = TIMER_BASE + TIMER_TICR2_OFFSET + 4 * timer_ch;
tmp_val = BL_RD_WORD(tmp_addr);
tmp_val |= (1 << cmp_no);
BL_WR_WORD(tmp_addr, tmp_val);
}
/****************************************************************************
* Name: timer_init
*
* Description:
* TIMER initialization function.
*
* Input Parameters:
* timer_cfg - TIMER configuration structure pointer.
*
* Returned Value:
* None
*
****************************************************************************/
void timer_init(timer_cfg_t *timer_cfg)
{
timer_chan_t timer_ch = timer_cfg->timer_ch;
uint32_t tmp_val;
/* Configure timer clock source */
tmp_val = BL_RD_REG(TIMER_BASE, TIMER_TCCR);
if (timer_ch == TIMER_CH0)
{
tmp_val = BL_SET_REG_BITS_VAL(tmp_val, TIMER_CS_1, timer_cfg->clk_src);
}
else
{
tmp_val = BL_SET_REG_BITS_VAL(tmp_val, TIMER_CS_2, timer_cfg->clk_src);
}
BL_WR_REG(TIMER_BASE, TIMER_TCCR, tmp_val);
/* Configure timer clock division */
tmp_val = BL_RD_REG(TIMER_BASE, TIMER_TCDR);
if (timer_ch == TIMER_CH0)
{
tmp_val =
BL_SET_REG_BITS_VAL(tmp_val, TIMER_TCDR2, timer_cfg->clock_division);
}
else
{
tmp_val =
BL_SET_REG_BITS_VAL(tmp_val, TIMER_TCDR3, timer_cfg->clock_division);
}
BL_WR_REG(TIMER_BASE, TIMER_TCDR, tmp_val);
/* Configure timer count mode: preload or free run */
timer_setcountmode(timer_ch, timer_cfg->count_mode);
/* Configure timer preload trigger src */
timer_setpreloadtrigsrc(timer_ch, timer_cfg->pl_trig_src);
if (timer_cfg->count_mode == TIMER_COUNT_PRELOAD)
{
/* Configure timer preload value */
timer_setpreloadvalue(timer_ch, timer_cfg->pre_load_val);
}
/* Configure match compare values */
timer_setcompvalue(timer_ch, TIMER_COMP_ID_0, timer_cfg->match_val0);
timer_setcompvalue(timer_ch, TIMER_COMP_ID_1, timer_cfg->match_val1);
timer_setcompvalue(timer_ch, TIMER_COMP_ID_2, timer_cfg->match_val2);
}
/****************************************************************************
* Name: timer_enable
*
* Description:
* TIMER enable one channel function.
*
* Input Parameters:
* timer_ch - TIMER channel type.
*
* Returned Value:
* None.
*
****************************************************************************/
void timer_enable(timer_chan_t timer_ch)
{
uint32_t tmp_val;
tmp_val = BL_RD_REG(TIMER_BASE, TIMER_TCER);
tmp_val |= (1 << (timer_ch + 1));
BL_WR_REG(TIMER_BASE, TIMER_TCER, tmp_val);
}
/****************************************************************************
* Name: timer_disable
*
* Description:
* TIMER disable one channel function.
*
* Input Parameters:
* timer_ch - TIMER channel type.
*
* Returned Value:
* None.
*
****************************************************************************/
void timer_disable(timer_chan_t timer_ch)
{
uint32_t tmp_val;
tmp_val = BL_RD_REG(TIMER_BASE, TIMER_TCER);
tmp_val &= (~(1 << (timer_ch + 1)));
BL_WR_REG(TIMER_BASE, TIMER_TCER, tmp_val);
}
/****************************************************************************
* Name: timer_intmask
*
* Description:
* TIMER mask or unmask certain or all interrupt.
*
* Input Parameters:
* timer_ch - TIMER channel type.
* int_type - TIMER interrupt type.
* int_mask - TIMER interrupt mask value:1:disbale interrupt.0:enable
*interrupt.
*
* Returned Value:
* None.
*
****************************************************************************/
void timer_intmask(timer_chan_t timer_ch,
timer_int_t int_type,
uint32_t int_mask)
{
uint32_t tmp_addr;
uint32_t tmp_val;
tmp_addr = TIMER_BASE + TIMER_TIER2_OFFSET + 4 * timer_ch;
tmp_val = BL_RD_WORD(tmp_addr);
switch (int_type)
{
case TIMER_INT_COMP_0:
if (int_mask == 0)
{
/* Enable this interrupt */
BL_WR_WORD(tmp_addr, BL_SET_REG_BIT(tmp_val, TIMER_TIER_0));
}
else
{
/* Disable this interrupt */
BL_WR_WORD(tmp_addr, BL_CLR_REG_BIT(tmp_val, TIMER_TIER_0));
}
break;
case TIMER_INT_COMP_1:
if (int_mask == 0)
{
/* Enable this interrupt */
BL_WR_WORD(tmp_addr, BL_SET_REG_BIT(tmp_val, TIMER_TIER_1));
}
else
{
/* Disable this interrupt */
BL_WR_WORD(tmp_addr, BL_CLR_REG_BIT(tmp_val, TIMER_TIER_1));
}
break;
case TIMER_INT_COMP_2:
if (int_mask == 0)
{
/* Enable this interrupt */
BL_WR_WORD(tmp_addr, BL_SET_REG_BIT(tmp_val, TIMER_TIER_2));
}
else
{
/* Disable this interrupt */
BL_WR_WORD(tmp_addr, BL_CLR_REG_BIT(tmp_val, TIMER_TIER_2));
}
break;
case TIMER_INT_ALL:
if (int_mask == 0)
{
/* Enable this interrupt */
BL_WR_WORD(tmp_addr, BL_SET_REG_BIT(tmp_val, TIMER_TIER_0));
BL_WR_WORD(tmp_addr, BL_SET_REG_BIT(tmp_val, TIMER_TIER_1));
BL_WR_WORD(tmp_addr, BL_SET_REG_BIT(tmp_val, TIMER_TIER_2));
}
else
{
/* Disable this interrupt */
BL_WR_WORD(tmp_addr, BL_CLR_REG_BIT(tmp_val, TIMER_TIER_0));
BL_WR_WORD(tmp_addr, BL_CLR_REG_BIT(tmp_val, TIMER_TIER_1));
BL_WR_WORD(tmp_addr, BL_CLR_REG_BIT(tmp_val, TIMER_TIER_2));
}
break;
default:
break;
}
}
/****************************************************************************
* Name: wdt_set_clock
*
* Description:
* TIMER set watchdog clock source and clock division.
*
* Input Parameters:
* clk_src - Watchdog timer clock source type.
* div - Watchdog timer clock division value.
*
* Returned Value:
* None.
*
****************************************************************************/
void wdt_set_clock(timer_clksrc_t clk_src, uint8_t div)
{
uint32_t tmp_val;
/* Configure watchdog timer clock source */
tmp_val = BL_RD_REG(TIMER_BASE, TIMER_TCCR);
tmp_val = BL_SET_REG_BITS_VAL(tmp_val, TIMER_CS_WDT, clk_src);
BL_WR_REG(TIMER_BASE, TIMER_TCCR, tmp_val);
/* Configure watchdog timer clock divison */
tmp_val = BL_RD_REG(TIMER_BASE, TIMER_TCDR);
tmp_val = BL_SET_REG_BITS_VAL(tmp_val, TIMER_WCDR, div);
BL_WR_REG(TIMER_BASE, TIMER_TCDR, tmp_val);
}
/****************************************************************************
* Name: wdt_getmatchvalue
*
* Description:
* TIMER get watchdog match compare value.
*
* Input Parameters:
* None.
*
* Returned Value:
* Watchdog match comapre register value.
*
****************************************************************************/
uint32_t wdt_getmatchvalue(void)
{
uint32_t tmp_val;
WDT_ENABLE_ACCESS();
/* Get watchdog timer match register value */
tmp_val = BL_RD_REG(TIMER_BASE, TIMER_WMR);
return tmp_val;
}
/****************************************************************************
* Name: wdt_setcompvalue
*
* Description:
* TIMER set watchdog match compare value.
*
* Input Parameters:
* val - Watchdog match compare value
*
* Returned Value:
* None.
*
****************************************************************************/
void wdt_setcompvalue(uint16_t val)
{
WDT_ENABLE_ACCESS();
/* Set watchdog timer match register value */
BL_WR_REG(TIMER_BASE, TIMER_WMR, val);
}
/****************************************************************************
* Name: wdt_getcountervalue
*
* Description:
* TIMER get watchdog count register value.
*
* Input Parameters:
* None.
*
* Returned Value:
* Watchdog count register value.
*
****************************************************************************/
uint16_t wdt_getcountervalue(void)
{
uint32_t tmp_val;
WDT_ENABLE_ACCESS();
/* Get watchdog timer count register value */
tmp_val = BL_RD_REG(TIMER_BASE, TIMER_WVR);
return tmp_val;
}
/****************************************************************************
* Name: wdt_resetcountervalue
*
* Description:
* TIMER reset watchdog count register value.
*
* Input Parameters:
* None.
*
* Returned Value:
* None.
*
****************************************************************************/
void wdt_resetcountervalue(void)
{
uint32_t tmp_val;
/* Reset watchdog timer count register value */
WDT_ENABLE_ACCESS();
tmp_val = BL_RD_REG(TIMER_BASE, TIMER_WCR);
/* Set watchdog counter reset register bit0 to 1 */
BL_WR_REG(TIMER_BASE, TIMER_WCR, BL_SET_REG_BIT(tmp_val, TIMER_WCR));
}
/****************************************************************************
* Name: wdt_getresetstatus
*
* Description:
* TIMER get watchdog reset status.
*
* Input Parameters:
* None.
*
* Returned Value:
* 0 or 1.
*
****************************************************************************/
uint32_t wdt_getresetstatus(void)
{
uint32_t tmp_val;
uint32_t ret;
WDT_ENABLE_ACCESS();
/* Get watchdog status register */
tmp_val = BL_RD_REG(TIMER_BASE, TIMER_WSR);
ret = (BL_IS_REG_BIT_SET(tmp_val, TIMER_WTS)) ? 1 : 0;
return ret;
}
/****************************************************************************
* Name: wdt_clearresetstatus
*
* Description:
* TIMER clear watchdog reset status.
*
* Input Parameters:
* None.
*
* Returned Value:
* None.
*
****************************************************************************/
void wdt_clearresetstatus(void)
{
uint32_t tmp_val;
WDT_ENABLE_ACCESS();
tmp_val = BL_RD_REG(TIMER_BASE, TIMER_WSR);
/* Set watchdog status register */
BL_WR_REG(TIMER_BASE, TIMER_WSR, BL_CLR_REG_BIT(tmp_val, TIMER_WTS));
}
/****************************************************************************
* Name: wdt_enable
*
* Description:
* TIMER enable watchdog function.
*
* Input Parameters:
* None.
*
* Returned Value:
* None.
*
****************************************************************************/
void wdt_enable(void)
{
uint32_t tmp_val;
WDT_ENABLE_ACCESS();
tmp_val = BL_RD_REG(TIMER_BASE, TIMER_WMER);
BL_WR_REG(TIMER_BASE, TIMER_WMER, BL_SET_REG_BIT(tmp_val, TIMER_WE));
}
/****************************************************************************
* Name: wdt_disable
*
* Description:
* Watchdog timer disable function.
*
* Input Parameters:
* None.
*
* Returned Value:
* None.
*
****************************************************************************/
void wdt_disable(void)
{
uint32_t tmp_val;
WDT_ENABLE_ACCESS();
tmp_val = BL_RD_REG(TIMER_BASE, TIMER_WMER);
BL_WR_REG(TIMER_BASE, TIMER_WMER, BL_CLR_REG_BIT(tmp_val, TIMER_WE));
}
/****************************************************************************
* Name: wdt_intmask
*
* Description:
* Watchdog timer mask or unmask certain or all interrupt.
*
* Input Parameters:
* int_type - Watchdog interrupt type.
* int_mask - Watchdog interrupt mask value:BL_STD_MASK:disbale
*interrupt.BL_STD_UNMASK:enable interrupt.
*
* Returned Value:
* None.
*
****************************************************************************/
void wdt_intmask(wdt_int_t int_type, uint32_t int_mask)
{
uint32_t tmp_val;
WDT_ENABLE_ACCESS();
/* Deal with watchdog match/interrupt enable register,WRIE:watchdog
* reset/interrupt enable
*/
tmp_val = BL_RD_REG(TIMER_BASE, TIMER_WMER);
switch (int_type)
{
case WDT_INT:
if (int_mask == 0)
{
/* Enable this interrupt */
/* 0 means generates a watchdog interrupt,a watchdog timer reset is
* not generated
*/
BL_WR_REG(
TIMER_BASE, TIMER_WMER, BL_CLR_REG_BIT(tmp_val, TIMER_WRIE));
}
else
{
/* Disable this interrupt */
/* 1 means generates a watchdog timer reset,a watchdog interrupt is
* not generated
*/
BL_WR_REG(
TIMER_BASE, TIMER_WMER, BL_SET_REG_BIT(tmp_val, TIMER_WRIE));
}
break;
default:
break;
}
}

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/****************************************************************************
* boards/risc-v/bl602/evb/src/bl602_lowerhalf.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <sys/types.h>
#include <stdint.h>
#include <string.h>
#include <errno.h>
#include <nuttx/irq.h>
#include <nuttx/timers/timer.h>
#include <arch/board/board.h>
#include <hardware/bl602_glb.h>
#include <hardware/bl602_timer.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#define TIMER_MAX_VALUE (0xFFFFFFFF)
#define TIMER_CLK_DIV (159)
/****************************************************************************
* Private Types
****************************************************************************/
struct bl602_lowerhalf_s
{
FAR const struct timer_ops_s *ops; /* Lower half operations */
tccb_t callback; /* Current upper half interrupt callback */
FAR void *arg; /* Argument passed to upper half callback */
bool started; /* True: Timer has been started */
uint8_t irq; /* IRQ associated with this UART */
uint8_t tim; /* timer tim 0,1 */
};
/****************************************************************************
* Private Function Prototypes
****************************************************************************/
static int bl602_timer_handler(int irq, void *context, void *arg);
/* "Lower half" driver methods */
static int bl602_start(FAR struct timer_lowerhalf_s *lower);
static int bl602_stop(FAR struct timer_lowerhalf_s *lower);
static int bl602_getstatus(FAR struct timer_lowerhalf_s *lower,
FAR struct timer_status_s * status);
static int bl602_settimeout(FAR struct timer_lowerhalf_s *lower,
uint32_t timeout);
static void bl602_setcallback(FAR struct timer_lowerhalf_s *lower,
tccb_t callback,
FAR void * arg);
/****************************************************************************
* Private Data
****************************************************************************/
/* "Lower half" driver methods */
static const struct timer_ops_s g_timer_ops =
{
.start = bl602_start,
.stop = bl602_stop,
.getstatus = bl602_getstatus,
.settimeout = bl602_settimeout,
.setcallback = bl602_setcallback,
.ioctl = NULL,
};
#ifdef CONFIG_BL602_TIMER0
static struct bl602_lowerhalf_s g_tim1_lowerhalf =
{
.ops = &g_timer_ops,
.irq = BL602_IRQ_TIMER_CH0,
.tim = TIMER_CH0,
};
#endif
#ifdef CONFIG_BL602_TIMER1
static struct bl602_lowerhalf_s g_tim2_lowerhalf =
{
.ops = &g_timer_ops,
.irq = BL602_IRQ_TIMER_CH1,
.tim = TIMER_CH1,
};
#endif
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Name: bl602_timer_handler
*
* Description:
* Timer interrupt handler
*
* Input Parameters:
*
* Returned Value:
*
****************************************************************************/
static int bl602_timer_handler(int irq, void *context, void *arg)
{
FAR struct bl602_lowerhalf_s *priv = (FAR struct bl602_lowerhalf_s *)arg;
uint32_t next_interval_us = 0;
/* Clear Interrupt Bits */
uint32_t int_id;
uint32_t tmp_val;
uint32_t tmp_addr;
int_id = BL_RD_WORD(TIMER_BASE + TIMER_TMSR2_OFFSET + 4 * priv->tim);
tmp_addr = TIMER_BASE + TIMER_TICR2_OFFSET + 4 * priv->tim;
tmp_val = BL_RD_WORD(tmp_addr);
/* Comparator 0 match interrupt */
if (BL_IS_REG_BIT_SET(int_id, TIMER_TMSR_0))
{
BL_WR_WORD(tmp_addr, BL_SET_REG_BIT(tmp_val, TIMER_TCLR_0));
if (priv->callback(&next_interval_us, priv->arg))
{
if (next_interval_us > 0)
{
/* Set a value to the alarm */
timer_disable(priv->tim);
timer_setcompvalue(
priv->tim, TIMER_COMP_ID_0, next_interval_us);
timer_setpreloadvalue(priv->tim, 0);
timer_enable(priv->tim);
}
}
else
{
timer_disable(priv->tim);
timer_setpreloadvalue(priv->tim, 0);
}
}
/* Comparator 1 match interrupt */
if (BL_IS_REG_BIT_SET(int_id, TIMER_TMSR_1))
{
BL_WR_WORD(tmp_addr, BL_SET_REG_BIT(tmp_val, TIMER_TCLR_1));
}
/* Comparator 2 match interrupt */
if (BL_IS_REG_BIT_SET(int_id, TIMER_TMSR_2))
{
BL_WR_WORD(tmp_addr, BL_SET_REG_BIT(tmp_val, TIMER_TCLR_2));
}
return OK;
}
/****************************************************************************
* Name: bl602_start
*
* Description:
* Start the timer, resetting the time to the current timeout,
*
* Input Parameters:
* lower - A pointer the publicly visible representation of the
* "lower-half" driver state structure.
*
* Returned Value:
* Zero on success; a negated errno value on failure.
*
****************************************************************************/
static int bl602_start(FAR struct timer_lowerhalf_s *lower)
{
FAR struct bl602_lowerhalf_s *priv = (FAR struct bl602_lowerhalf_s *)lower;
if (!priv->started)
{
if (priv->callback == NULL)
{
return -EPERM;
}
timer_setpreloadvalue(priv->tim, 0);
irq_attach(priv->irq, bl602_timer_handler, (void *)priv);
up_enable_irq(priv->irq);
timer_intmask(priv->tim, TIMER_INT_COMP_0, 0);
timer_enable(priv->tim);
priv->started = true;
return OK;
}
/* Return EBUSY to indicate that the timer was already running */
return -EBUSY;
}
/****************************************************************************
* Name: bl602_stop
*
* Description:
* Stop the timer
*
* Input Parameters:
* lower - A pointer the publicly visible representation of the
* "lower-half" driver state structure.
*
* Returned Value:
* Zero on success; a negated errno value on failure.
*
****************************************************************************/
static int bl602_stop(FAR struct timer_lowerhalf_s *lower)
{
FAR struct bl602_lowerhalf_s *priv = (FAR struct bl602_lowerhalf_s *)lower;
/* timer disable */
if (priv->started)
{
timer_disable(priv->tim);
priv->started = false;
up_disable_irq(priv->irq);
timer_intmask(priv->tim, TIMER_INT_COMP_0, 1);
return OK;
}
/* Return ENODEV to indicate that the timer was not running */
return -ENODEV;
}
/****************************************************************************
* Name: bl602_getstatus
*
* Description:
* get timer status
*
* Input Parameters:
* lower - A pointer the publicly visible representation of the "lower-
* half" driver state structure.
* status - The location to return the status information.
*
* Returned Value:
* Zero on success; a negated errno value on failure.
*
****************************************************************************/
static int bl602_getstatus(FAR struct timer_lowerhalf_s *lower,
FAR struct timer_status_s * status)
{
FAR struct bl602_lowerhalf_s *priv = (FAR struct bl602_lowerhalf_s *)lower;
uint32_t current_count;
status->timeout = timer_getcompvalue(priv->tim, TIMER_COMP_ID_0);
current_count = timer_getcountervalue(priv->tim);
if (current_count < status->timeout)
{
status->timeleft = status->timeout - current_count;
}
else
{
status->timeleft = 0;
}
return 0;
}
/****************************************************************************
* Name: bl602_settimeout
*
* Description:
* Set a new timeout value (and reset the timer)
*
* Input Parameters:
* lower - A pointer the publicly visible representation of the
*"lower-half" driver state structure. timeout - The new timeout value in
*microseconds.
*
* Returned Value:
* Zero on success; a negated errno value on failure.
*
****************************************************************************/
static int bl602_settimeout(FAR struct timer_lowerhalf_s *lower,
uint32_t timeout)
{
FAR struct bl602_lowerhalf_s *priv = (FAR struct bl602_lowerhalf_s *)lower;
timer_setcompvalue(priv->tim, TIMER_COMP_ID_0, timeout);
return OK;
}
/****************************************************************************
* Name: bl602_setcallback
*
* Description:
* Call this user provided timeout handler.
*
* Input Parameters:
* lower - A pointer the publicly visible representation of the
*"lower-half" driver state structure. callback - The new timer expiration
*function pointer. If this function pointer is NULL, then the
*reset-on-expiration behavior is restored, arg - Argument that will be
*provided in the callback
*
* Returned Value:
* The previous timer expiration function pointer or NULL is there was
* no previous function pointer.
*
****************************************************************************/
static void bl602_setcallback(FAR struct timer_lowerhalf_s *lower,
tccb_t callback,
FAR void * arg)
{
struct bl602_lowerhalf_s *priv = (FAR struct bl602_lowerhalf_s *)lower;
irqstate_t flags = enter_critical_section();
/* Save the new callback */
priv->callback = callback;
priv->arg = arg;
leave_critical_section(flags);
}
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: bl602_timer_initialize
*
* Description:
* Bind the configuration timer to a timer lower half instance and
* register the timer drivers at 'devpath'
*
* Input Parameters:
* devpath - The full path to the timer device. This should be of the
* form /dev/timer0
* timer - the timer's number.
*
* Returned Value:
* Zero (OK) is returned on success; A negated errno value is returned
* to indicate the nature of any failure.
*
****************************************************************************/
int bl602_timer_initialize(FAR const char *devpath, int timer)
{
FAR struct bl602_lowerhalf_s *lower;
timer_cfg_t timstr;
switch (timer)
{
case 0:
#ifdef CONFIG_BL602_TIMER0
lower = &g_tim1_lowerhalf;
#endif
break;
case 1:
#ifdef CONFIG_BL602_TIMER1
lower = &g_tim2_lowerhalf;
#endif
break;
default:
return -ENODEV;
}
timstr.timer_ch = lower->tim; /* Timer channel */
timstr.clk_src = TIMER_CLKSRC_FCLK; /* Timer clock source */
timstr.pl_trig_src =
TIMER_PRELOAD_TRIG_COMP0; /* Timer count register preload trigger source
slelect */
timstr.count_mode = TIMER_COUNT_PRELOAD; /* Timer count mode */
timstr.clock_division = TIMER_CLK_DIV; /* Timer clock divison value */
timstr.match_val0 = TIMER_MAX_VALUE; /* Timer match 0 value 0 */
timstr.match_val1 = TIMER_MAX_VALUE; /* Timer match 1 value 0 */
timstr.match_val2 = TIMER_MAX_VALUE; /* Timer match 2 value 0 */
timstr.pre_load_val = TIMER_MAX_VALUE; /* Timer preload value */
glb_ahb_slave1_reset(BL_AHB_SLAVE1_TMR);
timer_intmask(lower->tim, TIMER_INT_ALL, 1);
/* timer disable */
timer_disable(lower->tim);
timer_init(&timstr);
/* Initialize the elements of lower half state structure */
lower->started = false;
lower->callback = NULL;
/* Register the timer driver as /dev/timerX. The returned value from
* timer_register is a handle that could be used with timer_unregister().
* REVISIT: The returned handle is discard here.
*/
FAR void *drvr =
timer_register(devpath, (FAR struct timer_lowerhalf_s *)lower);
if (drvr == NULL)
{
/* The actual cause of the failure may have been a failure to allocate
* perhaps a failure to register the timer driver (such as if the
* 'depath' were not unique). We know here but we return EEXIST to
* indicate the failure (implying the non-unique devpath).
*/
return -EEXIST;
}
return OK;
}

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/**
* incubator-nuttx/arch/risc-v/src/bl602/bl602_lowerhalf.h
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __ARCH_RISCV_SRC_BL602_TIM_LOWERHALF_H
#define __ARCH_RISCV_SRC_BL602_TIM_LOWERHALF_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <bl602_tim_lowerhalf.h>
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: bl602_timer_initialize
****************************************************************************/
int bl602_timer_initialize(FAR const char *devpath, uint8_t timer);
#endif /* __ARCH_RISCV_SRC_BL602_TIM_LOWERHALF_H */

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/****************************************************************************
* arch/risc-v/src/bl602/bl602_timerisr.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <time.h>
#include <debug.h>
#include <nuttx/arch.h>
#include <nuttx/clock.h>
#include <arch/board/board.h>
#include "riscv_arch.h"
#include "chip.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#define TICK_COUNT (160 * 1000 * 1000 / TICK_PER_SEC)
#define CLINT_BASE_ADDRESS 0x02000000
#define getreg64(a) (*(volatile uint64_t *)(a))
#define putreg64(v, a) (*(volatile uint64_t *)(a) = (v))
/****************************************************************************
* Private Data
****************************************************************************/
static bool _b_tick_started = false;
#define MTIMER_HIGH (CLINT_BASE_ADDRESS + 0xBFFC)
#define MTIMER_LOW (CLINT_BASE_ADDRESS + 0xBFF8)
#define MTIMER_CMP (CLINT_BASE_ADDRESS + 0x4000)
/****************************************************************************
* Private Functions
****************************************************************************/
/* bl602 mmio registers are a bit odd, by default they are byte-wide
* registers that are on 32-bit word boundaries. So a "32-bit" registers
* is actually broken into four bytes spanning a total address space of
* 16 bytes.
*/
static inline uint64_t bl602_clint_time_read(void)
{
uint64_t r = getreg32(MTIMER_HIGH);
r <<= 32;
r |= getreg32(MTIMER_LOW);
return r;
}
static inline uint64_t bl602_clint_time_cmp_read(void)
{
return getreg64(MTIMER_CMP);
}
static inline void bl602_clint_time_cmp_write(uint64_t v)
{
putreg64(v, MTIMER_CMP);
}
/****************************************************************************
* Name: bl602_reload_mtimecmp
****************************************************************************/
static void bl602_reload_mtimecmp(void)
{
irqstate_t flags = spin_lock_irqsave();
uint64_t current;
uint64_t next;
if (!_b_tick_started)
{
_b_tick_started = true;
current = bl602_clint_time_read();
}
else
{
current = bl602_clint_time_cmp_read();
}
next = current + TICK_COUNT;
bl602_clint_time_cmp_write(next);
spin_unlock_irqrestore(flags);
}
/****************************************************************************
* Name: bl602_timerisr
****************************************************************************/
static int bl602_timerisr(int irq, void *context, FAR void *arg)
{
bl602_reload_mtimecmp();
/* Process timer interrupt */
nxsched_process_timer();
return 0;
}
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: up_timer_initialize
*
* Description:
* This function is called during start-up to initialize
* the timer interrupt.
*
****************************************************************************/
void up_timer_initialize(void)
{
/* Attach timer interrupt handler */
irq_attach(BL602_IRQ_MTIMER, bl602_timerisr, NULL);
/* Reload CLINT mtimecmp */
bl602_reload_mtimecmp();
/* And enable the timer interrupt */
up_enable_irq(BL602_IRQ_MTIMER);
}

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arch/risc-v/src/bl602/bl602_vectors.S Normal file
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/****************************************************************************
* arch/risc-v/src/bl602/bl602_vectors.S
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/************************************************************************************
* Included Files
************************************************************************************/
.section .init
.global __reset_vec
.global __trap_vec
/****************************************************************************
* Name: __reset_vec
****************************************************************************/
__reset_vec:
jal __start
/****************************************************************************
* Name: exception_common
****************************************************************************/
__trap_vec:
j exception_common
nop

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/****************************************************************************
* arch/risc-v/include/bl602/chip.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_RISCV_INCLUDE_BL602_CHIP_H
#define __ARCH_RISCV_INCLUDE_BL602_CHIP_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <sys/types.h>
#include <stdint.h>
#include <stdbool.h>
#include <arch/irq.h>
#include "riscv_internal.h"
#endif /* __ARCH_RISCV_INCLUDE_BL602_CHIP_H */

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/****************************************************************************
* arch/risc-v/src/bl602/hardware/bl602_common.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_RISCV_SRC_BL602_HARDWARE_BL602_COMMON_H
#define __ARCH_RISCV_SRC_BL602_HARDWARE_BL602_COMMON_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <stdint.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#define BL602_FLASH_XIP_BASE 0x23000000
#define BL602_FLASH_XIP_END (0x23000000 + 16 * 1024 * 1024)
#define BL602_FLASH_XIP_REMAP0_BASE 0x33000000
#define BL602_FLASH_XIP_REMAP0_END (0x33000000 + 16 * 1024 * 1024)
#define BL602_FLASH_XIP_REMAP1_BASE 0x43000000
#define BL602_FLASH_XIP_REMAP1_END (0x43000000 + 16 * 1024 * 1024)
#define BL602_FLASH_XIP_REMAP2_BASE 0x53000000
#define BL602_FLASH_XIP_REMAP2_END (0x53000000 + 16 * 1024 * 1024)
#define BL602_WRAM_BASE 0x42020000
#define BL602_WRAM_END (0x42020000 + 176 * 1024)
#define BL602_WRAM_REMAP0_BASE 0x22020000
#define BL602_WRAM_REMAP0_END (0x22020000 + 176 * 1024)
#define BL602_WRAM_REMAP1_BASE 0x32020000
#define BL602_WRAM_REMAP1_END (0x32020000 + 176 * 1024)
#define BL602_WRAM_REMAP2_BASE 0x52020000
#define BL602_WRAM_REMAP2_END (0x52020000 + 176 * 1024)
#define BL602_TCM_BASE 0x22008000
#define BL602_TCM_END (0x22008000 + (96 + 176) * 1024)
#define BL602_TCM_REMAP0_BASE 0x32008000
#define BL602_TCM_REMAP0_END (0x32008000 + (96 + 176) * 1024)
#define BL602_TCM_REMAP1_BASE 0x42008000
#define BL602_TCM_REMAP1_END (0x42008000 + (96 + 176) * 1024)
#define BL602_TCM_REMAP2_BASE 0x52008000
#define BL602_TCM_REMAP2_END (0x52008000 + (96 + 176) * 1024)
/* BL602 peripherals base address */
#define GLB_BASE ((uint32_t)0x40000000)
#define RF_BASE ((uint32_t)0x40001000)
/* AUX module base address */
#define GPIP_BASE ((uint32_t)0x40002000)
/* Security Debug module base address */
#define SEC_DBG_BASE ((uint32_t)0x40003000)
/* Security Engine module base address */
#define SEC_ENG_BASE ((uint32_t)0x40004000)
/* Trustzone control security base address */
#define TZC_SEC_BASE ((uint32_t)0x40005000)
/* Trustzone control none-security base address */
#define TZC_NSEC_BASE ((uint32_t)0x40006000)
#define EF_DATA_BASE ((uint32_t)0x40007000)
#define EF_CTRL_BASE ((uint32_t)0x40007000)
#define CCI_BASE ((uint32_t)0x40008000)
/* L1 cache config base address */
#define L1C_BASE ((uint32_t)0x40009000)
#define UART0_BASE ((uint32_t)0x4000A000)
#define UART1_BASE ((uint32_t)0x4000A100)
#define SPI_BASE ((uint32_t)0x4000A200)
#define I2C_BASE ((uint32_t)0x4000A300)
#define PWM_BASE ((uint32_t)0x4000A400)
#define TIMER_BASE ((uint32_t)0x4000A500)
#define IR_BASE ((uint32_t)0x4000A600)
#define SF_CTRL_BASE ((uint32_t)0x4000B000)
#define SF_CTRL_BUF_BASE ((uint32_t)0x4000B700)
#define DMA_BASE ((uint32_t)0x4000C000)
#define SDU_BASE ((uint32_t)0x4000D000)
/* Power down sleep module base address */
#define PDS_BASE ((uint32_t)0x4000E000)
/* Hibernate module base address */
#define HBN_BASE ((uint32_t)0x4000F000)
/* Always on module base address */
#define AON_BASE ((uint32_t)0x4000F000)
#define HBN_RAM_BASE ((uint32_t)0x40010000)
#define BL_RD_WORD(addr) (*((volatile uint32_t *)(addr)))
#define BL_WR_WORD(addr, val) ((*(volatile uint32_t *)(addr)) = (val))
#define BL_RD_SHORT(addr) (*((volatile uint16_t *)(addr)))
#define BL_WR_SHORT(addr, val) ((*(volatile uint16_t *)(addr)) = (val))
#define BL_RD_BYTE(addr) (*((volatile uint8_t *)(addr)))
#define BL_WR_BYTE(addr, val) ((*(volatile uint8_t *)(addr)) = (val))
#define BL_RDWD_FRM_BYTEP(p) \
((p[3] << 24) | (p[2] << 16) | (p[1] << 8) | (p[0]))
#define BL_WRWD_TO_BYTEP(p, val) \
{ \
p[0] = val & 0xff; \
p[1] = (val >> 8) & 0xff; \
p[2] = (val >> 16) & 0xff; \
p[3] = (val >> 24) & 0xff; \
}
/**
* @brief Register access macro
*/
#define BL_RD_REG16(addr, regname) BL_RD_SHORT(addr + regname##_OFFSET)
#define BL_WR_REG16(addr, regname, val) \
BL_WR_SHORT(addr + regname##_OFFSET, val)
#define BL_RD_REG(addr, regname) BL_RD_WORD(addr + regname##_OFFSET)
#define BL_WR_REG(addr, regname, val) BL_WR_WORD(addr + regname##_OFFSET, val)
#define BL_SET_REG_BIT(val, bitname) ((val) | (1U << bitname##_POS))
#define BL_CLR_REG_BIT(val, bitname) ((val)&bitname##_UMSK)
#define BL_GET_REG_BITS_VAL(val, bitname) \
(((val)&bitname##_MSK) >> bitname##_POS)
#define BL_SET_REG_BITS_VAL(val, bitname, bitval) \
(((val)&bitname##_UMSK) | ((uint32_t)(bitval) << bitname##_POS))
#define BL_IS_REG_BIT_SET(val, bitname) \
(((val) & (1U << (bitname##_POS))) != 0)
#define __NOP() \
__asm volatile("nop") /* This implementation generates debug information \
*/
#define BL_DRV_DUMMY \
{ \
__NOP(); \
__NOP(); \
__NOP(); \
__NOP(); \
}
/* Std driver attribute macro */
#define ATTR_CLOCK_SECTION __attribute__((section(".sclock_rlt_code")))
#define ATTR_CLOCK_CONST_SECTION __attribute__((section(".sclock_rlt_const")))
#define ATTR_TCM_SECTION __attribute__((section(".tcm_code")))
#define ATTR_TCM_CONST_SECTION __attribute__((section(".tcm_const")))
#define ATTR_DTCM_SECTION __attribute__((section(".tcm_data")))
#define ATTR_HSRAM_SECTION __attribute__((section(".hsram_code")))
#define SystemCoreClockSet(val) BL_WR_WORD(0x4000f108, val)
#define SystemCoreClockGet(val) BL_RD_WORD(0x4000f108)
/****************************************************************************
* Public Types
****************************************************************************/
#ifndef __ASSEMBLY__
enum bl_ahb_slave1_e
{
BL_AHB_SLAVE1_GLB = 0x00,
BL_AHB_SLAVE1_RF = 0x01,
BL_AHB_SLAVE1_GPIP_PHY_AGC = 0x02,
BL_AHB_SLAVE1_SEC_DBG = 0x03,
BL_AHB_SLAVE1_SEC = 0x04,
BL_AHB_SLAVE1_TZ1 = 0x05,
BL_AHB_SLAVE1_TZ2 = 0x06,
BL_AHB_SLAVE1_EFUSE = 0x07,
BL_AHB_SLAVE1_CCI = 0x08,
BL_AHB_SLAVE1_L1C = 0x09,
BL_AHB_SLAVE1_RSVD0A = 0x0a,
BL_AHB_SLAVE1_SFC = 0x0b,
BL_AHB_SLAVE1_DMA = 0x0c,
BL_AHB_SLAVE1_SDU = 0x0d,
BL_AHB_SLAVE1_PDS_HBN_AON_HBNRAM = 0x0e,
BL_AHB_SLAVE1_RSVD0F = 0x0f,
BL_AHB_SLAVE1_UART0 = 0x10,
BL_AHB_SLAVE1_UART1 = 0x11,
BL_AHB_SLAVE1_SPI = 0x12,
BL_AHB_SLAVE1_I2C = 0x13,
BL_AHB_SLAVE1_PWM = 0x14,
BL_AHB_SLAVE1_TMR = 0x15,
BL_AHB_SLAVE1_IRR = 0x16,
BL_AHB_SLAVE1_CKS = 0x17,
BL_AHB_SLAVE1_MAX = 0x18,
};
/****************************************************************************
* Public Data
****************************************************************************/
#ifdef __cplusplus
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Inline Functions
****************************************************************************/
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
#undef EXTERN
#ifdef __cplusplus
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_RISCV_SRC_BL602_HARDWARE_BL602_COMMON_H */

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/****************************************************************************
* arch/risc-v/src/bl602/hardware/bl602_gpio.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_RISCV_SRC_BL602_HARDWARE_BL602_GPIO_H
#define __ARCH_RISCV_SRC_BL602_HARDWARE_BL602_GPIO_H
/****************************************************************************
* Included Files
****************************************************************************/
#include "hardware/bl602_common.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Input Floating Mode */
#define GPIO_MODE_INPUT ((uint32_t)0x00000000U)
/* Output Push Pull Mode */
#define GPIO_MODE_OUTPUT ((uint32_t)0x00000001U)
/* Alternate function */
#define GPIO_MODE_AF ((uint32_t)0x00000002U)
/* GPIO pull up */
#define GPIO_PULL_UP ((uint32_t)0x00000000U)
/* GPIO pull down */
#define GPIO_PULL_DOWN ((uint32_t)0x00000001U)
/* GPIO no pull up or down */
#define GPIO_PULL_NONE ((uint32_t)0x00000002U)
/* GPIO0 function definition */
#define GPIO0_FUN_SDIO_CLK 1
#define GPIO0_FUN_SF_D1 2
#define GPIO0_FUN_UNUSED3 3
#define GPIO0_FUN_SPI_MISO_SPI_MOSI 4
#define GPIO0_FUN_UNUSED5 5
#define GPIO0_FUN_I2C_SCL 6
#define GPIO0_FUN_UART_SIG0 7
#define GPIO0_FUN_PWM_CH0 8
#define GPIO0_FUN_FEM_GPIO_0 9
#define GPIO0_FUN_ATEST_IN 10
#define GPIO0_FUN_SWGPIO_0 11
#define GPIO0_FUN_E21_TMS 14
/* GPIO1 function definition */
#define GPIO1_FUN_SDIO_CMD 1
#define GPIO1_FUN_SF_D2 2
#define GPIO1_FUN_UNUSED3 3
#define GPIO1_FUN_SPI_MOSI_SPI_MISO 4
#define GPIO1_FUN_UNUSED5 5
#define GPIO1_FUN_I2C_SDA 6
#define GPIO1_FUN_UART_SIG1 7
#define GPIO1_FUN_PWM_CH1 8
#define GPIO1_FUN_FEM_GPIO_1 9
#define GPIO1_FUN_ATEST_IP 10
#define GPIO1_FUN_SWGPIO_1 11
#define GPIO1_FUN_E21_TDI 14
/* GPIO2 function definition */
#define GPIO2_FUN_SDIO_DAT0 1
#define GPIO2_FUN_SF_D3 2
#define GPIO2_FUN_UNUSED3 3
#define GPIO2_FUN_SPI_SS 4
#define GPIO2_FUN_UNUSED5 5
#define GPIO2_FUN_I2C_SCL 6
#define GPIO2_FUN_UART_SIG2 7
#define GPIO2_FUN_PWM_CH2 8
#define GPIO2_FUN_FEM_GPIO_2 9
#define GPIO2_FUN_ATEST_QN 10
#define GPIO2_FUN_SWGPIO_2 11
#define GPIO2_FUN_E21_TCK 14
/* GPIO3 function definition */
#define GPIO3_FUN_SDIO_DAT1 1
#define GPIO3_FUN_UNUSED2 2
#define GPIO3_FUN_UNUSED3 3
#define GPIO3_FUN_SPI_SCLK 4
#define GPIO3_FUN_UNUSED5 5
#define GPIO3_FUN_I2C_SDA 6
#define GPIO3_FUN_UART_SIG3 7
#define GPIO3_FUN_PWM_CH3 8
#define GPIO3_FUN_FEM_GPIO_3 9
#define GPIO3_FUN_ATEST_QP 10
#define GPIO3_FUN_SWGPIO_3 11
#define GPIO3_FUN_E21_TDO 14
/* GPIO4 function definition */
#define GPIO4_FUN_SDIO_DAT2 1
#define GPIO4_FUN_UNUSED2 2
#define GPIO4_FUN_UNUSED3 3
#define GPIO4_FUN_SPI_MISO_SPI_MOSI 4
#define GPIO4_FUN_UNUSED5 5
#define GPIO4_FUN_I2C_SCL 6
#define GPIO4_FUN_UART_SIG4 7
#define GPIO4_FUN_PWM_CH4 8
#define GPIO4_FUN_FEM_GPIO_0 9
#define GPIO4_FUN_GPIP_CH1 10
#define GPIO4_FUN_SWGPIO_4 11
#define GPIO4_FUN_E21_TMS 14
/* GPIO5 function definition */
#define GPIO5_FUN_SDIO_DAT3 1
#define GPIO5_FUN_UNUSED2 2
#define GPIO5_FUN_UNUSED3 3
#define GPIO5_FUN_SPI_MOSI_SPI_MISO 4
#define GPIO5_FUN_UNUSED5 5
#define GPIO5_FUN_I2C_SDA 6
#define GPIO5_FUN_UART_SIG5 7
#define GPIO5_FUN_PWM_CH0 8
#define GPIO5_FUN_FEM_GPIO_1 9
#define GPIO5_FUN_GPIP_CH4 10
#define GPIO5_FUN_SWGPIO_5 11
#define GPIO5_FUN_E21_TDI 14
/* GPIO6 function definition */
#define GPIO6_FUN_UNUSED1 1
#define GPIO6_FUN_UNUSED2 2
#define GPIO6_FUN_UNUSED3 3
#define GPIO6_FUN_SPI_SS 4
#define GPIO6_FUN_UNUSED5 5
#define GPIO6_FUN_I2C_SCL 6
#define GPIO6_FUN_UART_SIG6 7
#define GPIO6_FUN_PWM_CH1 8
#define GPIO6_FUN_FEM_GPIO_2 9
#define GPIO6_FUN_GPIP_CH5 10
#define GPIO6_FUN_SWGPIO_6 11
#define GPIO6_FUN_E21_TCK 14
/* GPIO7 function definition */
#define GPIO7_FUN_UNUSED1 1
#define GPIO7_FUN_UNUSED2 2
#define GPIO7_FUN_UNUSED3 3
#define GPIO7_FUN_SPI_SCLK 4
#define GPIO7_FUN_UNUSED5 5
#define GPIO7_FUN_I2C_SDA 6
#define GPIO7_FUN_UART_SIG7 7
#define GPIO7_FUN_PWM_CH2 8
#define GPIO7_FUN_FEM_GPIO_3 9
#define GPIO7_FUN_UNUSED10 10
#define GPIO7_FUN_SWGPIO_7 11
#define GPIO7_FUN_E21_TDO 14
/* GPIO8 function definition */
#define GPIO8_FUN_UNUSED1 1
#define GPIO8_FUN_UNUSED2 2
#define GPIO8_FUN_UNUSED3 3
#define GPIO8_FUN_SPI_MISO_SPI_MOSI 4
#define GPIO8_FUN_UNUSED5 5
#define GPIO8_FUN_I2C_SCL 6
#define GPIO8_FUN_UART_SIG0 7
#define GPIO8_FUN_PWM_CH3 8
#define GPIO8_FUN_FEM_GPIO_0 9
#define GPIO8_FUN_UNUSED10 10
#define GPIO8_FUN_SWGPIO_8 11
#define GPIO8_FUN_E21_TMS 14
/* GPIO9 function definition */
#define GPIO9_FUN_UNUSED1 1
#define GPIO9_FUN_UNUSED2 2
#define GPIO9_FUN_UNUSED3 3
#define GPIO9_FUN_SPI_MOSI_SPI_MISO 4
#define GPIO9_FUN_UNUSED5 5
#define GPIO9_FUN_I2C_SDA 6
#define GPIO9_FUN_UART_SIG1 7
#define GPIO9_FUN_PWM_CH4 8
#define GPIO9_FUN_FEM_GPIO_1 9
#define GPIO9_FUN_GPIP_CH6_GPIP_CH7 10
#define GPIO9_FUN_SWGPIO_9 11
#define GPIO9_FUN_E21_TDI 14
/* GPIO10 function definition */
#define GPIO10_FUN_UNUSED1 1
#define GPIO10_FUN_UNUSED2 2
#define GPIO10_FUN_UNUSED3 3
#define GPIO10_FUN_SPI_SS 4
#define GPIO10_FUN_UNUSED5 5
#define GPIO10_FUN_I2C_SCL 6
#define GPIO10_FUN_UART_SIG2 7
#define GPIO10_FUN_PWM_CH0 8
#define GPIO10_FUN_FEM_GPIO_2 9
#define GPIO10_FUN_MICBIAS_GPIP_CH8_GPIP_CH9 10
#define GPIO10_FUN_SWGPIO_10 11
#define GPIO10_FUN_E21_TCK 14
/* GPIO11 function definition */
#define GPIO11_FUN_UNUSED1 1
#define GPIO11_FUN_UNUSED2 2
#define GPIO11_FUN_UNUSED3 3
#define GPIO11_FUN_SPI_SCLK 4
#define GPIO11_FUN_UNUSED5 5
#define GPIO11_FUN_I2C_SDA 6
#define GPIO11_FUN_UART_SIG3 7
#define GPIO11_FUN_PWM_CH1 8
#define GPIO11_FUN_FEM_GPIO_3 9
#define GPIO11_FUN_IRLED_OUT_GPIP_CH10 10
#define GPIO11_FUN_SWGPIO_11 11
#define GPIO11_FUN_E21_TDO 14
/* GPIO12 function definition */
#define GPIO12_FUN_UNUSED1 1
#define GPIO12_FUN_UNUSED2 2
#define GPIO12_FUN_UNUSED3 3
#define GPIO12_FUN_SPI_MISO_SPI_MOSI 4
#define GPIO12_FUN_UNUSED5 5
#define GPIO12_FUN_I2C_SCL 6
#define GPIO12_FUN_UART_SIG4 7
#define GPIO12_FUN_PWM_CH2 8
#define GPIO12_FUN_FEM_GPIO_0 9
#define GPIO12_FUN_GPIP_CH0_GPADC_VREF_EXT 10
#define GPIO12_FUN_SWGPIO_12 11
#define GPIO12_FUN_E21_TMS 14
/* GPIO13 function definition */
#define GPIO13_FUN_UNUSED1 1
#define GPIO13_FUN_UNUSED2 2
#define GPIO13_FUN_UNUSED3 3
#define GPIO13_FUN_SPI_MOSI_SPI_MISO 4
#define GPIO13_FUN_UNUSED5 5
#define GPIO13_FUN_I2C_SDA 6
#define GPIO13_FUN_UART_SIG5 7
#define GPIO13_FUN_PWM_CH3 8
#define GPIO13_FUN_FEM_GPIO_1 9
#define GPIO13_FUN_GPIP_CH3 10
#define GPIO13_FUN_SWGPIO_13 11
#define GPIO13_FUN_E21_TDI 14
/* GPIO14 function definition */
#define GPIO14_FUN_UNUSED1 1
#define GPIO14_FUN_UNUSED2 2
#define GPIO14_FUN_UNUSED3 3
#define GPIO14_FUN_SPI_SS 4
#define GPIO14_FUN_UNUSED5 5
#define GPIO14_FUN_I2C_SCL 6
#define GPIO14_FUN_UART_SIG6 7
#define GPIO14_FUN_PWM_CH4 8
#define GPIO14_FUN_FEM_GPIO_2 9
#define GPIO14_FUN_GPIP_CH2 10
#define GPIO14_FUN_SWGPIO_14 11
#define GPIO14_FUN_E21_TCK 14
/* GPIO15 function definition */
#define GPIO15_FUN_UNUSED1 1
#define GPIO15_FUN_UNUSED2 2
#define GPIO15_FUN_UNUSED3 3
#define GPIO15_FUN_SPI_SCLK 4
#define GPIO15_FUN_UNUSED5 5
#define GPIO15_FUN_I2C_SDA 6
#define GPIO15_FUN_UART_SIG7 7
#define GPIO15_FUN_PWM_CH0 8
#define GPIO15_FUN_FEM_GPIO_3 9
#define GPIO15_FUN_PSW_IRRCV_OUT_GPIP_CH11 10
#define GPIO15_FUN_SWGPIO_15 11
#define GPIO15_FUN_E21_TDO 14
/* GPIO16 function definition */
#define GPIO16_FUN_UNUSED1 1
#define GPIO16_FUN_UNUSED2 2
#define GPIO16_FUN_UNUSED3 3
#define GPIO16_FUN_SPI_MISO_SPI_MOSI 4
#define GPIO16_FUN_UNUSED5 5
#define GPIO16_FUN_I2C_SCL 6
#define GPIO16_FUN_UART_SIG0 7
#define GPIO16_FUN_PWM_CH1 8
#define GPIO16_FUN_FEM_GPIO_0 9
#define GPIO16_FUN_UNUSED10 10
#define GPIO16_FUN_SWGPIO_16 11
#define GPIO16_FUN_E21_TMS 14
/* GPIO17 function definition */
#define GPIO17_FUN_UNUSED1 1
#define GPIO17_FUN_SF_D3 2
#define GPIO17_FUN_UNUSED3 3
#define GPIO17_FUN_SPI_MOSI_SPI_MISO 4
#define GPIO17_FUN_UNUSED5 5
#define GPIO17_FUN_I2C_SDA 6
#define GPIO17_FUN_UART_SIG1 7
#define GPIO17_FUN_PWM_CH2 8
#define GPIO17_FUN_FEM_GPIO_1 9
#define GPIO17_FUN_PMIP_DC_TP_OUT 10
#define GPIO17_FUN_SWGPIO_17 11
#define GPIO17_FUN_E21_TDI 14
/* GPIO18 function definition */
#define GPIO18_FUN_UNUSED1 1
#define GPIO18_FUN_SF_D2 2
#define GPIO18_FUN_UNUSED3 3
#define GPIO18_FUN_SPI_SS 4
#define GPIO18_FUN_UNUSED5 5
#define GPIO18_FUN_I2C_SCL 6
#define GPIO18_FUN_UART_SIG2 7
#define GPIO18_FUN_PWM_CH3 8
#define GPIO18_FUN_FEM_GPIO_2 9
#define GPIO18_FUN_UNUSED10 10
#define GPIO18_FUN_SWGPIO_18 11
#define GPIO18_FUN_E21_TCK 14
/* GPIO19 function definition */
#define GPIO19_FUN_UNUSED1 1
#define GPIO19_FUN_SF_D1 2
#define GPIO19_FUN_UNUSED3 3
#define GPIO19_FUN_SPI_SCLK 4
#define GPIO19_FUN_UNUSED5 5
#define GPIO19_FUN_I2C_SDA 6
#define GPIO19_FUN_UART_SIG3 7
#define GPIO19_FUN_PWM_CH4 8
#define GPIO19_FUN_FEM_GPIO_3 9
#define GPIO19_FUN_UNUSED10 10
#define GPIO19_FUN_SWGPIO_19 11
#define GPIO19_FUN_E21_TDO 14
/* GPIO20 function definition */
#define GPIO20_FUN_UNUSED1 1
#define GPIO20_FUN_SF_D0 2
#define GPIO20_FUN_UNUSED3 3
#define GPIO20_FUN_SPI_MISO_SPI_MOSI 4
#define GPIO20_FUN_UNUSED5 5
#define GPIO20_FUN_I2C_SCL 6
#define GPIO20_FUN_UART_SIG4 7
#define GPIO20_FUN_PWM_CH0 8
#define GPIO20_FUN_FEM_GPIO_0 9
#define GPIO20_FUN_UNUSED10 10
#define GPIO20_FUN_SWGPIO_20 11
#define GPIO20_FUN_E21_TMS 14
/* GPIO21 function definition */
#define GPIO21_FUN_UNUSED1 1
#define GPIO21_FUN_SF_CS 2
#define GPIO21_FUN_UNUSED3 3
#define GPIO21_FUN_SPI_MOSI_SPI_MISO 4
#define GPIO21_FUN_UNUSED5 5
#define GPIO21_FUN_I2C_SDA 6
#define GPIO21_FUN_UART_SIG5 7
#define GPIO21_FUN_PWM_CH1 8
#define GPIO21_FUN_FEM_GPIO_1 9
#define GPIO21_FUN_UNUSED10 10
#define GPIO21_FUN_SWGPIO_21 11
#define GPIO21_FUN_E21_TDI 14
/* GPIO22 function definition */
#define GPIO22_FUN_UNUSED1 1
#define GPIO22_FUN_SF_CLK_OUT 2
#define GPIO22_FUN_UNUSED3 3
#define GPIO22_FUN_SPI_SS 4
#define GPIO22_FUN_UNUSED5 5
#define GPIO22_FUN_I2C_SCL 6
#define GPIO22_FUN_UART_SIG6 7
#define GPIO22_FUN_PWM_CH2 8
#define GPIO22_FUN_FEM_GPIO_2 9
#define GPIO22_FUN_UNUSED10 10
#define GPIO22_FUN_SWGPIO_22 11
#define GPIO22_FUN_E21_TCK 14
/****************************************************************************
* Public Types
****************************************************************************/
#ifndef __ASSEMBLY__
enum gpio_pins_e
{
GLB_GPIO_PIN_0 = 0,
GLB_GPIO_PIN_1,
GLB_GPIO_PIN_2,
GLB_GPIO_PIN_3,
GLB_GPIO_PIN_4,
GLB_GPIO_PIN_5,
GLB_GPIO_PIN_6,
GLB_GPIO_PIN_7,
GLB_GPIO_PIN_8,
GLB_GPIO_PIN_9,
GLB_GPIO_PIN_10,
GLB_GPIO_PIN_11,
GLB_GPIO_PIN_12,
GLB_GPIO_PIN_13,
GLB_GPIO_PIN_14,
GLB_GPIO_PIN_15,
GLB_GPIO_PIN_16,
GLB_GPIO_PIN_17,
GLB_GPIO_PIN_18,
GLB_GPIO_PIN_19,
GLB_GPIO_PIN_20,
GLB_GPIO_PIN_21,
GLB_GPIO_PIN_22,
GLB_GPIO_PIN_MAX
};
enum gpio_fun_e
{
GPIO_FUN_SDIO = 1,
GPIO_FUN_FLASH = 2,
GPIO_FUN_SPI = 4,
GPIO_FUN_I2C = 6,
GPIO_FUN_UART = 7,
GPIO_FUN_PWM = 8,
GPIO_FUN_EXT_PA = 8,
GPIO_FUN_ANALOG = 10,
GPIO_FUN_SWGPIO = 11,
GPIO_FUN_JTAG = 14
};
struct gpio_cfg_s
{
enum gpio_pins_e gpio_pin;
enum gpio_fun_e gpio_fun;
int gpio_mode;
int pull_type;
int drive;
int smt_ctrl;
};
/****************************************************************************
* Public Data
****************************************************************************/
#ifdef __cplusplus
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Inline Functions
****************************************************************************/
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: gpio_init
*
* Description:
* Init a gpio pin.
*
* Input Parameters:
* cfg: gpio configuration
*
* Returned Value:
* Description of the value returned by this function (if any),
* including an enumeration of all possible error values.
*
* Assumptions/Limitations:
* Anything else that one might need to know to use this function.
*
****************************************************************************/
EXTERN void gpio_init(struct gpio_cfg_s *cfg);
#undef EXTERN
#ifdef __cplusplus
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_RISCV_SRC_BL602_HARDWARE_BL602_GPIO_H */

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/****************************************************************************
* arch/risc-v/src/bl602/hardware/bl602_timer.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_RISCV_SRC_BL602_HARDWARE_BL602_TIMER_H
#define __ARCH_RISCV_SRC_BL602_HARDWARE_BL602_TIMER_H
/****************************************************************************
* Included Files
****************************************************************************/
#include "hardware/bl602_common.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* 0x0 : TCCR */
#define TIMER_TCCR_OFFSET (0x0)
#define TIMER_CS_1 TIMER_CS_1
#define TIMER_CS_1_POS (2U)
#define TIMER_CS_1_LEN (2U)
#define TIMER_CS_1_MSK (((1U << TIMER_CS_1_LEN) - 1) << TIMER_CS_1_POS)
#define TIMER_CS_1_UMSK (~(((1U << TIMER_CS_1_LEN) - 1) << TIMER_CS_1_POS))
#define TIMER_CS_2 TIMER_CS_2
#define TIMER_CS_2_POS (5U)
#define TIMER_CS_2_LEN (2U)
#define TIMER_CS_2_MSK (((1U << TIMER_CS_2_LEN) - 1) << TIMER_CS_2_POS)
#define TIMER_CS_2_UMSK (~(((1U << TIMER_CS_2_LEN) - 1) << TIMER_CS_2_POS))
#define TIMER_CS_WDT TIMER_CS_WDT
#define TIMER_CS_WDT_POS (8U)
#define TIMER_CS_WDT_LEN (2U)
#define TIMER_CS_WDT_MSK (((1U << TIMER_CS_WDT_LEN) - 1) << TIMER_CS_WDT_POS)
#define TIMER_CS_WDT_UMSK \
(~(((1U << TIMER_CS_WDT_LEN) - 1) << TIMER_CS_WDT_POS))
/* 0x10 : TMR2_0 */
#define TIMER_TMR2_0_OFFSET (0x10)
#define TIMER_TMR TIMER_TMR
#define TIMER_TMR_POS (0U)
#define TIMER_TMR_LEN (32U)
#define TIMER_TMR_MSK (((1U << TIMER_TMR_LEN) - 1) << TIMER_TMR_POS)
#define TIMER_TMR_UMSK (~(((1U << TIMER_TMR_LEN) - 1) << TIMER_TMR_POS))
/* 0x14 : TMR2_1 */
#define TIMER_TMR2_1_OFFSET (0x14)
#define TIMER_TMR TIMER_TMR
#define TIMER_TMR_POS (0U)
#define TIMER_TMR_LEN (32U)
#define TIMER_TMR_MSK (((1U << TIMER_TMR_LEN) - 1) << TIMER_TMR_POS)
#define TIMER_TMR_UMSK (~(((1U << TIMER_TMR_LEN) - 1) << TIMER_TMR_POS))
/* 0x18 : TMR2_2 */
#define TIMER_TMR2_2_OFFSET (0x18)
#define TIMER_TMR TIMER_TMR
#define TIMER_TMR_POS (0U)
#define TIMER_TMR_LEN (32U)
#define TIMER_TMR_MSK (((1U << TIMER_TMR_LEN) - 1) << TIMER_TMR_POS)
#define TIMER_TMR_UMSK (~(((1U << TIMER_TMR_LEN) - 1) << TIMER_TMR_POS))
/* 0x1C : TMR3_0 */
#define TIMER_TMR3_0_OFFSET (0x1C)
#define TIMER_TMR TIMER_TMR
#define TIMER_TMR_POS (0U)
#define TIMER_TMR_LEN (32U)
#define TIMER_TMR_MSK (((1U << TIMER_TMR_LEN) - 1) << TIMER_TMR_POS)
#define TIMER_TMR_UMSK (~(((1U << TIMER_TMR_LEN) - 1) << TIMER_TMR_POS))
/* 0x20 : TMR3_1 */
#define TIMER_TMR3_1_OFFSET (0x20)
#define TIMER_TMR TIMER_TMR
#define TIMER_TMR_POS (0U)
#define TIMER_TMR_LEN (32U)
#define TIMER_TMR_MSK (((1U << TIMER_TMR_LEN) - 1) << TIMER_TMR_POS)
#define TIMER_TMR_UMSK (~(((1U << TIMER_TMR_LEN) - 1) << TIMER_TMR_POS))
/* 0x24 : TMR3_2 */
#define TIMER_TMR3_2_OFFSET (0x24)
#define TIMER_TMR TIMER_TMR
#define TIMER_TMR_POS (0U)
#define TIMER_TMR_LEN (32U)
#define TIMER_TMR_MSK (((1U << TIMER_TMR_LEN) - 1) << TIMER_TMR_POS)
#define TIMER_TMR_UMSK (~(((1U << TIMER_TMR_LEN) - 1) << TIMER_TMR_POS))
/* 0x2C : TCR2 */
#define TIMER_TCR2_OFFSET (0x2C)
#define TIMER_TCR TIMER_TCR
#define TIMER_TCR_POS (0U)
#define TIMER_TCR_LEN (32U)
#define TIMER_TCR_MSK (((1U << TIMER_TCR_LEN) - 1) << TIMER_TCR_POS)
#define TIMER_TCR_UMSK (~(((1U << TIMER_TCR_LEN) - 1) << TIMER_TCR_POS))
/* 0x30 : TCR3 */
#define TIMER_TCR3_OFFSET (0x30)
#define TIMER_TCR3_COUNTER TIMER_TCR3_COUNTER
#define TIMER_TCR3_COUNTER_POS (0U)
#define TIMER_TCR3_COUNTER_LEN (32U)
#define TIMER_TCR3_COUNTER_MSK \
(((1U << TIMER_TCR3_COUNTER_LEN) - 1) << TIMER_TCR3_COUNTER_POS)
#define TIMER_TCR3_COUNTER_UMSK \
(~(((1U << TIMER_TCR3_COUNTER_LEN) - 1) << TIMER_TCR3_COUNTER_POS))
/* 0x38 : TMSR2 */
#define TIMER_TMSR2_OFFSET (0x38)
#define TIMER_TMSR_0 TIMER_TMSR_0
#define TIMER_TMSR_0_POS (0U)
#define TIMER_TMSR_0_LEN (1U)
#define TIMER_TMSR_0_MSK (((1U << TIMER_TMSR_0_LEN) - 1) << TIMER_TMSR_0_POS)
#define TIMER_TMSR_0_UMSK \
(~(((1U << TIMER_TMSR_0_LEN) - 1) << TIMER_TMSR_0_POS))
#define TIMER_TMSR_1 TIMER_TMSR_1
#define TIMER_TMSR_1_POS (1U)
#define TIMER_TMSR_1_LEN (1U)
#define TIMER_TMSR_1_MSK (((1U << TIMER_TMSR_1_LEN) - 1) << TIMER_TMSR_1_POS)
#define TIMER_TMSR_1_UMSK \
(~(((1U << TIMER_TMSR_1_LEN) - 1) << TIMER_TMSR_1_POS))
#define TIMER_TMSR_2 TIMER_TMSR_2
#define TIMER_TMSR_2_POS (2U)
#define TIMER_TMSR_2_LEN (1U)
#define TIMER_TMSR_2_MSK (((1U << TIMER_TMSR_2_LEN) - 1) << TIMER_TMSR_2_POS)
#define TIMER_TMSR_2_UMSK \
(~(((1U << TIMER_TMSR_2_LEN) - 1) << TIMER_TMSR_2_POS))
/* 0x3C : TMSR3 */
#define TIMER_TMSR3_OFFSET (0x3C)
#define TIMER_TMSR_0 TIMER_TMSR_0
#define TIMER_TMSR_0_POS (0U)
#define TIMER_TMSR_0_LEN (1U)
#define TIMER_TMSR_0_MSK (((1U << TIMER_TMSR_0_LEN) - 1) << TIMER_TMSR_0_POS)
#define TIMER_TMSR_0_UMSK \
(~(((1U << TIMER_TMSR_0_LEN) - 1) << TIMER_TMSR_0_POS))
#define TIMER_TMSR_1 TIMER_TMSR_1
#define TIMER_TMSR_1_POS (1U)
#define TIMER_TMSR_1_LEN (1U)
#define TIMER_TMSR_1_MSK (((1U << TIMER_TMSR_1_LEN) - 1) << TIMER_TMSR_1_POS)
#define TIMER_TMSR_1_UMSK \
(~(((1U << TIMER_TMSR_1_LEN) - 1) << TIMER_TMSR_1_POS))
#define TIMER_TMSR_2 TIMER_TMSR_2
#define TIMER_TMSR_2_POS (2U)
#define TIMER_TMSR_2_LEN (1U)
#define TIMER_TMSR_2_MSK (((1U << TIMER_TMSR_2_LEN) - 1) << TIMER_TMSR_2_POS)
#define TIMER_TMSR_2_UMSK \
(~(((1U << TIMER_TMSR_2_LEN) - 1) << TIMER_TMSR_2_POS))
/* 0x44 : TIER2 */
#define TIMER_TIER2_OFFSET (0x44)
#define TIMER_TIER_0 TIMER_TIER_0
#define TIMER_TIER_0_POS (0U)
#define TIMER_TIER_0_LEN (1U)
#define TIMER_TIER_0_MSK (((1U << TIMER_TIER_0_LEN) - 1) << TIMER_TIER_0_POS)
#define TIMER_TIER_0_UMSK \
(~(((1U << TIMER_TIER_0_LEN) - 1) << TIMER_TIER_0_POS))
#define TIMER_TIER_1 TIMER_TIER_1
#define TIMER_TIER_1_POS (1U)
#define TIMER_TIER_1_LEN (1U)
#define TIMER_TIER_1_MSK (((1U << TIMER_TIER_1_LEN) - 1) << TIMER_TIER_1_POS)
#define TIMER_TIER_1_UMSK \
(~(((1U << TIMER_TIER_1_LEN) - 1) << TIMER_TIER_1_POS))
#define TIMER_TIER_2 TIMER_TIER_2
#define TIMER_TIER_2_POS (2U)
#define TIMER_TIER_2_LEN (1U)
#define TIMER_TIER_2_MSK (((1U << TIMER_TIER_2_LEN) - 1) << TIMER_TIER_2_POS)
#define TIMER_TIER_2_UMSK \
(~(((1U << TIMER_TIER_2_LEN) - 1) << TIMER_TIER_2_POS))
/* 0x48 : TIER3 */
#define TIMER_TIER3_OFFSET (0x48)
#define TIMER_TIER_0 TIMER_TIER_0
#define TIMER_TIER_0_POS (0U)
#define TIMER_TIER_0_LEN (1U)
#define TIMER_TIER_0_MSK (((1U << TIMER_TIER_0_LEN) - 1) << TIMER_TIER_0_POS)
#define TIMER_TIER_0_UMSK \
(~(((1U << TIMER_TIER_0_LEN) - 1) << TIMER_TIER_0_POS))
#define TIMER_TIER_1 TIMER_TIER_1
#define TIMER_TIER_1_POS (1U)
#define TIMER_TIER_1_LEN (1U)
#define TIMER_TIER_1_MSK (((1U << TIMER_TIER_1_LEN) - 1) << TIMER_TIER_1_POS)
#define TIMER_TIER_1_UMSK \
(~(((1U << TIMER_TIER_1_LEN) - 1) << TIMER_TIER_1_POS))
#define TIMER_TIER_2 TIMER_TIER_2
#define TIMER_TIER_2_POS (2U)
#define TIMER_TIER_2_LEN (1U)
#define TIMER_TIER_2_MSK (((1U << TIMER_TIER_2_LEN) - 1) << TIMER_TIER_2_POS)
#define TIMER_TIER_2_UMSK \
(~(((1U << TIMER_TIER_2_LEN) - 1) << TIMER_TIER_2_POS))
/* 0x50 : TPLVR2 */
#define TIMER_TPLVR2_OFFSET (0x50)
#define TIMER_TPLVR TIMER_TPLVR
#define TIMER_TPLVR_POS (0U)
#define TIMER_TPLVR_LEN (32U)
#define TIMER_TPLVR_MSK (((1U << TIMER_TPLVR_LEN) - 1) << TIMER_TPLVR_POS)
#define TIMER_TPLVR_UMSK (~(((1U << TIMER_TPLVR_LEN) - 1) << TIMER_TPLVR_POS))
/* 0x54 : TPLVR3 */
#define TIMER_TPLVR3_OFFSET (0x54)
#define TIMER_TPLVR TIMER_TPLVR
#define TIMER_TPLVR_POS (0U)
#define TIMER_TPLVR_LEN (32U)
#define TIMER_TPLVR_MSK (((1U << TIMER_TPLVR_LEN) - 1) << TIMER_TPLVR_POS)
#define TIMER_TPLVR_UMSK (~(((1U << TIMER_TPLVR_LEN) - 1) << TIMER_TPLVR_POS))
/* 0x5C : TPLCR2 */
#define TIMER_TPLCR2_OFFSET (0x5C)
#define TIMER_TPLCR TIMER_TPLCR
#define TIMER_TPLCR_POS (0U)
#define TIMER_TPLCR_LEN (2U)
#define TIMER_TPLCR_MSK (((1U << TIMER_TPLCR_LEN) - 1) << TIMER_TPLCR_POS)
#define TIMER_TPLCR_UMSK (~(((1U << TIMER_TPLCR_LEN) - 1) << TIMER_TPLCR_POS))
/* 0x60 : TPLCR3 */
#define TIMER_TPLCR3_OFFSET (0x60)
#define TIMER_TPLCR TIMER_TPLCR
#define TIMER_TPLCR_POS (0U)
#define TIMER_TPLCR_LEN (2U)
#define TIMER_TPLCR_MSK (((1U << TIMER_TPLCR_LEN) - 1) << TIMER_TPLCR_POS)
#define TIMER_TPLCR_UMSK (~(((1U << TIMER_TPLCR_LEN) - 1) << TIMER_TPLCR_POS))
/* 0x64 : WMER */
#define TIMER_WMER_OFFSET (0x64)
#define TIMER_WE TIMER_WE
#define TIMER_WE_POS (0U)
#define TIMER_WE_LEN (1U)
#define TIMER_WE_MSK (((1U << TIMER_WE_LEN) - 1) << TIMER_WE_POS)
#define TIMER_WE_UMSK (~(((1U << TIMER_WE_LEN) - 1) << TIMER_WE_POS))
#define TIMER_WRIE TIMER_WRIE
#define TIMER_WRIE_POS (1U)
#define TIMER_WRIE_LEN (1U)
#define TIMER_WRIE_MSK (((1U << TIMER_WRIE_LEN) - 1) << TIMER_WRIE_POS)
#define TIMER_WRIE_UMSK (~(((1U << TIMER_WRIE_LEN) - 1) << TIMER_WRIE_POS))
/* 0x68 : WMR */
#define TIMER_WMR_OFFSET (0x68)
#define TIMER_WMR TIMER_WMR
#define TIMER_WMR_POS (0U)
#define TIMER_WMR_LEN (16U)
#define TIMER_WMR_MSK (((1U << TIMER_WMR_LEN) - 1) << TIMER_WMR_POS)
#define TIMER_WMR_UMSK (~(((1U << TIMER_WMR_LEN) - 1) << TIMER_WMR_POS))
/* 0x6C : WVR */
#define TIMER_WVR_OFFSET (0x6C)
#define TIMER_WVR TIMER_WVR
#define TIMER_WVR_POS (0U)
#define TIMER_WVR_LEN (16U)
#define TIMER_WVR_MSK (((1U << TIMER_WVR_LEN) - 1) << TIMER_WVR_POS)
#define TIMER_WVR_UMSK (~(((1U << TIMER_WVR_LEN) - 1) << TIMER_WVR_POS))
/* 0x70 : WSR */
#define TIMER_WSR_OFFSET (0x70)
#define TIMER_WTS TIMER_WTS
#define TIMER_WTS_POS (0U)
#define TIMER_WTS_LEN (1U)
#define TIMER_WTS_MSK (((1U << TIMER_WTS_LEN) - 1) << TIMER_WTS_POS)
#define TIMER_WTS_UMSK (~(((1U << TIMER_WTS_LEN) - 1) << TIMER_WTS_POS))
/* 0x78 : TICR2 */
#define TIMER_TICR2_OFFSET (0x78)
#define TIMER_TCLR_0 TIMER_TCLR_0
#define TIMER_TCLR_0_POS (0U)
#define TIMER_TCLR_0_LEN (1U)
#define TIMER_TCLR_0_MSK (((1U << TIMER_TCLR_0_LEN) - 1) << TIMER_TCLR_0_POS)
#define TIMER_TCLR_0_UMSK \
(~(((1U << TIMER_TCLR_0_LEN) - 1) << TIMER_TCLR_0_POS))
#define TIMER_TCLR_1 TIMER_TCLR_1
#define TIMER_TCLR_1_POS (1U)
#define TIMER_TCLR_1_LEN (1U)
#define TIMER_TCLR_1_MSK (((1U << TIMER_TCLR_1_LEN) - 1) << TIMER_TCLR_1_POS)
#define TIMER_TCLR_1_UMSK \
(~(((1U << TIMER_TCLR_1_LEN) - 1) << TIMER_TCLR_1_POS))
#define TIMER_TCLR_2 TIMER_TCLR_2
#define TIMER_TCLR_2_POS (2U)
#define TIMER_TCLR_2_LEN (1U)
#define TIMER_TCLR_2_MSK (((1U << TIMER_TCLR_2_LEN) - 1) << TIMER_TCLR_2_POS)
#define TIMER_TCLR_2_UMSK \
(~(((1U << TIMER_TCLR_2_LEN) - 1) << TIMER_TCLR_2_POS))
/* 0x7C : TICR3 */
#define TIMER_TICR3_OFFSET (0x7C)
#define TIMER_TCLR_0 TIMER_TCLR_0
#define TIMER_TCLR_0_POS (0U)
#define TIMER_TCLR_0_LEN (1U)
#define TIMER_TCLR_0_MSK (((1U << TIMER_TCLR_0_LEN) - 1) << TIMER_TCLR_0_POS)
#define TIMER_TCLR_0_UMSK \
(~(((1U << TIMER_TCLR_0_LEN) - 1) << TIMER_TCLR_0_POS))
#define TIMER_TCLR_1 TIMER_TCLR_1
#define TIMER_TCLR_1_POS (1U)
#define TIMER_TCLR_1_LEN (1U)
#define TIMER_TCLR_1_MSK (((1U << TIMER_TCLR_1_LEN) - 1) << TIMER_TCLR_1_POS)
#define TIMER_TCLR_1_UMSK \
(~(((1U << TIMER_TCLR_1_LEN) - 1) << TIMER_TCLR_1_POS))
#define TIMER_TCLR_2 TIMER_TCLR_2
#define TIMER_TCLR_2_POS (2U)
#define TIMER_TCLR_2_LEN (1U)
#define TIMER_TCLR_2_MSK (((1U << TIMER_TCLR_2_LEN) - 1) << TIMER_TCLR_2_POS)
#define TIMER_TCLR_2_UMSK \
(~(((1U << TIMER_TCLR_2_LEN) - 1) << TIMER_TCLR_2_POS))
/* 0x80 : WICR */
#define TIMER_WICR_OFFSET (0x80)
#define TIMER_WICLR TIMER_WICLR
#define TIMER_WICLR_POS (0U)
#define TIMER_WICLR_LEN (1U)
#define TIMER_WICLR_MSK (((1U << TIMER_WICLR_LEN) - 1) << TIMER_WICLR_POS)
#define TIMER_WICLR_UMSK (~(((1U << TIMER_WICLR_LEN) - 1) << TIMER_WICLR_POS))
/* 0x84 : TCER */
#define TIMER_TCER_OFFSET (0x84)
#define TIMER2_EN TIMER2_EN
#define TIMER2_EN_POS (1U)
#define TIMER2_EN_LEN (1U)
#define TIMER2_EN_MSK (((1U << TIMER2_EN_LEN) - 1) << TIMER2_EN_POS)
#define TIMER2_EN_UMSK (~(((1U << TIMER2_EN_LEN) - 1) << TIMER2_EN_POS))
#define TIMER3_EN TIMER3_EN
#define TIMER3_EN_POS (2U)
#define TIMER3_EN_LEN (1U)
#define TIMER3_EN_MSK (((1U << TIMER3_EN_LEN) - 1) << TIMER3_EN_POS)
#define TIMER3_EN_UMSK (~(((1U << TIMER3_EN_LEN) - 1) << TIMER3_EN_POS))
/* 0x88 : TCMR */
#define TIMER_TCMR_OFFSET (0x88)
#define TIMER2_MODE TIMER2_MODE
#define TIMER2_MODE_POS (1U)
#define TIMER2_MODE_LEN (1U)
#define TIMER2_MODE_MSK (((1U << TIMER2_MODE_LEN) - 1) << TIMER2_MODE_POS)
#define TIMER2_MODE_UMSK (~(((1U << TIMER2_MODE_LEN) - 1) << TIMER2_MODE_POS))
#define TIMER3_MODE TIMER3_MODE
#define TIMER3_MODE_POS (2U)
#define TIMER3_MODE_LEN (1U)
#define TIMER3_MODE_MSK (((1U << TIMER3_MODE_LEN) - 1) << TIMER3_MODE_POS)
#define TIMER3_MODE_UMSK (~(((1U << TIMER3_MODE_LEN) - 1) << TIMER3_MODE_POS))
/* 0x90 : TILR2 */
#define TIMER_TILR2_OFFSET (0x90)
#define TIMER_TILR_0 TIMER_TILR_0
#define TIMER_TILR_0_POS (0U)
#define TIMER_TILR_0_LEN (1U)
#define TIMER_TILR_0_MSK (((1U << TIMER_TILR_0_LEN) - 1) << TIMER_TILR_0_POS)
#define TIMER_TILR_0_UMSK \
(~(((1U << TIMER_TILR_0_LEN) - 1) << TIMER_TILR_0_POS))
#define TIMER_TILR_1 TIMER_TILR_1
#define TIMER_TILR_1_POS (1U)
#define TIMER_TILR_1_LEN (1U)
#define TIMER_TILR_1_MSK (((1U << TIMER_TILR_1_LEN) - 1) << TIMER_TILR_1_POS)
#define TIMER_TILR_1_UMSK \
(~(((1U << TIMER_TILR_1_LEN) - 1) << TIMER_TILR_1_POS))
#define TIMER_TILR_2 TIMER_TILR_2
#define TIMER_TILR_2_POS (2U)
#define TIMER_TILR_2_LEN (1U)
#define TIMER_TILR_2_MSK (((1U << TIMER_TILR_2_LEN) - 1) << TIMER_TILR_2_POS)
#define TIMER_TILR_2_UMSK \
(~(((1U << TIMER_TILR_2_LEN) - 1) << TIMER_TILR_2_POS))
/* 0x94 : TILR3 */
#define TIMER_TILR3_OFFSET (0x94)
#define TIMER_TILR_0 TIMER_TILR_0
#define TIMER_TILR_0_POS (0U)
#define TIMER_TILR_0_LEN (1U)
#define TIMER_TILR_0_MSK (((1U << TIMER_TILR_0_LEN) - 1) << TIMER_TILR_0_POS)
#define TIMER_TILR_0_UMSK \
(~(((1U << TIMER_TILR_0_LEN) - 1) << TIMER_TILR_0_POS))
#define TIMER_TILR_1 TIMER_TILR_1
#define TIMER_TILR_1_POS (1U)
#define TIMER_TILR_1_LEN (1U)
#define TIMER_TILR_1_MSK (((1U << TIMER_TILR_1_LEN) - 1) << TIMER_TILR_1_POS)
#define TIMER_TILR_1_UMSK \
(~(((1U << TIMER_TILR_1_LEN) - 1) << TIMER_TILR_1_POS))
#define TIMER_TILR_2 TIMER_TILR_2
#define TIMER_TILR_2_POS (2U)
#define TIMER_TILR_2_LEN (1U)
#define TIMER_TILR_2_MSK (((1U << TIMER_TILR_2_LEN) - 1) << TIMER_TILR_2_POS)
#define TIMER_TILR_2_UMSK \
(~(((1U << TIMER_TILR_2_LEN) - 1) << TIMER_TILR_2_POS))
/* 0x98 : WCR */
#define TIMER_WCR_OFFSET (0x98)
#define TIMER_WCR TIMER_WCR
#define TIMER_WCR_POS (0U)
#define TIMER_WCR_LEN (1U)
#define TIMER_WCR_MSK (((1U << TIMER_WCR_LEN) - 1) << TIMER_WCR_POS)
#define TIMER_WCR_UMSK (~(((1U << TIMER_WCR_LEN) - 1) << TIMER_WCR_POS))
/* 0x9C : WFAR */
#define TIMER_WFAR_OFFSET (0x9C)
#define TIMER_WFAR TIMER_WFAR
#define TIMER_WFAR_POS (0U)
#define TIMER_WFAR_LEN (16U)
#define TIMER_WFAR_MSK (((1U << TIMER_WFAR_LEN) - 1) << TIMER_WFAR_POS)
#define TIMER_WFAR_UMSK (~(((1U << TIMER_WFAR_LEN) - 1) << TIMER_WFAR_POS))
/* 0xA0 : WSAR */
#define TIMER_WSAR_OFFSET (0xA0)
#define TIMER_WSAR TIMER_WSAR
#define TIMER_WSAR_POS (0U)
#define TIMER_WSAR_LEN (16U)
#define TIMER_WSAR_MSK (((1U << TIMER_WSAR_LEN) - 1) << TIMER_WSAR_POS)
#define TIMER_WSAR_UMSK (~(((1U << TIMER_WSAR_LEN) - 1) << TIMER_WSAR_POS))
/* 0xA8 : TCVWR2 */
#define TIMER_TCVWR2_OFFSET (0xA8)
#define TIMER_TCVWR TIMER_TCVWR
#define TIMER_TCVWR_POS (0U)
#define TIMER_TCVWR_LEN (32U)
#define TIMER_TCVWR_MSK (((1U << TIMER_TCVWR_LEN) - 1) << TIMER_TCVWR_POS)
#define TIMER_TCVWR_UMSK (~(((1U << TIMER_TCVWR_LEN) - 1) << TIMER_TCVWR_POS))
/* 0xAC : TCVWR3 */
#define TIMER_TCVWR3_OFFSET (0xAC)
#define TIMER_TCVWR TIMER_TCVWR
#define TIMER_TCVWR_POS (0U)
#define TIMER_TCVWR_LEN (32U)
#define TIMER_TCVWR_MSK (((1U << TIMER_TCVWR_LEN) - 1) << TIMER_TCVWR_POS)
#define TIMER_TCVWR_UMSK (~(((1U << TIMER_TCVWR_LEN) - 1) << TIMER_TCVWR_POS))
/* 0xB4 : TCVSYN2 */
#define TIMER_TCVSYN2_OFFSET (0xB4)
#define TIMER_TCVSYN2 TIMER_TCVSYN2
#define TIMER_TCVSYN2_POS (0U)
#define TIMER_TCVSYN2_LEN (32U)
#define TIMER_TCVSYN2_MSK \
(((1U << TIMER_TCVSYN2_LEN) - 1) << TIMER_TCVSYN2_POS)
#define TIMER_TCVSYN2_UMSK \
(~(((1U << TIMER_TCVSYN2_LEN) - 1) << TIMER_TCVSYN2_POS))
/* 0xB8 : TCVSYN3 */
#define TIMER_TCVSYN3_OFFSET (0xB8)
#define TIMER_TCVSYN3 TIMER_TCVSYN3
#define TIMER_TCVSYN3_POS (0U)
#define TIMER_TCVSYN3_LEN (32U)
#define TIMER_TCVSYN3_MSK \
(((1U << TIMER_TCVSYN3_LEN) - 1) << TIMER_TCVSYN3_POS)
#define TIMER_TCVSYN3_UMSK \
(~(((1U << TIMER_TCVSYN3_LEN) - 1) << TIMER_TCVSYN3_POS))
/* 0xBC : TCDR */
#define TIMER_TCDR_OFFSET (0xBC)
#define TIMER_TCDR2 TIMER_TCDR2
#define TIMER_TCDR2_POS (8U)
#define TIMER_TCDR2_LEN (8U)
#define TIMER_TCDR2_MSK (((1U << TIMER_TCDR2_LEN) - 1) << TIMER_TCDR2_POS)
#define TIMER_TCDR2_UMSK (~(((1U << TIMER_TCDR2_LEN) - 1) << TIMER_TCDR2_POS))
#define TIMER_TCDR3 TIMER_TCDR3
#define TIMER_TCDR3_POS (16U)
#define TIMER_TCDR3_LEN (8U)
#define TIMER_TCDR3_MSK (((1U << TIMER_TCDR3_LEN) - 1) << TIMER_TCDR3_POS)
#define TIMER_TCDR3_UMSK (~(((1U << TIMER_TCDR3_LEN) - 1) << TIMER_TCDR3_POS))
#define TIMER_WCDR TIMER_WCDR
#define TIMER_WCDR_POS (24U)
#define TIMER_WCDR_LEN (8U)
#define TIMER_WCDR_MSK (((1U << TIMER_WCDR_LEN) - 1) << TIMER_WCDR_POS)
#define TIMER_WCDR_UMSK (~(((1U << TIMER_WCDR_LEN) - 1) << TIMER_WCDR_POS))
#define WDT_ENABLE_ACCESS() \
{ \
BL_WR_REG(TIMER_BASE, \
TIMER_WFAR, \
BL_SET_REG_BITS_VAL( \
BL_RD_REG(TIMER_BASE, TIMER_WFAR), TIMER_WFAR, 0xBABA)); \
BL_WR_REG(TIMER_BASE, \
TIMER_WSAR, \
BL_SET_REG_BITS_VAL( \
BL_RD_REG(TIMER_BASE, TIMER_WSAR), TIMER_WSAR, 0xEB10)); \
}
/****************************************************************************
* Public Types
****************************************************************************/
#ifndef __ASSEMBLY__
/* TIMER channel type definition */
enum timer_chan_e
{
TIMER_CH0, /* TIMER channel 0 port define */
TIMER_CH1, /* TIMER channel 1 port define */
TIMER_CH_MAX
};
typedef enum timer_chan_e timer_chan_t;
/* TIMER clock source type definition */
enum timer_clksrc_e
{
TIMER_CLKSRC_FCLK, /* TIMER clock source :System CLK */
TIMER_CLKSRC_32K, /* TIMER clock source :32K CLK */
TIMER_CLKSRC_1K, /* TIMER clock source :1K CLK,Only for Timer not for
* Watchdog */
TIMER_CLKSRC_XTAL /* TIMER clock source :XTAL CLK */
};
typedef enum timer_clksrc_e timer_clksrc_t;
/* TIMER match compare ID type definition */
enum timer_comp_id_e
{
TIMER_COMP_ID_0, /* TIMER match compare ID 0 define */
TIMER_COMP_ID_1, /* TIMER match compare ID 1 define */
TIMER_COMP_ID_2 /* TIMER match compare ID 2 define */
};
typedef enum timer_comp_id_e timer_comp_id_t;
/* TIMER preload source type definition */
enum timer_preload_trig_e
{
TIMER_PRELOAD_TRIG_NONE, /* TIMER no preload source, just free run */
TIMER_PRELOAD_TRIG_COMP0, /* TIMER count register preload triggered by
* comparator 0 */
TIMER_PRELOAD_TRIG_COMP1, /* TIMER count register preload triggered by
* comparator 1 */
TIMER_PRELOAD_TRIG_COMP2 /* TIMER count register preload triggered by
* comparator 2 */
};
typedef enum timer_preload_trig_e timer_preload_trig_t;
/* TIMER count register run mode type definition */
enum timer_countmode_e
{
TIMER_COUNT_PRELOAD, /* TIMER count register preload from comparator
* register */
TIMER_COUNT_FREERUN /* TIMER count register free run */
};
typedef enum timer_countmode_e timer_countmode_t;
/* TIMER interrupt type definition */
enum timer_int_e
{
TIMER_INT_COMP_0, /* Comparator 0 match cause interrupt */
TIMER_INT_COMP_1, /* Comparator 1 match cause interrupt */
TIMER_INT_COMP_2, /* Comparator 2 match cause interrupt */
TIMER_INT_ALL
};
typedef enum timer_int_e timer_int_t;
/* Watchdog timer interrupt type definition */
enum wdt_int_e
{
WDT_INT, /* Comparator 0 match cause interrupt */
WDT_INT_ALL
};
typedef enum wdt_int_e wdt_int_t;
/* TIMER configuration structure type definition */
struct timer_cfg_s
{
timer_chan_t timer_ch; /* Timer channel */
timer_clksrc_t clk_src; /* Timer clock source */
timer_preload_trig_t
pl_trig_src; /* Timer count register preload trigger source slelect */
timer_countmode_t count_mode; /* Timer count mode */
uint8_t clock_division; /* Timer clock divison value */
uint32_t match_val0; /* Timer match 0 value 0 */
uint32_t match_val1; /* Timer match 1 value 0 */
uint32_t match_val2; /* Timer match 2 value 0 */
uint32_t pre_load_val; /* Timer preload value */
};
typedef struct timer_cfg_s timer_cfg_t;
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
EXTERN uint32_t timer_getcompvalue(timer_chan_t timer_ch,
timer_comp_id_t cmp_no);
EXTERN void timer_setcompvalue(timer_chan_t timer_ch,
timer_comp_id_t cmp_no,
uint32_t val);
EXTERN uint32_t timer_getcountervalue(timer_chan_t timer_ch);
EXTERN uint32_t timer_getmatchstatus(timer_chan_t timer_ch,
timer_comp_id_t cmp_no);
EXTERN uint32_t timer_getpreloadvalue(timer_chan_t timer_ch);
EXTERN void timer_setpreloadvalue(timer_chan_t timer_ch, uint32_t val);
EXTERN void timer_setpreloadtrigsrc(timer_chan_t timer_ch,
timer_preload_trig_t pl_src);
EXTERN void timer_setcountmode(timer_chan_t timer_ch,
timer_countmode_t count_mode);
EXTERN void timer_clearintstatus(timer_chan_t timer_ch,
timer_comp_id_t cmp_no);
EXTERN void timer_init(timer_cfg_t *timer_cfg);
EXTERN void timer_enable(timer_chan_t timer_ch);
EXTERN void timer_disable(timer_chan_t timer_ch);
EXTERN void timer_intmask(timer_chan_t timer_ch,
timer_int_t int_type, uint32_t int_mask);
EXTERN void wdt_set_clock(timer_clksrc_t clk_src, uint8_t div);
EXTERN uint32_t wdt_getmatchvalue(void);
EXTERN void wdt_setcompvalue(uint16_t val);
EXTERN uint16_t wdt_getcountervalue(void);
EXTERN void wdt_resetcountervalue(void);
EXTERN uint32_t wdt_getresetstatus(void);
EXTERN void wdt_clearresetstatus(void);
EXTERN void wdt_enable(void);
EXTERN void wdt_disable(void);
EXTERN void wdt_intmask(wdt_int_t int_type, uint32_t int_mask);
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_RISCV_SRC_BL602_HARDWARE_BL602_GPIO_H */

1010
arch/risc-v/src/bl602/hardware/bl602_uart.h Normal file
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43
arch/risc-v/src/bl602/hardware/clic.h Normal file
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@ -0,0 +1,43 @@
/****************************************************************************
* arch/risc-v/src/bl602/hardware/clic.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_RISCV_SRC_BL602_HARDWARE_CLIC_H
#define __ARCH_RISCV_SRC_BL602_HARDWARE_CLIC_H
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#define CLIC_CTRL_ADDR 0x02000000UL
#define CLIC_HART0_ADDR 0x02800000UL
#define CLIC_MSIP 0x0000
#define CLIC_MSIP_size 0x4
#define CLIC_MTIMECMP 0x4000
#define CLIC_MTIMECMP_size 0x8
#define CLIC_MTIME 0xBFF8
#define CLIC_MTIME_size 0x8
#define CLIC_INTIP 0x000
#define CLIC_INTIE 0x400
#define CLIC_INTCFG 0x800
#define CLIC_CFG 0xc00
#endif /* __ARCH_RISCV_SRC_BL602_HARDWARE_CLIC_H */

11
boards/Kconfig
View file

@ -74,6 +74,13 @@ config ARCH_BOARD_AXOLOTI
Axoloti synthesizer board based on the STMicro STM32F427IGH6 MCU.
See: http://www.axoloti.com/
config ARCH_BOARD_BL602EVB
bool "BouffaloLab BL602EVB Board"
depends on ARCH_CHIP_BL602
---help---
This is the board configuration for the port of NuttX to the BouffaloLab BL602EVB
board. This board features the RISC-V rv32imfc core
config ARCH_BOARD_C5471EVM
bool "Spectrum Digital C5471 evaluation board"
depends on ARCH_CHIP_C5471
@ -2192,6 +2199,7 @@ config ARCH_BOARD
default "avr32dev1" if ARCH_BOARD_AVR32DEV1
default "axoloti" if ARCH_BOARD_AXOLOTI
default "bambino-200e" if ARCH_BOARD_BAMBINO_200E
default "bl602evb" if ARCH_BOARD_BL602EVB
default "c5471evm" if ARCH_BOARD_C5471EVM
default "clicker2-stm32" if ARCH_BOARD_CLICKER2_STM32
default "cloudctrl" if ARCH_BOARD_CLOUDCTRL
@ -3065,6 +3073,9 @@ endif
if ARCH_BOARD_Z80SIM
source "boards/z80/z80/z80sim/Kconfig"
endif
if ARCH_BOARD_BL602EVB
source "boards/risc-v/bl602/bl602evb/Kconfig"
endif
config BOARD_CRASHDUMP
bool "Enable Board level logging of crash dumps"

8
boards/risc-v/bl602/bl602evb/Kconfig Normal file
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@ -0,0 +1,8 @@
#
# For a description of the syntax of this configuration file,
# see misc/tools/kconfig-language.txt.
#
if ARCH_BOARD_BL602EVB
endif

28
boards/risc-v/bl602/bl602evb/README.txt Normal file
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@ -0,0 +1,28 @@
1. Download and install toolchain
$ curl https://static.dev.sifive.com/dev-tools/riscv64-unknown-elf-gcc-8.3.0-2019.08.0-x86_64-linux-ubuntu14.tar.gz
2. Follow instruction on https://github.com/enjoy-digital/litex to build the vexriscv softcore fpga gateware
and flash to arty_a7 board
3. Configure and build NuttX
$ mkdir ./nuttx; cd ./nuttx
$ git clone https://bitbucket.org/nuttx/nuttx.git
$ git clone https://bitbucket.org/nuttx/apps.git
$ cd nuttx
$ make distclean
$ ./tools/configure.sh arty_a7:nsh
$ make V=1
4. Setup tftp server on your laptop, copy nuttx.bin to your tftpboot directory and change its name to boot.bin
5. Setup the wire connection(uart and tftp) between your board and laptop
6. Run $ minicom -b 1000000 /dev/ttyUSB1 (the default baudrate on litex vexriscv is 1e6)
when you see the bios prompt "litex>", type "netboot" and enter soon comes the nsh prompt
7. TODO
Support GPIO/SPI/I2C/RTC/WDT/PWM
Support RISC-V User mode

1242
boards/risc-v/bl602/bl602evb/configs/demo/defconfig Normal file
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75
boards/risc-v/bl602/bl602evb/configs/nsh/defconfig Normal file
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@ -0,0 +1,75 @@
#
# This file is autogenerated: PLEASE DO NOT EDIT IT.
#
# You can use "make menuconfig" to make any modifications to the installed .config file.
# You can then do "make savedefconfig" to generate a new defconfig file that includes your
# modifications.
#
# CONFIG_NSH_DISABLEBG is not set
# CONFIG_NSH_DISABLE_LOSMART is not set
# CONFIG_NSH_DISABLE_UNAME is not set
# CONFIG_STANDARD_SERIAL is not set
CONFIG_ARCH="risc-v"
CONFIG_ARCH_BOARD="bl602evb"
CONFIG_ARCH_BOARD_BL602EVB=y
CONFIG_ARCH_CHIP="bl602"
CONFIG_ARCH_CHIP_BL602=y
CONFIG_ARCH_INTERRUPTSTACK=8192
CONFIG_ARCH_FPU=y
CONFIG_ARCH_RISCV=y
CONFIG_ARCH_STACKDUMP=y
CONFIG_BINFMT_DISABLE=y
CONFIG_BOARD_LOOPSPERMSEC=10000
CONFIG_BUILTIN=y
CONFIG_DEBUG_FULLOPT=y
CONFIG_DEBUG_SYMBOLS=y
CONFIG_DEFAULT_SMALL=y
CONFIG_DEV_ZERO=y
CONFIG_DISABLE_MQUEUE=y
CONFIG_EXAMPLES_HELLO=y
CONFIG_EXAMPLES_HELLO_STACKSIZE=8192
CONFIG_FS_PROCFS=y
CONFIG_IDLETHREAD_STACKSIZE=8192
CONFIG_INTELHEX_BINARY=y
CONFIG_LIBC_PERROR_STDOUT=y
CONFIG_LIBC_STRERROR=y
CONFIG_MAX_TASKS=8
CONFIG_MAX_WDOGPARMS=2
CONFIG_NFILE_DESCRIPTORS=6
CONFIG_NFILE_STREAMS=6
CONFIG_NSH_ARCHINIT=y
CONFIG_NSH_BUILTIN_APPS=y
CONFIG_NSH_DISABLE_CD=y
CONFIG_NSH_DISABLE_CP=y
CONFIG_NSH_DISABLE_IFUPDOWN=y
CONFIG_NSH_DISABLE_MKDIR=y
CONFIG_NSH_DISABLE_RM=y
CONFIG_NSH_DISABLE_RMDIR=y
CONFIG_NSH_DISABLE_UMOUNT=y
CONFIG_NSH_FILEIOSIZE=64
CONFIG_NSH_STRERROR=y
CONFIG_PREALLOC_TIMERS=0
CONFIG_PREALLOC_WDOGS=4
CONFIG_PTHREAD_STACK_DEFAULT=8192
CONFIG_RAM_SIZE=134217728
CONFIG_RAM_START=0xc0800000
CONFIG_RAW_BINARY=y
CONFIG_RR_INTERVAL=200
CONFIG_RV32IM_CUSTOM_IRQ_SUPPORT=y
CONFIG_SCHED_WAITPID=y
CONFIG_STACK_COLORATION=y
CONFIG_START_DAY=20
CONFIG_START_MONTH=3
CONFIG_START_YEAR=2020
CONFIG_STDIO_DISABLE_BUFFERING=y
CONFIG_SYSTEM_NSH=y
CONFIG_TASK_NAME_SIZE=12
CONFIG_TASK_SPAWN_DEFAULT_STACKSIZE=8192
CONFIG_TESTING_GETPRIME=y
CONFIG_UART0_RXBUFSIZE=128
CONFIG_UART0_SERIAL_CONSOLE=y
CONFIG_UART0_TXBUFSIZE=128
CONFIG_USERMAIN_STACKSIZE=8192
CONFIG_USER_ENTRYPOINT="nsh_main"
CONFIG_WDOG_INTRESERVE=0
CONFIG_DEBUG_FEATURES=y

68
boards/risc-v/bl602/bl602evb/include/board.h Normal file
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@ -0,0 +1,68 @@
/****************************************************************************
* boards/risc-v/litex/arty_a7/include/board.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __BOARDS_RISCV_BL602_BL602EVB_INCLUDE_BOARD_H
#define __BOARDS_RISCV_BL602_BL602EVB_INCLUDE_BOARD_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Public Types
****************************************************************************/
#ifndef __ASSEMBLY__
/****************************************************************************
* Public Data
****************************************************************************/
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: litex_boardinitialize
****************************************************************************/
void litex_boardinitialize(void);
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __BOARDS_RISC-V_BL602_EVB_INCLUDE_BOARD_H */

89
boards/risc-v/bl602/bl602evb/scripts/Make.defs Normal file
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@ -0,0 +1,89 @@
############################################################################
# boards/risc-v/bl602/bl602evb/scripts/Make.defs
#
# Licensed to the Apache Software Foundation (ASF) under one or more
# contributor license agreements. See the NOTICE file distributed with
# this work for additional information regarding copyright ownership. The
# ASF licenses this file to you under the Apache License, Version 2.0 (the
# "License"); you may not use this file except in compliance with the
# License. You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
# License for the specific language governing permissions and limitations
# under the License.
#
############################################################################
include $(TOPDIR)/.config
include $(TOPDIR)/tools/Config.mk
include $(TOPDIR)/arch/risc-v/src/rv32im/Toolchain.defs
ARCH_SRCDIR = $(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src
ARCH_INCDIR = $(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)include
LDSCRIPT = ld.script
CINCPATH := ${shell $(INCDIR) -s "$(CC)" $(TOPDIR)$(DELIM)include}
CXXINCPATH := ${shell $(INCDIR) -s "$(CC)" $(TOPDIR)$(DELIM)include$(DELIM)cxx}
ARCHINCLUDES += $(CINCPATH)
ARCHXXINCLUDES += $(CINCPATH) $(CXXINCPATH)
ifeq ($(CONFIG_CYGWIN_WINTOOL),y)
ARCHSCRIPT = -T "${shell cygpath -w $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT)}"
else
ARCHSCRIPT = -T$(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT)
endif
CC = $(CROSSDEV)gcc
CXX = $(CROSSDEV)g++
CPP = $(CROSSDEV)gcc -E
LD = $(CROSSDEV)ld
STRIP = $(CROSSDEV)strip --strip-unneeded
AR = $(ARCROSSDEV)ar rcs
NM = $(ARCROSSDEV)nm
OBJCOPY = $(CROSSDEV)objcopy
OBJDUMP = $(CROSSDEV)objdump
ARCHCCVERSION = ${shell $(CC) -v 2>&1 | sed -n '/^gcc version/p' | sed -e 's/^gcc version \([0-9\.]\)/\1/g' -e 's/[-\ ].*//g' -e '1q'}
ARCHCCMAJOR = ${shell echo $(ARCHCCVERSION) | cut -d'.' -f1}
ifeq ($(CONFIG_DEBUG_SYMBOLS),y)
ARCHOPTIMIZATION = -g
ASARCHCPUFLAGS += -Wa,-g
endif
MAXOPTIMIZATION = -Os
ifneq ($(CONFIG_DEBUG_NOOPT),y)
ARCHOPTIMIZATION += $(MAXOPTIMIZATION) -fno-strict-aliasing -fno-strength-reduce -fomit-frame-pointer
endif
ARCHCPUFLAGS = -march=rv32imfc -mabi=ilp32f -mno-relax
ARCHCFLAGS = -fno-builtin -ffunction-sections -fdata-sections
ARCHCXXFLAGS = -fno-builtin -fno-exceptions -fcheck-new -fno-rtti
ARCHWARNINGS = -Wall -Wstrict-prototypes -Wshadow -Wundef
ARCHWARNINGSXX = -Wall -Wshadow -Wundef
ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10
ARCHDEFINES += -DARCH_RISCV
CFLAGS = $(ARCHCFLAGS) $(ARCHWARNINGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -pipe
CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS)
CXXFLAGS = $(ARCHCXXFLAGS) $(ARCHWARNINGSXX) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -pipe
CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS)
CPPFLAGS = $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS)
AFLAGS += $(CFLAGS) -D__ASSEMBLY__ $(ASARCHCPUFLAGS)
NXFLATLDFLAGS1 = -r -d -warn-common
NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections
LDNXFLATFLAGS = -e main -s 2048
LDFLAGS += --gc-sections -melf32lriscv
HOSTCC = gcc
HOSTCFLAGS = -Wall -Wstrict-prototypes -Wshadow -Wundef -g -pipe

279
boards/risc-v/bl602/bl602evb/scripts/ld.script Normal file
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@ -0,0 +1,279 @@
OUTPUT_ARCH( "riscv" )
ENTRY( bl602_start )
__EM_SIZE = DEFINED(ble_controller_init) ? 8K : 0K;
MEMORY
{
rom (rxai!w) : ORIGIN = 0x21015000, LENGTH = 44K
flash (rxai!w) : ORIGIN = 0x23000000, LENGTH = 4M
ram_tcm (wxa) : ORIGIN = 0x4200C000, LENGTH = (16K + 16K + 48K + 64K + 64K + 8K - __EM_SIZE) /*put itcm with dtam and also OCRAM*/
ram_wifi (wxa) : ORIGIN = 0x42042000 - __EM_SIZE, LENGTH = (8K + 104K - 64K - 8K) /*leave 8K left for BLE*/
}
SECTIONS
{
__stack_size = DEFINED(__stack_size) ? __stack_size : 2K;
BOOT2_PT_ADDR = 0x42049C00;
BOOT2_FLASHCFG_ADDR = 0x42049c18;
.init :
{
KEEP (*(SORT_NONE(.init)))
} > flash
.text :
{
*(.text.unlikely .text.unlikely.*)
*(.text.startup .text.startup.*)
*(.text .text.*)
*(.gnu.linkonce.t.*)
} > flash
.rodata :
{
*(.rdata)
*(.rodata .rodata.*)
*(.sdata2.*)
/* static cli cmds */
. = ALIGN(4);
_bl_static_cli_cmds_start = .;
KEEP(*(.static_cli_cmds))
*(.static_cli_cmds)
_bl_static_cli_cmds_end = .;
/* static fw attribute entry */
. = ALIGN(4);
_bl_static_fw_cfg_entry_start = .;
KEEP(*(.wifi.cfg.entry))
_bl_static_fw_cfg_entry_end = .;
/* static blog code1 */
. = ALIGN(4);
_bl_static_blogcomponent_code_start = .;
KEEP(SORT(*)(.static_blogcomponent_code*))
*(.static_blogcomponent_code*)
_bl_static_blogcomponent_code_end = .;
/* static blog code2 */
. = ALIGN(4);
_bl_static_blogfile_code_start = .;
KEEP(SORT(*)(.static_blogfile_code*))
*(.static_blogfile_code*)
_bl_static_blogfile_code_end = .;
/* static blog code3 */
. = ALIGN(4);
_bl_static_blogpri_code_start = .;
KEEP(SORT(*)(.static_blogpri_code*))
*(.static_blogpri_code*)
_bl_static_blogpri_code_end = .;
*(.gnu.linkonce.r.*)
/*Framework table section, use ALIGN here to avoid fill section*/
. = ALIGN(4);
_rom_framework_audio_device_start = .;
KEEP(*(.framework.audio_device))
_rom_framework_audio_device_end = .;
} > flash
/*put wifibss in the first place*/
.wifibss (NOLOAD) :
{
PROVIDE( __wifi_bss_start = ADDR(.wifibss) );
PROVIDE( __wifi_bss_end = ADDR(.wifibss) + SIZEOF(.wifibss) );
*ipc_shared.o(COMMON)
*sdu_shared.o(COMMON)
*hal_desc.o(COMMON)
*txl_buffer_shared.o(COMMON)
*txl_frame_shared.o(COMMON)
*scan_shared.o(COMMON)
*scanu_shared.o(COMMON)
*mfp_bip.o(COMMON)
*me_mic.o(COMMON)
*bl_sta_mgmt_others.o(COMMON)
*bl_pmk_mgmt.o(COMMON)
*bl_pmk_mgmt_internal.o(COMMON)
*libwifi_drv.a:bl_utils.o(COMMON)
*libwifi_drv.a:bl_utils.o(.bss*)
*(.wifi_ram*)
. = ALIGN(16);
} > ram_wifi
PROVIDE( _heap_wifi_start = . );
PROVIDE( _heap_wifi_size = ORIGIN(ram_wifi) + LENGTH(ram_wifi) - _heap_wifi_start );
.romdata :
{
/*always put freetos under global_pointer with the following order. No change!*/
PROVIDE( __global_pointer_head$ = . );
PROVIDE( __global_pointer$ = . + 0x7F0 );
. = . + 0x498;
} > ram_tcm AT > flash
.data :
{
PROVIDE( _data_load = LOADADDR(.data) );
PROVIDE( _data_run = ADDR(.data) );
PROVIDE( _data_run_end = ADDR(.data) + SIZEOF(.data));
*(.tcm_code)
*(.tcm_const)
*(.sclock_rlt_code)
*(.sclock_rlt_const)
*(.data .data.*)
*(.gnu.linkonce.d.*)
*(.sdata .sdata.*)
*(.gnu.linkonce.s.*)
. = ALIGN(8);
*(.srodata.cst16)
*(.srodata.cst8)
*(.srodata.cst4)
*(.srodata.cst2)
*(.srodata .srodata.*)
. = ALIGN(8);
*(._k_queue.static.*)
*(._k_sem.static.*)
*(._k_mutex.static.*)
_net_buf_pool_list = .;
KEEP(*(SORT_BY_NAME("._net_buf_pool.static.*")))
_bt_gatt_service_static_list_start = .;
KEEP(*(SORT_BY_NAME("._bt_gatt_service_static.static.*")))
_bt_gatt_service_static_list_end = .;
_bt_l2cap_fixed_chan_list_start = .;
KEEP(*(SORT_BY_NAME("._bt_l2cap_fixed_chan.static.*")))
_bt_l2cap_fixed_chan_list_end = .;
} > ram_tcm AT > flash
.boot2 (NOLOAD) :
{
PROVIDE ( __boot2_pt_addr_start = . );
*(.bss.boot2_partition_table)
PROVIDE ( __boot2_pt_addr_end = . );
PROVIDE ( __boot2_flash_cfg_start = . );
*(.bss.boot2_flashCfg)
PROVIDE ( __boot2_flash_cfg_end = . );
} > ram_tcm
.bss (NOLOAD) :
{
PROVIDE( __bss_start = ADDR(.bss) );
PROVIDE( __bss_end = ADDR(.bss) + SIZEOF(.bss) );
PROVIDE( _sbss = __bss_start );
PROVIDE( _ebss = __bss_end );
*(.sbss*)
*(.gnu.linkonce.sb.*)
*(.bss .bss.*)
*(.gnu.linkonce.b.*)
*(COMMON)
} > ram_tcm
PROVIDE( _heap_start = . );
PROVIDE( _heap_size = ADDR(.stack) - _heap_start );
.stack ORIGIN(ram_tcm) + LENGTH(ram_tcm) - __stack_size (NOLOAD) :
{
. = . + __stack_size;
PROVIDE( _sp_main = . );
__freertos_irq_stack_top = .;
} >ram_tcm
/*SYMOBOL used in code*/
PROVIDE( _ld_bl_static_cli_cmds_start = _bl_static_cli_cmds_start );
PROVIDE( _ld_bl_static_cli_cmds_end = _bl_static_cli_cmds_end );
/*CFG FW used in code*/
PROVIDE( _ld_bl_static_cfg_entry_start = _bl_static_fw_cfg_entry_start );
PROVIDE( _ld_bl_static_cfg_entry_end = _bl_static_fw_cfg_entry_end );
/* blog */
PROVIDE( _ld_bl_static_blogcomponent_code_start = _bl_static_blogcomponent_code_start );
PROVIDE( _ld_bl_static_blogcomponent_code_end = _bl_static_blogcomponent_code_end );
PROVIDE( _ld_bl_static_blogfile_code_start = _bl_static_blogfile_code_start );
PROVIDE( _ld_bl_static_blogfile_code_end = _bl_static_blogfile_code_end );
PROVIDE( _ld_bl_static_blogpri_code_start = _bl_static_blogpri_code_start );
PROVIDE( _ld_bl_static_blogpri_code_end = _bl_static_blogpri_code_end );
PROVIDE( _ld_ram_size0 = LENGTH(flash) );
PROVIDE( _ld_ram_addr0 = ORIGIN(flash) );
PROVIDE( _ld_ram_size1 = LENGTH(ram_tcm) );
PROVIDE( _ld_ram_addr1 = ORIGIN(ram_tcm) );
PROVIDE( _ld_ram_size2 = LENGTH(ram_wifi) );
PROVIDE( _ld_ram_addr2 = ORIGIN(ram_wifi) );
/*BOOT2 sections*/
PROVIDE ( __boot2_pt_addr_src = BOOT2_PT_ADDR );
PROVIDE ( __boot2_flash_cfg_src = BOOT2_FLASHCFG_ADDR );
PROVIDE(xTaskGetTickCount = 0x0000000021017694);
PROVIDE(xTaskGetTickCountFromISR = 0x00000000210176aa);
PROVIDE(pvPortMalloc = 0x0000000021019662);
PROVIDE(vPortFree = 0x000000002101973a);
PROVIDE(vTaskNotifyGiveFromISR = 0x00000000210188e8);
PROVIDE(vTaskSwitchContext = 0x0000000021017a04);
PROVIDE(ulTaskNotifyTake = 0x0000000021018548);
PROVIDE(vTaskExitCritical = 0x00000000210183f4);
PROVIDE(vTaskEnterCritical = 0x00000000210183e4);
PROVIDE(xTaskGetCurrentTaskHandle = 0x0000000021018152);
PROVIDE(xQueueSemaphoreTake = 0x0000000021015ce8);
PROVIDE(xQueueGenericSend = 0x0000000021015834);
PROVIDE(xQueueGenericSendFromISR = 0x0000000021015a4c);
PROVIDE(xTaskCreateStatic = 0x00000000210170a2);
PROVIDE(xTaskCreate = 0x000000002101713a);
PROVIDE(xQueueCreateMutex = 0x0000000021015a1c);
PROVIDE(xQueueCreateMutexStatic = 0x0000000021015994);
PROVIDE(vQueueDelete = 0x00000000210161d8);
PROVIDE(xQueueGenericCreateStatic = 0x00000000210156c2);
PROVIDE(xQueueGenericCreate = 0x0000000021015744);
PROVIDE(xQueueReceive = 0x0000000021015b8a);
PROVIDE(uxQueueMessagesWaiting = 0x0000000021016168);
PROVIDE(vTaskDelay = 0x00000000210179c6);
PROVIDE(vTaskDelayUntil = 0x0000000021017952);
PROVIDE(xPortGetFreeHeapSize = 0x00000000210197ce);
PROVIDE(vTaskList = 0x0000000021018408);
PROVIDE(xTimerGenericCommand = 0x0000000021018bec);
PROVIDE(xTimerCreateTimerTask = 0x0000000021018a9e);
PROVIDE(xTimerCreate = 0x0000000021018af6);
PROVIDE(xTimerCreateStatic = 0x0000000021018b66);
PROVIDE(xQueueCreateCountingSemaphoreStatic = 0x00000000210157c2);
PROVIDE(xQueueCreateCountingSemaphore = 0x0000000021015800);
PROVIDE(pTrapNetCounter = __global_pointer_head$);
PROVIDE(TrapNetCounter = __global_pointer_head$ + 0x58);
PROVIDE(vEventGroupDelete = 0x00000000210153be);
PROVIDE(xEventGroupWaitBits = 0x0000000021015086);
PROVIDE(xEventGroupCreateStatic = 0x0000000021015000);
PROVIDE(xEventGroupSetBits = 0x00000000210151e0);
PROVIDE(xStreamBufferGenericCreateStatic = 0x00000000210165c0);
PROVIDE(xStreamBufferReceive = 0x00000000210169ae);
PROVIDE(xStreamBufferSend = 0x00000000210167a8);
PROVIDE(pvTimerGetTimerID = 0x0000000021018fd4);
PROVIDE(xTaskGenericNotify = 0x00000000210186be);
PROVIDE(xTaskGenericNotifyFromISR = 0x00000000210187de);
PROVIDE(xQueueGiveMutexRecursive = 0x00000000210159c8);
PROVIDE(xQueueTakeMutexRecursive = 0x0000000021015e70);
PROVIDE(xTaskGetTickCount2 = 0x000000002101769a);
PROVIDE(xQueueGiveFromISR = 0x0000000021015b0e);
PROVIDE(vTaskDelete = 0x00000000210171b6);
PROVIDE(uxTaskGetStackHighWaterMark = 0x0000000021018110);
PROVIDE(pcTaskGetName = 0x00000000210176b6);
PROVIDE(vTaskStartScheduler = 0x0000000021017610);
PROVIDE(vPortDefineHeapRegions = 0x00000000210197da);
PROVIDE(__LD_CONFIG_EM_SEL = __EM_SIZE);
PROVIDE( _ld_symbol_rom_framework_audio_device_start = _rom_framework_audio_device_start);
PROVIDE( _ld_symbol_rom_framework_audio_device_end = _rom_framework_audio_device_end);
}

29
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############################################################################
# boards/risc-v/bl602/evb/src/Makefile
#
# Licensed to the Apache Software Foundation (ASF) under one or more
# contributor license agreements. See the NOTICE file distributed with
# this work for additional information regarding copyright ownership. The
# ASF licenses this file to you under the Apache License, Version 2.0 (the
# "License"); you may not use this file except in compliance with the
# License. You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
# License for the specific language governing permissions and limitations
# under the License.
#
############################################################################
include $(TOPDIR)/Make.defs
CSRCS = bl602_bringup.c bl602_boot.c
ifeq ($(CONFIG_LIB_BOARDCTL),y)
CSRCS += bl602_appinit.c
endif
include $(TOPDIR)/boards/Board.mk

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/****************************************************************************
* boards/risc-v/bl602/evb/src/litex_appinit.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdbool.h>
#include <stdio.h>
#include <syslog.h>
#include <errno.h>
#include <nuttx/board.h>
#include "chip.h"
#include "bl602evb.h"
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: board_app_initialize
*
* Description:
* Perform architecture specific initialization
*
* Input Parameters:
* arg - The boardctl() argument is passed to the board_app_initialize()
* implementation without modification. The argument has no
* meaning to NuttX; the meaning of the argument is a contract
* between the board-specific initialization logic and the
* matching application logic. The value could be such things as a
* mode enumeration value, a set of DIP switch switch settings, a
* pointer to configuration data read from a file or serial FLASH,
* or whatever you would like to do with it. Every implementation
* should accept zero/NULL as a default configuration.
*
* Returned Value:
* Zero (OK) is returned on success; a negated errno value is returned on
* any failure to indicate the nature of the failure.
*
****************************************************************************/
int board_app_initialize(uintptr_t arg)
{
bl602_bringup();
return 0;
}

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/****************************************************************************
* boards/risc-v/bl602/evb/src/litex_boot.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <debug.h>
#include <nuttx/board.h>
#include <arch/board/board.h>
#include "hardware/bl602_hbn.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: bl602_boardinitialize
*
* Description:
* All LITEX architectures must provide the following entry point.
* This entry point is called early in the initialization -- after all
* memory has been configured and mapped but before any devices have been
* initialized.
*
****************************************************************************/
void bl602_boardinitialize(void)
{
uint32_t tmp_val;
tmp_val = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE);
tmp_val = BL_SET_REG_BITS_VAL(tmp_val, HBN_REG_AON_PAD_IE_SMT, 1);
BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmp_val);
}

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/****************************************************************************
* boards/risc-v/bl602/evb/src/litex_bringup.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <nuttx/timers/oneshot.h>
#include <sys/mount.h>
#include <stdbool.h>
#include <stdio.h>
#include <syslog.h>
#include <errno.h>
#include <nuttx/board.h>
#include <nuttx/input/buttons.h>
#include <bl602_tim_lowerhalf.h>
#include <bl602_oneshot_lowerhalf.h>
#include "chip.h"
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: bl602_bringup
****************************************************************************/
int bl602_bringup(void)
{
#if defined(CONFIG_TIMER) && defined(CONFIG_ONESHOT) && \
defined(CONFIG_BL602_TIMER1)
struct oneshot_lowerhalf_s *os = NULL;
#endif
int ret = OK;
#ifdef CONFIG_FS_PROCFS
/* Mount the procfs file system */
ret = mount(NULL, "/proc", "procfs", 0, NULL);
if (ret < 0)
{
syslog(
LOG_ERR, "ERROR: Failed to mount procfs at %s: %d\n", "/proc", ret);
return ret;
}
#endif
#if defined(CONFIG_TIMER)
#if defined(CONFIG_BL602_TIMER0)
ret = bl602_timer_initialize("/dev/timer0", 0);
if (ret < 0)
{
syslog(LOG_ERR, "Failed to initialize /dev/timer0 Driver: %d\n", ret);
return ret;
}
#endif
#if defined(CONFIG_BL602_TIMER1) && !defined(CONFIG_ONESHOT)
ret = bl602_timer_initialize("/dev/timer1", 1);
if (ret < 0)
{
syslog(LOG_ERR, "Failed to initialize /dev/timer1 Driver: %d\n", ret);
return ret;
}
#elif defined(CONFIG_BL602_TIMER1) && defined(CONFIG_ONESHOT)
os = oneshot_initialize(1, 1);
if (os == NULL)
{
syslog(LOG_ERR, "ERROR: oneshot_initialize failed\n");
}
else
{
#ifdef CONFIG_CPULOAD_ONESHOT
/* Configure the oneshot timer to support CPU load measurement */
nxsched_oneshot_extclk(os);
#else
ret = oneshot_register("/dev/oneshot", os);
if (ret < 0)
{
syslog(LOG_ERR,
"ERROR: Failed to register oneshot at /dev/oneshot: %d\n",
ret);
}
#endif
}
#endif
#endif
return ret;
}

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/****************************************************************************
* boards/risc-v/bl602/bl602evb/src/bl602evb.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __BOARDS_RISCV_BL602_BL602EVB_SRC_BL602EVB_H
#define __BOARDS_RISCV_BL602_BL602EVB_SRC_BL602EVB_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
int bl602_bringup(void);
#endif /* __BOARDS_RISCV_BL602_EVB_SRC_ARTY_A7_H */