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arch/arm/src/lpc54xx: Implement GPIO interrupt support. configs/lpcxpress-lpc54628: Add support for the USER button. Enable the apps/examples/button test in the NSH configuration.
This commit is contained in:
Gregory Nutt
parent
83b382e906
commit
5a12079e53
20 changed files with 697 additions and 243 deletions
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@ -51,7 +51,7 @@
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#define LPC54_IRQ_GINT0 (LPC54_IRQ_EXTINT+2) /* GPIO group 0 */
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#define LPC54_IRQ_GINT1 (LPC54_IRQ_EXTINT+3) /* GPIO group 1 */
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#define LPC54_IRQ_PININT0 (LPC54_IRQ_EXTINT+4) /* Pin interrupt 0 or pattern match engine slice 0 */
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#define LPC54_IRQ_PININT1 (LPC54_IRQ_EXTINT+5) /* Pin interrupt 1or pattern match engine slice 1 */
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#define LPC54_IRQ_PININT1 (LPC54_IRQ_EXTINT+5) /* Pin interrupt 1 or pattern match engine slice 1 */
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#define LPC54_IRQ_PININT2 (LPC54_IRQ_EXTINT+6) /* Pin interrupt 2 or pattern match engine slice 2 */
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#define LPC54_IRQ_PININT3 (LPC54_IRQ_EXTINT+7) /* Pin interrupt 3 or pattern match engine slice 3 */
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#define LPC54_IRQ_UTICK (LPC54_IRQ_EXTINT+8) /* Micro-tick Timer */
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@ -405,7 +405,7 @@ config LPC54_GPIOIRQ
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default n
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config LPC54_GPIOIRQ_GROUPS
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bool "Support GPIO Interrupt groupe"
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bool "Support GPIO Interrupt groups"
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default n
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depends on LPC54_GPIOIRQ && EXPERIMENTAL
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@ -49,151 +49,159 @@
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/* Register offsets *********************************************************************************/
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#define LPC54_MUX_SCT0_INMUX0_OFFSET 0x0000 /* Input mux register for SCT0 input 0 */
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#define LPC54_MUX_SCT0_INMUX1_OFFSET 0x0004 /* Input mux register for SCT0 input 1 */
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#define LPC54_MUX_SCT0_INMUX2_OFFSET 0x0008 /* Input mux register for SCT0 input 2 */
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#define LPC54_MUX_SCT0_INMUX3_OFFSET 0x000c /* Input mux register for SCT0 input 3 */
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#define LPC54_MUX_SCT0_INMUX4_OFFSET 0x0010 /* Input mux register for SCT0 input 4 */
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#define LPC54_MUX_SCT0_INMUX5_OFFSET 0x0014 /* Input mux register for SCT0 input 5 */
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#define LPC54_MUX_SCT0_INMUX6_OFFSET 0x0018 /* Input mux register for SCT0 input 6 */
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#define LPC54_MUX_SCT0_INMUX_OFFSET(n) (0x0000 + ((n) << 2))
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#define LPC54_MUX_SCT0_INMUX0_OFFSET 0x0000 /* Input mux register for SCT0 input 0 */
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#define LPC54_MUX_SCT0_INMUX1_OFFSET 0x0004 /* Input mux register for SCT0 input 1 */
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#define LPC54_MUX_SCT0_INMUX2_OFFSET 0x0008 /* Input mux register for SCT0 input 2 */
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#define LPC54_MUX_SCT0_INMUX3_OFFSET 0x000c /* Input mux register for SCT0 input 3 */
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#define LPC54_MUX_SCT0_INMUX4_OFFSET 0x0010 /* Input mux register for SCT0 input 4 */
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#define LPC54_MUX_SCT0_INMUX5_OFFSET 0x0014 /* Input mux register for SCT0 input 5 */
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#define LPC54_MUX_SCT0_INMUX6_OFFSET 0x0018 /* Input mux register for SCT0 input 6 */
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#define LPC54_MUX_PINTSEL0_OFFSET 0x00c0 /* Pin interrupt select register 0 */
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#define LPC54_MUX_PINTSEL1_OFFSET 0x00c4 /* Pin interrupt select register 1 */
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#define LPC54_MUX_PINTSEL2_OFFSET 0x00c8 /* Pin interrupt select register 2 */
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#define LPC54_MUX_PINTSEL3_OFFSET 0x00cc /* Pin interrupt select register 3 */
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#define LPC54_MUX_PINTSEL4_OFFSET 0x00d0 /* Pin interrupt select register 4 */
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#define LPC54_MUX_PINTSEL5_OFFSET 0x00d4 /* Pin interrupt select register 5 */
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#define LPC54_MUX_PINTSEL6_OFFSET 0x00d8 /* Pin interrupt select register 6 */
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#define LPC54_MUX_PINTSEL7_OFFSET 0x00dc /* Pin interrupt select register 7 */
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#define LPC54_MUX_PINTSEL_OFFSET(n) (0x00c0 + ((n) << 2))
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#define LPC54_MUX_PINTSEL0_OFFSET 0x00c0 /* Pin interrupt select register 0 */
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#define LPC54_MUX_PINTSEL1_OFFSET 0x00c4 /* Pin interrupt select register 1 */
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#define LPC54_MUX_PINTSEL2_OFFSET 0x00c8 /* Pin interrupt select register 2 */
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#define LPC54_MUX_PINTSEL3_OFFSET 0x00cc /* Pin interrupt select register 3 */
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#define LPC54_MUX_PINTSEL4_OFFSET 0x00d0 /* Pin interrupt select register 4 */
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#define LPC54_MUX_PINTSEL5_OFFSET 0x00d4 /* Pin interrupt select register 5 */
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#define LPC54_MUX_PINTSEL6_OFFSET 0x00d8 /* Pin interrupt select register 6 */
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#define LPC54_MUX_PINTSEL7_OFFSET 0x00dc /* Pin interrupt select register 7 */
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#define LPC54_MUX_DMA_ITRIG_INMUX0_OFFSET 0x00e0 /* Trigger select register for DMA channel 0 */
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#define LPC54_MUX_DMA_ITRIG_INMUX1_OFFSET 0x00e4 /* Trigger select register for DMA channel 1 */
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#define LPC54_MUX_DMA_ITRIG_INMUX2_OFFSET 0x00e8 /* Trigger select register for DMA channel 2 */
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#define LPC54_MUX_DMA_ITRIG_INMUX3_OFFSET 0x00ec /* Trigger select register for DMA channel 3 */
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#define LPC54_MUX_DMA_ITRIG_INMUX4_OFFSET 0x00f0 /* Trigger select register for DMA channel 4 */
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#define LPC54_MUX_DMA_ITRIG_INMUX5_OFFSET 0x00f4 /* Trigger select register for DMA channel 5 */
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#define LPC54_MUX_DMA_ITRIG_INMUX6_OFFSET 0x00f8 /* Trigger select register for DMA channel 6 */
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#define LPC54_MUX_DMA_ITRIG_INMUX7_OFFSET 0x00fc /* Trigger select register for DMA channel 7 */
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#define LPC54_MUX_DMA_ITRIG_INMUX8_OFFSET 0x0100 /* Trigger select register for DMA channel 8 */
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#define LPC54_MUX_DMA_ITRIG_INMUX9_OFFSET 0x0104 /* Trigger select register for DMA channel 9 */
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#define LPC54_MUX_DMA_ITRIG_INMUX10_OFFSET 0x0108 /* Trigger select register for DMA channel 10 */
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#define LPC54_MUX_DMA_ITRIG_INMUX11_OFFSET 0x010c /* Trigger select register for DMA channel 11 */
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#define LPC54_MUX_DMA_ITRIG_INMUX12_OFFSET 0x0110 /* Trigger select register for DMA channel 12 */
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#define LPC54_MUX_DMA_ITRIG_INMUX13_OFFSET 0x0114 /* Trigger select register for DMA channel 13 */
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#define LPC54_MUX_DMA_ITRIG_INMUX14_OFFSET 0x0118 /* Trigger select register for DMA channel 14 */
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#define LPC54_MUX_DMA_ITRIG_INMUX15_OFFSET 0x011c /* Trigger select register for DMA channel 15 */
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#define LPC54_MUX_DMA_ITRIG_INMUX16_OFFSET 0x0120 /* Trigger select register for DMA channel 16 */
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#define LPC54_MUX_DMA_ITRIG_INMUX17_OFFSET 0x0124 /* Trigger select register for DMA channel 17 */
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#define LPC54_MUX_DMA_ITRIG_INMUX18_OFFSET 0x0128 /* Trigger select register for DMA channel 18 */
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#define LPC54_MUX_DMA_ITRIG_INMUX19_OFFSET 0x012c /* Trigger select register for DMA channel 19 */
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#define LPC54_MUX_DMA_ITRIG_INMUX20_OFFSET 0x0130 /* Trigger select register for DMA channel 20 */
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#define LPC54_MUX_DMA_ITRIG_INMUX21_OFFSET 0x0134 /* Trigger select register for DMA channel 21 */
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#define LPC54_MUX_DMA_ITRIG_INMUX22_OFFSET 0x0138 /* Trigger select register for DMA channel 22 */
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#define LPC54_MUX_DMA_ITRIG_INMUX23_OFFSET 0x013c /* Trigger select register for DMA channel 23 */
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#define LPC54_MUX_DMA_ITRIG_INMUX24_OFFSET 0x0140 /* Trigger select register for DMA channel 24 */
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#define LPC54_MUX_DMA_ITRIG_INMUX25_OFFSET 0x0144 /* Trigger select register for DMA channel 25 */
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#define LPC54_MUX_DMA_ITRIG_INMUX26_OFFSET 0x0148 /* Trigger select register for DMA channel 26 */
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#define LPC54_MUX_DMA_ITRIG_INMUX27_OFFSET 0x014c /* Trigger select register for DMA channel 27 */
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#define LPC54_MUX_DMA_ITRIG_INMUX28_OFFSET 0x0150 /* Trigger select register for DMA channel 28 */
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#define LPC54_MUX_DMA_ITRIG_INMUX29_OFFSET 0x0154 /* Trigger select register for DMA channel 29 */
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#define LPC54_MUX_DMA_ITRIG_INMUX_OFFSET(n) (0x00e0 + ((n) << 2))
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#define LPC54_MUX_DMA_ITRIG_INMUX0_OFFSET 0x00e0 /* Trigger select register for DMA channel 0 */
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#define LPC54_MUX_DMA_ITRIG_INMUX1_OFFSET 0x00e4 /* Trigger select register for DMA channel 1 */
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#define LPC54_MUX_DMA_ITRIG_INMUX2_OFFSET 0x00e8 /* Trigger select register for DMA channel 2 */
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#define LPC54_MUX_DMA_ITRIG_INMUX3_OFFSET 0x00ec /* Trigger select register for DMA channel 3 */
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#define LPC54_MUX_DMA_ITRIG_INMUX4_OFFSET 0x00f0 /* Trigger select register for DMA channel 4 */
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#define LPC54_MUX_DMA_ITRIG_INMUX5_OFFSET 0x00f4 /* Trigger select register for DMA channel 5 */
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#define LPC54_MUX_DMA_ITRIG_INMUX6_OFFSET 0x00f8 /* Trigger select register for DMA channel 6 */
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#define LPC54_MUX_DMA_ITRIG_INMUX7_OFFSET 0x00fc /* Trigger select register for DMA channel 7 */
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#define LPC54_MUX_DMA_ITRIG_INMUX8_OFFSET 0x0100 /* Trigger select register for DMA channel 8 */
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#define LPC54_MUX_DMA_ITRIG_INMUX9_OFFSET 0x0104 /* Trigger select register for DMA channel 9 */
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#define LPC54_MUX_DMA_ITRIG_INMUX10_OFFSET 0x0108 /* Trigger select register for DMA channel 10 */
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#define LPC54_MUX_DMA_ITRIG_INMUX11_OFFSET 0x010c /* Trigger select register for DMA channel 11 */
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#define LPC54_MUX_DMA_ITRIG_INMUX12_OFFSET 0x0110 /* Trigger select register for DMA channel 12 */
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#define LPC54_MUX_DMA_ITRIG_INMUX13_OFFSET 0x0114 /* Trigger select register for DMA channel 13 */
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#define LPC54_MUX_DMA_ITRIG_INMUX14_OFFSET 0x0118 /* Trigger select register for DMA channel 14 */
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#define LPC54_MUX_DMA_ITRIG_INMUX15_OFFSET 0x011c /* Trigger select register for DMA channel 15 */
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#define LPC54_MUX_DMA_ITRIG_INMUX16_OFFSET 0x0120 /* Trigger select register for DMA channel 16 */
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#define LPC54_MUX_DMA_ITRIG_INMUX17_OFFSET 0x0124 /* Trigger select register for DMA channel 17 */
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#define LPC54_MUX_DMA_ITRIG_INMUX18_OFFSET 0x0128 /* Trigger select register for DMA channel 18 */
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#define LPC54_MUX_DMA_ITRIG_INMUX19_OFFSET 0x012c /* Trigger select register for DMA channel 19 */
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#define LPC54_MUX_DMA_ITRIG_INMUX20_OFFSET 0x0130 /* Trigger select register for DMA channel 20 */
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#define LPC54_MUX_DMA_ITRIG_INMUX21_OFFSET 0x0134 /* Trigger select register for DMA channel 21 */
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#define LPC54_MUX_DMA_ITRIG_INMUX22_OFFSET 0x0138 /* Trigger select register for DMA channel 22 */
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#define LPC54_MUX_DMA_ITRIG_INMUX23_OFFSET 0x013c /* Trigger select register for DMA channel 23 */
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#define LPC54_MUX_DMA_ITRIG_INMUX24_OFFSET 0x0140 /* Trigger select register for DMA channel 24 */
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#define LPC54_MUX_DMA_ITRIG_INMUX25_OFFSET 0x0144 /* Trigger select register for DMA channel 25 */
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#define LPC54_MUX_DMA_ITRIG_INMUX26_OFFSET 0x0148 /* Trigger select register for DMA channel 26 */
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#define LPC54_MUX_DMA_ITRIG_INMUX27_OFFSET 0x014c /* Trigger select register for DMA channel 27 */
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#define LPC54_MUX_DMA_ITRIG_INMUX28_OFFSET 0x0150 /* Trigger select register for DMA channel 28 */
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#define LPC54_MUX_DMA_ITRIG_INMUX29_OFFSET 0x0154 /* Trigger select register for DMA channel 29 */
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#define LPC54_MUX_DMA_OTRIG_INMUX0_OFFSET 0x0160 /* DMA output trigger selection to become DMA trigger 18 */
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#define LPC54_MUX_DMA_OTRIG_INMUX1_OFFSET 0x0164 /* DMA output trigger selection to become DMA trigger 19 */
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#define LPC54_MUX_DMA_OTRIG_INMUX2_OFFSET 0x0168 /* DMA output trigger selection to become DMA trigger 20 */
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#define LPC54_MUX_DMA_OTRIG_INMUX3_OFFSET 0x016c /* DMA output trigger selection to become DMA trigger 21 */
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#define LPC54_MUX_DMA_OTRIG_INMUX_OFFSET(n) (0x0160 + ((n) << 2))
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#define LPC54_MUX_DMA_OTRIG_INMUX0_OFFSET 0x0160 /* DMA output trigger selection to become DMA trigger 18 */
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#define LPC54_MUX_DMA_OTRIG_INMUX1_OFFSET 0x0164 /* DMA output trigger selection to become DMA trigger 19 */
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#define LPC54_MUX_DMA_OTRIG_INMUX2_OFFSET 0x0168 /* DMA output trigger selection to become DMA trigger 20 */
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#define LPC54_MUX_DMA_OTRIG_INMUX3_OFFSET 0x016c /* DMA output trigger selection to become DMA trigger 21 */
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#define LPC54_MUX_FREQMEAS_REF_OFFSET 0x0180 /* Selection for frequency measurement reference clock */
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#define LPC54_MUX_FREQMEAS_TARGET_OFFSET 0x0184 /* Selection for frequency measurement target clock */
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#define LPC54_MUX_FREQMEAS_REF_OFFSET 0x0180 /* Selection for frequency measurement reference clock */
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#define LPC54_MUX_FREQMEAS_TARGET_OFFSET 0x0184 /* Selection for frequency measurement target clock */
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/* Register addresses *******************************************************************************/
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#define LPC54_MUX_SCT0_INMUX0 (LPC54_MUX_BASE + LPC54_MUX_SCT0_INMUX0_OFFSET)
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#define LPC54_MUX_SCT0_INMUX1 (LPC54_MUX_BASE + LPC54_MUX_SCT0_INMUX1_OFFSET)
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#define LPC54_MUX_SCT0_INMUX2 (LPC54_MUX_BASE + LPC54_MUX_SCT0_INMUX2_OFFSET)
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#define LPC54_MUX_SCT0_INMUX3 (LPC54_MUX_BASE + LPC54_MUX_SCT0_INMUX3_OFFSET)
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#define LPC54_MUX_SCT0_INMUX4 (LPC54_MUX_BASE + LPC54_MUX_SCT0_INMUX4_OFFSET)
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#define LPC54_MUX_SCT0_INMUX5 (LPC54_MUX_BASE + LPC54_MUX_SCT0_INMUX5_OFFSET)
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#define LPC54_MUX_SCT0_INMUX6 (LPC54_MUX_BASE + LPC54_MUX_SCT0_INMUX6_OFFSET)
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#define LPC54_MUX_SCT0_INMUX(n) (LPC54_MUX_BASE + LPC54_MUX_SCT0_INMUX_OFFSET(n))
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#define LPC54_MUX_SCT0_INMUX0 (LPC54_MUX_BASE + LPC54_MUX_SCT0_INMUX0_OFFSET)
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#define LPC54_MUX_SCT0_INMUX1 (LPC54_MUX_BASE + LPC54_MUX_SCT0_INMUX1_OFFSET)
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#define LPC54_MUX_SCT0_INMUX2 (LPC54_MUX_BASE + LPC54_MUX_SCT0_INMUX2_OFFSET)
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#define LPC54_MUX_SCT0_INMUX3 (LPC54_MUX_BASE + LPC54_MUX_SCT0_INMUX3_OFFSET)
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#define LPC54_MUX_SCT0_INMUX4 (LPC54_MUX_BASE + LPC54_MUX_SCT0_INMUX4_OFFSET)
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#define LPC54_MUX_SCT0_INMUX5 (LPC54_MUX_BASE + LPC54_MUX_SCT0_INMUX5_OFFSET)
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#define LPC54_MUX_SCT0_INMUX6 (LPC54_MUX_BASE + LPC54_MUX_SCT0_INMUX6_OFFSET)
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#define LPC54_MUX_PINTSEL0 (LPC54_MUX_BASE + LPC54_MUX_PINTSEL0_OFFSET)
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#define LPC54_MUX_PINTSEL1 (LPC54_MUX_BASE + LPC54_MUX_PINTSEL1_OFFSET)
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#define LPC54_MUX_PINTSEL2 (LPC54_MUX_BASE + LPC54_MUX_PINTSEL2_OFFSET)
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#define LPC54_MUX_PINTSEL3 (LPC54_MUX_BASE + LPC54_MUX_PINTSEL3_OFFSET)
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#define LPC54_MUX_PINTSEL4 (LPC54_MUX_BASE + LPC54_MUX_PINTSEL4_OFFSET)
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#define LPC54_MUX_PINTSEL5 (LPC54_MUX_BASE + LPC54_MUX_PINTSEL5_OFFSET)
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#define LPC54_MUX_PINTSEL6 (LPC54_MUX_BASE + LPC54_MUX_PINTSEL6_OFFSET)
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#define LPC54_MUX_PINTSEL7 (LPC54_MUX_BASE + LPC54_MUX_PINTSEL7_OFFSET)
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#define LPC54_MUX_PINTSEL(n) (LPC54_MUX_BASE + LPC54_MUX_PINTSEL_OFFSET(n))
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#define LPC54_MUX_PINTSEL0 (LPC54_MUX_BASE + LPC54_MUX_PINTSEL0_OFFSET)
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#define LPC54_MUX_PINTSEL1 (LPC54_MUX_BASE + LPC54_MUX_PINTSEL1_OFFSET)
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#define LPC54_MUX_PINTSEL2 (LPC54_MUX_BASE + LPC54_MUX_PINTSEL2_OFFSET)
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#define LPC54_MUX_PINTSEL3 (LPC54_MUX_BASE + LPC54_MUX_PINTSEL3_OFFSET)
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#define LPC54_MUX_PINTSEL4 (LPC54_MUX_BASE + LPC54_MUX_PINTSEL4_OFFSET)
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#define LPC54_MUX_PINTSEL5 (LPC54_MUX_BASE + LPC54_MUX_PINTSEL5_OFFSET)
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#define LPC54_MUX_PINTSEL6 (LPC54_MUX_BASE + LPC54_MUX_PINTSEL6_OFFSET)
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#define LPC54_MUX_PINTSEL7 (LPC54_MUX_BASE + LPC54_MUX_PINTSEL7_OFFSET)
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#define LPC54_MUX_DMA_ITRIG_INMUX0 (LPC54_MUX_BASE + LPC54_MUX_DMA_ITRIG_INMUX0_OFFSET)
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#define LPC54_MUX_DMA_ITRIG_INMUX1 (LPC54_MUX_BASE + LPC54_MUX_DMA_ITRIG_INMUX1_OFFSET)
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#define LPC54_MUX_DMA_ITRIG_INMUX2 (LPC54_MUX_BASE + LPC54_MUX_DMA_ITRIG_INMUX2_OFFSET)
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#define LPC54_MUX_DMA_ITRIG_INMUX3 (LPC54_MUX_BASE + LPC54_MUX_DMA_ITRIG_INMUX3_OFFSET)
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#define LPC54_MUX_DMA_ITRIG_INMUX4 (LPC54_MUX_BASE + LPC54_MUX_DMA_ITRIG_INMUX4_OFFSET)
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#define LPC54_MUX_DMA_ITRIG_INMUX5 (LPC54_MUX_BASE + LPC54_MUX_DMA_ITRIG_INMUX5_OFFSET)
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#define LPC54_MUX_DMA_ITRIG_INMUX6 (LPC54_MUX_BASE + LPC54_MUX_DMA_ITRIG_INMUX6_OFFSET)
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#define LPC54_MUX_DMA_ITRIG_INMUX7 (LPC54_MUX_BASE + LPC54_MUX_DMA_ITRIG_INMUX7_OFFSET)
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#define LPC54_MUX_DMA_ITRIG_INMUX8 (LPC54_MUX_BASE + LPC54_MUX_DMA_ITRIG_INMUX8_OFFSET)
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#define LPC54_MUX_DMA_ITRIG_INMUX9 (LPC54_MUX_BASE + LPC54_MUX_DMA_ITRIG_INMUX9_OFFSET)
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#define LPC54_MUX_DMA_ITRIG_INMUX10 (LPC54_MUX_BASE + LPC54_MUX_DMA_ITRIG_INMUX10_OFFSET)
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#define LPC54_MUX_DMA_ITRIG_INMUX11 (LPC54_MUX_BASE + LPC54_MUX_DMA_ITRIG_INMUX11_OFFSET)
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#define LPC54_MUX_DMA_ITRIG_INMUX12 (LPC54_MUX_BASE + LPC54_MUX_DMA_ITRIG_INMUX12_OFFSET)
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#define LPC54_MUX_DMA_ITRIG_INMUX13 (LPC54_MUX_BASE + LPC54_MUX_DMA_ITRIG_INMUX13_OFFSET)
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#define LPC54_MUX_DMA_ITRIG_INMUX14 (LPC54_MUX_BASE + LPC54_MUX_DMA_ITRIG_INMUX14_OFFSET)
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#define LPC54_MUX_DMA_ITRIG_INMUX15 (LPC54_MUX_BASE + LPC54_MUX_DMA_ITRIG_INMUX15_OFFSET)
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#define LPC54_MUX_DMA_ITRIG_INMUX16 (LPC54_MUX_BASE + LPC54_MUX_DMA_ITRIG_INMUX16_OFFSET)
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#define LPC54_MUX_DMA_ITRIG_INMUX17 (LPC54_MUX_BASE + LPC54_MUX_DMA_ITRIG_INMUX17_OFFSET)
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#define LPC54_MUX_DMA_ITRIG_INMUX18 (LPC54_MUX_BASE + LPC54_MUX_DMA_ITRIG_INMUX18_OFFSET)
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#define LPC54_MUX_DMA_ITRIG_INMUX19 (LPC54_MUX_BASE + LPC54_MUX_DMA_ITRIG_INMUX19_OFFSET)
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#define LPC54_MUX_DMA_ITRIG_INMUX20 (LPC54_MUX_BASE + LPC54_MUX_DMA_ITRIG_INMUX20_OFFSET)
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#define LPC54_MUX_DMA_ITRIG_INMUX21 (LPC54_MUX_BASE + LPC54_MUX_DMA_ITRIG_INMUX21_OFFSET)
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#define LPC54_MUX_DMA_ITRIG_INMUX22 (LPC54_MUX_BASE + LPC54_MUX_DMA_ITRIG_INMUX22_OFFSET)
|
||||
#define LPC54_MUX_DMA_ITRIG_INMUX23 (LPC54_MUX_BASE + LPC54_MUX_DMA_ITRIG_INMUX23_OFFSET)
|
||||
#define LPC54_MUX_DMA_ITRIG_INMUX24 (LPC54_MUX_BASE + LPC54_MUX_DMA_ITRIG_INMUX24_OFFSET)
|
||||
#define LPC54_MUX_DMA_ITRIG_INMUX25 (LPC54_MUX_BASE + LPC54_MUX_DMA_ITRIG_INMUX25_OFFSET)
|
||||
#define LPC54_MUX_DMA_ITRIG_INMUX26 (LPC54_MUX_BASE + LPC54_MUX_DMA_ITRIG_INMUX26_OFFSET)
|
||||
#define LPC54_MUX_DMA_ITRIG_INMUX27 (LPC54_MUX_BASE + LPC54_MUX_DMA_ITRIG_INMUX27_OFFSET)
|
||||
#define LPC54_MUX_DMA_ITRIG_INMUX28 (LPC54_MUX_BASE + LPC54_MUX_DMA_ITRIG_INMUX28_OFFSET)
|
||||
#define LPC54_MUX_DMA_ITRIG_INMUX29 (LPC54_MUX_BASE + LPC54_MUX_DMA_ITRIG_INMUX29_OFFSET)
|
||||
#define LPC54_MUX_DMA_ITRIG_INMUX(n) (LPC54_MUX_BASE + LPC54_MUX_DMA_ITRIG_INMUX_OFFSET(n))
|
||||
#define LPC54_MUX_DMA_ITRIG_INMUX0 (LPC54_MUX_BASE + LPC54_MUX_DMA_ITRIG_INMUX0_OFFSET)
|
||||
#define LPC54_MUX_DMA_ITRIG_INMUX1 (LPC54_MUX_BASE + LPC54_MUX_DMA_ITRIG_INMUX1_OFFSET)
|
||||
#define LPC54_MUX_DMA_ITRIG_INMUX2 (LPC54_MUX_BASE + LPC54_MUX_DMA_ITRIG_INMUX2_OFFSET)
|
||||
#define LPC54_MUX_DMA_ITRIG_INMUX3 (LPC54_MUX_BASE + LPC54_MUX_DMA_ITRIG_INMUX3_OFFSET)
|
||||
#define LPC54_MUX_DMA_ITRIG_INMUX4 (LPC54_MUX_BASE + LPC54_MUX_DMA_ITRIG_INMUX4_OFFSET)
|
||||
#define LPC54_MUX_DMA_ITRIG_INMUX5 (LPC54_MUX_BASE + LPC54_MUX_DMA_ITRIG_INMUX5_OFFSET)
|
||||
#define LPC54_MUX_DMA_ITRIG_INMUX6 (LPC54_MUX_BASE + LPC54_MUX_DMA_ITRIG_INMUX6_OFFSET)
|
||||
#define LPC54_MUX_DMA_ITRIG_INMUX7 (LPC54_MUX_BASE + LPC54_MUX_DMA_ITRIG_INMUX7_OFFSET)
|
||||
#define LPC54_MUX_DMA_ITRIG_INMUX8 (LPC54_MUX_BASE + LPC54_MUX_DMA_ITRIG_INMUX8_OFFSET)
|
||||
#define LPC54_MUX_DMA_ITRIG_INMUX9 (LPC54_MUX_BASE + LPC54_MUX_DMA_ITRIG_INMUX9_OFFSET)
|
||||
#define LPC54_MUX_DMA_ITRIG_INMUX10 (LPC54_MUX_BASE + LPC54_MUX_DMA_ITRIG_INMUX10_OFFSET)
|
||||
#define LPC54_MUX_DMA_ITRIG_INMUX11 (LPC54_MUX_BASE + LPC54_MUX_DMA_ITRIG_INMUX11_OFFSET)
|
||||
#define LPC54_MUX_DMA_ITRIG_INMUX12 (LPC54_MUX_BASE + LPC54_MUX_DMA_ITRIG_INMUX12_OFFSET)
|
||||
#define LPC54_MUX_DMA_ITRIG_INMUX13 (LPC54_MUX_BASE + LPC54_MUX_DMA_ITRIG_INMUX13_OFFSET)
|
||||
#define LPC54_MUX_DMA_ITRIG_INMUX14 (LPC54_MUX_BASE + LPC54_MUX_DMA_ITRIG_INMUX14_OFFSET)
|
||||
#define LPC54_MUX_DMA_ITRIG_INMUX15 (LPC54_MUX_BASE + LPC54_MUX_DMA_ITRIG_INMUX15_OFFSET)
|
||||
#define LPC54_MUX_DMA_ITRIG_INMUX16 (LPC54_MUX_BASE + LPC54_MUX_DMA_ITRIG_INMUX16_OFFSET)
|
||||
#define LPC54_MUX_DMA_ITRIG_INMUX17 (LPC54_MUX_BASE + LPC54_MUX_DMA_ITRIG_INMUX17_OFFSET)
|
||||
#define LPC54_MUX_DMA_ITRIG_INMUX18 (LPC54_MUX_BASE + LPC54_MUX_DMA_ITRIG_INMUX18_OFFSET)
|
||||
#define LPC54_MUX_DMA_ITRIG_INMUX19 (LPC54_MUX_BASE + LPC54_MUX_DMA_ITRIG_INMUX19_OFFSET)
|
||||
#define LPC54_MUX_DMA_ITRIG_INMUX20 (LPC54_MUX_BASE + LPC54_MUX_DMA_ITRIG_INMUX20_OFFSET)
|
||||
#define LPC54_MUX_DMA_ITRIG_INMUX21 (LPC54_MUX_BASE + LPC54_MUX_DMA_ITRIG_INMUX21_OFFSET)
|
||||
#define LPC54_MUX_DMA_ITRIG_INMUX22 (LPC54_MUX_BASE + LPC54_MUX_DMA_ITRIG_INMUX22_OFFSET)
|
||||
#define LPC54_MUX_DMA_ITRIG_INMUX23 (LPC54_MUX_BASE + LPC54_MUX_DMA_ITRIG_INMUX23_OFFSET)
|
||||
#define LPC54_MUX_DMA_ITRIG_INMUX24 (LPC54_MUX_BASE + LPC54_MUX_DMA_ITRIG_INMUX24_OFFSET)
|
||||
#define LPC54_MUX_DMA_ITRIG_INMUX25 (LPC54_MUX_BASE + LPC54_MUX_DMA_ITRIG_INMUX25_OFFSET)
|
||||
#define LPC54_MUX_DMA_ITRIG_INMUX26 (LPC54_MUX_BASE + LPC54_MUX_DMA_ITRIG_INMUX26_OFFSET)
|
||||
#define LPC54_MUX_DMA_ITRIG_INMUX27 (LPC54_MUX_BASE + LPC54_MUX_DMA_ITRIG_INMUX27_OFFSET)
|
||||
#define LPC54_MUX_DMA_ITRIG_INMUX28 (LPC54_MUX_BASE + LPC54_MUX_DMA_ITRIG_INMUX28_OFFSET)
|
||||
#define LPC54_MUX_DMA_ITRIG_INMUX29 (LPC54_MUX_BASE + LPC54_MUX_DMA_ITRIG_INMUX29_OFFSET)
|
||||
|
||||
#define LPC54_MUX_DMA_OTRIG_INMUX0 (LPC54_MUX_BASE + LPC54_MUX_DMA_OTRIG_INMUX0_OFFSET)
|
||||
#define LPC54_MUX_DMA_OTRIG_INMUX1 (LPC54_MUX_BASE + LPC54_MUX_DMA_OTRIG_INMUX1_OFFSET)
|
||||
#define LPC54_MUX_DMA_OTRIG_INMUX2 (LPC54_MUX_BASE + LPC54_MUX_DMA_OTRIG_INMUX2_OFFSET)
|
||||
#define LPC54_MUX_DMA_OTRIG_INMUX3 (LPC54_MUX_BASE + LPC54_MUX_DMA_OTRIG_INMUX3_OFFSET)
|
||||
#define LPC54_MUX_DMA_OTRIG_INMUX(n) (LPC54_MUX_BASE + LPC54_MUX_DMA_OTRIG_INMUX_OFFSET(n))
|
||||
#define LPC54_MUX_DMA_OTRIG_INMUX0 (LPC54_MUX_BASE + LPC54_MUX_DMA_OTRIG_INMUX0_OFFSET)
|
||||
#define LPC54_MUX_DMA_OTRIG_INMUX1 (LPC54_MUX_BASE + LPC54_MUX_DMA_OTRIG_INMUX1_OFFSET)
|
||||
#define LPC54_MUX_DMA_OTRIG_INMUX2 (LPC54_MUX_BASE + LPC54_MUX_DMA_OTRIG_INMUX2_OFFSET)
|
||||
#define LPC54_MUX_DMA_OTRIG_INMUX3 (LPC54_MUX_BASE + LPC54_MUX_DMA_OTRIG_INMUX3_OFFSET)
|
||||
|
||||
#define LPC54_MUX_FREQMEAS_REF (LPC54_MUX_BASE + LPC54_MUX_FREQMEAS_REF_OFFSET)
|
||||
#define LPC54_MUX_FREQMEAS_TARGET (LPC54_MUX_BASE + LPC54_MUX_FREQMEAS_TARGET_OFFSET)
|
||||
#define LPC54_MUX_FREQMEAS_REF (LPC54_MUX_BASE + LPC54_MUX_FREQMEAS_REF_OFFSET)
|
||||
#define LPC54_MUX_FREQMEAS_TARGET (LPC54_MUX_BASE + LPC54_MUX_FREQMEAS_TARGET_OFFSET)
|
||||
|
||||
/* Register bit definitions *************************************************************************/
|
||||
|
||||
/* Input mux register for SCT0 input 0-6 */
|
||||
|
||||
#define MUX_SCT0_INMUX_SHIFT (0) /* Bits 0-4: Input number to SCT0 inputs 0 to 6 */
|
||||
#define MUX_SCT0_INMUX_MASK (31 << MUX_SCT0_INMUX_SHIFT)
|
||||
# define MUX_SCT0_INMUX_SCTGPI0 (0 << MUX_SCT0_INMUX_SHIFT) /* function selected from IOCON register */
|
||||
# define MUX_SCT0_INMUX_SCTGPI1 (1 << MUX_SCT0_INMUX_SHIFT) /* function selected from IOCON register */
|
||||
# define MUX_SCT0_INMUX_SCTGPI2 (2 << MUX_SCT0_INMUX_SHIFT) /* function selected from IOCON register */
|
||||
# define MUX_SCT0_INMUX_SCTGPI3 (3 << MUX_SCT0_INMUX_SHIFT) /* function selected from IOCON register */
|
||||
# define MUX_SCT0_INMUX_SCTGPI4 (4 << MUX_SCT0_INMUX_SHIFT) /* function selected from IOCON register */
|
||||
# define MUX_SCT0_INMUX_SCTGPI5 (5 << MUX_SCT0_INMUX_SHIFT) /* function selected from IOCON register */
|
||||
# define MUX_SCT0_INMUX_SCTGPI6 (6 << MUX_SCT0_INMUX_SHIFT) /* function selected from IOCON register */
|
||||
# define MUX_SCT0_INMUX_SCTGPI7 (7 << MUX_SCT0_INMUX_SHIFT) /* function selected from IOCON register */
|
||||
# define MUX_SCT0_INMUX_T0OUT0 (8 << MUX_SCT0_INMUX_SHIFT) /* T0_OUT0 */
|
||||
# define MUX_SCT0_INMUX_T1OUT0 (9 << MUX_SCT0_INMUX_SHIFT) /* T1_OUT0 */
|
||||
# define MUX_SCT0_INMUX_T2OUT0 (10 << MUX_SCT0_INMUX_SHIFT) /* T2_OUT0 */
|
||||
# define MUX_SCT0_INMUX_T3OUT0 (11 << MUX_SCT0_INMUX_SHIFT) /* T3_OUT0 */
|
||||
# define MUX_SCT0_INMUX_T4OUT0 (12 << MUX_SCT0_INMUX_SHIFT) /* T4_OUT0 */
|
||||
# define MUX_SCT0_INMUX_ADCTHCMP (13 << MUX_SCT0_INMUX_SHIFT) /* ADC_THCMP_IRQ */
|
||||
# define MUX_SCT0_INMUX_BMATCH (14 << MUX_SCT0_INMUX_SHIFT) /* GPIOINT_BMATCH */
|
||||
# define MUX_SCT0_INMUX_USB0 (15 << MUX_SCT0_INMUX_SHIFT) /* USB0_FRAME_TOGGLE */
|
||||
# define MUX_SCT0_INMUX_USB1 (16 << MUX_SCT0_INMUX_SHIFT) /* USB1_FRAME_TOGGLE */
|
||||
# define MUX_SCT0_INMUX_ARMTXEV (17 << MUX_SCT0_INMUX_SHIFT) /* ARM_TXEV */
|
||||
# define MUX_SCT0_INMUX_HALTED (18 << MUX_SCT0_INMUX_SHIFT) /* DEBUG_HALTED */
|
||||
# define MUX_SCT0_INMUX_SC0TX (19 << MUX_SCT0_INMUX_SHIFT) /* SMARTCARD0_TX_ACTIVE */
|
||||
# define MUX_SCT0_INMUX_SC0RX (20 << MUX_SCT0_INMUX_SHIFT) /* SMARTCARD0_RX_ACTIVE */
|
||||
# define MUX_SCT0_INMUX_SC1TX (21 << MUX_SCT0_INMUX_SHIFT) /* SMARTCARD1_TX_ACTIVE */
|
||||
# define MUX_SCT0_INMUX_S10RX (22 << MUX_SCT0_INMUX_SHIFT) /* SMARTCARD1_RX_ACTIVE */
|
||||
# define MUX_SCT0_INMUX_I2S6SCLK (23 << MUX_SCT0_INMUX_SHIFT) /* I2S6_SCLK */
|
||||
# define MUX_SCT0_INMUX_I2S7SCLK (24 << MUX_SCT0_INMUX_SHIFT) /* I2S7_SCLK */
|
||||
#define MUX_SCT0_INMUX_SHIFT (0) /* Bits 0-4: Input number to SCT0 inputs 0 to 6 */
|
||||
#define MUX_SCT0_INMUX_MASK (31 << MUX_SCT0_INMUX_SHIFT)
|
||||
# define MUX_SCT0_INMUX_SCTGPI0 (0 << MUX_SCT0_INMUX_SHIFT) /* function selected from IOCON register */
|
||||
# define MUX_SCT0_INMUX_SCTGPI1 (1 << MUX_SCT0_INMUX_SHIFT) /* function selected from IOCON register */
|
||||
# define MUX_SCT0_INMUX_SCTGPI2 (2 << MUX_SCT0_INMUX_SHIFT) /* function selected from IOCON register */
|
||||
# define MUX_SCT0_INMUX_SCTGPI3 (3 << MUX_SCT0_INMUX_SHIFT) /* function selected from IOCON register */
|
||||
# define MUX_SCT0_INMUX_SCTGPI4 (4 << MUX_SCT0_INMUX_SHIFT) /* function selected from IOCON register */
|
||||
# define MUX_SCT0_INMUX_SCTGPI5 (5 << MUX_SCT0_INMUX_SHIFT) /* function selected from IOCON register */
|
||||
# define MUX_SCT0_INMUX_SCTGPI6 (6 << MUX_SCT0_INMUX_SHIFT) /* function selected from IOCON register */
|
||||
# define MUX_SCT0_INMUX_SCTGPI7 (7 << MUX_SCT0_INMUX_SHIFT) /* function selected from IOCON register */
|
||||
# define MUX_SCT0_INMUX_T0OUT0 (8 << MUX_SCT0_INMUX_SHIFT) /* T0_OUT0 */
|
||||
# define MUX_SCT0_INMUX_T1OUT0 (9 << MUX_SCT0_INMUX_SHIFT) /* T1_OUT0 */
|
||||
# define MUX_SCT0_INMUX_T2OUT0 (10 << MUX_SCT0_INMUX_SHIFT) /* T2_OUT0 */
|
||||
# define MUX_SCT0_INMUX_T3OUT0 (11 << MUX_SCT0_INMUX_SHIFT) /* T3_OUT0 */
|
||||
# define MUX_SCT0_INMUX_T4OUT0 (12 << MUX_SCT0_INMUX_SHIFT) /* T4_OUT0 */
|
||||
# define MUX_SCT0_INMUX_ADCTHCMP (13 << MUX_SCT0_INMUX_SHIFT) /* ADC_THCMP_IRQ */
|
||||
# define MUX_SCT0_INMUX_BMATCH (14 << MUX_SCT0_INMUX_SHIFT) /* GPIOINT_BMATCH */
|
||||
# define MUX_SCT0_INMUX_USB0 (15 << MUX_SCT0_INMUX_SHIFT) /* USB0_FRAME_TOGGLE */
|
||||
# define MUX_SCT0_INMUX_USB1 (16 << MUX_SCT0_INMUX_SHIFT) /* USB1_FRAME_TOGGLE */
|
||||
# define MUX_SCT0_INMUX_ARMTXEV (17 << MUX_SCT0_INMUX_SHIFT) /* ARM_TXEV */
|
||||
# define MUX_SCT0_INMUX_HALTED (18 << MUX_SCT0_INMUX_SHIFT) /* DEBUG_HALTED */
|
||||
# define MUX_SCT0_INMUX_SC0TX (19 << MUX_SCT0_INMUX_SHIFT) /* SMARTCARD0_TX_ACTIVE */
|
||||
# define MUX_SCT0_INMUX_SC0RX (20 << MUX_SCT0_INMUX_SHIFT) /* SMARTCARD0_RX_ACTIVE */
|
||||
# define MUX_SCT0_INMUX_SC1TX (21 << MUX_SCT0_INMUX_SHIFT) /* SMARTCARD1_TX_ACTIVE */
|
||||
# define MUX_SCT0_INMUX_S10RX (22 << MUX_SCT0_INMUX_SHIFT) /* SMARTCARD1_RX_ACTIVE */
|
||||
# define MUX_SCT0_INMUX_I2S6SCLK (23 << MUX_SCT0_INMUX_SHIFT) /* I2S6_SCLK */
|
||||
# define MUX_SCT0_INMUX_I2S7SCLK (24 << MUX_SCT0_INMUX_SHIFT) /* I2S7_SCLK */
|
||||
|
||||
/* Pin interrupt select register 0-7
|
||||
*
|
||||
|
|
@ -202,65 +210,65 @@
|
|||
* PIO0_0 to PIO1_31 correspond to numbers 0 to 63.
|
||||
*/
|
||||
|
||||
#define MUX_PINTSEL(n) (1 << (n))
|
||||
#define MUX_PINTSEL(n) (1 << (n))
|
||||
|
||||
/* Trigger select register for DMA channel 0-29 */
|
||||
|
||||
#define MUX_DMA_ITRIG_INMUX_SHIFT (0) /* Bit 0-4: Trigger input number for DMA channel n (n = 0 to 29) */
|
||||
#define MUX_DMA_ITRIG_INMUX_MASK (31 << MUX_DMA_ITRIG_INMUX_SHIFT)
|
||||
# define MUX_DMA_ITRIG_INMUX_ADC0A (0 << MUX_DMA_ITRIG_INMUX_SHIFT) /* ADC0 Sequence A interrupt */
|
||||
# define MUX_DMA_ITRIG_INMUX_ADC0B (1 << MUX_DMA_ITRIG_INMUX_SHIFT) /* ADC0 Sequence B interrupt */
|
||||
# define MUX_DMA_ITRIG_INMUX_SCT0DMA0 (2 << MUX_DMA_ITRIG_INMUX_SHIFT) /* SCT0 DMA request 0 */
|
||||
# define MUX_DMA_ITRIG_INMUX_SCT0DMA1 (3 << MUX_DMA_ITRIG_INMUX_SHIFT) /* SCT0 DMA request 1 */
|
||||
# define MUX_DMA_ITRIG_INMUX_PININT0 (4 << MUX_DMA_ITRIG_INMUX_SHIFT) /* Pin interrupt 0 */
|
||||
# define MUX_DMA_ITRIG_INMUX_PININT1 (5 << MUX_DMA_ITRIG_INMUX_SHIFT) /* Pin interrupt 1 */
|
||||
# define MUX_DMA_ITRIG_INMUX_PININT2 (6 << MUX_DMA_ITRIG_INMUX_SHIFT) /* Pin interrupt 2 */
|
||||
# define MUX_DMA_ITRIG_INMUX_PININT3 (7 << MUX_DMA_ITRIG_INMUX_SHIFT) /* Pin interrupt 3 */
|
||||
# define MUX_DMA_ITRIG_INMUX_CTIMER0MAT0 (8 << MUX_DMA_ITRIG_INMUX_SHIFT) /* Timer CTIMER0 Match 0 */
|
||||
# define MUX_DMA_ITRIG_INMUX_CTIMER0MAT1 (9 << MUX_DMA_ITRIG_INMUX_SHIFT) /* Timer CTIMER0 Match 1 */
|
||||
# define MUX_DMA_ITRIG_INMUX_CTIMER1MAT0 (10 << MUX_DMA_ITRIG_INMUX_SHIFT) /* Timer CTIMER1 Match 0 */
|
||||
# define MUX_DMA_ITRIG_INMUX_CTIMER1MAT1 (11 << MUX_DMA_ITRIG_INMUX_SHIFT) /* Timer CTIMER1 Match 1 */
|
||||
# define MUX_DMA_ITRIG_INMUX_CTIMER2MAT0 (12 << MUX_DMA_ITRIG_INMUX_SHIFT) /* Timer CTIMER2 Match 0 */
|
||||
# define MUX_DMA_ITRIG_INMUX_CTIMER2MAT1 (13 << MUX_DMA_ITRIG_INMUX_SHIFT) /* Timer CTIMER2 Match 1 */
|
||||
# define MUX_DMA_ITRIG_INMUX_CTIMER3MAT0 (14 << MUX_DMA_ITRIG_INMUX_SHIFT) /* Timer CTIMER3 Match 0 */
|
||||
# define MUX_DMA_ITRIG_INMUX_CTIMER3MAT1 (15 << MUX_DMA_ITRIG_INMUX_SHIFT) /* Timer CTIMER3 Match 1 */
|
||||
# define MUX_DMA_ITRIG_INMUX_CTIMER4MAT0 (16 << MUX_DMA_ITRIG_INMUX_SHIFT) /* Timer CTIMER4 Match 0 */
|
||||
# define MUX_DMA_ITRIG_INMUX_CTIMER4MAT1 (17 << MUX_DMA_ITRIG_INMUX_SHIFT) /* Timer CTIMER4 Match 1 */
|
||||
# define MUX_DMA_ITRIG_INMUX_DMAMUX0 (18 << MUX_DMA_ITRIG_INMUX_SHIFT) /* DMA output trigger mux 0 */
|
||||
# define MUX_DMA_ITRIG_INMUX_DMAMUX1 (19 << MUX_DMA_ITRIG_INMUX_SHIFT) /* DMA output trigger mux 1 */
|
||||
# define MUX_DMA_ITRIG_INMUX_DMAMUX2 (20 << MUX_DMA_ITRIG_INMUX_SHIFT) /* DMA output trigger mux 2 */
|
||||
# define MUX_DMA_ITRIG_INMUX_DMAMUX3 (21 << MUX_DMA_ITRIG_INMUX_SHIFT) /* DMA output trigger mux 3 */
|
||||
#define MUX_DMA_ITRIG_INMUX_SHIFT (0) /* Bit 0-4: Trigger input number for DMA channel n (n = 0 to 29) */
|
||||
#define MUX_DMA_ITRIG_INMUX_MASK (31 << MUX_DMA_ITRIG_INMUX_SHIFT)
|
||||
# define MUX_DMA_ITRIG_INMUX_ADC0A (0 << MUX_DMA_ITRIG_INMUX_SHIFT) /* ADC0 Sequence A interrupt */
|
||||
# define MUX_DMA_ITRIG_INMUX_ADC0B (1 << MUX_DMA_ITRIG_INMUX_SHIFT) /* ADC0 Sequence B interrupt */
|
||||
# define MUX_DMA_ITRIG_INMUX_SCT0DMA0 (2 << MUX_DMA_ITRIG_INMUX_SHIFT) /* SCT0 DMA request 0 */
|
||||
# define MUX_DMA_ITRIG_INMUX_SCT0DMA1 (3 << MUX_DMA_ITRIG_INMUX_SHIFT) /* SCT0 DMA request 1 */
|
||||
# define MUX_DMA_ITRIG_INMUX_PININT0 (4 << MUX_DMA_ITRIG_INMUX_SHIFT) /* Pin interrupt 0 */
|
||||
# define MUX_DMA_ITRIG_INMUX_PININT1 (5 << MUX_DMA_ITRIG_INMUX_SHIFT) /* Pin interrupt 1 */
|
||||
# define MUX_DMA_ITRIG_INMUX_PININT2 (6 << MUX_DMA_ITRIG_INMUX_SHIFT) /* Pin interrupt 2 */
|
||||
# define MUX_DMA_ITRIG_INMUX_PININT3 (7 << MUX_DMA_ITRIG_INMUX_SHIFT) /* Pin interrupt 3 */
|
||||
# define MUX_DMA_ITRIG_INMUX_CTIMER0MAT0 (8 << MUX_DMA_ITRIG_INMUX_SHIFT) /* Timer CTIMER0 Match 0 */
|
||||
# define MUX_DMA_ITRIG_INMUX_CTIMER0MAT1 (9 << MUX_DMA_ITRIG_INMUX_SHIFT) /* Timer CTIMER0 Match 1 */
|
||||
# define MUX_DMA_ITRIG_INMUX_CTIMER1MAT0 (10 << MUX_DMA_ITRIG_INMUX_SHIFT) /* Timer CTIMER1 Match 0 */
|
||||
# define MUX_DMA_ITRIG_INMUX_CTIMER1MAT1 (11 << MUX_DMA_ITRIG_INMUX_SHIFT) /* Timer CTIMER1 Match 1 */
|
||||
# define MUX_DMA_ITRIG_INMUX_CTIMER2MAT0 (12 << MUX_DMA_ITRIG_INMUX_SHIFT) /* Timer CTIMER2 Match 0 */
|
||||
# define MUX_DMA_ITRIG_INMUX_CTIMER2MAT1 (13 << MUX_DMA_ITRIG_INMUX_SHIFT) /* Timer CTIMER2 Match 1 */
|
||||
# define MUX_DMA_ITRIG_INMUX_CTIMER3MAT0 (14 << MUX_DMA_ITRIG_INMUX_SHIFT) /* Timer CTIMER3 Match 0 */
|
||||
# define MUX_DMA_ITRIG_INMUX_CTIMER3MAT1 (15 << MUX_DMA_ITRIG_INMUX_SHIFT) /* Timer CTIMER3 Match 1 */
|
||||
# define MUX_DMA_ITRIG_INMUX_CTIMER4MAT0 (16 << MUX_DMA_ITRIG_INMUX_SHIFT) /* Timer CTIMER4 Match 0 */
|
||||
# define MUX_DMA_ITRIG_INMUX_CTIMER4MAT1 (17 << MUX_DMA_ITRIG_INMUX_SHIFT) /* Timer CTIMER4 Match 1 */
|
||||
# define MUX_DMA_ITRIG_INMUX_DMAMUX0 (18 << MUX_DMA_ITRIG_INMUX_SHIFT) /* DMA output trigger mux 0 */
|
||||
# define MUX_DMA_ITRIG_INMUX_DMAMUX1 (19 << MUX_DMA_ITRIG_INMUX_SHIFT) /* DMA output trigger mux 1 */
|
||||
# define MUX_DMA_ITRIG_INMUX_DMAMUX2 (20 << MUX_DMA_ITRIG_INMUX_SHIFT) /* DMA output trigger mux 2 */
|
||||
# define MUX_DMA_ITRIG_INMUX_DMAMUX3 (21 << MUX_DMA_ITRIG_INMUX_SHIFT) /* DMA output trigger mux 3 */
|
||||
|
||||
/* DMA output trigger selection registers 0-3 */
|
||||
|
||||
#define MUX_DMA_OTRIG_INMUX_SHIFT (0) /* Bits 0-4: DMA trigger output number for DMA channel n=0..29 */
|
||||
#define MUX_DMA_OTRIG_INMUX_MASK (31 << MUX_DMA_OTRIG_INMUX_SHIFT)
|
||||
# define MUX_DMA_OTRIG_INMUX(n) ((uint32_t)(n) << MUX_DMA_OTRIG_INMUX_SHIFT)
|
||||
#define MUX_DMA_OTRIG_INMUX_SHIFT (0) /* Bits 0-4: DMA trigger output number for DMA channel n=0..29 */
|
||||
#define MUX_DMA_OTRIG_INMUX_MASK (31 << MUX_DMA_OTRIG_INMUX_SHIFT)
|
||||
# define MUX_DMA_OTRIG_INMUX(n) ((uint32_t)(n) << MUX_DMA_OTRIG_INMUX_SHIFT)
|
||||
|
||||
/* Selection for frequency measurement reference clock */
|
||||
|
||||
#define MUX_FREQMEAS_REF_SHIFT (0) /* Bits 0-4: Clock source for frequency measure farget clock */
|
||||
#define MUX_FREQMEAS_REF_MASK (31 << MUX_FREQMEAS_REF_SHIFT)
|
||||
# define MUX_FREQMEAS_REF_CLKIN (0 << MUX_FREQMEAS_REF_SHIFT) /* External crystal oscillator (clk_in) */
|
||||
# define MUX_FREQMEAS_REF_FRO12M (1 << MUX_FREQMEAS_REF_SHIFT) /* FRO 12 MHz oscillator (fro_12m) */
|
||||
# define MUX_FREQMEAS_REF_FROHF (2 << MUX_FREQMEAS_REF_SHIFT) /* FRO 96 or 48 MHz (fro_hf) */
|
||||
# define MUX_FREQMEAS_REF_WDTCLK (3 << MUX_FREQMEAS_REF_SHIFT) /* Watchdog oscillator (wdt_clk) */
|
||||
# define MUX_FREQMEAS_REF_32KCLK (4 << MUX_FREQMEAS_REF_SHIFT) /* 32 kHz RTC oscillator (32k_clk) */
|
||||
# define MUX_FREQMEAS_REF_MAINCLK (5 << MUX_FREQMEAS_REF_SHIFT) /* Main clock (main_clk) */
|
||||
# define MUX_FREQMEAS_REF_GPIOCLKA (6 << MUX_FREQMEAS_REF_SHIFT) /* FREQME_GPIO_CLK_A */
|
||||
# define MUX_FREQMEAS_REF_GPIOCLKB (7 << MUX_FREQMEAS_REF_SHIFT) /* FREQME_GPIO_CLK_B */
|
||||
#define MUX_FREQMEAS_REF_SHIFT (0) /* Bits 0-4: Clock source for frequency measure farget clock */
|
||||
#define MUX_FREQMEAS_REF_MASK (31 << MUX_FREQMEAS_REF_SHIFT)
|
||||
# define MUX_FREQMEAS_REF_CLKIN (0 << MUX_FREQMEAS_REF_SHIFT) /* External crystal oscillator (clk_in) */
|
||||
# define MUX_FREQMEAS_REF_FRO12M (1 << MUX_FREQMEAS_REF_SHIFT) /* FRO 12 MHz oscillator (fro_12m) */
|
||||
# define MUX_FREQMEAS_REF_FROHF (2 << MUX_FREQMEAS_REF_SHIFT) /* FRO 96 or 48 MHz (fro_hf) */
|
||||
# define MUX_FREQMEAS_REF_WDTCLK (3 << MUX_FREQMEAS_REF_SHIFT) /* Watchdog oscillator (wdt_clk) */
|
||||
# define MUX_FREQMEAS_REF_32KCLK (4 << MUX_FREQMEAS_REF_SHIFT) /* 32 kHz RTC oscillator (32k_clk) */
|
||||
# define MUX_FREQMEAS_REF_MAINCLK (5 << MUX_FREQMEAS_REF_SHIFT) /* Main clock (main_clk) */
|
||||
# define MUX_FREQMEAS_REF_GPIOCLKA (6 << MUX_FREQMEAS_REF_SHIFT) /* FREQME_GPIO_CLK_A */
|
||||
# define MUX_FREQMEAS_REF_GPIOCLKB (7 << MUX_FREQMEAS_REF_SHIFT) /* FREQME_GPIO_CLK_B */
|
||||
|
||||
/* Selection for frequency measurement target clock */
|
||||
|
||||
#define MUX_FREQMEAS_TARGET_SHIFT (0) /* Bits 0-4: Selects target clock of the frequency measure function */
|
||||
#define MUX_FREQMEAS_TARGET_MASK (31 << MUX_FREQMEAS_TARGET_SHIFT)
|
||||
# define MUX_FREQMEAS_TARGET_CLKIN (0 << MUX_FREQMEAS_TARGET_SHIFT) /* External crystal oscillator (clk_in) */
|
||||
# define MUX_FREQMEAS_TARGET_FRO12M (1 << MUX_FREQMEAS_TARGET_SHIFT) /* FRO 12 MHz oscillator (fro_12m) */
|
||||
# define MUX_FREQMEAS_TARGET_FROHF (2 << MUX_FREQMEAS_TARGET_SHIFT) /* FRO 96 or 48 MHz (fro_hf) */
|
||||
# define MUX_FREQMEAS_TARGET_WDTCLK (3 << MUX_FREQMEAS_TARGET_SHIFT) /* Watchdog oscillator (wdt_clk) */
|
||||
# define MUX_FREQMEAS_TARGET_32KCLK (4 << MUX_FREQMEAS_TARGET_SHIFT) /* 32 kHz RTC oscillator (32k_clk) */
|
||||
# define MUX_FREQMEAS_TARGET_MAINCLK (5 << MUX_FREQMEAS_TARGET_SHIFT) /* Main clock (main_clk) */
|
||||
# define MUX_FREQMEAS_TARGET_GPIOCLKA (6 << MUX_FREQMEAS_TARGET_SHIFT) /* FREQME_GPIO_CLK_A */
|
||||
# define MUX_FREQMEAS_TARGET_ PIOCLKB (7 << MUX_FREQMEAS_TARGET_SHIFT) /* FREQME_GPIO_CLK_B */
|
||||
#define MUX_FREQMEAS_TARGET_SHIFT (0) /* Bits 0-4: Selects target clock of the frequency measure function */
|
||||
#define MUX_FREQMEAS_TARGET_MASK (31 << MUX_FREQMEAS_TARGET_SHIFT)
|
||||
# define MUX_FREQMEAS_TARGET_CLKIN (0 << MUX_FREQMEAS_TARGET_SHIFT) /* External crystal oscillator (clk_in) */
|
||||
# define MUX_FREQMEAS_TARGET_FRO12M (1 << MUX_FREQMEAS_TARGET_SHIFT) /* FRO 12 MHz oscillator (fro_12m) */
|
||||
# define MUX_FREQMEAS_TARGET_FROHF (2 << MUX_FREQMEAS_TARGET_SHIFT) /* FRO 96 or 48 MHz (fro_hf) */
|
||||
# define MUX_FREQMEAS_TARGET_WDTCLK (3 << MUX_FREQMEAS_TARGET_SHIFT) /* Watchdog oscillator (wdt_clk) */
|
||||
# define MUX_FREQMEAS_TARGET_32KCLK (4 << MUX_FREQMEAS_TARGET_SHIFT) /* 32 kHz RTC oscillator (32k_clk) */
|
||||
# define MUX_FREQMEAS_TARGET_MAINCLK (5 << MUX_FREQMEAS_TARGET_SHIFT) /* Main clock (main_clk) */
|
||||
# define MUX_FREQMEAS_TARGET_GPIOCLKA (6 << MUX_FREQMEAS_TARGET_SHIFT) /* FREQME_GPIO_CLK_A */
|
||||
# define MUX_FREQMEAS_TARGET_ PIOCLKB (7 << MUX_FREQMEAS_TARGET_SHIFT) /* FREQME_GPIO_CLK_B */
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_LPC54XX_CHIP_LPC54_INPUTMUX_H */
|
||||
|
|
|
|||
|
|
@ -113,7 +113,6 @@
|
|||
|
||||
/* Pattern match interrupt bit-slice source */
|
||||
|
||||
|
||||
/* PINTSELn=1 indicates that PINSETn is the source to bit slice m. */
|
||||
|
||||
#define PINT_PMSRC_PINTSEL0 0
|
||||
|
|
|
|||
|
|
@ -59,7 +59,6 @@
|
|||
/* Default input pin configuration */
|
||||
|
||||
#define PORTPIN_MASK (GPIO_PORT_MASK|GPIO_PIN_MASK)
|
||||
#define DEFAULT_INPUT (GPIO_INPUT|GPIO_PULLUP|GPIO_MODE_DIGITAL)
|
||||
|
||||
/* Pin types */
|
||||
|
||||
|
|
@ -173,8 +172,7 @@ static void lpc54_setpinfunction(unsigned int port, unsigned int pin,
|
|||
*
|
||||
****************************************************************************/
|
||||
|
||||
static inline void lpc54_gpio_input(lpc54_pinset_t cfgset,
|
||||
unsigned int port, unsigned int pin)
|
||||
static inline void lpc54_gpio_input(unsigned int port, unsigned int pin)
|
||||
{
|
||||
uintptr_t regaddr;
|
||||
uint32_t regval;
|
||||
|
|
@ -349,7 +347,6 @@ static void lpc54_gpio_iocon(lpc54_pinset_t cfgset, unsigned int port,
|
|||
|
||||
int lpc54_gpio_config(lpc54_pinset_t cfgset)
|
||||
{
|
||||
lpc54_pinset_t definput;
|
||||
unsigned int port;
|
||||
unsigned int pin;
|
||||
|
||||
|
|
@ -369,8 +366,7 @@ int lpc54_gpio_config(lpc54_pinset_t cfgset)
|
|||
* configuration.
|
||||
*/
|
||||
|
||||
definput = (cfgset & PORTPIN_MASK) | DEFAULT_INPUT;
|
||||
lpc54_gpio_input(definput, port, pin);
|
||||
lpc54_gpio_input(port, pin);
|
||||
|
||||
/* Set the IOCON bits */
|
||||
|
||||
|
|
@ -387,7 +383,9 @@ int lpc54_gpio_config(lpc54_pinset_t cfgset)
|
|||
case GPIO_INTFE: /* GPIO interrupt falling edge */
|
||||
case GPIO_INTRE: /* GPIO interrupt rising edge */
|
||||
case GPIO_INTBOTH: /* GPIO interrupt both edges */
|
||||
lpc54_gpio_interrupt(cfgset, port, pin);
|
||||
case GPIO_INTLOW: /* GPIO interrupt low level */
|
||||
case GPIO_INTHIGH: /* GPIO interrupt high level */
|
||||
lpc54_gpio_interrupt(cfgset);
|
||||
break;
|
||||
#endif
|
||||
|
||||
|
|
|
|||
|
|
@ -57,10 +57,10 @@
|
|||
************************************************************************************/
|
||||
/* Bit-encoded input to lpc54_gpio_config() ******************************************/
|
||||
|
||||
/* 32-Bit Encoding: .... .... TTTT TTTT FFFF MM.V PPPN NNNN
|
||||
/* 32-Bit Encoding: .... .... TTTT TTTT FFFF FMMV PPPN NNNN
|
||||
*
|
||||
* Special Pin Functions: TTTT TTTT
|
||||
* Pin Function: FFFF
|
||||
* Pin Function: FFFF F
|
||||
* Pin Mode bits: MM
|
||||
* Initial value: V (output pins)
|
||||
* Port number: PPP (0-5)
|
||||
|
|
@ -115,47 +115,54 @@
|
|||
/* Pin Function bits:
|
||||
* Only meaningful when the GPIO function is GPIO_PIN
|
||||
*
|
||||
* .... .... .... .... FFFF .... .... ....
|
||||
* .... .... .... .... FFFF F... .... ....
|
||||
*/
|
||||
|
||||
#define GPIO_FUNC_SHIFT (12) /* Bits 12-15: GPIO mode */
|
||||
#define GPIO_FUNC_MASK (15 << GPIO_FUNC_SHIFT)
|
||||
# define GPIO_INPUT (0 << GPIO_FUNC_SHIFT) /* 0000 GPIO input pin */
|
||||
# define GPIO_INTFE (1 << GPIO_FUNC_SHIFT) /* 0001 GPIO interrupt falling edge */
|
||||
# define GPIO_INTRE (2 << GPIO_FUNC_SHIFT) /* 0010 GPIO interrupt rising edge */
|
||||
# define GPIO_INTBOTH (3 << GPIO_FUNC_SHIFT) /* 0011 GPIO interrupt both edges */
|
||||
# define GPIO_OUTPUT (4 << GPIO_FUNC_SHIFT) /* 0100 GPIO outpout pin */
|
||||
# define GPIO_ALT1 (5 << GPIO_FUNC_SHIFT) /* 0101 Alternate function 1 */
|
||||
# define GPIO_ALT2 (6 << GPIO_FUNC_SHIFT) /* 0110 Alternate function 2 */
|
||||
# define GPIO_ALT3 (7 << GPIO_FUNC_SHIFT) /* 0111 Alternate function 3 */
|
||||
# define GPIO_ALT4 (8 << GPIO_FUNC_SHIFT) /* 1000 Alternate function 4 */
|
||||
# define GPIO_ALT5 (9 << GPIO_FUNC_SHIFT) /* 1001 Alternate function 5 */
|
||||
# define GPIO_ALT6 (10 << GPIO_FUNC_SHIFT) /* 1010 Alternate function 6 */
|
||||
# define GPIO_ALT7 (11 << GPIO_FUNC_SHIFT) /* 1011 Alternate function 7 */
|
||||
#define GPIO_FUNC_SHIFT (11) /* Bits 11-15: GPIO mode */
|
||||
#define GPIO_FUNC_MASK (0x1f << GPIO_FUNC_SHIFT)
|
||||
# define GPIO_INPUT (0x00 << GPIO_FUNC_SHIFT) /* 00000 GPIO input pin */
|
||||
# define GPIO_OUTPUT (0x01 << GPIO_FUNC_SHIFT) /* 00001 GPIO output pin */
|
||||
|
||||
#define GPIO_EDGE_SHIFT (12) /* Bits 12-13: Interrupt edge bits */
|
||||
#define GPIO_EDGE_MASK (3 << GPIO_EDGE_SHIFT)
|
||||
# define GPIO_INTFE (0x09 << GPIO_FUNC_SHIFT) /* 01001 GPIO interrupt falling edge */
|
||||
# define GPIO_INTRE (0x0a << GPIO_FUNC_SHIFT) /* 01010 GPIO interrupt rising edge */
|
||||
# define GPIO_INTBOTH (0x0b << GPIO_FUNC_SHIFT) /* 01011 GPIO interrupt both edges */
|
||||
# define GPIO_INTLOW (0x0d << GPIO_FUNC_SHIFT) /* 01101 GPIO interrupt low level */
|
||||
# define GPIO_INTHIGH (0x0e << GPIO_FUNC_SHIFT) /* 01110 GPIO interrupt high level */
|
||||
|
||||
#define GPIO_INOUT_MASK GPIO_OUTPUT
|
||||
#define GPIO_FE_MASK GPIO_INTFE
|
||||
#define GPIO_RE_MASK GPIO_INTRE
|
||||
# define GPIO_ALT1 (0x11 << GPIO_FUNC_SHIFT) /* 10001 Alternate function 1 */
|
||||
# define GPIO_ALT2 (0x12 << GPIO_FUNC_SHIFT) /* 10010 Alternate function 2 */
|
||||
# define GPIO_ALT3 (0x13 << GPIO_FUNC_SHIFT) /* 10011 Alternate function 3 */
|
||||
# define GPIO_ALT4 (0x14 << GPIO_FUNC_SHIFT) /* 10100 Alternate function 4 */
|
||||
# define GPIO_ALT5 (0x15 << GPIO_FUNC_SHIFT) /* 10101 Alternate function 5 */
|
||||
# define GPIO_ALT6 (0x16 << GPIO_FUNC_SHIFT) /* 10110 Alternate function 6 */
|
||||
# define GPIO_ALT7 (0x17 << GPIO_FUNC_SHIFT) /* 10111 Alternate function 7 */
|
||||
|
||||
#define GPIO_ISGPIO(ps) ((uint16_t(ps) & GPIO_FUNC_MASK) <= GPIO_OUTPUT)
|
||||
#define GPIO_ISALT(ps) ((uint16_t(ps) & GPIO_FUNC_MASK) > GPIO_OUTPUT)
|
||||
#define GPIO_ISINPUT(ps) (((ps) & GPIO_FUNC_MASK) == GPIO_INPUT)
|
||||
#define GPIO_ISOUTPUT(ps) (((ps) & GPIO_FUNC_MASK) == GPIO_OUTPUT)
|
||||
#define GPIO_ISINORINT(ps) (((ps) & GPIO_INOUT_MASK) == 0)
|
||||
#define GPIO_ISOUTORALT(ps) (((ps) & GPIO_INOUT_MASK) != 0)
|
||||
#define GPIO_ISINTERRUPT(ps) (GPIO_ISOUTPUT(ps) && !GPIO_ISINPUT(ps))
|
||||
#define GPIO_ISFE(ps) (((ps) & GPIO_FE_MASK) != 0)
|
||||
#define GPIO_ISRE(ps) (((ps) & GPIO_RE_MASK) != 0)
|
||||
#define GPIO_GPIO_MASK (0x1e << GPIO_FUNC_SHIFT) /* 1111x */
|
||||
#define GPIO_GPIO_CODE (0x00 << GPIO_FUNC_SHIFT) /* 0000x */
|
||||
#define GPIO_IS_GPIO(ps) (((uint32_t)(ps) & GPIO_GPIO_MASK) == GPIO_GPIO_CODE)
|
||||
#define GPIO_IS_GPIOINPUT(ps) ((uint32_t)(ps) == GPIO_INPUT)
|
||||
#define GPIO_IS_GPIOOUTPUT(ps) ((uint32_t)(ps) == GPIO_OUTPUT)
|
||||
|
||||
#define GPIO_INTR_MASK (0x18 << GPIO_FUNC_SHIFT) /* 11xxx */
|
||||
#define GPIO_INTR_CODE (0x08 << GPIO_FUNC_SHIFT) /* 01xxx */
|
||||
#define GPIO_IS_INTR(ps) (((uint32_t)(ps) & GPIO_INTR_MASK) == GPIO_INTR_CODE)
|
||||
|
||||
#define GPIO_TRIG_MASK (0x18 << GPIO_FUNC_SHIFT) /* 111xx */
|
||||
#define GPIO_TRIG_LEVEL_CODE (0x08 << GPIO_FUNC_SHIFT) /* 010xx */
|
||||
#define GPIO_TRIG_EDGE_CODE (0x0c << GPIO_FUNC_SHIFT) /* 011xx */
|
||||
#define GPIO_IS_INTLEVEL(ps) (((uint32_t)(ps) & GPIO_TRIG_MASK) == GPIO_TRIG_LEVEL_CODE)
|
||||
#define GPIO_IS_INTEDGE(ps) (((uint32_t)(ps) & GPIO_TRIG_MASK) == GPIO_TRIG_EDGE_CODE)
|
||||
|
||||
#define GPIO_ALT_MASK (0x18 << GPIO_FUNC_SHIFT) /* 11xxx */
|
||||
#define GPIO_ALT_CODE (0x10 << GPIO_FUNC_SHIFT) /* 10xxx */
|
||||
#define GPIO_IS_ALT(ps) (((uint32_t)(ps) & GPIO_ALT_MASK) == GPIO_ALT_CODE)
|
||||
|
||||
/* Pin Mode: MM
|
||||
*
|
||||
* .... .... .... .... .... MM.. .... ....
|
||||
* .... .... .... .... .... .MM. .... ....
|
||||
*/
|
||||
|
||||
#define GPIO_MODE_SHIFT (10) /* Bits 10-11: Pin pull-up mode */
|
||||
#define GPIO_MODE_SHIFT (9) /* Bits 9-10: Pin pull-up mode */
|
||||
#define GPIO_MODE_MASK (3 << GPIO_MODE_SHIFT)
|
||||
# define GPIO_FLOAT (IOCON_MODE_FLOAT << GPIO_MODE_SHIFT) /* Neither pull-up nor -down */
|
||||
# define GPIO_PULLDOWN (IOCON_MODE_PULLDOWN << GPIO_MODE_SHIFT) /* Pull-down resistor enabled */
|
||||
|
|
@ -163,13 +170,18 @@
|
|||
# define GPIO_REPEATER (IOCON_MODE_REPEATER << GPIO_MODE_SHIFT) /* Repeater mode enabled */
|
||||
|
||||
/* Initial value: V
|
||||
*
|
||||
* .... .... .... .... .... ...V .... ....
|
||||
*/
|
||||
|
||||
#define GPIO_VALUE (1 << 8) /* Bit 8: Initial GPIO output value */
|
||||
# define GPIO_VALUE_ONE GPIO_VALUE
|
||||
# define GPIO_VALUE_ZERO (0)
|
||||
|
||||
/* Port number: PPP (0-5) */
|
||||
/* Port number: PPP (0-5)
|
||||
*
|
||||
* .... .... .... .... .... .... PPP. ....
|
||||
*/
|
||||
|
||||
#define GPIO_PORT_SHIFT (5) /* Bit 5-7: Port number */
|
||||
#define GPIO_PORT_MASK (7 << GPIO_PORT_SHIFT)
|
||||
|
|
@ -180,7 +192,10 @@
|
|||
# define GPIO_PORT4 (4 << GPIO_PORT_SHIFT)
|
||||
# define GPIO_PORT5 (5 << GPIO_PORT_SHIFT)
|
||||
|
||||
/* Pin number: NNNNN (0-31) */
|
||||
/* Pin number: NNNNN (0-31)
|
||||
*
|
||||
* .... .... .... .... .... .... ...N NNNN
|
||||
*/
|
||||
|
||||
#define GPIO_PIN_SHIFT 0 /* Bits 0-4: GPIO number: 0-31 */
|
||||
#define GPIO_PIN_MASK (31 << GPIO_PIN_SHIFT)
|
||||
|
|
@ -277,7 +292,20 @@ int lpc54_gpio_config(lpc54_pinset_t cfgset);
|
|||
************************************************************************************/
|
||||
|
||||
#ifdef CONFIG_LPC54_GPIOIRQ
|
||||
void lpc54_gpio_interrupt(lpc54_pinset_t pinset);
|
||||
int lpc54_gpio_interrupt(lpc54_pinset_t pinset);
|
||||
#endif
|
||||
|
||||
/************************************************************************************
|
||||
* Name: lpc54_gpio_irqno
|
||||
*
|
||||
* Description:
|
||||
* Returns the IRQ number that was associated with an interrupt pin after it was
|
||||
* configured.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifdef CONFIG_LPC54_GPIOIRQ
|
||||
int lpc54_gpio_irqno(lpc54_pinset_t pinset);
|
||||
#endif
|
||||
|
||||
/************************************************************************************
|
||||
|
|
|
|||
|
|
@ -39,13 +39,91 @@
|
|||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include <errno.h>
|
||||
|
||||
#include <nuttx/arch.h>
|
||||
#include <nuttx/irq.h>
|
||||
|
||||
#include "up_arch.h"
|
||||
|
||||
#include "chip/lpc54_syscon.h"
|
||||
#include "chip/lpc54_inputmux.h"
|
||||
#include "chip/lpc54_pint.h"
|
||||
#include "lpc54_gpio.h"
|
||||
|
||||
#ifdef CONFIG_LPC54_GPIOIRQ
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/* The maximum number of pin interrupts */
|
||||
|
||||
#define MAX_PININT 8
|
||||
|
||||
/* A mask for both the port and pin number */
|
||||
|
||||
#define GPIO_PORTPIN_MASK (GPIO_PORT_MASK | GPIO_PIN_MASK)
|
||||
|
||||
/****************************************************************************
|
||||
* Private Data
|
||||
****************************************************************************/
|
||||
|
||||
/* This is the set of all pin interrupts that have been allocated. Any pin
|
||||
* in P0 or P1 may be configured as an interrupts source via the input
|
||||
* multiplexor. Up to eight pin interrupts are supported.
|
||||
*/
|
||||
|
||||
static uint8_t g_pinints;
|
||||
|
||||
/* Maps a pin interrupt number to an IRQ number (they are not contiguous) */
|
||||
|
||||
static const uint8_t g_pinirq[MAX_PININT] =
|
||||
{
|
||||
LPC54_IRQ_PININT0, LPC54_IRQ_PININT1, LPC54_IRQ_PININT2, LPC54_IRQ_PININT3,
|
||||
LPC54_IRQ_PININT4, LPC54_IRQ_PININT5, LPC54_IRQ_PININT6, LPC54_IRQ_PININT7
|
||||
};
|
||||
|
||||
/****************************************************************************
|
||||
* Private Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: lpc54_alloc_pinint
|
||||
*
|
||||
* Description:
|
||||
* Initialize logic to support interrupting GPIO pins. This function is
|
||||
* called by the OS inialization logic and is not a user interface.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static int lpc54_alloc_pinint(lpc54_pinset_t pinset)
|
||||
{
|
||||
irqstate_t flags = enter_critical_section();
|
||||
int pin;
|
||||
|
||||
/* REVISIT: This is overlying complex in the current design. There is
|
||||
* not yet any mechanism to de-configure a pin. At present, a simple
|
||||
* counter would be sufficient to assign a pin. This bit-mapped allocator
|
||||
* is used in the anticipation that such pin-deconfiguration will be
|
||||
* supported in the future.
|
||||
*/
|
||||
|
||||
for (pin = 0; pin < MAX_PININT; pin++)
|
||||
{
|
||||
uint8_t mask = (1 << pin);
|
||||
if ((g_pinints & mask) == 0)
|
||||
{
|
||||
g_pinints |= mask;
|
||||
leave_critical_section(flags);
|
||||
return pin;
|
||||
}
|
||||
}
|
||||
|
||||
leave_critical_section(flags);
|
||||
return -ENOSPC;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
|
@ -61,6 +139,14 @@
|
|||
|
||||
void lpc54_gpio_irqinitialize(void)
|
||||
{
|
||||
/* NOTE: "Once set up, no clocks are needed for the input multiplexer to
|
||||
* function. The system clock is needed only to write to or read from the
|
||||
* INPUT MUX registers. Once the input multiplexer is configured, disable
|
||||
* the clock to the INPUT MUX block in the AHBCLKCTRL register."
|
||||
*
|
||||
* REVISIT: Future power optimization.
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_LPC54_GPIOIRQ_GROUPS
|
||||
/* Enable the Input Mux, PINT, and GINT modules */
|
||||
|
||||
|
|
@ -72,8 +158,6 @@ void lpc54_gpio_irqinitialize(void)
|
|||
putreg32(SYSCON_AHBCLKCTRL0_INPUTMUX | SYSCON_AHBCLKCTRL0_PINT,
|
||||
LPC54_SYSCON_AHBCLKCTRLSET0);
|
||||
#endif
|
||||
|
||||
#warning Missing logic
|
||||
}
|
||||
|
||||
/************************************************************************************
|
||||
|
|
@ -86,10 +170,151 @@ void lpc54_gpio_irqinitialize(void)
|
|||
*
|
||||
************************************************************************************/
|
||||
|
||||
void lpc54_gpio_interrupt(lpc54_pinset_t pinset)
|
||||
int lpc54_gpio_interrupt(lpc54_pinset_t pinset)
|
||||
{
|
||||
#warning Missing logic
|
||||
uintptr_t regaddr;
|
||||
uint32_t mask;
|
||||
unsigned int port;
|
||||
int pinint;
|
||||
|
||||
/* Is this pin configured as an interrupting pin */
|
||||
|
||||
if (!GPIO_IS_INTR(pinset))
|
||||
{
|
||||
return -EPERM;
|
||||
}
|
||||
|
||||
/* Pin interrupts are supported only on P0 and P1 */
|
||||
|
||||
port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
|
||||
if (port > 1)
|
||||
{
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
/* Assign a pin interrupt */
|
||||
|
||||
pinint = lpc54_alloc_pinint(pinset);
|
||||
if (pinint < 0)
|
||||
{
|
||||
return pinint;
|
||||
}
|
||||
|
||||
/* Make sure that the pin interrupt is disabled at the NVIC. */
|
||||
|
||||
up_disable_irq(g_pinirq[pinint]);
|
||||
|
||||
/* Select the pin interrupt input:
|
||||
*
|
||||
* For PIOm.n: pin = (m * 32) + n.
|
||||
* PIO0.0 to PIO1.31 correspond to numbers 0 to 63.
|
||||
*/
|
||||
|
||||
regaddr = LPC54_MUX_PINTSEL(pinint);
|
||||
putreg32((uint32_t)pinset & GPIO_PORTPIN_MASK, regaddr);
|
||||
|
||||
/* Enable the pin interrupt triggers */
|
||||
|
||||
mask = (1 << pinint);
|
||||
if (GPIO_IS_INTLEVEL(pinset))
|
||||
{
|
||||
/* Set the pinint bit to select level sensitive trigger */
|
||||
|
||||
modifyreg32(LPC54_PINT_ISEL, 0, mask);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Clear the pinint bit to select edge sensitive trigger */
|
||||
|
||||
modifyreg32(LPC54_PINT_ISEL, mask, 0);
|
||||
}
|
||||
|
||||
switch (pinset & GPIO_FUNC_MASK)
|
||||
{
|
||||
/* Write to SIENR to enable rising-edge or level interrupts */
|
||||
|
||||
case GPIO_INTRE: /* GPIO interrupt rising edge */
|
||||
case GPIO_INTBOTH: /* GPIO interrupt both edges */
|
||||
case GPIO_INTLOW: /* GPIO interrupt low level */
|
||||
case GPIO_INTHIGH: /* GPIO interrupt high level */
|
||||
putreg32(mask, LPC54_PINT_SIENR);
|
||||
break;
|
||||
|
||||
/* Write to CIENR to disable rising-edge or level interrupts */
|
||||
|
||||
case GPIO_INTFE: /* GPIO interrupt falling edge */
|
||||
putreg32(mask, LPC54_PINT_SIENR);
|
||||
break;
|
||||
|
||||
default:
|
||||
DEBUGPANIC();
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
switch (pinset & GPIO_FUNC_MASK)
|
||||
{
|
||||
/* Write to SIENF to enable falling-edge or active-high level
|
||||
* interrupts.
|
||||
*/
|
||||
|
||||
case GPIO_INTFE: /* GPIO interrupt falling edge */
|
||||
case GPIO_INTBOTH: /* GPIO interrupt both edges */
|
||||
case GPIO_INTHIGH: /* GPIO interrupt high level */
|
||||
putreg32(mask, LPC54_PINT_SIENR);
|
||||
break;
|
||||
|
||||
/* Write to CIENF to disable falling-edge or enable active-low level
|
||||
* interrupts.
|
||||
*/
|
||||
|
||||
case GPIO_INTRE: /* GPIO interrupt rising edge */
|
||||
case GPIO_INTLOW: /* GPIO interrupt low level */
|
||||
putreg32(mask, LPC54_PINT_SIENR);
|
||||
break;
|
||||
|
||||
default:
|
||||
DEBUGPANIC();
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
return OK;
|
||||
}
|
||||
|
||||
/************************************************************************************
|
||||
* Name: lpc54_gpio_irqno
|
||||
*
|
||||
* Description:
|
||||
* Returns the IRQ number that was associated with an interrupt pin after it was
|
||||
* configured.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
int lpc54_gpio_irqno(lpc54_pinset_t pinset)
|
||||
{
|
||||
irqstate_t flags;
|
||||
uintptr_t regaddr;
|
||||
uint32_t regval;
|
||||
int portpin = pinset & GPIO_PORTPIN_MASK;
|
||||
int i;
|
||||
|
||||
flags = enter_critical_section();
|
||||
|
||||
/* Find the PININT index that as the assignment to the this port and pin */
|
||||
|
||||
for (i = 0, regaddr = LPC54_MUX_PINTSEL0;
|
||||
i < MAX_PININT;
|
||||
i++, regaddr += 4)
|
||||
{
|
||||
regval = getreg32(regaddr) & GPIO_PORTPIN_MASK;
|
||||
if (regval == portpin)
|
||||
{
|
||||
leave_critical_section(flags);
|
||||
return (int)g_pinirq[i];
|
||||
}
|
||||
}
|
||||
|
||||
leave_critical_section(flags);
|
||||
return -ENOENT;
|
||||
}
|
||||
|
||||
#endif /* CONFIG_LPC54_GPIOIRQ */
|
||||
|
|
|
|||
|
|
@ -52,6 +52,7 @@
|
|||
#include "up_arch.h"
|
||||
#include "up_internal.h"
|
||||
|
||||
#include "lpc54_gpio.h"
|
||||
#include "lpc54_irq.h"
|
||||
|
||||
/****************************************************************************
|
||||
|
|
|
|||
|
|
@ -333,6 +333,8 @@ config ARCH_BOARD_LPCXPRESSO_LPC54628
|
|||
bool "NXP LPCXpresso LPC54628"
|
||||
depends on ARCH_CHIP_LPC54628
|
||||
select ARCH_HAVE_LEDS
|
||||
select ARCH_HAVE_BUTTONS
|
||||
select ARCH_HAVE_IRQBUTTONS
|
||||
---help---
|
||||
LPCXpresso LPC54626 board featuring the NXP LPC54628 MCU.
|
||||
|
||||
|
|
|
|||
|
|
@ -49,6 +49,10 @@ STATUS
|
|||
2017-12-15: Added an I2C driver. This is the first step on the road
|
||||
to getting support for the capacitive touchscreen on the TFT panel.
|
||||
The I2C driver appears to be functional but is not yet well-tested.
|
||||
2017-12-16: Added support for LPC54xx GPIO interrupts; added button
|
||||
support (with interrupts) to the NSH configuration. The button
|
||||
test is partially functional but appears to miss a lot of button-
|
||||
related events. More testing is needed.
|
||||
|
||||
Configurations
|
||||
==============
|
||||
|
|
@ -183,9 +187,9 @@ Configurations
|
|||
RAMTest: Address-in-address test: a0000000 16777216
|
||||
nsh>
|
||||
|
||||
3. I2C2 is enabled (will be used with the capacitive touchscreen). In
|
||||
order to verify I2C functionality, the I2C tool at apps/system/i2ctool
|
||||
is enabled in this configuration.
|
||||
3. I2C2 is enabled (will be used with the capacitive touchscreen). In
|
||||
order to verify I2C functionality, the I2C tool at apps/system/i2ctool
|
||||
is enabled in this configuration.
|
||||
|
||||
nsh> i2c bus
|
||||
BUS EXISTS?
|
||||
|
|
@ -210,10 +214,15 @@ Configurations
|
|||
60: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
|
||||
70: -- -- -- -- -- -- -- --
|
||||
|
||||
I believe that the on-board Accelerometer, Audio Codec, and touch
|
||||
panel controller should have been detected (but perhaps the touch
|
||||
panel is not powered in this configuration?)
|
||||
I believe that the on-board Accelerometer, Audio Codec, and touch
|
||||
panel controller should have been detected (but perhaps the touch
|
||||
panel is not powered in this configuration since the LCD is not
|
||||
configured?)
|
||||
|
||||
Codec I2C address: 0x1a
|
||||
Accel I2C address: 0x1d
|
||||
Touch panel I2C address: 0x38
|
||||
Codec I2C address: 0x1a
|
||||
Accel I2C address: 0x1d
|
||||
Touch panel I2C address: 0x38
|
||||
|
||||
4. Support for the on-board USER button is included as well as the
|
||||
button test program at apps/examples/buttons. This test is useful
|
||||
for verifying the functionality of GPIO interrupts.
|
||||
|
|
|
|||
|
|
@ -21,6 +21,7 @@ CONFIG_LPC54_EMC_DYNAMIC_CS0_OFFSET=0x00080000
|
|||
CONFIG_LPC54_EMC_DYNAMIC_CS0_SIZE=0x00f80000
|
||||
CONFIG_LPC54_EMC_DYNAMIC_CS0=y
|
||||
CONFIG_LPC54_EMC=y
|
||||
CONFIG_LPC54_GPIOIRQ=y
|
||||
CONFIG_LPC54_LCD_BGR=y
|
||||
CONFIG_LPC54_LCD_BPP16_565=y
|
||||
CONFIG_LPC54_LCD_HBACKPORCH=43
|
||||
|
|
|
|||
|
|
@ -260,10 +260,10 @@
|
|||
* software usage.
|
||||
*/
|
||||
|
||||
#define BOARD_BUTTON_USER 0
|
||||
#define BOARD_NUM_BUTTONS 1
|
||||
#define BUTTON_USER 0
|
||||
#define NUM_BUTTONS 1
|
||||
|
||||
#define BOARD_BUTTON_USER_BIT (1 << BOARD_BUTTON_USER)
|
||||
#define BUTTON_USER_BIT (1 << BUTTON_USER)
|
||||
|
||||
/* Pin Disambiguation *******************************************************/
|
||||
/* Flexcomm0/USART0
|
||||
|
|
|
|||
|
|
@ -1,13 +1,18 @@
|
|||
# CONFIG_ARCH_FPU is not set
|
||||
CONFIG_ARCH_BOARD_LPCXPRESSO_LPC54628=y
|
||||
CONFIG_ARCH_BOARD="lpcxpresso-lpc54628"
|
||||
CONFIG_ARCH_BUTTONS=y
|
||||
CONFIG_ARCH_CHIP_LPC54628=y
|
||||
CONFIG_ARCH_CHIP_LPC54XX=y
|
||||
CONFIG_ARCH_IRQBUTTONS=y
|
||||
CONFIG_ARCH_STACKDUMP=y
|
||||
CONFIG_ARCH_STDARG_H=y
|
||||
CONFIG_ARCH="arm"
|
||||
CONFIG_BOARD_LOOPSPERMSEC=18535
|
||||
CONFIG_BUILTIN=y
|
||||
CONFIG_BUTTONS_LOWER=y
|
||||
CONFIG_BUTTONS=y
|
||||
CONFIG_EXAMPLES_BUTTONS=y
|
||||
CONFIG_EXAMPLES_NSH=y
|
||||
CONFIG_FAT_LCNAMES=y
|
||||
CONFIG_FAT_LFN=y
|
||||
|
|
@ -15,8 +20,10 @@ CONFIG_FS_FAT=y
|
|||
CONFIG_FS_PROCFS=y
|
||||
CONFIG_I2C=y
|
||||
CONFIG_I2CTOOL_MAXBUS=9
|
||||
CONFIG_INPUT=y
|
||||
CONFIG_LPC54_EMC_DYNAMIC_CS0=y
|
||||
CONFIG_LPC54_EMC=y
|
||||
CONFIG_LPC54_GPIOIRQ=y
|
||||
CONFIG_LPC54_I2C2_MASTER=y
|
||||
CONFIG_LPC54_USART0=y
|
||||
CONFIG_MAX_TASKS=16
|
||||
|
|
|
|||
|
|
@ -42,6 +42,10 @@ ifeq ($(CONFIG_ARCH_LEDS),y)
|
|||
CSRCS += lpc54_autoleds.c
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_ARCH_BUTTONS),y)
|
||||
CSRCS += lpc54_buttons.c
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_LIB_BOARDCTL),y)
|
||||
CSRCS += lpc54_appinit.c
|
||||
endif
|
||||
|
|
|
|||
|
|
@ -46,6 +46,10 @@
|
|||
#include <nuttx/video/fb.h>
|
||||
#include <nuttx/i2c/i2c_master.h>
|
||||
|
||||
#ifdef CONFIG_BUTTONS_LOWER
|
||||
# include <nuttx/input/buttons.h>
|
||||
#endif
|
||||
|
||||
#include "lpc54_config.h"
|
||||
#include "lpc54_i2c_master.h"
|
||||
#include "lpcxpresso-lpc54628.h"
|
||||
|
|
@ -178,6 +182,16 @@ int lpc54_bringup(void)
|
|||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_BUTTONS_LOWER
|
||||
/* Register the BUTTON driver */
|
||||
|
||||
ret = btn_lower_initialize("/dev/buttons");
|
||||
if (ret < 0)
|
||||
{
|
||||
syslog(LOG_ERR, "ERROR: btn_lower_initialize() failed: %d\n", ret);
|
||||
}
|
||||
#endif
|
||||
|
||||
UNUSED(ret);
|
||||
return OK;
|
||||
}
|
||||
|
|
|
|||
153
configs/lpcxpresso-lpc54628/src/lpc54_buttons.c
Normal file
153
configs/lpcxpresso-lpc54628/src/lpc54_buttons.c
Normal file
|
|
@ -0,0 +1,153 @@
|
|||
/****************************************************************************
|
||||
* configs/lpcxpresso-lpc54628/src/lpc54_buttons.c
|
||||
*
|
||||
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include <stdint.h>
|
||||
#include <errno.h>
|
||||
|
||||
#include <nuttx/arch.h>
|
||||
#include <nuttx/board.h>
|
||||
#include <nuttx/irq.h>
|
||||
|
||||
#include <nuttx/irq.h>
|
||||
|
||||
#include "lpc54_gpio.h"
|
||||
#include "lpcxpresso-lpc54628.h"
|
||||
|
||||
#include <arch/board/board.h>
|
||||
|
||||
#ifdef CONFIG_ARCH_BUTTONS
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: board_button_initialize
|
||||
*
|
||||
* Description:
|
||||
* board_button_initialize() must be called to initialize button resources.
|
||||
* After that, board_buttons() may be called to collect the current state
|
||||
* of all buttons or board_button_irq() may be called to register button
|
||||
* interrupt handlers.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void board_button_initialize(void)
|
||||
{
|
||||
(void)lpc54_gpio_config(GPIO_BUTTON_USER);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: board_buttons
|
||||
*
|
||||
* Description:
|
||||
* After board_button_initialize() has been called, board_buttons() may be
|
||||
* called to collect the state of all buttons. board_buttons() returns an
|
||||
* 32-bit bit set with each bit associated with a button. See the BUTTON*
|
||||
* definitions above for the meaning of each bit in the returned value.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
uint32_t board_buttons(void)
|
||||
{
|
||||
return lpc54_gpio_read(GPIO_BUTTON_USER) ? 0 : BUTTON_USER_BIT;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: board_button_irq
|
||||
*
|
||||
* Description:
|
||||
* This function may be called to register an interrupt handler that will
|
||||
* be called when a button is depressed or released. The ID value is one
|
||||
* of the BUTTON* definitions provided above.
|
||||
*
|
||||
* Configuration Notes:
|
||||
* Configuration CONFIG_AVR32_GPIOIRQ must be selected to enable the
|
||||
* overall GPIO IRQ feature and CONFIG_AVR32_GPIOIRQSETA and/or
|
||||
* CONFIG_AVR32_GPIOIRQSETB must be enabled to select GPIOs to support
|
||||
* interrupts on. For button support, bits 2 and 3 must be set in
|
||||
* CONFIG_AVR32_GPIOIRQSETB (PB2 and PB3).
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#if defined(CONFIG_LPC54_GPIOIRQ) && defined(CONFIG_ARCH_IRQBUTTONS)
|
||||
int board_button_irq(int id, xcpt_t irqhandler, FAR void *arg)
|
||||
{
|
||||
int ret = -EINVAL;
|
||||
|
||||
if (id == BUTTON_USER)
|
||||
{
|
||||
int irq;
|
||||
|
||||
/* Get the IRQ number assigned to the port/pin when it was condfigured. */
|
||||
|
||||
irq = lpc54_gpio_irqno(GPIO_BUTTON_USER);
|
||||
if (irq < 0)
|
||||
{
|
||||
return irq;
|
||||
}
|
||||
|
||||
/* Are we attaching or detaching? */
|
||||
|
||||
if (irqhandler != NULL)
|
||||
{
|
||||
/* Yes.. Attach and enable the interrupt */
|
||||
|
||||
ret = irq_attach(irq, irqhandler, arg);
|
||||
if (ret >= 0)
|
||||
{
|
||||
up_enable_irq(irq);
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* No.. Disable and detach the interrupt */
|
||||
|
||||
up_disable_irq(irq);
|
||||
ret = irq_detach(irq);
|
||||
}
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* CONFIG_ARCH_BUTTONS */
|
||||
|
|
@ -93,9 +93,14 @@
|
|||
* P0.6 are also used as EMC_D2, EMC_D3, and EMC_D4, respectively.
|
||||
*
|
||||
* So SW5 is really the only button that that is generally available for
|
||||
* software usage.
|
||||
* software usage. When pressed, it will be sensed low.
|
||||
*
|
||||
* P1.1 is a Type D pin.
|
||||
*/
|
||||
|
||||
#define GPIO_BUTTON_USER \
|
||||
(GPIO_PORT1 | GPIO_PIN1 | GPIO_INTBOTH | GPIO_MODE_DIGITAL | GPIO_FILTER_ON)
|
||||
|
||||
/* LCD/TSC definitions ******************************************************/
|
||||
/* The backlight is controlled by P3.31 and is intended to connect via PWM
|
||||
* to control the brightness level. For simplicity here, it configured as a
|
||||
|
|
|
|||
|
|
@ -194,7 +194,7 @@
|
|||
#define BOARD_JOYSTICK_LEFT 6
|
||||
#define BOARD_JOYSTICK_RIGHT 7
|
||||
|
||||
#define BOARD_NUM_BUTTONS 8
|
||||
#define NUM_BUTTONS 8
|
||||
|
||||
#define BOARD_BUTTON_BUTTON1_BIT (1 << BOARD_BUTTON_1)
|
||||
#define BOARD_BUTTON_BUTTON2_BIT (1 << BOARD_BUTTON_2)
|
||||
|
|
|
|||
|
|
@ -290,7 +290,7 @@
|
|||
#define BOARD_JOYSTICK_D 6
|
||||
#define BOARD_JOYSTICK_CTR 7
|
||||
|
||||
#define BOARD_NUM_BUTTONS 8
|
||||
#define NUM_BUTTONS 8
|
||||
|
||||
#define BOARD_BUTTON_USER1_BIT (1 << BOARD_BUTTON_USER1)
|
||||
#define BOARD_BUTTON_USER2_BIT (1 << BOARD_BUTTON_USER2)
|
||||
|
|
|
|||
|
|
@ -194,7 +194,7 @@
|
|||
#define BOARD_BUTTON_3 2
|
||||
#define BOARD_BUTTON_4 3
|
||||
#define BOARD_BUTTON_5 4
|
||||
#define BOARD_NUM_BUTTONS 5
|
||||
#define NUM_BUTTONS 5
|
||||
|
||||
#define BOARD_BUTTON1_BIT (1 << BOARD_BUTTON_1)
|
||||
#define BOARD_BUTTON2_BIT (1 << BOARD_BUTTON_2)
|
||||
|
|
|
|||
Loading…
Reference in a new issue