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Merged in hardlulz/modem-3.0-nuttx/fix-stmpe811-gpio (pull request #523)
Fix GPIO operation of STMPE811 driver. Fixed issues: 1. STMPE811_GPIO_DIR was defined for register name and later was redefined to be the pin direction mask for `stmpe811_gpioconfig` I decided to change register name to be STMPE811_GPIO_DIR_REG, and keep pin direction mask STMPE811_GPIO_DIR, so that any external code that already use this driver will be unchanged. 2. The STMPE811 register GPIO_DIR uses bit value 1 for output and 0 for input, but `stmpe811_gpioconfig` set the opposite. 3. The call to `stmpe811_gpiowrite` from inside of `stmpe811_gpioconfig` leaded to deadlock. Approved-by: Gregory Nutt <gnutt@nuttx.org>
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2 changed files with 17 additions and 10 deletions
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@ -172,22 +172,29 @@ int stmpe811_gpioconfig(STMPE811_HANDLE handle, uint8_t pinconfig)
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{
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/* The pin is an output */
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regval = stmpe811_getreg8(priv, STMPE811_GPIO_DIR);
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regval &= ~pinmask;
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stmpe811_putreg8(priv, STMPE811_GPIO_DIR, regval);
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regval = stmpe811_getreg8(priv, STMPE811_GPIO_DIR_REG);
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regval |= pinmask;
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stmpe811_putreg8(priv, STMPE811_GPIO_DIR_REG, regval);
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/* Set its initial output value */
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stmpe811_gpiowrite(handle, pinconfig,
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(pinconfig & STMPE811_GPIO_VALUE) != STMPE811_GPIO_ZERO);
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if ((pinconfig & STMPE811_GPIO_VALUE) != STMPE811_GPIO_ZERO)
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{
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/* Set the output valu(s)e by writing to the SET register */
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stmpe811_putreg8(priv, STMPE811_GPIO_SETPIN, (1 << pin));
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}
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else
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{
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/* Clear the output value(s) by writing to the CLR register */
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stmpe811_putreg8(priv, STMPE811_GPIO_CLRPIN, (1 << pin));
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}
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}
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else
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{
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/* It is an input */
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regval = stmpe811_getreg8(priv, STMPE811_GPIO_DIR);
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regval |= pinmask;
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stmpe811_putreg8(priv, STMPE811_GPIO_DIR, regval);
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regval = stmpe811_getreg8(priv, STMPE811_GPIO_DIR_REG);
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regval &= ~pinmask;
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stmpe811_putreg8(priv, STMPE811_GPIO_DIR_REG, regval);
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/* Set up the falling edge detection */
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@ -190,7 +190,7 @@
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#define STMPE811_GPIO_SETPIN 0x10 /* GPIO set pin register */
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#define STMPE811_GPIO_CLRPIN 0x11 /* GPIO clear pin register */
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#define STMPE811_GPIO_MPSTA 0x12 /* GPIO monitor pin state register */
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#define STMPE811_GPIO_DIR 0x13 /* GPIO direction register */
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#define STMPE811_GPIO_DIR_REG 0x13 /* GPIO direction register */
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#define STMPE811_GPIO_ED 0x14 /* GPIO edge detect register */
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#define STMPE811_GPIO_RE 0x15 /* GPIO rising edge register */
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#define STMPE811_GPIO_FE 0x16 /* GPIO falling edge register */
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