diff --git a/arch/Kconfig b/arch/Kconfig index 193d860273..efb95eb2d4 100644 --- a/arch/Kconfig +++ b/arch/Kconfig @@ -171,11 +171,15 @@ config ARCH_HAVE_IRQPRIO bool default n -config ARCH_L2CACHE +config ARCH_ICACHE bool default n -config ARCH_HAVE_COHERENT_DCACHE +config ARCH_DCACHE + bool + default n + +config ARCH_L2CACHE bool default n diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 80b6733cb6..fedb3a3afc 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -405,6 +405,8 @@ endchoice config ARCH_ARM7TDMI bool default n + select ARCH_DCACHE + select ARCH_ICACHE ---help--- The Arm7TDMI-S is an excellent workhorse processor capable of a wide array of applications. Traditionally used in mobile handsets, the @@ -413,6 +415,8 @@ config ARCH_ARM7TDMI config ARCH_ARM920T bool default n + select ARCH_DCACHE + select ARCH_ICACHE select ARCH_HAVE_MMU select ARCH_USE_MMU ---help--- @@ -428,6 +432,8 @@ config ARCH_ARM920T config ARCH_ARM926EJS bool default n + select ARCH_DCACHE + select ARCH_ICACHE select ARCH_HAVE_MMU select ARCH_USE_MMU ---help--- @@ -449,6 +455,8 @@ config ARCH_ARM926EJS config ARCH_ARM1136J bool default n + select ARCH_DCACHE + select ARCH_ICACHE select ARCH_HAVE_MMU select ARCH_USE_MMU ---help--- @@ -459,6 +467,8 @@ config ARCH_ARM1136J config ARCH_ARM1156T2 bool default n + select ARCH_DCACHE + select ARCH_ICACHE select ARCH_HAVE_MMU select ARCH_USE_MMU ---help--- @@ -468,6 +478,8 @@ config ARCH_ARM1156T2 config ARCH_ARM1176JZ bool default n + select ARCH_DCACHE + select ARCH_ICACHE select ARCH_HAVE_MMU select ARCH_USE_MMU ---help--- @@ -527,54 +539,59 @@ config ARCH_CORTEXM7 select ARCH_HAVE_HIPRI_INTERRUPT select ARCH_HAVE_RESET select ARCH_HAVE_TESTSET - select ARCH_HAVE_COHERENT_DCACHE if ELF || MODULE select ARCH_HAVE_HARDFAULT_DEBUG select ARCH_HAVE_MEMFAULT_DEBUG config ARCH_CORTEXA5 bool default n + select ARCH_DCACHE + select ARCH_ICACHE select ARCH_HAVE_MMU select ARCH_USE_MMU select ARCH_HAVE_TESTSET - select ARCH_HAVE_COHERENT_DCACHE if ELF || MODULE config ARCH_CORTEXA8 bool default n + select ARCH_DCACHE + select ARCH_ICACHE select ARCH_HAVE_MMU select ARCH_USE_MMU select ARCH_HAVE_TESTSET - select ARCH_HAVE_COHERENT_DCACHE if ELF || MODULE config ARCH_CORTEXA9 bool default n + select ARCH_DCACHE + select ARCH_ICACHE select ARCH_HAVE_MMU select ARCH_USE_MMU select ARCH_HAVE_TESTSET - select ARCH_HAVE_COHERENT_DCACHE if ELF || MODULE config ARCH_CORTEXR4 bool default n + select ARCH_DCACHE + select ARCH_ICACHE select ARCH_HAVE_MPU select ARCH_HAVE_TESTSET - select ARCH_HAVE_COHERENT_DCACHE if ELF || MODULE config ARCH_CORTEXR5 bool default n + select ARCH_DCACHE + select ARCH_ICACHE select ARCH_HAVE_MPU select ARCH_HAVE_TESTSET - select ARCH_HAVE_COHERENT_DCACHE if ELF || MODULE config ARCH_CORTEXR7 bool default n + select ARCH_DCACHE + select ARCH_ICACHE select ARCH_HAVE_MPU select ARCH_HAVE_TESTSET - select ARCH_HAVE_COHERENT_DCACHE if ELF || MODULE config ARCH_FAMILY string diff --git a/arch/arm/src/a1x/Make.defs b/arch/arm/src/a1x/Make.defs index 60c9502f1f..aae34c2020 100644 --- a/arch/arm/src/a1x/Make.defs +++ b/arch/arm/src/a1x/Make.defs @@ -111,11 +111,7 @@ CMN_CSRCS += arm_virtpgaddr.c endif endif -ifeq ($(CONFIG_ELF),y) -CMN_CSRCS += arm_coherent_dcache.c -else ifeq ($(CONFIG_MODULE),y) -CMN_CSRCS += arm_coherent_dcache.c -endif +CMN_CSRCS += arm_cache.c ifeq ($(CONFIG_ARCH_FPU),y) CMN_ASRCS += arm_savefpu.S arm_restorefpu.S diff --git a/arch/arm/src/am335x/Make.defs b/arch/arm/src/am335x/Make.defs index 6f2de1c3a7..65cff8e698 100644 --- a/arch/arm/src/am335x/Make.defs +++ b/arch/arm/src/am335x/Make.defs @@ -107,11 +107,7 @@ CMN_CSRCS += arm_virtpgaddr.c endif endif -ifeq ($(CONFIG_ELF),y) -CMN_CSRCS += arm_coherent_dcache.c -else ifeq ($(CONFIG_MODULE),y) -CMN_CSRCS += arm_coherent_dcache.c -endif +CMN_CSRCS += arm_cache.c ifeq ($(CONFIG_ARCH_FPU),y) CMN_ASRCS += arm_savefpu.S arm_restorefpu.S diff --git a/arch/arm/src/am335x/am335x_boot.c b/arch/arm/src/am335x/am335x_boot.c index 56c5178728..d724772563 100644 --- a/arch/arm/src/am335x/am335x_boot.c +++ b/arch/arm/src/am335x/am335x_boot.c @@ -43,6 +43,7 @@ #include #include +#include #ifdef CONFIG_PAGING # include #endif @@ -52,7 +53,6 @@ #include "chip.h" #include "arm.h" #include "mmu.h" -#include "cache.h" #include "fpu.h" #include "up_internal.h" #include "up_arch.h" @@ -348,8 +348,8 @@ static void am335x_copyvectorblock(void) #else /* Flush the DCache to assure that the vector data is in physical RAM */ - arch_clean_dcache((uintptr_t)AM335X_VECTOR_VSRAM, - (uintptr_t)AM335X_VECTOR_VSRAM + am335x_vectorsize()); + up_clean_dcache((uintptr_t)AM335X_VECTOR_VSRAM, + (uintptr_t)AM335X_VECTOR_VSRAM + am335x_vectorsize()); #endif } diff --git a/arch/arm/src/arm/arm.h b/arch/arm/src/arm/arm.h index 81fe724be3..a58bbbd04a 100644 --- a/arch/arm/src/arm/arm.h +++ b/arch/arm/src/arm/arm.h @@ -44,12 +44,6 @@ * Pre-processor Definitions ************************************************************************************/ -#undef CONFIG_ALIGNMENT_TRAP -#undef CONFIG_DCACHE_WRITETHROUGH -#undef CONFIG_CACHE_ROUND_ROBIN -#undef CONFIG_DCACHE_DISABLE -#undef CONFIG_ICACHE_DISABLE - /* ARM9EJS **************************************************************************/ /* PSR bits */ diff --git a/arch/arm/src/arm/cache.h b/arch/arm/src/arm/cache.h deleted file mode 100644 index a463490bc7..0000000000 --- a/arch/arm/src/arm/cache.h +++ /dev/null @@ -1,78 +0,0 @@ -/**************************************************************************** - * arch/arm/src/arm/cache.h - * - * Copyright (C) 2013 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Several of these cache operations come from Atmel sample code with - * modifications for better integration with NuttX. The Atmel sample code - * has a BSD compatibile license that requires this copyright notice: - * - * Copyright (c) 2008, Atmel Corporation - * - * [Actually, I think that all of the Atmel functions are commented out now] - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the names NuttX nor Atmel nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_ARM_CACHE_H -#define __ARCH_ARM_SRC_ARM_CACHE_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -/**************************************************************************** - * Pre-processor Defintiions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -void cp15_flush_idcache(uint32_t start, uint32_t end); -#if 0 /* Not used */ -void cp15_invalidate_idcache(void); -void cp15_invalidate_icache(void); -#endif -void cp15_invalidate_dcache(uint32_t start, uint32_t end); -#if 0 /* Not used */ -void cp15_invalidate_dcache_all(void); -void cp15_prefetch_icacheline(unsigned int value); -void cp15_testcleaninvalidate_dcache(void); -void cp15_drain_writebuffer(void); - -unsigned int cp15_read_dcachelockdown(void); -void cp15_write_dcachelockdown(unsigned int value); -unsigned int cp15_read_icachelockdown(void); -void cp15_write_icachelockdown(unsigned int value); -#endif - -#endif /* __ARCH_ARM_SRC_ARM_CACHE_H */ - diff --git a/arch/arm/src/arm/up_cache.S b/arch/arm/src/arm/up_cache.S index 564df75534..d16f79625d 100644 --- a/arch/arm/src/arm/up_cache.S +++ b/arch/arm/src/arm/up_cache.S @@ -41,7 +41,7 @@ * ****************************************************************************/ - .file "up_cp15.S" + .file "up_cache.S" /**************************************************************************** * Included Files @@ -93,10 +93,10 @@ * the corresponding I-Cache lines. */ - .globl cp15_flush_idcache - .type cp15_flush_idcache, function + .globl up_coherent_dcache + .type up_coherent_dcache, function -cp15_flush_idcache: +up_coherent_dcache: bic r0, r0, #CACHE_DLINESIZE - 1 1: mcr p15, 0, r0, c7, c10, 1 /* Clean D entry */ mcr p15, 0, r0, c7, c5, 1 /* Invalidate I entry */ @@ -105,34 +105,28 @@ cp15_flush_idcache: blo 1b mcr p15, 0, r0, c7, c10, 4 /* Drain WB */ mov pc, lr - .size cp15_flush_idcache, .-cp15_flush_idcache + .size up_coherent_dcache, .-up_coherent_dcache -#if 0 /* Not used */ -/* Invalidate all of Icache and Dcache */ +/* Invalidate ICache in the region described by r0=start and r1=end. */ - .globl cp15_invalidate_idcache - .type cp15_invalidate_idcache, function + .globl up_invalidate_icache + .type up_invalidate_icache, function -cp15_invalidate_idcache: - mov r0, #0 - mcr p15, 0, r0, c7, c7, 0 - nop - nop - nop - nop - nop - nop - nop - nop - bx lr - .size cp15_invalidate_idcache, . - cp15_invalidate_idcache +up_invalidate_icache: + bic r0, r0, #CACHE_DLINESIZE - 1 +1: mcr p15, 0, r0, c7, c5, 1 /* Invalidate I entry */ + add r0, r0, #CACHE_DLINESIZE + cmp r0, r1 + blo 1b + mov pc, lr + .size up_invalidate_icache, .-up_invalidate_icache /* Invalidate all of Icache */ - .globl cp15_invalidate_icache - .type cp15_invalidate_icache, function + .globl up_invalidate_icache_all + .type up_invalidate_icache_all, function -cp15_invalidate_icache: +up_invalidate_icache_all: mov r0, #0 mcr p15, 0, r0, c7, c5, 0 nop @@ -144,30 +138,28 @@ cp15_invalidate_icache: nop nop bx lr - .size cp15_invalidate_icache, . - cp15_invalidate_icache -#endif /* Not used */ + .size up_invalidate_icache_all, . - up_invalidate_icache_all /* Invalidate D-Cache in the region described by r0=start and r1=end. */ - .globl cp15_invalidate_dcache - .type cp15_invalidate_dcache, function + .globl up_invalidate_dcache + .type up_invalidate_dcache, function -cp15_invalidate_dcache: +up_invalidate_dcache: bic r0, r0, #CACHE_DLINESIZE - 1 1: mcr p15, 0, r0, c7, c6, 1 /* Invalidate D entry */ add r0, r0, #CACHE_DLINESIZE cmp r0, r1 blo 1b mov pc, lr - .size cp15_invalidate_dcache, .-cp15_invalidate_dcache + .size up_invalidate_dcache, .-up_invalidate_dcache -#if 0 /* Not used */ /* Invalidate Dcache */ - .globl cp15_invalidate_dcache_all - .type cp15_invalidate_dcache_all, function + .globl up_invalidate_dcache_all + .type up_invalidate_dcache_all, function -cp15_invalidate_dcache_all: +up_invalidate_dcache_all: mov r0, #0 mcr p15, 0, r0, c7, c6, 0 nop @@ -179,124 +171,59 @@ cp15_invalidate_dcache_all: nop nop bx lr - .size cp15_invalidate_dcache_all, . - cp15_invalidate_dcache_all + .size up_invalidate_dcache_all, . - up_invalidate_dcache_all -/* CP15 Prefetch Icache line c7 - * Performs an Icache lookup of the specified modified virtual address. - * If the cache misses, and the region is cacheable, a linefill is performed. - * Prefetch Icache line (MVA): MCR p15, 0, , c7, c13, 1 - */ +/* Clean D-Cache in the region described by r0=start and r1=end. */ - .globl cp15_prefetch_icacheline - .type cp15_prefetch_icacheline, function + .globl up_clean_dcache + .type up_clean_dcache, function -cp15_prefetch_icacheline: - mcr p15, 0, r0, c7, c13, 1 +up_clean_dcache: + bic r0, r0, #CACHE_DLINESIZE - 1 +1: mcr p15, 0, r0, c7, c10, 1 /* Clean D entry */ + add r0, r0, #CACHE_DLINESIZE + cmp r0, r1 + blo 1b + mov pc, lr + .size up_clean_dcache, .-up_clean_dcache + +/* Clean D-cache */ + + .globl up_clean_dcache_all + .type up_clean_dcache_all, function + +up_clean_dcache_all: + mrc p15, 0, r0, c7, c10, 3 + bne up_clean_dcache_all bx lr - .size cp15_prefetch_icacheline, . - cp15_prefetch_icacheline + .size up_clean_dcache_all, . - up_clean_dcache_all + +/* Clean & invalidate D-Cache in the region described by r0=start and r1=end. */ + + .globl up_flush_dcache + .type up_flush_dcache, function + +up_flush_dcache: + bic r0, r0, #CACHE_DLINESIZE - 1 +1: mcr p15, 0, r0, c7, c14, 1 /* Clean & invalidate D entry */ + add r0, r0, #CACHE_DLINESIZE + cmp r0, r1 + blo 1b + mov pc, lr + .size up_flush_dcache, .-up_flush_dcache /* CP15 Test, clean, and invalidate Dcache c7 * As for test and clean, except that when the entire cache has * been tested and cleaned, it is invalidated. */ - .globl cp15_testcleaninvalidate_dcache - .type cp15_testcleaninvalidate_dcache, function + .globl up_flush_dcache_all + .type up_flush_dcache_all, function -cp15_testcleaninvalidate_dcache: +up_flush_dcache_all: mrc p15, 0, r0, c7, c14, 3 - bne cp15_testcleaninvalidate_dcache + bne up_flush_dcache_all bx lr - .size cp15_testcleaninvalidate_dcache, . - cp15_testcleaninvalidate_dcache + .size up_flush_dcache_all, . - up_flush_dcache_all -/* CP15 Drain write buffer c7 - * This instruction acts as an explicit memory barrier. It drains - * the contents of the write buffers of all memory stores - * occurring in program order before this instruction is - * completed. No instructions occurring in program order - * after this instruction are executed until it completes. This - * can be used when timing of specific stores to the level two - * memory system has to be controlled (for example, when a - * store to an interrupt acknowledge location has to complete - * before interrupts are enabled). - */ - - .globl cp15_drain_writebuffer - .type cp15_drain_writebuffer, function - -cp15_drain_writebuffer: - mov r0, #0 - mcr p15, 0, r0, c7, c10, 4 - bx lr - .size cp15_drain_writebuffer, . - cp15_drain_writebuffer - -/**************************************************************************** - * Cache Lockdown - ****************************************************************************/ - -/* Cache Lockdown Register c9 - * The Cache Lockdown Register uses a cache-way-based locking scheme (Format C) that - * enables you to control each cache way independently. - * These registers enable you to control which cache ways of the four-way cache are used - * for the allocation on a linefill. When the registers are defined, subsequent linefills are - * only placed in the specified target cache way. This gives you some control over the - * cache pollution caused by particular applications, and provides a traditional lockdown - * operation for locking critical code into the cache. - * - * Read Dcache Lockdown Register MRC p15,0,,c9,c0,0 - * Write Dcache Lockdown Register MCR p15,0,,c9,c0,0 - * Read Icache Lockdown Register MRC p15,0,,c9,c0,1 - * Write Icache Lockdown Register MCR p15,0,,c9,c0,1 - */ - - .globl cp15_read_dcachelockdown - .type cp15_read_dcachelockdown, function - -cp15_read_dcachelockdown: - mov r0, #0 - mrc p15, 0, r0, c9, c0, 0 - bx lr - .size cp15_read_dcachelockdown, . - cp15_read_dcachelockdown - - .globl cp15_write_dcachelockdown - .type cp15_write_dcachelockdown, function - -cp15_write_dcachelockdown: - mcr p15, 0, r0, c9, c0, 0 - nop - nop - nop - nop - nop - nop - nop - nop - bx lr - .size cp15_write_dcachelockdown, . - cp15_write_dcachelockdown - - .globl cp15_read_icachelockdown - .type cp15_read_icachelockdown, function - -cp15_read_icachelockdown: - mov r0, #0 - mrc p15, 0, r0, c9, c0, 1 - bx lr - .size cp15_read_icachelockdown, . - cp15_read_icachelockdown - - .globl cp15_write_icachelockdown - .type cp15_write_icachelockdown, function - -cp15_write_icachelockdown: - mcr p15, 0, r0, c9, c0, 1 - nop - nop - nop - nop - nop - nop - nop - nop - bx lr - .size cp15_write_icachelockdown, . - cp15_write_icachelockdown -#endif /* Not used */ .end diff --git a/arch/arm/src/armv7-a/arm_addrenv.c b/arch/arm/src/armv7-a/arm_addrenv.c index def1ea66d9..f327a5fd92 100644 --- a/arch/arm/src/armv7-a/arm_addrenv.c +++ b/arch/arm/src/armv7-a/arm_addrenv.c @@ -118,7 +118,6 @@ #include #include "pgalloc.h" -#include "cache.h" #include "mmu.h" #include "addrenv.h" @@ -181,8 +180,8 @@ static int up_addrenv_initdata(uintptr_t l2table) /* Invalidate D-Cache so that we read from the physical memory */ - arch_invalidate_dcache((uintptr_t)virtptr, - (uintptr_t)virtptr + sizeof(uint32_t)); + up_invalidate_dcache((uintptr_t)virtptr, + (uintptr_t)virtptr + sizeof(uint32_t)); /* Get the physical address of the first page of of .bss/.data */ @@ -208,8 +207,8 @@ static int up_addrenv_initdata(uintptr_t l2table) /* Make sure that the initialized data is flushed to physical memory. */ - arch_flush_dcache((uintptr_t)virtptr, - (uintptr_t)virtptr + ARCH_DATA_RESERVE_SIZE); + up_flush_dcache((uintptr_t)virtptr, + (uintptr_t)virtptr + ARCH_DATA_RESERVE_SIZE); #ifndef CONFIG_ARCH_PGPOOL_MAPPING /* Restore the scratch section L1 page table entry */ @@ -715,18 +714,18 @@ int up_addrenv_coherent(FAR const group_addrenv_t *addrenv) #warning REVISIT... causes crashes #if 0 - arch_clean_dcache(CONFIG_ARCH_TEXT_VBASE, - CONFIG_ARCH_TEXT_VBASE + - CONFIG_ARCH_TEXT_NPAGES * MM_PGSIZE - 1); + up_clean_dcache(CONFIG_ARCH_TEXT_VBASE, + CONFIG_ARCH_TEXT_VBASE + + CONFIG_ARCH_TEXT_NPAGES * MM_PGSIZE - 1); - arch_clean_dcache(CONFIG_ARCH_DATA_VBASE, - CONFIG_ARCH_DATA_VBASE + - CONFIG_ARCH_DATA_NPAGES * MM_PGSIZE - 1); + up_clean_dcache(CONFIG_ARCH_DATA_VBASE, + CONFIG_ARCH_DATA_VBASE + + CONFIG_ARCH_DATA_NPAGES * MM_PGSIZE - 1); #endif #ifdef CONFIG_BUILD_KERNEL - arch_clean_dcache(CONFIG_ARCH_HEAP_VBASE, - CONFIG_ARCH_HEAP_VBASE + addrenv->heapsize); + up_clean_dcache(CONFIG_ARCH_HEAP_VBASE, + CONFIG_ARCH_HEAP_VBASE + addrenv->heapsize); #endif return OK; diff --git a/arch/arm/src/armv7-a/arm_addrenv_shm.c b/arch/arm/src/armv7-a/arm_addrenv_shm.c index cc9c9440d8..7e6387c167 100644 --- a/arch/arm/src/armv7-a/arm_addrenv_shm.c +++ b/arch/arm/src/armv7-a/arm_addrenv_shm.c @@ -49,7 +49,6 @@ #include #include "mmu.h" -#include "cache.h" #include "addrenv.h" #include "pgalloc.h" @@ -195,9 +194,9 @@ int up_shmat(FAR uintptr_t *pages, unsigned int npages, uintptr_t vaddr) * flush the entire L2 page table numerous times. */ - arch_flush_dcache((uintptr_t)l2table, - (uintptr_t)l2table + - ENTRIES_PER_L2TABLE * sizeof(uint32_t)); + up_flush_dcache((uintptr_t)l2table, + (uintptr_t)l2table + + ENTRIES_PER_L2TABLE * sizeof(uint32_t)); #ifndef CONFIG_ARCH_PGPOOL_MAPPING /* Restore the scratch section L1 page table entry */ @@ -313,9 +312,9 @@ int up_shmdt(uintptr_t vaddr, unsigned int npages) * flush the entire L2 page table numerous times. */ - arch_flush_dcache((uintptr_t)l2table, - (uintptr_t)l2table + - ENTRIES_PER_L2TABLE * sizeof(uint32_t)); + up_flush_dcache((uintptr_t)l2table, + (uintptr_t)l2table + + ENTRIES_PER_L2TABLE * sizeof(uint32_t)); #ifndef CONFIG_ARCH_PGPOOL_MAPPING /* Restore the scratch section L1 page table entry */ diff --git a/arch/arm/src/armv7-a/arm_addrenv_utils.c b/arch/arm/src/armv7-a/arm_addrenv_utils.c index 2eb58623af..f3f60bb2c9 100644 --- a/arch/arm/src/armv7-a/arm_addrenv_utils.c +++ b/arch/arm/src/armv7-a/arm_addrenv_utils.c @@ -43,10 +43,8 @@ #include #include - #include -#include "cache.h" #include "mmu.h" #include "pgalloc.h" #include "addrenv.h" @@ -166,9 +164,9 @@ int arm_addrenv_create_region(FAR uintptr_t **list, unsigned int listlen, * memory. */ - arch_flush_dcache((uintptr_t)l2table, - (uintptr_t)l2table + - ENTRIES_PER_L2TABLE * sizeof(uint32_t)); + up_flush_dcache((uintptr_t)l2table, + (uintptr_t)l2table + + ENTRIES_PER_L2TABLE * sizeof(uint32_t)); #ifndef CONFIG_ARCH_PGPOOL_MAPPING /* Restore the scratch section L1 page table entry */ diff --git a/arch/arm/src/armv7-r/cache.h b/arch/arm/src/armv7-a/arm_cache.c similarity index 72% rename from arch/arm/src/armv7-r/cache.h rename to arch/arm/src/armv7-a/arm_cache.c index 721f40313f..c09ab06820 100644 --- a/arch/arm/src/armv7-r/cache.h +++ b/arch/arm/src/armv7-a/arm_cache.c @@ -1,7 +1,7 @@ -/************************************************************************************ - * arch/arm/src/armv7-r/cache.h +/**************************************************************************** + * arch/arm/src/armv7-a/arm_cache.c * - * Copyright (C) 2015 Gregory Nutt. All rights reserved. + * Copyright (C) 2014, 2019 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -31,25 +31,22 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * - ************************************************************************************/ + ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_ARMV7_R_CACHE_H -#define __ARCH_ARM_SRC_ARMV7_R_CACHE_H - -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include +#include #include -#include "sctlr.h" #include "cp15_cacheops.h" #include "l2cc.h" -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ /* Intrinsics are used in these inline functions */ @@ -61,14 +58,12 @@ #define ARM_ISB() arm_isb(15) #define ARM_DMB() arm_dmb(15) -/************************************************************************************ - * Inline Functions - ************************************************************************************/ - -#ifndef __ASSEMBLY__ +/**************************************************************************** + * Public Functions + ****************************************************************************/ /**************************************************************************** - * Name: arch_invalidate_dcache + * Name: up_invalidate_dcache * * Description: * Invalidate the data cache within the specified region; we will be @@ -89,14 +84,14 @@ * ****************************************************************************/ -static inline void arch_invalidate_dcache(uintptr_t start, uintptr_t end) +void up_invalidate_dcache(uintptr_t start, uintptr_t end) { cp15_invalidate_dcache(start, end); l2cc_invalidate(start, end); } /**************************************************************************** - * Name: arch_invalidate_dcache_all + * Name: up_invalidate_dcache_all * * Description: * Invalidate the entire contents of D cache. @@ -112,7 +107,7 @@ static inline void arch_invalidate_dcache(uintptr_t start, uintptr_t end) * ****************************************************************************/ -static inline void arch_invalidate_dcache_all(void) +void up_invalidate_dcache_all(void) { #ifdef CONFIG_ARCH_L2CACHE irqstate_t flags = enter_critical_section(); @@ -124,11 +119,12 @@ static inline void arch_invalidate_dcache_all(void) #endif } -/************************************************************************************ - * Name: arch_invalidate_icache +/**************************************************************************** + * Name: up_invalidate_icache_all * * Description: - * Invalidate all instruction caches to PoU, also flushes branch target cache + * Invalidate all instruction caches to PoU, also flushes branch target + * cache * * Input Parameters: * None @@ -136,12 +132,15 @@ static inline void arch_invalidate_dcache_all(void) * Returned Value: * None * - ************************************************************************************/ + ****************************************************************************/ -#define arch_invalidate_icache() cp15_invalidate_icache() +void up_invalidate_icache_all(void) +{ + cp15_invalidate_icache(); +} /**************************************************************************** - * Name: arch_clean_dcache + * Name: up_clean_dcache * * Description: * Clean the data cache within the specified region by flushing the @@ -161,14 +160,14 @@ static inline void arch_invalidate_dcache_all(void) * ****************************************************************************/ -static inline void arch_clean_dcache(uintptr_t start, uintptr_t end) +void up_clean_dcache(uintptr_t start, uintptr_t end) { cp15_clean_dcache(start, end); l2cc_clean(start, end); } /**************************************************************************** - * Name: arch_flush_dcache + * Name: up_flush_dcache * * Description: * Flush the data cache within the specified region by cleaning and @@ -188,14 +187,14 @@ static inline void arch_clean_dcache(uintptr_t start, uintptr_t end) * ****************************************************************************/ -static inline void arch_flush_dcache(uintptr_t start, uintptr_t end) +void up_flush_dcache(uintptr_t start, uintptr_t end) { cp15_flush_dcache(start, end); l2cc_flush(start, end); } /**************************************************************************** - * Name: arch_enable_icache + * Name: up_enable_icache * * Description: * Enable the I-Cache @@ -208,76 +207,100 @@ static inline void arch_flush_dcache(uintptr_t start, uintptr_t end) * ****************************************************************************/ -static inline void arch_enable_icache(void) +void up_enable_icache(void) { -#ifdef CONFIG_ARMV7R_ICACHE - uint32_t regval; - - ARM_DSB(); - ARM_ISB(); - - /* Enable the I-Cache */ - - regval = cp15_rdsctlr(); - if ((regval & SCTLR_I) == 0) - { - cp15_wrsctlr(regval | SCTLR_I); - } - - ARM_DSB(); - ARM_ISB(); -#endif + cp15_enable_icache(); } /**************************************************************************** -* Name: arch_enable_dcache -* -* Description: -* Enable the D-Cache -* -* Input Parameters: -* None -* -* Returned Value: -* None -* -****************************************************************************/ - -static inline void arch_enable_dcache(void) -{ -#ifdef CONFIG_ARMV7R_DCACHE - uint32_t regval; - - /* Enable the D-Cache */ - - regval = cp15_rdsctlr(); - if ((regval & SCTLR_C) == 0) - { - cp15_wrsctlr(regval | SCTLR_C); - } -#endif -} - -/**************************************************************************** - * Public Data + * Name: up_disable_icache + * + * Description: + * Disable the I-Cache + * + * Input Parameters: + * None + * + * Returned Value: + * None + * ****************************************************************************/ -#ifdef __cplusplus -#define EXTERN extern "C" -extern "C" +void up_disable_icache(void) { -#else -#define EXTERN extern -#endif + cp15_disable_icache(); +} /**************************************************************************** - * Public Function Prototypes + * Name: up_enable_dcache + * + * Description: + * Enable the D-Cache + * + * Input Parameters: + * None + * + * Returned Value: + * None + * ****************************************************************************/ -#undef EXTERN -#ifdef __cplusplus +void up_enable_dcache(void) +{ + cp15_enable_dcache(); + l2cc_enable(); } -#endif -#endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_ARMV7_R_CACHE_H */ +/**************************************************************************** + * Name: up_disable_dcache + * + * Description: + * Disable the D-Cache + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void up_disable_dcache(void) +{ + cp15_disable_dcache(); + l2cc_disable(); +} + +/**************************************************************************** + * Name: up_coherent_dcache + * + * Description: + * Ensure that the I and D caches are coherent within specified region + * by cleaning the D cache (i.e., flushing the D cache contents to memory + * and invalidating the I cache. This is typically used when code has been + * written to a memory region, and will be executed. + * + * Input Parameters: + * addr - virtual start address of region + * len - Size of the address region in bytes + * + * Returned Value: + * None + * + ****************************************************************************/ + +void up_coherent_dcache(uintptr_t addr, size_t len) +{ + if (len > 0) + { + /* Perform the operation on the L1 cache */ + + cp15_coherent_dcache(addr, addr + len); + +#ifdef CONFIG_ARCH_L2CACHE + /* If we have an L2 cache, then there more things that need to done */ + +# warning This is insufficient +#endif + } +} diff --git a/arch/arm/src/armv7-a/arm_coherent_dcache.c b/arch/arm/src/armv7-a/arm_coherent_dcache.c deleted file mode 100644 index c9552093ef..0000000000 --- a/arch/arm/src/armv7-a/arm_coherent_dcache.c +++ /dev/null @@ -1,85 +0,0 @@ -/**************************************************************************** - * arch/arm/src/armv7-a/up_coherent_dcache.c - * - * Copyright (C) 2014 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include "cp15_cacheops.h" - -#include - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: up_coherent_dcache - * - * Description: - * Ensure that the I and D caches are coherent within specified region - * by cleaning the D cache (i.e., flushing the D cache contents to memory - * and invalidating the I cache. This is typically used when code has been - * written to a memory region, and will be executed. - * - * Input Parameters: - * addr - virtual start address of region - * len - Size of the address region in bytes - * - * Returned Value: - * None - * - ****************************************************************************/ - -void up_coherent_dcache(uintptr_t addr, size_t len) -{ - if (len > 0) - { - /* Perform the operation on the L1 cache */ - - cp15_coherent_dcache(addr, addr + len - 1); - -#ifdef CONFIG_ARCH_L2CACHE - /* If we have an L2 cache, then there more things that need to done */ - -# warning This is insufficient -#endif - } -} diff --git a/arch/arm/src/armv7-a/arm_mmu.c b/arch/arm/src/armv7-a/arm_mmu.c index 133ddc8af6..95461b8597 100644 --- a/arch/arm/src/armv7-a/arm_mmu.c +++ b/arch/arm/src/armv7-a/arm_mmu.c @@ -41,7 +41,7 @@ #include -#include "cache.h" +#include "cp15_cacheops.h" #include "mmu.h" /**************************************************************************** diff --git a/arch/arm/src/armv7-a/arm_pgalloc.c b/arch/arm/src/armv7-a/arm_pgalloc.c index 514c623fe9..0377eb12cf 100644 --- a/arch/arm/src/armv7-a/arm_pgalloc.c +++ b/arch/arm/src/armv7-a/arm_pgalloc.c @@ -48,7 +48,6 @@ #include #include -#include "cache.h" #include "mmu.h" #include "pgalloc.h" @@ -105,8 +104,8 @@ static uintptr_t alloc_pgtable(void) * memory. */ - arch_flush_dcache((uintptr_t)l2table, - (uintptr_t)l2table + MM_PGSIZE); + up_flush_dcache((uintptr_t)l2table, + (uintptr_t)l2table + MM_PGSIZE); #ifndef CONFIG_ARCH_PGPOOL_MAPPING /* Restore the scratch section page table entry */ @@ -297,8 +296,8 @@ uintptr_t pgalloc(uintptr_t brkaddr, unsigned int npages) * memory. */ - arch_flush_dcache((uintptr_t)&l2table[index], - (uintptr_t)&l2table[index] + sizeof(uint32_t)); + up_flush_dcache((uintptr_t)&l2table[index], + (uintptr_t)&l2table[index] + sizeof(uint32_t)); #ifndef CONFIG_ARCH_PGPOOL_MAPPING /* Restore the scratch L1 page table entry */ diff --git a/arch/arm/src/armv7-a/arm_physpgaddr.c b/arch/arm/src/armv7-a/arm_physpgaddr.c index 0c753ab864..123b3df8a3 100644 --- a/arch/arm/src/armv7-a/arm_physpgaddr.c +++ b/arch/arm/src/armv7-a/arm_physpgaddr.c @@ -49,7 +49,6 @@ #include "chip.h" #include "mmu.h" -#include "cache.h" #include "pgalloc.h" @@ -115,8 +114,8 @@ uintptr_t arm_physpgaddr(uintptr_t vaddr) */ index = (vaddr & SECTION_MASK) >> MM_PGSHIFT; - arch_invalidate_dcache((uintptr_t)&l2table[index], - (uintptr_t)&l2table[index] + sizeof(uint32_t)); + up_invalidate_dcache((uintptr_t)&l2table[index], + (uintptr_t)&l2table[index] + sizeof(uint32_t)); /* Get the Level 2 page table entry corresponding to this virtual * address. Extract the physical address of the page containing diff --git a/arch/arm/src/armv7-a/arm_scu.c b/arch/arm/src/armv7-a/arm_scu.c index eedf179e73..99d4bc3c8b 100644 --- a/arch/arm/src/armv7-a/arm_scu.c +++ b/arch/arm/src/armv7-a/arm_scu.c @@ -44,7 +44,6 @@ #include "up_arch.h" #include "cp15_cacheops.h" #include "sctlr.h" -#include "cache.h" #include "scu.h" #ifdef CONFIG_SMP diff --git a/arch/arm/src/armv7-a/cp15_cacheops.h b/arch/arm/src/armv7-a/cp15_cacheops.h index ce38540793..dbe0bf201e 100644 --- a/arch/arm/src/armv7-a/cp15_cacheops.h +++ b/arch/arm/src/armv7-a/cp15_cacheops.h @@ -193,6 +193,26 @@ #ifdef __ASSEMBLY__ +/************************************************************************************ + * Name: cp15_enable_dcache + * + * Description: + * Enable L1 D Cache + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ************************************************************************************/ + + .macro cp15_enable_dcache, tmp + mrc p15, 0, \tmp, c1, c0, 0 /* Read SCTLR */ + orr \tmp, \tmp, #(0x1 << 2) /* Enable D cache */ + mcr p15, 0, \tmp, c1, c0, 0 /* Update the SCTLR */ + .endm + /************************************************************************************ * Name: cp15_disable_dcache * @@ -214,10 +234,10 @@ .endm /************************************************************************************ - * Name: cp15_disable_caches + * Name: cp15_enable_icache * * Description: - * Disable L1 Caches + * Enable L1 I Cache * * Input Parameters: * None @@ -227,10 +247,29 @@ * ************************************************************************************/ - .macro cp15_disable_caches, tmp + .macro cp15_enable_icache, tmp + mrc p15, 0, \tmp, c1, c0, 0 /* Read SCTLR */ + orr \tmp, \tmp, #(0x1 << 12) /* Enable I cache */ + mcr p15, 0, \tmp, c1, c0, 0 /* Update the SCTLR */ + .endm + +/************************************************************************************ + * Name: cp15_disable_icache + * + * Description: + * Disable L1 I Cache + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ************************************************************************************/ + + .macro cp15_disable_icache, tmp mrc p15, 0, \tmp, c1, c0, 0 /* Read SCTLR */ bic \tmp, \tmp, #(0x1 << 12) /* Disable I cache */ - bic \tmp, \tmp, #(0x1 << 2) /* Disable D cache */ mcr p15, 0, \tmp, c1, c0, 0 /* Update the SCTLR */ .endm @@ -481,11 +520,38 @@ #ifndef __ASSEMBLY__ +/************************************************************************************ + * Name: cp15_enable_dcache + * + * Description: + * Enable L1 D Cache + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ************************************************************************************/ + +static inline void cp15_enable_dcache(void) +{ + __asm__ __volatile__ + ( + "\tmrc p15, 0, r0, c1, c0, 0\n" /* Read SCTLR */ + "\torr r0, r0, #(1 << 2)\n" /* Enable D cache */ + "\tmcr p15, 0, r0, c1, c0, 0\n" /* Update the SCTLR */ + : + : + : "r0", "memory" + ); +} + /************************************************************************************ * Name: cp15_disable_dcache * * Description: - * Disable L1 Caches + * Disable L1 D Cache * * Input Parameters: * None @@ -509,10 +575,10 @@ static inline void cp15_disable_dcache(void) } /************************************************************************************ - * Name: cp15_disable_caches + * Name: cp15_enable_icache * * Description: - * Disable L1 Caches + * Enable L1 I Cache * * Input Parameters: * None @@ -522,13 +588,39 @@ static inline void cp15_disable_dcache(void) * ************************************************************************************/ -static inline void cp15_disable_caches(void) +static inline void cp15_enable_icache(void) +{ + __asm__ __volatile__ + ( + "\tmrc p15, 0, r0, c1, c0, 0\n" /* Read SCTLR */ + "\torr r0, r0, #(1 << 12)\n" /* Enable I cache */ + "\tmcr p15, 0, r0, c1, c0, 0\n" /* Update the SCTLR */ + : + : + : "r0", "memory" + ); +} + +/************************************************************************************ + * Name: cp15_disable_icache + * + * Description: + * Disable L1 I Cache + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ************************************************************************************/ + +static inline void cp15_disable_icache(void) { __asm__ __volatile__ ( "\tmrc p15, 0, r0, c1, c0, 0\n" /* Read SCTLR */ "\tbic r0, r0, #(1 << 12)\n" /* Disable I cache */ - "\tbic r0, r0, #(1 << 2)\n" /* Disable D cache */ "\tmcr p15, 0, r0, c1, c0, 0\n" /* Update the SCTLR */ : : diff --git a/arch/arm/src/armv7-m/Kconfig b/arch/arm/src/armv7-m/Kconfig index 37e64bb194..60f19c435a 100644 --- a/arch/arm/src/armv7-m/Kconfig +++ b/arch/arm/src/armv7-m/Kconfig @@ -89,11 +89,13 @@ config ARMV7M_ICACHE bool "Use I-Cache" default n depends on ARMV7M_HAVE_ICACHE + select ARCH_ICACHE config ARMV7M_DCACHE bool "Use D-Cache" default n depends on ARMV7M_HAVE_DCACHE + select ARCH_DCACHE config ARMV7M_DCACHE_WRITETHROUGH bool "D-Cache Write-Through" diff --git a/arch/arm/src/armv7-m/arch_clean_dcache.c b/arch/arm/src/armv7-m/arch_clean_dcache.c deleted file mode 100644 index 0c2828d2b5..0000000000 --- a/arch/arm/src/armv7-m/arch_clean_dcache.c +++ /dev/null @@ -1,149 +0,0 @@ -/**************************************************************************** - * arch/arm/src/armv7-m/arch_clean_dcache.c - * - * Copyright (C) 2015 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Some logic in this header file derives from the ARM CMSIS core_cm7.h - * header file which has a compatible 3-clause BSD license: - * - * Copyright (c) 2009 - 2014 ARM LIMITED. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name ARM, NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include "cache.h" - -#if defined(CONFIG_ARMV7M_DCACHE) && !defined(CONFIG_ARMV7M_DCACHE_WRITETHROUGH) - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: arch_clean_dcache - * - * Description: - * Clean the data cache within the specified region by flushing the - * contents of the data cache to memory. - * - * Input Parameters: - * start - virtual start address of region - * end - virtual end address of region + 1 - * - * Returned Value: - * None - * - * Assumptions: - * This operation is not atomic. This function assumes that the caller - * has exclusive access to the address range so that no harm is done if - * the operation is pre-empted. - * - ****************************************************************************/ - -void arch_clean_dcache(uintptr_t start, uintptr_t end) -{ - uint32_t ccsidr; - uint32_t smask; - uint32_t sshift; - uint32_t ways; - uint32_t wshift; - uint32_t ssize; - uint32_t set; - uint32_t sw; - - /* Get the characteristics of the D-Cache */ - - ccsidr = getreg32(NVIC_CCSIDR); - smask = CCSIDR_SETS(ccsidr); /* (Number of sets) - 1 */ - sshift = CCSIDR_LSSHIFT(ccsidr) + 4; /* log2(cache-line-size-in-bytes) */ - ways = CCSIDR_WAYS(ccsidr); /* (Number of ways) - 1 */ - - /* Calculate the bit offset for the way field in the DCCSW register by - * counting the number of leading zeroes. For example: - * - * Number of Value of ways Field - * Ways 'ways' Offset - * 2 1 31 - * 4 3 30 - * 8 7 29 - * ... - */ - - wshift = arm_clz(ways) & 0x1f; - - /* Clean the D-Cache over the range of addresses */ - - ssize = (1 << sshift); - start &= ~(ssize - 1); - ARM_DSB(); - - do - { - int32_t tmpways = ways; - - /* Isolate the cache line associated with this address. For example - * if the cache line size is 32 bytes and the cache size is 16KB, then - * - * sshift = 5 : Offset to the beginning of the set field - * smask = 0x007f : Mask of the set field - */ - - set = ((uint32_t)start >> sshift) & smask; - - /* Clean and invalidate each way for this cacheline */ - - do - { - sw = ((tmpways << wshift) | (set << sshift)); - putreg32(sw, NVIC_DCCSW); - } - while (tmpways--); - - /* Increment the address by the size of one cache line. */ - - start += ssize; - } - while (start < end); - - ARM_DSB(); - ARM_ISB(); -} - -#endif /* CONFIG_ARMV7M_DCACHE && !CONFIG_ARMV7M_DCACHE_WRITETHROUGH */ diff --git a/arch/arm/src/armv7-m/arch_clean_dcache_all.c b/arch/arm/src/armv7-m/arch_clean_dcache_all.c deleted file mode 100644 index 296780bee5..0000000000 --- a/arch/arm/src/armv7-m/arch_clean_dcache_all.c +++ /dev/null @@ -1,129 +0,0 @@ -/**************************************************************************** - * arch/arm/src/armv7-m/arch_clean_dcache_all.c - * - * Copyright (C) 2015 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Some logic in this header file derives from the ARM CMSIS core_cm7.h - * header file which has a compatible 3-clause BSD license: - * - * Copyright (c) 2009 - 2014 ARM LIMITED. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name ARM, NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include "cache.h" - -#if defined(CONFIG_ARMV7M_DCACHE) && !defined(CONFIG_ARMV7M_DCACHE_WRITETHROUGH) - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: arch_clean_dcache_all - * - * Description: - * Clean the entire data cache within the specified region by flushing the - * contents of the data cache to memory. - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - * Assumptions: - * This operation is not atomic. This function assumes that the caller - * has exclusive access to the address range so that no harm is done if - * the operation is pre-empted. - * - ****************************************************************************/ - -void arch_clean_dcache_all(void) -{ - uint32_t ccsidr; - uint32_t sshift; - uint32_t wshift; - uint32_t sw; - uint32_t sets; - uint32_t ways; - - /* Get the characteristics of the D-Cache */ - - ccsidr = getreg32(NVIC_CCSIDR); - sets = CCSIDR_SETS(ccsidr); /* (Number of sets) - 1 */ - sshift = CCSIDR_LSSHIFT(ccsidr) + 4; /* log2(cache-line-size-in-bytes) */ - ways = CCSIDR_WAYS(ccsidr); /* (Number of ways) - 1 */ - - /* Calculate the bit offset for the way field in the DCCSW register by - * counting the number of leading zeroes. For example: - * - * Number of Value of ways Field - * Ways 'ways' Offset - * 2 1 31 - * 4 3 30 - * 8 7 29 - * ... - */ - - wshift = arm_clz(ways) & 0x1f; - - ARM_DSB(); - - /* Clean the entire D-Cache */ - - do - { - int32_t tmpways = ways; - - do - { - sw = ((tmpways << wshift) | (sets << sshift)); - putreg32(sw, NVIC_DCCSW); - } - while (tmpways--); - } - while (sets--); - - ARM_DSB(); - ARM_ISB(); -} - -#endif /* CONFIG_ARMV7M_DCACHE && !CONFIG_ARMV7M_DCACHE_WRITETHROUGH */ diff --git a/arch/arm/src/armv7-m/arch_disable_dcache.c b/arch/arm/src/armv7-m/arch_disable_dcache.c deleted file mode 100644 index c21c8cb8f7..0000000000 --- a/arch/arm/src/armv7-m/arch_disable_dcache.c +++ /dev/null @@ -1,130 +0,0 @@ -/**************************************************************************** - * arch/arm/src/armv7-m/arch_disable_dcache.c - * - * Copyright (C) 2015 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Some logic in this header file derives from the ARM CMSIS core_cm7.h - * header file which has a compatible 3-clause BSD license: - * - * Copyright (c) 2009 - 2014 ARM LIMITED. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name ARM, NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include "cache.h" - -#ifdef CONFIG_ARMV7M_DCACHE - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: arch_disable_dcache - * - * Description: - * Disable the D-Cache - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ - -void arch_disable_dcache(void) -{ - uint32_t ccsidr; - uint32_t ccr; - uint32_t sshift; - uint32_t wshift; - uint32_t sw; - uint32_t sets; - uint32_t ways; - - /* Get the characteristics of the D-Cache */ - - ccsidr = getreg32(NVIC_CCSIDR); - sets = CCSIDR_SETS(ccsidr); /* (Number of sets) - 1 */ - sshift = CCSIDR_LSSHIFT(ccsidr) + 4; /* log2(cache-line-size-in-bytes) */ - ways = CCSIDR_WAYS(ccsidr); /* (Number of ways) - 1 */ - - /* Calculate the bit offset for the way field in the DCCISW register by - * counting the number of leading zeroes. For example: - * - * Number of Value of ways Field - * Ways 'ways' Offset - * 2 1 31 - * 4 3 30 - * 8 7 29 - * ... - */ - - wshift = arm_clz(ways) & 0x1f; - - ARM_DSB(); - - /* Disable the D-Cache */ - - ccr = getreg32(NVIC_CFGCON); - ccr &= ~NVIC_CFGCON_DC; - putreg32(ccr, NVIC_CFGCON); - - /* Clean and invalidate the entire D-Cache */ - - do - { - int32_t tmpways = ways; - - do - { - sw = ((tmpways << wshift) | (sets << sshift)); - putreg32(sw, NVIC_DCCISW); - } - while (tmpways--); - } - while (sets--); - - ARM_DSB(); - ARM_ISB(); -} - -#endif /* CONFIG_ARMV7M_DCACHE */ diff --git a/arch/arm/src/armv7-m/arch_enable_dcache.c b/arch/arm/src/armv7-m/arch_enable_dcache.c deleted file mode 100644 index 9c1abe47c6..0000000000 --- a/arch/arm/src/armv7-m/arch_enable_dcache.c +++ /dev/null @@ -1,131 +0,0 @@ -/**************************************************************************** - * arch/arm/src/armv7-m/arch_enable_dcache.c - * - * Copyright (C) 2015 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Some logic in this header file derives from the ARM CMSIS core_cm7.h - * header file which has a compatible 3-clause BSD license: - * - * Copyright (c) 2009 - 2014 ARM LIMITED. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name ARM, NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include "cache.h" - -#ifdef CONFIG_ARMV7M_DCACHE - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: arch_enable_dcache - * - * Description: - * Enable the D-Cache - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ - -void arch_enable_dcache(void) -{ - uint32_t ccsidr; - uint32_t ccr; - uint32_t sshift; - uint32_t wshift; - uint32_t sw; - uint32_t sets; - uint32_t ways; - - /* Get the characteristics of the D-Cache */ - - ccsidr = getreg32(NVIC_CCSIDR); - sets = CCSIDR_SETS(ccsidr); /* (Number of sets) - 1 */ - sshift = CCSIDR_LSSHIFT(ccsidr) + 4; /* log2(cache-line-size-in-bytes) */ - ways = CCSIDR_WAYS(ccsidr); /* (Number of ways) - 1 */ - - /* Calculate the bit offset for the way field in the DCISW register by - * counting the number of leading zeroes. For example: - * - * Number of Value of ways Field - * Ways 'ways' Offset - * 2 1 31 - * 4 3 30 - * 8 7 29 - * ... - */ - - wshift = arm_clz(ways) & 0x1f; - - /* Invalidate the entire D-Cache */ - - ARM_DSB(); - do - { - int32_t tmpways = ways; - - do - { - sw = ((tmpways << wshift) | (sets << sshift)); - putreg32(sw, NVIC_DCISW); - } - while (tmpways--); - } - while (sets--); - - ARM_DSB(); - - /* Enable the D-Cache */ - - ccr = getreg32(NVIC_CFGCON); - ccr |= NVIC_CFGCON_DC; - putreg32(ccr, NVIC_CFGCON); - - ARM_DSB(); - ARM_ISB(); -} - -#endif /* CONFIG_ARMV7M_DCACHE */ diff --git a/arch/arm/src/armv7-m/arch_flush_dcache.c b/arch/arm/src/armv7-m/arch_flush_dcache.c deleted file mode 100644 index 28ab2a00a0..0000000000 --- a/arch/arm/src/armv7-m/arch_flush_dcache.c +++ /dev/null @@ -1,149 +0,0 @@ -/**************************************************************************** - * arch/arm/src/armv7-m/arch_flush_dcache.c - * - * Copyright (C) 2015 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Some logic in this header file derives from the ARM CMSIS core_cm7.h - * header file which has a compatible 3-clause BSD license: - * - * Copyright (c) 2009 - 2014 ARM LIMITED. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name ARM, NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include "cache.h" - -#if defined(CONFIG_ARMV7M_DCACHE) && !defined(CONFIG_ARMV7M_DCACHE_WRITETHROUGH) - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: arch_flush_dcache - * - * Description: - * Flush the data cache within the specified region by cleaning and - * invalidating the D cache. - * - * Input Parameters: - * start - virtual start address of region - * end - virtual end address of region + 1 - * - * Returned Value: - * None - * - * Assumptions: - * This operation is not atomic. This function assumes that the caller - * has exclusive access to the address range so that no harm is done if - * the operation is pre-empted. - * - ****************************************************************************/ - -void arch_flush_dcache(uintptr_t start, uintptr_t end) -{ - uint32_t ccsidr; - uint32_t smask; - uint32_t sshift; - uint32_t ways; - uint32_t wshift; - uint32_t ssize; - uint32_t set; - uint32_t sw; - - /* Get the characteristics of the D-Cache */ - - ccsidr = getreg32(NVIC_CCSIDR); - smask = CCSIDR_SETS(ccsidr); /* (Number of sets) - 1 */ - sshift = CCSIDR_LSSHIFT(ccsidr) + 4; /* log2(cache-line-size-in-bytes) */ - ways = CCSIDR_WAYS(ccsidr); /* (Number of ways) - 1 */ - - /* Calculate the bit offset for the way field in the DCCISW register by - * counting the number of leading zeroes. For example: - * - * Number of Value of ways Field - * Ways 'ways' Offset - * 2 1 31 - * 4 3 30 - * 8 7 29 - * ... - */ - - wshift = arm_clz(ways) & 0x1f; - - /* Clean and invalidate the D-Cache over the range of addresses */ - - ssize = (1 << sshift); - start &= ~(ssize - 1); - ARM_DSB(); - - do - { - int32_t tmpways = ways; - - /* Isolate the cache line associated with this address. For example - * if the cache line size is 32 bytes and the cache size is 16KB, then - * - * sshift = 5 : Offset to the beginning of the set field - * smask = 0x007f : Mask of the set field - */ - - set = ((uint32_t)start >> sshift) & smask; - - /* Clean and invalidate each way for this cacheline */ - - do - { - sw = ((tmpways << wshift) | (set << sshift)); - putreg32(sw, NVIC_DCCISW); - } - while (tmpways--); - - /* Increment the address by the size of one cache line. */ - - start += ssize; - } - while (start < end); - - ARM_DSB(); - ARM_ISB(); -} - -#endif /* CONFIG_ARMV7M_DCACHE && !CONFIG_ARMV7M_DCACHE_WRITETHROUGH */ diff --git a/arch/arm/src/armv7-m/arch_flush_dcache_all.c b/arch/arm/src/armv7-m/arch_flush_dcache_all.c deleted file mode 100644 index 33f80b85ba..0000000000 --- a/arch/arm/src/armv7-m/arch_flush_dcache_all.c +++ /dev/null @@ -1,128 +0,0 @@ -/**************************************************************************** - * arch/arm/src/armv7-m/arch_flush_dcache_all.c - * - * Copyright (C) 2015 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Some logic in this header file derives from the ARM CMSIS core_cm7.h - * header file which has a compatible 3-clause BSD license: - * - * Copyright (c) 2009 - 2014 ARM LIMITED. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name ARM, NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include "cache.h" - -#if defined(CONFIG_ARMV7M_DCACHE) && !defined(CONFIG_ARMV7M_DCACHE_WRITETHROUGH) - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: arch_flush_dcache_all - * - * Description: - * Flush the entire data cache by cleaning and invalidating the D cache. - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - * Assumptions: - * This operation is not atomic. This function assumes that the caller - * has exclusive access to the address range so that no harm is done if - * the operation is pre-empted. - * - ****************************************************************************/ - -void arch_flush_dcache_all(void) -{ - uint32_t ccsidr; - uint32_t sshift; - uint32_t wshift; - uint32_t sw; - uint32_t sets; - uint32_t ways; - - /* Get the characteristics of the D-Cache */ - - ccsidr = getreg32(NVIC_CCSIDR); - sets = CCSIDR_SETS(ccsidr); /* (Number of sets) - 1 */ - sshift = CCSIDR_LSSHIFT(ccsidr) + 4; /* log2(cache-line-size-in-bytes) */ - ways = CCSIDR_WAYS(ccsidr); /* (Number of ways) - 1 */ - - /* Calculate the bit offset for the way field in the DCCISW register by - * counting the number of leading zeroes. For example: - * - * Number of Value of ways Field - * Ways 'ways' Offset - * 2 1 31 - * 4 3 30 - * 8 7 29 - * ... - */ - - wshift = arm_clz(ways) & 0x1f; - - ARM_DSB(); - - /* Clean and invalidate the entire D-Cache */ - - do - { - int32_t tmpways = ways; - - do - { - sw = ((tmpways << wshift) | (sets << sshift)); - putreg32(sw, NVIC_DCCISW); - } - while (tmpways--); - } - while (sets--); - - ARM_DSB(); - ARM_ISB(); -} - -#endif /* CONFIG_ARMV7M_DCACHE && !CONFIG_ARMV7M_DCACHE_WRITETHROUGH */ diff --git a/arch/arm/src/armv7-m/arch_invalidate_dcache.c b/arch/arm/src/armv7-m/arch_invalidate_dcache.c deleted file mode 100644 index 4d8b600a3f..0000000000 --- a/arch/arm/src/armv7-m/arch_invalidate_dcache.c +++ /dev/null @@ -1,217 +0,0 @@ -/**************************************************************************** - * arch/arm/src/armv7-m/arch_invalidate_dcache.c - * - * Copyright (C) 2015, 2018 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * Bob Feretich - * - * Some logic in this header file derives from the ARM CMSIS core_cm7.h - * header file which has a compatible 3-clause BSD license: - * - * Copyright (c) 2009 - 2014 ARM LIMITED. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name ARM, NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include "cache.h" - -#ifdef CONFIG_ARMV7M_DCACHE - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: arch_invalidate_dcache - * - * Description: - * Invalidate the data cache within the specified region; we will be - * performing a DMA operation in this region and we want to purge old data - * in the cache. Note that this function invalidates all cache ways - * in sets that could be associated with the address range, regardless of - * whether the address range is contained in the cache or not. - * - * Input Parameters: - * start - virtual start address of region - * end - virtual end address of region + 1 - * - * Returned Value: - * None - * - * Assumptions: - * This operation is not atomic. This function assumes that the caller - * has exclusive access to the address range so that no harm is done if - * the operation is pre-empted. - * - ****************************************************************************/ - -void arch_invalidate_dcache(uintptr_t start, uintptr_t end) -{ - uint32_t ccsidr; - uint32_t smask; - uint32_t sshift; - uint32_t ways; - uint32_t wshift; - uint32_t ssize; - uint32_t set; - uint32_t sw; - - /* Get the characteristics of the D-Cache */ - - ccsidr = getreg32(NVIC_CCSIDR); - smask = CCSIDR_SETS(ccsidr); /* (Number of sets) - 1 */ - sshift = CCSIDR_LSSHIFT(ccsidr) + 4; /* log2(cache-line-size-in-bytes) */ - ways = CCSIDR_WAYS(ccsidr); /* (Number of ways) - 1 */ - - /* Calculate the bit offset for the way field in the DCISW register by - * counting the number of leading zeroes. For example: - * - * Number of Value of ways Field - * Ways 'ways' Offset - * 2 1 31 - * 4 3 30 - * 8 7 29 - * ... - */ - - wshift = arm_clz(ways) & 0x1f; - - /* Invalidate the D-Cache over the range of addresses */ - - ssize = (1 << sshift); - start &= ~(ssize - 1); - ARM_DSB(); - - do - { - int32_t tmpways = ways; - - /* Isolate the cache line associated with this address. For example - * if the cache line size is 32 bytes and the cache size is 16KB, then - * - * sshift = 5 : Offset to the beginning of the set field - * smask = 0x007f : Mask of the set field - */ - - set = ((uint32_t)start >> sshift) & smask; - - /* Clean and invalidate each way for this cacheline */ - - do - { - sw = ((tmpways << wshift) | (set << sshift)); - putreg32(sw, NVIC_DCISW); - } - while (tmpways--); - - /* Increment the address by the size of one cache line. */ - - start += ssize; - } - while (start < end); - - ARM_DSB(); - ARM_ISB(); -} - -/**************************************************************************** - * Name: arch_invalidate_dcache_by_addr - * - * Description: - * Invalidate the data cache within the specified region; we will be - * performing a DMA operation in this region and we want to purge old data - * in the cache. Note that this function only invalidates cache sets that - * contain data from this address range. - * - * Input Parameters: - * start - virtual start address of region - * end - virtual end address of region + 1 - * - * Returned Value: - * None - * - * Assumptions: - * This operation is not atomic. This function assumes that the caller - * has exclusive access to the address range so that no harm is done if - * the operation is pre-empted. - * - ****************************************************************************/ - -void arch_invalidate_dcache_by_addr(uintptr_t start, uintptr_t end) -{ - uint32_t ccsidr; - uint32_t sshift; - uint32_t ssize; - - /* Get the characteristics of the D-Cache */ - - ccsidr = getreg32(NVIC_CCSIDR); - sshift = CCSIDR_LSSHIFT(ccsidr) + 4; /* log2(cache-line-size-in-bytes) */ - - /* Invalidate the D-Cache containing this range of addresses */ - - ssize = (1 << sshift); - - /* Round down the start address to the nearest cache line boundary. - * - * sshift = 5 : Offset to the beginning of the set field - * (ssize - 1) = 0x007f : Mask of the set field - */ - - start &= ~(ssize - 1); - ARM_DSB(); - - do - { - /* The below store causes the cache to check its directory and - * determine if this address is contained in the cache. If so, it - * invalidate that cache line. Only the cache way containing the - * address is invalidated. If the address is not in the cache, then - * nothing is invalidated. - */ - - putreg32(start, NVIC_DCIMVAC); - - /* Increment the address by the size of one cache line. */ - - start += ssize; - } - while (start < end); - - ARM_DSB(); - ARM_ISB(); -} - -#endif /* CONFIG_ARMV7M_DCACHE */ diff --git a/arch/arm/src/armv7-m/arch_invalidate_dcache_all.c b/arch/arm/src/armv7-m/arch_invalidate_dcache_all.c deleted file mode 100644 index 380d7d5015..0000000000 --- a/arch/arm/src/armv7-m/arch_invalidate_dcache_all.c +++ /dev/null @@ -1,123 +0,0 @@ -/**************************************************************************** - * arch/arm/src/armv7-m/arch_invalidate_dcache_all.c - * - * Copyright (C) 2015 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Some logic in this header file derives from the ARM CMSIS core_cm7.h - * header file which has a compatible 3-clause BSD license: - * - * Copyright (c) 2009 - 2014 ARM LIMITED. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name ARM, NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include "cache.h" - -#ifdef CONFIG_ARMV7M_DCACHE - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: arch_invalidate_dcache_all - * - * Description: - * Invalidate the entire contents of D cache. - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ - -void arch_invalidate_dcache_all(void) -{ - uint32_t ccsidr; - uint32_t sshift; - uint32_t wshift; - uint32_t sw; - uint32_t sets; - uint32_t ways; - - /* Get the characteristics of the D-Cache */ - - ccsidr = getreg32(NVIC_CCSIDR); - sets = CCSIDR_SETS(ccsidr); /* (Number of sets) - 1 */ - sshift = CCSIDR_LSSHIFT(ccsidr) + 4; /* log2(cache-line-size-in-bytes) */ - ways = CCSIDR_WAYS(ccsidr); /* (Number of ways) - 1 */ - - /* Calculate the bit offset for the way field in the DCISW register by - * counting the number of leading zeroes. For example: - * - * Number of Value of ways Field - * Ways 'ways' Offset - * 2 1 31 - * 4 3 30 - * 8 7 29 - * ... - */ - - wshift = arm_clz(ways) & 0x1f; - - ARM_DSB(); - - /* Invalidate the entire D-Cache */ - - do - { - int32_t tmpways = ways; - - do - { - sw = ((tmpways << wshift) | (sets << sshift)); - putreg32(sw, NVIC_DCISW); - } - while (tmpways--); - } - while (sets--); - - ARM_DSB(); - ARM_ISB(); -} - -#endif /* CONFIG_ARMV7M_DCACHE */ diff --git a/arch/arm/src/armv7-m/cache.h b/arch/arm/src/armv7-m/cache.h deleted file mode 100644 index 22897489fe..0000000000 --- a/arch/arm/src/armv7-m/cache.h +++ /dev/null @@ -1,507 +0,0 @@ -/**************************************************************************** - * arch/arm/src/armv7-m/cache.h - * - * Copyright (C) 2015, 2018 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Some logic in this header file derives from the ARM CMSIS core_cm7.h - * header file which has a compatible 3-clause BSD license: - * - * Copyright (c) 2009 - 2014 ARM LIMITED. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name ARM, NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_ARMV7_M_CACHE_H -#define __ARCH_ARM_SRC_ARMV7_M_CACHE_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include "up_arch.h" -#include "nvic.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Cache Size ID (CCSIDR) register macros used by inline functions - * Given the value of the CCSIDR reginer (n): - * - * CCSIDR_WAYS - Returns the (number of ways) - 1 - * CCSIDR_SETS - Returns the (number of sets) - 1 - * CCSIDR_LSSHIFT - Returns log2(cache line size in words) - 2 - * Eg. 0 -> 4 words - * 1 -> 8 words - * ... - */ - -#define CCSIDR_WAYS(n) \ - (((n) & NVIC_CCSIDR_ASSOCIATIVITY_MASK) >> NVIC_CCSIDR_ASSOCIATIVITY_SHIFT) -#define CCSIDR_SETS(n) \ - (((n) & NVIC_CCSIDR_NUMSETS_MASK) >> NVIC_CCSIDR_NUMSETS_SHIFT) -#define CCSIDR_LSSHIFT(n) \ - (((n) & NVIC_CCSIDR_LINESIZE_MASK) >> NVIC_CCSIDR_LINESIZE_SHIFT) - -/* intrinsics are used in these inline functions */ - -#define arm_isb(n) __asm__ __volatile__ ("isb " #n : : : "memory") -#define arm_dsb(n) __asm__ __volatile__ ("dsb " #n : : : "memory") -#define arm_dmb(n) __asm__ __volatile__ ("dmb " #n : : : "memory") - -#define ARM_DSB() arm_dsb(15) -#define ARM_ISB() arm_isb(15) -#define ARM_DMB() arm_dmb(15) - -/**************************************************************************** - * Inline Functions - ****************************************************************************/ - -#ifndef __ASSEMBLY__ - -/**************************************************************************** - * Name: arm_clz - * - * Description: - * Access to CLZ instructions - * - * Input Parameters: - * value - The value to perform the CLZ operation on - * - * Returned Value: - * None - * - ****************************************************************************/ - -static inline uint32_t arm_clz(unsigned int value) -{ - uint32_t ret; - - __asm__ __volatile__ ("clz %0, %1" : "=r"(ret) : "r"(value)); - return ret; -} - -/**************************************************************************** - * Name: arch_enable_icache - * - * Description: - * Enable the I-Cache - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ - -static inline void arch_enable_icache(void) -{ -#ifdef CONFIG_ARMV7M_ICACHE - uint32_t regval; - - ARM_DSB(); - ARM_ISB(); - - /* Invalidate the entire I-Cache */ - - putreg32(0, NVIC_ICIALLU); - - /* Enable the I-Cache */ - - regval = getreg32(NVIC_CFGCON); - regval |= NVIC_CFGCON_IC; - putreg32(regval, NVIC_CFGCON); - - ARM_DSB(); - ARM_ISB(); -#endif -} - -/**************************************************************************** - * Name: arch_disable_icache - * - * Description: - * Disable the I-Cache - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ - -static inline void arch_disable_icache(void) -{ -#ifdef CONFIG_ARMV7M_ICACHE - uint32_t regval; - - ARM_DSB(); - ARM_ISB(); - - /* Disable the I-Cache */ - - regval = getreg32(NVIC_CFGCON); - regval &= ~NVIC_CFGCON_IC; - putreg32(regval, NVIC_CFGCON); - - /* Invalidate the entire I-Cache */ - - putreg32(0, NVIC_ICIALLU); - - ARM_DSB(); - ARM_ISB(); -#endif -} - -/**************************************************************************** - * Name: arch_invalidate_icache_all - * - * Description: - * Invalidate the entire contents of I cache. - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ - -static inline void arch_invalidate_icache_all(void) -{ -#ifdef CONFIG_ARMV7M_ICACHE - ARM_DSB(); - ARM_ISB(); - - /* Invalidate the entire I-Cache */ - - putreg32(0, NVIC_ICIALLU); - - ARM_DSB(); - ARM_ISB(); -#endif -} - -/**************************************************************************** - * Name: arch_dcache_writethrough - * - * Description: - * Configure the D-Cache for Write-Through operation. - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ - -#if defined(CONFIG_ARMV7M_DCACHE) && defined(CONFIG_ARMV7M_DCACHE_WRITETHROUGH) -static inline void arch_dcache_writethrough(void) -{ - uint32_t regval = getreg32(NVIC_CACR); - regval |= NVIC_CACR_FORCEWT; - putreg32(regval, NVIC_CACR); -} -#else -# define arch_dcache_writethrough() -#endif - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -#ifdef __cplusplus -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - - /**************************************************************************** - * Name: arch_enable_dcache - * - * Description: - * Enable the D-Cache - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifdef CONFIG_ARMV7M_DCACHE -void arch_enable_dcache(void); -#else -# define arch_enable_dcache() -#endif - -/**************************************************************************** - * Name: arch_disable_dcache - * - * Description: - * Disable the D-Cache - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifdef CONFIG_ARMV7M_DCACHE -void arch_disable_dcache(void); -#else -# define arch_disable_dcache() -#endif - -/**************************************************************************** - * Name: arch_invalidate_dcache - * - * Description: - * Invalidate the data cache within the specified region; we will be - * performing a DMA operation in this region and we want to purge old data - * in the cache. Note that this function invalidates all cache ways - * in sets that could be associated with the address range, regardless of - * whether the address range is contained in the cache or not. - * - * Input Parameters: - * start - virtual start address of region - * end - virtual end address of region + 1 - * - * Returned Value: - * None - * - * Assumptions: - * This operation is not atomic. This function assumes that the caller - * has exclusive access to the address range so that no harm is done if - * the operation is pre-empted. - * - ****************************************************************************/ - -#ifdef CONFIG_ARMV7M_DCACHE -void arch_invalidate_dcache(uintptr_t start, uintptr_t end); -#else -# define arch_invalidate_dcache(s,e) -#endif - -/**************************************************************************** - * Name: arch_invalidate_dcache_by_addr - * - * Description: - * Invalidate the data cache within the specified region; we will be - * performing a DMA operation in this region and we want to purge old data - * in the cache. Note that this function only invalidates cache sets that - * contain data from this address range. - * - * Input Parameters: - * start - virtual start address of region - * end - virtual end address of region + 1 - * - * Returned Value: - * None - * - * Assumptions: - * This operation is not atomic. This function assumes that the caller - * has exclusive access to the address range so that no harm is done if - * the operation is pre-empted. - * - ****************************************************************************/ - -#ifdef CONFIG_ARMV7M_DCACHE -void arch_invalidate_dcache_by_addr(uintptr_t start, uintptr_t end); -#else -# define arch_invalidate_dcache_by_addr(s,e) -#endif - -/**************************************************************************** - * Name: arch_invalidate_dcache_all - * - * Description: - * Invalidate the entire contents of D cache. - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifdef CONFIG_ARMV7M_DCACHE -void arch_invalidate_dcache_all(void); -#else -# define arch_invalidate_dcache_all() -#endif - -/**************************************************************************** - * Name: arch_clean_dcache - * - * Description: - * Clean the data cache within the specified region by flushing the - * contents of the data cache to memory. - * - * NOTE: This operation is un-necessary if the DCACHE is configured in - * write-through mode. - * - * Input Parameters: - * start - virtual start address of region - * end - virtual end address of region + 1 - * - * Returned Value: - * None - * - * Assumptions: - * This operation is not atomic. This function assumes that the caller - * has exclusive access to the address range so that no harm is done if - * the operation is pre-empted. - * - ****************************************************************************/ - -#if defined(CONFIG_ARMV7M_DCACHE) && !defined(CONFIG_ARMV7M_DCACHE_WRITETHROUGH) -void arch_clean_dcache(uintptr_t start, uintptr_t end); -#else -# define arch_clean_dcache(s,e) -#endif - -/**************************************************************************** - * Name: arch_clean_dcache_all - * - * Description: - * Clean the entire data cache within the specified region by flushing the - * contents of the data cache to memory. - * - * NOTE: This operation is un-necessary if the DCACHE is configured in - * write-through mode. - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - * Assumptions: - * This operation is not atomic. This function assumes that the caller - * has exclusive access to the address range so that no harm is done if - * the operation is pre-empted. - * - ****************************************************************************/ - -#if defined(CONFIG_ARMV7M_DCACHE) && !defined(CONFIG_ARMV7M_DCACHE_WRITETHROUGH) -void arch_clean_dcache_all(void); -#else -# define arch_clean_dcache_all() -#endif - -/**************************************************************************** - * Name: arch_flush_dcache - * - * Description: - * Flush the data cache within the specified region by cleaning and - * invalidating the D cache. - * - * NOTE: If DCACHE write-through is configured, then this operation is the - * same as arch_invalidate_cache(). - * - * Input Parameters: - * start - virtual start address of region - * end - virtual end address of region + 1 - * - * Returned Value: - * None - * - * Assumptions: - * This operation is not atomic. This function assumes that the caller - * has exclusive access to the address range so that no harm is done if - * the operation is pre-empted. - * - ****************************************************************************/ - -#ifdef CONFIG_ARMV7M_DCACHE -#ifdef CONFIG_ARMV7M_DCACHE_WRITETHROUGH -# define arch_flush_dcache(s,e) arch_invalidate_dcache(s,e) -#else -void arch_flush_dcache(uintptr_t start, uintptr_t end); -#endif -#else -# define arch_flush_dcache(s,e) -#endif - -/**************************************************************************** - * Name: arch_flush_dcache_all - * - * Description: - * Flush the entire data cache by cleaning and invalidating the D cache. - * - * NOTE: If DCACHE write-through is configured, then this operation is the - * same as arch_invalidate_cache_all(). - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - * Assumptions: - * This operation is not atomic. This function assumes that the caller - * has exclusive access to the address range so that no harm is done if - * the operation is pre-empted. - * - ****************************************************************************/ - -#ifdef CONFIG_ARMV7M_DCACHE -#ifdef CONFIG_ARMV7M_DCACHE_WRITETHROUGH -# define arch_flush_dcache_all() arch_invalidate_dcache_all() -#else -void arch_flush_dcache_all(void); -#endif -#else -# define arch_flush_dcache_all() -#endif - -#undef EXTERN -#ifdef __cplusplus -} -#endif -#endif /* __ASSEMBLY__ */ - -#endif /* __ARCH_ARM_SRC_ARMV7_M_CACHE_H */ diff --git a/arch/arm/src/armv7-m/mpu.h b/arch/arm/src/armv7-m/mpu.h index 4a5bab065b..9551d765b1 100644 --- a/arch/arm/src/armv7-m/mpu.h +++ b/arch/arm/src/armv7-m/mpu.h @@ -268,7 +268,6 @@ static inline void mpu_control(bool enable, bool hfnmiena, bool privdefena) * ****************************************************************************/ -#if defined(CONFIG_ARMV7M_HAVE_ICACHE) || defined(CONFIG_ARMV7M_DCACHE) static inline void mpu_priv_stronglyordered(uintptr_t base, size_t size) { unsigned int region = mpu_allocregion(); @@ -300,7 +299,6 @@ static inline void mpu_priv_stronglyordered(uintptr_t base, size_t size) MPU_RASR_AP_RWNO; /* P:RW U:None */ putreg32(regval, MPU_RASR); } -#endif /**************************************************************************** * Name: mpu_user_flash diff --git a/arch/arm/src/armv7-m/up_cache.c b/arch/arm/src/armv7-m/up_cache.c new file mode 100644 index 0000000000..a168d0f35d --- /dev/null +++ b/arch/arm/src/armv7-m/up_cache.c @@ -0,0 +1,832 @@ +/**************************************************************************** + * arch/arm/src/armv7-m/up_cache.c + * + * Copyright (C) 2015, 2018 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * Bob Feretich + * + * Some logic in this header file derives from the ARM CMSIS core_cm7.h + * header file which has a compatible 3-clause BSD license: + * + * Copyright (c) 2009 - 2014 ARM LIMITED. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name ARM, NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include "up_arch.h" +#include "nvic.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Cache Size ID (CCSIDR) register macros used by inline functions + * Given the value of the CCSIDR reginer (n): + * + * CCSIDR_WAYS - Returns the (number of ways) - 1 + * CCSIDR_SETS - Returns the (number of sets) - 1 + * CCSIDR_LSSHIFT - Returns log2(cache line size in words) - 2 + * Eg. 0 -> 4 words + * 1 -> 8 words + * ... + */ + +#define CCSIDR_WAYS(n) \ + (((n) & NVIC_CCSIDR_ASSOCIATIVITY_MASK) >> NVIC_CCSIDR_ASSOCIATIVITY_SHIFT) +#define CCSIDR_SETS(n) \ + (((n) & NVIC_CCSIDR_NUMSETS_MASK) >> NVIC_CCSIDR_NUMSETS_SHIFT) +#define CCSIDR_LSSHIFT(n) \ + (((n) & NVIC_CCSIDR_LINESIZE_MASK) >> NVIC_CCSIDR_LINESIZE_SHIFT) + +/* intrinsics are used in these inline functions */ + +#define arm_isb(n) __asm__ __volatile__ ("isb " #n : : : "memory") +#define arm_dsb(n) __asm__ __volatile__ ("dsb " #n : : : "memory") +#define arm_dmb(n) __asm__ __volatile__ ("dmb " #n : : : "memory") + +#define ARM_DSB() arm_dsb(15) +#define ARM_ISB() arm_isb(15) +#define ARM_DMB() arm_dmb(15) + +/**************************************************************************** + * Inline Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: arm_clz + * + * Description: + * Access to CLZ instructions + * + * Input Parameters: + * value - The value to perform the CLZ operation on + * + * Returned Value: + * None + * + ****************************************************************************/ + +static inline uint32_t arm_clz(unsigned int value) +{ + uint32_t ret; + + __asm__ __volatile__ ("clz %0, %1" : "=r"(ret) : "r"(value)); + return ret; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_enable_icache + * + * Description: + * Enable the I-Cache + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_ARMV7M_ICACHE +void up_enable_icache(void) +{ + uint32_t regval; + + ARM_DSB(); + ARM_ISB(); + + /* Invalidate the entire I-Cache */ + + putreg32(0, NVIC_ICIALLU); + + /* Enable the I-Cache */ + + regval = getreg32(NVIC_CFGCON); + regval |= NVIC_CFGCON_IC; + putreg32(regval, NVIC_CFGCON); + + ARM_DSB(); + ARM_ISB(); +} +#endif + +/**************************************************************************** + * Name: up_disable_icache + * + * Description: + * Disable the I-Cache + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_ARMV7M_ICACHE +void up_disable_icache(void) +{ + uint32_t regval; + + ARM_DSB(); + ARM_ISB(); + + /* Disable the I-Cache */ + + regval = getreg32(NVIC_CFGCON); + regval &= ~NVIC_CFGCON_IC; + putreg32(regval, NVIC_CFGCON); + + /* Invalidate the entire I-Cache */ + + putreg32(0, NVIC_ICIALLU); + + ARM_DSB(); + ARM_ISB(); +} +#endif + +/**************************************************************************** + * Name: up_invalidate_icache_all + * + * Description: + * Invalidate the entire contents of I cache. + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_ARMV7M_ICACHE +void up_invalidate_icache_all(void) +{ + ARM_DSB(); + ARM_ISB(); + + /* Invalidate the entire I-Cache */ + + putreg32(0, NVIC_ICIALLU); + + ARM_DSB(); + ARM_ISB(); +} +#endif + +/**************************************************************************** + * Name: up_enable_dcache + * + * Description: + * Enable the D-Cache + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_ARMV7M_DCACHE +void up_enable_dcache(void) +{ + uint32_t ccsidr; + uint32_t ccr; + uint32_t sshift; + uint32_t wshift; + uint32_t sw; + uint32_t sets; + uint32_t ways; + + /* Get the characteristics of the D-Cache */ + + ccsidr = getreg32(NVIC_CCSIDR); + sets = CCSIDR_SETS(ccsidr); /* (Number of sets) - 1 */ + sshift = CCSIDR_LSSHIFT(ccsidr) + 4; /* log2(cache-line-size-in-bytes) */ + ways = CCSIDR_WAYS(ccsidr); /* (Number of ways) - 1 */ + + /* Calculate the bit offset for the way field in the DCISW register by + * counting the number of leading zeroes. For example: + * + * Number of Value of ways Field + * Ways 'ways' Offset + * 2 1 31 + * 4 3 30 + * 8 7 29 + * ... + */ + + wshift = arm_clz(ways) & 0x1f; + + /* Invalidate the entire D-Cache */ + + ARM_DSB(); + do + { + int32_t tmpways = ways; + + do + { + sw = ((tmpways << wshift) | (sets << sshift)); + putreg32(sw, NVIC_DCISW); + } + while (tmpways--); + } + while (sets--); + + ARM_DSB(); + +#ifdef CONFIG_ARMV7M_DCACHE_WRITETHROUGH + ccr = getreg32(NVIC_CACR); + ccr |= NVIC_CACR_FORCEWT; + putreg32(ccr, NVIC_CACR); +#endif + + /* Enable the D-Cache */ + + ccr = getreg32(NVIC_CFGCON); + ccr |= NVIC_CFGCON_DC; + putreg32(ccr, NVIC_CFGCON); + + ARM_DSB(); + ARM_ISB(); +} +#endif /* CONFIG_ARMV7M_DCACHE */ + +/**************************************************************************** + * Name: up_disable_dcache + * + * Description: + * Disable the D-Cache + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_ARMV7M_DCACHE +void up_disable_dcache(void) +{ + uint32_t ccsidr; + uint32_t ccr; + uint32_t sshift; + uint32_t wshift; + uint32_t sw; + uint32_t sets; + uint32_t ways; + + /* Get the characteristics of the D-Cache */ + + ccsidr = getreg32(NVIC_CCSIDR); + sets = CCSIDR_SETS(ccsidr); /* (Number of sets) - 1 */ + sshift = CCSIDR_LSSHIFT(ccsidr) + 4; /* log2(cache-line-size-in-bytes) */ + ways = CCSIDR_WAYS(ccsidr); /* (Number of ways) - 1 */ + + /* Calculate the bit offset for the way field in the DCCISW register by + * counting the number of leading zeroes. For example: + * + * Number of Value of ways Field + * Ways 'ways' Offset + * 2 1 31 + * 4 3 30 + * 8 7 29 + * ... + */ + + wshift = arm_clz(ways) & 0x1f; + + ARM_DSB(); + + /* Disable the D-Cache */ + + ccr = getreg32(NVIC_CFGCON); + ccr &= ~NVIC_CFGCON_DC; + putreg32(ccr, NVIC_CFGCON); + + /* Clean and invalidate the entire D-Cache */ + + do + { + int32_t tmpways = ways; + + do + { + sw = ((tmpways << wshift) | (sets << sshift)); + putreg32(sw, NVIC_DCCISW); + } + while (tmpways--); + } + while (sets--); + + ARM_DSB(); + ARM_ISB(); +} +#endif /* CONFIG_ARMV7M_DCACHE */ + +/**************************************************************************** + * Name: up_invalidate_dcache + * + * Description: + * Invalidate the data cache within the specified region; we will be + * performing a DMA operation in this region and we want to purge old data + * in the cache. Note that this function invalidates all cache ways + * in sets that could be associated with the address range, regardless of + * whether the address range is contained in the cache or not. + * + * Input Parameters: + * start - virtual start address of region + * end - virtual end address of region + 1 + * + * Returned Value: + * None + * + * Assumptions: + * This operation is not atomic. This function assumes that the caller + * has exclusive access to the address range so that no harm is done if + * the operation is pre-empted. + * + ****************************************************************************/ + +#ifdef CONFIG_ARMV7M_DCACHE +void up_invalidate_dcache(uintptr_t start, uintptr_t end) +{ + uint32_t ccsidr; + uint32_t sshift; + uint32_t ssize; + + /* Get the characteristics of the D-Cache */ + + ccsidr = getreg32(NVIC_CCSIDR); + sshift = CCSIDR_LSSHIFT(ccsidr) + 4; /* log2(cache-line-size-in-bytes) */ + + /* Invalidate the D-Cache containing this range of addresses */ + + ssize = (1 << sshift); + + /* Round down the start address to the nearest cache line boundary. + * + * sshift = 5 : Offset to the beginning of the set field + * (ssize - 1) = 0x007f : Mask of the set field + */ + + start &= ~(ssize - 1); + ARM_DSB(); + + do + { + /* The below store causes the cache to check its directory and + * determine if this address is contained in the cache. If so, it + * invalidate that cache line. Only the cache way containing the + * address is invalidated. If the address is not in the cache, then + * nothing is invalidated. + */ + + putreg32(start, NVIC_DCIMVAC); + + /* Increment the address by the size of one cache line. */ + + start += ssize; + } + while (start < end); + + ARM_DSB(); + ARM_ISB(); +} +#endif /* CONFIG_ARMV7M_DCACHE */ + +/**************************************************************************** + * Name: up_invalidate_dcache_all + * + * Description: + * Invalidate the entire contents of D cache. + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_ARMV7M_DCACHE +void up_invalidate_dcache_all(void) +{ + uint32_t ccsidr; + uint32_t sshift; + uint32_t wshift; + uint32_t sw; + uint32_t sets; + uint32_t ways; + + /* Get the characteristics of the D-Cache */ + + ccsidr = getreg32(NVIC_CCSIDR); + sets = CCSIDR_SETS(ccsidr); /* (Number of sets) - 1 */ + sshift = CCSIDR_LSSHIFT(ccsidr) + 4; /* log2(cache-line-size-in-bytes) */ + ways = CCSIDR_WAYS(ccsidr); /* (Number of ways) - 1 */ + + /* Calculate the bit offset for the way field in the DCISW register by + * counting the number of leading zeroes. For example: + * + * Number of Value of ways Field + * Ways 'ways' Offset + * 2 1 31 + * 4 3 30 + * 8 7 29 + * ... + */ + + wshift = arm_clz(ways) & 0x1f; + + ARM_DSB(); + + /* Invalidate the entire D-Cache */ + + do + { + int32_t tmpways = ways; + + do + { + sw = ((tmpways << wshift) | (sets << sshift)); + putreg32(sw, NVIC_DCISW); + } + while (tmpways--); + } + while (sets--); + + ARM_DSB(); + ARM_ISB(); +} +#endif /* CONFIG_ARMV7M_DCACHE */ + +/**************************************************************************** + * Name: up_clean_dcache + * + * Description: + * Clean the data cache within the specified region by flushing the + * contents of the data cache to memory. + * + * NOTE: This operation is un-necessary if the DCACHE is configured in + * write-through mode. + * + * Input Parameters: + * start - virtual start address of region + * end - virtual end address of region + 1 + * + * Returned Value: + * None + * + * Assumptions: + * This operation is not atomic. This function assumes that the caller + * has exclusive access to the address range so that no harm is done if + * the operation is pre-empted. + * + ****************************************************************************/ + +#ifdef CONFIG_ARMV7M_DCACHE +void up_clean_dcache(uintptr_t start, uintptr_t end) +{ +#ifndef CONFIG_ARMV7M_DCACHE_WRITETHROUGH + uint32_t ccsidr; + uint32_t sshift; + uint32_t ssize; + + /* Get the characteristics of the D-Cache */ + + ccsidr = getreg32(NVIC_CCSIDR); + sshift = CCSIDR_LSSHIFT(ccsidr) + 4; /* log2(cache-line-size-in-bytes) */ + + /* Clean the D-Cache over the range of addresses */ + + ssize = (1 << sshift); + start &= ~(ssize - 1); + ARM_DSB(); + + do + { + /* The below store causes the cache to check its directory and + * determine if this address is contained in the cache. If so, it + * clean that cache line. Only the cache way containing the + * address is invalidated. If the address is not in the cache, then + * nothing is invalidated. + */ + + putreg32(start, NVIC_DCCMVAC); + + /* Increment the address by the size of one cache line. */ + + start += ssize; + } + while (start < end); + + ARM_DSB(); + ARM_ISB(); +#endif /* !CONFIG_ARMV7M_DCACHE_WRITETHROUGH */ +} +#endif /* CONFIG_ARMV7M_DCACHE */ + +/**************************************************************************** + * Name: up_clean_dcache_all + * + * Description: + * Clean the entire data cache within the specified region by flushing the + * contents of the data cache to memory. + * + * NOTE: This operation is un-necessary if the DCACHE is configured in + * write-through mode. + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + * Assumptions: + * This operation is not atomic. This function assumes that the caller + * has exclusive access to the address range so that no harm is done if + * the operation is pre-empted. + * + ****************************************************************************/ + +#ifdef CONFIG_ARMV7M_DCACHE +void up_clean_dcache_all(void) +{ +#ifndef CONFIG_ARMV7M_DCACHE_WRITETHROUGH + uint32_t ccsidr; + uint32_t sshift; + uint32_t wshift; + uint32_t sw; + uint32_t sets; + uint32_t ways; + + /* Get the characteristics of the D-Cache */ + + ccsidr = getreg32(NVIC_CCSIDR); + sets = CCSIDR_SETS(ccsidr); /* (Number of sets) - 1 */ + sshift = CCSIDR_LSSHIFT(ccsidr) + 4; /* log2(cache-line-size-in-bytes) */ + ways = CCSIDR_WAYS(ccsidr); /* (Number of ways) - 1 */ + + /* Calculate the bit offset for the way field in the DCCSW register by + * counting the number of leading zeroes. For example: + * + * Number of Value of ways Field + * Ways 'ways' Offset + * 2 1 31 + * 4 3 30 + * 8 7 29 + * ... + */ + + wshift = arm_clz(ways) & 0x1f; + + ARM_DSB(); + + /* Clean the entire D-Cache */ + + do + { + int32_t tmpways = ways; + + do + { + sw = ((tmpways << wshift) | (sets << sshift)); + putreg32(sw, NVIC_DCCSW); + } + while (tmpways--); + } + while (sets--); + + ARM_DSB(); + ARM_ISB(); +#endif /* !CONFIG_ARMV7M_DCACHE_WRITETHROUGH */ +} +#endif /* CONFIG_ARMV7M_DCACHE */ + +/**************************************************************************** + * Name: up_flush_dcache + * + * Description: + * Flush the data cache within the specified region by cleaning and + * invalidating the D cache. + * + * NOTE: If DCACHE write-through is configured, then this operation is the + * same as up_invalidate_cache(). + * + * Input Parameters: + * start - virtual start address of region + * end - virtual end address of region + 1 + * + * Returned Value: + * None + * + * Assumptions: + * This operation is not atomic. This function assumes that the caller + * has exclusive access to the address range so that no harm is done if + * the operation is pre-empted. + * + ****************************************************************************/ + +#ifdef CONFIG_ARMV7M_DCACHE +void up_flush_dcache(uintptr_t start, uintptr_t end) +{ +#ifndef CONFIG_ARMV7M_DCACHE_WRITETHROUGH + uint32_t ccsidr; + uint32_t sshift; + uint32_t ssize; + + /* Get the characteristics of the D-Cache */ + + ccsidr = getreg32(NVIC_CCSIDR); + sshift = CCSIDR_LSSHIFT(ccsidr) + 4; /* log2(cache-line-size-in-bytes) */ + + /* Clean and invalidate the D-Cache over the range of addresses */ + + ssize = (1 << sshift); + start &= ~(ssize - 1); + ARM_DSB(); + + do + { + /* The below store causes the cache to check its directory and + * determine if this address is contained in the cache. If so, it clean + * and invalidate that cache line. Only the cache way containing the + * address is invalidated. If the address is not in the cache, then + * nothing is invalidated. + */ + + putreg32(start, NVIC_DCCIMVAC); + + /* Increment the address by the size of one cache line. */ + + start += ssize; + } + while (start < end); + + ARM_DSB(); + ARM_ISB(); +#else + up_invalidate_dcache(start, end); +#endif /* !CONFIG_ARMV7M_DCACHE_WRITETHROUGH */ +} +#endif /* CONFIG_ARMV7M_DCACHE */ + +/**************************************************************************** + * Name: up_flush_dcache_all + * + * Description: + * Flush the entire data cache by cleaning and invalidating the D cache. + * + * NOTE: If DCACHE write-through is configured, then this operation is the + * same as up_invalidate_cache_all(). + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + * Assumptions: + * This operation is not atomic. This function assumes that the caller + * has exclusive access to the address range so that no harm is done if + * the operation is pre-empted. + * + ****************************************************************************/ + +#ifdef CONFIG_ARMV7M_DCACHE +void up_flush_dcache_all(void) +{ +#ifndef CONFIG_ARMV7M_DCACHE_WRITETHROUGH + uint32_t ccsidr; + uint32_t sshift; + uint32_t wshift; + uint32_t sw; + uint32_t sets; + uint32_t ways; + + /* Get the characteristics of the D-Cache */ + + ccsidr = getreg32(NVIC_CCSIDR); + sets = CCSIDR_SETS(ccsidr); /* (Number of sets) - 1 */ + sshift = CCSIDR_LSSHIFT(ccsidr) + 4; /* log2(cache-line-size-in-bytes) */ + ways = CCSIDR_WAYS(ccsidr); /* (Number of ways) - 1 */ + + /* Calculate the bit offset for the way field in the DCCISW register by + * counting the number of leading zeroes. For example: + * + * Number of Value of ways Field + * Ways 'ways' Offset + * 2 1 31 + * 4 3 30 + * 8 7 29 + * ... + */ + + wshift = arm_clz(ways) & 0x1f; + + ARM_DSB(); + + /* Clean and invalidate the entire D-Cache */ + + do + { + int32_t tmpways = ways; + + do + { + sw = ((tmpways << wshift) | (sets << sshift)); + putreg32(sw, NVIC_DCCISW); + } + while (tmpways--); + } + while (sets--); + + ARM_DSB(); + ARM_ISB(); +#else + up_invalidate_dcache_all(); +#endif /* !CONFIG_ARMV7M_DCACHE_WRITETHROUGH */ +} +#endif /* CONFIG_ARMV7M_DCACHE */ + +/**************************************************************************** + * Name: up_coherent_dcache + * + * Description: + * Ensure that the I and D caches are coherent within specified region + * by cleaning the D cache (i.e., flushing the D cache contents to memory + * and invalidating the I cache. This is typically used when code has been + * written to a memory region, and will be executed. + * + * Input Parameters: + * addr - virtual start address of region + * len - Size of the address region in bytes + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_ARMV7M_ICACHE +void up_coherent_dcache(uintptr_t addr, size_t len) +{ + uintptr_t end; + + if (len > 0) + { + /* Flush any dirtcy D-Cache lines to memory */ + + end = addr + len; + up_clean_dcache(addr, end); + UNUSED(end); + + /* Invalidate the entire I-Cache */ + + up_invalidate_icache_all(); + } +} +#endif diff --git a/arch/arm/src/armv7-m/up_coherent_dcache.c b/arch/arm/src/armv7-m/up_coherent_dcache.c deleted file mode 100644 index 008b37a9a3..0000000000 --- a/arch/arm/src/armv7-m/up_coherent_dcache.c +++ /dev/null @@ -1,87 +0,0 @@ -/**************************************************************************** - * arch/arm/src/armv7-m/up_coherent_dcache.c - * - * Copyright (C) 2015 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include "cache.h" - -#include - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: up_coherent_dcache - * - * Description: - * Ensure that the I and D caches are coherent within specified region - * by cleaning the D cache (i.e., flushing the D cache contents to memory - * and invalidating the I cache. This is typically used when code has been - * written to a memory region, and will be executed. - * - * Input Parameters: - * addr - virtual start address of region - * len - Size of the address region in bytes - * - * Returned Value: - * None - * - ****************************************************************************/ - -void up_coherent_dcache(uintptr_t addr, size_t len) -{ - uintptr_t end; - - if (len > 0) - { - /* Flush any dirtcy D-Cache lines to memory */ - - end = addr + len; - arch_clean_dcache(addr, end); - UNUSED(end); - - /* Invalidate the entire I-Cache */ - - arch_invalidate_icache_all(); - } -} diff --git a/arch/arm/src/armv7-r/Kconfig b/arch/arm/src/armv7-r/Kconfig index da6cddaed1..97f4a7bf28 100644 --- a/arch/arm/src/armv7-r/Kconfig +++ b/arch/arm/src/armv7-r/Kconfig @@ -26,29 +26,6 @@ config ARMV7R_MEMINIT the memory initialization first, then explicitly call arm_data_initialize(). -config ARMV7R_HAVE_ICACHE - bool - default n - -config ARMV7R_HAVE_DCACHE - bool - default n - -config ARMV7R_ICACHE - bool "Use I-Cache" - default n - depends on ARMV7R_HAVE_ICACHE - -config ARMV7R_DCACHE - bool "Use D-Cache" - default n - depends on ARMV7R_HAVE_DCACHE - -config ARMV7R_DCACHE_WRITETHROUGH - bool "D-Cache Write-Through" - default n - depends on ARMV7R_DCACHE - config ARMV7R_HAVE_L2CC bool default n diff --git a/arch/arm/src/armv7-a/cache.h b/arch/arm/src/armv7-r/arm_cache.c similarity index 67% rename from arch/arm/src/armv7-a/cache.h rename to arch/arm/src/armv7-r/arm_cache.c index c9af0611f7..dc96ab59e9 100644 --- a/arch/arm/src/armv7-a/cache.h +++ b/arch/arm/src/armv7-r/arm_cache.c @@ -1,7 +1,7 @@ -/************************************************************************************ - * arch/arm/src/armv7-a/cache.h +/**************************************************************************** + * arch/arm/src/armv7-r/arm_cache.c * - * Copyright (C) 2014 Gregory Nutt. All rights reserved. + * Copyright (C) 2015, 2019 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -31,24 +31,22 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * - ************************************************************************************/ + ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_ARMV7_A_CACHE_H -#define __ARCH_ARM_SRC_ARMV7_A_CACHE_H - -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include +#include #include #include "cp15_cacheops.h" #include "l2cc.h" -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ /* Intrinsics are used in these inline functions */ @@ -60,14 +58,12 @@ #define ARM_ISB() arm_isb(15) #define ARM_DMB() arm_dmb(15) - /************************************************************************************ - * Inline Functions - ************************************************************************************/ - -#ifndef __ASSEMBLY__ +/**************************************************************************** + * Public Functions + ****************************************************************************/ /**************************************************************************** - * Name: arch_invalidate_dcache + * Name: up_invalidate_dcache * * Description: * Invalidate the data cache within the specified region; we will be @@ -88,14 +84,14 @@ * ****************************************************************************/ -static inline void arch_invalidate_dcache(uintptr_t start, uintptr_t end) +void up_invalidate_dcache(uintptr_t start, uintptr_t end) { cp15_invalidate_dcache(start, end); l2cc_invalidate(start, end); } /**************************************************************************** - * Name: arch_invalidate_dcache_all + * Name: up_invalidate_dcache_all * * Description: * Invalidate the entire contents of D cache. @@ -111,7 +107,7 @@ static inline void arch_invalidate_dcache(uintptr_t start, uintptr_t end) * ****************************************************************************/ -static inline void arch_invalidate_dcache_all(void) +void up_invalidate_dcache_all(void) { #ifdef CONFIG_ARCH_L2CACHE irqstate_t flags = enter_critical_section(); @@ -123,11 +119,12 @@ static inline void arch_invalidate_dcache_all(void) #endif } -/************************************************************************************ - * Name: arch_invalidate_icache +/**************************************************************************** + * Name: up_invalidate_icache_all * * Description: - * Invalidate all instruction caches to PoU, also flushes branch target cache + * Invalidate all instruction caches to PoU, also flushes branch target + * cache * * Input Parameters: * None @@ -135,12 +132,15 @@ static inline void arch_invalidate_dcache_all(void) * Returned Value: * None * - ************************************************************************************/ + ****************************************************************************/ -#define arch_invalidate_icache() cp15_invalidate_icache() +void up_invalidate_icache_all(void) +{ + cp15_invalidate_icache(); +} /**************************************************************************** - * Name: arch_clean_dcache + * Name: up_clean_dcache * * Description: * Clean the data cache within the specified region by flushing the @@ -160,14 +160,14 @@ static inline void arch_invalidate_dcache_all(void) * ****************************************************************************/ -static inline void arch_clean_dcache(uintptr_t start, uintptr_t end) +void up_clean_dcache(uintptr_t start, uintptr_t end) { cp15_clean_dcache(start, end); l2cc_clean(start, end); } /**************************************************************************** - * Name: arch_flush_dcache + * Name: up_flush_dcache * * Description: * Flush the data cache within the specified region by cleaning and @@ -187,32 +187,120 @@ static inline void arch_clean_dcache(uintptr_t start, uintptr_t end) * ****************************************************************************/ -static inline void arch_flush_dcache(uintptr_t start, uintptr_t end) +void up_flush_dcache(uintptr_t start, uintptr_t end) { cp15_flush_dcache(start, end); l2cc_flush(start, end); } /**************************************************************************** - * Public Data + * Name: up_enable_icache + * + * Description: + * Enable the I-Cache + * + * Input Parameters: + * None + * + * Returned Value: + * None + * ****************************************************************************/ -#ifdef __cplusplus -#define EXTERN extern "C" -extern "C" +void up_enable_icache(void) { -#else -#define EXTERN extern -#endif + cp15_enable_icache(); +} /**************************************************************************** - * Public Function Prototypes + * Name: up_disable_icache + * + * Description: + * Disable the I-Cache + * + * Input Parameters: + * None + * + * Returned Value: + * None + * ****************************************************************************/ -#undef EXTERN -#ifdef __cplusplus +void up_disable_icache(void) +{ + cp15_disable_icache(); } -#endif -#endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_ARMV7_A_CACHE_H */ +/**************************************************************************** + * Name: up_enable_dcache + * + * Description: + * Enable the D-Cache + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void up_enable_dcache(void) +{ + cp15_enable_dcache(); + l2cc_enable(); +} + +/**************************************************************************** + * Name: up_disable_dcache + * + * Description: + * Disable the D-Cache + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void up_disable_dcache(void) +{ + cp15_disable_dcache(); + l2cc_disable(); +} + +/**************************************************************************** + * Name: up_coherent_dcache + * + * Description: + * Ensure that the I and D caches are coherent within specified region + * by cleaning the D cache (i.e., flushing the D cache contents to memory + * and invalidating the I cache. This is typically used when code has been + * written to a memory region, and will be executed. + * + * Input Parameters: + * addr - virtual start address of region + * len - Size of the address region in bytes + * + * Returned Value: + * None + * + ****************************************************************************/ + +void up_coherent_dcache(uintptr_t addr, size_t len) +{ + if (len > 0) + { + /* Perform the operation on the L1 cache */ + + cp15_coherent_dcache(addr, addr + len); + +#ifdef CONFIG_ARCH_L2CACHE + /* If we have an L2 cache, then there more things that need to done */ + +# warning This is insufficient +#endif + } +} diff --git a/arch/arm/src/armv7-r/arm_coherent_dcache.c b/arch/arm/src/armv7-r/arm_coherent_dcache.c deleted file mode 100644 index 3be6b8df5c..0000000000 --- a/arch/arm/src/armv7-r/arm_coherent_dcache.c +++ /dev/null @@ -1,97 +0,0 @@ -/**************************************************************************** - * arch/arm/src/armv7-r/up_coherent_dcache.c - * - * Copyright (C) 2015 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include "cp15_cacheops.h" - -#include - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: up_coherent_dcache - * - * Description: - * Ensure that the I and D caches are coherent within specified region - * by cleaning the D cache (i.e., flushing the D cache contents to memory - * and invalidating the I cache. This is typically used when code has been - * written to a memory region, and will be executed. - * - * Input Parameters: - * addr - virtual start address of region - * len - Size of the address region in bytes - * - * Returned Value: - * None - * - ****************************************************************************/ - -void up_coherent_dcache(uintptr_t addr, size_t len) -{ - if (len > 0) - { - /* Perform the operation on the L1 cache */ - - cp15_coherent_dcache(addr, addr + len - 1); - -#ifdef CONFIG_ARCH_L2CACHE - /* If we have an L2 cache, then there more things that need to done */ - -# warning This is insufficient -#endif - } -} diff --git a/arch/arm/src/armv7-r/arm_head.S b/arch/arm/src/armv7-r/arm_head.S index 2fd0fbda07..adb53026a9 100644 --- a/arch/arm/src/armv7-r/arm_head.S +++ b/arch/arm/src/armv7-r/arm_head.S @@ -467,7 +467,7 @@ arm_data_initialize: adr r3, ..Lramfunc ldmia r3, {r0, r1} - ldr r3, =arch_clean_dcache + ldr r3, =up_clean_dcache b r3 #else /* Otherwise return to the caller */ diff --git a/arch/arm/src/armv7-r/cp15_cacheops.h b/arch/arm/src/armv7-r/cp15_cacheops.h index aa0dee9906..0c0c4924c3 100644 --- a/arch/arm/src/armv7-r/cp15_cacheops.h +++ b/arch/arm/src/armv7-r/cp15_cacheops.h @@ -201,6 +201,26 @@ #ifdef __ASSEMBLY__ +/************************************************************************************ + * Name: cp15_enable_dcache + * + * Description: + * Enable L1 D Cache + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ************************************************************************************/ + + .macro cp15_enable_dcache, tmp + mrc p15, 0, \tmp, c1, c0, 0 /* Read SCTLR */ + orr \tmp, \tmp, #(0x1 << 2) /* Enable D cache */ + mcr p15, 0, \tmp, c1, c0, 0 /* Update the SCTLR */ + .endm + /************************************************************************************ * Name: cp15_disable_dcache * @@ -222,10 +242,10 @@ .endm /************************************************************************************ - * Name: cp15_disable_caches + * Name: cp15_enable_icache * * Description: - * Disable L1 Caches + * Enable L1 I Cache * * Input Parameters: * None @@ -235,10 +255,29 @@ * ************************************************************************************/ - .macro cp15_disable_caches, tmp + .macro cp15_enable_icache, tmp + mrc p15, 0, \tmp, c1, c0, 0 /* Read SCTLR */ + orr \tmp, \tmp, #(0x1 << 12) /* Enable I cache */ + mcr p15, 0, \tmp, c1, c0, 0 /* Update the SCTLR */ + .endm + +/************************************************************************************ + * Name: cp15_disable_icache + * + * Description: + * Disable L1 I Cache + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ************************************************************************************/ + + .macro cp15_disable_icache, tmp mrc p15, 0, \tmp, c1, c0, 0 /* Read SCTLR */ bic \tmp, \tmp, #(0x1 << 12) /* Disable I cache */ - bic \tmp, \tmp, #(0x1 << 2) /* Disable D cache */ mcr p15, 0, \tmp, c1, c0, 0 /* Update the SCTLR */ .endm @@ -489,11 +528,38 @@ #ifndef __ASSEMBLY__ +/************************************************************************************ + * Name: cp15_enable_dcache + * + * Description: + * Enable L1 D Cache + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ************************************************************************************/ + +static inline void cp15_enable_dcache(void) +{ + __asm__ __volatile__ + ( + "\tmrc p15, 0, r0, c1, c0, 0\n" /* Read SCTLR */ + "\torr r0, r0, #(1 << 2)\n" /* Enable D cache */ + "\tmcr p15, 0, r0, c1, c0, 0\n" /* Update the SCTLR */ + : + : + : "r0", "memory" + ); +} + /************************************************************************************ * Name: cp15_disable_dcache * * Description: - * Disable L1 Caches + * Disable L1 D Cache * * Input Parameters: * None @@ -517,10 +583,10 @@ static inline void cp15_disable_dcache(void) } /************************************************************************************ - * Name: cp15_disable_caches + * Name: cp15_enable_icache * * Description: - * Disable L1 Caches + * Enable L1 I Cache * * Input Parameters: * None @@ -530,13 +596,39 @@ static inline void cp15_disable_dcache(void) * ************************************************************************************/ -static inline void cp15_disable_caches(void) +static inline void cp15_enable_icache(void) +{ + __asm__ __volatile__ + ( + "\tmrc p15, 0, r0, c1, c0, 0\n" /* Read SCTLR */ + "\torr r0, r0, #(1 << 12)\n" /* Enable I cache */ + "\tmcr p15, 0, r0, c1, c0, 0\n" /* Update the SCTLR */ + : + : + : "r0", "memory" + ); +} + +/************************************************************************************ + * Name: cp15_disable_icache + * + * Description: + * Disable L1 I Cache + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ************************************************************************************/ + +static inline void cp15_disable_icache(void) { __asm__ __volatile__ ( "\tmrc p15, 0, r0, c1, c0, 0\n" /* Read SCTLR */ "\tbic r0, r0, #(1 << 12)\n" /* Disable I cache */ - "\tbic r0, r0, #(1 << 2)\n" /* Disable D cache */ "\tmcr p15, 0, r0, c1, c0, 0\n" /* Update the SCTLR */ : : diff --git a/arch/arm/src/armv7-r/mpu.h b/arch/arm/src/armv7-r/mpu.h index 646e4875f6..501011ce06 100644 --- a/arch/arm/src/armv7-r/mpu.h +++ b/arch/arm/src/armv7-r/mpu.h @@ -49,7 +49,6 @@ # include # include "up_arch.h" -# include "cache.h" # include "sctlr.h" # include "cp15.h" #endif @@ -410,7 +409,6 @@ static inline void mpu_control(bool enable) * ****************************************************************************/ -#if defined(CONFIG_ARMV7R_HAVE_ICACHE) || defined(CONFIG_ARMV7R_DCACHE) static inline void mpu_priv_stronglyordered(uintptr_t base, size_t size) { unsigned int region = mpu_allocregion(); @@ -444,7 +442,6 @@ static inline void mpu_priv_stronglyordered(uintptr_t base, size_t size) ((uint32_t)subregions << MPU_RASR_SRD_SHIFT); /* Sub-regions */ mpu_set_drsr(regval); } -#endif /**************************************************************************** * Name: mpu_user_flash diff --git a/arch/arm/src/imx6/Make.defs b/arch/arm/src/imx6/Make.defs index 704c7f8dea..34c9e1aaf3 100644 --- a/arch/arm/src/imx6/Make.defs +++ b/arch/arm/src/imx6/Make.defs @@ -123,11 +123,7 @@ CMN_CSRCS += arm_virtpgaddr.c endif endif -ifeq ($(CONFIG_ELF),y) -CMN_CSRCS += arm_coherent_dcache.c -else ifeq ($(CONFIG_MODULE),y) -CMN_CSRCS += arm_coherent_dcache.c -endif +CMN_CSRCS += arm_cache.c ifeq ($(CONFIG_ARCH_FPU),y) CMN_ASRCS += arm_savefpu.S arm_restorefpu.S diff --git a/arch/arm/src/imx6/imx_boot.c b/arch/arm/src/imx6/imx_boot.c index f48b3e70a2..76b2127396 100644 --- a/arch/arm/src/imx6/imx_boot.c +++ b/arch/arm/src/imx6/imx_boot.c @@ -43,6 +43,7 @@ #include #include +#include #ifdef CONFIG_PAGING # include #endif @@ -53,7 +54,6 @@ #include "arm.h" #include "mmu.h" #include "scu.h" -#include "cache.h" #include "fpu.h" #include "up_internal.h" #include "up_arch.h" @@ -287,8 +287,8 @@ static void imx_copyvectorblock(void) #else /* Flush the DCache to assure that the vector data is in physical RAM */ - arch_clean_dcache((uintptr_t)IMX_VECTOR_VSRAM, - (uintptr_t)IMX_VECTOR_VSRAM + imx_vectorsize()); + up_clean_dcache((uintptr_t)IMX_VECTOR_VSRAM, + (uintptr_t)IMX_VECTOR_VSRAM + imx_vectorsize()); #endif } @@ -453,7 +453,7 @@ void arm_boot(void) * be available when fetched into the I-Cache. */ - arch_clean_dcache((uintptr_t)&_sramfuncs, (uintptr_t)&_eramfuncs) + up_clean_dcache((uintptr_t)&_sramfuncs, (uintptr_t)&_eramfuncs) PROGRESS('F'); #endif diff --git a/arch/arm/src/imxrt/Make.defs b/arch/arm/src/imxrt/Make.defs index e3ad6a818d..de4e4b6abb 100644 --- a/arch/arm/src/imxrt/Make.defs +++ b/arch/arm/src/imxrt/Make.defs @@ -79,14 +79,7 @@ ifeq ($(CONFIG_STACK_COLORATION),y) CMN_CSRCS += up_checkstack.c endif -ifeq ($(CONFIG_ARMV7M_DCACHE),y) -CMN_CSRCS += arch_enable_dcache.c arch_disable_dcache.c -CMN_CSRCS += arch_invalidate_dcache.c arch_invalidate_dcache_all.c -ifneq ($(CONFIG_ARMV7M_DCACHE_WRITETHROUGH),y) -CMN_CSRCS += arch_clean_dcache.c arch_clean_dcache_all.c -CMN_CSRCS += arch_flush_dcache.c arch_flush_dcache_all.c -endif -endif +CMN_CSRCS += up_cache.c ifeq ($(CONFIG_ARCH_FPU),y) CMN_ASRCS += up_fpu.S diff --git a/arch/arm/src/imxrt/imxrt_edma.c b/arch/arm/src/imxrt/imxrt_edma.c index bb8d5f7762..e0c69ede70 100644 --- a/arch/arm/src/imxrt/imxrt_edma.c +++ b/arch/arm/src/imxrt/imxrt_edma.c @@ -58,7 +58,6 @@ #include #include "up_arch.h" -#include "cache.h" #include "up_internal.h" #include "sched/sched.h" @@ -1105,8 +1104,8 @@ int imxrt_dmach_xfrsetup(DMACH_HANDLE *handle, /* Clean cache associated with the previous TCD memory */ - arch_clean_dcache((uintptr_t)prev, - (uintptr_t)prev + sizeof(struct imxrt_edmatcd_s)); + up_clean_dcache((uintptr_t)prev, + (uintptr_t)prev + sizeof(struct imxrt_edmatcd_s)); /* Check if the TCD block in the DMA channel registers is the same as * the previous previous TCD. This can happen if the previous TCD was @@ -1130,8 +1129,8 @@ int imxrt_dmach_xfrsetup(DMACH_HANDLE *handle, /* Clean cache associated with the TCD memory */ - arch_clean_dcache((uintptr_t)tcd, - (uintptr_t)tcd + sizeof(struct imxrt_edmatcd_s)); + up_clean_dcache((uintptr_t)tcd, + (uintptr_t)tcd + sizeof(struct imxrt_edmatcd_s)); #else /* Scatter/gather DMA is NOT supported */ @@ -1168,8 +1167,8 @@ int imxrt_dmach_xfrsetup(DMACH_HANDLE *handle, * is one. */ - arch_invalidate_dcache((uintptr_t)config->daddr, - (uintptr_t)config->daddr + config->nbytes); + up_invalidate_dcache((uintptr_t)config->daddr, + (uintptr_t)config->daddr + config->nbytes); } /* Check for an Tx (peripheral-to-memory/memory-to-memory) DMA transfer */ @@ -1183,8 +1182,8 @@ int imxrt_dmach_xfrsetup(DMACH_HANDLE *handle, */ #warning Missing logic - arch_clean_dcache((uintptr_t)config->saddr, - (uintptr_t)config->saddr + config->nbytes); + up_clean_dcache((uintptr_t)config->saddr, + (uintptr_t)config->saddr + config->nbytes); } dmach->state = IMXRT_DMA_CONFIGURED; diff --git a/arch/arm/src/imxrt/imxrt_enet.c b/arch/arm/src/imxrt/imxrt_enet.c index 92dd5bc5d5..e9f4b9494d 100644 --- a/arch/arm/src/imxrt/imxrt_enet.c +++ b/arch/arm/src/imxrt/imxrt_enet.c @@ -64,7 +64,6 @@ #endif #include "up_arch.h" -#include "cache.h" #include "chip.h" #include "imxrt_config.h" #include "chip/imxrt_enet.h" @@ -502,8 +501,8 @@ static int imxrt_transmit(FAR struct imxrt_driver_s *priv) } #ifdef CONFIG_DEBUG_ASSERTIONS - arch_invalidate_dcache((uintptr_t)txdesc, - (uintptr_t)txdesc + sizeof(struct enet_desc_s)); + up_invalidate_dcache((uintptr_t)txdesc, + (uintptr_t)txdesc + sizeof(struct enet_desc_s)); DEBUGASSERT(priv->txtail != priv->txhead && (txdesc->status1 & TXDESC_R) == 0); @@ -816,8 +815,8 @@ static void imxrt_receive(FAR struct imxrt_driver_s *priv) */ rxdesc = &priv->rxdesc[priv->rxtail]; - arch_invalidate_dcache((uintptr_t)rxdesc, - (uintptr_t)rxdesc + sizeof(struct enet_desc_s)); + up_invalidate_dcache((uintptr_t)rxdesc, + (uintptr_t)rxdesc + sizeof(struct enet_desc_s)); /* Check if the data buffer associated with the descriptor has * been filled with valid data. @@ -837,8 +836,8 @@ static void imxrt_receive(FAR struct imxrt_driver_s *priv) * from memory when the packet content is accessed. */ - arch_invalidate_dcache((uintptr_t)priv->dev.d_buf, - (uintptr_t)priv->dev.d_buf + priv->dev.d_len); + up_invalidate_dcache((uintptr_t)priv->dev.d_buf, + (uintptr_t)priv->dev.d_buf + priv->dev.d_len); /* Dispatch (or drop) the newly received packet */ @@ -911,8 +910,8 @@ static void imxrt_txdone(FAR struct imxrt_driver_s *priv) */ txdesc = &priv->txdesc[priv->txtail]; - arch_invalidate_dcache((uintptr_t)txdesc, - (uintptr_t)txdesc + sizeof(struct enet_desc_s)); + up_invalidate_dcache((uintptr_t)txdesc, + (uintptr_t)txdesc + sizeof(struct enet_desc_s)); txdone = false; if ((txdesc->status1 & TXDESC_R) == 0 && priv->txtail != priv->txhead) diff --git a/arch/arm/src/imxrt/imxrt_lpspi.c b/arch/arm/src/imxrt/imxrt_lpspi.c index 161c355ccc..4b34638135 100644 --- a/arch/arm/src/imxrt/imxrt_lpspi.c +++ b/arch/arm/src/imxrt/imxrt_lpspi.c @@ -82,7 +82,6 @@ #include "up_internal.h" #include "up_arch.h" -#include "cache.h" #include "chip.h" #include "imxrt_lpspi.h" diff --git a/arch/arm/src/imxrt/imxrt_mpuinit.c b/arch/arm/src/imxrt/imxrt_mpuinit.c index 9ead633d92..b428bc9a35 100644 --- a/arch/arm/src/imxrt/imxrt_mpuinit.c +++ b/arch/arm/src/imxrt/imxrt_mpuinit.c @@ -44,7 +44,6 @@ #include #include "mpu.h" -#include "cache.h" #include "chip/imxrt_memorymap.h" #include "imxrt_mpuinit.h" diff --git a/arch/arm/src/imxrt/imxrt_start.c b/arch/arm/src/imxrt/imxrt_start.c index 347a711a54..0247d8113f 100644 --- a/arch/arm/src/imxrt/imxrt_start.c +++ b/arch/arm/src/imxrt/imxrt_start.c @@ -43,13 +43,13 @@ #include #include +#include #include #include #include "up_arch.h" #include "up_internal.h" -#include "cache.h" #ifdef CONFIG_ARCH_FPU # include "nvic.h" #endif @@ -377,9 +377,8 @@ void __start(void) /* Enable I- and D-Caches */ - arch_dcache_writethrough(); - arch_enable_icache(); - arch_enable_dcache(); + up_enable_icache(); + up_enable_dcache(); /* Perform early serial initialization */ diff --git a/arch/arm/src/imxrt/imxrt_usdhc.c b/arch/arm/src/imxrt/imxrt_usdhc.c index 38051ce310..77c0bb652d 100644 --- a/arch/arm/src/imxrt/imxrt_usdhc.c +++ b/arch/arm/src/imxrt/imxrt_usdhc.c @@ -59,7 +59,6 @@ #include #include -#include "cache.h" #include "chip.h" #include "up_arch.h" @@ -996,8 +995,8 @@ static void imxrt_endtransfer(struct imxrt_dev_s *priv, /* DMA modified the buffer, so we need to flush its cache lines. */ - arch_invalidate_dcache((uintptr_t)priv->buffer, - (uintptr_t)priv->bufferend); + up_invalidate_dcache((uintptr_t)priv->buffer, + (uintptr_t)priv->bufferend); /* Debug instrumentation */ diff --git a/arch/arm/src/kinetis/kinetis_serial.c b/arch/arm/src/kinetis/kinetis_serial.c index 66da4cbf4a..58c4b575b9 100644 --- a/arch/arm/src/kinetis/kinetis_serial.c +++ b/arch/arm/src/kinetis/kinetis_serial.c @@ -61,7 +61,6 @@ #include -#include "cache.h" #include "up_arch.h" #include "up_internal.h" @@ -1582,8 +1581,8 @@ static int up_dma_receive(struct uart_dev_s *dev, unsigned int *status) { /* Invalidate the DMA buffer */ - arch_invalidate_dcache((uintptr_t)priv->rxfifo, - (uintptr_t)priv->rxfifo + RXDMA_BUFFER_SIZE); + up_invalidate_dcache((uintptr_t)priv->rxfifo, + (uintptr_t)priv->rxfifo + RXDMA_BUFFER_SIZE); /* Now read from the DMA buffer */ diff --git a/arch/arm/src/lpc31xx/lpc31_ehci.c b/arch/arm/src/lpc31xx/lpc31_ehci.c index 87a4d1e4a1..2619f50e97 100644 --- a/arch/arm/src/lpc31xx/lpc31_ehci.c +++ b/arch/arm/src/lpc31xx/lpc31_ehci.c @@ -61,8 +61,6 @@ #include #include "up_arch.h" -#include "cache.h" - #include "chip.h" #include "lpc31.h" #include "lpc31_cgudrvr.h" @@ -1371,8 +1369,8 @@ static int lpc31_qtd_invalidate(struct lpc31_qtd_s *qtd, uint32_t **bp, void *ar * memory over the specified address range. */ - cp15_invalidate_dcache((uintptr_t)&qtd->hw, - (uintptr_t)&qtd->hw + sizeof(struct ehci_qtd_s)); + up_invalidate_dcache((uintptr_t)&qtd->hw, + (uintptr_t)&qtd->hw + sizeof(struct ehci_qtd_s)); return OK; } #endif @@ -1390,8 +1388,8 @@ static int lpc31_qh_invalidate(struct lpc31_qh_s *qh) { /* Invalidate the QH first so that we reload the qTD list head */ - cp15_invalidate_dcache((uintptr_t)&qh->hw, - (uintptr_t)&qh->hw + sizeof(struct ehci_qh_s)); + up_invalidate_dcache((uintptr_t)&qh->hw, + (uintptr_t)&qh->hw + sizeof(struct ehci_qh_s)); /* Then invalidate all of the qTD entries in the queue */ @@ -1415,10 +1413,8 @@ static int lpc31_qtd_flush(struct lpc31_qtd_s *qtd, uint32_t **bp, void *arg) * to force re-loading of the data from memory when next accessed. */ - cp15_flush_idcache((uintptr_t)&qtd->hw, - (uintptr_t)&qtd->hw + sizeof(struct ehci_qtd_s)); - cp15_invalidate_dcache((uintptr_t)&qtd->hw, - (uintptr_t)&qtd->hw + sizeof(struct ehci_qtd_s)); + up_flush_dcache((uintptr_t)&qtd->hw, + (uintptr_t)&qtd->hw + sizeof(struct ehci_qtd_s)); return OK; } @@ -1438,10 +1434,8 @@ static int lpc31_qh_flush(struct lpc31_qh_s *qh) * reloaded from D-Cache. */ - cp15_flush_idcache((uintptr_t)&qh->hw, - (uintptr_t)&qh->hw + sizeof(struct ehci_qh_s)); - cp15_invalidate_dcache((uintptr_t)&qh->hw, - (uintptr_t)&qh->hw + sizeof(struct ehci_qh_s)); + up_flush_dcache((uintptr_t)&qh->hw, + (uintptr_t)&qh->hw + sizeof(struct ehci_qh_s)); /* Then flush all of the qTD entries in the queue */ @@ -1672,8 +1666,8 @@ static void lpc31_qh_enqueue(struct lpc31_qh_s *qhead, struct lpc31_qh_s *qh) physaddr = (uintptr_t)lpc31_physramaddr((uintptr_t)qh); qhead->hw.hlp = lpc31_swap32(physaddr | QH_HLP_TYP_QH); - cp15_flush_idcache((uintptr_t)&qhead->hw, - (uintptr_t)&qhead->hw + sizeof(struct ehci_qh_s)); + up_clean_dcache((uintptr_t)&qhead->hw, + (uintptr_t)&qhead->hw + sizeof(struct ehci_qh_s)); } /**************************************************************************** @@ -1832,8 +1826,7 @@ static int lpc31_qtd_addbpl(struct lpc31_qtd_s *qtd, const void *buffer, size_t * will be accessed for an OUT DMA. */ - cp15_flush_idcache((uintptr_t)buffer, (uintptr_t)buffer + buflen); - cp15_invalidate_dcache((uintptr_t)buffer, (uintptr_t)buffer + buflen); + up_flush_dcache((uintptr_t)buffer, (uintptr_t)buffer + buflen); /* Loop, adding the aligned physical addresses of the buffer to the buffer page * list. Only the first entry need not be aligned (because only the first @@ -2523,7 +2516,7 @@ static ssize_t lpc31_transfer_wait(struct lpc31_epinfo_s *epinfo) * invalid in this memory region. */ - cp15_invalidate_dcache((uintptr_t)buffer, (uintptr_t)buffer + buflen); + up_invalidate_dcache((uintptr_t)buffer, (uintptr_t)buffer + buflen); } #endif @@ -2673,8 +2666,8 @@ static int lpc31_qtd_ioccheck(struct lpc31_qtd_s *qtd, uint32_t **bp, void *arg) /* Make sure we reload the QH from memory */ - cp15_invalidate_dcache((uintptr_t)&qtd->hw, - (uintptr_t)&qtd->hw + sizeof(struct ehci_qtd_s)); + up_invalidate_dcache((uintptr_t)&qtd->hw, + (uintptr_t)&qtd->hw + sizeof(struct ehci_qtd_s)); lpc31_qtd_print(qtd); /* Remove the qTD from the list @@ -2724,8 +2717,8 @@ static int lpc31_qh_ioccheck(struct lpc31_qh_s *qh, uint32_t **bp, void *arg) /* Make sure we reload the QH from memory */ - cp15_invalidate_dcache((uintptr_t)&qh->hw, - (uintptr_t)&qh->hw + sizeof(struct ehci_qh_s)); + up_invalidate_dcache((uintptr_t)&qh->hw, + (uintptr_t)&qh->hw + sizeof(struct ehci_qh_s)); lpc31_qh_print(qh); /* Get the endpoint info pointer from the extended QH data. Only the @@ -2778,7 +2771,7 @@ static int lpc31_qh_ioccheck(struct lpc31_qh_s *qh, uint32_t **bp, void *arg) */ **bp = qh->hw.hlp; - cp15_flush_idcache((uintptr_t)*bp, (uintptr_t)*bp + sizeof(uint32_t)); + up_clean_dcache((uintptr_t)*bp, (uintptr_t)*bp + sizeof(uint32_t)); /* Check for errors, update the data toggle */ @@ -2878,8 +2871,8 @@ static int lpc31_qtd_cancel(struct lpc31_qtd_s *qtd, uint32_t **bp, void *arg) /* Make sure we reload the QH from memory */ - cp15_invalidate_dcache((uintptr_t)&qtd->hw, - (uintptr_t)&qtd->hw + sizeof(struct ehci_qtd_s)); + up_invalidate_dcache((uintptr_t)&qtd->hw, + (uintptr_t)&qtd->hw + sizeof(struct ehci_qtd_s)); lpc31_qtd_print(qtd); /* Remove the qTD from the list @@ -2923,8 +2916,8 @@ static int lpc31_qh_cancel(struct lpc31_qh_s *qh, uint32_t **bp, void *arg) /* Make sure we reload the QH from memory */ - cp15_invalidate_dcache((uintptr_t)&qh->hw, - (uintptr_t)&qh->hw + sizeof(struct ehci_qh_s)); + up_invalidate_dcache((uintptr_t)&qh->hw, + (uintptr_t)&qh->hw + sizeof(struct ehci_qh_s)); lpc31_qh_print(qh); /* Check if this is the QH that we are looking for */ @@ -2953,7 +2946,7 @@ static int lpc31_qh_cancel(struct lpc31_qh_s *qh, uint32_t **bp, void *arg) */ **bp = qh->hw.hlp; - cp15_flush_idcache((uintptr_t)*bp, (uintptr_t)*bp + sizeof(uint32_t)); + up_clean_dcache((uintptr_t)*bp, (uintptr_t)*bp + sizeof(uint32_t)); /* Re-enable the schedules (if they were enabled before. */ @@ -3003,8 +2996,8 @@ static inline void lpc31_ioc_bottomhalf(void) /* Check the Asynchronous Queue */ /* Make sure that the head of the asynchronous queue is invalidated */ - cp15_invalidate_dcache((uintptr_t)&g_asynchead.hw, - (uintptr_t)&g_asynchead.hw + sizeof(struct ehci_qh_s)); + up_invalidate_dcache((uintptr_t)&g_asynchead.hw, + (uintptr_t)&g_asynchead.hw + sizeof(struct ehci_qh_s)); /* Set the back pointer to the forward QH pointer of the asynchronous * queue head. @@ -3034,8 +3027,8 @@ static inline void lpc31_ioc_bottomhalf(void) /* Check the Interrupt Queue */ /* Make sure that the head of the interrupt queue is invalidated */ - cp15_invalidate_dcache((uintptr_t)&g_intrhead.hw, - (uintptr_t)&g_intrhead.hw + sizeof(struct ehci_qh_s)); + up_invalidate_dcache((uintptr_t)&g_intrhead.hw, + (uintptr_t)&g_intrhead.hw + sizeof(struct ehci_qh_s)); /* Set the back pointer to the forward qTD pointer of the asynchronous * queue head. @@ -5200,8 +5193,8 @@ FAR struct usbhost_connection_s *lpc31_ehci_initialize(int controller) g_asynchead.hw.overlay.token = lpc31_swap32(QH_TOKEN_HALTED); g_asynchead.fqp = lpc31_swap32(QTD_NQP_T); - cp15_flush_idcache((uintptr_t)&g_asynchead.hw, - (uintptr_t)&g_asynchead.hw + sizeof(struct ehci_qh_s)); + up_clean_dcache((uintptr_t)&g_asynchead.hw, + (uintptr_t)&g_asynchead.hw + sizeof(struct ehci_qh_s)); /* Set the Current Asynchronous List Address. */ @@ -5231,10 +5224,10 @@ FAR struct usbhost_connection_s *lpc31_ehci_initialize(int controller) /* Set the Periodic Frame List Base Address. */ - cp15_flush_idcache((uintptr_t)&g_intrhead.hw, - (uintptr_t)&g_intrhead.hw + sizeof(struct ehci_qh_s)); - cp15_flush_idcache((uintptr_t)g_framelist, - (uintptr_t)g_framelist + FRAME_LIST_SIZE * sizeof(uint32_t)); + up_clean_dcache((uintptr_t)&g_intrhead.hw, + (uintptr_t)&g_intrhead.hw + sizeof(struct ehci_qh_s)); + up_clean_dcache((uintptr_t)g_framelist, + (uintptr_t)g_framelist + FRAME_LIST_SIZE * sizeof(uint32_t)); physaddr = lpc31_physramaddr((uintptr_t)g_framelist); lpc31_putreg(lpc31_swap32(physaddr), &HCOR->periodiclistbase); diff --git a/arch/arm/src/lpc43xx/lpc43_can.c b/arch/arm/src/lpc43xx/lpc43_can.c index e004baea63..630e00e0f1 100644 --- a/arch/arm/src/lpc43xx/lpc43_can.c +++ b/arch/arm/src/lpc43xx/lpc43_can.c @@ -52,7 +52,6 @@ #include "up_internal.h" #include "up_arch.h" -#include "cache.h" #include "chip.h" #include "lpc43_gpio.h" diff --git a/arch/arm/src/nrf52/nrf52_nvmc.c b/arch/arm/src/nrf52/nrf52_nvmc.c index e1fee5fd6b..8b5d3d1ef6 100644 --- a/arch/arm/src/nrf52/nrf52_nvmc.c +++ b/arch/arm/src/nrf52/nrf52_nvmc.c @@ -44,7 +44,6 @@ #include #include -#include "cache.h" #include "chip/nrf52_ficr.h" #include "chip/nrf52_nvmc.h" diff --git a/arch/arm/src/sama5/Make.defs b/arch/arm/src/sama5/Make.defs index 23b50d85d1..67fefb606b 100644 --- a/arch/arm/src/sama5/Make.defs +++ b/arch/arm/src/sama5/Make.defs @@ -113,11 +113,7 @@ CMN_CSRCS += arm_virtpgaddr.c endif endif -ifeq ($(CONFIG_ELF),y) -CMN_CSRCS += arm_coherent_dcache.c -else ifeq ($(CONFIG_MODULE),y) -CMN_CSRCS += arm_coherent_dcache.c -endif +CMN_CSRCS += arm_cache.c ifeq ($(CONFIG_ARCH_FPU),y) CMN_ASRCS += arm_savefpu.S arm_restorefpu.S diff --git a/arch/arm/src/sama5/sam_adc.c b/arch/arm/src/sama5/sam_adc.c index 67f56a120a..b9c3c92d84 100644 --- a/arch/arm/src/sama5/sam_adc.c +++ b/arch/arm/src/sama5/sam_adc.c @@ -71,7 +71,6 @@ #include "up_arch.h" #include "chip.h" -#include "cache.h" #include "chip/sam_adc.h" #include "chip/sam_pmc.h" #include "chip/sam_pinmap.h" @@ -662,8 +661,8 @@ static void sam_adc_dmadone(void *arg) * newly DMAed data from RAM. */ - arch_invalidate_dcache((uintptr_t)buffer, - (uintptr_t)buffer + SAMA5_ADC_SAMPLES * sizeof(uint16_t)); + up_invalidate_dcache((uintptr_t)buffer, + (uintptr_t)buffer + SAMA5_ADC_SAMPLES * sizeof(uint16_t)); /* Process each sample */ diff --git a/arch/arm/src/sama5/sam_boot.c b/arch/arm/src/sama5/sam_boot.c index 609f147608..01f93ae360 100644 --- a/arch/arm/src/sama5/sam_boot.c +++ b/arch/arm/src/sama5/sam_boot.c @@ -43,6 +43,7 @@ #include #include +#include #ifdef CONFIG_PAGING # include #endif @@ -52,7 +53,6 @@ #include "chip.h" #include "arm.h" #include "mmu.h" -#include "cache.h" #include "fpu.h" #include "up_internal.h" #include "up_arch.h" @@ -283,8 +283,8 @@ static void sam_copyvectorblock(void) #else /* Flush the DCache to assure that the vector data is in physical in ISRAM */ - arch_clean_dcache((uintptr_t)SAM_VECTOR_VSRAM, - (uintptr_t)SAM_VECTOR_VSRAM + sam_vectorsize()); + up_clean_dcache((uintptr_t)SAM_VECTOR_VSRAM, + (uintptr_t)SAM_VECTOR_VSRAM + sam_vectorsize()); #endif } @@ -457,7 +457,7 @@ void arm_boot(void) * be available when fetched into the I-Cache. */ - arch_clean_dcache((uintptr_t)&_sramfuncs, (uintptr_t)&_eramfuncs) + up_clean_dcache((uintptr_t)&_sramfuncs, (uintptr_t)&_eramfuncs) #endif /* Setup up vector block. _vector_start and _vector_end are exported from diff --git a/arch/arm/src/sama5/sam_dmac.c b/arch/arm/src/sama5/sam_dmac.c index 0690fea8bd..c136641951 100644 --- a/arch/arm/src/sama5/sam_dmac.c +++ b/arch/arm/src/sama5/sam_dmac.c @@ -50,7 +50,6 @@ #include #include "up_arch.h" -#include "cache.h" #include "up_internal.h" #include "sched/sched.h" @@ -1449,8 +1448,8 @@ sam_allocdesc(struct sam_dmach_s *dmach, struct dma_linklist_s *prev, * that hardware will be accessing the descriptor via DMA. */ - arch_clean_dcache((uintptr_t)desc, - (uintptr_t)desc + sizeof(struct dma_linklist_s)); + up_clean_dcache((uintptr_t)desc, + (uintptr_t)desc + sizeof(struct dma_linklist_s)); break; } } @@ -1773,7 +1772,7 @@ static void sam_dmaterminate(struct sam_dmach_s *dmach, int result) if (dmach->rx) { - arch_invalidate_dcache(dmach->rxaddr, dmach->rxaddr + dmach->rxsize); + up_invalidate_dcache(dmach->rxaddr, dmach->rxaddr + dmach->rxsize); } /* Perform the DMA complete callback */ @@ -2187,7 +2186,7 @@ int sam_dmatxsetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr, /* Clean caches associated with the DMA memory */ - arch_clean_dcache(maddr, maddr + nbytes); + up_clean_dcache(maddr, maddr + nbytes); return ret; } @@ -2268,7 +2267,7 @@ int sam_dmarxsetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr, /* Clean caches associated with the DMA memory */ - arch_clean_dcache(maddr, maddr + nbytes); + up_clean_dcache(maddr, maddr + nbytes); return ret; } diff --git a/arch/arm/src/sama5/sam_ehci.c b/arch/arm/src/sama5/sam_ehci.c index 304351cc70..c866cd1052 100644 --- a/arch/arm/src/sama5/sam_ehci.c +++ b/arch/arm/src/sama5/sam_ehci.c @@ -60,8 +60,6 @@ #include #include "up_arch.h" -#include "cache.h" - #include "chip.h" #include "sam_periphclks.h" #include "sam_memories.h" @@ -1173,8 +1171,8 @@ static int sam_qtd_invalidate(struct sam_qtd_s *qtd, uint32_t **bp, void *arg) * memory over the specified address range. */ - arch_invalidate_dcache((uintptr_t)&qtd->hw, - (uintptr_t)&qtd->hw + sizeof(struct ehci_qtd_s)); + up_invalidate_dcache((uintptr_t)&qtd->hw, + (uintptr_t)&qtd->hw + sizeof(struct ehci_qtd_s)); return OK; } #endif @@ -1192,8 +1190,8 @@ static int sam_qh_invalidate(struct sam_qh_s *qh) { /* Invalidate the QH first so that we reload the qTD list head */ - arch_invalidate_dcache((uintptr_t)&qh->hw, - (uintptr_t)&qh->hw + sizeof(struct ehci_qh_s)); + up_invalidate_dcache((uintptr_t)&qh->hw, + (uintptr_t)&qh->hw + sizeof(struct ehci_qh_s)); /* Then invalidate all of the qTD entries in the queue */ @@ -1218,13 +1216,13 @@ static int sam_qtd_flush(struct sam_qtd_s *qtd, uint32_t **bp, void *arg) */ #if 0 /* Didn't behave as expected */ - arch_flush_dcache((uintptr_t)&qtd->hw, - (uintptr_t)&qtd->hw + sizeof(struct ehci_qtd_s)); + up_flush_dcache((uintptr_t)&qtd->hw, + (uintptr_t)&qtd->hw + sizeof(struct ehci_qtd_s)); #else - arch_clean_dcache((uintptr_t)&qtd->hw, - (uintptr_t)&qtd->hw + sizeof(struct ehci_qtd_s)); - arch_invalidate_dcache((uintptr_t)&qtd->hw, - (uintptr_t)&qtd->hw + sizeof(struct ehci_qtd_s)); + up_clean_dcache((uintptr_t)&qtd->hw, + (uintptr_t)&qtd->hw + sizeof(struct ehci_qtd_s)); + up_invalidate_dcache((uintptr_t)&qtd->hw, + (uintptr_t)&qtd->hw + sizeof(struct ehci_qtd_s)); #endif return OK; @@ -1246,13 +1244,13 @@ static int sam_qh_flush(struct sam_qh_s *qh) */ #if 0 /* Didn't behave as expected */ - arch_flush_dcache((uintptr_t)&qh->hw, - (uintptr_t)&qh->hw + sizeof(struct ehci_qh_s)); + up_flush_dcache((uintptr_t)&qh->hw, + (uintptr_t)&qh->hw + sizeof(struct ehci_qh_s)); #else - arch_clean_dcache((uintptr_t)&qh->hw, - (uintptr_t)&qh->hw + sizeof(struct ehci_qh_s)); - arch_invalidate_dcache((uintptr_t)&qh->hw, - (uintptr_t)&qh->hw + sizeof(struct ehci_qh_s)); + up_clean_dcache((uintptr_t)&qh->hw, + (uintptr_t)&qh->hw + sizeof(struct ehci_qh_s)); + up_invalidate_dcache((uintptr_t)&qh->hw, + (uintptr_t)&qh->hw + sizeof(struct ehci_qh_s)); #endif /* Then flush all of the qTD entries in the queue */ @@ -1484,8 +1482,8 @@ static void sam_qh_enqueue(struct sam_qh_s *qhead, struct sam_qh_s *qh) physaddr = (uintptr_t)sam_physramaddr((uintptr_t)qh); qhead->hw.hlp = sam_swap32(physaddr | QH_HLP_TYP_QH); - arch_clean_dcache((uintptr_t)&qhead->hw, - (uintptr_t)&qhead->hw + sizeof(struct ehci_qh_s)); + up_clean_dcache((uintptr_t)&qhead->hw, + (uintptr_t)&qhead->hw + sizeof(struct ehci_qh_s)); } /**************************************************************************** @@ -1645,10 +1643,10 @@ static int sam_qtd_addbpl(struct sam_qtd_s *qtd, const void *buffer, size_t bufl */ #if 0 /* Didn't behave as expected */ - arch_flush_dcache((uintptr_t)buffer, (uintptr_t)buffer + buflen); + up_flush_dcache((uintptr_t)buffer, (uintptr_t)buffer + buflen); #else - arch_clean_dcache((uintptr_t)buffer, (uintptr_t)buffer + buflen); - arch_invalidate_dcache((uintptr_t)buffer, (uintptr_t)buffer + buflen); + up_clean_dcache((uintptr_t)buffer, (uintptr_t)buffer + buflen); + up_invalidate_dcache((uintptr_t)buffer, (uintptr_t)buffer + buflen); #endif /* Loop, adding the aligned physical addresses of the buffer to the buffer page @@ -2338,7 +2336,7 @@ static ssize_t sam_transfer_wait(struct sam_epinfo_s *epinfo) * invalid in this memory region. */ - arch_invalidate_dcache((uintptr_t)buffer, (uintptr_t)buffer + buflen); + up_invalidate_dcache((uintptr_t)buffer, (uintptr_t)buffer + buflen); } #endif @@ -2488,8 +2486,8 @@ static int sam_qtd_ioccheck(struct sam_qtd_s *qtd, uint32_t **bp, void *arg) /* Make sure we reload the QH from memory */ - arch_invalidate_dcache((uintptr_t)&qtd->hw, - (uintptr_t)&qtd->hw + sizeof(struct ehci_qtd_s)); + up_invalidate_dcache((uintptr_t)&qtd->hw, + (uintptr_t)&qtd->hw + sizeof(struct ehci_qtd_s)); sam_qtd_print(qtd); /* Remove the qTD from the list @@ -2539,8 +2537,8 @@ static int sam_qh_ioccheck(struct sam_qh_s *qh, uint32_t **bp, void *arg) /* Make sure we reload the QH from memory */ - arch_invalidate_dcache((uintptr_t)&qh->hw, - (uintptr_t)&qh->hw + sizeof(struct ehci_qh_s)); + up_invalidate_dcache((uintptr_t)&qh->hw, + (uintptr_t)&qh->hw + sizeof(struct ehci_qh_s)); sam_qh_print(qh); /* Get the endpoint info pointer from the extended QH data. Only the @@ -2593,7 +2591,7 @@ static int sam_qh_ioccheck(struct sam_qh_s *qh, uint32_t **bp, void *arg) */ **bp = qh->hw.hlp; - arch_clean_dcache((uintptr_t)*bp, (uintptr_t)*bp + sizeof(uint32_t)); + up_clean_dcache((uintptr_t)*bp, (uintptr_t)*bp + sizeof(uint32_t)); /* Check for errors, update the data toggle */ @@ -2692,8 +2690,8 @@ static int sam_qtd_cancel(struct sam_qtd_s *qtd, uint32_t **bp, void *arg) /* Make sure we reload the QH from memory */ - arch_invalidate_dcache((uintptr_t)&qtd->hw, - (uintptr_t)&qtd->hw + sizeof(struct ehci_qtd_s)); + up_invalidate_dcache((uintptr_t)&qtd->hw, + (uintptr_t)&qtd->hw + sizeof(struct ehci_qtd_s)); sam_qtd_print(qtd); /* Remove the qTD from the list @@ -2735,8 +2733,8 @@ static int sam_qh_cancel(struct sam_qh_s *qh, uint32_t **bp, void *arg) /* Make sure we reload the QH from memory */ - arch_invalidate_dcache((uintptr_t)&qh->hw, - (uintptr_t)&qh->hw + sizeof(struct ehci_qh_s)); + up_invalidate_dcache((uintptr_t)&qh->hw, + (uintptr_t)&qh->hw + sizeof(struct ehci_qh_s)); sam_qh_print(qh); /* Check if this is the QH that we are looking for */ @@ -2814,8 +2812,8 @@ static inline void sam_ioc_bottomhalf(void) /* Check the Asynchronous Queue */ /* Make sure that the head of the asynchronous queue is invalidated */ - arch_invalidate_dcache((uintptr_t)&g_asynchead.hw, - (uintptr_t)&g_asynchead.hw + sizeof(struct ehci_qh_s)); + up_invalidate_dcache((uintptr_t)&g_asynchead.hw, + (uintptr_t)&g_asynchead.hw + sizeof(struct ehci_qh_s)); /* Set the back pointer to the forward QH pointer of the asynchronous * queue head. @@ -2845,8 +2843,8 @@ static inline void sam_ioc_bottomhalf(void) /* Check the Interrupt Queue */ /* Make sure that the head of the interrupt queue is invalidated */ - arch_invalidate_dcache((uintptr_t)&g_intrhead.hw, - (uintptr_t)&g_intrhead.hw + sizeof(struct ehci_qh_s)); + up_invalidate_dcache((uintptr_t)&g_intrhead.hw, + (uintptr_t)&g_intrhead.hw + sizeof(struct ehci_qh_s)); /* Set the back pointer to the forward qTD pointer of the asynchronous * queue head. @@ -5012,8 +5010,8 @@ FAR struct usbhost_connection_s *sam_ehci_initialize(int controller) g_asynchead.hw.overlay.token = sam_swap32(QH_TOKEN_HALTED); g_asynchead.fqp = sam_swap32(QTD_NQP_T); - arch_clean_dcache((uintptr_t)&g_asynchead.hw, - (uintptr_t)&g_asynchead.hw + sizeof(struct ehci_qh_s)); + up_clean_dcache((uintptr_t)&g_asynchead.hw, + (uintptr_t)&g_asynchead.hw + sizeof(struct ehci_qh_s)); /* Set the Current Asynchronous List Address. */ @@ -5043,10 +5041,10 @@ FAR struct usbhost_connection_s *sam_ehci_initialize(int controller) /* Set the Periodic Frame List Base Address. */ - arch_clean_dcache((uintptr_t)&g_intrhead.hw, - (uintptr_t)&g_intrhead.hw + sizeof(struct ehci_qh_s)); - arch_clean_dcache((uintptr_t)g_framelist, - (uintptr_t)g_framelist + FRAME_LIST_SIZE * sizeof(uint32_t)); + up_clean_dcache((uintptr_t)&g_intrhead.hw, + (uintptr_t)&g_intrhead.hw + sizeof(struct ehci_qh_s)); + up_clean_dcache((uintptr_t)g_framelist, + (uintptr_t)g_framelist + FRAME_LIST_SIZE * sizeof(uint32_t)); physaddr = sam_physramaddr((uintptr_t)g_framelist); sam_putreg(sam_swap32(physaddr), &HCOR->periodiclistbase); diff --git a/arch/arm/src/sama5/sam_emaca.c b/arch/arm/src/sama5/sam_emaca.c index 033bc69c37..4447bddfe5 100644 --- a/arch/arm/src/sama5/sam_emaca.c +++ b/arch/arm/src/sama5/sam_emaca.c @@ -77,7 +77,6 @@ #include "up_arch.h" #include "up_internal.h" -#include "cache.h" #include "chip.h" #include "chip/sam_pinmap.h" @@ -785,7 +784,7 @@ static int sam_transmit(struct sam_emac_s *priv) virtaddr = sam_virtramaddr(txdesc->addr); memcpy((void *)virtaddr, dev->d_buf, dev->d_len); - arch_clean_dcache((uint32_t)virtaddr, (uint32_t)virtaddr + dev->d_len); + up_clean_dcache((uint32_t)virtaddr, (uint32_t)virtaddr + dev->d_len); } /* Update TX descriptor status. */ @@ -799,8 +798,8 @@ static int sam_transmit(struct sam_emac_s *priv) /* Update the descriptor status and flush the updated value to RAM */ txdesc->status = status; - arch_clean_dcache((uint32_t)txdesc, - (uint32_t)txdesc + sizeof(struct emac_txdesc_s)); + up_clean_dcache((uint32_t)txdesc, + (uint32_t)txdesc + sizeof(struct emac_txdesc_s)); /* Increment the head index */ @@ -1015,8 +1014,8 @@ static int sam_recvframe(struct sam_emac_s *priv) /* Invalidate the RX descriptor to force re-fetching from RAM */ - arch_invalidate_dcache((uintptr_t)rxdesc, - (uintptr_t)rxdesc + sizeof(struct emac_rxdesc_s)); + up_invalidate_dcache((uintptr_t)rxdesc, + (uintptr_t)rxdesc + sizeof(struct emac_rxdesc_s)); ninfo("rxndx: %d\n", rxndx); @@ -1039,9 +1038,9 @@ static int sam_recvframe(struct sam_emac_s *priv) /* Flush the modified RX descriptor to RAM */ - arch_clean_dcache((uintptr_t)rxdesc, - (uintptr_t)rxdesc + - sizeof(struct emac_rxdesc_s)); + up_clean_dcache((uintptr_t)rxdesc, + (uintptr_t)rxdesc + + sizeof(struct emac_rxdesc_s)); /* Increment the RX index */ @@ -1084,9 +1083,9 @@ static int sam_recvframe(struct sam_emac_s *priv) /* Flush the modified RX descriptor to RAM */ - arch_clean_dcache((uintptr_t)rxdesc, - (uintptr_t)rxdesc + - sizeof(struct emac_rxdesc_s)); + up_clean_dcache((uintptr_t)rxdesc, + (uintptr_t)rxdesc + + sizeof(struct emac_rxdesc_s)); /* Increment the RX index */ @@ -1114,7 +1113,7 @@ static int sam_recvframe(struct sam_emac_s *priv) physaddr = (uintptr_t)(rxdesc->addr & EMACRXD_ADDR_MASK); src = (const uint8_t *)sam_virtramaddr(physaddr); - arch_invalidate_dcache((uintptr_t)src, (uintptr_t)src + copylen); + up_invalidate_dcache((uintptr_t)src, (uintptr_t)src + copylen); /* And do the copy */ @@ -1144,9 +1143,9 @@ static int sam_recvframe(struct sam_emac_s *priv) /* Flush the modified RX descriptor to RAM */ - arch_clean_dcache((uintptr_t)rxdesc, - (uintptr_t)rxdesc + - sizeof(struct emac_rxdesc_s)); + up_clean_dcache((uintptr_t)rxdesc, + (uintptr_t)rxdesc + + sizeof(struct emac_rxdesc_s)); /* Increment the RX index */ @@ -1184,9 +1183,9 @@ static int sam_recvframe(struct sam_emac_s *priv) /* Flush the modified RX descriptor to RAM */ - arch_clean_dcache((uintptr_t)rxdesc, - (uintptr_t)rxdesc + - sizeof(struct emac_rxdesc_s)); + up_clean_dcache((uintptr_t)rxdesc, + (uintptr_t)rxdesc + + sizeof(struct emac_rxdesc_s)); priv->rxndx = rxndx; } @@ -1197,8 +1196,8 @@ static int sam_recvframe(struct sam_emac_s *priv) /* Invalidate the RX descriptor to force re-fetching from RAM */ - arch_invalidate_dcache((uintptr_t)rxdesc, - (uintptr_t)rxdesc + sizeof(struct emac_rxdesc_s)); + up_invalidate_dcache((uintptr_t)rxdesc, + (uintptr_t)rxdesc + sizeof(struct emac_rxdesc_s)); } /* isframe indicates that we have found a SOF. If we've received a SOF, @@ -1405,8 +1404,8 @@ static void sam_txdone(struct sam_emac_s *priv) /* Yes.. check the next buffer at the tail of the list */ txdesc = &priv->txdesc[priv->txtail]; - arch_invalidate_dcache((uintptr_t)txdesc, - (uintptr_t)txdesc + sizeof(struct emac_txdesc_s)); + up_invalidate_dcache((uintptr_t)txdesc, + (uintptr_t)txdesc + sizeof(struct emac_txdesc_s)); /* Is this TX descriptor still in use? */ @@ -1425,8 +1424,8 @@ static void sam_txdone(struct sam_emac_s *priv) sam_physramaddr((uintptr_t)txdesc) != sam_getreg(priv, SAM_EMAC_TBQP)) { txdesc->status = (uint32_t)EMACTXD_STA_USED; - arch_clean_dcache((uintptr_t)txdesc, - (uintptr_t)txdesc + sizeof(struct emac_txdesc_s)); + up_clean_dcache((uintptr_t)txdesc, + (uintptr_t)txdesc + sizeof(struct emac_txdesc_s)); } else #endif @@ -3324,9 +3323,9 @@ static void sam_txreset(struct sam_emac_s *priv) /* Flush the entire TX descriptor table to RAM */ - arch_clean_dcache((uintptr_t)txdesc, - (uintptr_t)txdesc + - CONFIG_SAMA5_EMAC_NTXBUFFERS * sizeof(struct emac_txdesc_s)); + up_clean_dcache((uintptr_t)txdesc, + (uintptr_t)txdesc + + CONFIG_SAMA5_EMAC_NTXBUFFERS * sizeof(struct emac_txdesc_s)); /* Set the Transmit Buffer Queue Pointer Register */ @@ -3388,9 +3387,9 @@ static void sam_rxreset(struct sam_emac_s *priv) /* Flush the entire RX descriptor table to RAM */ - arch_clean_dcache((uintptr_t)rxdesc, - (uintptr_t)rxdesc + - CONFIG_SAMA5_EMAC_NRXBUFFERS * sizeof(struct emac_rxdesc_s)); + up_clean_dcache((uintptr_t)rxdesc, + (uintptr_t)rxdesc + + CONFIG_SAMA5_EMAC_NRXBUFFERS * sizeof(struct emac_rxdesc_s)); /* Set the Receive Buffer Queue Pointer Register */ diff --git a/arch/arm/src/sama5/sam_emacb.c b/arch/arm/src/sama5/sam_emacb.c index 1fda59cb12..6807fa4f6a 100644 --- a/arch/arm/src/sama5/sam_emacb.c +++ b/arch/arm/src/sama5/sam_emacb.c @@ -91,7 +91,6 @@ #include "up_arch.h" #include "up_internal.h" -#include "cache.h" #include "chip.h" #include "chip/sam_pinmap.h" @@ -1120,7 +1119,7 @@ static int sam_transmit(struct sam_emac_s *priv) virtaddr = sam_virtramaddr(txdesc->addr); memcpy((void *)virtaddr, dev->d_buf, dev->d_len); - arch_clean_dcache((uint32_t)virtaddr, (uint32_t)virtaddr + dev->d_len); + up_clean_dcache((uint32_t)virtaddr, (uint32_t)virtaddr + dev->d_len); } /* Update TX descriptor status. */ @@ -1134,8 +1133,8 @@ static int sam_transmit(struct sam_emac_s *priv) /* Update the descriptor status and flush the updated value to RAM */ txdesc->status = status; - arch_clean_dcache((uint32_t)txdesc, - (uint32_t)txdesc + sizeof(struct emac_txdesc_s)); + up_clean_dcache((uint32_t)txdesc, + (uint32_t)txdesc + sizeof(struct emac_txdesc_s)); /* Increment the head index */ @@ -1351,8 +1350,8 @@ static int sam_recvframe(struct sam_emac_s *priv) /* Invalidate the RX descriptor to force re-fetching from RAM */ - arch_invalidate_dcache((uintptr_t)rxdesc, - (uintptr_t)rxdesc + sizeof(struct emac_rxdesc_s)); + up_invalidate_dcache((uintptr_t)rxdesc, + (uintptr_t)rxdesc + sizeof(struct emac_rxdesc_s)); ninfo("rxndx: %d\n", rxndx); while ((rxdesc->addr & EMACRXD_ADDR_OWNER) != 0) @@ -1374,9 +1373,9 @@ static int sam_recvframe(struct sam_emac_s *priv) /* Flush the modified RX descriptor to RAM */ - arch_clean_dcache((uintptr_t)rxdesc, - (uintptr_t)rxdesc + - sizeof(struct emac_rxdesc_s)); + up_clean_dcache((uintptr_t)rxdesc, + (uintptr_t)rxdesc + + sizeof(struct emac_rxdesc_s)); /* Increment the RX index */ @@ -1419,9 +1418,9 @@ static int sam_recvframe(struct sam_emac_s *priv) /* Flush the modified RX descriptor to RAM */ - arch_clean_dcache((uintptr_t)rxdesc, - (uintptr_t)rxdesc + - sizeof(struct emac_rxdesc_s)); + up_clean_dcache((uintptr_t)rxdesc, + (uintptr_t)rxdesc + + sizeof(struct emac_rxdesc_s)); /* Increment the RX index */ @@ -1449,7 +1448,7 @@ static int sam_recvframe(struct sam_emac_s *priv) physaddr = (uintptr_t)(rxdesc->addr & EMACRXD_ADDR_MASK); src = (const uint8_t *)sam_virtramaddr(physaddr); - arch_invalidate_dcache((uintptr_t)src, (uintptr_t)src + copylen); + up_invalidate_dcache((uintptr_t)src, (uintptr_t)src + copylen); /* And do the copy */ @@ -1479,9 +1478,9 @@ static int sam_recvframe(struct sam_emac_s *priv) /* Flush the modified RX descriptor to RAM */ - arch_clean_dcache((uintptr_t)rxdesc, - (uintptr_t)rxdesc + - sizeof(struct emac_rxdesc_s)); + up_clean_dcache((uintptr_t)rxdesc, + (uintptr_t)rxdesc + + sizeof(struct emac_rxdesc_s)); /* Increment the RX index */ @@ -1519,9 +1518,9 @@ static int sam_recvframe(struct sam_emac_s *priv) /* Flush the modified RX descriptor to RAM */ - arch_clean_dcache((uintptr_t)rxdesc, - (uintptr_t)rxdesc + - sizeof(struct emac_rxdesc_s)); + up_clean_dcache((uintptr_t)rxdesc, + (uintptr_t)rxdesc + + sizeof(struct emac_rxdesc_s)); priv->rxndx = rxndx; } @@ -1532,8 +1531,8 @@ static int sam_recvframe(struct sam_emac_s *priv) /* Invalidate the RX descriptor to force re-fetching from RAM */ - arch_invalidate_dcache((uintptr_t)rxdesc, - (uintptr_t)rxdesc + sizeof(struct emac_rxdesc_s)); + up_invalidate_dcache((uintptr_t)rxdesc, + (uintptr_t)rxdesc + sizeof(struct emac_rxdesc_s)); } /* isframe indicates that we have found a SOF. If we've received a SOF, @@ -1743,8 +1742,8 @@ static void sam_txdone(struct sam_emac_s *priv) /* Yes.. check the next buffer at the tail of the list */ txdesc = &priv->txdesc[priv->txtail]; - arch_invalidate_dcache((uintptr_t)txdesc, - (uintptr_t)txdesc + sizeof(struct emac_txdesc_s)); + up_invalidate_dcache((uintptr_t)txdesc, + (uintptr_t)txdesc + sizeof(struct emac_txdesc_s)); /* Is this TX descriptor still in use? */ @@ -1776,8 +1775,8 @@ static void sam_txdone(struct sam_emac_s *priv) sam_physramaddr((uintptr_t)txdesc) != sam_getreg(priv, SAM_EMAC_TBQB_OFFSET)) { txdesc->status = (uint32_t)EMACTXD_STA_USED; - arch_clean_dcache((uintptr_t)txdesc, - (uintptr_t)txdesc + sizeof(struct emac_txdesc_s)); + up_clean_dcache((uintptr_t)txdesc, + (uintptr_t)txdesc + sizeof(struct emac_txdesc_s)); } else #endif @@ -1794,8 +1793,8 @@ static void sam_txdone(struct sam_emac_s *priv) /* Make sure that the USED bit is set */ txdesc->status = (uint32_t)EMACTXD_STA_USED; - arch_clean_dcache((uintptr_t)txdesc, - (uintptr_t)txdesc + sizeof(struct emac_txdesc_s)); + up_clean_dcache((uintptr_t)txdesc, + (uintptr_t)txdesc + sizeof(struct emac_txdesc_s)); #endif /* Increment the tail index */ @@ -3884,9 +3883,9 @@ static void sam_txreset(struct sam_emac_s *priv) /* Flush the entire TX descriptor table to RAM */ - arch_clean_dcache((uintptr_t)txdesc, - (uintptr_t)txdesc + - priv->attr->ntxbuffers * sizeof(struct emac_txdesc_s)); + up_clean_dcache((uintptr_t)txdesc, + (uintptr_t)txdesc + + priv->attr->ntxbuffers * sizeof(struct emac_txdesc_s)); /* Set the Transmit Buffer Queue Pointer Register */ @@ -3948,9 +3947,9 @@ static void sam_rxreset(struct sam_emac_s *priv) /* Flush the entire RX descriptor table to RAM */ - arch_clean_dcache((uintptr_t)rxdesc, - (uintptr_t)rxdesc + - priv->attr->nrxbuffers * sizeof(struct emac_rxdesc_s)); + up_clean_dcache((uintptr_t)rxdesc, + (uintptr_t)rxdesc + + priv->attr->nrxbuffers * sizeof(struct emac_rxdesc_s)); /* Set the Receive Buffer Queue Pointer Register */ diff --git a/arch/arm/src/sama5/sam_gmac.c b/arch/arm/src/sama5/sam_gmac.c index 9206e13eaf..95ef7e65e3 100644 --- a/arch/arm/src/sama5/sam_gmac.c +++ b/arch/arm/src/sama5/sam_gmac.c @@ -74,7 +74,6 @@ #include "up_arch.h" #include "up_internal.h" -#include "cache.h" #include "chip.h" #include "chip/sam_pinmap.h" @@ -717,7 +716,7 @@ static int sam_transmit(struct sam_gmac_s *priv) virtaddr = sam_virtramaddr(txdesc->addr); memcpy((void *)virtaddr, dev->d_buf, dev->d_len); - arch_clean_dcache((uint32_t)virtaddr, (uint32_t)virtaddr + dev->d_len); + up_clean_dcache((uint32_t)virtaddr, (uint32_t)virtaddr + dev->d_len); } /* Update TX descriptor status. */ @@ -731,8 +730,8 @@ static int sam_transmit(struct sam_gmac_s *priv) /* Update the descriptor status and flush the updated value to RAM */ txdesc->status = status; - arch_clean_dcache((uint32_t)txdesc, - (uint32_t)txdesc + sizeof(struct gmac_txdesc_s)); + up_clean_dcache((uint32_t)txdesc, + (uint32_t)txdesc + sizeof(struct gmac_txdesc_s)); /* Increment the head index */ @@ -947,8 +946,8 @@ static int sam_recvframe(struct sam_gmac_s *priv) /* Invalidate the RX descriptor to force re-fetching from RAM */ - arch_invalidate_dcache((uintptr_t)rxdesc, - (uintptr_t)rxdesc + sizeof(struct gmac_rxdesc_s)); + up_invalidate_dcache((uintptr_t)rxdesc, + (uintptr_t)rxdesc + sizeof(struct gmac_rxdesc_s)); ninfo("rxndx: %d\n", rxndx); @@ -971,9 +970,9 @@ static int sam_recvframe(struct sam_gmac_s *priv) /* Flush the modified RX descriptor to RAM */ - arch_clean_dcache((uintptr_t)rxdesc, - (uintptr_t)rxdesc + - sizeof(struct gmac_rxdesc_s)); + up_clean_dcache((uintptr_t)rxdesc, + (uintptr_t)rxdesc + + sizeof(struct gmac_rxdesc_s)); /* Increment the RX index */ @@ -1016,9 +1015,9 @@ static int sam_recvframe(struct sam_gmac_s *priv) /* Flush the modified RX descriptor to RAM */ - arch_clean_dcache((uintptr_t)rxdesc, - (uintptr_t)rxdesc + - sizeof(struct gmac_rxdesc_s)); + up_clean_dcache((uintptr_t)rxdesc, + (uintptr_t)rxdesc + + sizeof(struct gmac_rxdesc_s)); /* Increment the RX index */ @@ -1046,7 +1045,7 @@ static int sam_recvframe(struct sam_gmac_s *priv) physaddr = (uintptr_t)(rxdesc->addr & GMACRXD_ADDR_MASK); src = (const uint8_t *)sam_virtramaddr(physaddr); - arch_invalidate_dcache((uintptr_t)src, (uintptr_t)src + copylen); + up_invalidate_dcache((uintptr_t)src, (uintptr_t)src + copylen); /* And do the copy */ @@ -1076,9 +1075,9 @@ static int sam_recvframe(struct sam_gmac_s *priv) /* Flush the modified RX descriptor to RAM */ - arch_clean_dcache((uintptr_t)rxdesc, - (uintptr_t)rxdesc + - sizeof(struct gmac_rxdesc_s)); + up_clean_dcache((uintptr_t)rxdesc, + (uintptr_t)rxdesc + + sizeof(struct gmac_rxdesc_s)); /* Increment the RX index */ @@ -1114,9 +1113,9 @@ static int sam_recvframe(struct sam_gmac_s *priv) /* Flush the modified RX descriptor to RAM */ - arch_clean_dcache((uintptr_t)rxdesc, - (uintptr_t)rxdesc + - sizeof(struct gmac_rxdesc_s)); + up_clean_dcache((uintptr_t)rxdesc, + (uintptr_t)rxdesc + + sizeof(struct gmac_rxdesc_s)); priv->rxndx = rxndx; } @@ -1127,8 +1126,8 @@ static int sam_recvframe(struct sam_gmac_s *priv) /* Invalidate the RX descriptor to force re-fetching from RAM */ - arch_invalidate_dcache((uintptr_t)rxdesc, - (uintptr_t)rxdesc + sizeof(struct gmac_rxdesc_s)); + up_invalidate_dcache((uintptr_t)rxdesc, + (uintptr_t)rxdesc + sizeof(struct gmac_rxdesc_s)); } /* isframe indicates that we have found a SOF. If we've received a SOF, @@ -1335,8 +1334,8 @@ static void sam_txdone(struct sam_gmac_s *priv) /* Yes.. check the next buffer at the tail of the list */ txdesc = &priv->txdesc[priv->txtail]; - arch_invalidate_dcache((uintptr_t)txdesc, - (uintptr_t)txdesc + sizeof(struct gmac_txdesc_s)); + up_invalidate_dcache((uintptr_t)txdesc, + (uintptr_t)txdesc + sizeof(struct gmac_txdesc_s)); /* Is this TX descriptor still in use? */ @@ -1354,8 +1353,8 @@ static void sam_txdone(struct sam_gmac_s *priv) sam_physramaddr((uintptr_t)txdesc) != sam_getreg(priv, SAM_GMAC_TBQB)) { txdesc->status = (uint32_t)GMACTXD_STA_USED; - arch_clean_dcache((uintptr_t)txdesc, - (uintptr_t)txdesc + sizeof(struct gmac_txdesc_s)); + up_clean_dcache((uintptr_t)txdesc, + (uintptr_t)txdesc + sizeof(struct gmac_txdesc_s)); } else { @@ -3372,9 +3371,9 @@ static void sam_txreset(struct sam_gmac_s *priv) /* Flush the entire TX descriptor table to RAM */ - arch_clean_dcache((uintptr_t)txdesc, - (uintptr_t)txdesc + - CONFIG_SAMA5_GMAC_NTXBUFFERS * sizeof(struct gmac_txdesc_s)); + up_clean_dcache((uintptr_t)txdesc, + (uintptr_t)txdesc + + CONFIG_SAMA5_GMAC_NTXBUFFERS * sizeof(struct gmac_txdesc_s)); /* Set the Transmit Buffer Queue Base Register */ @@ -3436,9 +3435,9 @@ static void sam_rxreset(struct sam_gmac_s *priv) /* Flush the entire RX descriptor table to RAM */ - arch_clean_dcache((uintptr_t)rxdesc, - (uintptr_t)rxdesc + - CONFIG_SAMA5_GMAC_NRXBUFFERS * sizeof(struct gmac_rxdesc_s)); + up_clean_dcache((uintptr_t)rxdesc, + (uintptr_t)rxdesc + + CONFIG_SAMA5_GMAC_NRXBUFFERS * sizeof(struct gmac_rxdesc_s)); /* Set the Receive Buffer Queue Base Register */ diff --git a/arch/arm/src/sama5/sam_irq.c b/arch/arm/src/sama5/sam_irq.c index fbdc1eda5c..44cce23e13 100644 --- a/arch/arm/src/sama5/sam_irq.c +++ b/arch/arm/src/sama5/sam_irq.c @@ -55,7 +55,7 @@ #include "chip.h" #include "mmu.h" -#include "cache.h" +#include "cp15_cacheops.h" #include "sctlr.h" #include "chip/sam_aic.h" #include "chip/sam_matrix.h" diff --git a/arch/arm/src/sama5/sam_nand.c b/arch/arm/src/sama5/sam_nand.c index a0fb369ce1..3f1bc5bd84 100644 --- a/arch/arm/src/sama5/sam_nand.c +++ b/arch/arm/src/sama5/sam_nand.c @@ -69,7 +69,6 @@ #include #include "up_arch.h" -#include "cache.h" #include "sam_memories.h" #include "sam_dmac.h" @@ -1294,7 +1293,7 @@ static int nand_dma_read(struct sam_nandcs_s *priv, * that memory will be re-cached after the DMA completes). */ - arch_invalidate_dcache(vdest, vdest + nbytes); + up_invalidate_dcache(vdest, vdest + nbytes); /* DMA will need physical addresses. */ @@ -1379,7 +1378,7 @@ static int nand_dma_write(struct sam_nandcs_s *priv, * the data to be transferred lies in physical memory */ - arch_clean_dcache(vsrc, vsrc + nbytes); + up_clean_dcache(vsrc, vsrc + nbytes); /* DMA will need physical addresses. */ diff --git a/arch/arm/src/sama5/sam_ohci.c b/arch/arm/src/sama5/sam_ohci.c index dcd66b38a3..ce5bbf8722 100644 --- a/arch/arm/src/sama5/sam_ohci.c +++ b/arch/arm/src/sama5/sam_ohci.c @@ -65,7 +65,6 @@ #include "up_arch.h" #include "up_internal.h" -#include "cache.h" #include "chip.h" #include "sam_periphclks.h" #include "sam_memories.h" @@ -851,7 +850,7 @@ static int sam_addctrled(struct sam_ed_s *ed) /* Add the new control ED to the head of the control list */ ed->hw.nexted = sam_getreg(SAM_USBHOST_CTRLHEADED); - arch_clean_dcache((uintptr_t)ed, (uintptr_t)ed + sizeof(struct ohci_ed_s)); + up_clean_dcache((uintptr_t)ed, (uintptr_t)ed + sizeof(struct ohci_ed_s)); physed = sam_physramaddr((uintptr_t)ed); sam_putreg((uint32_t)physed, SAM_USBHOST_CTRLHEADED); @@ -921,8 +920,8 @@ static inline int sam_remctrled(struct sam_ed_s *ed) */ prev->hw.nexted = ed->hw.nexted; - arch_clean_dcache((uintptr_t)prev, - (uintptr_t)prev + sizeof(struct sam_ed_s)); + up_clean_dcache((uintptr_t)prev, + (uintptr_t)prev + sizeof(struct sam_ed_s)); } } @@ -969,7 +968,7 @@ static inline int sam_addbulked(struct sam_ed_s *ed) /* Add the new bulk ED to the head of the bulk list */ ed->hw.nexted = sam_getreg(SAM_USBHOST_BULKHEADED); - arch_clean_dcache((uintptr_t)ed, (uintptr_t)ed + sizeof(struct ohci_ed_s)); + up_clean_dcache((uintptr_t)ed, (uintptr_t)ed + sizeof(struct ohci_ed_s)); physed = sam_physramaddr((uintptr_t)ed); sam_putreg((uint32_t)physed, SAM_USBHOST_BULKHEADED); @@ -1043,8 +1042,8 @@ static inline int sam_rembulked(struct sam_ed_s *ed) */ prev->hw.nexted = ed->hw.nexted; - arch_clean_dcache((uintptr_t)prev, - (uintptr_t)prev + sizeof(struct sam_ed_s)); + up_clean_dcache((uintptr_t)prev, + (uintptr_t)prev + sizeof(struct sam_ed_s)); } } @@ -1133,7 +1132,7 @@ static void sam_setinttab(uint32_t value, unsigned int interval, unsigned int of /* Make sure that the modified table value is flushed to RAM */ inttbl = (uintptr_t)g_hcca.inttbl; - arch_clean_dcache(inttbl, inttbl + sizeof(uint32_t)*HCCA_INTTBL_WSIZE); + up_clean_dcache(inttbl, inttbl + sizeof(uint32_t)*HCCA_INTTBL_WSIZE); } #endif @@ -1236,7 +1235,7 @@ static inline int sam_addinted(const struct usbhost_epdesc_s *epdesc, */ ed->hw.nexted = physhead; - arch_clean_dcache((uintptr_t)ed, (uintptr_t)ed + sizeof(struct ohci_ed_s)); + up_clean_dcache((uintptr_t)ed, (uintptr_t)ed + sizeof(struct ohci_ed_s)); physed = sam_physramaddr((uintptr_t)ed); sam_setinttab((uint32_t)physed, interval, offset); @@ -1473,8 +1472,8 @@ static int sam_enqueuetd(struct sam_rhport_s *rhport, struct sam_eplist_s *eplis /* Skip processing of this ED while we modify the TD list. */ ed->hw.ctrl |= ED_CONTROL_K; - arch_clean_dcache((uintptr_t)ed, - (uintptr_t)ed + sizeof(struct ohci_ed_s)); + up_clean_dcache((uintptr_t)ed, + (uintptr_t)ed + sizeof(struct ohci_ed_s)); /* Get the tail ED for this hub port */ @@ -1513,20 +1512,20 @@ static int sam_enqueuetd(struct sam_rhport_s *rhport, struct sam_eplist_s *eplis if (buffer && buflen > 0) { - arch_clean_dcache((uintptr_t)buffer, - (uintptr_t)buffer + buflen); + up_clean_dcache((uintptr_t)buffer, + (uintptr_t)buffer + buflen); } - arch_clean_dcache((uintptr_t)tdtail, - (uintptr_t)tdtail + sizeof(struct ohci_gtd_s)); - arch_clean_dcache((uintptr_t)td, - (uintptr_t)td + sizeof(struct ohci_gtd_s)); + up_clean_dcache((uintptr_t)tdtail, + (uintptr_t)tdtail + sizeof(struct ohci_gtd_s)); + up_clean_dcache((uintptr_t)td, + (uintptr_t)td + sizeof(struct ohci_gtd_s)); /* Resume processing of this ED */ ed->hw.ctrl &= ~ED_CONTROL_K; - arch_clean_dcache((uintptr_t)ed, - (uintptr_t)ed + sizeof(struct ohci_ed_s)); + up_clean_dcache((uintptr_t)ed, + (uintptr_t)ed + sizeof(struct ohci_ed_s)); ret = OK; } @@ -1606,10 +1605,10 @@ static int sam_ep0enqueue(struct sam_rhport_s *rhport) /* Flush the affected control ED and tail TD to RAM */ - arch_clean_dcache((uintptr_t)edctrl, - (uintptr_t)edctrl + sizeof(struct ohci_ed_s)); - arch_clean_dcache((uintptr_t)tdtail, - (uintptr_t)tdtail + sizeof(struct ohci_gtd_s)); + up_clean_dcache((uintptr_t)edctrl, + (uintptr_t)edctrl + sizeof(struct ohci_ed_s)); + up_clean_dcache((uintptr_t)tdtail, + (uintptr_t)tdtail + sizeof(struct ohci_gtd_s)); /* Add the ED to the control list */ @@ -1684,8 +1683,8 @@ static void sam_ep0dequeue(struct sam_eplist_s *ep0) /* Flush the modified ED to RAM */ - arch_clean_dcache((uintptr_t)preved, - (uintptr_t)preved + sizeof(struct ohci_ed_s)); + up_clean_dcache((uintptr_t)preved, + (uintptr_t)preved + sizeof(struct ohci_ed_s)); } else { @@ -2106,11 +2105,11 @@ static void sam_wdh_bottomhalf(void) /* Invalidate D-cache to force re-reading of the Done Head */ #if 0 /* Apparently insufficient */ - arch_invalidate_dcache((uintptr_t)&g_hcca.donehead, - (uintptr_t)&g_hcca.donehead + sizeof(uint32_t)); + up_invalidate_dcache((uintptr_t)&g_hcca.donehead, + (uintptr_t)&g_hcca.donehead + sizeof(uint32_t)); #else - arch_invalidate_dcache((uintptr_t)&g_hcca, - (uintptr_t)&g_hcca + sizeof(struct ohci_hcca_s)); + up_invalidate_dcache((uintptr_t)&g_hcca, + (uintptr_t)&g_hcca + sizeof(struct ohci_hcca_s)); #endif /* Now read the done head. */ @@ -2126,8 +2125,8 @@ static void sam_wdh_bottomhalf(void) * reloaded from memory. */ - arch_invalidate_dcache((uintptr_t)td, - (uintptr_t)td + sizeof(struct ohci_gtd_s)); + up_invalidate_dcache((uintptr_t)td, + (uintptr_t)td + sizeof(struct ohci_gtd_s)); /* Get the ED in which this TD was enqueued */ @@ -2153,8 +2152,8 @@ static void sam_wdh_bottomhalf(void) * memory. */ - arch_invalidate_dcache((uintptr_t)ed, - (uintptr_t)ed + sizeof(struct ohci_ed_s)); + up_invalidate_dcache((uintptr_t)ed, + (uintptr_t)ed + sizeof(struct ohci_ed_s)); /* Save the condition code from the (single) TD status/control * word. @@ -2605,8 +2604,8 @@ static int sam_ep0configure(struct usbhost_driver_s *drvr, usbhost_ep_t ep0, /* Flush the modified control ED to RAM */ - arch_clean_dcache((uintptr_t)edctrl, - (uintptr_t)edctrl + sizeof(struct ohci_ed_s)); + up_clean_dcache((uintptr_t)edctrl, + (uintptr_t)edctrl + sizeof(struct ohci_ed_s)); sam_givesem(&g_ohci.exclsem); usbhost_vtrace2(OHCI_VTRACE2_EP0CTRLED, RHPORT(rhport), (uint16_t)edctrl->hw.ctrl); @@ -2764,10 +2763,10 @@ static int sam_epalloc(struct usbhost_driver_s *drvr, /* Make sure these settings are flushed to RAM */ - arch_clean_dcache((uintptr_t)ed, - (uintptr_t)ed + sizeof(struct ohci_ed_s)); - arch_clean_dcache((uintptr_t)td, - (uintptr_t)td + sizeof(struct ohci_gtd_s)); + up_clean_dcache((uintptr_t)ed, + (uintptr_t)ed + sizeof(struct ohci_ed_s)); + up_clean_dcache((uintptr_t)td, + (uintptr_t)td + sizeof(struct ohci_gtd_s)); /* Now add the endpoint descriptor to the appropriate list */ @@ -3142,7 +3141,7 @@ static int sam_ctrlin(struct usbhost_driver_s *drvr, usbhost_ep_t ep0, */ sam_givesem(&g_ohci.exclsem); - arch_invalidate_dcache((uintptr_t)buffer, (uintptr_t)buffer + len); + up_invalidate_dcache((uintptr_t)buffer, (uintptr_t)buffer + len); return ret; } @@ -3383,8 +3382,8 @@ static ssize_t sam_transfer(struct usbhost_driver_s *drvr, usbhost_ep_t ep, /* Invalidate the D cache to force the ED to be reloaded from RAM */ - arch_invalidate_dcache((uintptr_t)ed, - (uintptr_t)ed + sizeof(struct ohci_ed_s)); + up_invalidate_dcache((uintptr_t)ed, + (uintptr_t)ed + sizeof(struct ohci_ed_s)); /* Check the TD completion status bits */ @@ -3396,8 +3395,8 @@ static ssize_t sam_transfer(struct usbhost_driver_s *drvr, usbhost_ep_t ep, if (in) { - arch_invalidate_dcache((uintptr_t)buffer, - (uintptr_t)buffer + buflen); + up_invalidate_dcache((uintptr_t)buffer, + (uintptr_t)buffer + buflen); } nbytes = eplist->xfrd; @@ -3467,8 +3466,8 @@ static void sam_asynch_completion(struct sam_eplist_s *eplist) /* Invalidate the D cache to force the ED to be reloaded from RAM */ - arch_invalidate_dcache((uintptr_t)ed, - (uintptr_t)ed + sizeof(struct ohci_ed_s)); + up_invalidate_dcache((uintptr_t)ed, + (uintptr_t)ed + sizeof(struct ohci_ed_s)); /* Check the TD completion status bits */ @@ -3481,7 +3480,7 @@ static void sam_asynch_completion(struct sam_eplist_s *eplist) if ((ed->hw.ctrl & ED_CONTROL_D_MASK) == ED_CONTROL_D_IN) { uintptr_t buffaddr = (uintptr_t)eplist->buffer; - arch_invalidate_dcache(buffaddr, buffaddr + eplist->buflen); + up_invalidate_dcache(buffaddr, buffaddr + eplist->buflen); } nbytes = eplist->xfrd; @@ -3688,8 +3687,8 @@ static int sam_cancel(struct usbhost_driver_s *drvr, usbhost_ep_t ep) paddr = sam_physramaddr((uintptr_t)eplist->tail); ed->hw.headp = paddr; - arch_clean_dcache((uintptr_t)ed, - (uintptr_t)ed + sizeof(struct ohci_ed_s)); + up_clean_dcache((uintptr_t)ed, + (uintptr_t)ed + sizeof(struct ohci_ed_s)); /* Re-enable bulk list processing, if it was enabled before */ @@ -3706,8 +3705,8 @@ static int sam_cancel(struct usbhost_driver_s *drvr, usbhost_ep_t ep) paddr = sam_physramaddr((uintptr_t)eplist->tail); ed->hw.headp = paddr; - arch_clean_dcache((uintptr_t)ed, - (uintptr_t)ed + sizeof(struct ohci_ed_s)); + up_clean_dcache((uintptr_t)ed, + (uintptr_t)ed + sizeof(struct ohci_ed_s)); } /* Free all transfer descriptors that were connected to the ED. In some @@ -3989,8 +3988,8 @@ struct usbhost_connection_s *sam_ohci_initialize(int controller) memset((void *)&g_hcca, 0, sizeof(struct ohci_hcca_s)); - arch_clean_dcache((uint32_t)&g_hcca, - (uint32_t)&g_hcca + sizeof(struct ohci_hcca_s)); + up_clean_dcache((uint32_t)&g_hcca, + (uint32_t)&g_hcca + sizeof(struct ohci_hcca_s)); /* Initialize user-configurable EDs */ diff --git a/arch/arm/src/sama5/sam_pgalloc.c b/arch/arm/src/sama5/sam_pgalloc.c index 5fbaac8a95..774518f659 100644 --- a/arch/arm/src/sama5/sam_pgalloc.c +++ b/arch/arm/src/sama5/sam_pgalloc.c @@ -49,7 +49,6 @@ #include "chip.h" #include "mmu.h" -#include "cache.h" #include "sam_pgalloc.h" diff --git a/arch/arm/src/sama5/sam_ssc.c b/arch/arm/src/sama5/sam_ssc.c index 0515cca8a7..5da89da2f9 100644 --- a/arch/arm/src/sama5/sam_ssc.c +++ b/arch/arm/src/sama5/sam_ssc.c @@ -62,7 +62,6 @@ #include "up_internal.h" #include "up_arch.h" -#include "cache.h" #include "chip.h" #include "sam_pio.h" @@ -1339,8 +1338,8 @@ static int ssc_rxdma_setup(struct sam_ssc_s *priv) * DMA buffer after starting the DMA transfer. */ - arch_invalidate_dcache((uintptr_t)apb->samp, - (uintptr_t)apb->samp + apb->nmaxbytes); + up_invalidate_dcache((uintptr_t)apb->samp, + (uintptr_t)apb->samp + apb->nmaxbytes); } #if 1 /* REVISIT: Chained RX transfers */ @@ -1754,7 +1753,7 @@ static int ssc_txdma_setup(struct sam_ssc_s *priv) * before starting the DMA. */ - arch_clean_dcache(samp, samp + nbytes); + up_clean_dcache(samp, samp + nbytes); } #if 1 /* REVISIT: Chained TX transfers */ while (0); diff --git a/arch/arm/src/sama5/sam_udphs.c b/arch/arm/src/sama5/sam_udphs.c index 1c04600e1a..5c1edc53fe 100644 --- a/arch/arm/src/sama5/sam_udphs.c +++ b/arch/arm/src/sama5/sam_udphs.c @@ -66,7 +66,6 @@ #include "up_arch.h" #include "up_internal.h" -#include "cache.h" #include "sam_periphclks.h" #include "sam_memories.h" @@ -904,7 +903,7 @@ static void sam_dma_single(uint8_t epno, struct sam_req_s *privreq, /* Flush the contents of the DMA buffer to RAM */ buffer = (uintptr_t)&privreq->req.buf[privreq->req.xfrd]; - arch_clean_dcache(buffer, buffer + privreq->inflight); + up_clean_dcache(buffer, buffer + privreq->inflight); /* Set up the DMA */ @@ -2414,7 +2413,7 @@ static void sam_dma_interrupt(struct sam_usbdev_s *priv, int epno) DEBUGASSERT(USB_ISEPOUT(privep->ep.eplog)); buf = &privreq->req.buf[privreq->req.xfrd]; - arch_invalidate_dcache((uintptr_t)buf, (uintptr_t)buf + xfrsize); + up_invalidate_dcache((uintptr_t)buf, (uintptr_t)buf + xfrsize); /* Complete this transfer, return the request to the class * implementation, and try to start the next, queue read request. @@ -2470,7 +2469,7 @@ static void sam_dma_interrupt(struct sam_usbdev_s *priv, int epno) */ buf = &privreq->req.buf[privreq->req.xfrd]; - arch_invalidate_dcache((uintptr_t)buf, (uintptr_t)buf + xfrsize); + up_invalidate_dcache((uintptr_t)buf, (uintptr_t)buf + xfrsize); /* Complete this transfer, return the request to the class * implementation, and try to start the next, queue read request. diff --git a/arch/arm/src/sama5/sam_xdmac.c b/arch/arm/src/sama5/sam_xdmac.c index 881c7a39e8..e903b0dd03 100644 --- a/arch/arm/src/sama5/sam_xdmac.c +++ b/arch/arm/src/sama5/sam_xdmac.c @@ -50,7 +50,6 @@ #include #include "up_arch.h" -#include "cache.h" #include "up_internal.h" #include "sched/sched.h" @@ -1399,8 +1398,8 @@ sam_allocdesc(struct sam_xdmach_s *xdmach, struct chnext_view1_s *prev, * that hardware will be accessing the descriptor via DMA. */ - arch_clean_dcache((uintptr_t)descr, - (uintptr_t)descr + sizeof(struct chnext_view1_s)); + up_clean_dcache((uintptr_t)descr, + (uintptr_t)descr + sizeof(struct chnext_view1_s)); break; } } @@ -1803,7 +1802,7 @@ static void sam_dmaterminate(struct sam_xdmach_s *xdmach, int result) if (xdmach->rx) { - arch_invalidate_dcache(xdmach->rxaddr, xdmach->rxaddr + xdmach->rxsize); + up_invalidate_dcache(xdmach->rxaddr, xdmach->rxaddr + xdmach->rxsize); } /* Perform the DMA complete callback */ @@ -2223,7 +2222,7 @@ int sam_dmatxsetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr, /* Clean caches associated with the DMA memory */ - arch_clean_dcache(maddr, maddr + nbytes); + up_clean_dcache(maddr, maddr + nbytes); return ret; } @@ -2304,7 +2303,7 @@ int sam_dmarxsetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr, /* Clean caches associated with the DMA memory */ - arch_clean_dcache(maddr, maddr + nbytes); + up_clean_dcache(maddr, maddr + nbytes); return ret; } diff --git a/arch/arm/src/samv7/Make.defs b/arch/arm/src/samv7/Make.defs index a5ff18e2f1..448d56b988 100644 --- a/arch/arm/src/samv7/Make.defs +++ b/arch/arm/src/samv7/Make.defs @@ -72,14 +72,7 @@ CMN_ASRCS += up_exception.S endif CMN_CSRCS += up_vectors.c -ifeq ($(CONFIG_ARMV7M_DCACHE),y) -CMN_CSRCS += arch_enable_dcache.c arch_disable_dcache.c -CMN_CSRCS += arch_invalidate_dcache.c arch_invalidate_dcache_all.c -ifneq ($(CONFIG_ARMV7M_DCACHE_WRITETHROUGH),y) -CMN_CSRCS += arch_clean_dcache.c arch_clean_dcache_all.c -CMN_CSRCS += arch_flush_dcache.c arch_flush_dcache_all.c -endif -endif +CMN_CSRCS += up_cache.c ifeq ($(CONFIG_ARCH_FPU),y) CMN_ASRCS += up_fpu.S @@ -101,12 +94,6 @@ endif endif endif -ifeq ($(CONFIG_ELF),y) -CMN_CSRCS += up_coherent_dcache.c -else ifeq ($(CONFIG_MODULE),y) -CMN_CSRCS += up_coherent_dcache.c -endif - ifeq ($(CONFIG_STACK_COLORATION),y) CMN_CSRCS += up_checkstack.c endif diff --git a/arch/arm/src/samv7/sam_dac.c b/arch/arm/src/samv7/sam_dac.c index 815a5e22d8..74b3f97f69 100644 --- a/arch/arm/src/samv7/sam_dac.c +++ b/arch/arm/src/samv7/sam_dac.c @@ -54,7 +54,6 @@ #include "up_internal.h" #include "up_arch.h" -#include "cache.h" #include "chip/sam_dacc.h" #include "chip/sam_pmc.h" diff --git a/arch/arm/src/samv7/sam_emac.c b/arch/arm/src/samv7/sam_emac.c index 1bc31289e0..4432bf7445 100644 --- a/arch/arm/src/samv7/sam_emac.c +++ b/arch/arm/src/samv7/sam_emac.c @@ -83,7 +83,6 @@ #include "up_arch.h" #include "up_internal.h" -#include "cache.h" #include "chip/sam_pinmap.h" #include "chip/sam_chipid.h" @@ -1419,8 +1418,8 @@ static int sam_transmit(struct sam_emac_s *priv, int qid) */ memcpy((void *)txdesc->addr, dev->d_buf, dev->d_len); - arch_clean_dcache((uint32_t)txdesc->addr, - (uint32_t)txdesc->addr + dev->d_len); + up_clean_dcache((uint32_t)txdesc->addr, + (uint32_t)txdesc->addr + dev->d_len); } /* Update TX descriptor status (with USED=0). */ @@ -1434,8 +1433,8 @@ static int sam_transmit(struct sam_emac_s *priv, int qid) /* Update the descriptor status and flush the updated value to RAM */ txdesc->status = status; - arch_clean_dcache((uint32_t)txdesc, - (uint32_t)txdesc + sizeof(struct emac_txdesc_s)); + up_clean_dcache((uint32_t)txdesc, + (uint32_t)txdesc + sizeof(struct emac_txdesc_s)); /* Increment the head index */ @@ -1665,8 +1664,8 @@ static int sam_recvframe(struct sam_emac_s *priv, int qid) /* Invalidate the RX descriptor to force re-fetching from RAM. */ - arch_invalidate_dcache((uintptr_t)rxdesc, - (uintptr_t)rxdesc + sizeof(struct emac_rxdesc_s)); + up_invalidate_dcache((uintptr_t)rxdesc, + (uintptr_t)rxdesc + sizeof(struct emac_rxdesc_s)); ninfo("Entry rxndx[%d]: %d\n", qid, rxndx); @@ -1693,9 +1692,9 @@ static int sam_recvframe(struct sam_emac_s *priv, int qid) /* Flush the modified RX descriptor to RAM */ - arch_clean_dcache((uintptr_t)rxdesc, - (uintptr_t)rxdesc + - sizeof(struct emac_rxdesc_s)); + up_clean_dcache((uintptr_t)rxdesc, + (uintptr_t)rxdesc + + sizeof(struct emac_rxdesc_s)); /* Increment the RX index to the start fragment */ @@ -1741,9 +1740,9 @@ static int sam_recvframe(struct sam_emac_s *priv, int qid) /* Flush the modified RX descriptor to RAM */ - arch_clean_dcache((uintptr_t)rxdesc, - (uintptr_t)rxdesc + - sizeof(struct emac_rxdesc_s)); + up_clean_dcache((uintptr_t)rxdesc, + (uintptr_t)rxdesc + + sizeof(struct emac_rxdesc_s)); /* Increment the RX index */ @@ -1771,7 +1770,7 @@ static int sam_recvframe(struct sam_emac_s *priv, int qid) */ src = (const uint8_t *)(rxdesc->addr & EMACRXD_ADDR_MASK); - arch_invalidate_dcache((uintptr_t)src, (uintptr_t)src + copylen); + up_invalidate_dcache((uintptr_t)src, (uintptr_t)src + copylen); /* Copy the data from the driver managed the ring buffer. If we * wanted to support zero copy transfers, we would need to make @@ -1805,9 +1804,9 @@ static int sam_recvframe(struct sam_emac_s *priv, int qid) /* Flush the modified RX descriptor to RAM */ - arch_clean_dcache((uintptr_t)rxdesc, - (uintptr_t)rxdesc + - sizeof(struct emac_rxdesc_s)); + up_clean_dcache((uintptr_t)rxdesc, + (uintptr_t)rxdesc + + sizeof(struct emac_rxdesc_s)); /* Increment the RX index of the descriptor that was just * released. @@ -1850,9 +1849,9 @@ static int sam_recvframe(struct sam_emac_s *priv, int qid) /* Flush the modified RX descriptor to RAM */ - arch_clean_dcache((uintptr_t)rxdesc, - (uintptr_t)rxdesc + - sizeof(struct emac_rxdesc_s)); + up_clean_dcache((uintptr_t)rxdesc, + (uintptr_t)rxdesc + + sizeof(struct emac_rxdesc_s)); /* rxndx already points to the next fragment to be examined. * Use it to update the candidate Start-of-Frame. @@ -1869,8 +1868,8 @@ static int sam_recvframe(struct sam_emac_s *priv, int qid) /* Invalidate the RX descriptor to force re-fetching from RAM */ - arch_invalidate_dcache((uintptr_t)rxdesc, - (uintptr_t)rxdesc + sizeof(struct emac_rxdesc_s)); + up_invalidate_dcache((uintptr_t)rxdesc, + (uintptr_t)rxdesc + sizeof(struct emac_rxdesc_s)); } /* isframe indicates that we have found a SOF. If we've received a SOF, @@ -2090,8 +2089,8 @@ static void sam_txdone(struct sam_emac_s *priv, int qid) /* Yes.. check the next buffer at the tail of the list */ txdesc = &xfrq->txdesc[tail]; - arch_invalidate_dcache((uintptr_t)txdesc, - (uintptr_t)txdesc + sizeof(struct emac_txdesc_s)); + up_invalidate_dcache((uintptr_t)txdesc, + (uintptr_t)txdesc + sizeof(struct emac_txdesc_s)); /* Break out of the loop if frame has not yet been sent. On TX * completion, the GMAC sets the USED bit only into the very first @@ -2123,8 +2122,8 @@ static void sam_txdone(struct sam_emac_s *priv, int qid) /* Get the next TX descriptor */ txdesc = &xfrq->txdesc[tail]; - arch_invalidate_dcache((uintptr_t)txdesc, - (uintptr_t)txdesc + sizeof(struct emac_txdesc_s)); + up_invalidate_dcache((uintptr_t)txdesc, + (uintptr_t)txdesc + sizeof(struct emac_txdesc_s)); } /* Go to first buffer of the next frame */ @@ -2218,8 +2217,8 @@ static void sam_txerr_interrupt(FAR struct sam_emac_s *priv, int qid) /* Make H/W updates to the TX descriptor visible to the CPU. */ - arch_invalidate_dcache((uintptr_t)txdesc, - (uintptr_t)txdesc + sizeof(struct emac_txdesc_s)); + up_invalidate_dcache((uintptr_t)txdesc, + (uintptr_t)txdesc + sizeof(struct emac_txdesc_s)); /* Go to the last buffer descriptor of the frame */ @@ -2236,8 +2235,8 @@ static void sam_txerr_interrupt(FAR struct sam_emac_s *priv, int qid) /* Get the next TX descriptor */ txdesc = &xfrq->txdesc[tail]; - arch_invalidate_dcache((uintptr_t)txdesc, - (uintptr_t)txdesc + sizeof(struct emac_txdesc_s)); + up_invalidate_dcache((uintptr_t)txdesc, + (uintptr_t)txdesc + sizeof(struct emac_txdesc_s)); } /* Go to first buffer of the next frame */ @@ -4387,9 +4386,9 @@ static void sam_txreset(struct sam_emac_s *priv, int qid) /* Flush the entire TX descriptor table to RAM */ - arch_clean_dcache((uintptr_t)txdesc, - (uintptr_t)txdesc + - xfrq->ntxbuffers * sizeof(struct emac_txdesc_s)); + up_clean_dcache((uintptr_t)txdesc, + (uintptr_t)txdesc + + xfrq->ntxbuffers * sizeof(struct emac_txdesc_s)); /* Set the Transmit Buffer Queue Pointer Register */ @@ -4458,9 +4457,9 @@ static void sam_rxreset(struct sam_emac_s *priv, int qid) /* Flush the entire RX descriptor table to RAM */ - arch_clean_dcache((uintptr_t)rxdesc, - (uintptr_t)rxdesc + - xfrq->nrxbuffers * sizeof(struct emac_rxdesc_s)); + up_clean_dcache((uintptr_t)rxdesc, + (uintptr_t)rxdesc + + xfrq->nrxbuffers * sizeof(struct emac_rxdesc_s)); /* Set the Receive Buffer Queue Pointer Register */ diff --git a/arch/arm/src/samv7/sam_mcan.c b/arch/arm/src/samv7/sam_mcan.c index e4ce46aed5..f8d0a76c42 100644 --- a/arch/arm/src/samv7/sam_mcan.c +++ b/arch/arm/src/samv7/sam_mcan.c @@ -58,7 +58,6 @@ #include #include -#include "cache.h" #include "up_internal.h" #include "up_arch.h" @@ -1815,7 +1814,7 @@ static int mcan_add_extfilter(FAR struct sam_mcan_s *priv, /* Flush the filter entry into physical RAM */ - arch_clean_dcache((uintptr_t)extfilter, (uintptr_t)exfilter + 8); + up_clean_dcache((uintptr_t)extfilter, (uintptr_t)exfilter + 8); /* Is this the first extended filter? */ @@ -2066,7 +2065,7 @@ static int mcan_add_stdfilter(FAR struct sam_mcan_s *priv, /* Flush the filter entry into physical RAM */ - arch_clean_dcache((uintptr_t)stdfilter, (uintptr_t)stdfilter + 4); + up_clean_dcache((uintptr_t)stdfilter, (uintptr_t)stdfilter + 4); /* Is this the first standard filter? */ @@ -2953,7 +2952,7 @@ static int mcan_send(FAR struct can_dev_s *dev, FAR struct can_msg_s *msg) /* Flush the D-Cache to memory before initiating the transfer */ msglen = 2 * sizeof(uint32_t) + nbytes; - arch_clean_dcache((uintptr_t)txbuffer, (uintptr_t)txbuffer + msglen); + up_clean_dcache((uintptr_t)txbuffer, (uintptr_t)txbuffer + msglen); UNUSED(msglen); /* Enable transmit interrupts from the TX FIFOQ buffer by setting TC @@ -3327,7 +3326,7 @@ static void mcan_receive(FAR struct can_dev_s *dev, FAR uint32_t *rxbuffer, /* Invalidate the D-Cache so that we reread the RX buffer data from memory. */ nbytes = (nwords << 2); - arch_invalidate_dcache((uintptr_t)rxbuffer, (uintptr_t)rxbuffer + nbytes); + up_invalidate_dcache((uintptr_t)rxbuffer, (uintptr_t)rxbuffer + nbytes); /* Format the CAN header */ /* Work R0 contains the CAN ID */ diff --git a/arch/arm/src/samv7/sam_mpuinit.c b/arch/arm/src/samv7/sam_mpuinit.c index 940e93e61a..4b2d67716b 100644 --- a/arch/arm/src/samv7/sam_mpuinit.c +++ b/arch/arm/src/samv7/sam_mpuinit.c @@ -44,7 +44,6 @@ #include #include "mpu.h" -#include "cache.h" #include "chip/sam_memorymap.h" #include "sam_mpuinit.h" diff --git a/arch/arm/src/samv7/sam_progmem.c b/arch/arm/src/samv7/sam_progmem.c index af613c9e95..991cee2b55 100644 --- a/arch/arm/src/samv7/sam_progmem.c +++ b/arch/arm/src/samv7/sam_progmem.c @@ -47,7 +47,6 @@ #include #include "up_arch.h" -#include "cache.h" #include "chip/sam_memorymap.h" #include "sam_progmem.h" @@ -593,7 +592,7 @@ ssize_t up_progmem_ispageerased(size_t cluster) /* Flush and invalidate D-Cache for this address range */ address = (cluster << SAMV7_CLUSTER_SHIFT) + SAMV7_PROGMEM_START; - arch_flush_dcache(address, address + SAMV7_CLUSTER_SIZE); + up_flush_dcache(address, address + SAMV7_CLUSTER_SIZE); /* Verify that the cluster is erased (i.e., all 0xff) */ @@ -731,7 +730,7 @@ ssize_t up_progmem_write(size_t address, const void *buffer, size_t buflen) /* Flush the data cache to memory */ - arch_clean_dcache(address, address + SAMV7_PAGE_SIZE); + up_clean_dcache(address, address + SAMV7_PAGE_SIZE); /* Send the write command */ diff --git a/arch/arm/src/samv7/sam_qspi.c b/arch/arm/src/samv7/sam_qspi.c index 9c65b2567b..6823f0dff9 100644 --- a/arch/arm/src/samv7/sam_qspi.c +++ b/arch/arm/src/samv7/sam_qspi.c @@ -60,7 +60,6 @@ #include "up_internal.h" #include "up_arch.h" -#include "cache.h" #include "sam_gpio.h" #include "sam_xdmac.h" diff --git a/arch/arm/src/samv7/sam_spi.c b/arch/arm/src/samv7/sam_spi.c index 68303a7e2b..195258c3c2 100644 --- a/arch/arm/src/samv7/sam_spi.c +++ b/arch/arm/src/samv7/sam_spi.c @@ -61,7 +61,6 @@ #include "up_internal.h" #include "up_arch.h" -#include "cache.h" #include "sam_gpio.h" #include "sam_xdmac.h" @@ -1760,7 +1759,7 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, * the DMA completes */ - arch_invalidate_dcache((uintptr_t)rxbuffer, (uintptr_t)rxbuffer + nbytes); + up_invalidate_dcache((uintptr_t)rxbuffer, (uintptr_t)rxbuffer + nbytes); /* Use normal RX memory incrementing. */ diff --git a/arch/arm/src/samv7/sam_ssc.c b/arch/arm/src/samv7/sam_ssc.c index 33d44caef3..78511b8f81 100644 --- a/arch/arm/src/samv7/sam_ssc.c +++ b/arch/arm/src/samv7/sam_ssc.c @@ -62,7 +62,6 @@ #include "up_internal.h" #include "up_arch.h" -#include "cache.h" #include "sam_gpio.h" #include "sam_xdmac.h" @@ -1314,8 +1313,8 @@ static int ssc_rxdma_setup(struct sam_ssc_s *priv) */ #warning Not yet supported #if 0 - arch_invalidate_dcache((uintptr_t)apb->samp, - (uintptr_t)apb->samp + apb->nmaxbytes); + up_invalidate_dcache((uintptr_t)apb->samp, + (uintptr_t)apb->samp + apb->nmaxbytes); #endif } #if 1 /* REVISIT: Chained RX transfers */ @@ -1730,9 +1729,9 @@ static int ssc_txdma_setup(struct sam_ssc_s *priv) */ #warning REVISIT #if 1 - arch_invalidate_dcache_all(); + up_invalidate_dcache_all(); #else - arch_clean_dcache(samp, samp + nbytes); + up_clean_dcache(samp, samp + nbytes); #endif } #if 1 /* REVISIT: Chained TX transfers */ diff --git a/arch/arm/src/samv7/sam_start.c b/arch/arm/src/samv7/sam_start.c index 4c10ece48f..400c202b1c 100644 --- a/arch/arm/src/samv7/sam_start.c +++ b/arch/arm/src/samv7/sam_start.c @@ -43,13 +43,13 @@ #include #include +#include #include #include #include "up_arch.h" #include "up_internal.h" -#include "cache.h" #ifdef CONFIG_ARCH_FPU # include "nvic.h" #endif @@ -391,9 +391,8 @@ void __start(void) /* Enable I- and D-Caches */ - arch_dcache_writethrough(); - arch_enable_icache(); - arch_enable_dcache(); + up_enable_icache(); + up_enable_dcache(); /* Perform early serial initialization */ diff --git a/arch/arm/src/samv7/sam_usbdevhs.c b/arch/arm/src/samv7/sam_usbdevhs.c index 5959cde64a..aabff02b62 100644 --- a/arch/arm/src/samv7/sam_usbdevhs.c +++ b/arch/arm/src/samv7/sam_usbdevhs.c @@ -70,7 +70,6 @@ #include "up_arch.h" #include "up_internal.h" -#include "cache.h" #include "chip.h" #include "sam_periphclks.h" @@ -972,7 +971,7 @@ static void sam_dma_single(uint8_t epno, struct sam_req_s *privreq, /* Flush the contents of the DMA buffer to RAM */ buffer = (uintptr_t)&privreq->req.buf[privreq->req.xfrd]; - arch_clean_dcache(buffer, buffer + privreq->inflight); + up_clean_dcache(buffer, buffer + privreq->inflight); /* Set up the DMA */ @@ -2584,7 +2583,7 @@ static void sam_dma_interrupt(struct sam_usbdev_s *priv, int epno) DEBUGASSERT(USB_ISEPOUT(privep->ep.eplog)); buf = &privreq->req.buf[privreq->req.xfrd]; - arch_invalidate_dcache((uintptr_t)buf, (uintptr_t)buf + xfrsize); + up_invalidate_dcache((uintptr_t)buf, (uintptr_t)buf + xfrsize); /* Complete this transfer, return the request to the class * implementation, and try to start the next, queue read request. @@ -2643,7 +2642,7 @@ static void sam_dma_interrupt(struct sam_usbdev_s *priv, int epno) */ buf = &privreq->req.buf[privreq->req.xfrd]; - arch_invalidate_dcache((uintptr_t)buf, (uintptr_t)buf + xfrsize); + up_invalidate_dcache((uintptr_t)buf, (uintptr_t)buf + xfrsize); /* Complete this transfer, return the request to the class * implementation, and try to start the next, queue read request. diff --git a/arch/arm/src/samv7/sam_xdmac.c b/arch/arm/src/samv7/sam_xdmac.c index 0459b1e494..44e43829f7 100644 --- a/arch/arm/src/samv7/sam_xdmac.c +++ b/arch/arm/src/samv7/sam_xdmac.c @@ -51,7 +51,6 @@ #include #include "up_arch.h" -#include "cache.h" #include "up_internal.h" #include "sched/sched.h" @@ -1090,8 +1089,8 @@ sam_allocdesc(struct sam_xdmach_s *xdmach, struct chnext_view1_s *prev, * that hardware will be accessing the descriptor via DMA. */ - arch_clean_dcache((uintptr_t)descr, - (uintptr_t)descr + sizeof(struct chnext_view1_s)); + up_clean_dcache((uintptr_t)descr, + (uintptr_t)descr + sizeof(struct chnext_view1_s)); break; } } @@ -1853,7 +1852,7 @@ int sam_dmatxsetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr, /* Clean caches associated with the DMA memory */ - arch_clean_dcache(maddr, maddr + nbytes); + up_clean_dcache(maddr, maddr + nbytes); return ret; } @@ -1934,7 +1933,7 @@ int sam_dmarxsetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr, /* Clean caches associated with the DMA memory */ - arch_clean_dcache(maddr, maddr + nbytes); + up_clean_dcache(maddr, maddr + nbytes); return ret; } @@ -1972,7 +1971,7 @@ int sam_dmastart(DMA_HANDLE handle, dma_callback_t callback, void *arg) if (xdmach->rx) { - arch_flush_dcache(xdmach->rxaddr, xdmach->rxaddr + xdmach->rxsize); + up_flush_dcache(xdmach->rxaddr, xdmach->rxaddr + xdmach->rxsize); } /* Is this a single block transfer? Or a multiple block transfer? */ diff --git a/arch/arm/src/stm32f7/Make.defs b/arch/arm/src/stm32f7/Make.defs index 68ff797f94..03fcd37ae1 100644 --- a/arch/arm/src/stm32f7/Make.defs +++ b/arch/arm/src/stm32f7/Make.defs @@ -72,14 +72,7 @@ CMN_ASRCS += up_exception.S endif CMN_CSRCS += up_vectors.c -ifeq ($(CONFIG_ARMV7M_DCACHE),y) -CMN_CSRCS += arch_enable_dcache.c arch_disable_dcache.c -CMN_CSRCS += arch_invalidate_dcache.c arch_invalidate_dcache_all.c -ifneq ($(CONFIG_ARMV7M_DCACHE_WRITETHROUGH),y) -CMN_CSRCS += arch_clean_dcache.c arch_clean_dcache_all.c -CMN_CSRCS += arch_flush_dcache.c arch_flush_dcache_all.c -endif -endif +CMN_CSRCS += up_cache.c ifeq ($(CONFIG_ARCH_FPU),y) CMN_ASRCS += up_fpu.S @@ -98,12 +91,6 @@ CMN_UASRCS += up_signal_handler.S endif endif -ifeq ($(CONFIG_ELF),y) -CMN_CSRCS += up_coherent_dcache.c -else ifeq ($(CONFIG_MODULE),y) -CMN_CSRCS += up_coherent_dcache.c -endif - ifeq ($(CONFIG_STACK_COLORATION),y) CMN_CSRCS += up_checkstack.c endif diff --git a/arch/arm/src/stm32f7/stm32_adc.c b/arch/arm/src/stm32f7/stm32_adc.c index 6343472f4f..7262f8c552 100644 --- a/arch/arm/src/stm32f7/stm32_adc.c +++ b/arch/arm/src/stm32f7/stm32_adc.c @@ -69,7 +69,6 @@ #include "up_internal.h" #include "up_arch.h" -#include "cache.h" #include "chip.h" #include "stm32_rcc.h" #include "stm32_tim.h" @@ -1190,8 +1189,8 @@ static void adc_dmaconvcallback(DMA_HANDLE handle, uint8_t isr, FAR void *arg) FAR struct stm32_dev_s *priv = (FAR struct stm32_dev_s *)dev->ad_priv; int i; - arch_invalidate_dcache((uintptr_t)priv->dmabuffer, - (uintptr_t)priv->dmabuffer + sizeof(priv->dmabuffer)); + up_invalidate_dcache((uintptr_t)priv->dmabuffer, + (uintptr_t)priv->dmabuffer + sizeof(priv->dmabuffer)); /* Verify that the upper-half driver has bound its callback functions */ diff --git a/arch/arm/src/stm32f7/stm32_dma.c b/arch/arm/src/stm32f7/stm32_dma.c index fa1c61c7f8..7c37219f56 100644 --- a/arch/arm/src/stm32f7/stm32_dma.c +++ b/arch/arm/src/stm32f7/stm32_dma.c @@ -918,8 +918,8 @@ bool stm32_dmacapable(uint32_t maddr, uint32_t count, uint32_t ccr) # if defined(CONFIG_ARMV7M_DCACHE) && !defined(CONFIG_ARMV7M_DCACHE_WRITETHROUGH) /* buffer alignment is required for DMA transfers with dcache in buffered - * mode (not write-through) because a) arch_invalidate_dcache could lose - * buffered writes and b) arch_flush_dcache could corrupt adjacent memory if + * mode (not write-through) because a) up_invalidate_dcache could lose + * buffered writes and b) up_flush_dcache could corrupt adjacent memory if * the maddr and the mend+1, the next next address are not on * ARMV7M_DCACHE_LINESIZE boundaries. */ diff --git a/arch/arm/src/stm32f7/stm32_ethernet.c b/arch/arm/src/stm32f7/stm32_ethernet.c index 7a879724b5..42c48af67e 100644 --- a/arch/arm/src/stm32f7/stm32_ethernet.c +++ b/arch/arm/src/stm32f7/stm32_ethernet.c @@ -61,7 +61,6 @@ # include #endif -#include "cache.h" #include "up_internal.h" #include "chip/stm32_syscfg.h" @@ -1067,8 +1066,8 @@ static int stm32_transmit(struct stm32_ethmac_s *priv) /* Flush the contents of the TX buffer into physical memory */ - arch_clean_dcache((uintptr_t)priv->dev.d_buf, - (uintptr_t)priv->dev.d_buf + priv->dev.d_len); + up_clean_dcache((uintptr_t)priv->dev.d_buf, + (uintptr_t)priv->dev.d_buf + priv->dev.d_len); /* Is the size to be sent greater than the size of the Ethernet buffer? */ @@ -1140,8 +1139,8 @@ static int stm32_transmit(struct stm32_ethmac_s *priv) * memory. */ - arch_clean_dcache((uintptr_t)txdesc, - (uintptr_t)txdesc + sizeof(struct eth_txdesc_s)); + up_clean_dcache((uintptr_t)txdesc, + (uintptr_t)txdesc + sizeof(struct eth_txdesc_s)); /* Get the next descriptor in the link list */ @@ -1176,8 +1175,8 @@ static int stm32_transmit(struct stm32_ethmac_s *priv) * memory. */ - arch_clean_dcache((uintptr_t)txdesc, - (uintptr_t)txdesc + sizeof(struct eth_txdesc_s)); + up_clean_dcache((uintptr_t)txdesc, + (uintptr_t)txdesc + sizeof(struct eth_txdesc_s)); /* Point to the next available TX descriptor */ @@ -1528,8 +1527,8 @@ static void stm32_freesegment(struct stm32_ethmac_s *priv, * memory. */ - arch_clean_dcache((uintptr_t)rxdesc, - (uintptr_t)rxdesc + sizeof(struct eth_rxdesc_s)); + up_clean_dcache((uintptr_t)rxdesc, + (uintptr_t)rxdesc + sizeof(struct eth_rxdesc_s)); /* Get the next RX descriptor in the chain (cache coherency should not * be an issue because the link address is constant. @@ -1614,8 +1613,8 @@ static int stm32_recvframe(struct stm32_ethmac_s *priv) /* Forces the first RX descriptor to be re-read from physical memory */ - arch_invalidate_dcache((uintptr_t)rxdesc, - (uintptr_t)rxdesc + sizeof(struct eth_rxdesc_s)); + up_invalidate_dcache((uintptr_t)rxdesc, + (uintptr_t)rxdesc + sizeof(struct eth_rxdesc_s)); for (i = 0; (rxdesc->rdes0 & ETH_RDES0_OWN) == 0 && @@ -1693,8 +1692,8 @@ static int stm32_recvframe(struct stm32_ethmac_s *priv) * physical memory. */ - arch_clean_dcache((uintptr_t)rxcurr, - (uintptr_t)rxdesc + sizeof(struct eth_rxdesc_s)); + up_clean_dcache((uintptr_t)rxcurr, + (uintptr_t)rxdesc + sizeof(struct eth_rxdesc_s)); /* Remember where we should re-start scanning and reset the segment * scanning logic @@ -1707,8 +1706,8 @@ static int stm32_recvframe(struct stm32_ethmac_s *priv) * physical memory. */ - arch_invalidate_dcache((uintptr_t)dev->d_buf, - (uintptr_t)dev->d_buf + dev->d_len); + up_invalidate_dcache((uintptr_t)dev->d_buf, + (uintptr_t)dev->d_buf + dev->d_len); ninfo("rxhead: %p d_buf: %p d_len: %d\n", priv->rxhead, dev->d_buf, dev->d_len); @@ -1734,8 +1733,8 @@ static int stm32_recvframe(struct stm32_ethmac_s *priv) /* Force the next RX descriptor to be re-read from physical memory */ - arch_invalidate_dcache((uintptr_t)rxdesc, - (uintptr_t)rxdesc + sizeof(struct eth_rxdesc_s)); + up_invalidate_dcache((uintptr_t)rxdesc, + (uintptr_t)rxdesc + sizeof(struct eth_rxdesc_s)); } /* We get here after all of the descriptors have been scanned or when rxdesc points @@ -1946,8 +1945,8 @@ static void stm32_freeframe(struct stm32_ethmac_s *priv) /* Force re-reading of the TX descriptor for physical memory */ - arch_invalidate_dcache((uintptr_t)txdesc, - (uintptr_t)txdesc + sizeof(struct eth_txdesc_s)); + up_invalidate_dcache((uintptr_t)txdesc, + (uintptr_t)txdesc + sizeof(struct eth_txdesc_s)); for (i = 0; (txdesc->tdes0 & ETH_TDES0_OWN) == 0; i++) { @@ -1977,8 +1976,8 @@ static void stm32_freeframe(struct stm32_ethmac_s *priv) * physical memory. */ - arch_clean_dcache((uintptr_t)txdesc, - (uintptr_t)txdesc + sizeof(struct eth_txdesc_s)); + up_clean_dcache((uintptr_t)txdesc, + (uintptr_t)txdesc + sizeof(struct eth_txdesc_s)); /* Check if this is the last segment of a TX frame */ @@ -2010,8 +2009,8 @@ static void stm32_freeframe(struct stm32_ethmac_s *priv) /* Force re-reading of the TX descriptor for physical memory */ - arch_invalidate_dcache((uintptr_t)txdesc, - (uintptr_t)txdesc + sizeof(struct eth_txdesc_s)); + up_invalidate_dcache((uintptr_t)txdesc, + (uintptr_t)txdesc + sizeof(struct eth_txdesc_s)); } /* We get here if (1) there are still frames "in-flight". Remember @@ -2833,9 +2832,9 @@ static void stm32_txdescinit(struct stm32_ethmac_s *priv, /* Flush all of the initialized TX descriptors to physical memory */ - arch_clean_dcache((uintptr_t)txtable, - (uintptr_t)txtable + - TXTABLE_SIZE * sizeof(union stm32_txdesc_u)); + up_clean_dcache((uintptr_t)txtable, + (uintptr_t)txtable + + TXTABLE_SIZE * sizeof(union stm32_txdesc_u)); /* Set Transmit Descriptor List Address Register */ @@ -2923,9 +2922,9 @@ static void stm32_rxdescinit(struct stm32_ethmac_s *priv, /* Flush all of the initialized RX descriptors to physical memory */ - arch_clean_dcache((uintptr_t)rxtable, - (uintptr_t)rxtable + - RXTABLE_SIZE * sizeof(union stm32_rxdesc_u)); + up_clean_dcache((uintptr_t)rxtable, + (uintptr_t)rxtable + + RXTABLE_SIZE * sizeof(union stm32_rxdesc_u)); /* Set Receive Descriptor List Address Register */ diff --git a/arch/arm/src/stm32f7/stm32_flash.c b/arch/arm/src/stm32f7/stm32_flash.c index 77e43e7dd3..d8152fe5a9 100644 --- a/arch/arm/src/stm32f7/stm32_flash.c +++ b/arch/arm/src/stm32f7/stm32_flash.c @@ -60,7 +60,6 @@ #include "chip/stm32_flash.h" #include "up_arch.h" -#include "cache.h" /**************************************************************************** * Pre-processor Definitions diff --git a/arch/arm/src/stm32f7/stm32_sdmmc.c b/arch/arm/src/stm32f7/stm32_sdmmc.c index da622bd701..20d2076fa8 100644 --- a/arch/arm/src/stm32f7/stm32_sdmmc.c +++ b/arch/arm/src/stm32f7/stm32_sdmmc.c @@ -60,7 +60,6 @@ #include #include -#include "cache.h" #include "chip.h" #include "up_arch.h" @@ -2995,7 +2994,7 @@ static int stm32_dmarecvsetup(FAR struct sdio_dev_s *dev, FAR uint8_t *buffer, #else # if defined(CONFIG_ARMV7M_DCACHE) && !defined(CONFIG_ARMV7M_DCACHE_WRITETHROUGH) /* buffer alignment is required for DMA transfers with dcache in buffered - * mode (not write-through) because the arch_invalidate_dcache could lose + * mode (not write-through) because the up_invalidate_dcache could lose * buffered buffered writes if the buffer alignment and sizes are not on * ARMV7M_DCACHE_LINESIZE boundaries. */ @@ -3044,7 +3043,7 @@ static int stm32_dmarecvsetup(FAR struct sdio_dev_s *dev, FAR uint8_t *buffer, if ((uintptr_t)buffer < DTCM_START || (uintptr_t)buffer + buflen > DTCM_END) { #if !defined(CONFIG_ARCH_HAVE_SDIO_DELAYED_INVLDT) - arch_invalidate_dcache_by_addr((uintptr_t)buffer,(uintptr_t)buffer + buflen); + up_invalidate_dcache((uintptr_t)buffer,(uintptr_t)buffer + buflen); #endif } @@ -3090,7 +3089,7 @@ static int stm32_dmasendsetup(FAR struct sdio_dev_s *dev, #else # if defined(CONFIG_ARMV7M_DCACHE) && !defined(CONFIG_ARMV7M_DCACHE_WRITETHROUGH) /* buffer alignment is required for DMA transfers with dcache in buffered - * mode (not write-through) because the arch_flush_dcache would corrupt adjacent + * mode (not write-through) because the up_flush_dcache would corrupt adjacent * memory if the buffer alignment and sizes are not on ARMV7M_DCACHE_LINESIZE * boundaries. */ @@ -3117,9 +3116,9 @@ static int stm32_dmasendsetup(FAR struct sdio_dev_s *dev, if ((uintptr_t)buffer < DTCM_START || (uintptr_t)buffer + buflen > DTCM_END) { #ifdef CONFIG_ARMV7M_DCACHE_WRITETHROUGH - arch_invalidate_dcache_by_addr((uintptr_t)buffer, (uintptr_t)buffer + buflen); + up_invalidate_dcache((uintptr_t)buffer, (uintptr_t)buffer + buflen); #else - arch_flush_dcache((uintptr_t)buffer, (uintptr_t)buffer + buflen); + up_flush_dcache((uintptr_t)buffer, (uintptr_t)buffer + buflen); #endif } @@ -3184,8 +3183,8 @@ static int stm32_dmadelydinvldt(FAR struct sdio_dev_s *dev, if ((uintptr_t)buffer < DTCM_START || (uintptr_t)buffer + buflen > DTCM_END) { - arch_invalidate_dcache_by_addr((uintptr_t)buffer, - (uintptr_t)buffer + buflen); + up_invalidate_dcache((uintptr_t)buffer, + (uintptr_t)buffer + buflen); } return OK; diff --git a/arch/arm/src/stm32f7/stm32_serial.c b/arch/arm/src/stm32f7/stm32_serial.c index 929041a501..a57db4aa22 100644 --- a/arch/arm/src/stm32f7/stm32_serial.c +++ b/arch/arm/src/stm32f7/stm32_serial.c @@ -59,7 +59,6 @@ # include #endif -#include "cache.h" #include "up_arch.h" #include "up_internal.h" @@ -2575,7 +2574,7 @@ static int up_dma_receive(struct uart_dev_s *dev, unsigned int *status) /* Invalidate the DMA buffer range */ addr = (uintptr_t)&priv->rxfifo[priv->rxdmanext]; - arch_invalidate_dcache(addr, addr + rxdmaavail); + up_invalidate_dcache(addr, addr + rxdmaavail); /* We don't need to invalidate the data cache for the next * rxdmaavail number of next bytes. diff --git a/arch/arm/src/stm32f7/stm32_spi.c b/arch/arm/src/stm32f7/stm32_spi.c index ee0e5e4672..d0c9da5fb1 100644 --- a/arch/arm/src/stm32f7/stm32_spi.c +++ b/arch/arm/src/stm32f7/stm32_spi.c @@ -82,7 +82,6 @@ #include "up_internal.h" #include "up_arch.h" -#include "cache.h" #include "chip.h" #include "stm32_gpio.h" #include "stm32_dma.h" @@ -1712,7 +1711,7 @@ static void spi_exchange(FAR struct spi_dev_s *dev, FAR const void *txbuffer, if (txbuffer) { - arch_flush_dcache((uintptr_t)txbuffer, (uintptr_t)txbuffer + buflen); + up_flush_dcache((uintptr_t)txbuffer, (uintptr_t)txbuffer + buflen); } #ifdef CONFIG_SPI_TRIGGER @@ -1751,13 +1750,13 @@ static void spi_exchange(FAR struct spi_dev_s *dev, FAR const void *txbuffer, if (rxbuffer) { - arch_invalidate_dcache((uintptr_t)rxbuffer, - (uintptr_t)rxbuffer + buflen); + up_invalidate_dcache((uintptr_t)rxbuffer, + (uintptr_t)rxbuffer + buflen); } else { - arch_invalidate_dcache((uintptr_t)rxdummy, - (uintptr_t)rxdummy + sizeof(rxdummy)); + up_invalidate_dcache((uintptr_t)rxdummy, + (uintptr_t)rxdummy + sizeof(rxdummy)); } } } diff --git a/arch/arm/src/stm32f7/stm32_start.c b/arch/arm/src/stm32f7/stm32_start.c index 92f3c02f64..78b379019e 100644 --- a/arch/arm/src/stm32f7/stm32_start.c +++ b/arch/arm/src/stm32f7/stm32_start.c @@ -43,13 +43,13 @@ #include #include +#include #include #include #include "up_arch.h" #include "up_internal.h" -#include "cache.h" #ifdef CONFIG_ARCH_FPU # include "nvic.h" #endif @@ -372,9 +372,8 @@ void __start(void) /* Enable I- and D-Caches */ - arch_dcache_writethrough(); - arch_enable_icache(); - arch_enable_dcache(); + up_enable_icache(); + up_enable_dcache(); /* Perform early serial initialization */ diff --git a/arch/arm/src/stm32h7/Make.defs b/arch/arm/src/stm32h7/Make.defs index 24855b3ff5..ba523251f5 100644 --- a/arch/arm/src/stm32h7/Make.defs +++ b/arch/arm/src/stm32h7/Make.defs @@ -64,15 +64,7 @@ CMN_ASRCS += up_exception.S endif CMN_CSRCS += up_vectors.c -ifeq ($(CONFIG_ARMV7M_DCACHE),y) -CMN_CSRCS += arch_enable_dcache.c arch_disable_dcache.c -CMN_CSRCS += arch_invalidate_dcache.c arch_invalidate_dcache_all.c -ifneq ($(CONFIG_ARMV7M_DCACHE_WRITETHROUGH),y) -CMN_CSRCS += arch_clean_dcache.c arch_clean_dcache_all.c -CMN_CSRCS += arch_flush_dcache.c arch_flush_dcache_all.c -endif -endif - +CMN_CSRCS += up_cache.c ifeq ($(CONFIG_ARCH_FPU),y) CMN_ASRCS += up_fpu.S CMN_CSRCS += up_copyarmstate.c @@ -94,12 +86,6 @@ CMN_UASRCS += up_signal_handler.S endif endif -ifeq ($(CONFIG_ELF),y) -CMN_CSRCS += up_coherent_dcache.c -else ifeq ($(CONFIG_MODULE),y) -CMN_CSRCS += up_coherent_dcache.c -endif - ifeq ($(CONFIG_STACK_COLORATION),y) CMN_CSRCS += up_checkstack.c endif diff --git a/arch/arm/src/stm32h7/stm32_serial.c b/arch/arm/src/stm32h7/stm32_serial.c index 921e0df25b..a63beaadee 100644 --- a/arch/arm/src/stm32h7/stm32_serial.c +++ b/arch/arm/src/stm32h7/stm32_serial.c @@ -59,7 +59,6 @@ # include #endif -#include "cache.h" #include "up_arch.h" #include "up_internal.h" diff --git a/arch/arm/src/stm32h7/stm32_spi.c b/arch/arm/src/stm32h7/stm32_spi.c index 4a4b4c9455..050d406251 100644 --- a/arch/arm/src/stm32h7/stm32_spi.c +++ b/arch/arm/src/stm32h7/stm32_spi.c @@ -83,7 +83,6 @@ #include "up_internal.h" #include "up_arch.h" -#include "cache.h" #include "chip.h" #include "stm32_rcc.h" #include "stm32_gpio.h" @@ -1763,7 +1762,7 @@ static void spi_exchange(FAR struct spi_dev_s *dev, FAR const void *txbuffer, if (txbuffer) { - arch_flush_dcache((uintptr_t)txbuffer, (uintptr_t)txbuffer + buflen); + up_flush_dcache((uintptr_t)txbuffer, (uintptr_t)txbuffer + buflen); } /* REVISIT: Master transfer start */ @@ -1806,13 +1805,13 @@ static void spi_exchange(FAR struct spi_dev_s *dev, FAR const void *txbuffer, if (rxbuffer) { - arch_invalidate_dcache((uintptr_t)rxbuffer, - (uintptr_t)rxbuffer + buflen); + up_invalidate_dcache((uintptr_t)rxbuffer, + (uintptr_t)rxbuffer + buflen); } else { - arch_invalidate_dcache((uintptr_t)rxdummy, - (uintptr_t)rxdummy + sizeof(rxdummy)); + up_invalidate_dcache((uintptr_t)rxdummy, + (uintptr_t)rxdummy + sizeof(rxdummy)); } } } diff --git a/arch/arm/src/stm32h7/stm32_start.c b/arch/arm/src/stm32h7/stm32_start.c index ab52429d33..d47b588a3a 100644 --- a/arch/arm/src/stm32h7/stm32_start.c +++ b/arch/arm/src/stm32h7/stm32_start.c @@ -43,13 +43,13 @@ #include #include +#include #include #include #include "up_arch.h" #include "up_internal.h" -#include "cache.h" #ifdef CONFIG_ARCH_FPU # include "nvic.h" #endif @@ -390,9 +390,8 @@ void __start(void) /* Enable I- and D-Caches */ - arch_dcache_writethrough(); - arch_enable_icache(); - arch_enable_dcache(); + up_enable_icache(); + up_enable_dcache(); showprogress('C'); /* Perform early serial initialization */ diff --git a/arch/arm/src/stm32l4/stm32l4_qspi.c b/arch/arm/src/stm32l4/stm32l4_qspi.c index a2566b0de1..46baa89383 100644 --- a/arch/arm/src/stm32l4/stm32l4_qspi.c +++ b/arch/arm/src/stm32l4/stm32l4_qspi.c @@ -60,7 +60,6 @@ #include "up_internal.h" #include "up_arch.h" -#include "cache.h" #include "stm32l4_gpio.h" #include "stm32l4_dma.h" diff --git a/arch/arm/src/stm32l4/stm32l4_sdmmc.c b/arch/arm/src/stm32l4/stm32l4_sdmmc.c index 9636267f4e..966fef561e 100644 --- a/arch/arm/src/stm32l4/stm32l4_sdmmc.c +++ b/arch/arm/src/stm32l4/stm32l4_sdmmc.c @@ -60,7 +60,6 @@ #include #include -#include "cache.h" #include "chip.h" #include "up_arch.h" @@ -2813,7 +2812,7 @@ static int stm32_dmarecvsetup(FAR struct sdio_dev_s *dev, FAR uint8_t *buffer, #else # if defined(CONFIG_ARMV7M_DCACHE) && !defined(CONFIG_ARMV7M_DCACHE_WRITETHROUGH) /* buffer alignment is required for DMA transfers with dcache in buffered - * mode (not write-through) because the arch_invalidate_dcache could lose + * mode (not write-through) because the up_invalidate_dcache could lose * buffered buffered writes if the buffer alignment and sizes are not on * ARMV7M_DCACHE_LINESIZE boundaries. */ @@ -2859,7 +2858,7 @@ static int stm32_dmarecvsetup(FAR struct sdio_dev_s *dev, FAR uint8_t *buffer, /* Force RAM reread */ - arch_invalidate_dcache((uintptr_t)buffer,(uintptr_t)buffer + buflen); + up_invalidate_dcache((uintptr_t)buffer,(uintptr_t)buffer + buflen); /* Start the DMA */ @@ -2903,7 +2902,7 @@ static int stm32_dmasendsetup(FAR struct sdio_dev_s *dev, #else # if defined(CONFIG_ARMV7M_DCACHE) && !defined(CONFIG_ARMV7M_DCACHE_WRITETHROUGH) /* buffer alignment is required for DMA transfers with dcache in buffered - * mode (not write-through) because the arch_flush_dcache would corrupt adjacent + * mode (not write-through) because the up_flush_dcache would corrupt adjacent * memory if the buffer alignment and sizes are not on ARMV7M_DCACHE_LINESIZE * boundaries. */ @@ -2927,7 +2926,7 @@ static int stm32_dmasendsetup(FAR struct sdio_dev_s *dev, /* Flush cache to physical memory */ - arch_flush_dcache((uintptr_t)buffer, (uintptr_t)buffer + buflen); + up_flush_dcache((uintptr_t)buffer, (uintptr_t)buffer + buflen); /* Save the source buffer information for use by the interrupt handler */ diff --git a/arch/arm/src/tms570/Make.defs b/arch/arm/src/tms570/Make.defs index e7a785084d..4e6a231806 100644 --- a/arch/arm/src/tms570/Make.defs +++ b/arch/arm/src/tms570/Make.defs @@ -84,11 +84,7 @@ ifeq ($(CONFIG_ARMV7R_L2CC_PL310),y) CMN_CSRCS += arm_l2cc_pl310.c endif -ifeq ($(CONFIG_ELF),y) -CMN_CSRCS += arm_coherent_dcache.c -else ifeq ($(CONFIG_MODULE),y) -CMN_CSRCS += arm_coherent_dcache.c -endif +CMN_CSRCS += arm_cache.c ifeq ($(CONFIG_ARCH_FPU),y) CMN_ASRCS += arm_savefpu.S arm_restorefpu.S diff --git a/arch/arm/src/tms570/tms570_boot.c b/arch/arm/src/tms570/tms570_boot.c index f362fff6aa..94e9cd9745 100644 --- a/arch/arm/src/tms570/tms570_boot.c +++ b/arch/arm/src/tms570/tms570_boot.c @@ -54,7 +54,6 @@ #include "chip.h" #include "arm.h" -#include "cache.h" #include "fpu.h" #include "sctlr.h" #include "up_internal.h" diff --git a/arch/or1k/src/common/up_initialize.c b/arch/or1k/src/common/up_initialize.c index 932048304d..56241dc602 100644 --- a/arch/or1k/src/common/up_initialize.c +++ b/arch/or1k/src/common/up_initialize.c @@ -68,7 +68,7 @@ ****************************************************************************/ #ifdef CONFIG_OR1K_ICACHE -static void up_enable_icache(void) +void up_enable_icache(void) { uint32_t iccfg; uint32_t sr; @@ -98,7 +98,7 @@ static void up_enable_icache(void) #endif #ifdef CONFIG_OR1K_DCACHE -static void up_enable_dcache(void) +void up_enable_dcache(void) { uint32_t dccfg; uint32_t sr; diff --git a/arch/or1k/src/mor1kx/Kconfig b/arch/or1k/src/mor1kx/Kconfig index e3ef2f9dba..9210cc3733 100644 --- a/arch/or1k/src/mor1kx/Kconfig +++ b/arch/or1k/src/mor1kx/Kconfig @@ -25,10 +25,12 @@ config OR1K_CPU_FREQUENCY config OR1K_ICACHE bool "Enable Instruction Cache" default n + select ARCH_ICACHE config OR1K_DCACHE bool "Enable Data Cache" default n + select ARCH_DCACHE config OR1K_MMU bool "Enable MMU" diff --git a/binfmt/libelf/libelf_bind.c b/binfmt/libelf/libelf_bind.c index 6bacf4eaa7..9b868d4bc9 100644 --- a/binfmt/libelf/libelf_bind.c +++ b/binfmt/libelf/libelf_bind.c @@ -452,7 +452,7 @@ int elf_bind(FAR struct elf_loadinfo_s *loadinfo, } } -#elif defined(CONFIG_ARCH_HAVE_COHERENT_DCACHE) +#else /* Ensure that the I and D caches are coherent before starting the newly * loaded module by cleaning the D cache (i.e., flushing the D cache * contents to memory and invalidating the I cache). diff --git a/configs/sama5d3x-ek/src/nor_main.c b/configs/sama5d3x-ek/src/nor_main.c index 62fcb9c8e4..ef5c1960df 100644 --- a/configs/sama5d3x-ek/src/nor_main.c +++ b/configs/sama5d3x-ek/src/nor_main.c @@ -42,11 +42,12 @@ #include #include +#include #include #include "up_arch.h" #include "mmu.h" -#include "cache.h" +#include "cp15_cacheops.h" #include "sam_periphclks.h" #include "chip/sam_hsmc.h" @@ -183,8 +184,8 @@ int nor_main(int argc, char *argv) /* Invalidate caches and TLBs */ - arch_invalidate_icache(); - arch_invalidate_dcache_all(); + up_invalidate_icache_all(); + up_invalidate_dcache_all(); cp15_invalidate_tlbs(); /* Then jump into NOR flash */ diff --git a/configs/sama5d4-ek/src/dram_main.c b/configs/sama5d4-ek/src/dram_main.c index 28d26629b6..00267a104e 100644 --- a/configs/sama5d4-ek/src/dram_main.c +++ b/configs/sama5d4-ek/src/dram_main.c @@ -43,11 +43,12 @@ #include #include +#include #include #include "up_arch.h" #include "mmu.h" -#include "cache.h" +#include "cp15_cacheops.h" #include "sama5d4-ek.h" @@ -143,9 +144,8 @@ int dram_main(int argc, char *argv) * we disable caching. */ - arch_clean_dcache((uintptr_t)SAM_DDRCS_VSECTION, - (uintptr_t)(SAM_DDRCS_VSECTION + - CONFIG_SAMA5_DDRCS_SIZE)); + up_clean_dcache((uintptr_t)SAM_DDRCS_VSECTION, + (uintptr_t)(SAM_DDRCS_VSECTION + CONFIG_SAMA5_DDRCS_SIZE)); /* Interrupts must be disabled through the following. In this * configuration, there should only be timer interrupts. Your NuttX diff --git a/configs/samv71-xult/src/sam_ili9488.c b/configs/samv71-xult/src/sam_ili9488.c index 604518853b..3e1db9af55 100644 --- a/configs/samv71-xult/src/sam_ili9488.c +++ b/configs/samv71-xult/src/sam_ili9488.c @@ -139,7 +139,6 @@ #include #include -#include "cache.h" #include "up_arch.h" #include "sam_gpio.h" #include "sam_periphclks.h" diff --git a/include/nuttx/arch.h b/include/nuttx/arch.h index c0c290c805..a32b61396b 100644 --- a/include/nuttx/arch.h +++ b/include/nuttx/arch.h @@ -98,6 +98,8 @@ #include +#include + /**************************************************************************** * Pre-processor definitions ****************************************************************************/ @@ -1319,28 +1321,6 @@ int up_shmdt(uintptr_t vaddr, unsigned int npages); /* See prototype in include/nuttx/elf.h */ -/**************************************************************************** - * Name: up_coherent_dcache - * - * Description: - * Ensure that the I and D caches are coherent within specified region - * by cleaning the D cache (i.e., flushing the D cache contents to memory - * and invalidating the I cache. This is typically used when code has been - * written to a memory region, and will be executed. - * - * Input Parameters: - * addr - virtual start address of region - * len - Size of the address region in bytes - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifdef CONFIG_ARCH_HAVE_COHERENT_DCACHE -void up_coherent_dcache(uintptr_t addr, size_t len); -#endif - /**************************************************************************** * Name: up_interrupt_context * diff --git a/include/nuttx/cache.h b/include/nuttx/cache.h new file mode 100644 index 0000000000..fbc96be09b --- /dev/null +++ b/include/nuttx/cache.h @@ -0,0 +1,378 @@ +/**************************************************************************** + * include/nuttx/cache.h + * + * Copyright (C) 2019 Pinecone Inc. All rights reserved. + * Author: Xiang Xiao + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __INCLUDE_NUTTX_CACHE_H +#define __INCLUDE_NUTTX_CACHE_H + +#ifndef __ASSEMBLY__ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_enable_icache + * + * Description: + * Enable the I-Cache + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + * Caution: + * The writable global variables aren't initialized yet. + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_ICACHE +void up_enable_icache(void); +#else +static inline void up_enable_icache(void) +{ +} +#endif + +/**************************************************************************** + * Name: up_disable_icache + * + * Description: + * Disable the I-Cache + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_ICACHE +void up_disable_icache(void); +#else +static inline void up_disable_icache(void) +{ +} +#endif + +/**************************************************************************** + * Name: up_invalidate_icache + * + * Description: + * Invalidate the instruction cache within the specified region. + * + * Input Parameters: + * start - virtual start address of region + * end - virtual end address of region + 1 + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_ICACHE +void up_invalidate_icache(uintptr_t start, uintptr_t end); +#else +static inline void up_invalidate_icache(uintptr_t start, uintptr_t end) +{ +} +#endif + +/**************************************************************************** + * Name: up_invalidate_icache_all + * + * Description: + * Invalidate the entire contents of I cache. + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_ICACHE +void up_invalidate_icache_all(void); +#else +static inline void up_invalidate_icache_all(void) +{ +} +#endif + + /**************************************************************************** + * Name: up_enable_dcache + * + * Description: + * Enable the D-Cache + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + * Caution: + * The writable global variables aren't initialized yet. + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_DCACHE +void up_enable_dcache(void); +#else +static inline void up_enable_dcache(void) +{ +} +#endif + +/**************************************************************************** + * Name: up_disable_dcache + * + * Description: + * Disable the D-Cache + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_DCACHE +void up_disable_dcache(void); +#else +static inline void up_disable_dcache(void) +{ +} +#endif + +/**************************************************************************** + * Name: up_invalidate_dcache + * + * Description: + * Invalidate the data cache within the specified region; we will be + * performing a DMA operation in this region and we want to purge old data + * in the cache. + * + * Input Parameters: + * start - virtual start address of region + * end - virtual end address of region + 1 + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_DCACHE +void up_invalidate_dcache(uintptr_t start, uintptr_t end); +#else +static inline void up_invalidate_dcache(uintptr_t start, uintptr_t end) +{ +} +#endif + +/**************************************************************************** + * Name: up_invalidate_dcache_all + * + * Description: + * Invalidate the entire contents of D cache. + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_DCACHE +void up_invalidate_dcache_all(void); +#else +static inline void up_invalidate_dcache_all(void) +{ +} +#endif + +/**************************************************************************** + * Name: up_clean_dcache + * + * Description: + * Clean the data cache within the specified region by flushing the + * contents of the data cache to memory. + * + * Input Parameters: + * start - virtual start address of region + * end - virtual end address of region + 1 + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_DCACHE +void up_clean_dcache(uintptr_t start, uintptr_t end); +#else +static inline void up_clean_dcache(uintptr_t start, uintptr_t end) +{ +} +#endif + +/**************************************************************************** + * Name: up_clean_dcache_all + * + * Description: + * Clean the entire data cache within the specified region by flushing the + * contents of the data cache to memory. + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_DCACHE +void up_clean_dcache_all(void); +#else +static inline void up_clean_dcache_all(void) +{ +} +#endif + +/**************************************************************************** + * Name: up_flush_dcache + * + * Description: + * Flush the data cache within the specified region by cleaning and + * invalidating the D cache. + * + * Input Parameters: + * start - virtual start address of region + * end - virtual end address of region + 1 + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_DCACHE +void up_flush_dcache(uintptr_t start, uintptr_t end); +#else +static inline void up_flush_dcache(uintptr_t start, uintptr_t end) +{ +} +#endif + +/**************************************************************************** + * Name: up_flush_dcache_all + * + * Description: + * Flush the entire data cache by cleaning and invalidating the D cache. + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_DCACHE +void up_flush_dcache_all(void); +#else +static inline void up_flush_dcache_all(void) +{ +} +#endif + +/**************************************************************************** + * Name: up_coherent_dcache + * + * Description: + * Ensure that the I and D caches are coherent within specified region + * by cleaning the D cache (i.e., flushing the D cache contents to memory + * and invalidating the I cache. This is typically used when code has been + * written to a memory region, and will be executed. + * + * Input Parameters: + * addr - virtual start address of region + * len - Size of the address region in bytes + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_ICACHE +void up_coherent_dcache(uintptr_t addr, size_t len); +#else +static inline void up_coherent_dcache(uintptr_t addr, size_t len) +{ +} +#endif + +#undef EXTERN +#ifdef __cplusplus +} +#endif + +#endif /* __ASSEMBLY__ */ + +#endif /* __INCLUDE_NUTTX_CACHE_H */ diff --git a/libs/libc/modlib/modlib_bind.c b/libs/libc/modlib/modlib_bind.c index 872bca29c4..cb7af8d96d 100644 --- a/libs/libc/modlib/modlib_bind.c +++ b/libs/libc/modlib/modlib_bind.c @@ -388,7 +388,6 @@ int modlib_bind(FAR struct module_s *modp, FAR struct mod_loadinfo_s *loadinfo) } } -#if defined(CONFIG_ARCH_HAVE_COHERENT_DCACHE) /* Ensure that the I and D caches are coherent before starting the newly * loaded module by cleaning the D cache (i.e., flushing the D cache * contents to memory and invalidating the I cache). @@ -397,7 +396,5 @@ int modlib_bind(FAR struct module_s *modp, FAR struct mod_loadinfo_s *loadinfo) up_coherent_dcache(loadinfo->textalloc, loadinfo->textsize); up_coherent_dcache(loadinfo->datastart, loadinfo->datasize); -#endif - return ret; }